Sigve Sebastian Farstad
mbed w/ spi bug fig
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mbed official
Revision 242:7074e42da0b2, committed 2014-06-27
- Comitter:
- mbed_official
- Date:
- Fri Jun 27 07:30:09 2014 +0100
- Parent:
- 241:ffe41b0c8126
- Child:
- 243:1b2bee05fe98
- Commit message:
- Synchronized with git revision 124ef5e3add9e74a3221347a3fbeea7c8b3cf353
Full URL: https://github.com/mbedmicro/mbed/commit/124ef5e3add9e74a3221347a3fbeea7c8b3cf353/
[DISCO_F407VG] HAL update.
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/hal_tick.c Fri Jun 27 07:30:09 2014 +0100
@@ -0,0 +1,124 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.c
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+
+void timer_irq_handler(void) {
+ // Channel 1 for mbed timeout
+ if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
+ __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
+ us_ticker_irq_handler();
+ }
+
+ // Channel 2 for HAL tick
+ if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
+ __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+ uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+ if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+ // Increment HAL variable
+ HAL_IncTick();
+ // Prepare next interrupt
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+ PreviousVal = val;
+#if 0 // For DEBUG only
+ HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
+#endif
+ }
+ }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+ // Enable timer clock
+ TIM_MST_RCC;
+
+ // Reset timer
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+
+ // Configure time base
+ TimMasterHandle.Instance = TIM_MST;
+ TimMasterHandle.Init.Period = 0xFFFFFFFF;
+ if ( SystemCoreClock == 16000000 ) {
+ TimMasterHandle.Init.Prescaler = (uint32_t)( SystemCoreClock / 1000000) - 1; // 1 µs tick
+ } else {
+ TimMasterHandle.Init.Prescaler = (uint32_t)( SystemCoreClock / 2 / 1000000) - 1; // 1 µs tick
+ }
+ TimMasterHandle.Init.ClockDivision = 0;
+ TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ TimMasterHandle.Init.RepetitionCounter = 0;
+ HAL_TIM_OC_Init(&TimMasterHandle);
+
+ NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_IRQ);
+
+ // Channel 1 for mbed timeout
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+ // Channel 2 for HAL tick
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+ PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+#if 0 // For DEBUG only
+ __GPIOB_CLK_ENABLE();
+ GPIO_InitTypeDef GPIO_InitStruct;
+ GPIO_InitStruct.Pin = GPIO_PIN_6;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/hal_tick.h Fri Jun 27 07:30:09 2014 +0100
@@ -0,0 +1,60 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.h
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM5
+#define TIM_MST_IRQ TIM5_IRQn
+#define TIM_MST_RCC __TIM5_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f407xx.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f407xx.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f407xx.h * @author MCD Application Team - * @version V2.0.0 - * @date 18-February-2014 + * @version V2.1.0 + * @date 19-June-2014 * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File. * * This file contains: @@ -948,6 +948,8 @@ #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */ +#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE @@ -4498,6 +4500,25 @@ #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) + /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface */ @@ -7895,6 +7916,19 @@ /****************************** WWDG Instances ********************************/ #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) +/******************************************************************************/ +/* For a painless codes migration between the STM32F4xx device product */ +/* lines, the aliases defined below are put in place to overcome the */ +/* differences in the interrupt handlers and IRQn definitions. */ +/* No need to update developed interrupt code when moving across */ +/* product lines within the same STM32F4 Family */ +/******************************************************************************/ + +/* Aliases for __IRQn */ +#define FMC_IRQn FSMC_IRQn + +/* Aliases for __IRQHandler */ +#define FMC_IRQHandler FSMC_IRQHandler /** * @}
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.0.0
- * @date 18-February-2014
+ * @version V2.1.0RC2
+ * @date 14-May-2014
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -70,7 +70,7 @@
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
- !defined (STM32F401xC) && !defined (STM32F401xE)
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
#define STM32F407xx /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
@@ -82,7 +82,8 @@
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
- /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE, STM32F401VE Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -98,12 +99,12 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.0.0
+ * @brief CMSIS Device version number V2.1.0RC2
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x02) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
@@ -137,6 +138,8 @@
#include "stm32f401xc.h"
#elif defined(STM32F401xE)
#include "stm32f401xe.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
@@ -196,6 +199,9 @@
* @}
*/
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,11 +2,11 @@
******************************************************************************
* @file stm32f4xx_hal.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief HAL module driver.
* This is the common part of the HAL initialization
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -15,7 +15,7 @@
The common HAL driver contains a set of generic and common APIs that can be
used by the PPP peripheral drivers and the user to start using the HAL.
[..]
- The HAL contains two APIs categories:
+ The HAL contains two APIs' categories:
(+) Common HAL APIs
(+) Services HAL APIs
@@ -65,12 +65,12 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
- * @brief STM32F4xx HAL Driver version number V1.0.0
+ * @brief STM32F4xx HAL Driver version number V1.1.0RC2
*/
#define __STM32F4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F4xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __STM32F4xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F4xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F4xx_HAL_VERSION_RC (0x02) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16)\
|(__STM32F4xx_HAL_VERSION_SUB2 << 8 )\
@@ -90,7 +90,7 @@
/* Alias word address of CMP_PD bit */
#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20)
#define CMP_PD_BitNumber ((uint8_t)0x00)
-#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
+#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
static __IO uint32_t uwTick;
@@ -114,7 +114,23 @@
configuration. It initializes the systick also when timeout is needed
and the backup domain when enabled.
(+) de-Initializes common part of the HAL
-
+ (+) Configure The time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) Systick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general purpose
+ timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ handled in milliseconds basis.
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically
+ at the beginning of the program after reset by HAL_Init() or at any time
+ when clock is configured, by HAL_RCC_ClockConfig().
+ (++) Source of time base is configured to generate interrupts at regular
+ time intervals. Care must be taken if HAL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher priority
+ (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __weak
+ to make override possible in case of other implementations in user file.
@endverbatim
* @{
*/
@@ -123,18 +139,17 @@
* @brief This function is used to initialize the HAL Library; it must be the first
* instruction to be executed in the main program (before to call any other
* HAL function), it performs the following:
- * - Configure the Flash prefetch, instruction and Data caches
- * - Configures the SysTick to generate an interrupt each 1 millisecond,
- * which is clocked by the HSI (at this stage, the clock is not yet
- * configured and thus the system is running from the internal HSI at 16 MHz)
- * - Set NVIC Group Priority to 4
- * - Calls the HAL_MspInit() callback function defined in user file
- * stm32f4xx_hal_msp.c to do the global low level hardware initialization
+ * Configure the Flash prefetch, instruction and Data caches.
+ * Configures the SysTick to generate an interrupt each 1 millisecond,
+ * which is clocked by the HSI (at this stage, the clock is not yet
+ * configured and thus the system is running from the internal HSI at 16 MHz).
+ * Set NVIC Group Priority to 4.
+ * Calls the HAL_MspInit() callback function defined in user file
+ * "stm32f4xx_hal_msp.c" to do the global low level hardware initialization
*
* @note SysTick is used as time base for the HAL_Delay() function, the application
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
- * @note
* @param None
* @retval HAL status
*/
@@ -153,11 +168,11 @@
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
- /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
- HAL_SYSTICK_Config(HSI_VALUE/ 1000);
-
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+ HAL_InitTick(TICK_INT_PRIORITY);
/* Init the low level hardware */
HAL_MspInit();
@@ -206,7 +221,7 @@
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
- */
+ */
}
/**
@@ -222,71 +237,139 @@
}
/**
+ * @brief This function configures the source of the time base.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
+ * @note In the default implementation, SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals.
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ * The the SysTick interrupt must have higher priority (numerically lower)
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ * The function is declared as __weak to be overwritten in case of other
+ * implementation in user file.
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ /*Configure the SysTick to have interrupt in 1ms time basis*/
+ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+
+ /*Configure the SysTick IRQ priority */
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
* @}
*/
/** @defgroup HAL_Group2 HAL Control functions
* @brief HAL Control functions
*
-@verbatim
+@verbatim
===============================================================================
##### HAL Control functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) provide a tick value in millisecond
- (+) provide a blocking delay in millisecond
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
- (+) Enable/Disable Debug module during Sleep mode
+ (+) Enable/Disable Debug module during SLEEP mode
(+) Enable/Disable Debug module during STOP mode
(+) Enable/Disable Debug module during STANDBY mode
-
@endverbatim
* @{
*/
/**
- * @brief This function is called from SysTick ISR each 1 millisecond, to increment
- * a global variable "uwTick" used as time base.
- * @param None
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ * in Systick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param None
* @retval None
*/
-void HAL_IncTick(void)
+__weak void HAL_IncTick(void)
{
uwTick++;
}
/**
- * @brief Povides a tick value in millisecond.
- * @param Non
+ * @brief Provides a tick value in millisecond.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param None
* @retval tick value
*/
-uint32_t HAL_GetTick(void)
+__weak uint32_t HAL_GetTick(void)
{
- return uwTick;
+ return uwTick;
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals where uwTick
+ * is incremented.
+ * @note ThiS function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay: specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(__IO uint32_t Delay)
+{
+ uint32_t tickstart = 0;
+ tickstart = HAL_GetTick();
+ while((HAL_GetTick() - tickstart) < Delay)
+ {
+ }
}
/**
- * @brief Provides a blocking delay in millisecond.
- * @note Care must be taken when using HAL_Delay(), this function provides accurate delay
- * (in milliseconds) based on variable incremented in SysTick ISR. This implies that
- * if HAL_Delay() is called from a peripheral ISR process, then the SysTick interrupt
- * must have higher priority (numerically lower) than the peripheral interrupt.
- * Otherwise the caller ISR process will be blocked. To change the SysTick interrupt
- * priority you have to use HAL_NVIC_SetPriority() function.
- * @param Delay : specifies the delay time length, in milliseconds.
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ * is called, the the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param None
* @retval None
*/
-void HAL_Delay(__IO uint32_t Delay)
+__weak void HAL_SuspendTick(void)
{
- uint32_t timingdelay;
-
- timingdelay = HAL_GetTick() + Delay;
- while(HAL_GetTick() < timingdelay)
- {
- }
+ /* Disable SysTick Interrupt */
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ * is called, the the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param None
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void)
+{
+ /* Enable SysTick Interrupt */
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
/**
@@ -320,7 +403,7 @@
}
/**
- * @brief Enable the Debug Module during SLEEP mode
+ * @brief Enable the Debug Module during SLEEP mode
* @param None
* @retval None
*/
@@ -330,7 +413,7 @@
}
/**
- * @brief Disable the Debug Module during SLEEP mode
+ * @brief Disable the Debug Module during SLEEP mode
* @param None
* @retval None
*/
@@ -340,7 +423,7 @@
}
/**
- * @brief Enable the Debug Module during STOP mode
+ * @brief Enable the Debug Module during STOP mode
* @param None
* @retval None
*/
@@ -350,7 +433,7 @@
}
/**
- * @brief Disable the Debug Module during STOP mode
+ * @brief Disable the Debug Module during STOP mode
* @param None
* @retval None
*/
@@ -360,7 +443,7 @@
}
/**
- * @brief Enable the Debug Module during STANDBY mode
+ * @brief Enable the Debug Module during STANDBY mode
* @param None
* @retval None
*/
@@ -370,7 +453,7 @@
}
/**
- * @brief Disable the Debug Module during STANDBY mode
+ * @brief Disable the Debug Module during STANDBY mode
* @param None
* @retval None
*/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** @@ -152,11 +152,14 @@ HAL_StatusTypeDef HAL_DeInit(void); void HAL_MspInit(void); void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); /* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(__IO uint32_t Delay); +void HAL_IncTick(void); +void HAL_Delay(__IO uint32_t Delay); uint32_t HAL_GetTick(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void);
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_adc.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_adc.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions
@@ -63,7 +63,7 @@
(#) Configure the ADC regular channels group features, use HAL_ADC_Init()
and HAL_ADC_ConfigChannel() functions.
- (#) Three mode of operations are available within this driver :
+ (#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -89,7 +89,7 @@
==============================
[..]
(+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
- of data to be transfered at each end of conversion
+ of data to be transferred at each end of conversion
(+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
(+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
@@ -410,7 +410,7 @@
*
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
- * last transfer and End of conversion selection).
+ *
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
@@ -780,7 +780,7 @@
* the configuration information for the specified ADC.
* @param pData: The destination Buffer address.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
@@ -846,7 +846,7 @@
* @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
{
@@ -1221,7 +1221,8 @@
/**
* @brief DMA transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
@@ -1245,7 +1246,8 @@
/**
* @brief DMA half transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
@@ -1257,7 +1259,8 @@
/**
* @brief DMA error callback
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_DMAError(DMA_HandleTypeDef *hdma)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_adc.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_adc.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention
@@ -139,9 +139,9 @@
*/
typedef struct
{
- uint32_t Channel; /*!< The ADC channel to configure
+ uint32_t Channel; /*!< The ADC channel to configure.
This parameter can be a value of @ref ADC_channels */
- uint32_t Rank; /*!< The rank in the regular group sequencer
+ uint32_t Rank; /*!< The rank in the regular group sequencer.
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel.
This parameter can be a value of @ref ADC_sampling_times */
@@ -154,14 +154,14 @@
typedef struct
{
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
- This parameter can be a value of @ref ADC_analog_watchdog_selection. */
+ This parameter can be a value of @ref ADC_analog_watchdog_selection */
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
This parameter must be a 12-bit value. */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
This parameter must be a 12-bit value. */
uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
This parameter has an effect only if watchdog mode is configured on single channel
- This parameter can be a value of @ref ADC_channels. */
+ This parameter can be a value of @ref ADC_channels */
uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
is interrupt mode or in polling mode.
This parameter can be set to ENABLE or DISABLE */
@@ -202,46 +202,6 @@
* @}
*/
-/** @defgroup ADC_delay_between_2_sampling_phases
- * @{
- */
-#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
-#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
-#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
-#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
-#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
-#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
-#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
-#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
-#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
-
-#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
- ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
-/**
- * @}
- */
-
/** @defgroup ADC_Resolution
* @{
*/
@@ -538,6 +498,13 @@
*/
/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset ADC handle state
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+
/**
* @brief Enable the ADC peripheral.
* @param __HANDLE__: ADC handle
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_adc_ex.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_adc_ex.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
@@ -24,22 +24,21 @@
(+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
(##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
- (++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
- (++) Configure and enable two DMA streams stream for managing data
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (+++) Configure and enable two DMA streams stream for managing data
transfer from peripheral to memory (output stream)
- (++) Associate the initilalized DMA handle to the CRYP DMA handle
+ (+++) Associate the initilalized DMA handle to the ADC DMA handle
using __HAL_LINKDMA()
- (++) Configure the priority and enable the NVIC for the transfer complete
+ (+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
- priority than the input stream.
-
+ priority than the input stream.
(#) Configure the ADC Prescaler, conversion resolution and data alignment
using the HAL_ADC_Init() function.
(#) Configure the ADC Injected channels group features, use HAL_ADC_Init()
and HAL_ADC_ConfigChannel() functions.
- (#) Three mode of operations are available within this driver :
+ (#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -66,7 +65,7 @@
==============================
[..]
(+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length
- of data to be transfered at each end of conversion
+ of data to be transferred at each end of conversion
(+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can
add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback
(+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can
@@ -79,7 +78,7 @@
(+) Select the Multi mode ADC regular channels features (dual or triple mode)
and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.
(+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length
- of data to be transfered at each end of conversion
+ of data to be transferred at each end of conversion
(+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.
@@ -409,10 +408,10 @@
* the configuration information for the specified ADC.
* @param InjectedRank: the ADC injected rank.
* This parameter can be one of the following values:
- * @arg ADC_InjectedChannel_1: Injected Channel1 selected
- * @arg ADC_InjectedChannel_2: Injected Channel2 selected
- * @arg ADC_InjectedChannel_3: Injected Channel3 selected
- * @arg ADC_InjectedChannel_4: Injected Channel4 selected
+ * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
+ * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
+ * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
+ * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
* @retval None
*/
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
@@ -463,7 +462,7 @@
* the configuration information for the specified ADC.
* @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
@@ -538,7 +537,7 @@
* @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
{
@@ -774,7 +773,8 @@
/**
* @brief DMA transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)
@@ -798,7 +798,8 @@
/**
* @brief DMA half transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)
@@ -810,7 +811,8 @@
/**
* @brief DMA error callback
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_adc_ex.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_adc_ex.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_adc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
@@ -61,8 +61,8 @@
*/
typedef struct
{
- uint32_t InjectedChannel; /*!< Configure the ADC injected channel
- This parameter can be a value of @ref ADC_channels. */
+ uint32_t InjectedChannel; /*!< Configure the ADC injected channel.
+ This parameter can be a value of @ref ADC_channels */
uint32_t InjectedRank; /*!< The rank in the injected group sequencer
This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
uint32_t InjectedSamplingTime; /*!< The sample time value to be set for the selected channel.
@@ -77,9 +77,9 @@
uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ExternalTrigInjecConvEdge; /*!< Select the external trigger edge and enable the trigger of an injected channels.
- This parameter can be a value of @ref ADC_External_trigger_Source_Injected. */
+ This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected */
uint32_t ExternalTrigInjecConv; /*!< Select the external event used to trigger the start of conversion of a injected channels.
- This parameter can be a value of @ref ADC_External_trigger_Source_Injected */
+ This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected */
}ADC_InjectionConfTypeDef;
/**
@@ -88,11 +88,11 @@
typedef struct
{
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
- This parameter can be a value of @ref ADC_Common_mode */
+ This parameter can be a value of @ref ADCEx_Common_mode */
uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
- This parameter can be a value of @ref ADC_Direct_memory_access_mode_for_multi_mode */
+ This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
- This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
+ This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases */
}ADC_MultiModeTypeDef;
/* Exported constants --------------------------------------------------------*/
@@ -152,6 +152,46 @@
* @}
*/
+ /** @defgroup ADCEx_delay_between_2_sampling_phases
+ * @{
+ */
+#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
+#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
+#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
+#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
+#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
+#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
+#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
+#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
+#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
+
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
+ ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
+/**
+ * @}
+ */
+
/** @defgroup ADCEx_External_trigger_edge_Injected
* @{
*/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_can.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_can.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_can.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
* + Initialization and de-initialization functions
@@ -771,10 +771,9 @@
* @brief Receives a correct CAN frame.
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
- * @param FIFONumber: FIFO Number value
- * @param Timeout: Specify Timeout value
+ * @param FIFONumber: FIFO Number value
+ * @param Timeout: Specify Timeout value
* @retval HAL status
- * @retval None
*/
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
{
@@ -881,7 +880,6 @@
* the configuration information for the specified CAN.
* @param FIFONumber: Specify the FIFO number
* @retval HAL status
- * @retval None
*/
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
@@ -1229,7 +1227,7 @@
##### Peripheral State and Error functions #####
==============================================================================
[..]
- This subsection provides functions allowing to
+ This subsection provides functions allowing to :
(+) Check the CAN state.
(+) Check CAN Errors detected during interrupt process
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_can.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_can.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_can.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
@@ -152,7 +152,7 @@
uint32_t FilterActivation; /*!< Enable or disable the filter.
This parameter can be set to ENABLE or DISABLE. */
- uint32_t BankNumber; /*!< Select the start slave bank filter
+ uint32_t BankNumber; /*!< Select the start slave bank filter.
This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
}CAN_FilterConfTypeDef;
@@ -579,6 +579,12 @@
/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset CAN handle state
+ * @param __HANDLE__: specifies the CAN Handle.
+ * @retval None
+ */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
/**
* @brief Enable the specified CAN interrupts.
* @param __HANDLE__: CAN handle
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_conf.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_conf.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_conf_template.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32f4xx_hal_conf.h. @@ -76,7 +76,7 @@ #define HAL_LTDC_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED -#define HAL_RNG_MODULE_ENABLED +//#define HAL_RNG_MODULE_ENABLED #define HAL_RTC_MODULE_ENABLED #define HAL_SAI_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED @@ -99,11 +99,11 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External crystal in Hz */ + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -116,12 +116,20 @@ #endif /* HSI_VALUE */ /** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +/** * @brief External clock source for I2S peripheral * This value is used by the I2S HAL module to compute the I2S clock source * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/ + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the external oscillator in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -131,9 +139,10 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 1 +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 #define INSTRUCTION_CACHE_ENABLE 1 #define DATA_CACHE_ENABLE 1
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cortex.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cortex.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@@ -16,40 +16,18 @@
==============================================================================
[..]
- *** How to configure Interrupts using Cortex HAL driver ***
+ *** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
- This section provide functions allowing to configure the NVIC interrupts (IRQ).
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M4 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
function according to the following table.
-
- The table below gives the allowed values of the pre-emption priority and subpriority according
- to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
- ==========================================================================================================================
- NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
- ==========================================================================================================================
- NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
- | | | 4 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
- | | | 3 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
- | | | 2 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
- | | | 1 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
- | | | 0 bits for subpriority
- ==========================================================================================================================
- (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
-
- (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+ (#) please refer to programing manual for details in how to configure priority.
-
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
@@ -59,12 +37,12 @@
(+@) Lowest hardware priority (IRQ number)
[..]
- *** How to configure Systick using Cortex HAL driver ***
+ *** How to configure Systick using CORTEX HAL driver ***
========================================================
[..]
- Setup SysTick Timer for 1 msec interrupts.
+ Setup SysTick Timer for time base.
- (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
+ (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
@@ -153,7 +131,7 @@
##### Initialization and de-initialization functions #####
==============================================================================
[..]
- This section provide the Cortex HAL driver functions allowing to configure Interrupts
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts
Systick functionalities
@endverbatim
@@ -191,8 +169,8 @@
/**
* @brief Sets the priority of an interrupt.
- * @param IRQn: External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @param PreemptPriority: The pre-emption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
@@ -219,8 +197,8 @@
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @retval None
*/
@@ -232,8 +210,8 @@
/**
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @retval None
*/
@@ -298,8 +276,8 @@
/**
* @brief Gets the priority of an interrupt.
- * @param IRQn: External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @param PriorityGroup: the priority grouping bits length.
* This parameter can be one of the following values:
@@ -341,8 +319,8 @@
/**
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt).
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
@@ -355,8 +333,8 @@
/**
* @brief Clears the pending bit of an external interrupt.
- * @param IRQn External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @retval None
*/
@@ -369,7 +347,7 @@
/**
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
* @param IRQn External interrupt number
- * This parameter can be an enumerator of @ref IRQn_Type enumeration
+ * This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cortex.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cortex.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cortex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_crc.c Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_crc.c Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_crc.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -105,7 +105,8 @@ /** * @brief Initializes the CRC according to the specified * parameters in the CRC_InitTypeDef and creates the associated handle. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) @@ -137,7 +138,8 @@ /** * @brief DeInitializes the CRC peripheral. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) @@ -169,7 +171,8 @@ /** * @brief Initializes the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @retval None */ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) @@ -181,7 +184,8 @@ /** * @brief DeInitializes the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @retval None */ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) @@ -215,7 +219,8 @@ /** * @brief Computes the 32-bit CRC of 32-bit data buffer using combination * of the previous CRC value and the new one. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @param pBuffer: pointer to the buffer containing the data to be computed * @param BufferLength: length of the buffer to be computed * @retval 32-bit CRC @@ -249,7 +254,8 @@ /** * @brief Computes the 32-bit CRC of 32-bit data buffer independently * of the previous CRC value. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @param pBuffer: Pointer to the buffer containing the data to be computed * @param BufferLength: Length of the buffer to be computed * @retval 32-bit CRC @@ -304,7 +310,8 @@ /** * @brief Returns the CRC state. - * @param hcrc: CRC handle + * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * the configuration information for CRC * @retval HAL state */ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_crc.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_crc.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_crc.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -85,6 +85,12 @@ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset CRC handle state + * @param __HANDLE__: CRC handle + * @retval None + */ +#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) + /** * @brief Resets CRC Data Register. * @param __HANDLE__: CRC handle
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cryp.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
@@ -29,18 +29,15 @@
(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
(##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
- (++) Enable the DMAx interface clock using
- (+++) __DMAx_CLK_ENABLE()
- (++) Configure and enable two DMA streams one for managing data transfer from
+ (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+ (+++) Configure and enable two DMA streams one for managing data transfer from
memory to peripheral (input stream) and another stream for managing data
transfer from peripheral to memory (output stream)
- (++) Associate the initilalized DMA handle to the CRYP DMA handle
+ (+++) Associate the initilalized DMA handle to the CRYP DMA handle
using __HAL_LINKDMA()
- (++) Configure the priority and enable the NVIC for the transfer complete
+ (+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA Streams. The output stream should have higher
- priority than the input stream.
- (+++) HAL_NVIC_SetPriority()
- (+++) HAL_NVIC_EnableIRQ()
+ priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
(#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
(##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
@@ -51,13 +48,13 @@
(#)Three processing (encryption/decryption) functions are available:
(##) Polling mode: encryption and decryption APIs are blocking functions
- i.e. they process the data and wait till the processing is finished
+ i.e. they process the data and wait till the processing is finished,
e.g. HAL_CRYP_AESCBC_Encrypt()
(##) Interrupt mode: encryption and decryption APIs are not blocking functions
- i.e. they process the data under interrupt
+ i.e. they process the data under interrupt,
e.g. HAL_CRYP_AESCBC_Encrypt_IT()
(##) DMA mode: encryption and decryption APIs are not blocking functions
- i.e. the data transfer is ensured by DMA
+ i.e. the data transfer is ensured by DMA,
e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
(#)When the processing function is called at first time after HAL_CRYP_Init()
@@ -161,7 +158,8 @@
/**
* @brief Initializes the CRYP according to the specified
* parameters in the CRYP_InitTypeDef and creates the associated handle.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
@@ -204,7 +202,8 @@
/**
* @brief DeInitializes the CRYP peripheral.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
@@ -243,7 +242,8 @@
/**
* @brief Initializes the CRYP MSP.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
@@ -255,7 +255,8 @@
/**
* @brief DeInitializes CRYP MSP.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
@@ -291,7 +292,8 @@
/**
* @brief Initializes the CRYP peripheral in AES ECB encryption mode
* then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pCypherData: Pointer to the cyphertext buffer
@@ -344,7 +346,8 @@
/**
* @brief Initializes the CRYP peripheral in AES CBC encryption mode
* then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pCypherData: Pointer to the cyphertext buffer
@@ -400,7 +403,8 @@
/**
* @brief Initializes the CRYP peripheral in AES CTR encryption mode
* then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pCypherData: Pointer to the cyphertext buffer
@@ -458,7 +462,8 @@
/**
* @brief Initializes the CRYP peripheral in AES ECB decryption mode
* then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pPlainData: Pointer to the plaintext buffer
@@ -545,7 +550,8 @@
/**
* @brief Initializes the CRYP peripheral in AES ECB decryption mode
* then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pPlainData: Pointer to the plaintext buffer
@@ -633,7 +639,8 @@
/**
* @brief Initializes the CRYP peripheral in AES CTR decryption mode
* then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pPlainData: Pointer to the plaintext buffer
@@ -688,7 +695,8 @@
/**
* @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
* @param pCypherData: Pointer to the cyphertext buffer
@@ -788,7 +796,8 @@
/**
* @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
* @param pCypherData: Pointer to the cyphertext buffer
@@ -890,7 +899,8 @@
/**
* @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
* @param pCypherData: Pointer to the cyphertext buffer
@@ -993,7 +1003,8 @@
/**
* @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pPlainData: Pointer to the plaintext buffer
@@ -1121,7 +1132,8 @@
/**
* @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pPlainData: Pointer to the plaintext buffer
@@ -1257,7 +1269,8 @@
/**
* @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pPlainData: Pointer to the plaintext buffer
@@ -1361,7 +1374,8 @@
/**
* @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
* @param pCypherData: Pointer to the cyphertext buffer
@@ -1415,7 +1429,8 @@
/**
* @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pCypherData: Pointer to the cyphertext buffer
@@ -1472,7 +1487,8 @@
/**
* @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16.
* @param pCypherData: Pointer to the cyphertext buffer
@@ -1530,7 +1546,8 @@
/**
* @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
* @param pPlainData: Pointer to the plaintext buffer
@@ -1613,7 +1630,8 @@
/**
* @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes
* @param pPlainData: Pointer to the plaintext buffer
@@ -1699,7 +1717,8 @@
/**
* @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 16
* @param pPlainData: Pointer to the plaintext buffer
@@ -1768,10 +1787,10 @@
==============================================================================
[..] This section provides functions allowing to:
(+) Encrypt plaintext using DES using ECB or CBC chaining modes
- (+) Decrypt cyphertext using using ECB or CBC chaining modes
+ (+) Decrypt cyphertext using ECB or CBC chaining modes
[..] Three processing functions are available:
- (+) polling mode
- (+) interrupt mode
+ (+) Polling mode
+ (+) Interrupt mode
(+) DMA mode
@endverbatim
@@ -1780,7 +1799,8 @@
/**
* @brief Initializes the CRYP peripheral in DES ECB encryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -1819,7 +1839,8 @@
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -1858,7 +1879,8 @@
/**
* @brief Initializes the CRYP peripheral in DES CBC encryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -1897,7 +1919,8 @@
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -1936,7 +1959,8 @@
/**
* @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2020,7 +2044,8 @@
/**
* @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2105,7 +2130,8 @@
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2189,7 +2215,8 @@
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2273,7 +2300,8 @@
/**
* @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2315,7 +2343,8 @@
/**
* @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2357,7 +2386,8 @@
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2399,7 +2429,8 @@
/**
* @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2451,11 +2482,11 @@
##### TDES processing functions #####
==============================================================================
[..] This section provides functions allowing to:
- (+) Encrypt plaintext using TDES using ECB or CBC chaining modes
- (+) Decrypt cyphertext using TDES using ECB or CBC chaining modes
+ (+) Encrypt plaintext using TDES based on ECB or CBC chaining modes
+ (+) Decrypt cyphertext using TDES based on ECB or CBC chaining modes
[..] Three processing functions are available:
- (+) polling mode
- (+) interrupt mode
+ (+) Polling mode
+ (+) Interrupt mode
(+) DMA mode
@endverbatim
@@ -2465,7 +2496,8 @@
/**
* @brief Initializes the CRYP peripheral in TDES ECB encryption mode
* then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2505,7 +2537,8 @@
/**
* @brief Initializes the CRYP peripheral in TDES ECB decryption mode
* then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2545,7 +2578,8 @@
/**
* @brief Initializes the CRYP peripheral in TDES CBC encryption mode
* then encrypt pPlainData. The cypher data are available in pCypherData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2585,7 +2619,8 @@
/**
* @brief Initializes the CRYP peripheral in TDES CBC decryption mode
* then decrypted pCypherData. The cypher data are available in pPlainData
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pPlainData: Pointer to the plaintext buffer
@@ -2624,7 +2659,8 @@
/**
* @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2708,7 +2744,8 @@
/**
* @brief Initializes the CRYP peripheral in TDES CBC encryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2791,7 +2828,8 @@
/**
* @brief Initializes the CRYP peripheral in TDES ECB decryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2874,7 +2912,8 @@
/**
* @brief Initializes the CRYP peripheral in TDES CBC decryption mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pPlainData: Pointer to the plaintext buffer
@@ -2957,7 +2996,8 @@
/**
* @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -2999,7 +3039,8 @@
/**
* @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -3041,7 +3082,8 @@
/**
* @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pPlainData: Pointer to the plaintext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pCypherData: Pointer to the cyphertext buffer
@@ -3083,7 +3125,8 @@
/**
* @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param pCypherData: Pointer to the cyphertext buffer
* @param Size: Length of the plaintext buffer, must be a multiple of 8
* @param pPlainData: Pointer to the plaintext buffer
@@ -3145,7 +3188,8 @@
/**
* @brief Input FIFO transfer completed callbacks.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
@@ -3157,7 +3201,8 @@
/**
* @brief Output FIFO transfer completed callbacks.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
@@ -3169,7 +3214,8 @@
/**
* @brief CRYP error callbacks.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
@@ -3198,7 +3244,8 @@
/**
* @brief This function handles CRYP interrupt request.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval None
*/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
@@ -3286,7 +3333,8 @@
/**
* @brief Returns the CRYP state.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @retval HAL state
*/
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
@@ -3352,7 +3400,8 @@
/**
* @brief Writes the Key in Key registers.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param Key: Pointer to Key buffer
* @param KeySize: Size of Key
* @retval None
@@ -3410,7 +3459,8 @@
/**
* @brief Writes the InitVector/InitCounter in IV registers.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param InitVector: Pointer to InitVector/InitCounter buffer
* @param IVSize: Size of the InitVector/InitCounter
* @retval None
@@ -3448,7 +3498,8 @@
/**
* @brief Process Data: Writes Input data in polling mode and read the output data
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param Input: Pointer to the Input buffer
* @param Ilength: Length of the Input buffer, must be a multiple of 16.
* @param Output: Pointer to the returned buffer
@@ -3510,7 +3561,8 @@
/**
* @brief Process Data: Write Input data in polling mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param Input: Pointer to the Input buffer
* @param Ilength: Length of the Input buffer, must be a multiple of 8
* @param Output: Pointer to the returned buffer
@@ -3565,7 +3617,8 @@
/**
* @brief Set the DMA configuration and start the DMA transfer
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param inputaddr: address of the Input buffer
* @param Size: Size of the Input buffer, must be a multiple of 16.
* @param outputaddr: address of the Output buffer
@@ -3602,7 +3655,8 @@
/**
* @brief Sets the CRYP peripheral in DES ECB mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param Direction: Encryption or decryption
* @retval None
*/
@@ -3628,7 +3682,8 @@
/**
* @brief Sets the CRYP peripheral in DES CBC mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param Direction: Encryption or decryption
* @retval None
*/
@@ -3657,7 +3712,8 @@
/**
* @brief Sets the CRYP peripheral in TDES ECB mode.
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param Direction: Encryption or decryption
* @retval None
*/
@@ -3682,7 +3738,8 @@
/**
* @brief Sets the CRYP peripheral in TDES CBC mode
- * @param hcryp: CRYP handle
+ * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
* @param Direction: Encryption or decryption
* @retval None
*/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_cryp.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
@@ -53,59 +53,57 @@
/** @addtogroup CRYP
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/**
- * @brief CRYP Configuration Structure definition
+ * @brief CRYP Configuration Structure definition
*/
typedef struct
-{
+{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref CRYP_Data_Type */
-
+
uint32_t KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length.
This parameter can be a value of @ref CRYP_Key_Size */
-
+
uint8_t* pKey; /*!< The key used for encryption/decryption */
-
+
uint8_t* pInitVect; /*!< The initialization vector used also as initialization
counter in CTR mode */
-
+
uint8_t IVSize; /*!< The size of initialization vector.
This parameter (called nonce size in CCM) is used only
in AES-128/192/256 encryption/decryption CCM mode */
-
+
uint8_t TagSize; /*!< The size of returned authentication TAG.
This parameter is used only in AES-128/192/256
encryption/decryption CCM mode */
-
+
uint8_t* Header; /*!< The header used in GCM and CCM modes */
-
+
uint16_t HeaderSize; /*!< The size of header buffer in bytes */
-
+
uint8_t* pScratch; /*!< Scratch buffer used to append the header. It's size must be equal to header size + 21 bytes.
This parameter is used only in AES-128/192/256 encryption/decryption CCM mode */
-
}CRYP_InitTypeDef;
/**
- * @brief HAL CRYP State structures definition
- */
+ * @brief HAL CRYP State structures definition
+ */
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */
HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */
- HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */
-
+ HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */
}HAL_CRYP_STATETypeDef;
/**
- * @brief HAL CRYP phase structures definition
- */
+ * @brief HAL CRYP phase structures definition
+ */
typedef enum
{
HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
@@ -115,32 +113,31 @@
}HAL_PhaseTypeDef;
/**
- * @brief CRYP handle Structure definition
+ * @brief CRYP handle Structure definition
*/
typedef struct
-{
+{
CRYP_InitTypeDef Init; /*!< CRYP required parameters */
-
+
uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
+
uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
+
__IO uint16_t CrypInCount; /*!< Counter of inputed data */
-
+
__IO uint16_t CrypOutCount; /*!< Counter of outputed data */
-
+
HAL_StatusTypeDef Status; /*!< CRYP peripheral status */
-
+
HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */
-
+
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
-
+
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
-
+
HAL_LockTypeDef Lock; /*!< CRYP locking object */
-
+
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
-
}CRYP_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
@@ -151,7 +148,7 @@
/** @defgroup CRYP_Key_Size
* @{
- */
+ */
#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000)
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
@@ -210,7 +207,6 @@
* @}
*/
-
/** @defgroup CRYP_Flags
* @{
*/
@@ -229,7 +225,7 @@
interrupt status */
/**
* @}
- */
+ */
/**
* @}
@@ -237,6 +233,12 @@
/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset CRYP handle state
+ * @param __HANDLE__: specifies the CRYP handle.
+ * @retval None
+ */
+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
+
/**
* @brief Enable/Disable the CRYP peripheral.
* @param None
@@ -253,13 +255,12 @@
#define __HAL_CRYP_FIFO_FLUSH() (CRYP->CR |= CRYP_CR_FFLUSH)
/**
- * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,...
+ * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,
* @param MODE: The algorithm mode.
* @retval None
*/
#define __HAL_CRYP_SET_MODE(MODE) CRYP->CR |= (uint32_t)(MODE)
-
/** @brief Check whether the specified CRYP flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
@@ -304,7 +305,7 @@
#include "stm32f4xx_hal_cryp_ex.h"
/* Exported functions --------------------------------------------------------*/
-/* Initialization/de-initialization functions **********************************/
+/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
@@ -368,10 +369,10 @@
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-/* Processing functions ********************************************************/
+/* Processing functions ******************************************************/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
-/* Peripheral State functions **************************************************/
+/* Peripheral State functions ************************************************/
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
/* MSP functions *************************************************************/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp_ex.c Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp_ex.c Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Extended CRYP HAL module driver * This file provides firmware functions to manage the following * functionalities of CRYP extension peripheral: @@ -153,7 +153,8 @@ /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode then * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -407,7 +408,8 @@ /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode then * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -504,7 +506,8 @@ /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode then * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the cyphertext buffer, must be a multiple of 16 * @param pPlainData: Pointer to the plaintext buffer @@ -596,7 +599,8 @@ /** * @brief Computes the authentication TAG. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Size: Total length of the plain/cyphertext buffer * @param AuthTag: Pointer to the authentication buffer * @param Timeout: Timeout duration @@ -704,7 +708,8 @@ /** * @brief Computes the authentication TAG for AES CCM mode. * @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt() - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param AuthTag: Pointer to the authentication buffer * @param Timeout: Timeout duration * @retval HAL status @@ -795,7 +800,8 @@ /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode then * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -1046,7 +1052,8 @@ /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -1196,7 +1203,8 @@ /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -1494,7 +1502,8 @@ /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the cyphertext buffer, must be a multiple of 16 * @param pPlainData: Pointer to the plaintext buffer @@ -1641,7 +1650,8 @@ /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pPlainData: Pointer to the plaintext buffer @@ -1930,7 +1940,8 @@ /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -2026,7 +2037,8 @@ /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pPlainData: Pointer to the plaintext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pCypherData: Pointer to the cyphertext buffer @@ -2279,7 +2291,8 @@ /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer. * @param Size: Length of the cyphertext buffer, must be a multiple of 16 * @param pPlainData: Pointer to the plaintext buffer @@ -2368,7 +2381,8 @@ /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param pCypherData: Pointer to the cyphertext buffer * @param Size: Length of the plaintext buffer, must be a multiple of 16 * @param pPlainData: Pointer to the plaintext buffer @@ -2621,7 +2635,8 @@ /** * @brief This function handles CRYP interrupt request. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @retval None */ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp) @@ -2707,7 +2722,8 @@ /** * @brief Writes the Key in Key registers. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Key: Pointer to Key buffer * @param KeySize: Size of Key * @retval None @@ -2765,7 +2781,8 @@ /** * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param InitVector: Pointer to InitVector/InitCounter buffer * @param IVSize: Size of the InitVector/InitCounter * @retval None @@ -2803,7 +2820,8 @@ /** * @brief Process Data: Writes Input data in polling mode and read the Output data. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Input: Pointer to the Input buffer. * @param Ilength: Length of the Input buffer, must be a multiple of 16 * @param Output: Pointer to the returned buffer @@ -2865,7 +2883,8 @@ /** * @brief Sets the header phase - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param Input: Pointer to the Input buffer. * @param Ilength: Length of the Input buffer, must be a multiple of 16 * @param Timeout: Timeout value @@ -2947,7 +2966,8 @@ /** * @brief Sets the DMA configuration and start the DMA transfert. - * @param hcryp: CRYP handle + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module * @param inputaddr: Address of the Input buffer * @param Size: Size of the Input buffer, must be a multiple of 16 * @param outputaddr: Address of the Output buffer
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp_ex.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_cryp_ex.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of CRYP HAL Extension module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dac.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dac.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dac.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -116,7 +116,7 @@
==============================
[..]
(+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
- of data to be transfered at each end of conversion
+ of data to be transferred at each end of conversion
(+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
function is executed and user can add his own code by customization of function pointer
HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
@@ -430,9 +430,9 @@
* @param Length: The length of data to be transferred from memory to DAC peripheral
* @param Alignment: Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
@@ -448,27 +448,18 @@
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
-
- /* Set the DMA transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
- /* Set the DMA half transfer complete callback for channel1 */
- hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
- /* Set the DMA error callback for channel1 */
- hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
- /* Set the DMA transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-
- /* Set the DMA half transfer complete callback for channel2 */
- hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-
- /* Set the DMA error callback for channel2 */
- hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
-
+
if(Channel == DAC_CHANNEL_1)
{
+ /* Set the DMA transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+ /* Set the DMA half transfer complete callback for channel1 */
+ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+ /* Set the DMA error callback for channel1 */
+ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
/* Enable the selected DAC channel1 DMA request */
hdac->Instance->CR |= DAC_CR_DMAEN1;
@@ -493,9 +484,18 @@
}
else
{
+ /* Set the DMA transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+ /* Set the DMA half transfer complete callback for channel2 */
+ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+
+ /* Set the DMA error callback for channel2 */
+ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
/* Enable the selected DAC channel2 DMA request */
hdac->Instance->CR |= DAC_CR_DMAEN2;
-
+
/* Case of use of channel 2 */
switch(Alignment)
{
@@ -556,20 +556,42 @@
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Disable the selected DAC channel DMA request */
- hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
+ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
/* Disable the Peripharal */
__HAL_DAC_DISABLE(hdac, Channel);
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
-
+ /* Disable the DMA Channel */
+ /* Channel1 is used */
+ if(Channel == DAC_CHANNEL_1)
+ {
+ status = HAL_DMA_Abort(hdac->DMA_Handle1);
+ }
+ else /* Channel2 is used for */
+ {
+ status = HAL_DMA_Abort(hdac->DMA_Handle2);
+ }
+
+ /* Check if DMA Channel effectively disabled */
+ if(status == HAL_ERROR)
+ {
+ /* Update ADC state machine to error */
+ hdac->State = HAL_DAC_STATE_ERROR;
+ }
+ else
+ {
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
+ }
+
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -732,7 +754,6 @@
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
- assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
@@ -776,9 +797,9 @@
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Alignment: Specifies the data alignment.
* This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+ * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+ * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data: Data to be loaded in the selected data holding register.
* @retval HAL status
*/
@@ -858,7 +879,8 @@
/**
* @brief DMA conversion complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
@@ -872,7 +894,8 @@
/**
* @brief DMA half transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
@@ -884,7 +907,8 @@
/**
* @brief DMA error callback
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dac.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dac.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dac.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
@@ -59,8 +59,8 @@
/* Exported types ------------------------------------------------------------*/
/**
- * @brief HAL State structures definition
- */
+ * @brief HAL State structures definition
+ */
typedef enum
{
HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
@@ -68,39 +68,37 @@
HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
-
}HAL_DAC_StateTypeDef;
/**
- * @brief DAC handle Structure definition
- */
+ * @brief DAC handle Structure definition
+ */
typedef struct
{
DAC_TypeDef *Instance; /*!< Register base address */
-
+
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
HAL_LockTypeDef Lock; /*!< DAC locking object */
-
+
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
-
- DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
-
+
+ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
+
__IO uint32_t ErrorCode; /*!< DAC Error code */
-
+
}DAC_HandleTypeDef;
/**
- * @brief DAC Configuration regular Channel structure definition
- */
+ * @brief DAC Configuration regular Channel structure definition
+ */
typedef struct
{
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
-
+
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
-
}DAC_ChannelConfTypeDef;
/* Exported constants --------------------------------------------------------*/
@@ -111,12 +109,12 @@
#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */
-#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
+#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
/**
* @}
*/
-
-/** @defgroup DAC_trigger_selection
+
+/** @defgroup DAC_trigger_selection
* @{
*/
@@ -186,7 +184,7 @@
/** @defgroup DAC_data
* @{
*/
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
@@ -195,7 +193,7 @@
* @{
*/
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || \
((FLAG) == DAC_FLAG_DMAUDR2))
@@ -207,67 +205,104 @@
* @{
*/
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
+#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || \
((IT) == DAC_IT_DMAUDR2))
-
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-/* Enable the DAC peripheral */
+
+/** @brief Reset DAC handle state
+ * @param __HANDLE__: specifies the DAC handle.
+ * @retval None
+ */
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+
+/** @brief Enable the DAC channel
+ * @param __HANDLE__: specifies the DAC handle.
+ * @param __DAC_Channel__: specifies the DAC channel
+ * @retval None
+ */
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
-/* Disable the DAC peripheral */
+/** @brief Disable the DAC channel
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __DAC_Channel__: specifies the DAC channel.
+ * @retval None
+ */
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
-
-/* Set DHR12R1 alignment */
+
+/** @brief Set DHR12R1 alignment
+ * @param __ALIGNEMENT__: specifies the DAC alignement
+ * @retval None
+ */
#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
-/* Set DHR12R2 alignment */
+/** @brief Set DHR12R2 alignment
+ * @param __ALIGNEMENT__: specifies the DAC alignement
+ * @retval None
+ */
#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
-/* Set DHR12RD alignment */
+/** @brief Set DHR12RD alignment
+ * @param __ALIGNEMENT__: specifies the DAC alignement
+ * @retval None
+ */
#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
-/* Enable the DAC interrupt */
+/** @brief Enable the DAC interrupt
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
+ * @retval None
+ */
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-/* Disable the DAC interrupt */
+/** @brief Disable the DAC interrupt
+ * @param __HANDLE__: specifies the DAC handle
+ * @param __INTERRUPT__: specifies the DAC interrupt.
+ * @retval None
+ */
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-/* Get the selected DAC's flag status */
+/** @brief Get the selected DAC's flag status.
+ * @param __HANDLE__: specifies the DAC handle.
+ * @retval None
+ */
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-/* Clear the DAC's flag */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) |= (__FLAG__))
+/** @brief Clear the DAC's flag.
+ * @param __HANDLE__: specifies the DAC handle.
+ * @retval None
+ */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) |= (__FLAG__))
/* Include DAC HAL Extension module */
-#include "stm32f4xx_hal_dac_ex.h"
+#include "stm32f4xx_hal_dac_ex.h"
-/* Exported functions --------------------------------------------------------*/
-/* Initialization/de-initialization functions ***********************************/
+/* Exported functions --------------------------------------------------------*/
+/* Initialization/de-initialization functions *********************************/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
-/* I/O operation functions ******************************************************/
+/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
-/* Peripheral Control functions *************************************************/
+/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-/* Peripheral State functions ***************************************************/
+/* Peripheral State functions *************************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dac_ex.c Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dac_ex.c Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: @@ -123,8 +123,7 @@ * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected + * DAC_CHANNEL_1 / DAC_CHANNEL_2 * @param Amplitude: Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 @@ -172,8 +171,7 @@ * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected + * DAC_CHANNEL_1 / DAC_CHANNEL_2 * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation @@ -221,9 +219,9 @@ * the configuration information for the specified DAC. * @param Alignment: Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected + * DAC_ALIGN_8B_R: 8bit right data alignment selected + * DAC_ALIGN_12B_L: 12bit left data alignment selected + * DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both @@ -317,7 +315,8 @@ /** * @brief DMA conversion complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) @@ -331,7 +330,8 @@ /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) @@ -343,7 +343,8 @@ /** * @brief DMA error callback - * @param hdma: pointer to DMA handle. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dac_ex.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dac_ex.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dac.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dcmi.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dcmi.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dcmi.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
@@ -39,9 +39,9 @@
window from the received image using HAL_DCMI_ConfigCrop()
and HAL_DCMI_EnableCROP() functions
- (#) The capture can be stopped using the following HAL_DCMI_Stop() function.
+ (#) The capture can be stopped using HAL_DCMI_Stop() function.
- (#) To control DCMI state you can use the following function : HAL_DCMI_GetState()
+ (#) To control DCMI state you can use the function HAL_DCMI_GetState().
*** DCMI HAL driver macros list ***
=============================================
@@ -217,7 +217,7 @@
* values.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
@@ -290,7 +290,7 @@
* @param DCMI_Mode: DCMI capture mode snapshot or continuous grab.
* @param pData: The destination memory Buffer address (LCD Frame buffer).
* @param Length: The length of capture to be transferred.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
{
@@ -363,6 +363,7 @@
* @brief Disable DCMI DMA request and Disable DCMI capture
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
{
@@ -417,7 +418,7 @@
* @brief Handles DCMI interrupt request.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for the DCMI.
- * @retval HAL status
+ * @retval None
*/
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
{
@@ -593,7 +594,7 @@
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the CROP feature.
- (+) ENABLE/DISABLE the CROP feature.
+ (+) Enable/Disable the CROP feature.
@endverbatim
* @{
@@ -640,7 +641,7 @@
* @brief Disable the Crop feature.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
{
@@ -666,7 +667,7 @@
* @brief Enable the Crop feature.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
{
@@ -736,7 +737,8 @@
/**
* @brief DMA conversion complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma)
@@ -789,7 +791,8 @@
/**
* @brief DMA error callback
- * @param hdma: pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dcmi.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dcmi.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dcmi.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention
@@ -59,17 +59,16 @@
/* Exported types ------------------------------------------------------------*/
/**
- * @brief DCMI Error source
- */
+ * @brief DCMI Error source
+ */
typedef enum
{
DCMI_ERROR_SYNC = 1, /*!< Synchronisation error */
DCMI_OVERRUN = 2, /*!< DCMI Overrun */
-
-}DCMI_ErrorTypeDef;
+}DCMI_ErrorTypeDef;
/**
- * @brief DCMI Embedded Synchronisation CODE Init structure definition
+ * @brief DCMI Embedded Synchronisation CODE Init structure definition
*/
typedef struct
{
@@ -77,11 +76,10 @@
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
-
}DCMI_CodesInitTypeDef;
/**
- * @brief DCMI Init structure definition
+ * @brief DCMI Init structure definition
*/
typedef struct
{
@@ -102,17 +100,16 @@
uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
This parameter can be a value of @ref DCMI_Extended_Data_Mode */
-
+
DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */
-
+
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
- This parameter can be a value of @ref DCMI_MODE_JPEG */
-
+ This parameter can be a value of @ref DCMI_MODE_JPEG */
+
}DCMI_InitTypeDef;
-
/**
- * @brief HAL DCMI State structures definition
+ * @brief HAL DCMI State structures definition
*/
typedef enum
{
@@ -121,35 +118,34 @@
HAL_DCMI_STATE_BUSY = 0x02, /*!< DCMI internal processing is ongoing */
HAL_DCMI_STATE_TIMEOUT = 0x03, /*!< DCMI timeout state */
HAL_DCMI_STATE_ERROR = 0x04 /*!< DCMI error state */
-
}HAL_DCMI_StateTypeDef;
/**
- * @brief DCMI handle Structure definition
- */
+ * @brief DCMI handle Structure definition
+ */
typedef struct
-{
+{
DCMI_TypeDef *Instance; /*!< DCMI Register base address */
-
+
DCMI_InitTypeDef Init; /*!< DCMI parameters */
-
+
HAL_LockTypeDef Lock; /*!< DCMI locking object */
-
+
__IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
-
+
__IO uint32_t XferCount; /*!< DMA transfer counter */
-
+
__IO uint32_t XferSize; /*!< DMA transfer size */
-
- uint32_t XferTransferNumber; /*!< DMA transfer number */
+
+ uint32_t XferTransferNumber; /*!< DMA transfer number */
- uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
-
+ uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
+
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
- __IO uint32_t ErrorCode; /*!< DCMI Error code */
-
-}DCMI_HandleTypeDef;
+ __IO uint32_t ErrorCode; /*!< DCMI Error code */
+
+}DCMI_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
@@ -162,13 +158,13 @@
*/
#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DCMI_ERROR_OVF ((uint32_t)0x00000001) /*!< Overflow error */
-#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */
+#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */
#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
/**
* @}
- */
+ */
-/** @defgroup DCMI_Capture_Mode
+/** @defgroup DCMI_Capture_Mode
* @{
*/
#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously
@@ -180,8 +176,7 @@
((MODE) == DCMI_MODE_SNAPSHOT))
/**
* @}
- */
-
+ */
/** @defgroup DCMI_Synchronization_Mode
* @{
@@ -190,17 +185,16 @@
is synchronized with the HSYNC/VSYNC signals */
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
synchronization codes embedded in the data flow */
-
+
#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
((MODE) == DCMI_SYNCHRO_EMBEDDED))
/**
* @}
- */
-
+ */
-/** @defgroup DCMI_PIXCK_Polarity
+/** @defgroup DCMI_PIXCK_Polarity
* @{
- */
+ */
#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
@@ -208,12 +202,11 @@
((POLARITY) == DCMI_PCKPOLARITY_RISING))
/**
* @}
- */
-
+ */
-/** @defgroup DCMI_VSYNC_Polarity
+/** @defgroup DCMI_VSYNC_Polarity
* @{
- */
+ */
#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
@@ -221,10 +214,9 @@
((POLARITY) == DCMI_VSPOLARITY_HIGH))
/**
* @}
- */
+ */
-
-/** @defgroup DCMI_HSYNC_Polarity
+/** @defgroup DCMI_HSYNC_Polarity
* @{
*/
#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */
@@ -234,11 +226,11 @@
((POLARITY) == DCMI_HSPOLARITY_HIGH))
/**
* @}
- */
+ */
/** @defgroup DCMI_MODE_JPEG
* @{
- */
+ */
#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< Mode JPEG Disabled */
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
@@ -246,11 +238,11 @@
((JPEG_MODE) == DCMI_JPEG_ENABLE))
/**
* @}
- */
+ */
/** @defgroup DCMI_Capture_Rate
* @{
- */
+ */
#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
@@ -260,12 +252,11 @@
((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
/**
* @}
- */
-
+ */
/** @defgroup DCMI_Extended_Data_Mode
* @{
- */
+ */
#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
@@ -277,11 +268,11 @@
((DATA) == DCMI_EXTEND_DATA_14B))
/**
* @}
- */
+ */
/** @defgroup DCMI_Window_Coordinate
* @{
- */
+ */
#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */
#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
@@ -297,11 +288,11 @@
#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
/**
* @}
- */
+ */
-/** @defgroup DCMI_interrupt_sources
+/** @defgroup DCMI_interrupt_sources
* @{
- */
+ */
#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)
#define DCMI_IT_OVF ((uint32_t)DCMI_IER_OVF_IE)
#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)
@@ -317,13 +308,14 @@
((IT) == DCMI_IT_LINE))
/**
* @}
- */
+ */
-/** @defgroup DCMI_Flags
+/** @defgroup DCMI_Flags
* @{
- */
+ */
+
/**
- * @brief DCMI SR register
+ * @brief DCMI SR register
*/
#define DCMI_FLAG_HSYNC ((uint32_t)0x2001)
#define DCMI_FLAG_VSYNC ((uint32_t)0x2002)
@@ -368,6 +360,13 @@
*/
/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DCMI handle state
+ * @param __HANDLE__: specifies the DCMI handle.
+ * @retval None
+ */
+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
+
/**
* @brief Enable the DCMI.
* @param __HANDLE__: DCMI handle
@@ -455,15 +454,15 @@
*/
#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
-/* Exported functions --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions *******************************/
+/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
-/* IO operation functions *******************************************************/
+/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
@@ -472,12 +471,12 @@
void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
-/* Peripheral Control functions *************************************************/
+/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);
-/* Peripheral State functions ***************************************************/
+/* Peripheral State functions *************************************************/
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_def.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_def.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_def.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
@@ -79,10 +79,10 @@
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
- (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
- (__DMA_HANDLE_).Parent = (__HANDLE__); \
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
#if (USE_RTOS == 1)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -47,7 +47,7 @@
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
add his own function by customization of function pointer XferCpltCallback and
XferErrorCallback (i.e a member of DMA handle structure).
-
+ [..]
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
detection.
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
@@ -54,36 +54,36 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/**
- * @brief DMA Configuration Structure definition
+ * @brief DMA Configuration Structure definition
*/
typedef struct
{
uint32_t Channel; /*!< Specifies the channel used for the specified stream.
This parameter can be a value of @ref DMA_Channel_selection */
-
+
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
- This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
+
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_Peripheral_data_size */
+ This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */
-
+
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Stream */
+ data transfer is configured on the selected Stream */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
This parameter can be a value of @ref DMA_Priority_level */
@@ -92,80 +92,75 @@
This parameter can be a value of @ref DMA_FIFO_direct_mode
@note The Direct mode (FIFO mode disabled) cannot be used if the
memory-to-memory data transfer is configured on the selected stream */
-
+
uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
This parameter can be a value of @ref DMA_FIFO_threshold_level */
-
+
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
It specifies the amount of data to be transferred in a single non interruptable
- transaction.
+ transaction.
This parameter can be a value of @ref DMA_Memory_burst
@note The burst mode is possible only if the address Increment mode is enabled. */
-
+
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
It specifies the amount of data to be transferred in a single non interruptable
transaction.
This parameter can be a value of @ref DMA_Peripheral_burst
@note The burst mode is possible only if the address Increment mode is enabled. */
-
}DMA_InitTypeDef;
/**
- * @brief HAL DMA State structures definition
- */
+ * @brief HAL DMA State structures definition
+ */
typedef enum
{
- HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
- HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
+ HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
- HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
+ HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
- HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
+ HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
-
}HAL_DMA_StateTypeDef;
/**
- * @brief HAL DMA Error Code structure definition
- */
+ * @brief HAL DMA Error Code structure definition
+ */
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
-
}HAL_DMA_LevelCompleteTypeDef;
-
/**
- * @brief DMA handle Structure definition
- */
+ * @brief DMA handle Structure definition
+ */
typedef struct __DMA_HandleTypeDef
-{
+{
DMA_Stream_TypeDef *Instance; /*!< Register base address */
-
+
DMA_InitTypeDef Init; /*!< DMA communication parameters */
-
+
HAL_LockTypeDef Lock; /*!< DMA locking object */
-
+
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
-
+
void *Parent; /*!< Parent object state */
-
+
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
-
+
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
-
+
void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
-
+
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
-
-}DMA_HandleTypeDef;
+}DMA_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
@@ -178,7 +173,7 @@
*/
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
-#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
+#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
/**
@@ -418,6 +413,13 @@
*/
/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DMA handle state
+ * @param __HANDLE__: specifies the DMA handle.
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
/**
* @brief Return the current DMA Stream FIFO filled level.
* @param __HANDLE__: DMA handle
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma2d.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma2d.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma2d.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief DMA2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DMA2D peripheral:
@@ -71,15 +71,15 @@
*** DMA2D HAL driver macros list ***
=============================================
[..]
- Below the list of most used macros in DMA2D HAL driver.
+ Below the list of most used macros in DMA2D HAL driver :
(+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
(+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral.
(+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
- (+) __HAL_DMA2D_CLEAR_FLAG: Clears the DMA2D pending flags.
- (+) __HAL_DMA2D_ENABLE_IT: Enables the specified DMA2D interrupts.
- (+) __HAL_DMA2D_DISABLE_IT: Disables the specified DMA2D interrupts.
- (+) __HAL_DMA2D_GET_IT_SOURCE: Checks whether the specified DMA2D interrupt has occurred or not.
+ (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
+ (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
+ (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
+ (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not.
[..]
(@) You can refer to the DMA2D HAL driver header file for more useful macros
@@ -320,8 +320,8 @@
(+) Abort DMA2D transfer.
(+) Suspend DMA2D transfer.
(+) Continue DMA2D transfer.
- (+) polling for transfer complete.
- (+) handles DMA2D interrupt request.
+ (+) Poll for transfer complete.
+ (+) handle DMA2D interrupt request.
@endverbatim
* @{
@@ -827,8 +827,9 @@
/**
* @brief Configure the DMA2D Layer according to the specified
* parameters in the DMA2D_InitTypeDef and create the associated handle.
- * @param hdma2d: DMA2D handle
- * @param LayerIdx: DMA2D Layer index
+ * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * the configuration information for the DMA2D.
+ * @param LayerIdx: DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -931,7 +932,7 @@
* the configuration information for the DMA2D.
* @param CLUTCfg: pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
- * @param LayerIdx: DMA2D Layer index
+ * @param LayerIdx: DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -1013,7 +1014,7 @@
* @brief Enable the DMA2D CLUT Transfer.
* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index
+ * @param LayerIdx: DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -1041,7 +1042,7 @@
* @brief Disable the DMA2D CLUT Transfer.
* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index
+ * @param LayerIdx: DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -1070,7 +1071,7 @@
* @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param Line: Line Watermark configuration.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
@@ -1108,7 +1109,7 @@
##### Peripheral State and Errors functions #####
===============================================================================
[..]
- This subsection provides functions allowing to
+ This subsection provides functions allowing to :
(+) Check the DMA2D state
(+) Get error code
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma2d.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma2d.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma2d.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention
@@ -58,121 +58,116 @@
/* Exported types ------------------------------------------------------------*/
#define MAX_DMA2D_LAYER 2
-
+
/**
- * @brief DMA2D color Structure definition
+ * @brief DMA2D color Structure definition
*/
typedef struct
{
uint32_t Blue; /*!< Configures the blue value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
- uint32_t Green; /*!< Configures the green value.
+ uint32_t Green; /*!< Configures the green value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint32_t Red; /*!< Configures the red value.
+
+ uint32_t Red; /*!< Configures the red value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
} DMA2D_ColorTypeDef;
/**
- * @brief DMA2D CLUT Structure definition
+ * @brief DMA2D CLUT Structure definition
*/
typedef struct
{
- uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address. */
+ uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
- uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
+ uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
This parameter can be one value of @ref DMA2D_CLUT_CM */
-
+
uint32_t Size; /*!< configures the DMA2D CLUT size.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
} DMA2D_CLUTCfgTypeDef;
/**
- * @brief DMA2D Init structure definition
+ * @brief DMA2D Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< configures the DMA2D transfer mode.
This parameter can be one value of @ref DMA2D_Mode */
-
+
uint32_t ColorMode; /*!< configures the color format of the output image.
This parameter can be one value of @ref DMA2D_Color_Mode */
uint32_t OutputOffset; /*!< Specifies the Offset value.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
-
} DMA2D_InitTypeDef;
/**
- * @brief DMA2D Layer structure definition
+ * @brief DMA2D Layer structure definition
*/
typedef struct
{
-
-
uint32_t InputOffset; /*!< configures the DMA2D foreground offset.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode .
This parameter can be one value of @ref DMA2D_Input_Color_Mode */
-
+
uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode.
This parameter can be one value of @ref DMA2D_ALPHA_MODE */
- uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value
+ uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
+
} DMA2D_LayerCfgTypeDef;
/**
- * @brief HAL DMA2D State structures definition
- */
+ * @brief HAL DMA2D State structures definition
+ */
typedef enum
{
HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */
HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */
HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */
-
}HAL_DMA2D_StateTypeDef;
/**
- * @brief DMA2D handle Structure definition
- */
+ * @brief DMA2D handle Structure definition
+ */
typedef struct __DMA2D_HandleTypeDef
-{
+{
DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */
-
+
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */
-
+
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */
-
+
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */
-
+
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
-
+
HAL_LockTypeDef Lock; /*!< DMA2D Lock */
-
+
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */
-
+
__IO uint32_t ErrorCode; /*!< DMA2D Error code */
-
-} DMA2D_HandleTypeDef;
+} DMA2D_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Constants
* @{
- */
+ */
/** @defgroup DMA2D_Layer
* @{
*/
-#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
+#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
/**
* @}
*/
@@ -182,12 +177,12 @@
*/
#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
-#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */
+#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */
#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
/**
* @}
*/
-
+
/** @defgroup DMA2D_Mode
* @{
*/
@@ -200,7 +195,7 @@
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
/**
* @}
- */
+ */
/** @defgroup DMA2D_Color_Mode
* @{
@@ -242,7 +237,7 @@
* @}
*/
-/** @defgroup DMA2D_OFFSET
+/** @defgroup DMA2D_Offset
* @{
*/
#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
@@ -303,7 +298,7 @@
* @}
*/
-/** @defgroup DMA2D_CLUT_SIZE
+/** @defgroup DMA2D_Size_Clut
* @{
*/
#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */
@@ -321,8 +316,8 @@
#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
/**
* @}
- */
-
+ */
+
/** @defgroup DMA2D_Interrupts
* @{
*/
@@ -339,7 +334,7 @@
/**
* @}
*/
-
+
/** @defgroup DMA2D_Flag
* @{
*/
@@ -361,6 +356,13 @@
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DMA2D handle state
+ * @param __HANDLE__: specifies the DMA2D handle.
+ * @retval None
+ */
+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
+
/**
* @brief Enable the DMA2D.
* @param __HANDLE__: DMA2D handle
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma_ex.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma_ex.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_dma_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
@@ -21,7 +21,7 @@
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
-@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
-@- In Multi (Double) buffer mode, it is possible to update the base address for
- the AHB memory port on-the-fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
+ the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
@endverbatim
******************************************************************************
@@ -217,8 +217,8 @@
* @param Address: The new address
* @param memory: the memory to be changed, This parameter can be one of
* the following values:
- * @arg MEMORY0
- * @arg MEMORY1
+ * MEMORY0 /
+ * MEMORY1
* @note The MEMORY0 address can be changed only when the current transfer use
* MEMORY1 and the MEMORY1 address can be changed only when the current
* transfer use MEMORY0.
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma_ex.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma_ex.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_eth.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_eth.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_eth.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:
@@ -152,7 +152,8 @@
/**
* @brief Initializes the Ethernet MAC and DMA according to default
* parameters.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
@@ -389,7 +390,8 @@
/**
* @brief De-Initializes the ETH peripheral.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
@@ -412,7 +414,8 @@
/**
* @brief Initializes the DMA Tx descriptors in chain mode.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param DMATxDescTab: Pointer to the first Tx desc list
* @param TxBuff: Pointer to the first TxBuffer list
* @param TxBuffCount: Number of the used Tx desc in the list
@@ -478,7 +481,8 @@
/**
* @brief Initializes the DMA Rx descriptors in chain mode.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param DMARxDescTab: Pointer to the first Rx desc list
* @param RxBuff: Pointer to the first RxBuffer list
* @param RxBuffCount: Number of the used Rx desc in the list
@@ -547,7 +551,8 @@
/**
* @brief Initializes the ETH MSP.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
@@ -559,7 +564,8 @@
/**
* @brief DeInitializes ETH MSP.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
@@ -588,7 +594,7 @@
HAL_ETH_GetReceivedFrame_IT();
(+) Read from an External PHY register
HAL_ETH_ReadPHYRegister();
- (+) Writo to an External PHY register
+ (+) Write to an External PHY register
HAL_ETH_WritePHYRegister();
@endverbatim
@@ -598,7 +604,8 @@
/**
* @brief Sends an Ethernet frame.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param FrameLength: Amount of data to be sent
* @retval HAL status
*/
@@ -711,7 +718,8 @@
/**
* @brief Checks for received frames.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
@@ -789,7 +797,8 @@
/**
* @brief Gets the Received frame in interrupt mode.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
@@ -873,7 +882,8 @@
/**
* @brief This function handles ETH interrupt request.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
@@ -932,7 +942,8 @@
/**
* @brief Tx Transfer completed callbacks.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
@@ -944,7 +955,8 @@
/**
* @brief Rx Transfer completed callbacks.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
@@ -956,7 +968,8 @@
/**
* @brief Ethernet transfer error callbacks
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
@@ -968,15 +981,15 @@
/**
* @brief Reads a PHY register
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
* This parameter can be one of the following values:
- * @arg PHY_BCR: Transceiver Basic Control Register
- * @arg PHY_BSR: Transceiver Basic Status Register
- * @arg More PHY register could be read depending on the used PHY
+ * PHY_BCR: Transceiver Basic Control Register,
+ * PHY_BSR: Transceiver Basic Status Register.
+ * More PHY register could be read depending on the used PHY
* @param RegValue: PHY register value
- * @retval HAL_TIMEOUT: in case of timeout
- * MACMIIDR register value: Data read from the selected PHY register (correct read )
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
{
@@ -1037,11 +1050,12 @@
/**
* @brief Writes to a PHY register.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
* This parameter can be one of the following values:
- * @arg PHY_BCR: Transceiver Control Register
- * @arg More PHY register could be written depending on the used PHY
+ * PHY_BCR: Transceiver Control Register.
+ * More PHY register could be written depending on the used PHY
* @param RegValue: the value to write
* @retval HAL status
*/
@@ -1129,7 +1143,8 @@
/**
* @brief Enables Ethernet MAC and DMA reception/transmission
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
@@ -1167,7 +1182,8 @@
/**
* @brief Stop Ethernet MAC and DMA reception/transmission
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
@@ -1205,7 +1221,8 @@
/**
* @brief Set ETH MAC Configuration.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param macconf: MAC Configuration structure
* @retval HAL status
*/
@@ -1371,7 +1388,8 @@
/**
* @brief Sets ETH DMA Configuration.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param dmaconf: DMA Configuration structure
* @retval HAL status
*/
@@ -1478,7 +1496,8 @@
/**
* @brief Return the ETH HAL state
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval HAL state
*/
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
@@ -1493,7 +1512,8 @@
/**
* @brief Configures Ethernet MAC and DMA with default parameters.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param err: Ethernet Init error
* @retval HAL status
*/
@@ -1749,7 +1769,8 @@
/**
* @brief Configures the selected MAC address.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @param MacAddr: The MAC address to configure
* This parameter can be one of the following values:
* @arg ETH_MAC_Address0: MAC Address0
@@ -1779,7 +1800,8 @@
/**
* @brief Enables the MAC transmission.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
@@ -1798,7 +1820,8 @@
/**
* @brief Disables the MAC transmission.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
@@ -1817,7 +1840,8 @@
/**
* @brief Enables the MAC reception.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
@@ -1836,7 +1860,8 @@
/**
* @brief Disables the MAC reception.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
@@ -1855,7 +1880,8 @@
/**
* @brief Enables the DMA transmission.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
@@ -1866,7 +1892,8 @@
/**
* @brief Disables the DMA transmission.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
@@ -1877,7 +1904,8 @@
/**
* @brief Enables the DMA reception.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
@@ -1888,7 +1916,8 @@
/**
* @brief Disables the DMA reception.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
@@ -1899,7 +1928,8 @@
/**
* @brief Clears the ETHERNET transmit FIFO.
- * @param heth: ETH handle
+ * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * the configuration information for ETHERNET module
* @retval None
*/
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_eth.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_eth.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_eth.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
@@ -85,24 +85,24 @@
and the mode (half/full-duplex).
This parameter can be a value of @ref ETH_AutoNegotiation */
- uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
This parameter can be a value of @ref ETH_Speed */
uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
This parameter can be a value of @ref ETH_Duplex_Mode */
- uint16_t PhyAddress; /*!< Ethernet PHY address
+ uint16_t PhyAddress; /*!< Ethernet PHY address.
This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
- uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode
+ uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
This parameter can be a value of @ref ETH_Rx_Mode */
- uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software
+ uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
This parameter can be a value of @ref ETH_Checksum_Mode */
- uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface
+ uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
This parameter can be a value of @ref ETH_Media_Interface */
} ETH_InitTypeDef;
@@ -124,78 +124,78 @@
When disabled, the MAC can send up to 16384 bytes.
This parameter can be a value of @ref ETH_Jabber */
- uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission
+ uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
This parameter can be a value of @ref ETH_Inter_Frame_Gap */
- uint32_t CarrierSense; /*!< Selects or not the Carrier Sense
+ uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
This parameter can be a value of @ref ETH_Carrier_Sense */
- uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn
+ uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
- in Half-Duplex mode
+ in Half-Duplex mode.
This parameter can be a value of @ref ETH_Receive_Own */
- uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode
+ uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
This parameter can be a value of @ref ETH_Loop_Back_Mode */
uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
This parameter can be a value of @ref ETH_Checksum_Offload */
uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
- when a collision occurs (Half-Duplex mode)
+ when a collision occurs (Half-Duplex mode).
This parameter can be a value of @ref ETH_Retry_Transmission */
- uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping
+ uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
- uint32_t BackOffLimit; /*!< Selects the BackOff limit value
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
This parameter can be a value of @ref ETH_Back_Off_Limit */
- uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode)
+ uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
This parameter can be a value of @ref ETH_Deferral_Check */
- uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering)
+ uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
This parameter can be a value of @ref ETH_Receive_All */
- uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
This parameter can be a value of @ref ETH_Source_Addr_Filter */
uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
This parameter can be a value of @ref ETH_Pass_Control_Frames */
- uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames
+ uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
- uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames
+ uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
This parameter can be a value of @ref ETH_Destination_Addr_Filter */
uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
This parameter can be a value of @ref ETH_Promiscuous_Mode */
- uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
+ uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
- uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
+ uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
- uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table
+ uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
- uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table
+ uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
- uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
- uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames
+ uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
- automatic retransmission of PAUSE Frame
+ automatic retransmission of PAUSE Frame.
This parameter can be a value of @ref ETH_Pause_Low_Threshold */
uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
- unicast address and unique multicast address)
+ unicast address and unique multicast address).
This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
@@ -207,7 +207,7 @@
This parameter can be a value of @ref ETH_Transmit_Flow_Control */
uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
- comparison and filtering
+ comparison and filtering.
This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
@@ -221,54 +221,54 @@
typedef struct
{
- uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames
+ uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
- uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode
+ uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
This parameter can be a value of @ref ETH_Receive_Store_Forward */
- uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames
+ uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
This parameter can be a value of @ref ETH_Flush_Received_Frame */
- uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode
+ uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
This parameter can be a value of @ref ETH_Transmit_Store_Forward */
- uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control
+ uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
- uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames
+ uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
This parameter can be a value of @ref ETH_Forward_Error_Frames */
uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
and length less than 64 bytes) including pad-bytes and CRC)
This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
- uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO
+ uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
This parameter can be a value of @ref ETH_Receive_Threshold_Control */
uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
frame of Transmit data even before obtaining the status for the first frame.
This parameter can be a value of @ref ETH_Second_Frame_Operate */
- uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats
+ uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
This parameter can be a value of @ref ETH_Address_Aligned_Beats */
- uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers
+ uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
This parameter can be a value of @ref ETH_Fixed_Burst */
- uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction
+ uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
- uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction
+ uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
- uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format
+ uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
- uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration
+ uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
This parameter can be a value of @ref ETH_DMA_Arbitration */
} ETH_DMAInitTypeDef;
@@ -1290,9 +1290,9 @@
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
-/**
- * @brief ETH_DMA_Enhanced_descriptor_format
- */
+/** @defgroup ETH_DMA_Enhanced_descriptor_format
+ * @{
+ */
#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
@@ -1700,6 +1700,12 @@
/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset ETH handle state
+ * @param __HANDLE__: specifies the ETH handle.
+ * @retval None
+ */
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
+
/**
* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
* @param __HANDLE__: ETH Handle
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_flash.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_flash.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -212,7 +212,7 @@
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
@@ -387,11 +387,11 @@
/**
* @brief FLASH end of operation interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
- * - Mass Erase: Bank number which has been requested to erase
- * - Sectors Erase: Sector which has been erased
+ * Mass Erase: Bank number which has been requested to erase
+ * Sectors Erase: Sector which has been erased
* (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
- * - Program: Address which was selected for data program
- * @retval none
+ * Program: Address which was selected for data program
+ * @retval None
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
@@ -403,10 +403,10 @@
/**
* @brief FLASH operation error interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
- * - Mass Erase: Bank number which has been requested to erase
- * - Sectors Erase: Sector number which returned an error
- * - Program: Address which was selected for data program
- * @retval none
+ * Mass Erase: Bank number which has been requested to erase
+ * Sectors Erase: Sector number which returned an error
+ * Program: Address which was selected for data program
+ * @retval None
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
@@ -437,7 +437,7 @@
/**
* @brief Unlock the FLASH control register access
* @param None
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
@@ -458,7 +458,7 @@
/**
* @brief Locks the FLASH control register access
* @param None
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
@@ -472,7 +472,7 @@
/**
* @brief Unlock the FLASH Option Control Registers access.
* @param None
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
@@ -493,7 +493,7 @@
/**
* @brief Lock the FLASH Option Control Registers access.
* @param None
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{
@@ -506,7 +506,7 @@
/**
* @brief Launch the option byte loading.
* @param None
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
@@ -529,7 +529,7 @@
##### Peripheral Errors functions #####
===============================================================================
[..]
- This subsection permit to get in run-time Errors of the FLASH peripheral.
+ This subsection permits to get in run-time Errors of the FLASH peripheral.
@endverbatim
* @{
@@ -558,7 +558,7 @@
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout: maximum flash operationtimeout
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_flash.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_flash.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_flash.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_flash_ex.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_flash_ex.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@@ -30,7 +30,7 @@
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
HAL_FLASH_Lock() functions
(++) Erase function: Erase sector, erase all sectors
- (++) There is two mode of erase :
+ (++) There are two modes of erase :
(+++) Polling Mode using HAL_FLASHEx_Erase()
(+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
@@ -154,7 +154,7 @@
* contains the configuration information on faulty sector in case of error
* (0xFFFFFFFF means that all the sectors have been correctly erased)
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
{
@@ -224,7 +224,7 @@
* @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
* contains the configuration information for the erasing.
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
@@ -277,7 +277,7 @@
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
{
@@ -361,7 +361,7 @@
* @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
* contains the configuration information for the programming.
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
{
@@ -440,7 +440,7 @@
* @note This function can be used only for STM32F427xx/STM32F429xx/STM32F437xx/STM32F439xx/STM32F401xx devices.
*
* @param None
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
{
@@ -466,7 +466,7 @@
* @note This function can be used only for STM32F427xx/STM32F429xx/STM32F437xx/STM32F439xx/STM32F401xx devices.
*
* @param None
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
{
@@ -522,7 +522,7 @@
* @arg FLASH_BANK_2: Bank2 to be erased
* @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
{
@@ -801,7 +801,7 @@
* @arg FLASH_BANK_2: WRP on all sectors of bank2
* @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
{
@@ -865,7 +865,7 @@
* @arg FLASH_BANK_2: WRP on all sectors of bank2
* @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
{
@@ -1014,7 +1014,7 @@
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: WRP on all sectors of bank1
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
{
@@ -1050,7 +1050,7 @@
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: WRP on all sectors of bank1
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
{
@@ -1080,7 +1080,7 @@
* This parameter can be one of the following values:
* @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
* @arg OB_PCROP_Sector_All
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector)
{
@@ -1108,7 +1108,7 @@
* This parameter can be one of the following values:
* @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
* @arg OB_PCROP_Sector_All
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)
{
@@ -1140,7 +1140,7 @@
*
* @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
*
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
{
@@ -1174,7 +1174,7 @@
* This parameter can be one of the following values:
* @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
* @arg OB_STDBY_RST: Reset generated when entering in STANDBY
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
{
@@ -1210,7 +1210,7 @@
* @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
* @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
* @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
{
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_flash_ex.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_flash_ex.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention
@@ -61,19 +61,19 @@
*/
typedef struct
{
- uint32_t TypeErase; /*!< TypeErase: Mass erase or sector Erase.
+ uint32_t TypeErase; /*!< Mass erase or sector Erase.
This parameter can be a value of @ref FLASHEx_Type_Erase */
- uint32_t Banks; /*!< Banks: Select banks to erase when Mass erase is enabled
+ uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
This parameter must be a value of @ref FLASHEx_Banks */
- uint32_t Sector; /*!< Sector: Initial FLASH sector to erase when Mass erase is disabled
+ uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
This parameter must be a value of @ref FLASHEx_Sectors */
- uint32_t NbSectors; /*!< NbSectors: Number of sectors to be erased.
+ uint32_t NbSectors; /*!< Number of sectors to be erased.
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
- uint32_t VoltageRange;/*!< VoltageRange: The device voltage range which defines the erase parallelism
+ uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
This parameter must be a value of @ref FLASHEx_Voltage_Range */
} FLASH_EraseInitTypeDef;
@@ -83,26 +83,25 @@
*/
typedef struct
{
- uint32_t OptionType; /*!< OptionType: Option byte to be configured.
+ uint32_t OptionType; /*!< Option byte to be configured.
This parameter can be a value of @ref FLASHEx_Option_Type */
- uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
+ uint32_t WRPState; /*!< Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_WRP_State */
- uint32_t WRPSector; /*!< WRPSector: specifies the sector(s) to be write protected
+ uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
The value of this parameter depend on device used within the same series */
- uint32_t Banks; /*!< Banks: Select banks for WRP activation/deactivation of all sectors
+ uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
This parameter must be a value of @ref FLASHEx_Banks */
- uint32_t RDPLevel; /*!< RDPLevel: Set the read protection level..
+ uint32_t RDPLevel; /*!< Set the read protection level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
- uint32_t BORLevel; /*!< BORLevel: Set the BOR Level.
+ uint32_t BORLevel; /*!< Set the BOR Level.
This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
- uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
- This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
+ uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */
} FLASH_OBProgramInitTypeDef;
@@ -112,27 +111,27 @@
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE)
typedef struct
{
- uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
+ uint32_t OptionType; /*!< Option byte to be configured for extension.
This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */
- uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
+ uint32_t PCROPState; /*!< PCROP activation or deactivation.
This parameter can be a value of @ref FLASHEx_PCROP_State */
#if defined (STM32F401xC) || defined (STM32F401xE)
- uint16_t Sectors; /*!< Sectors: specifies the sector(s) set for PCROP
+ uint16_t Sectors; /*!< specifies the sector(s) set for PCROP.
This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
#endif /* STM32F401xC || STM32F401xE */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
- uint32_t Banks; /*!< Banks: Select banks for PCROP activation/deactivation of all sectors
+ uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors.
This parameter must be a value of @ref FLASHEx_Banks */
- uint16_t SectorsBank1; /*!< SectorsBank1: specifies the sector(s) set for PCROP for Bank1
+ uint16_t SectorsBank1; /*!< Specifies the sector(s) set for PCROP for Bank1.
This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
- uint16_t SectorsBank2; /*!< SectorsBank2: specifies the sector(s) set for PCROP for Bank2
+ uint16_t SectorsBank2; /*!< Specifies the sector(s) set for PCROP for Bank2.
This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
- uint8_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
+ uint8_t BootConfig; /*!< Specifies Option bytes for boot config.
This parameter can be a value of @ref FLASHEx_Dual_Boot */
#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_gpio.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_gpio.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,18 +2,18 @@
******************************************************************************
* @file stm32f4xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- *
+ *
@verbatim
==============================================================================
##### GPIO Peripheral features #####
- ==============================================================================
+ ==============================================================================
[..]
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
configured by software in several modes:
@@ -22,7 +22,7 @@
(++) Output mode
(++) Alternate function mode
(++) External interrupt/event lines
-
+
(+) During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
@@ -31,27 +31,27 @@
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
-
+
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
multiplexer that allows only one peripheral alternate function (AF) connected
to an IO pin at a time. In this way, there can be no conflict between peripherals
sharing the same IO pin.
-
+
(+) All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-
+
(+) The external interrupt/event controller consists of up to 23 edge detectors
(16 lines are connected to GPIO) for generating event/interrupt requests (each
input line can be independently configured to select the type (interrupt or event)
and the corresponding trigger event (rising or falling or both). Each line can
also be masked independently.
-
+
##### How to use this driver #####
==============================================================================
- [..]
+ [..]
(#) Enable the GPIO AHB clock using the following function: __GPIOx_CLK_ENABLE().
-
+
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
@@ -65,7 +65,7 @@
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
-
+
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
@@ -213,14 +213,17 @@
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
- temp = ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)) ;
- GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- GPIOx->AFR[position >> 3] |= temp;
+ temp = GPIOx->AFR[position >> 3];
+ temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+ GPIOx->AFR[position >> 3] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
- GPIOx->MODER |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
@@ -229,18 +232,23 @@
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- GPIOx->OSPEEDR |= (GPIO_Init->Speed << (position * 2));
+ temp = GPIOx->OSPEEDR;
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+ temp |= (GPIO_Init->Speed << (position * 2));
+ GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
- GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
- GPIOx->OTYPER |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+ temp = GPIOx->OTYPER;
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+ GPIOx->OTYPER = temp;
}
/* Activate the Pull-up or Pull down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
- GPIOx->PUPDR |= ((GPIO_Init->Pull) << (position * 2));
-
+ temp = GPIOx->PUPDR;
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ temp |= ((GPIO_Init->Pull) << (position * 2));
+ GPIOx->PUPDR = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
@@ -249,35 +257,44 @@
/* Enable SYSCFG Clock */
__SYSCFG_CLK_ENABLE();
- temp = ((uint32_t)0x0F) << (4 * (position & 0x03));
- SYSCFG->EXTICR[position >> 2] &= ~temp;
- SYSCFG->EXTICR[position >> 2] |= ((uint32_t)(__HAL_GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03)));
-
+ temp = SYSCFG->EXTICR[position >> 2];
+ temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+ temp |= ((uint32_t)(__HAL_GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03)));
+ SYSCFG->EXTICR[position >> 2] = temp;
+
/* Clear EXTI line configuration */
- EXTI->IMR &= ~((uint32_t)iocurrent);
- EXTI->EMR &= ~((uint32_t)iocurrent);
-
+ temp = EXTI->IMR;
+ temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
- EXTI->IMR |= iocurrent;
+ temp |= iocurrent;
}
+ EXTI->IMR = temp;
+
+ temp = EXTI->EMR;
+ temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{
- EXTI->EMR |= iocurrent;
+ temp |= iocurrent;
}
+ EXTI->EMR = temp;
/* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~((uint32_t)iocurrent);
- EXTI->FTSR &= ~((uint32_t)iocurrent);
-
+ temp = EXTI->RTSR;
+ temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
{
- EXTI->RTSR |= iocurrent;
+ temp |= iocurrent;
}
+ EXTI->RTSR = temp;
+
+ temp = EXTI->FTSR;
+ temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
{
- EXTI->FTSR |= iocurrent;
+ temp |= iocurrent;
}
+ EXTI->FTSR = temp;
}
}
}
@@ -324,7 +341,6 @@
/* Deactivate the Pull-up oand Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
-
/*------------------------- EXTI Mode Configuration --------------------*/
/* Configure the External Interrupt or event for the current IO */
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
@@ -396,8 +412,8 @@
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinState: specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
- * @arg GPIO_BIT_RESET: to clear the port pin
- * @arg GPIO_BIT_SET: to set the port pin
+ * @arg GPIO_PIN_RESET: to clear the port pin
+ * @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
@@ -432,6 +448,45 @@
}
/**
+ * @brief Locks GPIO Pins configuration registers.
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ * @note The configuration of the locked GPIO pins can no longer be modified
+ * until the next reset.
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F4 family
+ * @param GPIO_Pin: specifies the port bit to be locked.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Apply lock key write sequence */
+ tmp |= GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+
+ if(GPIOx->LCKR & GPIO_LCKR_LCKK)
+ {
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
* @brief This function handles EXTI interrupt request.
* @param GPIO_Pin: Specifies the pins connected EXTI line
* @retval None
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_gpio.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_gpio.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_gpio.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
@@ -73,7 +73,7 @@
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed_define */
- uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
This parameter can be a value of @ref GPIO_Alternat_function_selection */
}GPIO_InitTypeDef;
@@ -177,7 +177,6 @@
/**
* @}
*/
-
/** @defgroup GPIO_speed_define
* @brief GPIO Output Maximum frequency
* @{
@@ -216,7 +215,7 @@
/**
* @brief Checks whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__: specifies the EXTI line flag to check.
- * This parameter can be EXTI_Linex where x can be(0..15)
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
@@ -224,7 +223,7 @@
/**
* @brief Clears the EXTI's line pending flags.
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..15)
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
@@ -232,7 +231,7 @@
/**
* @brief Checks whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__: specifies the EXTI line to check.
- * This parameter can be EXTI_Linex where x can be(0..15)
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
@@ -240,7 +239,7 @@
/**
* @brief Clears the EXTI's line pending bits.
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..15)
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
@@ -255,10 +254,11 @@
/* IO operation functions *******************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_gpio_ex.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_gpio_ex.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hash.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hash.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hash.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
@@ -148,7 +148,8 @@
/**
* @brief Initializes the HASH according to the specified parameters in the
HASH_HandleTypeDef and creates the associated handle.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
@@ -192,7 +193,8 @@
/**
* @brief DeInitializes the HASH peripheral.
* @note This API must be called before starting a new processing.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
@@ -229,7 +231,8 @@
/**
* @brief Initializes the HASH MSP.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
@@ -241,7 +244,8 @@
/**
* @brief DeInitializes HASH MSP.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
@@ -253,7 +257,8 @@
/**
* @brief Input data transfer complete callback.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
@@ -265,7 +270,8 @@
/**
* @brief Data transfer Error callback.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
@@ -278,7 +284,8 @@
/**
* @brief Digest computation complete callback. It is used only with interrupt.
* @note This callback is not relevant with DMA.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval None
*/
__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
@@ -311,9 +318,9 @@
/**
* @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param pOutBuffer: Pointer to the Output buffer (hashed buffer).
* @param Size: Length of the input buffer in bytes.
* If the Size is multiple of 64 bytes, appending the input buffer is possible.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware
@@ -388,7 +395,8 @@
/**
* @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is multiple of 64 bytes, appending the input buffer is possible.
@@ -434,9 +442,9 @@
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: HASH handle
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param pOutBuffer: Pointer to the Output buffer (hashed buffer).
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
@@ -510,7 +518,8 @@
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -575,8 +584,8 @@
/**
* @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: HASH handle
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pOutBuffer: Pointer to the Output buffer (hashed buffer).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -727,9 +736,9 @@
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: HASH handle
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param pOutBuffer: Pointer to the Output buffer (hashed buffer).
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
@@ -880,7 +889,8 @@
/**
* @brief This function handles HASH interrupt request.
- * @param hhash: hash handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval None
*/
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
@@ -923,11 +933,11 @@
/**
* @brief Initializes the HASH peripheral in MD5 mode then enables DMA to
control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -974,7 +984,8 @@
/**
* @brief Returns the computed digest in MD5 mode
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
* @param Timeout: Timeout value
* @retval HAL status
@@ -1026,11 +1037,11 @@
/**
* @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to
control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -1078,7 +1089,8 @@
/**
* @brief Returns the computed digest in SHA1 mode.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
* @param Timeout: Timeout value
* @retval HAL status
@@ -1150,7 +1162,8 @@
/**
* @brief Initializes the HASH peripheral in HMAC MD5 mode
* then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -1294,7 +1307,8 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA1 mode
* then processes pInBuffer. The digest is available in pOutBuffer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -1460,7 +1474,8 @@
/**
* @brief Initializes the HASH peripheral in HMAC MD5 mode
* then enables DMA to control data transfer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -1526,7 +1541,8 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA1 mode
* then enables DMA to control data transfer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -1609,7 +1625,8 @@
/**
* @brief return the HASH state
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval HAL state
*/
HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hash.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hash.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hash.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_HASH_H
@@ -56,72 +56,68 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/**
- * @brief HASH Configuration Structure definition
+ * @brief HASH Configuration Structure definition
*/
typedef struct
-{
+{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref HASH_Data_Type */
-
+
uint32_t KeySize; /*!< The key size is used only in HMAC operation */
-
+
uint8_t* pKey; /*!< The key is used only in HMAC operation */
-
}HASH_InitTypeDef;
/**
- * @brief HAL State structures definition
+ * @brief HAL State structures definition
*/
typedef enum
{
HAL_HASH_STATE_RESET = 0x00, /*!< HASH not yet initialized or disabled */
- HAL_HASH_STATE_READY = 0x01, /*!< HASH initialized and ready for use */
- HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */
+ HAL_HASH_STATE_READY = 0x01, /*!< HASH initialized and ready for use */
+ HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */
HAL_HASH_STATE_TIMEOUT = 0x03, /*!< HASH timeout state */
HAL_HASH_STATE_ERROR = 0x04 /*!< HASH error state */
-
}HAL_HASH_STATETypeDef;
/**
- * @brief HAL phase structures definition
- */
+ * @brief HAL phase structures definition
+ */
typedef enum
{
HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready for initialization */
HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in processing phase */
-
}HAL_HASHPhaseTypeDef;
/**
- * @brief HASH Handle Structure definition
- */
+ * @brief HASH Handle Structure definition
+ */
typedef struct
-{
+{
HASH_InitTypeDef Init; /*!< HASH required parameters */
-
+
uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
-
+
uint8_t *pHashOutBuffPtr; /*!< Pointer to input buffer */
-
+
__IO uint32_t HashBuffSize; /*!< Size of buffer to be processed */
-
+
__IO uint32_t HashInCount; /*!< Counter of inputed data */
-
+
__IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
-
+
HAL_StatusTypeDef Status; /*!< HASH peripheral status */
-
+
HAL_HASHPhaseTypeDef Phase; /*!< HASH peripheral phase */
-
+
DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */
-
+
HAL_LockTypeDef Lock; /*!< HASH locking object */
-
+
__IO HAL_HASH_STATETypeDef State; /*!< HASH peripheral state */
-
} HASH_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
@@ -130,9 +126,9 @@
* @{
*/
-/** @defgroup HASH_Algo_Selection
+/** @defgroup HASH_Algo_Selection
* @{
- */
+ */
#define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
#define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
#define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
@@ -146,7 +142,7 @@
* @}
*/
-/** @defgroup HASH_Algorithm_Mode
+/** @defgroup HASH_Algorithm_Mode
* @{
*/
#define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
@@ -158,9 +154,9 @@
* @}
*/
-/** @defgroup HASH_Data_Type
+/** @defgroup HASH_Data_Type
* @{
- */
+ */
#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
@@ -174,7 +170,7 @@
* @}
*/
-/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode
* @{
*/
#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
@@ -186,9 +182,9 @@
* @}
*/
-/** @defgroup HASH_flags_definition
+/** @defgroup HASH_flags_definition
* @{
- */
+ */
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
@@ -196,9 +192,9 @@
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
/**
* @}
- */
+ */
-/** @defgroup HASH_interrupts_definition
+/** @defgroup HASH_interrupts_definition
* @{
*/
#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */
@@ -213,6 +209,12 @@
/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset HASH handle state
+ * @param __HANDLE__: specifies the HASH handle.
+ * @retval None
+ */
+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
+
/** @brief Check whether the specified HASH flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hash_ex.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hash_ex.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hash_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief HASH HAL Extension module driver.
* This file provides firmware functions to manage the following
* functionalities of HASH peripheral:
@@ -143,9 +143,9 @@
/**
* @brief Initializes the HASH peripheral in SHA224 mode
* then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param pOutBuffer: Pointer to the output buffer (hashed buffer).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
@@ -219,9 +219,9 @@
/**
* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: HASH handle
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param pOutBuffer: Pointer to the output buffer (hashed buffer).
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
@@ -296,7 +296,8 @@
/**
* @brief Initializes the HASH peripheral in SHA224 mode
* then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -341,7 +342,8 @@
/**
* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -406,9 +408,9 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA224 mode
* then processes pInBuffer. The digest is available in pOutBuffer.
- * @param hhash: HASH handle
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param pOutBuffer: Pointer to the output buffer (hashed buffer).
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
@@ -549,9 +551,9 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA256 mode
* then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: HASH handle
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param pOutBuffer: Pointer to the output buffer (hashed buffer).
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
+ * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
@@ -715,7 +717,8 @@
/**
* @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -858,7 +861,8 @@
/**
* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -1000,7 +1004,8 @@
/**
* @brief This function handles HASH interrupt request.
- * @param hhash: hash handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @retval None
*/
void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)
@@ -1045,11 +1050,11 @@
/**
* @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to
control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -1096,8 +1101,10 @@
/**
* @brief Returns the computed digest in SHA224
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
+ * @param Timeout: Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1147,11 +1154,11 @@
/**
* @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to
control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
@@ -1198,8 +1205,10 @@
/**
* @brief Returns the computed digest in SHA256.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
+ * @param Timeout: Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1269,7 +1278,8 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA224 mode
* then enables DMA to control data transfer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
@@ -1335,7 +1345,8 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA256 mode
* then enables DMA to control data transfer.
- * @param hhash: HASH handle
+ * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * the configuration information for HASH module
* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
* @param Size: Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hash_ex.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hash_ex.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hash_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of HASH HAL Extension module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hcd.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hcd.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_hcd.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -25,9 +25,9 @@
(#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
(#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
- (##) Enable the HCD/USB Low Level interface clock using
- (+++) __OTGFS-OTG_CLK_ENABLE()/__OTGHS-OTG_CLK_ENABLE();
- (+++) __OTGHSULPI_CLK_ENABLE(); (For High Speed Mode)
+ (##) Enable the HCD/USB Low Level interface clock using the following macros
+ (+++) __OTGFS-OTG_CLK_ENABLE() or __OTGHS-OTG_CLK_ENABLE()
+ (+++) __OTGHSULPI_CLK_ENABLE() For High Speed Mode
(##) Initialize the related GPIO clocks
(##) Configure HCD pin-out
@@ -113,8 +113,8 @@
/**
* @brief Initialize the host driver
- * @param hhcd : HCD handle
- * @retval HAL state
+ * @param hhcd: HCD handle
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
@@ -151,27 +151,27 @@
/**
* @brief Initialize a host channel
- * @param hhcd : HCD handle
- * @param ch_num : Channel number
+ * @param hhcd: HCD handle
+ * @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
- * @param epnum : Endpoint number
+ * @param epnum: Endpoint number.
* This parameter can be a value from 1 to 15
* @param dev_address : Current device address
* This parameter can be a value from 0 to 255
- * @param speed : Current device speed
- * This parameter can be one of the these values:
- * @arg HCD_SPEED_HIGH: High speed mode
- * @arg HCD_SPEED_FULL: Full speed mode
- * @arg HCD_SPEED_LOW: Low speed mode
- * @param ep_type : Endpoint Type
- * This parameter can be one of the these values:
- * @arg EP_TYPE_CTRL: Control type
- * @arg EP_TYPE_ISOC: Isochrounous type
- * @arg EP_TYPE_BULK: Bulk type
- * @arg EP_TYPE_INTR: Interrupt type
- * @param mps : Max Packet Size
+ * @param speed: Current device speed.
+ * This parameter can be one of these values:
+ * HCD_SPEED_HIGH: High speed mode,
+ * HCD_SPEED_FULL: Full speed mode,
+ * HCD_SPEED_LOW: Low speed mode
+ * @param ep_type: Endpoint Type.
+ * This parameter can be one of these values:
+ * EP_TYPE_CTRL: Control type,
+ * EP_TYPE_ISOC: Isochrounous type,
+ * EP_TYPE_BULK: Bulk type,
+ * EP_TYPE_INTR: Interrupt type
+ * @param mps: Max Packet Size.
* This parameter can be a value from 0 to32K
- * @retval HAL state
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
@@ -209,10 +209,10 @@
/**
* @brief Halt a host channel
- * @param hhcd : HCD handle
- * @param ch_num : Channel number
+ * @param hhcd: HCD handle
+ * @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
- * @retval HAL state
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
uint8_t ch_num)
@@ -227,8 +227,8 @@
}
/**
* @brief DeInitialize the host driver
- * @param hhcd : HCD handle
- * @retval HAL state
+ * @param hhcd: HCD handle
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
{
@@ -294,30 +294,27 @@
/**
* @brief Submit a new URB for processing
- * @param hhcd : HCD handle
- * @param ch_num : Channel number
+ * @param hhcd: HCD handle
+ * @param ch_num: Channel number.
* This parameter can be a value from 1 to 15
- * @param direction : Channel number
- * This parameter can be one of the these values:
- * 0 : Output
- * 1 : Input
- * @param ep_type : Endpoint Type
- * This parameter can be one of the these values:
- * @arg EP_TYPE_CTRL: Control type
- * @arg EP_TYPE_ISOC: Isochrounous type
- * @arg EP_TYPE_BULK: Bulk type
- * @arg EP_TYPE_INTR: Interrupt type
- * @param token : Endpoint Type
- * This parameter can be one of the these values:
- * @arg 0: HC_PID_SETUP
- * @arg 1: HC_PID_DATA1
- * @param pbuff : pointer to URB data
- * @param length : Length of URB data
- * @param do_ping : activate do ping protocol (for high speed only)
- * This parameter can be one of the these values:
- * 0 : do ping inactive
- * 1 : do ping active
- * @retval HAL state
+ * @param direction: Channel number.
+ * This parameter can be one of these values:
+ * 0 : Output / 1 : Input
+ * @param ep_type: Endpoint Type.
+ * This parameter can be one of these values:
+ * EP_TYPE_CTRL: Control type/
+ * EP_TYPE_ISOC: Isochrounous type/
+ * EP_TYPE_BULK: Bulk type/
+ * EP_TYPE_INTR: Interrupt type/
+ * @param token: Endpoint Type.
+ * This parameter can be one of these values:
+ * 0: HC_PID_SETUP / 1: HC_PID_DATA1
+ * @param pbuff: pointer to URB data
+ * @param length: Length of URB data
+ * @param do_ping: activate do ping protocol (for high speed only).
+ * This parameter can be one of these values:
+ * 0 : do ping inactive / 1 : do ping active
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
@@ -442,7 +439,7 @@
/**
* @brief This function handles HCD interrupt request.
* @param hhcd: HCD handle
- * @retval none
+ * @retval None
*/
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
{
@@ -583,16 +580,16 @@
/**
* @brief Notify URB state change callback.
* @param hhcd: HCD handle
- * @param chnum : Channel number
+ * @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @param urb_state:
- * This parameter can be one of the these values:
- * @arg URB_IDLE
- * @arg URB_DONE
- * @arg URB_NOTREADY
- * @arg URB_NYET
- * @arg URB_ERROR
- * @arg URB_STALL
+ * This parameter can be one of these values:
+ * URB_IDLE/
+ * URB_DONE/
+ * URB_NOTREADY/
+ * URB_NYET/
+ * URB_ERROR/
+ * URB_STALL/
* @retval None
*/
__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
@@ -623,8 +620,8 @@
/**
* @brief Start the host driver
- * @param hhcd : HCD handle
- * @retval HAL state
+ * @param hhcd: HCD handle
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
{
@@ -637,8 +634,8 @@
/**
* @brief Stop the host driver
- * @param hhcd : HCD handle
- * @retval HAL state
+ * @param hhcd: HCD handle
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
@@ -651,8 +648,8 @@
/**
* @brief Reset the host port
- * @param hhcd : HCD handle
- * @retval HAL state
+ * @param hhcd: HCD handle
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
{
@@ -671,7 +668,7 @@
##### Peripheral State functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -680,7 +677,7 @@
/**
* @brief Return the HCD state
- * @param hhcd : HCD handle
+ * @param hhcd: HCD handle
* @retval HAL state
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
@@ -690,17 +687,17 @@
/**
* @brief Return URB state for a channel
- * @param hhcd : HCD handle
- * @param chnum : Channel number
+ * @param hhcd: HCD handle
+ * @param chnum: Channel number.
* This parameter can be a value from 1 to 15
- * @retval URB state
- * This parameter can be one of the these values:
- * @arg URB_IDLE
- * @arg URB_DONE
- * @arg URB_NOTREADY
- * @arg URB_NYET
- * @arg URB_ERROR
- * @arg URB_STALL
+ * @retval URB state.
+ * This parameter can be one of these values:
+ * URB_IDLE/
+ * URB_DONE/
+ * URB_NOTREADY/
+ * URB_NYET/
+ * URB_ERROR/
+ * URB_STALL
*/
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
@@ -710,8 +707,8 @@
/**
* @brief Return the last host transfer size
- * @param hhcd : HCD handle
- * @param chnum : Channel number
+ * @param hhcd: HCD handle
+ * @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @retval last transfer size in byte
*/
@@ -722,20 +719,20 @@
/**
* @brief Return the Host Channel state
- * @param hhcd : HCD handle
- * @param chnum : Channel number
+ * @param hhcd: HCD handle
+ * @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @retval Host channel state
* This parameter can be one of the these values:
- * @arg HC_IDLE
- * @arg HC_XFRC
- * @arg HC_HALTED
- * @arg HC_NYET
- * @arg HC_NAK
- * @arg HC_STALL
- * @arg HC_XACTERR
- * @arg HC_BBLERR
- * @arg HC_DATATGLERR
+ * HC_IDLE/
+ * HC_XFRC/
+ * HC_HALTED/
+ * HC_NYET/
+ * HC_NAK/
+ * HC_STALL/
+ * HC_XACTERR/
+ * HC_BBLERR/
+ * HC_DATATGLERR/
*/
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
@@ -744,8 +741,8 @@
/**
* @brief Return the current Host frame number
- * @param hhcd : HCD handle
- * @retval current Host frame number
+ * @param hhcd: HCD handle
+ * @retval Current Host frame number
*/
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
{
@@ -754,7 +751,7 @@
/**
* @brief Return the Host enumeration speed
- * @param hhcd : HCD handle
+ * @param hhcd: HCD handle
* @retval Enumeration speed
*/
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
@@ -769,7 +766,7 @@
/**
* @brief This function handles Host Channel IN interrupt requests.
* @param hhcd: HCD handle
- * @param chnum : Channel number
+ * @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @retval none
*/
@@ -908,7 +905,7 @@
/**
* @brief This function handles Host Channel OUT interrupt requests.
* @param hhcd: HCD handle
- * @param chnum : Channel number
+ * @param chnum: Channel number.
* This parameter can be a value from 1 to 15
* @retval none
*/
@@ -1100,7 +1097,7 @@
/**
* @brief This function handles Host Port interrupt requests.
* @param hhcd: HCD handle
- * @retval none
+ * @retval None
*/
static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
{
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hcd.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_hcd.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_hcd.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of HCD HAL module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2c.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2c.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -36,18 +36,18 @@
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream
(+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+ the DMA Tx or Rx Stream
(#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
- (#) Initialize the I2C registers by calling the HAL_I2C_Init() API:
- (+++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_I2C_MspInit(&hi2c) API.
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API.
(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
- (#) For I2C IO and IO MEM operations, three mode of operations are available within this driver :
+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -141,9 +141,9 @@
(+) __HAL_I2C_ENABLE: Enable the I2C peripheral
(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
(+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
- (+) __HAL_I2C_CLEAR_FLAG : Clears the specified I2C pending flag
- (+) __HAL_I2C_ENABLE_IT: Enables the specified I2C interrupt
- (+) __HAL_I2C_DISABLE_IT: Disables the specified I2C interrupt
+ (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
[..]
(@) You can refer to the I2C HAL driver header file for more useful macros
@@ -270,8 +270,8 @@
/**
* @brief Initializes the I2C according to the specified parameters
* in the I2C_InitTypeDef and create the associated handle.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
@@ -348,8 +348,8 @@
/**
* @brief DeInitializes the I2C peripheral.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
@@ -383,8 +383,8 @@
/**
* @brief I2C MSP Init.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
@@ -396,8 +396,8 @@
/**
* @brief I2C MSP DeInit
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
@@ -422,7 +422,7 @@
This subsection provides a set of functions allowing to manage the I2C data
transfers.
- (#) There is two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
after finishing transfer.
@@ -457,7 +457,7 @@
(++) HAL_I2C_Mem_Write_DMA()
(++) HAL_I2C_Mem_Read_DMA()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_I2C_MemTxCpltCallback()
(++) HAL_I2C_MemRxCpltCallback()
(++) HAL_I2C_MasterTxCpltCallback()
@@ -472,8 +472,8 @@
/**
* @brief Transmits in master mode an amount of data in blocking mode.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -570,8 +570,8 @@
/**
* @brief Receives in master mode an amount of data in blocking mode.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -762,8 +762,8 @@
/**
* @brief Transmits in slave mode an amount of data in blocking mode.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@@ -867,8 +867,8 @@
/**
* @brief Receive in slave mode an amount of data in blocking mode
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@@ -959,8 +959,8 @@
/**
* @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -1030,8 +1030,8 @@
/**
* @brief Receive in master mode an amount of data in no-blocking mode with Interrupt
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -1129,8 +1129,8 @@
/**
* @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1182,8 +1182,8 @@
/**
* @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1235,8 +1235,8 @@
/**
* @brief Transmit in master mode an amount of data in no-blocking mode with DMA
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -1311,8 +1311,8 @@
/**
* @brief Receive in master mode an amount of data in no-blocking mode with DMA
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -1398,8 +1398,8 @@
/**
* @brief Transmit in slave mode an amount of data in no-blocking mode with DMA
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1483,8 +1483,8 @@
/**
* @brief Receive in slave mode an amount of data in no-blocking mode with DMA
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1549,8 +1549,8 @@
}
/**
* @brief Write an amount of data in blocking mode to a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -1649,8 +1649,8 @@
/**
* @brief Read an amount of data in blocking mode from a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -1842,8 +1842,8 @@
}
/**
* @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -1915,8 +1915,8 @@
/**
* @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -2018,8 +2018,8 @@
}
/**
* @brief Write an amount of data in no-blocking mode with DMA to a specific memory address
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -2096,8 +2096,8 @@
/**
* @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -2189,8 +2189,8 @@
/**
* @brief Checks if target device is ready for communication.
* @note This function is used with Memory devices
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param Trials: Number of trials
* @param Timeout: Timeout duration
@@ -2299,8 +2299,8 @@
/**
* @brief This function handles I2C event interrupt request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
@@ -2404,8 +2404,8 @@
/**
* @brief This function handles I2C error interrupt request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
@@ -2474,8 +2474,8 @@
/**
* @brief Master Tx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
@@ -2487,8 +2487,8 @@
/**
* @brief Master Rx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
@@ -2499,8 +2499,8 @@
}
/** @brief Slave Tx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
@@ -2512,8 +2512,8 @@
/**
* @brief Slave Rx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
@@ -2525,8 +2525,8 @@
/**
* @brief Memory Tx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
@@ -2538,8 +2538,8 @@
/**
* @brief Memory Rx Transfer completed callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
@@ -2551,8 +2551,8 @@
/**
* @brief I2C error callbacks.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
@@ -2574,7 +2574,7 @@
##### Peripheral State and Errors functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -2583,7 +2583,8 @@
/**
* @brief Returns the I2C state.
- * @param hi2c : I2C handle
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL state
*/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
@@ -2608,8 +2609,8 @@
/**
* @brief Handle TXE flag for Master
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
@@ -2635,8 +2636,8 @@
/**
* @brief Handle BTF flag for Master transmitter
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
@@ -2691,8 +2692,8 @@
/**
* @brief Handle RXNE flag for Master
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
@@ -2759,8 +2760,8 @@
/**
* @brief Handle BTF flag for Master receiver
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
@@ -2835,8 +2836,8 @@
/**
* @brief Handle TXE flag for Slave
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
@@ -2858,8 +2859,8 @@
/**
* @brief Handle BTF flag for Slave transmitter
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
@@ -2881,8 +2882,8 @@
/**
* @brief Handle RXNE flag for Slave
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
@@ -2904,8 +2905,8 @@
/**
* @brief Handle BTF flag for Slave receiver
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
@@ -2927,8 +2928,8 @@
/**
* @brief Handle ADD flag for Slave
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
@@ -2946,8 +2947,8 @@
/**
* @brief Handle STOPF flag for Slave
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
@@ -2981,8 +2982,8 @@
}
/**
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
@@ -3016,8 +3017,8 @@
}
/**
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @retval HAL status
*/
@@ -3077,8 +3078,8 @@
/**
* @brief Master sends target device address for read request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @retval HAL status
*/
@@ -3169,8 +3170,8 @@
/**
* @brief Master sends target device address followed by internal memory address for write request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -3239,8 +3240,8 @@
/**
* @brief Master sends target device address followed by internal memory address for read request.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param DevAddress: Target device address
* @param MemAddress: Internal memory address
* @param MemAddSize: Size of internal memory address
@@ -3622,8 +3623,8 @@
/**
* @brief This function handles I2C Communication Timeout.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param Flag: specifies the I2C flag to check.
* @param Status: The new Flag status (SET or RESET).
* @param Timeout: Timeout duration
@@ -3679,8 +3680,8 @@
/**
* @brief This function handles I2C Communication Timeout for Master addressing phase.
- * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @param Flag: specifies the I2C flag to check.
* @param Timeout: Timeout duration
* @retval HAL status
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2c.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2c.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
@@ -80,7 +80,7 @@
This parameter can be a 7-bit address. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref I2C_general_call_addressing_mode. */
+ This parameter can be a value of @ref I2C_general_call_addressing_mode */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_nostretch_mode */
@@ -268,6 +268,13 @@
/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset I2C handle state
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+
/** @brief Enable or disable the specified I2C interrupts.
* @param __HANDLE__: specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2c_ex.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2c_ex.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2c_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief I2C Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C extension peripheral:
@@ -14,8 +14,8 @@
##### I2C peripheral extension features #####
==============================================================================
- [..] Comparing to other previous devices, the I2C interface for STM32F427X and
- STM32F429X devices contains the following additional features
+ [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/
+ 429xx/439xx devices contains the following additional features :
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
@@ -100,9 +100,9 @@
/**
* @brief Configures I2C Analog noise filter.
- * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
- * @param AnalogFilter : new state of the Analog filter.
+ * @param AnalogFilter: new state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
@@ -139,9 +139,9 @@
/**
* @brief Configures I2C Digital noise filter.
- * @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
- * @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F.
+ * @param DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2c_ex.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2c_ex.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of I2C HAL Extension module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2s.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2s.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -31,7 +31,7 @@
and HAL_I2S_Receive_DMA() APIs:
(+++) Declare a DMA handle structure for the Tx/Rx stream.
(+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream.
(+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
@@ -48,7 +48,7 @@
(+@) External clock source is configured after setting correctly
the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
- (#) Three mode of operations are available within this driver :
+ (#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -56,7 +56,7 @@
(+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
(+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
- *** Interrupt mode IO operation ***
+ *** Interrupt mode IO operation ***
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
@@ -68,11 +68,11 @@
(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
- *** DMA mode IO operation ***
+ *** DMA mode IO operation ***
==============================
[..]
(+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
@@ -84,25 +84,25 @@
(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxCpltCallback
+ add his own code by customization of function pointer HAL_I2S_RxCpltCallback
(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
- (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
- (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
- (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
-
+ (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
+ (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
+ (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
+
*** I2S HAL driver macros list ***
- =============================================
+ =============================================
[..]
Below the list of most used macros in USART HAL driver.
(+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
- (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
+ (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
-
- [..]
+
+ [..]
(@) You can refer to the I2S HAL driver header file for more useful macros
@endverbatim
@@ -195,7 +195,8 @@
/**
* @brief Initializes the I2S according to the specified parameters
* in the I2S_InitTypeDef and create the associated handle.
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
@@ -375,7 +376,8 @@
/**
* @brief DeInitializes the I2S peripheral
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
@@ -390,7 +392,8 @@
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_I2S_MspDeInit(hi2s);
-
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->State = HAL_I2S_STATE_RESET;
/* Release Lock */
@@ -401,7 +404,8 @@
/**
* @brief I2S MSP Init
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
@@ -413,7 +417,8 @@
/**
* @brief I2S MSP DeInit
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
@@ -438,7 +443,7 @@
This subsection provides a set of functions allowing to manage the I2S data
transfers.
- (#) There is two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
after finishing transfer.
@@ -460,7 +465,7 @@
(++) HAL_I2S_Transmit_DMA()
(++) HAL_I2S_Receive_DMA()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_I2S_TxCpltCallback()
(++) HAL_I2S_RxCpltCallback()
(++) HAL_I2S_ErrorCallback()
@@ -471,7 +476,8 @@
/**
* @brief Transmit an amount of data in blocking mode
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pData: a 16-bit pointer to data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
@@ -550,7 +556,8 @@
/**
* @brief Receive an amount of data in blocking mode
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pData: a 16-bit pointer to data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
@@ -635,7 +642,8 @@
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pData: a 16-bit pointer to data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
@@ -700,7 +708,8 @@
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
@@ -767,7 +776,8 @@
/**
* @brief Transmit an amount of data in non-blocking mode with DMA
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pData: a 16-bit pointer to the Transmit data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
@@ -851,7 +861,8 @@
/**
* @brief Receive an amount of data in non-blocking mode with DMA
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
@@ -942,8 +953,9 @@
/**
* @brief Pauses the audio stream playing from the Media.
- * @param hi2s: I2S handle
- * @retval None
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
{
@@ -986,8 +998,9 @@
/**
* @brief Resumes the audio stream playing from the Media.
- * @param hi2s: I2S handle
- * @retval None
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
{
@@ -1037,8 +1050,9 @@
/**
* @brief Resumes the audio stream playing from the Media.
- * @param hi2s: I2S handle
- * @retval None
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
{
@@ -1086,8 +1100,9 @@
/**
* @brief This function handles I2S interrupt request.
- * @param hi2s: I2S handle
- * @retval HAL status
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
*/
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
{
@@ -1106,7 +1121,7 @@
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
- /* I2S Overrun error interrupt occured ---------------------------------*/
+ /* I2S Overrun error interrupt occurred ---------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
@@ -1126,7 +1141,7 @@
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
- /* I2S Underrun error interrupt occured --------------------------------*/
+ /* I2S Underrun error interrupt occurred --------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
@@ -1158,7 +1173,7 @@
tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR;
tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
- /* I2Sext Overrun error interrupt occured ------------------------------*/
+ /* I2Sext Overrun error interrupt occurred ------------------------------*/
if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR))
{
/* Clear I2Sext OVR Flag */
@@ -1184,7 +1199,7 @@
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
- /* I2S Underrun error interrupt occured --------------------------------*/
+ /* I2S Underrun error interrupt occurred --------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
@@ -1211,7 +1226,7 @@
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
- /* I2S Overrun error interrupt occured ---------------------------------*/
+ /* I2S Overrun error interrupt occurred ---------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
@@ -1235,7 +1250,7 @@
tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR;
tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
- /* I2Sext Underrun error interrupt occured -----------------------------*/
+ /* I2Sext Underrun error interrupt occurred -----------------------------*/
if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR))
{
/* Clear I2Sext UDR Flag */
@@ -1256,7 +1271,8 @@
/**
* @brief Tx Transfer Half completed callbacks
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
@@ -1268,7 +1284,8 @@
/**
* @brief Tx Transfer completed callbacks
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
@@ -1280,7 +1297,8 @@
/**
* @brief Rx Transfer half completed callbacks
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
@@ -1292,7 +1310,8 @@
/**
* @brief Rx Transfer completed callbacks
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
@@ -1304,7 +1323,8 @@
/**
* @brief I2S error callbacks
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
@@ -1326,7 +1346,7 @@
##### Peripheral State and Errors functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1335,7 +1355,8 @@
/**
* @brief Return the I2S state
- * @param hi2s : I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval HAL state
*/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
@@ -1345,7 +1366,8 @@
/**
* @brief Return the I2S error code
- * @param hi2s : I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval I2S Error Code
*/
HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
@@ -1359,7 +1381,8 @@
/**
* @brief DMA I2S transmit process complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
@@ -1396,7 +1419,8 @@
/**
* @brief DMA I2S transmit process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1408,7 +1432,8 @@
/**
* @brief DMA I2S receive process complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
@@ -1444,7 +1469,8 @@
/**
* @brief DMA I2S receive process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1456,7 +1482,8 @@
/**
* @brief DMA I2S communication error callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
void I2S_DMAError(DMA_HandleTypeDef *hdma)
@@ -1474,7 +1501,8 @@
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval HAL status
*/
static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
@@ -1517,7 +1545,8 @@
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval HAL status
*/
static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
@@ -1568,7 +1597,8 @@
/**
* @brief This function handles I2S Communication Timeout.
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param Flag: Flag checked
* @param State: Value of the flag expected
* @param Timeout: Duration of the timeout
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2s.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2s.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2s.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
@@ -187,17 +187,25 @@
/** @defgroup I2S_Standard
* @{
*/
-#define I2S_STANDARD_PHILLIPS ((uint32_t)0x00000000)
+#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
#define I2S_STANDARD_MSB ((uint32_t)0x00000010)
#define I2S_STANDARD_LSB ((uint32_t)0x00000020)
#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILLIPS) || \
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
((STANDARD) == I2S_STANDARD_MSB) || \
((STANDARD) == I2S_STANDARD_LSB) || \
((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
((STANDARD) == I2S_STANDARD_PCM_LONG))
+/** @defgroup I2S_Legacy
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -307,6 +315,13 @@
/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset I2S handle state
+ * @param __HANDLE__: specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+
/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2s_ex.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2s_ex.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_i2s_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2S extension peripheral:
@@ -16,21 +16,21 @@
[..]
(#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
data simultaneously using two data lines. Each SPI peripheral has an extended block
- called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3).
+ called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
(#) The extension block is not a full SPI IP, it is used only as I2S slave to
implement full duplex mode. The extension block uses the same clock sources
as its master.
(#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
- -@- Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
+ [..]
+ (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
I2Sx can be I2S2 or I2S3.
- ===============================================================================
##### How to use this driver #####
===============================================================================
[..]
- Three mode of operations are available within this driver :
+ Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -137,7 +137,7 @@
This subsection provides a set of functions allowing to manage the I2S data
transfers.
- (#) There is two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
after finishing transfer.
@@ -156,7 +156,7 @@
(#) No-Blocking mode functions with DMA are :
(++) HAL_I2S_TransmitReceive_DMA()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_I2S_TxCpltCallback()
(++) HAL_I2S_RxCpltCallback()
(++) HAL_I2S_ErrorCallback()
@@ -167,7 +167,8 @@
/**
* @brief Full-Duplex Transmit/Receive data in blocking mode.
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pTxData: a 16-bit pointer to the Transmit data buffer.
* @param pRxData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
@@ -338,7 +339,8 @@
/**
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pTxData: a 16-bit pointer to the Transmit data buffer.
* @param pRxData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
@@ -346,7 +348,6 @@
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
- * @param Timeout: Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
@@ -464,7 +465,8 @@
/**
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @param pTxData: a 16-bit pointer to the Transmit data buffer.
* @param pRxData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
@@ -472,7 +474,6 @@
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
- * @param Timeout: Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
@@ -621,7 +622,8 @@
/**
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
- * @param hi2s: I2S handle
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2s_ex.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2s_ex.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_irda.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_irda.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,24 +2,24 @@
******************************************************************************
* @file stm32f4xx_hal_irda.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral State and Errors functions
- *
- @verbatim
+ * + Initialization and de-initialization methods
+ * + IO operation methods
+ * + Peripheral Control methods
+ *
+ @verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
- The IRDA HAL driver can be used as follow:
+ The IRDA HAL driver can be used as follows:
(#) Declare a IRDA_HandleTypeDef handle structure.
- (#) Initialize the IRDA low level resources by implement the HAL_IRDA_MspInit() API:
+ (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
(##) Enable the USARTx interface clock.
(##) IRDA pins configuration:
(+++) Enable the clock for the IRDA GPIOs.
@@ -47,7 +47,7 @@
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
- (#) Three mode of operations are available within this driver :
+ (#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -175,18 +175,7 @@
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible IRDA frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | IRDA frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
+ please refer to Reference manual for possible IRDA frame formats.
(++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
specification specifies a minimum of 10 ms delay between transmission and
@@ -204,7 +193,8 @@
/**
* @brief Initializes the IRDA mode according to the specified
* parameters in the IRDA_InitTypeDef and create the associated handle.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
@@ -261,7 +251,8 @@
/**
* @brief DeInitializes the IRDA peripheral
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
@@ -292,7 +283,8 @@
/**
* @brief IRDA MSP Init.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
@@ -304,7 +296,8 @@
/**
* @brief IRDA MSP DeInit.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
@@ -333,33 +326,33 @@
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
- (#) There are two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
+ or DMA, These APIs return the HAL status.
The end of the data processing will be indicated through the
dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
will be executed respectivelly at the end of the transmit or Receive process
- The HAL_IRDA_ErrorCallback()user callback will be executed when a communication error is detected
+ The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
(#) Blocking mode API's are :
(++) HAL_IRDA_Transmit()
(++) HAL_IRDA_Receive()
- (#) Non-Blocking mode API's with Interrupt are :
+ (#) Non Blocking mode APIs with Interrupt are :
(++) HAL_IRDA_Transmit_IT()
(++) HAL_IRDA_Receive_IT()
(++) HAL_IRDA_IRQHandler()
- (#) No-Blocking mode functions with DMA are :
+ (#) Non Blocking mode functions with DMA are :
(++) HAL_IRDA_Transmit_DMA()
(++) HAL_IRDA_Receive_DMA()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_IRDA_TxCpltCallback()
(++) HAL_IRDA_RxCpltCallback()
(++) HAL_IRDA_ErrorCallback()
@@ -370,7 +363,8 @@
/**
* @brief Sends an amount of data in blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Specify timeout value
@@ -461,7 +455,8 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @param Timeout: Specify timeout value
@@ -554,7 +549,8 @@
/**
* @brief Send an amount of data in non blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -608,7 +604,8 @@
/**
* @brief Receives an amount of data in non blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @retval HAL status
@@ -663,7 +660,8 @@
/**
* @brief Sends an amount of data in non blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -725,7 +723,8 @@
/**
* @brief Receives an amount of data in non blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
@@ -786,7 +785,8 @@
/**
* @brief This function handles IRDA interrupt request.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
@@ -795,7 +795,7 @@
tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE);
tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE);
- /* IRDA parity error interrupt occured -------------------------------------*/
+ /* IRDA parity error interrupt occurred -------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_PE);
@@ -804,7 +804,7 @@
tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE);
tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
- /* IRDA frame error interrupt occured --------------------------------------*/
+ /* IRDA frame error interrupt occurred --------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_FE);
@@ -813,7 +813,7 @@
tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE);
tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
- /* IRDA noise error interrupt occured --------------------------------------*/
+ /* IRDA noise error interrupt occurred --------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_NE);
@@ -822,7 +822,7 @@
tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE);
tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
- /* IRDA Over-Run interrupt occured -----------------------------------------*/
+ /* IRDA Over-Run interrupt occurred -----------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_ORE);
@@ -858,7 +858,8 @@
/**
* @brief Tx Transfer complete callbacks.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
@@ -870,7 +871,8 @@
/**
* @brief Rx Transfer complete callbacks.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
@@ -882,7 +884,8 @@
/**
* @brief IRDA error callbacks.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
@@ -905,9 +908,9 @@
==============================================================================
[..]
This subsection provides a set of functions allowing to return the State of IrDA
- communication process, return Peripheral Errors occured during communication process
+ communication process and also return Peripheral Errors occurred during communication process
(+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
- (+) HAL_IRDA_GetError() check in run-time errors that could be occured durung communication.
+ (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.
@endverbatim
* @{
@@ -915,7 +918,8 @@
/**
* @brief Returns the IRDA state.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL state
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
@@ -949,10 +953,14 @@
hirda->TxXferCount = 0;
+ /* Disable the DMA transfer for transmit request by setting the DMAT bit
+ in the IRDA CR3 register */
+ hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);
+
/* Wait for IRDA TC Flag */
if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, IRDA_TIMEOUT_VALUE) != HAL_OK)
{
- /* Timeout Occured */
+ /* Timeout occurred */
hirda->State = HAL_IRDA_STATE_TIMEOUT;
HAL_IRDA_ErrorCallback(hirda);
}
@@ -982,7 +990,11 @@
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hirda->RxXferCount = 0;
-
+
+ /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+ in the IRDA CR3 register */
+ hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
+
if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX;
@@ -1014,7 +1026,8 @@
/**
* @brief This function handles IRDA Communication Timeout.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param Flag: specifies the IRDA flag to check.
* @param Status: The new Flag status (SET or RESET).
* @param Timeout: Timeout duration
@@ -1082,7 +1095,8 @@
/**
* @brief Send an amount of data in non blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
@@ -1093,9 +1107,6 @@
tmp1 = hirda->State;
if((tmp1 == HAL_IRDA_STATE_BUSY_TX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX))
{
- /* Process Locked */
- __HAL_LOCK(hirda);
-
if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
tmp = (uint16_t*) hirda->pTxBuffPtr;
@@ -1133,17 +1144,12 @@
hirda->State = HAL_IRDA_STATE_READY;
}
- /* Call the Process Unlocked before calling the Tx call back API to give the possibiity to
- start again the Transmission under the Tx call back API */
- __HAL_UNLOCK(hirda);
-
+
HAL_IRDA_TxCpltCallback(hirda);
return HAL_OK;
}
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
+
return HAL_OK;
}
else
@@ -1154,7 +1160,8 @@
/**
* @brief Receives an amount of data in non blocking mode.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
@@ -1165,9 +1172,6 @@
tmp1 = hirda->State;
if((tmp1 == HAL_IRDA_STATE_BUSY_RX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX))
{
- /* Process Locked */
- __HAL_LOCK(hirda);
-
if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
tmp = (uint16_t*) hirda->pRxBuffPtr;
@@ -1215,18 +1219,10 @@
hirda->State = HAL_IRDA_STATE_READY;
}
- /* Call the Process Unlocked before calling the Rx call back API to give the possibiity to
- start again the receiption under the Rx call back API */
- __HAL_UNLOCK(hirda);
-
HAL_IRDA_RxCpltCallback(hirda);
return HAL_OK;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
return HAL_OK;
}
else
@@ -1237,7 +1233,8 @@
/**
* @brief Configures the IRDA peripheral.
- * @param hirda: IRDA handle
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_irda.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_irda.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_irda.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of IRDA HAL module. ****************************************************************************** * @attention @@ -233,22 +233,33 @@ #define IRDA_IT_TC ((uint32_t)0x10000040) #define IRDA_IT_RXNE ((uint32_t)0x10000020) #define IRDA_IT_IDLE ((uint32_t)0x10000010) - + #define IRDA_IT_LBD ((uint32_t)0x20000040) -#define IRDA_IT_CTS ((uint32_t)0x30000400) +#define IRDA_IT_CTS ((uint32_t)0x30000400) #define IRDA_IT_ERR ((uint32_t)0x30000001) /** * @} */ - + /** * @} */ /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset IRDA handle state + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET) + +/** @brief Flushs the IRDA DR register + * @param __HANDLE__: specifies the IRDA Handle. + */ +#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) + /** @brief Checks whether the specified IRDA flag is set or not. * @param __HANDLE__: specifies the USART Handle. * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_iwdg.c Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_iwdg.c Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_iwdg.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: @@ -142,7 +142,8 @@ /** * @brief Initializes the IWDG according to the specified * parameters in the IWDG_InitTypeDef and creates the associated handle. - * @param hiwdg: IWDG handle + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) @@ -206,7 +207,8 @@ /** * @brief Initializes the IWDG MSP. - * @param hiwdg: IWDG handle + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval None */ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) @@ -237,7 +239,8 @@ /** * @brief Starts the IWDG. - * @param hiwdg: IWDG handle + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) @@ -266,7 +269,8 @@ /** * @brief Refreshes the IWDG. - * @param hiwdg: IWDG handle + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) @@ -314,7 +318,8 @@ /** * @brief Returns the IWDG state. - * @param hiwdg: IWDG handle + * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval HAL state */ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_iwdg.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_iwdg.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_iwdg.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention @@ -167,6 +167,12 @@ /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset IWDG handle state + * @param __HANDLE__: IWDG handle + * @retval None + */ +#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET) + /** * @brief Enables the IWDG peripheral. * @param __HANDLE__: IWDG handle
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_ltdc.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_ltdc.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_ltdc.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief LTDC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LTDC peripheral:
@@ -17,12 +17,12 @@
##### How to use this driver #####
==============================================================================
[..]
- (#) Program the required configuration through following parameters:
+ (#) Program the required configuration through the following parameters:
the LTDC timing, the horizontal and vertical polarity,
the pixel clock polarity, Data Enable polarity and the LTDC background color value
using HAL_LTDC_Init() function
- (#) Program the required configuration through following parameters:
+ (#) Program the required configuration through the following parameters:
the pixel format, the blending factors, input alpha value, the window size
and the image size using HAL_LTDC_ConfigLayer() function for foreground
or/and background layer.
@@ -38,7 +38,7 @@
(#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineInterrupt()
function
- (#) If needed, Reconfigure and change the pixel format value, the alpha value
+ (#) If needed, reconfigure and change the pixel format value, the alpha value
value, the window size, the window position and the layer start address
for foreground or/and background layer using respectively the following
functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
@@ -57,10 +57,10 @@
(+) __HAL_LTDC_LAYER_DISABLE: Disable the LTDC Layer.
(+) __HAL_LTDC_RELOAD_CONFIG: Reload Layer Configuration.
(+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
- (+) __HAL_LTDC_CLEAR_FLAG: Clears the LTDC pending flags.
- (+) __HAL_LTDC_ENABLE_IT: Enables the specified LTDC interrupts.
- (+) __HAL_LTDC_DISABLE_IT: Disables the specified LTDC interrupts.
- (+) __HAL_LTDC_GET_IT_SOURCE: Checks whether the specified LTDC interrupt has occurred or not.
+ (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
+ (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
+ (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
+ (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
[..]
(@) You can refer to the LTDC HAL driver header file for more useful macros
@@ -421,9 +421,9 @@
(+) Enable / Disable the C-LUT.
(+) Update the layer position.
(+) Update the layer size.
- (+) update pixel format on the fly the.
- (+) update transparency on the fly the.
- (+) update address on the fly.
+ (+) Update pixel format on the fly.
+ (+) Update transparency on the fly.
+ (+) Update address on the fly.
@endverbatim
* @{
@@ -436,7 +436,7 @@
* the configuration information for the LTDC.
* @param pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains
* the configuration information for the Layer.
- * @param LayerIdx: LTDC Layer index
+ * @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -485,10 +485,10 @@
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param RGBValue: the color key value
- * @param LayerIdx: LTDC Layer index
+ * @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
{
@@ -523,10 +523,10 @@
* the configuration information for the LTDC.
* @param pCLUT: pointer to the color lookup table address.
* @param CLUTSize: the color lookup table size.
- * @param LayerIdx: LTDC Layer index
+ * @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
{
@@ -566,10 +566,10 @@
* @brief Enable the color keying.
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LayerIdx: LTDC Layer index
+ * @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
@@ -601,10 +601,10 @@
* @brief Disable the color keying.
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LayerIdx: LTDC Layer index
+ * @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
@@ -636,10 +636,10 @@
* @brief Enable the color lookup table.
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LayerIdx: LTDC Layer index
+ * @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
@@ -672,10 +672,10 @@
* @brief Disable the color lookup table.
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LayerIdx: LTDC Layer index
+ * @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
@@ -708,7 +708,7 @@
* @brief Enables Dither.
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)
@@ -735,7 +735,7 @@
* @brief Disables Dither.
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)
@@ -764,10 +764,10 @@
* the configuration information for the LTDC.
* @param XSize: LTDC Pixel per line
* @param YSize: LTDC Line number
- * @param LayerIdx: LTDC Layer index
+ * @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
{
@@ -826,10 +826,10 @@
* the configuration information for the LTDC.
* @param X0: LTDC window X offset
* @param Y0: LTDC window Y offset
- * @param LayerIdx: LTDC Layer index
+ * @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
{
@@ -882,7 +882,7 @@
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
{
@@ -924,10 +924,10 @@
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param Alpha: new alpha value.
- * @param LayerIdx: LTDC Layer index
+ * @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
{
@@ -971,7 +971,7 @@
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
{
@@ -1012,7 +1012,7 @@
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param Line: Line Interrupt Position.
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)
{
@@ -1091,7 +1091,7 @@
* @param hltdc : Pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param pLayerCfg: Pointer LTDC Layer Configuration strusture
- * @param LayerIdx: LTDC Layer index
+ * @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values: 0 or 1
* @retval None
*/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_ltdc.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_ltdc.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_ltdc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of LTDC HAL module.
******************************************************************************
* @attention
@@ -59,9 +59,9 @@
/* Exported types ------------------------------------------------------------*/
#define MAX_LAYER 2
-
+
/**
- * @brief LTDC color structure definition
+ * @brief LTDC color structure definition
*/
typedef struct
{
@@ -70,15 +70,15 @@
uint8_t Green; /*!< Configures the green value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
+
uint8_t Red; /*!< Configures the red value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-
- uint8_t Reserved; /*!< Reserved 0xFF */
-} LTDC_ColorTypeDef;
-
+
+ uint8_t Reserved; /*!< Reserved 0xFF */
+} LTDC_ColorTypeDef;
+
/**
- * @brief LTDC Init structure definition
+ * @brief LTDC Init structure definition
*/
typedef struct
{
@@ -95,7 +95,7 @@
This parameter can be one of value of @ref LTDC_PC_POLARITY */
uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t VerticalSync; /*!< configures the number of Vertical synchronization heigh.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
@@ -104,42 +104,41 @@
This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch heigh.
- This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
-
- uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. This parameter
- This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
+ This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
- uint32_t AccumulatedActiveH; /*!< configures the accumulated active heigh. This parameter
+ uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
+ This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
+
+ uint32_t AccumulatedActiveH; /*!< configures the accumulated active heigh.
This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
- uint32_t TotalWidth; /*!< configures the total width. This parameter
+ uint32_t TotalWidth; /*!< configures the total width.
This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
- uint32_t TotalHeigh; /*!< configures the total heigh. This parameter
+ uint32_t TotalHeigh; /*!< configures the total heigh.
This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
-
+
LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
-
} LTDC_InitTypeDef;
/**
- * @brief LTDC Layer structure definition
+ * @brief LTDC Layer structure definition
*/
typedef struct
{
uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-
+
uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-
+
uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
+
uint32_t PixelFormat; /*!< Specifies the pixel format.
This parameter can be one of value of @ref LTDC_Pixelformat */
@@ -154,60 +153,58 @@
uint32_t BlendingFactor2; /*!< Select the blending factor 2.
This parameter can be one of value of @ref LTDC_BlendingFactor2 */
-
+
uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
-
+
uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
-
+
LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
-
} LTDC_LayerCfgTypeDef;
/**
- * @brief HAL LTDC State structures definition
- */
+ * @brief HAL LTDC State structures definition
+ */
typedef enum
{
- HAL_LTDC_STATE_RESET = 0x00, /*!< LTDC not yet initialized or disabled */
+ HAL_LTDC_STATE_RESET = 0x00, /*!< LTDC not yet initialized or disabled */
HAL_LTDC_STATE_READY = 0x01, /*!< LTDC initialized and ready for use */
- HAL_LTDC_STATE_BUSY = 0x02, /*!< LTDC internal process is ongoing */
- HAL_LTDC_STATE_TIMEOUT = 0x03, /*!< LTDC Timeout state */
- HAL_LTDC_STATE_ERROR = 0x04 /*!< LTDC state error */
-
+ HAL_LTDC_STATE_BUSY = 0x02, /*!< LTDC internal process is ongoing */
+ HAL_LTDC_STATE_TIMEOUT = 0x03, /*!< LTDC Timeout state */
+ HAL_LTDC_STATE_ERROR = 0x04 /*!< LTDC state error */
}HAL_LTDC_StateTypeDef;
/**
- * @brief LTDC handle Structure definition
- */
+ * @brief LTDC handle Structure definition
+ */
typedef struct
-{
+{
LTDC_TypeDef *Instance; /*!< LTDC Register base address */
-
+
LTDC_InitTypeDef Init; /*!< LTDC parameters */
-
+
LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */
-
- HAL_LockTypeDef Lock; /*!< LTDC Lock */
-
+
+ HAL_LockTypeDef Lock; /*!< LTDC Lock */
+
__IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */
- __IO uint32_t ErrorCode; /*!< LTDC Error code */
-
-} LTDC_HandleTypeDef;
+ __IO uint32_t ErrorCode; /*!< LTDC Error code */
+
+} LTDC_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup LTDC_Exported_Constants
* @{
*/
-
+
/** @defgroup LTDC_Layer
* @{
*/
-#define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER)
+#define IS_LTDC_LAYER(LAYER) ((LAYER) <= MAX_LAYER)
/**
* @}
*/
@@ -331,7 +328,7 @@
*/
#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001) /*!< RGB888 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002) /*!< RGB565 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002) /*!< RGB565 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005) /*!< L8 LTDC pixel format */
@@ -388,7 +385,7 @@
/** @defgroup LTDC_Interrupts
* @{
- */
+ */
#define LTDC_IT_LI LTDC_IER_LIE
#define LTDC_IT_FU LTDC_IER_FUIE
#define LTDC_IT_TE LTDC_IER_TERRIE
@@ -411,13 +408,20 @@
((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
/**
* @}
- */
+ */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset LTDC handle state
+ * @param __HANDLE__: specifies the LTDC handle.
+ * @retval None
+ */
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
+
/**
* @brief Enable the LTDC.
* @param __HANDLE__: LTDC handle
@@ -443,7 +447,6 @@
#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((__HAL_LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
-
/**
* @brief Disable the LTDC Layer.
* @param __HANDLE__: LTDC handle
@@ -525,10 +528,10 @@
* @retval The state of INTERRUPT (SET or RESET).
*/
#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
-
-/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions *******************************/
+/* Exported functions --------------------------------------------------------*/
+
+/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
@@ -536,10 +539,10 @@
void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc);
-/* IO operation functions *******************************************************/
+/* IO operation functions *****************************************************/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
-/* Peripheral Control functions *************************************************/
+/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
@@ -556,7 +559,7 @@
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
-/* Peripheral State functions ***************************************************/
+/* Peripheral State functions *************************************************/
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_nand.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_nand.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_nand.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
@@ -125,7 +125,8 @@
/**
* @brief Perform NAND memory Initialization sequence
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param ComSpace_Timing: pointer to Common space timing structure
* @param AttSpace_Timing: pointer to Attribute space timing structure
* @retval HAL status
@@ -164,7 +165,8 @@
/**
* @brief Perform NAND memory De-Initialization sequence
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
@@ -186,7 +188,8 @@
/**
* @brief NAND MSP Init
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval None
*/
__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
@@ -198,7 +201,8 @@
/**
* @brief NAND MSP DeInit
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval None
*/
__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
@@ -211,7 +215,8 @@
/**
* @brief This function handles NAND device interrupt request.
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval HAL status
*/
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
@@ -260,7 +265,8 @@
/**
* @brief NAND interrupt feature callback
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval None
*/
__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
@@ -291,7 +297,8 @@
/**
* @brief Read the NAND memory electronic signature
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param pNAND_ID: NAND ID structure
* @retval HAL status
*/
@@ -346,7 +353,8 @@
/**
* @brief NAND memory reset
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
@@ -392,7 +400,8 @@
/**
* @brief Read Page(s) from NAND memory block
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer : pointer to destination read buffer
* @param NumPageToRead : number of pages to read from block
@@ -479,7 +488,8 @@
/**
* @brief Write Page(s) to NAND memory block
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer : pointer to source buffer to write
* @param NumPageToWrite : number of pages to write to block
@@ -580,7 +590,8 @@
/**
* @brief Read Spare area(s) from NAND memory
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer: pointer to source buffer to write
* @param NumSpareAreaToRead: Number of spare area to read
@@ -666,7 +677,8 @@
/**
* @brief Write Spare area(s) to NAND memory
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer : pointer to source buffer to write
* @param NumSpareAreaTowrite : number of spare areas to write to block
@@ -767,7 +779,8 @@
/**
* @brief NAND memory Block erase
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @retval HAL status
*/
@@ -824,7 +837,8 @@
/**
* @brief NAND memory read status
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval NAND status
*/
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
@@ -864,7 +878,8 @@
/**
* @brief Increment the NAND memory address
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param pAddress: pointer to NAND adress structure
* @retval The new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
@@ -921,7 +936,8 @@
/**
* @brief Enables dynamically NAND ECC feature.
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
@@ -947,7 +963,8 @@
/**
* @brief Disables dynamically FMC_NAND ECC feature.
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
@@ -972,7 +989,8 @@
/**
* @brief Disables dynamically NAND ECC feature.
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @param ECCval: pointer to ECC value
* @param Timeout: maximum timeout to wait
* @retval HAL status
@@ -1012,7 +1030,7 @@
##### NAND State functions #####
==============================================================================
[..]
- This subsection permit to get in run-time the status of the NAND controller
+ This subsection permits to get in run-time the status of the NAND controller
and the data flow.
@endverbatim
@@ -1021,7 +1039,8 @@
/**
* @brief return the NAND state
- * @param hnand: pointer to NAND handle
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
* @retval HAL state
*/
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_nand.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_nand.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_nand.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_NAND_H
@@ -62,70 +62,67 @@
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-/* Exported typedef ----------------------------------------------------------*/
+/* Exported typedef ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/**
- * @brief HAL NAND State structures definition
- */
+ * @brief HAL NAND State structures definition
+ */
typedef enum
{
HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
-
}HAL_NAND_StateTypeDef;
/**
- * @brief NAND Memory electronic signature Structure definition
+ * @brief NAND Memory electronic signature Structure definition
*/
typedef struct
{
- /*<! NAND memory electronic signature maker and device IDs */
-
+ /*<! NAND memory electronic signature maker and device IDs */
+
uint8_t Maker_Id;
-
+
uint8_t Device_Id;
-
+
uint8_t Third_Id;
-
+
uint8_t Fourth_Id;
-
}NAND_IDTypeDef;
/**
- * @brief NAND Memory address Structure definition
+ * @brief NAND Memory address Structure definition
*/
typedef struct
{
- uint16_t Page; /*!< NAND memory Page address */
-
- uint16_t Zone; /*!< NAND memory Zone address */
-
+ uint16_t Page; /*!< NAND memory Page address */
+
+ uint16_t Zone; /*!< NAND memory Zone address */
+
uint16_t Block; /*!< NAND memory Block address */
-
+
}NAND_AddressTypedef;
/**
- * @brief NAND Memory info Structure definition
+ * @brief NAND Memory info Structure definition
*/
typedef struct
{
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
-
- uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
-
- uint32_t BlockSize; /*!< NAND memory block size number of pages */
-
+
+ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
+
+ uint32_t BlockSize; /*!< NAND memory block size number of pages */
+
uint32_t BlockNbr; /*!< NAND memory number of blocks */
-
+
uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
-
}NAND_InfoTypeDef;
/**
- * @brief NAND handle Structure definition
+ * @brief NAND handle Structure definition
*/
typedef struct
{
@@ -133,12 +130,11 @@
FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
- HAL_LockTypeDef Lock; /*!< NAND locking object */
+ HAL_LockTypeDef Lock; /*!< NAND locking object */
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
-
+
NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
-
}NAND_HandleTypeDef;
@@ -170,9 +166,16 @@
*/
/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset NAND handle state
+ * @param __HANDLE__: specifies the NAND handle.
+ * @retval None
+ */
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+
/**
* @brief NAND memory address computation.
- * @param __ADDRESS__: NAND memory address.
+ * @param __ADDRESS__: NAND memory address.
* @param __HANDLE__ : NAND handle.
* @retval NAND Raw address value
*/
@@ -180,7 +183,7 @@
/**
* @brief NAND memory address cycling.
- * @param __ADDRESS__: NAND memory address.
+ * @param __ADDRESS__: NAND memory address.
* @retval NAND address cycling value.
*/
#define ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__)& 0xFF) /* 1st addressing cycle */
@@ -190,7 +193,7 @@
/* Exported functions --------------------------------------------------------*/
-/* Initialization/de-initialization functions **********************************/
+/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
@@ -198,7 +201,7 @@
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
-/* IO operation functions *****************************************************/
+/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
@@ -209,12 +212,12 @@
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
-/* NAND Control functions ******************************************************/
+/* NAND Control functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
-/* NAND State functions *********************************************************/
+/* NAND State functions *******************************************************/
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_nor.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_nor.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_nor.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
@@ -126,7 +126,8 @@
/**
* @brief Perform the NOR memory Initialization sequence
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @param Timing: pointer to NOR control timing structure
* @param ExtTiming: pointer to NOR extended mode timing structure
* @retval HAL status
@@ -165,7 +166,8 @@
/**
* @brief Perform NOR memory De-Initialization sequence
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
@@ -187,7 +189,8 @@
/**
* @brief NOR MSP Init
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @retval None
*/
__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
@@ -199,7 +202,8 @@
/**
* @brief NOR MSP DeInit
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @retval None
*/
__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
@@ -211,7 +215,8 @@
/**
* @brief NOR BSP Wait fro Ready/Busy signal
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @param Timeout: Maximum timeout value
* @retval None
*/
@@ -242,7 +247,8 @@
/**
* @brief Read NOR flash IDs
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @param pNOR_ID : pointer to NOR ID structure
* @retval HAL status
*/
@@ -282,7 +288,8 @@
/**
* @brief Returns the NOR memory to Read mode.
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
@@ -309,7 +316,8 @@
/**
* @brief Read data from NOR memory
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @param pAddress: pointer to Device address
* @param pData : pointer to read data
* @retval HAL status
@@ -347,7 +355,8 @@
/**
* @brief Program data to NOR memory
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @param pAddress: Device address
* @param pData : pointer to the data to write
* @retval HAL status
@@ -385,7 +394,8 @@
/**
* @brief Reads a block of data from the FMC NOR memory.
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @param uwAddress: NOR memory internal address to read from.
* @param pData: pointer to the buffer that receives the data read from the
* NOR memory.
@@ -431,7 +441,8 @@
/**
* @brief Writes a half-word buffer to the FMC NOR memory. This function
* must be used only with S29GL128P NOR memory.
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @param uwAddress: NOR memory internal address from which the data
* @param pData: pointer to source data buffer.
* @param uwBufferSize: number of Half words to write. The maximum allowed
@@ -493,7 +504,8 @@
/**
* @brief Erase the specified block of the NOR memory
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @param BlockAddress : Block to erase address
* @param Address: Device address
* @retval HAL status
@@ -532,7 +544,8 @@
/**
* @brief Erase the entire NOR chip.
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @param Address : Device address
* @retval HAL status
*/
@@ -569,7 +582,8 @@
/**
* @brief Read NOR flash CFI IDs
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @param pNOR_CFI : pointer to NOR CFI IDs structure
* @retval HAL status
*/
@@ -626,7 +640,8 @@
/**
* @brief Enables dynamically NOR write operation.
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
@@ -648,7 +663,8 @@
/**
* @brief Disables dynamically NOR write operation.
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
@@ -683,7 +699,7 @@
##### NOR State functions #####
==============================================================================
[..]
- This subsection permit to get in run-time the status of the NOR controller
+ This subsection permits to get in run-time the status of the NOR controller
and the data flow.
@endverbatim
@@ -692,7 +708,8 @@
/**
* @brief return the NOR controller state
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @retval NOR controller state
*/
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
@@ -702,7 +719,8 @@
/**
* @brief Returns the NOR operation status.
- * @param hnor: pointer to NOR handle
+ * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * the configuration information for NOR module.
* @param Address: Device address
* @param Timeout: NOR progamming Timeout
* @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_nor.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_nor.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_nor.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
@@ -62,7 +62,7 @@
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-/* Exported typedef ----------------------------------------------------------*/
+/* Exported typedef ----------------------------------------------------------*/
/**
* @brief HAL SRAM State structures definition
*/
@@ -71,10 +71,9 @@
HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
- HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
- HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
-
-}HAL_NOR_StateTypeDef;
+ HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
+ HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
+}HAL_NOR_StateTypeDef;
/**
* @brief FMC NOR Status typedef
@@ -85,8 +84,7 @@
NOR_ONGOING,
NOR_ERROR,
NOR_TIMEOUT
-
-}NOR_StatusTypedef;
+}NOR_StatusTypedef;
/**
* @brief FMC NOR ID typedef
@@ -94,19 +92,17 @@
typedef struct
{
uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
-
- uint16_t Device_Code1;
-
- uint16_t Device_Code2;
-
- uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
+
+ uint16_t Device_Code1;
+
+ uint16_t Device_Code2;
+
+ uint16_t Device_Code3; /*!< Defines the devices' codes used to identify the memory.
These codes can be accessed by performing read operations with specific
control signals and addresses set.They can also be accessed by issuing
- an Auto Select command */
-
+ an Auto Select command */
}NOR_IDTypeDef;
-
/**
* @brief FMC NOR CFI typedef
*/
@@ -115,32 +111,31 @@
/*!< Defines the information stored in the memory's Common flash interface
which contains a description of various electrical and timing parameters,
density information and functions supported by the memory */
-
- uint16_t CFI_1;
-
- uint16_t CFI_2;
-
- uint16_t CFI_3;
-
- uint16_t CFI_4;
-
+
+ uint16_t CFI_1;
+
+ uint16_t CFI_2;
+
+ uint16_t CFI_3;
+
+ uint16_t CFI_4;
}NOR_CFITypeDef;
/**
- * @brief NOR handle Structure definition
+ * @brief NOR handle Structure definition
*/
typedef struct
{
- FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
-
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
-
+
FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
- HAL_LockTypeDef Lock; /*!< NOR locking object */
-
+ HAL_LockTypeDef Lock; /*!< NOR locking object */
+
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
-
+
}NOR_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
@@ -173,6 +168,13 @@
*/
/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset NOR handle state
+ * @param __HANDLE__: specifies the NOR handle.
+ * @retval None
+ */
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+
/**
* @brief NOR memory address shifting.
* @param __ADDRESS__: NOR memory address
@@ -194,14 +196,14 @@
/* Exported functions --------------------------------------------------------*/
-/* Initialization/de-initialization functions **********************************/
+/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
-/* I/O operation functions *****************************************************/
+/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
@@ -214,11 +216,11 @@
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
-/* NOR Control functions *******************************************************/
+/* NOR Control functions *****************************************************/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
-/* NOR State functions **********************************************************/
+/* NOR State functions ********************************************************/
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pccard.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pccard.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pccard.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief PCCARD HAL module driver.
* This file provides a generic firmware to drive PCCARD memories mounted
* as external device.
@@ -116,7 +116,8 @@
/**
* @brief Perform the PCCARD memory Initialization sequence
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @param ComSpaceTiming: Common space timing structure
* @param AttSpaceTiming: Attribute space timing structure
* @param IOSpaceTiming: IO space timing structure
@@ -163,7 +164,8 @@
/**
* @brief Perform the PCCARD memory De-initialization sequence
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
@@ -185,7 +187,8 @@
/**
* @brief PCCARD MSP Init
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval None
*/
__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
@@ -197,7 +200,8 @@
/**
* @brief PCCARD MSP DeInit
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval None
*/
__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
@@ -227,8 +231,9 @@
/**
* @brief Read Compact Flash's ID.
- * @param hpccard : pointer to PCCARD handle
- * @param CF_ID: Compact flash ID structure.
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param CompactFlash_ID: Compact flash ID structure.
* @param pStatus: pointer to compact flash status
* @retval HAL status
*
@@ -289,10 +294,11 @@
/**
* @brief Read sector from PCCARD memory
- * @param hpccard : pointer to PCCARD handle
- * @param pBuffer : pointer to destination read buffer
- * @param SectorAddress : Sector address to read
- * @param pStatus : pointer to CF status
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param pBuffer: pointer to destination read buffer
+ * @param SectorAddress: Sector address to read
+ * @param pStatus: pointer to CF status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CF_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
@@ -364,10 +370,11 @@
/**
* @brief Write sector to PCCARD memory
- * @param hpccard : pointer to PCCARD handle
- * @param pBuffer : pointer to source write buffer
- * @param SectorAddress : Sector address to write
- * @param pStatus : pointer to CF status
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param pBuffer: pointer to source write buffer
+ * @param SectorAddress: Sector address to write
+ * @param pStatus: pointer to CF status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CF_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
@@ -437,9 +444,10 @@
/**
* @brief Erase sector from PCCARD memory
- * @param hpccard : pointer to PCCARD handle
- * @param SectorAddress : Sector address to erase
- * @param pStatus : pointer to CF status
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @param SectorAddress: Sector address to erase
+ * @param pStatus: pointer to CF status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CF_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
@@ -495,7 +503,8 @@
/**
* @brief Reset the PCCARD memory
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CF_Reset(PCCARD_HandleTypeDef *hpccard)
@@ -533,7 +542,8 @@
/**
* @brief This function handles PCCARD device interrupt request.
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval HAL status
*/
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
@@ -582,7 +592,8 @@
/**
* @brief PCCARD interrupt feature callback
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval None
*/
__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
@@ -604,7 +615,7 @@
##### PCCARD State functions #####
==============================================================================
[..]
- This subsection permit to get in run-time the status of the PCCARD controller
+ This subsection permits to get in run-time the status of the PCCARD controller
and the data flow.
@endverbatim
@@ -613,8 +624,9 @@
/**
* @brief return the PCCARD controller state
- * @param hpccard : pointer to PCCARD handle
- * @retval PCCARD controller state
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
+ * @retval HAL state
*/
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
{
@@ -623,7 +635,8 @@
/**
* @brief Get the compact flash memory status
- * @param hpccard: PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval New status of the CF operation. This parameter can be:
* - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
* a Timeout error
@@ -659,7 +672,8 @@
/**
* @brief Reads the Compact Flash memory status using the Read status command
- * @param hpccard : pointer to PCCARD handle
+ * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * the configuration information for PCCARD module.
* @retval The status of the Compact Flash memory. This parameter can be:
* - CompactFlash_BUSY: when memory is busy
* - CompactFlash_READY: when memory is ready for the next operation
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pccard.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pccard.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pccard.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of PCCARD HAL module. ****************************************************************************** * @attention @@ -138,6 +138,13 @@ /** * @} */ +/* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset PCCARD handle state + * @param __HANDLE__: specifies the PCCARD handle. + * @retval None + */ +#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET) /* Exported functions --------------------------------------------------------*/ /* Initialization/de-initialization functions **********************************/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pcd.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pcd.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -597,7 +597,7 @@
}
/**
* @brief Setup stage callback
- * @param hpcd: ppp handle
+ * @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
@@ -694,7 +694,7 @@
/**
* @brief Disconnection event callbacks
- * @param hpcd: ppp handle
+ * @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
@@ -726,8 +726,6 @@
/**
* @brief Send an amount of data in blocking mode
* @param hpcd: PCD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
@@ -741,8 +739,6 @@
/**
* @brief Send an amount of data in blocking mode
* @param hpcd: PCD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
@@ -1025,7 +1021,7 @@
/**
* @brief Update FIFO configuration
* @param hpcd: PCD handle
- * @retval status
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
@@ -1069,7 +1065,7 @@
/**
* @brief Update FIFO configuration
* @param hpcd: PCD handle
- * @retval status
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
{
@@ -1083,7 +1079,7 @@
/**
* @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling
* @param hpcd: PCD handle
- * @retval status
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
@@ -1100,7 +1096,7 @@
/**
* @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling
* @param hpcd: PCD handle
- * @retval status
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
@@ -1122,7 +1118,7 @@
##### Peripheral State functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1131,7 +1127,7 @@
/**
* @brief Return the PCD state
- * @param hpcd : PCD handle
+ * @param hpcd: PCD handle
* @retval HAL state
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
@@ -1146,7 +1142,7 @@
* @brief DCD_WriteEmptyTxFifo
* check FIFO for the next packet to be loaded
* @param hpcd: PCD handle
- * @retval status
+ * @retval HAL status
*/
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pcd.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pcd.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pwr.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pwr.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -276,6 +276,9 @@
{
__HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD);
}
+ /* Clear the edge trigger for the EXTI Line 16 (PVD) */
+ EXTI->RTSR &= ~EXTI_RTSR_TR16;
+ EXTI->FTSR &= ~EXTI_FTSR_TR16;
/* Configure the rising edge */
if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\
(sConfigPVD->Mode == PWR_MODE_IT_RISING))
@@ -312,7 +315,7 @@
/**
* @brief Enables the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
* @retval None
@@ -326,7 +329,7 @@
/**
* @brief Disables the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
* @retval None
@@ -363,10 +366,7 @@
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
- /* Disable SysTick Timer */
- SysTick->CTRL &= 0xFE;
-
+
/* Select SLEEP mode entry -------------------------------------------------*/
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
@@ -376,11 +376,10 @@
else
{
/* Request Wait For Event */
+ __SEV();
+ __WFE();
__WFE();
}
-
- /* Enable SysTick Timer */
- SysTick->CTRL |= 0x01;
}
/**
@@ -490,8 +489,8 @@
/**
* @brief PWR PVD interrupt callback
- * @param none
- * @retval none
+ * @param None
+ * @retval None
*/
__weak void HAL_PWR_PVDCallback(void)
{
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pwr.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pwr.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pwr.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
@@ -60,7 +60,7 @@
*/
typedef struct
{
- uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
This parameter can be a value of @ref PWR_PVD_detection_level */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pwr_ex.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pwr_ex.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
@@ -172,7 +172,7 @@
/**
* @brief Disables the Backup Regulator.
* @param None
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
{
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pwr_ex.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_pwr_ex.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -115,7 +115,7 @@
##### Initialization and de-initialization functions #####
===============================================================================
[..]
- This section provide functions allowing to configure the internal/external oscillators
+ This section provides functions allowing to configure the internal/external oscillators
(HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
and APB2).
@@ -176,77 +176,17 @@
(#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
Depending on the device voltage range, the maximum frequency should
- be adapted accordingly:
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
- |---------------|----------------|----------------|-----------------|-----------------|
- |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
- +-------------------------------------------------------------------------------------+
+ be adapted accordingly (refer to the product datasheets for more details).
+
(#) For the STM32F42xxx and STM32F43xxx devices, the maximum frequency
of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
Depending on the device voltage range, the maximum frequency should
- be adapted accordingly:
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)|150< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
- |---------------|----------------|----------------|-----------------|-----------------|
- |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
- |-------------------------------------------------------------------------------------|
- |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 180|
- +-------------------------------------------------------------------------------------+
+ be adapted accordingly (refer to the product datasheets for more details).
+
(#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
PCLK2 84 MHz and PCLK1 42 MHz.
Depending on the device voltage range, the maximum frequency should
- be adapted accordingly:
- +-------------------------------------------------------------------------------------+
- | Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
- | | voltage range | voltage range | voltage range | voltage range |
- | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
- |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
- +-------------------------------------------------------------------------------------+
+ be adapted accordingly (refer to the product datasheets for more details).
@endverbatim
* @{
*/
@@ -301,8 +241,7 @@
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
-
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
@@ -324,16 +263,16 @@
/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
- /* Get timeout */
- timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
/* Set the new HSE configuration ---------------------------------------*/
@@ -342,30 +281,30 @@
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) == RCC_HSE_ON)
{
- /* Get timeout */
- timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
- /* Get timeout */
- timeout = HAL_GetTick() + HSE_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -393,16 +332,16 @@
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
- /* Get timeout */
- timeout = HAL_GetTick() + HSI_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
@@ -413,16 +352,16 @@
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
- /* Get timeout */
- timeout = HAL_GetTick() + HSI_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -438,34 +377,34 @@
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
-
- /* Get timeout */
- timeout = HAL_GetTick() + LSI_TIMEOUT_VALUE;
-
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
-
- /* Get timeout */
- timeout = HAL_GetTick() + LSI_TIMEOUT_VALUE;
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -482,29 +421,29 @@
PWR->CR |= PWR_CR_DBP;
/* Wait for Backup domain Write protection disable */
- timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE;
+ tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
-
+
/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
- /* Get timeout */
- timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
-
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
/* Set the new LSE configuration -----------------------------------------*/
@@ -512,30 +451,30 @@
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
{
- /* Get timeout */
- timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
- /* Get timeout */
- timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -558,17 +497,17 @@
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
-
- /* Get timeout */
- timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE;
-
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
/* Configure the main PLL clock source, multiplication and division factors. */
@@ -580,32 +519,33 @@
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
- /* Get timeout */
- timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE;
-
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- /* Get timeout */
- timeout = HAL_GetTick() + PLL_TIMEOUT_VALUE;
-
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -644,8 +584,7 @@
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
-
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
@@ -668,6 +607,13 @@
return HAL_ERROR;
}
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
@@ -702,34 +648,34 @@
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
- /* Get timeout */
- timeout = HAL_GetTick() + CLOCKSWITCH_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -740,7 +686,14 @@
/* Decreasing the CPU frequency */
else
{
- /*------------------------- SYSCLK Configuration ---------------------------*/
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration -------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
@@ -774,14 +727,14 @@
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
- /* Get timeout */
- timeout = HAL_GetTick() + CLOCKSWITCH_TIMEOUT_VALUE;
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -791,7 +744,7 @@
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
@@ -801,10 +754,10 @@
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
{
- if(HAL_GetTick() >= timeout)
+ if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -819,14 +772,7 @@
return HAL_ERROR;
}
}
-
- /*-------------------------- HCLK Configuration ----------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- {
- assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- }
-
+
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
@@ -841,16 +787,8 @@
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
}
- /* Setup SysTick Timer for 1 msec interrupts.
- ------------------------------------------
- The SysTick_Config() function is a CMSIS function which configure:
- - The SysTick Reload register with value passed as function parameter.
- - Configure the SysTick IRQ priority to the lowest value (0x0F).
- - Reset the SysTick Counter register.
- - Configure the SysTick Counter clock source to be Core Clock Source (HCLK).
- - Enable the SysTick Interrupt.
- - Start the SysTick Counter.*/
- SysTick_Config(HAL_RCC_GetHCLKFreq() / 1000);
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick (TICK_INT_PRIORITY);
return HAL_OK;
}
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@@ -67,16 +67,16 @@
uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
This parameter must be a value of @ref RCC_PLL_Clock_Source */
- uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
- uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
- uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK)
- This parameter must be a value of @ref RCC_PLLP_Clock_Divider. */
+ uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
+ This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
- uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks
+ uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
}RCC_PLLInitTypeDef;
@@ -190,7 +190,7 @@
#define DBP_TIMEOUT_VALUE ((uint32_t)100)
-#define LSE_TIMEOUT_VALUE ((uint32_t)5000)
+#define LSE_TIMEOUT_VALUE ((uint32_t)500)
/**
* @}
*/
@@ -1042,11 +1042,6 @@
*/
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
-/** @defgroup RCC_Flags_Interrupts_Management
- * @brief macros to manage the specified RCC Flags and interrupts.
- * @{
- */
-
/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
* the selected interrupts).
* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
@@ -1126,9 +1121,6 @@
*/
#define RCC_FLAG_MASK ((uint8_t)0x1F)
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
-/**
- * @}
- */
#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc_ex.c Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc_ex.c Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Extension RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: @@ -316,8 +316,8 @@ /** * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that - * will be configured. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @@ -471,7 +471,7 @@ /** * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc_ex.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc_ex.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
@@ -61,16 +61,16 @@
*/
typedef struct
{
- uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock
- This parameter must be a number between Min_Data = 192 and Max_Data = 432
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432.
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
- uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock
- This parameter must be a number between Min_Data = 2 and Max_Data = 7
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
- This parameter must be a number between Min_Data = 2 and Max_Data = 15
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.
This parameter will be used only when PLLI2S is selected as Clock Source SAI */
}RCC_PLLI2SInitTypeDef;
@@ -80,15 +80,15 @@
typedef struct
{
uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
- This parameter must be a number between Min_Data = 192 and Max_Data = 432
+ This parameter must be a number between Min_Data = 192 and Max_Data = 432.
This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
- This parameter must be a number between Min_Data = 2 and Max_Data = 15
+ This parameter must be a number between Min_Data = 2 and Max_Data = 15.
This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
- This parameter must be a number between Min_Data = 2 and Max_Data = 7
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
}RCC_PLLSAIInitTypeDef;
@@ -100,13 +100,13 @@
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
- RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
- RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters
+ RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
- uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock
+ uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
This parameter must be a number between Min_Data = 1 and Max_Data = 32
This parameter will be used only when PLLI2S is selected as Clock Source SAI */
@@ -117,10 +117,10 @@
uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
This parameter can be a value of @ref RCC_RTC_Clock_Source */
- uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection
+ uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
}RCC_PeriphCLKInitTypeDef;
@@ -132,12 +132,12 @@
*/
typedef struct
{
- uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock
+ uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
This parameter must be a number between Min_Data = 192 and Max_Data = 432
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
- uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock
- This parameter must be a number between Min_Data = 2 and Max_Data = 7
+ uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
+ This parameter must be a number between Min_Data = 2 and Max_Data = 7.
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
}RCC_PLLI2SInitTypeDef;
@@ -151,10 +151,10 @@
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
- RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
+ RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
- uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
+ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
This parameter can be a value of @ref RCC_RTC_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rng.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rng.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rng.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
@@ -102,7 +102,8 @@
/**
* @brief Initializes the RNG according to the specified
* parameters in the RNG_InitTypeDef and creates the associated handle.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
@@ -118,20 +119,23 @@
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
}
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
/* Enable the RNG Peripheral */
__HAL_RNG_ENABLE(hrng);
-
+
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitializes the RNG peripheral.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
@@ -168,7 +172,8 @@
/**
* @brief Initializes the RNG MSP.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval None
*/
__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
@@ -180,7 +185,8 @@
/**
* @brief DeInitializes the RNG MSP.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval None
*/
__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
@@ -215,7 +221,8 @@
* @brief Returns a 32-bit random number.
* @note Each time the random number data is read the RNG_FLAG_DRDY flag
* is automatically cleared.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval 32-bit random number
*/
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
@@ -249,7 +256,8 @@
/**
* @brief Returns a 32-bit random number with interrupt enabled.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval 32-bit random number
*/
uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
@@ -286,13 +294,14 @@
* not have enough entropy. In this case, it is recommended to clear the
* SEIS bit using __HAL_RNG_CLEAR_FLAG(), then disable and enable
* the RNG peripheral to reinitialize and restart the RNG.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval None
*/
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
{
- /* RNG clock error interrupt occured */
+ /* RNG clock error interrupt occurred */
if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_CEI) != RESET)
{
HAL_RNG_ErrorCallback(hrng);
@@ -307,7 +316,7 @@
__HAL_UNLOCK(hrng);
}
- /* RNG seed error interrupt occured */
+ /* RNG seed error interrupt occurred */
if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_SEI) != RESET)
{
HAL_RNG_ErrorCallback(hrng);
@@ -341,7 +350,8 @@
/**
* @brief Data Ready callback in non-blocking mode.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval None
*/
@@ -354,7 +364,8 @@
/**
* @brief RNG error callbacks.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval None
*/
__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
@@ -385,7 +396,8 @@
/**
* @brief Returns the RNG state.
- * @param hrng: RNG handle
+ * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * the configuration information for RNG.
* @retval HAL state
*/
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rng.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rng.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_rng.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of RNG HAL module. ****************************************************************************** * @attention @@ -121,6 +121,12 @@ /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset RNG handle state + * @param __HANDLE__: RNG Handle + * @retval None + */ +#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) + /** * @brief Enables the RNG peripheral. * @param __HANDLE__: RNG Handle
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rtc.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rtc.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@@ -24,7 +24,7 @@
the RTC when VDD is turned off, VBAT pin can be connected to an optional
standby voltage supplied by a battery or by another source.
- [..] To allow the RTC to operate even when the main digital supply (VDD) is turned
+ [..] To allow the RTC operating even when the main digital supply (VDD) is turned
off, the VBAT pin powers the following blocks:
(#) The RTC
(#) The LSE oscillator
@@ -32,13 +32,13 @@
(#) PC13 to PC15 I/Os, plus PI8 I/O (when available)
[..] When the backup domain is supplied by VDD (analog switch connected to VDD),
- the following functions are available:
+ the following pins are available:
(#) PC14 and PC15 can be used as either GPIO or LSE pins
(#) PC13 can be used as a GPIO or as the RTC_AF1 pin
(#) PI8 can be used as a GPIO or as the RTC_AF2 pin
[..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
- because VDD is not present), the following functions are available:
+ because VDD is not present), the following pins are available:
(#) PC14 and PC15 can be used as LSE pins only
(#) PC13 can be used as the RTC_AF1 pin
(#) PI8 can be used as the RTC_AF2 pin
@@ -47,7 +47,7 @@
==================================================================
[..] The backup domain reset sets all RTC registers and the RCC_BDCR register
to their reset values. The BKPSRAM is not affected by this reset. The only
- way of resetting the BKPSRAM is through the Flash interface by requesting
+ way to reset the BKPSRAM is through the Flash interface by requesting
a protection level change from 1 to 0.
[..] A backup domain reset is generated when one of the following events occurs:
(#) Software reset, triggered by setting the BDRST bit in the
@@ -101,7 +101,7 @@
or the RTC wakeup events.
[..] The RTC provides a programmable time base for waking up from the
Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC clock source
+ Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
is LSE or LSI.
@endverbatim
@@ -167,18 +167,18 @@
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
- [..] This section provide functions allowing to initialize and configure the
+ [..] This section provides functions allowing to initialize and configure the
RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
RTC registers Write protection, enter and exit the RTC initialization mode,
RTC registers synchronization check and reference clock detection enable.
(#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
It is split into 2 programmable prescalers to minimize power consumption.
- (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+ (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
(++) When both prescalers are used, it is recommended to configure the
- asynchronous prescaler to a high value to minimize consumption.
+ asynchronous prescaler to a high value to minimize power consumption.
(#) All RTC registers are Write protected. Writing to the RTC registers
is enabled by writing a key into the Write Protection register, RTC_WPR.
- (#) To Configure the RTC Calendar, user application should enter
+ (#) To configure the RTC Calendar, user application should enter
initialization mode. In this mode, the calendar counter is stopped
and its value can be updated. When the initialization sequence is
complete, the calendar restarts counting after 4 RTCCLK cycles.
@@ -196,7 +196,8 @@
/**
* @brief Initializes the RTC peripheral
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
@@ -267,7 +268,8 @@
/**
* @brief DeInitializes the RTC peripheral
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note This function doesn't reset the RTC Backup Data registers.
* @retval HAL status
*/
@@ -366,7 +368,8 @@
/**
* @brief Initializes the RTC MSP.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
@@ -378,7 +381,8 @@
/**
* @brief DeInitializes the RTC MSP.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
@@ -400,7 +404,7 @@
##### RTC Time and Date functions #####
===============================================================================
- [..] This section provide functions allowing to configure Time and Date features
+ [..] This section provides functions allowing to configure Time and Date features
@endverbatim
* @{
@@ -408,12 +412,13 @@
/**
* @brief Sets RTC current time.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -532,12 +537,13 @@
/**
* @brief Gets RTC current time.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
* @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
* in the higher-order calendar shadow registers.
* @retval HAL status
@@ -575,12 +581,13 @@
/**
* @brief Sets RTC current date.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sDate: Pointer to date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -683,12 +690,13 @@
/**
* @brief Gets RTC current date.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sDate: Pointer to Date structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN : Binary data format
- * @arg Format_BCD : BCD data format
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -730,19 +738,20 @@
##### RTC Alarm functions #####
===============================================================================
- [..] This section provide functions allowing to configure Alarm feature
+ [..] This section provides functions allowing to configure Alarm feature
@endverbatim
* @{
*/
/**
* @brief Sets the specified RTC Alarm.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
@@ -918,12 +927,13 @@
/**
* @brief Sets the specified RTC Alarm with Interrupt
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
@@ -1104,11 +1114,12 @@
/**
* @brief Deactive the specified RTC Alarm
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Alarm: Specifies the Alarm.
* This parameter can be one of the following values:
- * @arg ALARM_A : AlarmA
- * @arg ALARM_B : AlarmB
+ * @arg RTC_ALARM_A: AlarmA
+ * @arg RTC_ALARM_B: AlarmB
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
@@ -1193,16 +1204,17 @@
/**
* @brief Gets the RTC Alarm value and masks.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sAlarm: Pointer to Date structure
- * @param Alarm: Specifies the Alarm
+ * @param Alarm: Specifies the Alarm.
* This parameter can be one of the following values:
- * @arg ALARM_A: AlarmA
- * @arg ALARM_B: AlarmB
+ * @arg RTC_ALARM_A: AlarmA
+ * @arg RTC_ALARM_B: AlarmB
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * @arg FORMAT_BIN: Binary data format
+ * @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
@@ -1252,7 +1264,8 @@
/**
* @brief This function handles Alarm interrupt request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
@@ -1292,7 +1305,8 @@
/**
* @brief Alarm A callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1304,7 +1318,8 @@
/**
* @brief This function handles AlarmA Polling request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
@@ -1367,7 +1382,8 @@
* The software must then wait until it is set again before reading
* the calendar, which means that the calendar registers have been
* correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
@@ -1406,8 +1422,9 @@
* @{
*/
/**
- * @brief Returns the Alarm state.
- * @param hrtc: RTC handle
+ * @brief Returns the RTC state.
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL state
*/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
@@ -1423,7 +1440,8 @@
* @brief Enters the RTC Initialization mode.
* @note The RTC Initialization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rtc.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rtc.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rtc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
@@ -98,7 +98,7 @@
typedef struct
{
uint8_t Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
@@ -113,7 +113,7 @@
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
- uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
+ uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation.
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
@@ -542,6 +542,12 @@
/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset RTC handle state
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+
/**
* @brief Disable the write protection for RTC registers.
* @param __HANDLE__: specifies the RTC handle.
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rtc_ex.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rtc_ex.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@@ -26,7 +26,7 @@
================================
[..]
(+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
- function. You can also configure the RTC Wakeup timer with interrupt mode
+ function. You can also configure the RTC Wakeup timer in interrupt mode
using the HAL_RTC_SetWakeUpTimer_IT() function.
(+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
function.
@@ -34,7 +34,7 @@
*** TimeStamp configuration ***
===============================
[..]
- (+) Configure the RTC_AFx trigger and enables the RTC TimeStamp using the
+ (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the
HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with
interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
(+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
@@ -47,10 +47,10 @@
*** Tamper configuration ***
============================
[..]
- (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
+ (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
or Level according to the Tamper filter (if equal to 0 Edge else Level)
value, sampling frequency, precharge or discharge and Pull-UP using the
- HAL_RTC_SetTamper() function. You can configure RTC Tamper with interrupt
+ HAL_RTC_SetTamper() function. You can configure RTC Tamper in interrupt
mode using HAL_RTC_SetTamper_IT() function.
(+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13)
or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in
@@ -130,7 +130,7 @@
##### RTC TimeStamp and Tamper functions #####
===============================================================================
- [..] This section provide functions allowing to configure TimeStamp feature
+ [..] This section provides functions allowing to configure TimeStamp feature
@endverbatim
* @{
@@ -139,13 +139,14 @@
/**
* @brief Sets TimeStamp.
* @note This API must be called before enabling the TimeStamp feature.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
* activated.
- * This parameter can be one of the following:
- * @arg TimeStampEdge_Rising: the Time stamp event occurs on the
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
- * @arg TimeStampEdge_Falling: the Time stamp event occurs on the
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
* @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
@@ -196,14 +197,15 @@
/**
* @brief Sets TimeStamp with Interrupt.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note This API must be called before enabling the TimeStamp feature.
* @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
* activated.
- * This parameter can be one of the following:
- * @arg TimeStampEdge_Rising: the Time stamp event occurs on the
+ * This parameter can be one of the following values:
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
- * @arg TimeStampEdge_Falling: the Time stamp event occurs on the
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
* @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
@@ -261,7 +263,8 @@
/**
* @brief Deactivates TimeStamp.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
@@ -298,13 +301,14 @@
/**
* @brief Gets the RTC TimeStamp value.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTimeStamp: Pointer to Time structure
* @param sTimeStampDate: Pointer to Date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg Format_BIN: Binary data format
- * @arg Format_BCD: BCD data format
+ * FORMAT_BIN: Binary data format
+ * FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
@@ -354,7 +358,8 @@
/**
* @brief Sets Tamper
* @note By calling this API we disable the tamper interrupt for all tampers.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTamper: Pointer to Tamper Structure.
* @retval HAL status
*/
@@ -403,7 +408,8 @@
/**
* @brief Sets Tamper with interrupt.
* @note By calling this API we force the tamper interrupt for all tampers.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTamper: Pointer to RTC Tamper.
* @retval HAL status
*/
@@ -427,11 +433,7 @@
hrtc->State = HAL_RTC_STATE_BUSY;
/* Configure the tamper trigger */
- if((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || (sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL))
- {
- sTamper->Trigger = RTC_TAMPERTRIGGER_RISINGEDGE;
- }
- else
+ if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
{
sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
}
@@ -464,7 +466,8 @@
/**
* @brief Deactivates Tamper.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Tamper: Selected tamper pin.
* This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
* @retval HAL status
@@ -491,7 +494,8 @@
/**
* @brief This function handles TimeStamp interrupt request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
@@ -545,7 +549,8 @@
/**
* @brief TimeStamp callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
@@ -557,7 +562,8 @@
/**
* @brief Tamper 1 callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
@@ -569,7 +575,8 @@
/**
* @brief Tamper 2 callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
@@ -581,7 +588,8 @@
/**
* @brief This function handles TimeStamp polling request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
@@ -623,7 +631,8 @@
/**
* @brief This function handles Tamper1 Polling.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
@@ -658,7 +667,8 @@
/**
* @brief This function handles Tamper2 Polling.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
@@ -703,7 +713,7 @@
##### RTC Wake-up functions #####
===============================================================================
- [..] This section provide functions allowing to configure Wake-up feature
+ [..] This section provides functions allowing to configure Wake-up feature
@endverbatim
* @{
@@ -711,7 +721,8 @@
/**
* @brief Sets wake up timer.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param WakeUpCounter: Wake up counter
* @param WakeUpClock: Wake up clock
* @retval HAL status
@@ -778,9 +789,10 @@
/**
* @brief Sets wake up timer with interrupt
- * @param hrtc: RTC handle
- * @param WakeUpCounter: wake up counter
- * @param WakeUpClock: wake up clock
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param WakeUpCounter: Wake up counter
+ * @param WakeUpClock: Wake up clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
@@ -853,7 +865,8 @@
/**
* @brief Deactivates wake up timer counter.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -905,7 +918,8 @@
/**
* @brief Gets wake up timer counter.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval Counter value
*/
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -916,7 +930,8 @@
/**
* @brief This function handles Wake Up Timer interrupt request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
@@ -943,7 +958,8 @@
/**
* @brief Wake Up Timer callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
@@ -955,7 +971,8 @@
/**
* @brief This function handles Wake Up Timer Polling.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
@@ -1002,18 +1019,18 @@
===============================================================================
[..]
This subsection provides functions allowing to
- (+) Writes a data in a specified RTC Backup data register
+ (+) Write a data in a specified RTC Backup data register
(+) Read a data in a specified RTC Backup data register
- (+) Sets the Coarse calibration parameters.
- (+) Deactivates the Coarse calibration parameters
- (+) Sets the Smooth calibration parameters.
- (+) Configures the Synchronization Shift Control Settings.
- (+) Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- (+) Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- (+) Enables the RTC reference clock detection.
+ (+) Set the Coarse calibration parameters.
+ (+) Deactivate the Coarse calibration parameters
+ (+) Set the Smooth calibration parameters.
+ (+) Configure the Synchronization Shift Control Settings.
+ (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ (+) Enable the RTC reference clock detection.
(+) Disable the RTC reference clock detection.
- (+) Enables the Bypass Shadow feature.
- (+) Disables the Bypass Shadow feature.
+ (+) Enable the Bypass Shadow feature.
+ (+) Disable the Bypass Shadow feature.
@endverbatim
* @{
@@ -1021,7 +1038,8 @@
/**
* @brief Writes a data in a specified RTC Backup data register.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param BackupRegister: RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
* specify the register.
@@ -1044,7 +1062,8 @@
/**
* @brief Reads data from the specified RTC Backup data Register.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param BackupRegister: RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
* specify the register.
@@ -1066,7 +1085,8 @@
/**
* @brief Sets the Coarse calibration parameters.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param CalibSign: Specifies the sign of the coarse calibration value.
* This parameter can be one of the following values :
* @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive
@@ -1134,7 +1154,8 @@
/**
* @brief Deactivates the Coarse calibration parameters.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc)
@@ -1184,7 +1205,8 @@
/**
* @brief Sets the Smooth calibration parameters.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param SmoothCalibPeriod: Select the Smooth Calibration Period.
* This parameter can be can be one of the following values :
* @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s.
@@ -1198,7 +1220,7 @@
* This parameter can be one any value from 0 to 0x000001FF.
* @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
* must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
- * SmouthCalibMinusPulsesValue mut be equal to 0.
+ * SmouthCalibMinusPulsesValue must be equal to 0.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
@@ -1260,7 +1282,8 @@
/**
* @brief Configures the Synchronization Shift Control Settings.
* @note When REFCKON is set, firmware must not write to Shift control register.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
* This parameter can be one of the following values :
* @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
@@ -1355,8 +1378,9 @@
/**
* @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: RTC handle
- * @param CalibOutput : Select the Calibration output Selection .
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param CalibOutput: Select the Calibration output Selection .
* This parameter can be one of the following values:
* @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
* @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
@@ -1397,7 +1421,8 @@
/**
* @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
@@ -1426,7 +1451,8 @@
/**
* @brief Enables the RTC reference clock detection.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
@@ -1475,7 +1501,8 @@
/**
* @brief Disable the RTC reference clock detection.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
@@ -1524,7 +1551,8 @@
/**
* @brief Enables the Bypass Shadow feature.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
* @retval HAL status
@@ -1556,7 +1584,8 @@
/**
* @brief Disables the Bypass Shadow feature.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
* @retval HAL status
@@ -1607,7 +1636,8 @@
/**
* @brief Alarm B callback.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1619,7 +1649,8 @@
/**
* @brief This function handles AlarmB Polling request.
- * @param hrtc: RTC handle
+ * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout: Timeout duration
* @retval HAL status
*/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rtc_ex.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rtc_ex.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_rtc_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention
@@ -335,7 +335,7 @@
* @}
*/
-/** @defgroup RTC_Smooth_calib_period_Definitions
+/** @defgroup RTCEx_Smooth_calib_period_Definitions
* @{
*/
#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sai.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sai.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sai.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief SAI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Audio Interface (SAI) peripheral:
@@ -18,10 +18,10 @@
==============================================================================
[..]
- The SAI HAL driver can be used as follow:
+ The SAI HAL driver can be used as follows:
(#) Declare a SAI_HandleTypeDef handle structure.
- (#) Initialize the SAI low level resources by implement the HAL_SAI_MspInit() API:
+ (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API:
(##) Enable the SAI interface clock.
(##) SAI pins configuration:
(+++) Enable the clock for the SAI GPIOs.
@@ -56,12 +56,12 @@
the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
[..]
- (@) In master TX mode: enabling the audio block immediately generates the bit clock
+ (@) In master Tx mode: enabling the audio block immediately generates the bit clock
for the external slaves even if there is no data in the FIFO, However FS signal
generation is conditioned by the presence of data in the FIFO.
[..]
- (@) In master RX mode: enabling the audio block immediately generates the bit clock
+ (@) In master Rx mode: enabling the audio block immediately generates the bit clock
and FS signal for the external slaves.
[..]
@@ -72,7 +72,7 @@
(+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected.
[..]
- Three mode of operations are available within this driver :
+ Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -110,7 +110,7 @@
*** SAI HAL driver macros list ***
=============================================
[..]
- Below the list of most used macros in USART HAL driver.
+ Below the list of most used macros in USART HAL driver :
(+) __HAL_SAI_ENABLE: Enable the SAI peripheral
(+) __HAL_SAI_DISABLE: Disable the SAI peripheral
@@ -199,7 +199,7 @@
[..] This subsection provides a set of functions allowing to initialize and
de-initialize the SAIx peripheral:
- (+) User must Implement HAL_SAI_MspInit() function in which he configures
+ (+) User must implement HAL_SAI_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
(+) Call the function HAL_SAI_Init() to configure the selected device with
@@ -223,7 +223,8 @@
/**
* @brief Initializes the SAI according to the specified parameters
* in the SAI_InitTypeDef and create the associated handle.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
@@ -453,7 +454,8 @@
/**
* @brief DeInitializes the SAI peripheral.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai)
@@ -483,7 +485,8 @@
/**
* @brief SAI MSP Init.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @retval None
*/
__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai)
@@ -495,7 +498,8 @@
/**
* @brief SAI MSP DeInit.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @retval None
*/
__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai)
@@ -520,7 +524,7 @@
This subsection provides a set of functions allowing to manage the SAI data
transfers.
- (+) There is two mode of transfer:
+ (+) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
after finishing transfer.
@@ -535,17 +539,17 @@
(++) HAL_SAI_Receive()
(++) HAL_SAI_TransmitReceive()
- (+) No-Blocking mode functions with Interrupt are :
+ (+) Non Blocking mode functions with Interrupt are :
(++) HAL_SAI_Transmit_IT()
(++) HAL_SAI_Receive_IT()
(++) HAL_SAI_TransmitReceive_IT()
- (+) No-Blocking mode functions with DMA are :
+ (+) Non Blocking mode functions with DMA are :
(++) HAL_SAI_Transmit_DMA()
(++) HAL_SAI_Receive_DMA()
(++) HAL_SAI_TransmitReceive_DMA()
- (+) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SAI_TxCpltCallback()
(++) HAL_SAI_RxCpltCallback()
(++) HAL_SAI_ErrorCallback()
@@ -556,7 +560,8 @@
/**
* @brief Transmits an amount of data in blocking mode.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@@ -630,7 +635,8 @@
/**
* @brief Receives an amount of data in blocking mode.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @param Timeout: Timeout duration
@@ -707,7 +713,8 @@
/**
* @brief Transmits an amount of data in no-blocking mode with Interrupt.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -784,7 +791,8 @@
/**
* @brief Receives an amount of data in no-blocking mode with Interrupt.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @retval HAL status
@@ -855,8 +863,9 @@
/**
* @brief Pauses the audio stream playing from the Media.
- * @param hsai: SAI handle
- * @retval None
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai)
{
@@ -875,8 +884,9 @@
/**
* @brief Resumes the audio stream playing from the Media.
- * @param hsai: SAI handle
- * @retval None
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai)
{
@@ -901,9 +911,10 @@
}
/**
- * @brief Resumes the audio stream playing from the Media.
- * @param hsai: SAI handle
- * @retval None
+ * @brief Stops the audio stream playing from the Media.
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
{
@@ -936,7 +947,8 @@
}
/**
* @brief Transmits an amount of data in no-blocking mode with DMA.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -996,8 +1008,9 @@
}
/**
- * @brief Receive an amount of data in no-blocking mode with DMA.
- * @param hsai: SAI handle
+ * @brief Receives an amount of data in no-blocking mode with DMA.
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @retval HAL status
@@ -1058,7 +1071,8 @@
/**
* @brief This function handles SAI interrupt request.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @retval HAL status
*/
void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
@@ -1120,7 +1134,8 @@
/**
* @brief Tx Transfer completed callbacks.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @retval None
*/
__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai)
@@ -1132,7 +1147,8 @@
/**
* @brief Tx Transfer Half completed callbacks
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @retval None
*/
__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai)
@@ -1144,7 +1160,8 @@
/**
* @brief Rx Transfer completed callbacks.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @retval None
*/
__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai)
@@ -1156,7 +1173,8 @@
/**
* @brief Rx Transfer half completed callbacks
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @retval None
*/
__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai)
@@ -1168,7 +1186,8 @@
/**
* @brief SAI error callbacks.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @retval None
*/
__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
@@ -1191,7 +1210,7 @@
##### Peripheral State and Errors functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1200,7 +1219,8 @@
/**
* @brief Returns the SAI state.
- * @param hsai: SAI handle
+ * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * the configuration information for SAI module.
* @retval HAL state
*/
HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
@@ -1224,7 +1244,8 @@
/**
* @brief DMA SAI transmit process complete callback.
- * @param hdma: DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma)
@@ -1265,7 +1286,8 @@
/**
* @brief DMA SAI transmit process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1277,7 +1299,8 @@
/**
* @brief DMA SAI receive process complete callback.
- * @param hdma: DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma)
@@ -1296,7 +1319,8 @@
/**
* @brief DMA SAI receive process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1307,7 +1331,8 @@
}
/**
* @brief DMA SAI communication error callback.
- * @param hdma: DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SAI_DMAError(DMA_HandleTypeDef *hdma)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sai.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sai.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sai.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of SAI HAL module.
******************************************************************************
* @attention
@@ -177,35 +177,34 @@
typedef struct
{
SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
-
+
SAI_InitTypeDef Init; /*!< SAI communication parameters */
-
+
SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */
-
+
SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
-
- uint16_t *pTxBuffPtr; /*!< Pointer to SAI Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SAI Tx transfer size */
-
- uint16_t TxXferCount; /*!< SAI Tx transfer counter */
-
- uint16_t *pRxBuffPtr; /*!< Pointer to SAI Rx transfer buffer */
-
- uint16_t RxXferSize; /*!< SAI Rx transfer size */
-
- uint16_t RxXferCount; /*!< SAI Rx transfer counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
+
+ uint16_t *pTxBuffPtr; /*!< Pointer to SAI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SAI Tx transfer size */
+
+ uint16_t TxXferCount; /*!< SAI Tx transfer counter */
+
+ uint16_t *pRxBuffPtr; /*!< Pointer to SAI Rx transfer buffer */
+
+ uint16_t RxXferSize; /*!< SAI Rx transfer size */
- HAL_LockTypeDef Lock; /*!< SAI locking object */
-
- __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
-
- __IO uint32_t ErrorCode; /*!< SAI Error code */
+ uint16_t RxXferCount; /*!< SAI Rx transfer counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
+ HAL_LockTypeDef Lock; /*!< SAI locking object */
+
+ __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
+
+ __IO uint32_t ErrorCode; /*!< SAI Error code */
}SAI_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
@@ -218,7 +217,7 @@
*/
#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun Error */
-#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002) /*!< Underrun error */
+#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002) /*!< Underrun error */
#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
/**
* @}
@@ -236,7 +235,7 @@
((SOURCE) == SAI_CLKSOURCE_EXT))
/**
* @}
- */
+ */
/** @defgroup SAI_Audio_Frequency
* @{
@@ -462,8 +461,8 @@
/** @defgroup SAI_Block_Slot_Active
* @{
*/
-#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000)
-#define SAI_SLOTACTIVE_0 ((uint32_t)0x00010000)
+#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000)
+#define SAI_SLOTACTIVE_0 ((uint32_t)0x00010000)
#define SAI_SLOTACTIVE_1 ((uint32_t)0x00020000)
#define SAI_SLOTACTIVE_2 ((uint32_t)0x00040000)
#define SAI_SLOTACTIVE_3 ((uint32_t)0x00080000)
@@ -645,6 +644,11 @@
*/
/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset SAI handle state
+ * @param __HANDLE__: specifies the SAI Handle.
+ * @retval None
+ */
+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
/** @brief Enable or disable the specified SAI interrupts.
* @param __HANDLE__: specifies the SAI Handle.
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sd.c Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sd.c Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sd.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: @@ -1388,7 +1388,8 @@ /** * @brief SD Transfer complete Rx callback in non blocking mode. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ __weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma) @@ -1400,7 +1401,8 @@ /** * @brief SD DMA transfer complete Rx error callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ __weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma) @@ -1412,7 +1414,8 @@ /** * @brief SD Transfer complete Tx callback in non blocking mode. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ __weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma) @@ -1424,7 +1427,8 @@ /** * @brief SD DMA transfer complete error Tx callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ __weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma) @@ -2167,7 +2171,8 @@ /** * @brief SD DMA transfer complete Rx callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma) @@ -2188,7 +2193,8 @@ /** * @brief SD DMA transfer Error Rx callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SD_DMA_RxError(DMA_HandleTypeDef *hdma) @@ -2201,7 +2207,8 @@ /** * @brief SD DMA transfer complete Tx callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma) @@ -2222,7 +2229,8 @@ /** * @brief SD DMA transfer Error Tx callback. - * @param hdma: DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sd.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sd.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sd.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of SD HAL module.
******************************************************************************
* @attention
@@ -63,11 +63,11 @@
*/
typedef struct
{
- SD_TypeDef *Instance; /*!< SDIO register base address */
+ SD_TypeDef *Instance; /*!< SDIO register base address */
SD_InitTypeDef Init; /*!< SD required parameters */
- HAL_LockTypeDef Lock; /*!< SD locking object */
+ HAL_LockTypeDef Lock; /*!< SD locking object */
uint32_t CardType; /*!< SD card type */
@@ -79,13 +79,13 @@
__IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */
- __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */
+ __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */
__IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */
__IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */
- DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
@@ -199,7 +199,7 @@
SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */
SD_DATA_TIMEOUT = (4), /*!< Data timeout */
SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */
- SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */
+ SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */
SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */
SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */
SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */
@@ -231,20 +231,20 @@
/**
* @brief Standard error defines
*/
- SD_INTERNAL_ERROR = (34),
+ SD_INTERNAL_ERROR = (34),
SD_NOT_CONFIGURED = (35),
- SD_REQUEST_PENDING = (36),
- SD_REQUEST_NOT_APPLICABLE = (37),
- SD_INVALID_PARAMETER = (38),
- SD_UNSUPPORTED_FEATURE = (39),
- SD_UNSUPPORTED_HW = (40),
- SD_ERROR = (41),
+ SD_REQUEST_PENDING = (36),
+ SD_REQUEST_NOT_APPLICABLE = (37),
+ SD_INVALID_PARAMETER = (38),
+ SD_UNSUPPORTED_FEATURE = (39),
+ SD_UNSUPPORTED_HW = (40),
+ SD_ERROR = (41),
SD_OK = (0)
}HAL_SD_ErrorTypedef;
/**
- * @brief SD Transfer state enumeration structure
+ * @brief SD Transfer state enumeration structure
*/
typedef enum
{
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sdram.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sdram.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sdram.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief SDRAM HAL module driver.
* This file provides a generic firmware to drive SDRAM memories mounted
* as external device.
@@ -20,7 +20,7 @@
with SDRAM memories:
(#) Declare a SDRAM_HandleTypeDef handle structure, for example:
- SDRAM_HandleTypeDef hdsram; and:
+ SDRAM_HandleTypeDef hdsram
(++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
values of the structure member.
@@ -133,7 +133,8 @@
/**
* @brief Performs the SDRAM device initialization sequence.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @param Timing: Pointer to SDRAM control timing structure
* @retval HAL status
*/
@@ -168,7 +169,8 @@
/**
* @brief Perform the SDRAM device initialization sequence.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
@@ -190,7 +192,8 @@
/**
* @brief SDRAM MSP Init.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @retval None
*/
__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
@@ -202,7 +205,8 @@
/**
* @brief SDRAM MSP DeInit.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @retval None
*/
__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
@@ -214,7 +218,8 @@
/**
* @brief This function handles SDRAM refresh error interrupt request.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @retval HAL status
*/
void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
@@ -232,7 +237,8 @@
/**
* @brief SDRAM Refresh error callback.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @retval None
*/
__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
@@ -244,7 +250,8 @@
/**
* @brief DMA transfer complete callback.
- * @param hdma: DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
@@ -286,7 +293,8 @@
/**
* @brief Reads 8-bit data buffer from the SDRAM memory.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
@@ -326,7 +334,8 @@
/**
* @brief Writes 8-bit data buffer to SDRAM memory.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
@@ -369,7 +378,8 @@
/**
* @brief Reads 16-bit data buffer from the SDRAM memory.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
@@ -408,7 +418,8 @@
/**
* @brief Writes 16-bit data buffer to SDRAM memory.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
@@ -450,7 +461,8 @@
/**
* @brief Reads 32-bit data buffer from the SDRAM memory.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
@@ -489,7 +501,8 @@
/**
* @brief Writes 32-bit data buffer to SDRAM memory.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
@@ -531,7 +544,8 @@
/**
* @brief Reads a Words data from the SDRAM memory using DMA transfer.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
@@ -571,7 +585,8 @@
/**
* @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
@@ -630,7 +645,8 @@
/**
* @brief Enables dynamically SDRAM write protection.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
@@ -655,7 +671,8 @@
/**
* @brief Disables dynamically SDRAM write protection.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
@@ -680,10 +697,11 @@
/**
* @brief Sends Command to the SDRAM bank.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @param Command: SDRAM command structure
* @param Timeout: Timeout duration
- * @retval HAL state
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
{
@@ -714,9 +732,10 @@
/**
* @brief Programs the SDRAM Memory Refresh rate.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @param RefreshRate: The SDRAM refresh rate value
- * @retval HAL state
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
{
@@ -740,9 +759,10 @@
/**
* @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @param AutoRefreshNumber: The SDRAM auto Refresh number
- * @retval None
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
{
@@ -766,7 +786,8 @@
/**
* @brief Returns the SDRAM memory current mode.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @retval The SDRAM memory mode.
*/
uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
@@ -796,7 +817,8 @@
/**
* @brief Returns the SDRAM state.
- * @param hsdram: SDRAM handle
+ * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * the configuration information for SDRAM module.
* @retval HAL state
*/
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sdram.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sdram.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sdram.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of SDRAM HAL module.
******************************************************************************
* @attention
@@ -89,8 +89,15 @@
}SDRAM_HandleTypeDef;
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset SDRAM handle state
+ * @param __HANDLE__: specifies the SDRAM handle.
+ * @retval None
+ */
+#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
+
/* Exported functions --------------------------------------------------------*/
/* Initialization/de-initialization functions **********************************/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_smartcard.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_smartcard.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
@@ -16,10 +16,10 @@
##### How to use this driver #####
==============================================================================
[..]
- The SMARTCARD HAL driver can be used as follow:
+ The SMARTCARD HAL driver can be used as follows:
(#) Declare a SMARTCARD_HandleTypeDef handle structure.
- (#) Initialize the SMARTCARD low level resources by implement the HAL_SMARTCARD_MspInit ()API:
+ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
(##) Enable the USARTx interface clock.
(##) SMARTCARD pins configuration:
(+++) Enable the clock for the SMARTCARD GPIOs.
@@ -28,10 +28,6 @@
and HAL_SMARTCARD_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
(+++) Enable the NVIC USART IRQ handle.
-
- -@@- The specific SMARTCARD interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __SMARTCARD_ENABLE_IT() and __SMARTCARD_DISABLE_IT() inside the transmit and receive process.
(##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
and HAL_SMARTCARD_Receive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx stream.
@@ -42,13 +38,18 @@
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
(#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) in the hsc Init structure.
+ flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
(#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
- (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_SMARTCARD_MspInit(&hsc) API.
-
- (#) Three mode of operations are available within this driver :
+ (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_SMARTCARD_MspInit() API.
+ [..]
+ (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __SMARTCARD_ENABLE_IT() and __SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+ [..]
+ Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -87,10 +88,10 @@
(+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
(+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
- (+) __HAL_SMARTCARD_GET_FLAG : Checks whether the specified SMARTCARD flag is set or not
- (+) __HAL_SMARTCARD_CLEAR_FLAG : Clears the specified SMARTCARD pending flag
- (+) __HAL_SMARTCARD_ENABLE_IT: Enables the specified SMARTCARD interrupt
- (+) __HAL_SMARTCARD_DISABLE_IT: Disables the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
+ (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+ (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
[..]
(@) You can refer to the SMARTCARD HAL driver header file for more useful macros
@@ -182,18 +183,7 @@
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible SmartCard frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
+ please refer to Reference manual for possible SMARTDARD frame formats.
(++) USART polarity
(++) USART phase
(++) USART LastBit
@@ -225,7 +215,8 @@
/**
* @brief Initializes the SmartCard mode according to the specified
* parameters in the SMARTCARD_InitTypeDef and create the associated handle .
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
@@ -287,7 +278,8 @@
/**
* @brief DeInitializes the USART SmartCard peripheral
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
@@ -317,7 +309,8 @@
/**
* @brief SMARTCARD MSP Init
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
@@ -329,7 +322,8 @@
/**
* @brief SMARTCARD MSP DeInit
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
@@ -358,33 +352,33 @@
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
- (#) There are two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
+ (++) Non Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
The end of the data processing will be indicated through the
dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
- The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected
+ will be executed respectivelly at the end of the Transmit or Receive process
+ The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected
- (#) Blocking mode API's are :
+ (#) Blocking mode APIs are :
(++) HAL_SMARTCARD_Transmit()
(++) HAL_SMARTCARD_Receive()
- (#) Non-Blocking mode API's with Interrupt are :
+ (#) Non Blocking mode APIs with Interrupt are :
(++) HAL_SMARTCARD_Transmit_IT()
(++) HAL_SMARTCARD_Receive_IT()
(++) HAL_SMARTCARD_IRQHandler()
- (#) No-Blocking mode functions with DMA are :
+ (#) Non Blocking mode functions with DMA are :
(++) HAL_SMARTCARD_Transmit_DMA()
(++) HAL_SMARTCARD_Receive_DMA()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SMARTCARD_TxCpltCallback()
(++) HAL_SMARTCARD_RxCpltCallback()
(++) HAL_SMARTCARD_ErrorCallback()
@@ -395,16 +389,20 @@
/**
* @brief Send an amount of data in blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp;
-
- if(hsc->State == HAL_SMARTCARD_STATE_READY)
+ uint32_t tmp1 = 0;
+
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
{
if((pData == NULL) || (Size == 0))
{
@@ -415,8 +413,16 @@
__HAL_LOCK(hsc);
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+
hsc->TxXferSize = Size;
hsc->TxXferCount = Size;
while(hsc->TxXferCount > 0)
@@ -454,8 +460,15 @@
return HAL_TIMEOUT;
}
- hsc->State = HAL_SMARTCARD_STATE_READY;
-
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
+ }
/* Process Unlocked */
__HAL_UNLOCK(hsc);
@@ -469,16 +482,20 @@
/**
* @brief Receive an amount of data in blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be received
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp;
-
- if(hsc->State == HAL_SMARTCARD_STATE_READY)
+ uint32_t tmp1 = 0;
+
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
{
if((pData == NULL) || (Size == 0))
{
@@ -489,7 +506,16 @@
__HAL_LOCK(hsc);
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
hsc->RxXferSize = Size;
hsc->RxXferCount = Size;
@@ -531,7 +557,16 @@
}
}
}
- hsc->State = HAL_SMARTCARD_STATE_READY;
+
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
+ }
/* Process Unlocked */
__HAL_UNLOCK(hsc);
@@ -546,14 +581,18 @@
/**
* @brief Send an amount of data in non blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
- if(hsc->State == HAL_SMARTCARD_STATE_READY)
+ uint32_t tmp1 = 0;
+
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
{
if((pData == NULL) || (Size == 0))
{
@@ -568,7 +607,15 @@
hsc->TxXferCount = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
/* Enable the SMARTCARD Parity Error Interrupt */
__SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
@@ -592,14 +639,18 @@
/**
* @brief Receive an amount of data in non blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
- if(hsc->State == HAL_SMARTCARD_STATE_READY)
+ uint32_t tmp1 = 0;
+
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
{
if((pData == NULL) || (Size == 0))
{
@@ -614,7 +665,15 @@
hsc->RxXferCount = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
/* Enable the SMARTCARD Data Register not empty Interrupt */
__SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE);
@@ -638,7 +697,8 @@
/**
* @brief Send an amount of data in non blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @retval HAL status
@@ -646,10 +706,10 @@
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
- uint32_t tmpstate;
+ uint32_t tmp1 = 0;
- tmpstate = hsc->State;
- if((tmpstate == HAL_SMARTCARD_STATE_READY) || (tmpstate == HAL_SMARTCARD_STATE_BUSY_RX))
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
{
if((pData == NULL) || (Size == 0))
{
@@ -664,7 +724,15 @@
hsc->TxXferCount = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
/* Set the SMARTCARD DMA transfert complete callback */
hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
@@ -693,7 +761,8 @@
/**
* @brief Receive an amount of data in non blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be received
* @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
@@ -702,10 +771,10 @@
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
- uint32_t tmpstate;
+ uint32_t tmp1 = 0;
- tmpstate = hsc->State;
- if((tmpstate == HAL_SMARTCARD_STATE_READY) || (tmpstate == HAL_SMARTCARD_STATE_BUSY_TX))
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
{
if((pData == NULL) || (Size == 0))
{
@@ -719,7 +788,15 @@
hsc->RxXferSize = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
/* Set the SMARTCARD DMA transfert complete callback */
hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
@@ -748,62 +825,59 @@
/**
* @brief This function handles SMARTCARD interrupt request.
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
{
uint32_t tmp1 = 0, tmp2 = 0;
- tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_PE);
+ tmp1 = hsc->Instance->SR;
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE);
+
/* SMARTCARD parity error interrupt occured --------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ if(((tmp1 & SMARTCARD_FLAG_PE) != RESET) && (tmp2 != RESET))
{
__HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_PE);
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
}
- tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_FE);
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
/* SMARTCARD frame error interrupt occured ---------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ if(((tmp1 & SMARTCARD_FLAG_FE) != RESET) && (tmp2 != RESET))
{
__HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_FE);
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
}
- tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_NE);
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
/* SMARTCARD noise error interrupt occured ---------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ if(((tmp1 & SMARTCARD_FLAG_NE) != RESET) && (tmp2 != RESET))
{
__HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_NE);
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
}
-
- tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_ORE);
+
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
/* SMARTCARD Over-Run interrupt occured ------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ if(((tmp1 & SMARTCARD_FLAG_ORE) != RESET) && (tmp2 != RESET))
{
__HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_ORE);
hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
}
- tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_RXNE);
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE);
/* SMARTCARD in mode Receiver ----------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ if(((tmp1 & SMARTCARD_FLAG_RXNE) != RESET) && (tmp2 != RESET))
{
SMARTCARD_Receive_IT(hsc);
__HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_RXNE);
}
-
- tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TC);
+
tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC);
/* SMARTCARD in mode Transmitter -------------------------------------------*/
- if((tmp1 != RESET) && (tmp2 != RESET))
+ if(((tmp1 & SMARTCARD_FLAG_TC) != RESET) && (tmp2 != RESET))
{
SMARTCARD_Transmit_IT(hsc);
__HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
@@ -820,7 +894,8 @@
/**
* @brief Tx Transfer completed callbacks
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
@@ -832,7 +907,8 @@
/**
* @brief Rx Transfer completed callbacks
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
@@ -844,7 +920,8 @@
/**
* @brief SMARTCARD error callbacks
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
@@ -875,7 +952,8 @@
/**
* @brief return the SMARTCARD state
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL state
*/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
@@ -900,7 +978,8 @@
/**
* @brief DMA SMARTCARD transmit process complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
@@ -923,14 +1002,23 @@
else
{
/* No Timeout */
- hsc->State= HAL_SMARTCARD_STATE_READY;
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
+ }
HAL_SMARTCARD_TxCpltCallback(hsc);
}
}
/**
* @brief DMA SMARTCARD receive process complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
@@ -943,14 +1031,23 @@
in the USART CR3 register */
hsc->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
- hsc->State= HAL_SMARTCARD_STATE_READY;
-
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
+ }
+
HAL_SMARTCARD_RxCpltCallback(hsc);
}
/**
* @brief DMA SMARTCARD communication error callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
@@ -1031,18 +1128,18 @@
/**
* @brief Send an amount of data in non blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
{
uint16_t* tmp;
-
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ uint32_t tmp1 = 0;
+
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
{
- /* Process Locked */
- __HAL_LOCK(hsc);
-
if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
{
tmp = (uint16_t*) hsc->pTxBuffPtr;
@@ -1072,20 +1169,21 @@
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
__SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
- hsc->State = HAL_SMARTCARD_STATE_READY;
-
- /* Call the Process Unlocked before calling the Tx call back API to give the possibiity to
- start again the Transmission under the Tx call back API */
- __HAL_UNLOCK(hsc);
+ /* Check if a non-blocking receive process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
+ }
HAL_SMARTCARD_TxCpltCallback(hsc);
return HAL_OK;
}
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
return HAL_OK;
}
else
@@ -1096,18 +1194,18 @@
/**
* @brief Receive an amount of data in non blocking mode
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
{
uint16_t* tmp;
-
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ uint32_t tmp1 = 0;
+
+ tmp1 = hsc->State;
+ if((tmp1 == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
{
- /* Process Locked */
- __HAL_LOCK(hsc);
-
if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
{
tmp = (uint16_t*) hsc->pRxBuffPtr;
@@ -1147,20 +1245,20 @@
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
__SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
- hsc->State = HAL_SMARTCARD_STATE_READY;
-
- /* Call the Process Unlocked before calling the Rx call back API to give the possibiity to
- start again the receiption under the Rx call back API */
- __HAL_UNLOCK(hsc);
+ /* Check if a non-blocking transmit process is ongoing or not */
+ if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ hsc->State = HAL_SMARTCARD_STATE_READY;
+ }
HAL_SMARTCARD_RxCpltCallback(hsc);
return HAL_OK;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
return HAL_OK;
}
else
@@ -1171,7 +1269,8 @@
/**
* @brief Configure the SMARTCARD peripheral
- * @param hsc: usart handle
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_smartcard.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_smartcard.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
@@ -91,13 +91,13 @@
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref SMARTCARD_Last_Bit */
- uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler
+ uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler.
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
- uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time
+ uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time.
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
- uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state
+ uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state.
This parameter can be a value of @ref SmartCard_NACK_State */
}SMARTCARD_InitTypeDef;
@@ -106,13 +106,14 @@
*/
typedef enum
{
- HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
- HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
+ HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
+ HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
}HAL_SMARTCARD_StateTypeDef;
/**
@@ -313,6 +314,12 @@
/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset SMARTCARD handle state
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
+
/** @brief Flushs the Smartcard DR register
* @param __HANDLE__: specifies the SMARTCARD Handle.
*/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_spi.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_spi.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_spi.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief SPI HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -22,7 +22,7 @@
(#) Declare a SPI_HandleTypeDef handle structure, for example:
SPI_HandleTypeDef hspi;
- (#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API:
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
(##) Enable the SPIx interface clock
(##) SPI pins configuration
(+++) Enable the clock for the SPI GPIOs
@@ -43,7 +43,7 @@
(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_SPI_MspInit(&hspi) API.
+ by calling the customed HAL_SPI_MspInit() API.
@endverbatim
******************************************************************************
@@ -123,7 +123,7 @@
[..] This subsection provides a set of functions allowing to initialize and
de-initialiaze the SPIx peripheral:
- (+) User must Implement HAL_SPI_MspInit() function in which he configures
+ (+) User must implement HAL_SPI_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
(+) Call the function HAL_SPI_Init() to configure the selected device with
@@ -149,7 +149,8 @@
/**
* @brief Initializes the SPI according to the specified parameters
* in the SPI_InitTypeDef and create the associated handle.
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
@@ -209,7 +210,8 @@
/**
* @brief DeInitializes the SPI peripheral
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
@@ -237,7 +239,8 @@
/**
* @brief SPI MSP Init
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
@@ -249,7 +252,8 @@
/**
* @brief SPI MSP DeInit
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
@@ -275,12 +279,12 @@
[..] The SPI supports master and slave mode :
- (#) There are two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
+ or DMA, These APIs return the HAL status.
The end of the data processing will be indicated through the
dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
@@ -288,23 +292,23 @@
will be executed respectivelly at the end of the transmit or Receive process
The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
- (#) Blocking mode API's are :
+ (#) Blocking mode APIs are :
(++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_TransmitReceive() in full duplex mode
- (#) Non-Blocking mode API's with Interrupt are :
+ (#) Non Blocking mode API's with Interrupt are :
(++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_TransmitReceive_IT()in full duplex mode
(++) HAL_SPI_IRQHandler()
- (#) No-Blocking mode functions with DMA are :
+ (#) Non Blocking mode functions with DMA are :
(++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
(++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SPI_TxCpltCallback()
(++) HAL_SPI_RxCpltCallback()
(++) HAL_SPI_ErrorCallback()
@@ -316,7 +320,8 @@
/**
* @brief Transmit an amount of data in blocking mode
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @param Timeout: Timeout duration
@@ -454,7 +459,8 @@
/**
* @brief Receive an amount of data in blocking mode
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @param Timeout: Timeout duration
@@ -627,7 +633,8 @@
/**
* @brief Transmit and Receive an amount of data in blocking mode
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pTxData: pointer to transmission data buffer
* @param pRxData: pointer to reception data buffer to be
* @param Size: amount of data to be sent
@@ -871,7 +878,8 @@
/**
* @brief Transmit an amount of data in no-blocking mode with Interrupt
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @retval HAL status
@@ -945,7 +953,8 @@
/**
* @brief Receive an amount of data in no-blocking mode with Interrupt
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @retval HAL status
@@ -1023,7 +1032,8 @@
/**
* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pTxData: pointer to transmission data buffer
* @param pRxData: pointer to reception data buffer to be
* @param Size: amount of data to be sent
@@ -1095,7 +1105,8 @@
/**
* @brief Transmit an amount of data in no-blocking mode with DMA
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @retval HAL status
@@ -1173,7 +1184,8 @@
/**
* @brief Receive an amount of data in no-blocking mode with DMA
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @note When the CRC feature is enabled the pData Length must be Size + 1.
* @param Size: amount of data to be sent
@@ -1257,7 +1269,8 @@
/**
* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param pTxData: pointer to transmission data buffer
* @param pRxData: pointer to reception data buffer
* @note When the CRC feature is enabled the pRxData Length must be Size + 1
@@ -1360,7 +1373,8 @@
/**
* @brief This function handles SPI interrupt request.
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval HAL status
*/
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
@@ -1388,20 +1402,20 @@
if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
{
- /* SPI CRC error interrupt occured ---------------------------------------*/
+ /* SPI CRC error interrupt occurred ---------------------------------------*/
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
- /* SPI Mode Fault error interrupt occured --------------------------------*/
+ /* SPI Mode Fault error interrupt occurred --------------------------------*/
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
{
hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
__HAL_SPI_CLEAR_MODFFLAG(hspi);
}
- /* SPI Overrun error interrupt occured -----------------------------------*/
+ /* SPI Overrun error interrupt occurred -----------------------------------*/
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
{
if(hspi->State != HAL_SPI_STATE_BUSY_TX)
@@ -1411,7 +1425,7 @@
}
}
- /* SPI Frame error interrupt occured -------------------------------------*/
+ /* SPI Frame error interrupt occurred -------------------------------------*/
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
@@ -1429,7 +1443,8 @@
/**
* @brief Tx Transfer completed callbacks
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
@@ -1441,7 +1456,8 @@
/**
* @brief Rx Transfer completed callbacks
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
@@ -1453,7 +1469,8 @@
/**
* @brief Tx and Rx Transfer completed callbacks
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
@@ -1465,7 +1482,8 @@
/**
* @brief SPI error callbacks
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
@@ -1473,7 +1491,7 @@
/* NOTE : - This function Should not be modified, when the callback is needed,
the HAL_SPI_ErrorCallback() could be implenetd in the user file.
- The ErrorCode parameter in the hspi handle is updated by the SPI processes
- and user can use HAL_SPI_GetError() API to check the latest error occured.
+ and user can use HAL_SPI_GetError() API to check the latest error occurred.
*/
}
@@ -1498,8 +1516,9 @@
/**
* @brief Return the SPI state
- * @param hspi : SPI handle
- * @retval SPI state
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL state
*/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
{
@@ -1508,7 +1527,8 @@
/**
* @brief Return the SPI error code
- * @param hspi : SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval SPI Error Code
*/
HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
@@ -1522,7 +1542,8 @@
/**
* @brief Interrupt Handler to close Tx transfer
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval void
*/
static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
@@ -1582,7 +1603,8 @@
/**
* @brief Interrupt Handler to transmit amount of data in no-blocking mode
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval void
*/
static void SPI_TxISR(SPI_HandleTypeDef *hspi)
@@ -1613,7 +1635,8 @@
/**
* @brief Interrupt Handler to close Rx transfer
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval void
*/
static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
@@ -1690,7 +1713,8 @@
/**
* @brief Interrupt Handler to receive amount of data in 2Lines mode
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval void
*/
static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
@@ -1716,7 +1740,8 @@
/**
* @brief Interrupt Handler to receive amount of data in no-blocking mode
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval void
*/
static void SPI_RxISR(SPI_HandleTypeDef *hspi)
@@ -1749,7 +1774,8 @@
/**
* @brief DMA SPI transmit process complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
@@ -1794,7 +1820,8 @@
/**
* @brief DMA SPI receive process complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
@@ -1854,7 +1881,8 @@
/**
* @brief DMA SPI transmit receive process complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
@@ -1921,7 +1949,8 @@
/**
* @brief DMA SPI communication error callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
@@ -1936,7 +1965,8 @@
/**
* @brief This function handles SPI Communication Timeout.
- * @param hspi: SPI handle
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_spi.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_spi.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_spi.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -346,6 +346,13 @@ /* Exported macro ------------------------------------------------------------*/ +/** @brief Reset SPI handle state + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) + /** @brief Enable or disable the specified SPI interrupts. * @param __HANDLE__: specifies the SPI handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sram.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sram.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_sram.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
@@ -134,7 +134,8 @@
/**
* @brief Performs the SRAM device initialization sequence
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param Timing: Pointer to SRAM control timing structure
* @param ExtTiming: Pointer to SRAM extended mode timing structure
* @retval HAL status
@@ -170,7 +171,8 @@
/**
* @brief Performs the SRAM device De-initialization sequence.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
@@ -191,7 +193,8 @@
/**
* @brief SRAM MSP Init.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @retval None
*/
__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
@@ -203,7 +206,8 @@
/**
* @brief SRAM MSP DeInit.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @retval None
*/
__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
@@ -215,8 +219,9 @@
/**
* @brief DMA transfer complete callback.
- * @param hsram: pointer to SRAM handle
- * @retval none
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
*/
__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
{
@@ -227,8 +232,9 @@
/**
* @brief DMA transfer complete error callback.
- * @param hsram: pointer to SRAM handle
- * @retval none
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval None
*/
__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
{
@@ -257,7 +263,8 @@
/**
* @brief Reads 8-bit buffer from SRAM memory.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
@@ -292,7 +299,8 @@
/**
* @brief Writes 8-bit buffer to SRAM memory.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
@@ -333,7 +341,8 @@
/**
* @brief Reads 16-bit buffer from SRAM memory.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
@@ -368,7 +377,8 @@
/**
* @brief Writes 16-bit buffer to SRAM memory.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
@@ -409,7 +419,8 @@
/**
* @brief Reads 32-bit buffer from SRAM memory.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
@@ -442,7 +453,8 @@
/**
* @brief Writes 32-bit buffer to SRAM memory.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
@@ -481,7 +493,8 @@
/**
* @brief Reads a Words data from the SRAM memory using DMA transfer.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
@@ -513,7 +526,8 @@
/**
* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
@@ -570,7 +584,8 @@
/**
* @brief Enables dynamically SRAM write operation.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
@@ -592,7 +607,8 @@
/**
* @brief Disables dynamically SRAM write operation.
- * @param hsram: pointer to SRAM handle
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
@@ -636,8 +652,9 @@
/**
* @brief Returns the SRAM controller state
- * @param hsram: pointer to SRAM handle
- * @retval SRAM controller state
+ * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * the configuration information for SRAM module.
+ * @retval HAL state
*/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
{
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sram.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_sram.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_sram.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention @@ -97,8 +97,15 @@ }SRAM_HandleTypeDef; -/* Exported constants --------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset SRAM handle state + * @param __HANDLE__: SRAM handle + * @retval None + */ +#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) + /* Exported functions --------------------------------------------------------*/ /* Initialization/de-initialization functions **********************************/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_tim.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_tim.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_tim.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -193,7 +193,8 @@
/**
* @brief Initializes the TIM Time base Unit according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM Base handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
@@ -229,7 +230,8 @@
/**
* @brief DeInitializes the TIM Base peripheral
- * @param htim: TIM Base handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
@@ -256,7 +258,8 @@
/**
* @brief Initializes the TIM Base MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
@@ -268,7 +271,8 @@
/**
* @brief DeInitializes TIM Base MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
@@ -280,7 +284,8 @@
/**
* @brief Starts the TIM Base generation.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
@@ -303,7 +308,8 @@
/**
* @brief Stops the TIM Base generation.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
@@ -326,7 +332,8 @@
/**
* @brief Starts the TIM Base generation in interrupt mode.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
@@ -346,7 +353,8 @@
/**
* @brief Stops the TIM Base generation in interrupt mode.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
@@ -365,7 +373,8 @@
/**
* @brief Starts the TIM Base generation in DMA mode.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param pData: The source Buffer address.
* @param Length: The length of data to be transferred from memory to peripheral.
* @retval HAL status
@@ -411,7 +420,8 @@
/**
* @brief Stops the TIM Base generation in DMA mode.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
@@ -460,7 +470,8 @@
/**
* @brief Initializes the TIM Output Compare according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM Output Compare handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
@@ -496,7 +507,8 @@
/**
* @brief DeInitializes the TIM peripheral
- * @param htim: TIM Output Compare handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
@@ -523,7 +535,8 @@
/**
* @brief Initializes the TIM Output Compare MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
@@ -535,7 +548,8 @@
/**
* @brief DeInitializes TIM Output Compare MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
@@ -547,8 +561,9 @@
/**
* @brief Starts the TIM Output Compare signal generation.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -579,8 +594,9 @@
/**
* @brief Stops the TIM Output Compare signal generation.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -611,8 +627,9 @@
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode.
- * @param htim : TIM OC handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -677,8 +694,9 @@
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -743,8 +761,9 @@
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -862,8 +881,9 @@
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -957,7 +977,8 @@
/**
* @brief Initializes the TIM PWM Time Base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
@@ -993,7 +1014,8 @@
/**
* @brief DeInitializes the TIM peripheral
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
@@ -1020,7 +1042,8 @@
/**
* @brief Initializes the TIM PWM MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
@@ -1032,7 +1055,8 @@
/**
* @brief DeInitializes TIM PWM MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
@@ -1044,8 +1068,9 @@
/**
* @brief Starts the PWM signal generation.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1076,8 +1101,9 @@
/**
* @brief Stops the PWM signal generation.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1111,8 +1137,9 @@
/**
* @brief Starts the PWM signal generation in interrupt mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1177,8 +1204,9 @@
/**
* @brief Stops the PWM signal generation in interrupt mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1243,8 +1271,9 @@
/**
* @brief Starts the TIM PWM signal generation in DMA mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1362,8 +1391,9 @@
/**
* @brief Stops the TIM PWM signal generation in DMA mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1457,7 +1487,8 @@
/**
* @brief Initializes the TIM Input Capture Time base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM Input Capture handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
@@ -1493,7 +1524,8 @@
/**
* @brief DeInitializes the TIM peripheral
- * @param htim: TIM Input Capture handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
@@ -1520,7 +1552,8 @@
/**
* @brief Initializes the TIM INput Capture MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
@@ -1532,7 +1565,8 @@
/**
* @brief DeInitializes TIM Input Capture MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
@@ -1544,8 +1578,9 @@
/**
* @brief Starts the TIM Input Capture measurement.
- * @param hdma : TIM Input Capture handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1570,8 +1605,9 @@
/**
* @brief Stops the TIM Input Capture measurement.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1596,8 +1632,9 @@
/**
* @brief Starts the TIM Input Capture measurement in interrupt mode.
- * @param hdma : TIM Input Capture handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1655,8 +1692,9 @@
/**
* @brief Stops the TIM Input Capture measurement in interrupt mode.
- * @param htim : TIM handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1715,8 +1753,9 @@
/**
* @brief Starts the TIM Input Capture measurement on in DMA mode.
- * @param htim : TIM Input Capture handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1830,8 +1869,9 @@
/**
* @brief Stops the TIM Input Capture measurement on in DMA mode.
- * @param htim : TIM Input Capture handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1919,7 +1959,8 @@
/**
* @brief Initializes the TIM One Pulse Time Base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM OnePulse handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param OnePulseMode: Select the One pulse mode.
* This parameter can be one of the following values:
* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
@@ -1966,7 +2007,8 @@
/**
* @brief DeInitializes the TIM One Pulse
- * @param htim: TIM One Pulse handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
@@ -1993,7 +2035,8 @@
/**
* @brief Initializes the TIM One Pulse MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
@@ -2005,7 +2048,8 @@
/**
* @brief DeInitializes TIM One Pulse MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
@@ -2017,8 +2061,9 @@
/**
* @brief Starts the TIM One Pulse signal generation.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel : TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2050,8 +2095,9 @@
/**
* @brief Stops the TIM One Pulse signal generation.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channels to be disable
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel : TIM Channels to be disable.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2083,8 +2129,9 @@
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel : TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2122,8 +2169,9 @@
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel : TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2185,7 +2233,8 @@
*/
/**
* @brief Initializes the TIM Encoder Interface and create the associated handle.
- * @param htim: TIM Encoder Interface handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sConfig: TIM Encoder Interface configuration structure
* @retval HAL status
*/
@@ -2272,7 +2321,8 @@
/**
* @brief DeInitializes the TIM Encoder interface
- * @param htim: TIM Encoder handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
@@ -2299,7 +2349,8 @@
/**
* @brief Initializes the TIM Encoder Interface MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
@@ -2311,7 +2362,8 @@
/**
* @brief DeInitializes TIM Encoder Interface MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
@@ -2323,8 +2375,9 @@
/**
* @brief Starts the TIM Encoder Interface.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2364,8 +2417,9 @@
/**
* @brief Stops the TIM Encoder Interface.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2406,8 +2460,9 @@
/**
* @brief Starts the TIM Encoder Interface in interrupt mode.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2453,8 +2508,9 @@
/**
* @brief Stops the TIM Encoder Interface in interrupt mode.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2503,8 +2559,9 @@
/**
* @brief Starts the TIM Encoder Interface in DMA mode.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2622,8 +2679,9 @@
/**
* @brief Stops the TIM Encoder Interface in DMA mode.
- * @param htim : TIM Encoder Interface handle
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2688,7 +2746,8 @@
*/
/**
* @brief This function handles TIM interrupts requests.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
@@ -2844,9 +2903,10 @@
/**
* @brief Initializes the TIM Output Compare Channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim: TIM Output Compare handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sConfig: TIM Output Compare configuration structure
- * @param Channel : TIM Channels to be enabled
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2917,9 +2977,10 @@
/**
* @brief Initializes the TIM Input Capture Channels according to the specified
* parameters in the TIM_IC_InitTypeDef.
- * @param htim: TIM IC handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sConfig: TIM Input Capture configuration structure
- * @param Channel : TIM Channels to be enabled
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3013,9 +3074,10 @@
/**
* @brief Initializes the TIM PWM channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sConfig: TIM PWM configuration structure
- * @param Channel : TIM Channels to be enabled
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3113,13 +3175,14 @@
/**
* @brief Initializes the TIM One Pulse Channels according to the specified
* parameters in the TIM_OnePulse_InitTypeDef.
- * @param htim: TIM One Pulse handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sConfig: TIM One Pulse configuration structure
- * @param OutputChannel : TIM Channels to be enabled
+ * @param OutputChannel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @param InputChannel : TIM Channels to be enabled
+ * @param InputChannel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3225,8 +3288,9 @@
/**
* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
- * @param htim: TIM handle
- * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
* This parameters can be on of the following values:
* @arg TIM_DMABase_CR1
* @arg TIM_DMABase_CR2
@@ -3247,7 +3311,7 @@
* @arg TIM_DMABase_CCR4
* @arg TIM_DMABase_BDTR
* @arg TIM_DMABase_DCR
- * @param BurstRequestSrc: TIM DMA Request sources
+ * @param BurstRequestSrc: TIM DMA Request sources.
* This parameters can be on of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
@@ -3258,7 +3322,7 @@
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer: The Buffer address.
* @param BurstLength: DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
@@ -3388,7 +3452,8 @@
/**
* @brief Stops the TIM DMA Burst mode
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param BurstRequestSrc: TIM DMA Request sources to disable
* @retval HAL status
*/
@@ -3406,8 +3471,9 @@
/**
* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
- * @param htim: TIM handle
- * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
* This parameters can be on of the following values:
* @arg TIM_DMABase_CR1
* @arg TIM_DMABase_CR2
@@ -3428,7 +3494,7 @@
* @arg TIM_DMABase_CCR4
* @arg TIM_DMABase_BDTR
* @arg TIM_DMABase_DCR
- * @param BurstRequestSrc: TIM DMA Request sources
+ * @param BurstRequestSrc: TIM DMA Request sources.
* This parameters can be on of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
@@ -3439,7 +3505,7 @@
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer: The Buffer address.
* @param BurstLength: DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
@@ -3570,7 +3636,8 @@
/**
* @brief Stop the DMA burst reading
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param BurstRequestSrc: TIM DMA Request sources to disable.
* @retval HAL status
*/
@@ -3588,7 +3655,8 @@
/**
* @brief Generate a software event
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param EventSource: specifies the event source.
* This parameter can be one of the following values:
* @arg TIM_EventSource_Update: Timer update Event source
@@ -3630,15 +3698,16 @@
/**
* @brief Configures the OCRef clear feature
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
* contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel: specifies the TIM Channel
+ * @param Channel: specifies the TIM Channel.
* This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
@@ -3738,7 +3807,8 @@
/**
* @brief Configures the clock source to be used
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
@@ -3871,7 +3941,8 @@
/**
* @brief Selects the signal connected to the TI1 input: direct from CH1_input
* or a XOR combination between CH1_input, CH2_input & CH3_input
- * @param htim: TIM handle.
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module..
* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
* output of a XOR gate.
* This parameter can be one of the following values:
@@ -3905,7 +3976,8 @@
/**
* @brief Configures the TIM in Slave mode
- * @param htim: TIM handle.
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module..
* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
* timer input or external trigger input) and the ) and the Slave
@@ -4052,8 +4124,9 @@
/**
* @brief Read the captured value from Capture Compare unit
- * @param htim: TIM handle.
- * @param Channel : TIM Channels to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module..
+ * @param Channel: TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -4145,7 +4218,8 @@
/**
* @brief Period elapsed callback in non blocking mode
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
@@ -4157,7 +4231,8 @@
}
/**
* @brief Output Compare callback in non blocking mode
- * @param htim : TIM OC handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
@@ -4168,7 +4243,8 @@
}
/**
* @brief Input Capture callback in non blocking mode
- * @param htim : TIM IC handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
@@ -4180,7 +4256,8 @@
/**
* @brief PWM Pulse finished callback in non blocking mode
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
@@ -4192,7 +4269,8 @@
/**
* @brief Hall Trigger detection callback in non blocking mode
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
@@ -4204,7 +4282,8 @@
/**
* @brief Timer error callback in non blocking mode
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
@@ -4226,7 +4305,7 @@
##### Peripheral State functions #####
==============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -4235,7 +4314,8 @@
/**
* @brief Return the TIM Base state
- * @param htim: TIM Base handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
@@ -4245,7 +4325,8 @@
/**
* @brief Return the TIM OC state
- * @param htim: TIM Ouput Compare handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
@@ -4255,7 +4336,8 @@
/**
* @brief Return the TIM PWM state
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
@@ -4265,7 +4347,8 @@
/**
* @brief Return the TIM Input Capture state
- * @param htim: TIM IC handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
@@ -4275,7 +4358,8 @@
/**
* @brief Return the TIM One Pulse Mode state
- * @param htim: TIM OPM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
@@ -4285,7 +4369,8 @@
/**
* @brief Return the TIM Encoder Mode state
- * @param htim: TIM Encoder handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
@@ -4299,7 +4384,8 @@
/**
* @brief TIM DMA error callback
- * @param hdma : pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
@@ -4313,7 +4399,8 @@
/**
* @brief TIM DMA Delay Pulse complete callback.
- * @param hdma : pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
@@ -4326,7 +4413,8 @@
}
/**
* @brief TIM DMA Capture complete callback.
- * @param hdma : pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
@@ -4341,7 +4429,8 @@
/**
* @brief TIM DMA Period Elapse complete callback.
- * @param hdma : pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
@@ -4355,7 +4444,8 @@
/**
* @brief TIM DMA Trigger callback.
- * @param hdma : pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_tim.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_tim.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_tim.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
@@ -52,9 +52,9 @@
/** @addtogroup TIM
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/**
* @brief TIM Time base Configuration Structure definition
@@ -69,7 +69,7 @@
uint32_t Period; /*!< Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t ClockDivision; /*!< Specifies the clock division.
This parameter can be a value of @ref TIM_ClockDivision */
@@ -89,12 +89,12 @@
*/
typedef struct
-{
+{
uint32_t OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
@@ -121,12 +121,12 @@
* @brief TIM One Pulse Mode Configuration Structure definition
*/
typedef struct
-{
+{
uint32_t OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
@@ -159,7 +159,7 @@
*/
typedef struct
-{
+{
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -204,7 +204,7 @@
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC2Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_Encoder_InitTypeDef;
/**
@@ -212,14 +212,14 @@
*/
typedef struct
{
- uint32_t ClockSource; /*!< TIM clock sources
+ uint32_t ClockSource; /*!< TIM clock sources.
This parameter can be a value of @ref TIM_Clock_Source */
- uint32_t ClockPolarity; /*!< TIM clock polarity
+ uint32_t ClockPolarity; /*!< TIM clock polarity.
This parameter can be a value of @ref TIM_Clock_Polarity */
- uint32_t ClockPrescaler; /*!< TIM clock prescaler
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler.
This parameter can be a value of @ref TIM_Clock_Prescaler */
- uint32_t ClockFilter; /*!< TIM clock filter
- This parameter can be a value of @ref TIM_Clock_Filter */
+ uint32_t ClockFilter; /*!< TIM clock filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
}TIM_ClockConfigTypeDef;
/**
@@ -227,16 +227,16 @@
*/
typedef struct
{
- uint32_t ClearInputState; /*!< TIM clear Input state
+ uint32_t ClearInputState; /*!< TIM clear Input state.
This parameter can be ENABLE or DISABLE */
- uint32_t ClearInputSource; /*!< TIM clear Input sources
+ uint32_t ClearInputSource; /*!< TIM clear Input sources.
This parameter can be a value of @ref TIM_ClearInput_Source */
- uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
This parameter can be a value of @ref TIM_ClearInput_Polarity */
- uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
This parameter can be a value of @ref TIM_ClearInput_Prescaler */
- uint32_t ClearInputFilter; /*!< TIM Clear Input filter
- This parameter can be a value of @ref TIM_ClearInput_Filter */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
}TIM_ClearInputConfigTypeDef;
/**
@@ -252,7 +252,7 @@
uint32_t TriggerPrescaler; /*!< Input trigger prescaler
This parameter can be a value of @ref TIM_Trigger_Prescaler */
uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a value of @ref TIM_Trigger_Filter */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
}TIM_SlaveConfigTypeDef;
@@ -263,9 +263,9 @@
{
HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
- HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+ HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
}HAL_TIM_StateTypeDef;
/**
@@ -275,9 +275,9 @@
{
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
}HAL_TIM_ActiveChannel;
/**
@@ -285,13 +285,13 @@
*/
typedef struct
{
- TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
}TIM_HandleTypeDef;
/* Exported constants --------------------------------------------------------*/
@@ -312,15 +312,15 @@
/** @defgroup TIM_ETR_Polarity
* @{
*/
-#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
/**
* @}
*/
/** @defgroup TIM_ETR_Prescaler
* @{
- */
+ */
#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
@@ -332,7 +332,6 @@
/** @defgroup TIM_Counter_Mode
* @{
*/
-
#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
@@ -346,12 +345,11 @@
((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
/**
* @}
- */
-
+ */
+
/** @defgroup TIM_ClockDivision
* @{
*/
-
#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
@@ -366,7 +364,6 @@
/** @defgroup TIM_Output_Compare_and_PWM_modes
* @{
*/
-
#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
@@ -392,7 +389,6 @@
/** @defgroup TIM_Output_Compare_State
* @{
*/
-
#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
@@ -400,7 +396,8 @@
((STATE) == TIM_OUTPUTSTATE_ENABLE))
/**
* @}
- */
+ */
+
/** @defgroup TIM_Output_Fast_State
* @{
*/
@@ -411,11 +408,11 @@
((STATE) == TIM_OCFAST_ENABLE))
/**
* @}
- */
+ */
+
/** @defgroup TIM_Output_Compare_N_State
* @{
*/
-
#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
@@ -424,11 +421,10 @@
/**
* @}
*/
-
+
/** @defgroup TIM_Output_Compare_Polarity
* @{
*/
-
#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
@@ -441,7 +437,6 @@
/** @defgroup TIM_Output_Compare_N_Polarity
* @{
*/
-
#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
@@ -454,7 +449,6 @@
/** @defgroup TIM_Output_Compare_Idle_State
* @{
*/
-
#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
@@ -466,7 +460,6 @@
/** @defgroup TIM_Output_Compare_N_Idle_State
* @{
*/
-
#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
@@ -478,7 +471,6 @@
/** @defgroup TIM_Channel
* @{
*/
-
#define TIM_CHANNEL_1 ((uint32_t)0x0000)
#define TIM_CHANNEL_2 ((uint32_t)0x0004)
#define TIM_CHANNEL_3 ((uint32_t)0x0008)
@@ -495,35 +487,32 @@
((CHANNEL) == TIM_CHANNEL_2))
#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
+ ((CHANNEL) == TIM_CHANNEL_2))
#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))
/**
* @}
- */
-
+ */
/** @defgroup TIM_Input_Capture_Polarity
* @{
*/
-
#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
-
+
#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
((POLARITY) == TIM_ICPOLARITY_FALLING) || \
((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
/**
* @}
- */
+ */
/** @defgroup TIM_Input_Capture_Selection
* @{
*/
-
#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
@@ -535,12 +524,11 @@
((SELECTION) == TIM_ICSELECTION_TRC))
/**
* @}
- */
+ */
/** @defgroup TIM_Input_Capture_Prescaler
* @{
*/
-
#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
@@ -557,17 +545,17 @@
/** @defgroup TIM_One_Pulse_Mode
* @{
*/
-
#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
((MODE) == TIM_OPMODE_REPETITIVE))
/**
* @}
- */
+ */
+
/** @defgroup TIM_Encoder_Mode
* @{
- */
+ */
#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
@@ -576,7 +564,8 @@
((MODE) == TIM_ENCODERMODE_TI12))
/**
* @}
- */
+ */
+
/** @defgroup TIM_Interrupt_definition
* @{
*/
@@ -598,17 +587,14 @@
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_COM) || \
((IT) == TIM_IT_TRIGGER) || \
- ((IT) == TIM_IT_BREAK))
+ ((IT) == TIM_IT_BREAK))
/**
* @}
*/
-#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
/** @defgroup TIM_DMA_sources
* @{
*/
-
#define TIM_DMA_UPDATE (TIM_DIER_UDE)
#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
@@ -617,15 +603,13 @@
#define TIM_DMA_COM (TIM_DIER_COMDE)
#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
-
/**
* @}
*/
-
+
/** @defgroup TIM_Event_Source
* @{
*/
-
#define TIM_EventSource_Update TIM_EGR_UG
#define TIM_EventSource_CC1 TIM_EGR_CC1G
#define TIM_EventSource_CC2 TIM_EGR_CC2G
@@ -634,16 +618,14 @@
#define TIM_EventSource_COM TIM_EGR_COMG
#define TIM_EventSource_Trigger TIM_EGR_TG
#define TIM_EventSource_Break TIM_EGR_BG
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
-
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
/**
* @}
- */
+ */
/** @defgroup TIM_Flag_definition
* @{
- */
-
+ */
#define TIM_FLAG_UPDATE (TIM_SR_UIF)
#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
@@ -668,14 +650,14 @@
((FLAG) == TIM_FLAG_CC1OF) || \
((FLAG) == TIM_FLAG_CC2OF) || \
((FLAG) == TIM_FLAG_CC3OF) || \
- ((FLAG) == TIM_FLAG_CC4OF))
+ ((FLAG) == TIM_FLAG_CC4OF))
/**
* @}
*/
/** @defgroup TIM_Clock_Source
* @{
- */
+ */
#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
@@ -699,7 +681,7 @@
((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
/**
* @}
- */
+ */
/** @defgroup TIM_Clock_Polarity
* @{
@@ -718,9 +700,10 @@
/**
* @}
*/
+
/** @defgroup TIM_Clock_Prescaler
* @{
- */
+ */
#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
@@ -732,15 +715,15 @@
((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
/**
* @}
- */
+ */
+
/** @defgroup TIM_Clock_Filter
* @{
*/
-
#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
/**
* @}
- */
+ */
/** @defgroup TIM_ClearInput_Source
* @{
@@ -763,7 +746,7 @@
((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
/**
* @}
- */
+ */
/** @defgroup TIM_ClearInput_Prescaler
* @{
@@ -779,113 +762,15 @@
/**
* @}
*/
-
+
/** @defgroup TIM_ClearInput_Filter
* @{
*/
-
#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
/**
* @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
- * @{
- */
-#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
- ((STATE) == TIM_OSSR_DISABLE))
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
- * @{
- */
-#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
- ((STATE) == TIM_OSSI_DISABLE))
-/**
- * @}
*/
-/** @defgroup TIM_Lock_level
- * @{
- */
-#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
-#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
- ((LEVEL) == TIM_LOCKLEVEL_1) || \
- ((LEVEL) == TIM_LOCKLEVEL_2) || \
- ((LEVEL) == TIM_LOCKLEVEL_3))
-/**
- * @}
- */
-/** @defgroup TIM_Break_Input_enable_disable
- * @{
- */
-#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
- ((STATE) == TIM_BREAK_DISABLE))
-/**
- * @}
- */
-/** @defgroup TIM_Break_Polarity
- * @{
- */
-#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
-#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
-
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
- ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
-/**
- * @}
- */
-/** @defgroup TIM_AOE_Bit_Set_Reset
- * @{
- */
-#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
-#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Mode_Selection
- * @{
- */
-#define TIM_TRGO_RESET ((uint32_t)0x0000)
-#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
-#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
-#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
-#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
- ((SOURCE) == TIM_TRGO_ENABLE) || \
- ((SOURCE) == TIM_TRGO_UPDATE) || \
- ((SOURCE) == TIM_TRGO_OC1) || \
- ((SOURCE) == TIM_TRGO_OC1REF) || \
- ((SOURCE) == TIM_TRGO_OC2REF) || \
- ((SOURCE) == TIM_TRGO_OC3REF) || \
- ((SOURCE) == TIM_TRGO_OC4REF))
-
-
-/**
- * @}
- */
/** @defgroup TIM_Slave_Mode
* @{
*/
@@ -902,23 +787,11 @@
((MODE) == TIM_SLAVEMODE_EXTERNAL1))
/**
* @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode
- * @{
*/
-#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
-#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
-/**
- * @}
- */
/** @defgroup TIM_Trigger_Selection
* @{
*/
-
#define TIM_TS_ITR0 ((uint32_t)0x0000)
#define TIM_TS_ITR1 ((uint32_t)0x0010)
#define TIM_TS_ITR2 ((uint32_t)0x0020)
@@ -969,7 +842,7 @@
/** @defgroup TIM_Trigger_Prescaler
* @{
- */
+ */
#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
@@ -986,30 +859,26 @@
/** @defgroup TIM_Trigger_Filter
* @{
*/
-
#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
/**
* @}
- */
+ */
/** @defgroup TIM_TI1_Selection
* @{
*/
-
#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
-
/**
* @}
*/
-
+
/** @defgroup TIM_DMA_Base_address
* @{
*/
-
#define TIM_DMABase_CR1 (0x00000000)
#define TIM_DMABase_CR2 (0x00000001)
#define TIM_DMABase_SMCR (0x00000002)
@@ -1049,7 +918,7 @@
((BASE) == TIM_DMABase_CCR4) || \
((BASE) == TIM_DMABase_BDTR) || \
((BASE) == TIM_DMABase_DCR) || \
- ((BASE) == TIM_DMABase_OR))
+ ((BASE) == TIM_DMABase_OR))
/**
* @}
*/
@@ -1057,7 +926,6 @@
/** @defgroup TIM_DMA_Burst_Length
* @{
*/
-
#define TIM_DMABurstLength_1Transfer (0x00000000)
#define TIM_DMABurstLength_2Transfers (0x00000100)
#define TIM_DMABurstLength_3Transfers (0x00000200)
@@ -1096,11 +964,11 @@
((LENGTH) == TIM_DMABurstLength_18Transfers))
/**
* @}
- */
+ */
+
/** @defgroup TIM_Input_Capture_Filer_Value
* @{
*/
-
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
/**
* @}
@@ -1137,6 +1005,12 @@
/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset TIM handle state
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+
/**
* @brief Enable the TIM peripheral.
* @param __HANDLE__: TIM handle
@@ -1173,8 +1047,8 @@
} \
} while(0)
-/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
+/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
/**
* @brief Disable the TIM main Output.
* @param __HANDLE__: TIM handle
@@ -1189,7 +1063,7 @@
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \
} \
- } while(0)
+ } while(0)
#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
@@ -1215,7 +1089,7 @@
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
-
+
/**
* @brief Sets the TIM Capture Compare Register value on runtime without
* calling another time ConfigChannel function.
@@ -1233,12 +1107,33 @@
(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
/**
+ * @brief Gets the TIM Capture Compare Register value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @retval None
+ */
+#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
+ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
+
+/**
* @brief Sets the TIM Counter Register value on runtime.
* @param __HANDLE__: TIM handle.
* @param __COUNTER__: specifies the Counter register new value.
* @retval None
*/
-#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+ * @brief Gets the TIM Counter Register value on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GetCounter(__HANDLE__) ((__HANDLE__)->Instance->CNT)
/**
* @brief Sets the TIM Autoreload Register value on runtime without calling
@@ -1247,11 +1142,17 @@
* @param __AUTORELOAD__: specifies the Counter register new value.
* @retval None
*/
-#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
} while(0)
+/**
+ * @brief Gets the TIM Autoreload Register value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GetAutoreload(__HANDLE__) ((__HANDLE__)->Instance->ARR)
/**
* @brief Sets the TIM Clock Division value on runtime without calling
@@ -1261,16 +1162,22 @@
* This parameter can be one of the following value:
* @arg TIM_CLOCKDIVISION_DIV1
* @arg TIM_CLOCKDIVISION_DIV2
- * @arg TIM_CLOCKDIVISION_DIV4
+ * @arg TIM_CLOCKDIVISION_DIV4
* @retval None
*/
#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
- do{ \
+ do{ \
(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
(__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0)
-
+/**
+ * @brief Gets the TIM Clock Division value on runtime
+ * @param __HANDLE__: TIM handle.
+ * @retval None
+ */
+#define __HAL_TIM_GetClockDivision(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
/**
* @brief Sets the TIM Input Capture prescaler on runtime without calling
* another time HAL_TIM_IC_ConfigChannel() function.
@@ -1293,9 +1200,25 @@
do{ \
__HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
__HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0)
+ } while(0)
/**
+ * @brief Gets the TIM Input Capture prescaler on runtime
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__ : TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+ * @retval None
+ */
+#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
+/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_tim_ex.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_tim_ex.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer extension peripheral:
@@ -145,7 +145,8 @@
*/
/**
* @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
- * @param htim: TIM Encoder Interface handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sConfig: TIM Hall Sensor configuration structure
* @retval HAL status
*/
@@ -218,7 +219,8 @@
/**
* @brief DeInitializes the TIM Hall Sensor interface
- * @param htim: TIM Hall Sensor handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
@@ -245,7 +247,8 @@
/**
* @brief Initializes the TIM Hall Sensor MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
@@ -257,7 +260,8 @@
/**
* @brief DeInitializes TIM Hall Sensor MSP.
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
@@ -269,7 +273,8 @@
/**
* @brief Starts the TIM Hall Sensor Interface.
- * @param htim : TIM Hall Sensor handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
@@ -290,7 +295,8 @@
/**
* @brief Stops the TIM Hall sensor Interface.
- * @param htim : TIM Hall Sensor handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
@@ -311,7 +317,8 @@
/**
* @brief Starts the TIM Hall Sensor Interface in interrupt mode.
- * @param htim : TIM Hall Sensor handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
@@ -335,7 +342,8 @@
/**
* @brief Stops the TIM Hall Sensor Interface in interrupt mode.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
@@ -359,7 +367,8 @@
/**
* @brief Starts the TIM Hall Sensor Interface in DMA mode.
- * @param htim : TIM Hall Sensor handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param pData: The destination Buffer address.
* @param Length: The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
@@ -408,7 +417,8 @@
/**
* @brief Stops the TIM Hall Sensor Interface in DMA mode.
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
@@ -458,13 +468,14 @@
/**
* @brief Starts the TIM Output Compare signal generation on the complementary
* output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * TIM_CHANNEL_1/
+ * TIM_CHANNEL_2/
+ * TIM_CHANNEL_3/
+ * TIM_CHANNEL_4
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -488,13 +499,14 @@
/**
* @brief Stops the TIM Output Compare signal generation on the complementary
* output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * TIM_CHANNEL_1/
+ * TIM_CHANNEL_2/
+ * TIM_CHANNEL_3/
+ * TIM_CHANNEL_4
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -518,13 +530,14 @@
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
- * @param htim : TIM OC handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * TIM_CHANNEL_1/
+ * TIM_CHANNEL_2/
+ * TIM_CHANNEL_3/
+ * TIM_CHANNEL_4
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -582,13 +595,14 @@
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * TIM_CHANNEL_1/
+ * TIM_CHANNEL_2/
+ * TIM_CHANNEL_3/
+ * TIM_CHANNEL_4
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -646,13 +660,14 @@
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode
* on the complementary output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * TIM_CHANNEL_1/
+ * TIM_CHANNEL_2/
+ * TIM_CHANNEL_3/
+ * TIM_CHANNEL_4
* @param pData: The source Buffer address.
* @param Length: The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
@@ -763,13 +778,14 @@
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode
* on the complementary output.
- * @param htim : TIM Output Compare handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * TIM_CHANNEL_1/
+ * TIM_CHANNEL_2/
+ * TIM_CHANNEL_3/
+ * TIM_CHANNEL_4
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -863,13 +879,14 @@
/**
* @brief Starts the PWM signal generation on the complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * TIM_CHANNEL_1/
+ * TIM_CHANNEL_2/
+ * TIM_CHANNEL_3/
+ * TIM_CHANNEL_4
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -892,13 +909,14 @@
/**
* @brief Stops the PWM signal generation on the complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * TIM_CHANNEL_1/
+ * TIM_CHANNEL_2/
+ * TIM_CHANNEL_3/
+ * TIM_CHANNEL_4
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -922,13 +940,14 @@
/**
* @brief Starts the PWM signal generation in interrupt mode on the
* complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * TIM_CHANNEL_1/
+ * TIM_CHANNEL_2/
+ * TIM_CHANNEL_3/
+ * TIM_CHANNEL_4
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -989,13 +1008,14 @@
/**
* @brief Stops the PWM signal generation in interrupt mode on the
* complementary output.
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * TIM_CHANNEL_1/
+ * TIM_CHANNEL_2/
+ * TIM_CHANNEL_3/
+ * TIM_CHANNEL_4
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -1056,13 +1076,14 @@
/**
* @brief Starts the TIM PWM signal generation in DMA mode on the
* complementary output
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * TIM_CHANNEL_1/
+ * TIM_CHANNEL_2/
+ * TIM_CHANNEL_3/
+ * TIM_CHANNEL_4
* @param pData: The source Buffer address.
* @param Length: The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
@@ -1173,13 +1194,14 @@
/**
* @brief Stops the TIM PWM signal generation in DMA mode on the complementary
* output
- * @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param Channel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * TIM_CHANNEL_1/
+ * TIM_CHANNEL_2/
+ * TIM_CHANNEL_3/
+ * TIM_CHANNEL_4
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -1262,11 +1284,12 @@
/**
* @brief Starts the TIM One Pulse signal generation on the complemetary
* output.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * TIM_CHANNEL_1 /
+ * IM_CHANNEL_2
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -1287,11 +1310,11 @@
/**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * TIM_CHANNEL_1 / TIM_CHANNEL_2
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -1316,11 +1339,11 @@
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be enabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel: TIM Channel to be enabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * TIM_CHANNEL_1 / IM_CHANNEL_2
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -1347,11 +1370,11 @@
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @param htim : TIM One Pulse handle
- * @param OutputChannel : TIM Channel to be disabled
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param OutputChannel: TIM Channel to be disabled.
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * TIM_CHANNEL_1 / IM_CHANNEL_2
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
@@ -1402,21 +1425,22 @@
*/
/**
* @brief Configure the TIM commutation event sequence.
- * @note: this function is mandatory to use the commutation event in order to
+ * @note This function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
* the typical use of this feature is with the use of another Timer(interface Timer)
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim: TIM handle
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource : the Commutation Event source
+ * TIM_TS_ITR0 /
+ * TIM_TS_ITR1 /
+ * TIM_TS_ITR2 /
+ * TIM_TS_ITR3 /
+ * TIM_TS_NONE
+ * @param CommutationSource: the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
@@ -1451,21 +1475,22 @@
/**
* @brief Configure the TIM commutation event sequence with interrupt.
- * @note: this function is mandatory to use the commutation event in order to
+ * @note This function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
* the typical use of this feature is with the use of another Timer(interface Timer)
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim: TIM handle
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource : the Commutation Event source
+ * TIM_TS_ITR0 /
+ * TIM_TS_ITR1 /
+ * TIM_TS_ITR2 /
+ * TIM_TS_ITR3 /
+ * TIM_TS_NONE
+ * @param CommutationSource: the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
@@ -1503,22 +1528,23 @@
/**
* @brief Configure the TIM commutation event sequence with DMA.
- * @note: this function is mandatory to use the commutation event in order to
+ * @note This function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
* the typical use of this feature is with the use of another Timer(interface Timer)
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
* @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
- * @param htim: TIM handle
- * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal trigger 0 selected
- * @arg TIM_TS_ITR1: Internal trigger 1 selected
- * @arg TIM_TS_ITR2: Internal trigger 2 selected
- * @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource : the Commutation Event source
+ * TIM_TS_ITR0 /
+ * TIM_TS_ITR1 /
+ * TIM_TS_ITR2 /
+ * TIM_TS_ITR3 /
+ * TIM_TS_NONE
+ * @param CommutationSource: the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
@@ -1562,7 +1588,8 @@
/**
* @brief Configures the TIM in master mode.
- * @param htim: TIM handle.
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
* contains the selected trigger output (TRGO) and the Master/Slave
* mode.
@@ -1599,7 +1626,8 @@
/**
* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
* and the AOE(automatic output enable).
- * @param htim: TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
* @retval HAL status
@@ -1641,7 +1669,8 @@
/**
* @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
- * @param htim: TIM handle.
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module..
* @param TIM_Remap: specifies the TIM input remapping source.
* This parameter can be one of the following values:
* @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
@@ -1697,7 +1726,8 @@
/**
* @brief Hall commutation changed callback in non blocking mode
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
@@ -1709,7 +1739,8 @@
/**
* @brief Hall Break detection callback in non blocking mode
- * @param htim : TIM handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
@@ -1731,7 +1762,7 @@
##### Extension Peripheral State functions #####
==============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1740,7 +1771,8 @@
/**
* @brief Return the TIM Hall Sensor interface state
- * @param htim: TIM Hall Sensor handle
+ * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
@@ -1754,7 +1786,8 @@
/**
* @brief TIM DMA Commutation callback.
- * @param hdma : pointer to DMA handle.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_tim_ex.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_tim_ex.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_tim_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention
@@ -79,10 +79,10 @@
* @brief TIM Master configuration Structure definition
*/
typedef struct {
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
- This parameter can be a value of @ref TIM_Master_Mode_Selection */
- uint32_t MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref TIM_Master_Slave_Mode */
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection.
+ This parameter can be a value of @ref TIMEx_Master_Mode_Selection */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection.
+ This parameter can be a value of @ref TIMEx_Master_Slave_Mode */
}TIM_MasterConfigTypeDef;
/**
@@ -90,27 +90,145 @@
*/
typedef struct
{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level
- This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode.
+ This parameter can be a value of @ref TIMEx_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
+ This parameter can be a value of @ref TIMEx_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level.
+ This parameter can be a value of @ref TIMEx_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time.
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint32_t BreakState; /*!< TIM Break State
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity
- This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+ uint32_t BreakState; /*!< TIM Break State.
+ This parameter can be a value of @ref TIMEx_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity.
+ This parameter can be a value of @ref TIMEx_Break_Polarity */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
+ This parameter can be a value of @ref TIMEx_AOE_Bit_Set_Reset */
}TIM_BreakDeadTimeConfigTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants
* @{
*/
+/** @defgroup TIMEx_OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
+#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
+ ((STATE) == TIM_OSSR_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
+#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
+ ((STATE) == TIM_OSSI_DISABLE))
+/**
+ * @}
+ */
+/** @defgroup TIMEx_Lock_level
+ * @{
+ */
+#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
+#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
+#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
+#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
+
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
+ ((LEVEL) == TIM_LOCKLEVEL_1) || \
+ ((LEVEL) == TIM_LOCKLEVEL_2) || \
+ ((LEVEL) == TIM_LOCKLEVEL_3))
+/**
+ * @}
+ */
+/** @defgroup TIMEx_Break_Input_enable_disable
+ * @{
+ */
+#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
+#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
+ ((STATE) == TIM_BREAK_DISABLE))
+/**
+ * @}
+ */
+/** @defgroup TIMEx_Break_Polarity
+ * @{
+ */
+#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
+#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
+
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
+ ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
+/**
+ * @}
+ */
+/** @defgroup TIMEx_AOE_Bit_Set_Reset
+ * @{
+ */
+#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
+#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Master_Mode_Selection
+ * @{
+ */
+#define TIM_TRGO_RESET ((uint32_t)0x0000)
+#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
+#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
+#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
+#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
+#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
+ ((SOURCE) == TIM_TRGO_ENABLE) || \
+ ((SOURCE) == TIM_TRGO_UPDATE) || \
+ ((SOURCE) == TIM_TRGO_OC1) || \
+ ((SOURCE) == TIM_TRGO_OC1REF) || \
+ ((SOURCE) == TIM_TRGO_OC2REF) || \
+ ((SOURCE) == TIM_TRGO_OC3REF) || \
+ ((SOURCE) == TIM_TRGO_OC4REF))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
+#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Commutation_Mode
+ * @{
+ */
+#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
+#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
+/**
+ * @}
+ */
+
/** @defgroup TIMEx_Remap
* @{
*/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_uart.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_uart.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_uart.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -21,7 +21,7 @@
(#) Declare a UART_HandleTypeDef handle structure.
- (#) Initialize the UART low level resources by implement the HAL_UART_MspInit() API:
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
(##) Enable the USARTx interface clock.
(##) UART pins configuration:
(+++) Enable the clock for the UART GPIOs.
@@ -42,7 +42,7 @@
interrupt on the DMA Tx/Rx Stream.
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) in the huart Init structure.
+ flow control and Mode(Receiver/Transmitter) in the Init structure.
(#) For the UART asynchronous mode, initialize the UART registers by calling
the HAL_UART_Init() API.
@@ -55,16 +55,19 @@
(#) For the Multi-Processor mode, initialize the UART registers by calling
the HAL_MultiProcessor_Init() API.
- -@- The specific UART interrupts (Transmission complete interrupt,
+ [..]
+ (@) The specific UART interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
and receive process.
- -@- These API's(HAL_UART_Init() and HAL_HalfDuplex_Init()) configures also the
+ [..]
+ (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed
HAL_UART_MspInit() API.
- (#) Three mode of operations are available within this driver :
+ [..]
+ Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -114,10 +117,10 @@
(+) __HAL_UART_ENABLE: Enable the UART peripheral
(+) __HAL_UART_DISABLE: Disable the UART peripheral
- (+) __HAL_UART_GET_FLAG : Checks whether the specified UART flag is set or not
- (+) __HAL_UART_CLEAR_FLAG : Clears the specified UART pending flag
- (+) __HAL_UART_ENABLE_IT: Enables the specified UART interrupt
- (+) __HAL_UART_DISABLE_IT: Disables the specified UART interrupt
+ (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
+ (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
+ (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
+ (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
[..]
(@) You can refer to the UART HAL driver header file for more useful macros
@@ -205,18 +208,7 @@
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible UART frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | UART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
+ please refer to Reference manual for possible UART frame formats.
(++) Hardware flow control
(++) Receiver/transmitter modes
(++) Over Sampling Methode
@@ -232,7 +224,8 @@
/**
* @brief Initializes the UART mode according to the specified parameters in
* the UART_InitTypeDef and create the associated handle.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
@@ -259,9 +252,9 @@
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
-
- huart->State = HAL_UART_STATE_BUSY;
-
+
+ huart->State = HAL_UART_STATE_BUSY;
+
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
@@ -287,7 +280,8 @@
/**
* @brief Initializes the half-duplex mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
@@ -303,7 +297,9 @@
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
-
+
+ huart->State = HAL_UART_STATE_BUSY;
+
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
@@ -332,7 +328,8 @@
/**
* @brief Initializes the LIN mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param BreakDetectLength: Specifies the LIN break detection length.
* This parameter can be one of the following values:
* @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
@@ -354,7 +351,9 @@
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
-
+
+ huart->State = HAL_UART_STATE_BUSY;
+
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
@@ -387,7 +386,8 @@
/**
* @brief Initializes the Multi-Processor mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param Address: USART address
* @param WakeUpMethode: specifies the USART wakeup method.
* This parameter can be one of the following values:
@@ -412,7 +412,9 @@
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
-
+
+ huart->State = HAL_UART_STATE_BUSY;
+
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
@@ -446,7 +448,8 @@
/**
* @brief DeInitializes the UART peripheral.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
@@ -476,7 +479,8 @@
/**
* @brief UART MSP Init.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
@@ -488,7 +492,8 @@
/**
* @brief UART MSP DeInit.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
@@ -517,7 +522,7 @@
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
- (++) Non-Blocking mode: The communication is performed using Interrupts
+ (++) Non blocking mode: The communication is performed using Interrupts
or DMA, these APIs return the HAL status.
The end of the data processing will be indicated through the
dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
@@ -527,20 +532,20 @@
The HAL_UART_ErrorCallback() user callback will be executed when
a communication error is detected.
- (#) Blocking mode API's are:
+ (#) Blocking mode APIs are:
(++) HAL_UART_Transmit()
(++) HAL_UART_Receive()
- (#) Non-Blocking mode API's with Interrupt are:
+ (#) Non Blocking mode APIs with Interrupt are:
(++) HAL_UART_Transmit_IT()
(++) HAL_UART_Receive_IT()
(++) HAL_UART_IRQHandler()
- (#) No-Blocking mode functions with DMA are:
+ (#) Non Blocking mode functions with DMA are:
(++) HAL_UART_Transmit_DMA()
(++) HAL_UART_Receive_DMA()
- (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
(++) HAL_UART_TxCpltCallback()
(++) HAL_UART_RxCpltCallback()
(++) HAL_UART_ErrorCallback()
@@ -556,7 +561,8 @@
/**
* @brief Sends an amount of data in blocking mode.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@@ -649,7 +655,8 @@
/**
* @brief Receives an amount of data in blocking mode.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @param Timeout: Timeout duration
@@ -748,7 +755,8 @@
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -805,7 +813,8 @@
/**
* @brief Receives an amount of data in non blocking mode
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @retval HAL status
@@ -862,7 +871,8 @@
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -928,7 +938,8 @@
/**
* @brief Receives an amount of data in non blocking mode.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
* @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
@@ -954,7 +965,7 @@
huart->RxXferSize = Size;
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Check if a transmit rocess is ongoing or not */
+ /* Check if a transmit process is ongoing or not */
if(huart->State == HAL_UART_STATE_BUSY_TX)
{
huart->State = HAL_UART_STATE_BUSY_TX_RX;
@@ -994,8 +1005,9 @@
/**
* @brief Pauses the DMA Transfer.
- * @param huart: UART handle
- * @retval None
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
{
@@ -1027,8 +1039,9 @@
/**
* @brief Resumes the DMA Transfer.
- * @param huart: UART handle
- * @retval None
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{
@@ -1067,8 +1080,9 @@
/**
* @brief Stops the DMA Transfer.
- * @param huart: UART handle
- * @retval None
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
{
@@ -1102,7 +1116,8 @@
/**
* @brief This function handles UART interrupt request.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
@@ -1178,7 +1193,8 @@
/**
* @brief Tx Transfer completed callbacks.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
@@ -1190,7 +1206,8 @@
/**
* @brief Tx Half Transfer completed callbacks.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
@@ -1202,7 +1219,8 @@
/**
* @brief Rx Transfer completed callbacks.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
@@ -1214,7 +1232,8 @@
/**
* @brief Rx Half Transfer completed callbacks.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
@@ -1226,7 +1245,8 @@
/**
* @brief UART error callbacks.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
@@ -1259,7 +1279,8 @@
/**
* @brief Transmits break characters.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
@@ -1285,7 +1306,8 @@
/**
* @brief Enters the UART in mute mode.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
@@ -1311,7 +1333,8 @@
/**
* @brief Exits the UART mute mode: wake up software.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
@@ -1337,9 +1360,9 @@
/**
* @brief Enables the UART transmitter and disables the UART receiver.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
- * @retval None
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
{
@@ -1372,7 +1395,8 @@
/**
* @brief Enables the UART receiver and disables the UART transmitter.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
@@ -1417,10 +1441,10 @@
==============================================================================
[..]
This subsection provides a set of functions allowing to return the State of
- UART communication process, return Peripheral Errors occured during communication
+ UART communication process, return Peripheral Errors occurred during communication
process
(+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
- (+) HAL_UART_GetError() check in run-time errors that could be occured durung communication.
+ (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.
@endverbatim
* @{
@@ -1428,7 +1452,8 @@
/**
* @brief Returns the UART state.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL state
*/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
@@ -1468,7 +1493,7 @@
/* Wait for UART TC Flag */
if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK)
{
- /* Timeout Occured */
+ /* Timeout occurred */
huart->State = HAL_UART_STATE_TIMEOUT;
HAL_UART_ErrorCallback(huart);
}
@@ -1490,7 +1515,8 @@
/**
* @brief DMA UART transmit process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1528,7 +1554,8 @@
/**
* @brief DMA UART receive process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1555,7 +1582,8 @@
/**
* @brief This function handles UART Communication Timeout.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @param Flag: specifies the UART flag to check.
* @param Status: The new Flag status (SET or RESET).
* @param Timeout: Timeout duration
@@ -1623,7 +1651,8 @@
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
@@ -1634,9 +1663,6 @@
tmp1 = huart->State;
if((tmp1 == HAL_UART_STATE_BUSY_TX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX))
{
- /* Process Locked */
- __HAL_LOCK(huart);
-
if(huart->Init.WordLength == UART_WORDLENGTH_9B)
{
tmp = (uint16_t*) huart->pTxBuffPtr;
@@ -1675,28 +1701,21 @@
huart->State = HAL_UART_STATE_READY;
}
- /* Call the Process Unlocked before calling the Tx callback API to give the possibility to
- start again the Transmission under the Tx callback API */
- __HAL_UNLOCK(huart);
-
HAL_UART_TxCpltCallback(huart);
return HAL_OK;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
+ return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
* @brief Receives an amount of data in non blocking mode
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
@@ -1707,9 +1726,6 @@
tmp1 = huart->State;
if((tmp1 == HAL_UART_STATE_BUSY_RX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX))
{
- /* Process Locked */
- __HAL_LOCK(huart);
-
if(huart->Init.WordLength == UART_WORDLENGTH_9B)
{
tmp = (uint16_t*) huart->pRxBuffPtr;
@@ -1738,8 +1754,9 @@
if(--huart->RxXferCount == 0)
{
- while(HAL_IS_BIT_SET(huart->Instance->SR, UART_FLAG_RXNE))
- {
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, SET, UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
}
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
@@ -1758,17 +1775,10 @@
huart->State = HAL_UART_STATE_READY;
}
- /* Call the Process Unlocked before calling the Rx callback API to give the possibility to
- start again the reception under the Rx callback API */
- __HAL_UNLOCK(huart);
-
HAL_UART_RxCpltCallback(huart);
return HAL_OK;
}
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
else
@@ -1779,7 +1789,8 @@
/**
* @brief Configures the UART peripheral.
- * @param huart: UART handle
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_uart.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_uart.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_uart.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -300,19 +300,32 @@ #define UART_IT_LBD ((uint32_t)0x20000040) #define UART_IT_CTS ((uint32_t)0x30000400) - + #define UART_IT_ERR ((uint32_t)0x30000001) /** * @} */ - + /** * @} */ /* Exported macro ------------------------------------------------------------*/ - + +/** @brief Reset UART handle state + * @param __HANDLE__: specifies the UART Handle. + * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or + * UART peripheral. + * @retval None + */ +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET) + +/** @brief Flushs the UART DR register + * @param __HANDLE__: specifies the UART Handle. + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) + /** @brief Checks whether the specified UART flag is set or not. * @param __HANDLE__: specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_usart.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_usart.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_usart.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
@@ -18,7 +18,7 @@
The USART HAL driver can be used as follows:
(#) Declare a USART_HandleTypeDef handle structure.
- (#) Initialize the USART low level resources by implement the HAL_USART_MspInit ()API:
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API:
(##) Enable the USARTx interface clock.
(##) USART pins configuration:
(+++) Enable the clock for the USART GPIOs.
@@ -40,14 +40,14 @@
flow control and Mode(Receiver/Transmitter) in the husart Init structure.
(#) Initialize the USART registers by calling the HAL_USART_Init() API:
- (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customed HAL_USART_MspInit(&husart) API.
-@@- The specific USART interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__USART_ENABLE_IT() and __USART_DISABLE_IT() inside the transmit and receive process.
- (#) Three mode of operations are available within this driver :
+ (#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -97,10 +97,10 @@
(+) __HAL_USART_ENABLE: Enable the USART peripheral
(+) __HAL_USART_DISABLE: Disable the USART peripheral
- (+) __HAL_USART_GET_FLAG : Checks whether the specified USART flag is set or not
- (+) __HAL_USART_CLEAR_FLAG : Clears the specified USART pending flag
- (+) __HAL_USART_ENABLE_IT: Enables the specified USART interrupt
- (+) __HAL_USART_DISABLE_IT: Disables the specified USART interrupt
+ (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
+ (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
+ (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
+ (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
[..]
(@) You can refer to the USART HAL driver header file for more useful macros
@@ -150,7 +150,7 @@
#ifdef HAL_USART_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define DYMMY_DATA 0xFFFF
+#define DUMMY_DATA 0xFFFF
#define USART_TIMEOUT_VALUE 22000
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@@ -189,18 +189,7 @@
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible USART frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
+ please refer to Reference manual for possible USART frame formats.
(++) USART polarity
(++) USART phase
(++) USART LastBit
@@ -217,7 +206,8 @@
/**
* @brief Initializes the USART mode according to the specified
* parameters in the USART_InitTypeDef and create the associated handle.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
@@ -260,7 +250,8 @@
/**
* @brief DeInitializes the USART peripheral.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
@@ -290,7 +281,8 @@
/**
* @brief USART MSP Init.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
@@ -302,7 +294,8 @@
/**
* @brief USART MSP DeInit.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
@@ -331,7 +324,7 @@
The USART supports master mode only: it cannot receive or send data related to an input
clock (SCLK is always an output).
- (#) There are two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
@@ -341,28 +334,28 @@
dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
- user callbacks
+ user callbacks
will be executed respectivelly at the end of the transmit or Receive process
- The HAL_USART_ErrorCallback()user callback will be executed when a communication
+ The HAL_USART_ErrorCallback() user callback will be executed when a communication
error is detected
- (#) Blocking mode API's are :
- (++) HAL_USART_Transmit()in simplex mode
+ (#) Blocking mode APIs are :
+ (++) HAL_USART_Transmit() in simplex mode
(++) HAL_USART_Receive() in full duplex receive only
(++) HAL_USART_TransmitReceive() in full duplex mode
- (#) Non-Blocking mode API's with Interrupt are :
+ (#) Non Blocking mode APIs with Interrupt are :
(++) HAL_USART_Transmit_IT()in simplex mode
(++) HAL_USART_Receive_IT() in full duplex receive only
- (++) HAL_USART_TransmitReceive_IT()in full duplex mode
+ (++) HAL_USART_TransmitReceive_IT() in full duplex mode
(++) HAL_USART_IRQHandler()
- (#) No-Blocking mode functions with DMA are :
+ (#) Non Blocking mode functions with DMA are :
(++) HAL_USART_Transmit_DMA()in simplex mode
(++) HAL_USART_Receive_DMA() in full duplex receive only
(++) HAL_USART_TransmitReceie_DMA() in full duplex mode
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_USART_TxCpltCallback()
(++) HAL_USART_RxCpltCallback()
(++) HAL_USART_ErrorCallback()
@@ -374,9 +367,11 @@
/**
* @brief Simplex Send an amount of data in blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param pTxData: Pointer to data buffer
* @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
@@ -449,9 +444,11 @@
/**
* @brief Full-Duplex Receive an amount of data in blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param pRxData: Pointer to data buffer
* @param Size: Amount of data to be received
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
@@ -484,7 +481,7 @@
return HAL_TIMEOUT;
}
/* Send dummy byte in order to generate clock */
- husart->Instance->DR = (DYMMY_DATA & (uint16_t)0x01FF);
+ husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
/* Wait for RXNE Flag */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
@@ -512,7 +509,7 @@
}
/* Send Dummy Byte in order to generate clock */
- husart->Instance->DR = (DYMMY_DATA & (uint16_t)0x00FF);
+ husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);
/* Wait until RXNE flag is set to receive the byte */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
@@ -548,9 +545,12 @@
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
- * @param husart: USART handle
- * @param pTxData: Pointer to data buffer
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data transmitted buffer
+ * @param pRxData: Pointer to data received buffer
* @param Size: Amount of data to be sent
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
@@ -656,7 +656,8 @@
/**
* @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param pTxData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -705,7 +706,8 @@
/**
* @brief Simplex Receive an amount of data in non-blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param pRxData: Pointer to data buffer
* @param Size: Amount of data to be received
* @retval HAL status
@@ -741,7 +743,7 @@
__HAL_UNLOCK(husart);
/* Send dummy byte in order to generate the clock for the slave to send data */
- husart->Instance->DR = (DYMMY_DATA & (uint16_t)0x01FF);
+ husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
return HAL_OK;
}
@@ -753,8 +755,10 @@
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @param husart: USART handle
- * @param pTxData: Pointer to data buffer
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data transmitted buffer
+ * @param pRxData: Pointer to data received buffer
* @param Size: Amount of data to be received
* @retval HAL status
*/
@@ -804,8 +808,9 @@
/**
* @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: USART handle
- * @param pData: Pointer to data buffer
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
*/
@@ -859,7 +864,8 @@
/**
* @brief Full-Duplex Receive an amount of data in non-blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param pRxData: Pointer to data buffer
* @param Size: Amount of data to be received
* @retval HAL status
@@ -927,8 +933,10 @@
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
- * @param husart: USART handle
- * @param pRxData: Pointer to data buffer
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @param pTxData: Pointer to data transmitted buffer
+ * @param pRxData: Pointer to data received buffer
* @param Size: Amount of data to be received
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
* @retval HAL status
@@ -1001,8 +1009,9 @@
/**
* @brief Pauses the DMA Transfer.
- * @param husart: USART handle
- * @retval None
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
{
@@ -1035,8 +1044,9 @@
/**
* @brief Resumes the DMA Transfer.
- * @param husart: USART handle
- * @retval None
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
{
@@ -1076,8 +1086,9 @@
/**
* @brief Stops the DMA Transfer.
- * @param husart: USART handle
- * @retval None
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
{
@@ -1111,7 +1122,8 @@
/**
* @brief This function handles USART interrupt request.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
@@ -1195,7 +1207,8 @@
/**
* @brief Tx Transfer completed callbacks.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
@@ -1207,7 +1220,8 @@
/**
* @brief Tx Half Transfer completed callbacks.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1219,7 +1233,8 @@
/**
* @brief Rx Transfer completed callbacks.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
@@ -1231,7 +1246,8 @@
/**
* @brief Rx Half Transfer completed callbacks.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1243,7 +1259,8 @@
/**
* @brief Tx/Rx Transfers completed callback for the non-blocking process.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
@@ -1255,7 +1272,8 @@
/**
* @brief USART error callbacks.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
@@ -1279,10 +1297,10 @@
[..]
This subsection provides a set of functions allowing to return the State of
USART communication
- process, return Peripheral Errors occured during communication process
+ process, return Peripheral Errors occurred during communication process
(+) HAL_USART_GetState() API can be helpful to check in run-time the state
of the USART peripheral.
- (+) HAL_USART_GetError() check in run-time errors that could be occured durung
+ (+) HAL_USART_GetError() check in run-time errors that could be occurred during
communication.
@endverbatim
* @{
@@ -1290,7 +1308,8 @@
/**
* @brief Returns the USART state.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval HAL state
*/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
@@ -1329,7 +1348,7 @@
/* Wait for USART TC Flag */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK)
{
- /* Timeout Occured */
+ /* Timeout occurred */
husart->State = HAL_USART_STATE_TIMEOUT;
HAL_USART_ErrorCallback(husart);
}
@@ -1352,7 +1371,8 @@
/**
* @brief DMA USART transmit process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1385,7 +1405,8 @@
/**
* @brief DMA USART receive process half complete callback
- * @param hdma : DMA handle
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1414,7 +1435,8 @@
/**
* @brief This function handles USART Communication Timeout.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param Flag: specifies the USART flag to check.
* @param Status: The new Flag status (SET or RESET).
* @param Timeout: Timeout duration
@@ -1483,7 +1505,8 @@
/**
* @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval HAL status
* @note The USART errors are not managed to avoid the overrun error.
*/
@@ -1493,9 +1516,6 @@
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
- /* Process Locked */
- __HAL_LOCK(husart);
-
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
tmp = (uint16_t*) husart->pTxBuffPtr;
@@ -1524,18 +1544,10 @@
husart->State = HAL_USART_STATE_READY;
- /* Call the Process Unlocked before calling the Tx callback API to give the possibility to
- start again the Transmission under the Tx callback API */
- __HAL_UNLOCK(husart);
-
HAL_USART_TxCpltCallback(husart);
return HAL_OK;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
return HAL_OK;
}
else
@@ -1546,7 +1558,8 @@
/**
* @brief Simplex Receive an amount of data in non-blocking mode.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
@@ -1554,9 +1567,6 @@
uint16_t* tmp;
if(husart->State == HAL_USART_STATE_BUSY_RX)
{
- /* Process Locked */
- __HAL_LOCK(husart);
-
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
tmp = (uint16_t*) husart->pRxBuffPtr;
@@ -1573,7 +1583,7 @@
if(--husart->RxXferCount != 0x00)
{
/* Send dummy byte in order to generate the clock for the slave to send the next data */
- husart->Instance->DR = (DYMMY_DATA & (uint16_t)0x01FF);
+ husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x01FF);
}
}
else
@@ -1590,7 +1600,7 @@
if(--husart->RxXferCount != 0x00)
{
/* Send dummy byte in order to generate the clock for the slave to send the next data */
- husart->Instance->DR = (DYMMY_DATA & (uint16_t)0x00FF);
+ husart->Instance->DR = (DUMMY_DATA & (uint16_t)0x00FF);
}
}
@@ -1606,18 +1616,10 @@
__USART_DISABLE_IT(husart, USART_IT_ERR);
husart->State = HAL_USART_STATE_READY;
- /* Call the Process Unlocked before calling the Rx callback API to give the possibility to
- start again the reception under the Rx callback API */
- __HAL_UNLOCK(husart);
-
HAL_USART_RxCpltCallback(husart);
return HAL_OK;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
return HAL_OK;
}
else
@@ -1628,7 +1630,8 @@
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
@@ -1738,7 +1741,8 @@
/**
* @brief Configures the USART peripheral.
- * @param husart: USART handle
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
static void USART_SetConfig(USART_HandleTypeDef *husart)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_usart.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_usart.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_usart.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
@@ -62,7 +62,7 @@
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
+ - IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate)))
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
@@ -251,7 +251,7 @@
* @}
*/
-/** @defgroup Usart_NACK_State
+/** @defgroup USART_NACK_State
* @{
*/
#define USARTNACK_ENABLED ((uint32_t)USART_CR3_NACK)
@@ -262,7 +262,7 @@
* @}
*/
-/** @defgroup Usart_Flags
+/** @defgroup USART_Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
@@ -298,24 +298,29 @@
#define USART_IT_LBD ((uint32_t)0x20000040)
#define USART_IT_CTS ((uint32_t)0x30000400)
-
+
#define USART_IT_ERR ((uint32_t)0x30000001)
/**
* @}
*/
-
+
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
+/** @brief Reset USART handle state
+ * @param __HANDLE__: specifies the USART Handle.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
+ * @retval None
+ */
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
/** @brief Checks whether the specified Smartcard flag is set or not.
* @param __HANDLE__: specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg USART_FLAG_TXE: Transmit data register empty flag
@@ -333,8 +338,7 @@
/** @brief Clears the specified Smartcard pending flags.
* @param __HANDLE__: specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @param __FLAG__: specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg USART_FLAG_TC: Transmission Complete flag.
@@ -356,8 +360,7 @@
/** @brief Enables or disables the specified Usart interrupts.
* @param __HANDLE__: specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @param __INTERRUPT__: specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
@@ -381,8 +384,7 @@
/** @brief Checks whether the specified Usart interrupt has occurred or not.
* @param __HANDLE__: specifies the USART Handle.
- * This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
- * UART peripheral.
+ * This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @param __IT__: specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_wwdg.c Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_wwdg.c Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_wwdg.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: @@ -144,7 +144,8 @@ /** * @brief Initializes the WWDG according to the specified * parameters in the WWDG_InitTypeDef and creates the associated handle. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) @@ -206,7 +207,8 @@ /** * @brief DeInitializes the WWDG peripheral. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) @@ -238,7 +240,8 @@ /** * @brief Initializes the WWDG MSP. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) @@ -250,7 +253,8 @@ /** * @brief DeInitializes the WWDG MSP. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) @@ -283,7 +287,8 @@ /** * @brief Starts the WWDG. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg) @@ -309,7 +314,8 @@ /** * @brief Starts the WWDG with interrupt enabled. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg) @@ -332,7 +338,8 @@ /** * @brief Refreshes the WWDG. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) @@ -368,7 +375,8 @@ * generated and the corresponding Interrupt Service Routine (ISR) can * be used to trigger specific actions (such as communications or data * logging), before resetting the device. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) @@ -392,7 +400,8 @@ /** * @brief Early Wakeup WWDG callback. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) @@ -423,7 +432,8 @@ /** * @brief Returns the WWDG state. - * @param hwwdg: WWDG handle + * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL state */ HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_wwdg.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_wwdg.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_wwdg.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
@@ -74,13 +74,13 @@
*/
typedef struct
{
- uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
+ uint32_t Prescaler; /*!< Specifies the prescaler.
This parameter can be a value of @ref WWDG_Prescaler */
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
This parameter must be a number lower than Max_Data = 0x80 */
- uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
+ uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
}WWDG_InitTypeDef;
@@ -102,10 +102,6 @@
/* Exported constants --------------------------------------------------------*/
-/** @defgroup WWDG_Exported_Constants
- * @{
- */
-
/** @defgroup WWDG_BitAddress_AliasRegion
* @{
*/
@@ -140,7 +136,7 @@
/**
* @}
*/
-
+
/** @defgroup WWDG_Prescaler
* @{
*/
@@ -152,7 +148,7 @@
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_PRESCALER_1) || \
((PRESCALER) == WWDG_PRESCALER_2) || \
((PRESCALER) == WWDG_PRESCALER_4) || \
- ((PRESCALER) == WWDG_PRESCALER_8))
+ ((PRESCALER) == WWDG_PRESCALER_8))
/**
* @}
@@ -176,11 +172,13 @@
* @}
*/
-/**
- * @}
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset WWDG handle state
+ * @param __HANDLE__: WWDG handle
+ * @retval None
*/
-
-/* Exported macro ------------------------------------------------------------*/
+#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
/**
* @brief Enables the WWDG peripheral.
@@ -216,7 +214,6 @@
*/
#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__))
-
/* Exported functions --------------------------------------------------------*/
/* Initialization/de-initialization functions **********************************/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_fmc.c Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_fmc.c Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_fmc.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief FMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_fmc.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_fmc.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_fmc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention
@@ -63,70 +63,69 @@
#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
-#define FMC_NORSRAM_DEVICE FMC_Bank1
-#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
-#define FMC_NAND_DEVICE FMC_Bank2_3
-#define FMC_PCCARD_DEVICE FMC_Bank4
-#define FMC_SDRAM_DEVICE FMC_Bank5_6
-
+#define FMC_NORSRAM_DEVICE FMC_Bank1
+#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
+#define FMC_NAND_DEVICE FMC_Bank2_3
+#define FMC_PCCARD_DEVICE FMC_Bank4
+#define FMC_SDRAM_DEVICE FMC_Bank5_6
/**
- * @brief FMC_NORSRAM Configuration Structure definition
+ * @brief FMC_NORSRAM Configuration Structure definition
*/
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FMC_NORSRAM_Bank */
-
+ This parameter can be a value of @ref FMC_NORSRAM_Bank */
+
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the data bus or not.
This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
-
+
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
This parameter can be a value of @ref FMC_Memory_Type */
-
+
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
-
+
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FMC_Burst_Access_Mode */
-
+
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
-
+
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FMC_Wrap_Mode */
-
+
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FMC_Wait_Timing */
-
+
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
This parameter can be a value of @ref FMC_Write_Operation */
-
+
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FMC_Wait_Signal */
-
+
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FMC_Extended_Mode */
-
+
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FMC_AsynchronousWait */
-
+
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FMC_Write_Burst */
-
+ This parameter can be a value of @ref FMC_Write_Burst */
+
uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
This parameter is only enabled through the FMC_BCR1 register, and don't care
through FMC_BCR2..4 registers.
- This parameter can be a value of @ref FMC_Continous_Clock */
+ This parameter can be a value of @ref FMC_Continous_Clock */
}FMC_NORSRAM_InitTypeDef;
@@ -139,28 +138,28 @@
the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
-
+
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between Min_Data = 1 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
-
+
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NOR Flash memories. */
-
+
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is only used for multiplexed NOR Flash memories. */
-
+
uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
accesses. */
-
+
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
@@ -168,10 +167,9 @@
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
with synchronous burst mode enable */
-
+
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FMC_Access_Mode */
-
}FMC_NORSRAM_TimingTypeDef;
/**
@@ -180,29 +178,28 @@
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
- This parameter can be a value of @ref FMC_NAND_Bank */
-
+ This parameter can be a value of @ref FMC_NAND_Bank */
+
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
This parameter can be any value of @ref FMC_Wait_feature */
-
+
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FMC_NAND_Data_Width */
-
+
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FMC_ECC */
-
+
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FMC_ECC_Page_Size */
-
+
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FMC_NAND_InitTypeDef;
+}FMC_NAND_InitTypeDef;
/**
* @brief FMC_NAND_PCCARD Timing parameters structure definition
@@ -214,45 +211,43 @@
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
data bus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
}FMC_NAND_PCC_TimingTypeDef;
/**
- * @brief FMC_NAND Configuration Structure definition
+ * @brief FMC_NAND Configuration Structure definition
*/
typedef struct
{
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
This parameter can be any value of @ref FMC_Wait_feature */
-
+
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FMC_PCCARD_InitTypeDef;
+}FMC_PCCARD_InitTypeDef;
/**
* @brief FMC_SDRAM Configuration Structure definition
@@ -260,37 +255,36 @@
typedef struct
{
uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
- This parameter can be a value of @ref FMC_SDRAM_Bank */
-
+ This parameter can be a value of @ref FMC_SDRAM_Bank */
+
uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
-
+
uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
-
+
uint32_t MemoryDataWidth; /*!< Defines the memory device width.
This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
-
+
uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
-
+
uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
-
+
uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
-
+
uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
to disable the clock before changing frequency.
This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
-
+
uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
commands during the CAS latency and stores data in the Read FIFO.
This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
-
+
uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
-
}FMC_SDRAM_InitTypeDef;
/**
@@ -301,32 +295,31 @@
uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
an active or Refresh command in number of memory clock cycles.
This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
+
uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
issuing the Activate command in number of memory clock cycles.
This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
+
uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
cycles.
This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
+
uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
and the delay between two consecutive Refresh commands in number of
memory clock cycles.
This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
+
uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
+
uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
in number of memory clock cycles.
This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
+
uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
command in number of memory clock cycles.
This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
-}FMC_SDRAM_TimingTypeDef;
+}FMC_SDRAM_TimingTypeDef;
/**
* @brief SDRAM command parameters structure definition
@@ -334,25 +327,23 @@
typedef struct
{
uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
- This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
-
+ This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
+
uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
- This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
-
+ This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
+
uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
in auto refresh mode.
- This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
-
- uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
-
+ This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
+ uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
}FMC_SDRAM_CommandTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup FMC_NOR_SRAM_Controller
* @{
- */
-
+ */
+
/** @defgroup FMC_NORSRAM_Bank
* @{
*/
@@ -474,7 +465,7 @@
#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) || \
- ((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
+ ((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
/**
* @}
*/
@@ -630,7 +621,7 @@
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
- ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+ ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
/**
* @}
*/
@@ -1131,16 +1122,16 @@
* @retval None
*/
#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
- ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
+ ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
/**
* @brief Disable the NAND device access.
* @param __INSTANCE__: FMC_NAND Instance
* @param __BANK__: FMC_NAND Bank
* @retval None
- */
+ */
#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
- ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
+ ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_fsmc.c Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_fsmc.c Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_fsmc.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief FSMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_fsmc.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_fsmc.h Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ll_fsmc.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V1.1.0RC2
+ * @date 14-May-2014
* @brief Header file of FSMC HAL module.
******************************************************************************
* @attention
@@ -62,69 +62,68 @@
#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
-#define FSMC_NORSRAM_DEVICE FSMC_Bank1
-#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
-#define FSMC_NAND_DEVICE FSMC_Bank2_3
-#define FSMC_PCCARD_DEVICE FSMC_Bank4
+#define FSMC_NORSRAM_DEVICE FSMC_Bank1
+#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
+#define FSMC_NAND_DEVICE FSMC_Bank2_3
+#define FSMC_PCCARD_DEVICE FSMC_Bank4
/**
- * @brief FSMC_NORSRAM Configuration Structure definition
+ * @brief FSMC_NORSRAM Configuration Structure definition
*/
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */
-
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the data bus or not.
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
+
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
This parameter can be a value of @ref FSMC_Memory_Type */
-
+
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
-
+
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
-
+
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
-
+
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FSMC_Wrap_Mode */
-
+
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FSMC_Wait_Timing */
-
+
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
This parameter can be a value of @ref FSMC_Write_Operation */
-
+
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal */
-
+
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FSMC_Extended_Mode */
-
+
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FSMC_AsynchronousWait */
-
+
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FSMC_Write_Burst */
+ This parameter can be a value of @ref FSMC_Write_Burst */
}FSMC_NORSRAM_InitTypeDef;
-
/**
- * @brief FSMC_NORSRAM Timing parameters structure definition
+ * @brief FSMC_NORSRAM Timing parameters structure definition
*/
typedef struct
{
@@ -132,28 +131,28 @@
the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
-
+
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between Min_Data = 1 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
-
+
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NOR Flash memories. */
-
+
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is only used for multiplexed NOR Flash memories. */
-
+
uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
accesses. */
-
+
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
@@ -161,40 +160,40 @@
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
with synchronous burst mode enable */
-
+
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FSMC_Access_Mode */
-
+
}FSMC_NORSRAM_TimingTypeDef;
/**
- * @brief FSMC_NAND Configuration Structure definition
+ * @brief FSMC_NAND Configuration Structure definition
*/
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
- This parameter can be a value of @ref FSMC_NAND_Bank */
-
+ This parameter can be a value of @ref FSMC_NAND_Bank */
+
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
This parameter can be any value of @ref FSMC_Wait_feature */
-
+
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FSMC_NAND_Data_Width */
-
+
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FSMC_ECC */
-
+
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FSMC_ECC_Page_Size */
-
+
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
}FSMC_NAND_InitTypeDef;
/**
@@ -207,45 +206,45 @@
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
data bus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
}FSMC_NAND_PCC_TimingTypeDef;
/**
- * @brief FSMC_NAND Configuration Structure definition
- */
+ * @brief FSMC_NAND Configuration Structure definition
+ */
typedef struct
{
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
This parameter can be any value of @ref FSMC_Wait_feature */
-
+
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FSMC_PCCARD_InitTypeDef;
+
+}FSMC_PCCARD_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
@@ -379,7 +378,7 @@
#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WRITE_OPERATION_DISABLE) || \
- ((OPERATION) == FSMC_WRITE_OPERATION_ENABLE))
+ ((OPERATION) == FSMC_WRITE_OPERATION_ENABLE))
/**
* @}
*/
@@ -542,7 +541,7 @@
#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
- ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+ ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_sdmmc.c Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_sdmmc.c Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief SDMMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_sdmmc.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_sdmmc.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of SDMMC HAL module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_usb.c Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_usb.c Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_usb.c * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_usb.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_usb.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_ll_usb.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/system_stm32f4xx.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/system_stm32f4xx.c Fri Jun 27 07:30:09 2014 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
- * @version V1.0.0
- * @date 18-February-2014
+ * @version V2.1.0RC2
+ * @date 14-May-2014
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@@ -20,7 +20,23 @@
* be called whenever the core clock is changed
* during program execution.
*
- *
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 16 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 168 | 168
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 168 | 168
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 42 | 42
+ *-----------------------------------------------------------------------------
+ * APB2CLK (MHz) | 84 | 84
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | NO
+ *-----------------------------------------------------------------------------
******************************************************************************
* @attention
*
@@ -63,7 +79,16 @@
* @{
*/
-#include "stm32f4xx_hal.h"
+#include "stm32f4xx.h"
+#include "hal_tick.h"
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
/**
* @}
@@ -82,6 +107,19 @@
*/
/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
+ on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
+ #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
@@ -98,6 +136,10 @@
* @{
*/
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
/**
* @}
*/
@@ -114,7 +156,7 @@
variable is updated automatically.
*/
uint32_t SystemCoreClock = 168000000; /* [CHANGED FOR MBED] */
- __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
@@ -124,8 +166,15 @@
* @{
*/
-/* [ADDED FOR MBED] */
-void SystemClock_Config(void);
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
/**
* @}
@@ -167,6 +216,10 @@
/* Disable all interrupts */
RCC->CIR = 0x00000000;
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
@@ -174,9 +227,18 @@
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
- /* [ADDED FOR MBED] */
+ /* Configure the Cube driver */
+ SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
HAL_Init();
- SystemClock_Config();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+ SystemCoreClockUpdate();
+
+ /* Reset the timer to avoid issues after the RAM initialization */
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
}
/**
@@ -263,9 +325,269 @@
SystemCoreClock >>= tmp;
}
-/* [ADDED FOR MBED]
- Configure the System clock to 84 MHz (max value) using the internal HSI 16 MHz clock */
-void SystemClock_Config(void)
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f4xx.s before jump to main.
+ * This function configures the external memories (SRAM/SDRAM)
+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined (DATA_IN_ExtSDRAM)
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register uint32_t index;
+
+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+ clock */
+ RCC->AHB1ENR |= 0x000001F8;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x000000CC;
+ GPIOD->AFR[1] = 0xCC000CCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xA02A000A;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOD->OSPEEDR = 0xA02A000A;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA800A;
+ /* Configure PEx pins speed to 50 MHz */
+ GPIOE->OSPEEDR = 0xAAAA800A;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0xCCCCCCCC;
+ GPIOF->AFR[1] = 0xCCCCCCCC;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA800AAA;
+ /* Configure PFx pins speed to 50 MHz */
+ GPIOF->OSPEEDR = 0xAA800AAA;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0xCCCCCCCC;
+ GPIOG->AFR[1] = 0xCCCCCCCC;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xAAAAAAAA;
+ /* Configure PGx pins speed to 50 MHz */
+ GPIOG->OSPEEDR = 0xAAAAAAAA;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0x00C0CC00;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAA08A0;
+ /* Configure PHx pins speed to 50 MHz */
+ GPIOH->OSPEEDR = 0xAAAA08A0;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PHx pins */
+ GPIOH->PUPDR = 0x00000000;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0x0028AAAA;
+ /* Configure PIx pins speed to 50 MHz */
+ GPIOI->OSPEEDR = 0x0028AAAA;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PIx pins */
+ GPIOI->PUPDR = 0x00000000;
+
+/*-- FMC Configuration ------------------------------------------------------*/
+ /* Enable the FMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+ /* Configure and enable SDRAM bank1 */
+ FMC_Bank5_6->SDCR[0] = 0x000019E0;
+ FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6->SDCMR = 0x00000011;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index = 0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6->SDCMR = 0x00000012;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Auto refresh command */
+ FMC_Bank5_6->SDCMR = 0x00000073;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* MRD register program */
+ FMC_Bank5_6->SDCMR = 0x00046014;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6->SDRTR;
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6->SDCR[0];
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ RCC->AHB1ENR |= 0x00000078;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00CCC0CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAA0A8A;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0FCF;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA828A;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCC0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA000AAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFF000FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0x000000C0;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0x00085AAA;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0x000CAFFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+/*-- FMC/FSMC Configuration --------------------------------------------------*/
+ /* Enable the FMC/FSMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001011;
+ FMC_Bank1->BTCR[3] = 0x00000201;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FSMC_Bank1->BTCR[2] = 0x00001011;
+ FSMC_Bank1->BTCR[3] = 0x00000201;
+ FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+}
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
@@ -276,57 +598,96 @@
__PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
- /* Enable HSI Oscillator and activate PLL with HSI as source */
+ /* Enable HSE oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
- RCC_OscInitStruct.HSEState = RCC_HSE_ON;
- RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
- RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
- RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ if (bypass == 0)
+ {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+ }
+ else
+ {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
+ }
+RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- RCC_OscInitStruct.PLL.PLLM = 8;
- RCC_OscInitStruct.PLL.PLLN = 336;
- RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
- RCC_OscInitStruct.PLL.PLLQ = 7;
+ RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
- // System clock initialization failed
- while(1)
- {
- // [TODO] Put something here to tell the user that a problem occured...
- }
+ return 0; // FAIL
}
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz (SPI1 clock...)
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
{
- // System clock initialization failed
- while(1)
- {
- // [TODO] Put something here to tell the user that a problem occured...
- }
+ return 0; // FAIL
}
- /* Update the SystemCoreClock variable
- - Not needed because the variable is already set on top of this file.
- - Warning: this function call is removed by the compiler with -O3/-Otime options. */
- //SystemCoreClockUpdate();
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ /*
+ if (bypass == 0)
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+ else
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+ */
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
- /* Output SYSCLK on MCO2 pin(PC9) for debugging purpose */
- //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 168 MHz / 4 = 42 MHz
-}
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ /* Enable HSI oscillator and activate PLL with HSI as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
-/* [ADDED FOR MBED]
- Used for the different timeouts in the HAL */
-void SysTick_Handler(void)
-{
- HAL_IncTick();
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
}
/**
--- a/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/system_stm32f4xx.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/system_stm32f4xx.h Fri Jun 27 07:30:09 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.0.0 - * @date 18-February-2014 + * @version V2.1.0RC2 + * @date 14-May-2014 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention @@ -102,6 +102,8 @@ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + /** * @} */
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/analogin_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/analogin_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -25,14 +25,14 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "mbed_assert.h"
#include "analogin_api.h"
-#include "wait_api.h"
#if DEVICE_ANALOGIN
+#include "wait_api.h"
#include "cmsis.h"
#include "pinmap.h"
-#include "stm32f4xx_hal.h"
static const PinMap PinMap_ADC[] = {
{PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0
@@ -41,8 +41,8 @@
{PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3
{PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4
{PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5
- {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6
- {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7
+ {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7
{PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8
{PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9
{PC_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN10
@@ -59,7 +59,7 @@
int adc_inited = 0;
void analogin_init(analogin_t *obj, PinName pin) {
- // Get the peripheral name (ADC_1, ADC_2...) from the pin and assign it to the object
+ // Get the peripheral name from the pin and assign it to the object
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
@@ -161,20 +161,16 @@
HAL_ADC_Start(&AdcHandle); // Start conversion
- HAL_ADC_PollForConversion(&AdcHandle, 10); // Wait end of conversion
-
- if (HAL_ADC_GetState(&AdcHandle) == HAL_ADC_STATE_EOC_REG)
- {
- return(HAL_ADC_GetValue(&AdcHandle)); // Get conversion value
- }
- else
- {
+ // Wait end of conversion and get value
+ if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
+ return (HAL_ADC_GetValue(&AdcHandle));
+ } else {
return 0;
}
}
uint16_t analogin_read_u16(analogin_t *obj) {
- return(adc_read(obj));
+ return (adc_read(obj));
}
float analogin_read(analogin_t *obj) {
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/analogout_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/analogout_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -103,7 +103,7 @@
static inline void dac_write(dac_t *obj, uint16_t value)
{
- HAL_StatusTypeDef status;
+ HAL_StatusTypeDef status = HAL_ERROR;
if (obj->channel == PA_4) {
status = HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value);
@@ -123,6 +123,7 @@
} else if (obj->channel == PA_5) {
return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2);
}
+ return 0; /* Just silented warning */
}
void analogout_write(dac_t *obj, float value)
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/device.h Thu Jun 26 10:30:09 2014 +0100 +++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/device.h Fri Jun 27 07:30:09 2014 +0100 @@ -42,10 +42,10 @@ #define DEVICE_SERIAL 1 #define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 // Not supported yet +#define DEVICE_I2CSLAVE 1 #define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 0 // Not supported yet +#define DEVICE_SPISLAVE 1 #define DEVICE_RTC 1
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/gpio_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/gpio_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -31,7 +31,6 @@
#include "gpio_api.h"
#include "pinmap.h"
#include "error.h"
-#include "stm32f4xx_hal.h"
extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
@@ -67,8 +66,7 @@
MBED_ASSERT(obj->pin != (PinName)NC);
if (direction == PIN_OUTPUT) {
pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
- }
- else { // PIN_INPUT
+ } else { // PIN_INPUT
pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
}
}
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/gpio_irq_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/gpio_irq_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -32,7 +32,6 @@
#include "gpio_irq_api.h"
#include "pinmap.h"
-#include "stm32f4xx_hal.h"
#include "error.h"
#define EDGE_NONE (0)
@@ -54,8 +53,7 @@
uint32_t pin = (uint32_t)(1 << channel_pin[irq_index]);
// Clear interrupt flag
- if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET)
- {
+ if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
__HAL_GPIO_EXTI_CLEAR_FLAG(pin);
}
@@ -64,20 +62,40 @@
// Check which edge has generated the irq
if ((gpio->IDR & pin) == 0) {
irq_handler(channel_ids[irq_index], IRQ_FALL);
- }
- else {
+ } else {
irq_handler(channel_ids[irq_index], IRQ_RISE);
}
}
// The irq_index is passed to the function
-static void gpio_irq0(void) {handle_interrupt_in(0);} // EXTI line 0
-static void gpio_irq1(void) {handle_interrupt_in(1);} // EXTI line 1
-static void gpio_irq2(void) {handle_interrupt_in(2);} // EXTI line 2
-static void gpio_irq3(void) {handle_interrupt_in(3);} // EXTI line 3
-static void gpio_irq4(void) {handle_interrupt_in(4);} // EXTI line 4
-static void gpio_irq5(void) {handle_interrupt_in(5);} // EXTI lines 5 to 9
-static void gpio_irq6(void) {handle_interrupt_in(6);} // EXTI lines 10 to 15
+// EXTI line 0
+static void gpio_irq0(void) {
+ handle_interrupt_in(0);
+}
+// EXTI line 1
+static void gpio_irq1(void) {
+ handle_interrupt_in(1);
+}
+// EXTI line 2
+static void gpio_irq2(void) {
+ handle_interrupt_in(2);
+}
+// EXTI line 3
+static void gpio_irq3(void) {
+ handle_interrupt_in(3);
+}
+// EXTI line 4
+static void gpio_irq4(void) {
+ handle_interrupt_in(4);
+}
+// EXTI lines 5 to 9
+static void gpio_irq5(void) {
+ handle_interrupt_in(5);
+}
+// EXTI lines 10 to 15
+static void gpio_irq6(void) {
+ handle_interrupt_in(6);
+}
extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
@@ -138,7 +156,7 @@
irq_index = 6;
break;
default:
- error("InterruptIn error: pin not supported.");
+ error("InterruptIn error: pin not supported.\n");
return -1;
}
@@ -187,8 +205,7 @@
if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
mode = STM_MODE_IT_RISING_FALLING;
obj->event = EDGE_BOTH;
- }
- else { // NONE or RISE
+ } else { // NONE or RISE
mode = STM_MODE_IT_RISING;
obj->event = EDGE_RISE;
}
@@ -198,14 +215,12 @@
if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
mode = STM_MODE_IT_RISING_FALLING;
obj->event = EDGE_BOTH;
- }
- else { // NONE or FALL
+ } else { // NONE or FALL
mode = STM_MODE_IT_FALLING;
obj->event = EDGE_FALL;
}
}
- }
- else {
+ } else {
mode = STM_MODE_INPUT;
pull = GPIO_NOPULL;
obj->event = EDGE_NONE;
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/gpio_object.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/gpio_object.h Fri Jun 27 07:30:09 2014 +0100
@@ -52,8 +52,7 @@
MBED_ASSERT(obj->pin != (PinName)NC);
if (value) {
*obj->reg_set = obj->mask;
- }
- else {
+ } else {
*obj->reg_clr = obj->mask;
}
}
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/i2c_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/i2c_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -34,7 +34,6 @@
#include "cmsis.h"
#include "pinmap.h"
-#include "stm32f4xx_hal.h"
/* Timeout values for flags and events waiting loops. These timeouts are
not based on accurate values, they just guarantee that the application will
@@ -95,6 +94,9 @@
// I2C configuration
i2c_frequency(obj, 100000); // 100 kHz per default
+
+ // I2C master by default
+ obj->slave = 0;
}
void i2c_frequency(i2c_t *obj, int hz) {
@@ -112,6 +114,10 @@
I2cHandle.Init.OwnAddress1 = 0;
I2cHandle.Init.OwnAddress2 = 0;
HAL_I2C_Init(&I2cHandle);
+ if (obj->slave) {
+ /* Enable Address Acknowledge */
+ I2cHandle.Instance->CR1 |= I2C_CR1_ACK;
+ }
}
@@ -148,29 +154,101 @@
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+ int count;
+ int value;
+
if (length == 0) return 0;
- I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ i2c_start(obj);
+
+ // Wait until SB flag is set
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
+ }
+
+ i2c->DR = __HAL_I2C_7BIT_ADD_READ(address);
+
- // Reception process with 5 seconds timeout
- if (HAL_I2C_Master_Receive(&I2cHandle, (uint16_t)address, (uint8_t *)data, length, 5000) != HAL_OK) {
- return 0; // Error
+ // Wait address is acknowledged
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
}
+ __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle);
+
+ // Read all bytes except last one
+ for (count = 0; count < (length - 1); count++) {
+ value = i2c_byte_read(obj, 0);
+ data[count] = (char)value;
+ }
+
+ // If not repeated start, send stop.
+ // Warning: must be done BEFORE the data is read.
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ // Read the last byte
+ value = i2c_byte_read(obj, 1);
+ data[count] = (char)value;
return length;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+ I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ int timeout;
+ int count;
+
if (length == 0) return 0;
+ i2c_start(obj);
- I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ // Wait until SB flag is set
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
+ }
+
+ i2c->DR = __HAL_I2C_7BIT_ADD_WRITE(address);
+
- // Transmission process with 5 seconds timeout
- if (HAL_I2C_Master_Transmit(&I2cHandle, (uint16_t)address, (uint8_t *)data, length, 5000) != HAL_OK) {
- return 0; // Error
+ // Wait address is acknowledged
+ timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) {
+ timeout--;
+ if (timeout == 0) {
+ return 0;
+ }
}
+ __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle);
- return length;
+ for (count = 0; count < length; count++) {
+ if (i2c_byte_write(obj, data[count]) != 1) {
+ i2c_stop(obj);
+ return 0;
+ }
+ }
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ }
+
+ return count;
}
int i2c_byte_read(i2c_t *obj, int last) {
@@ -233,7 +311,7 @@
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
- uint16_t tmpreg;
+ uint16_t tmpreg = 0;
// Get the old register value
tmpreg = i2c->OAR1;
@@ -246,7 +324,12 @@
}
void i2c_slave_mode(i2c_t *obj, int enable_slave) {
- // Nothing to do
+ I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
+ if (enable_slave) {
+ obj->slave = 1;
+ /* Enable Address Acknowledge */
+ I2cHandle.Instance->CR1 |= I2C_CR1_ACK;
+ }
}
// See I2CSlave.h
@@ -256,34 +339,137 @@
#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
int i2c_slave_receive(i2c_t *obj) {
- // TO BE DONE
- return(0);
+ int retValue = NoData;
+
+ if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) {
+ if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) {
+ if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TRA) == 1)
+ retValue = ReadAddressed;
+ else
+ retValue = WriteAddressed;
+
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR);
+ }
+ }
+
+ return (retValue);
}
int i2c_slave_read(i2c_t *obj, char *data, int length) {
+ uint32_t Timeout;
+ int size = 0;
if (length == 0) return 0;
I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
- // Reception process with 5 seconds timeout
- if (HAL_I2C_Slave_Receive(&I2cHandle, (uint8_t *)data, length, 5000) != HAL_OK) {
- return 0; // Error
+ while (length > 0) {
+ /* Wait until RXNE flag is set */
+ // Wait until the byte is received
+ Timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) {
+ Timeout--;
+ if (Timeout == 0) {
+ return 0;
+ }
+ }
+
+ /* Read data from DR */
+ (*data++) = I2cHandle.Instance->DR;
+ length--;
+ size++;
+
+ if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) {
+ /* Read data from DR */
+ (*data++) = I2cHandle.Instance->DR;
+ length--;
+ size++;
+ }
}
- return length;
+ /* Wait until STOP flag is set */
+ Timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) {
+ Timeout--;
+ if (Timeout == 0) {
+ return 0;
+ }
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_STOPFLAG(&I2cHandle);
+
+ /* Wait until BUSY flag is reset */
+ Timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) {
+ Timeout--;
+ if (Timeout == 0) {
+ return 0;
+ }
+ }
+
+ return size;
}
int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+ uint32_t Timeout;
+ int size = 0;
if (length == 0) return 0;
I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
- // Transmission process with 5 seconds timeout
- if (HAL_I2C_Slave_Transmit(&I2cHandle, (uint8_t *)data, length, 5000) != HAL_OK) {
- return 0; // Error
+ while (length > 0) {
+ /* Wait until TXE flag is set */
+ Timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXE) == RESET) {
+ Timeout--;
+ if (Timeout == 0) {
+ return 0;
+ }
+ }
+
+
+ /* Write data to DR */
+ I2cHandle.Instance->DR = (*data++);
+ length--;
+ size++;
+
+ if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) {
+ /* Write data to DR */
+ I2cHandle.Instance->DR = (*data++);
+ length--;
+ size++;
+ }
}
- return length;
+ /* Wait until AF flag is set */
+ Timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_AF) == RESET) {
+ Timeout--;
+ if (Timeout == 0) {
+ return 0;
+ }
+ }
+
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF);
+
+
+ /* Wait until BUSY flag is reset */
+ Timeout = FLAG_TIMEOUT;
+ while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) {
+ Timeout--;
+ if (Timeout == 0) {
+ return 0;
+ }
+ }
+
+ I2cHandle.State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(&I2cHandle);
+
+ return size;
}
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/objects.h Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/objects.h Fri Jun 27 07:30:09 2014 +0100
@@ -71,6 +71,8 @@
uint32_t databits;
uint32_t stopbits;
uint32_t parity;
+ PinName pin_tx;
+ PinName pin_rx;
};
struct spi_s {
@@ -81,10 +83,15 @@
uint32_t mode;
uint32_t nss;
uint32_t br_presc;
+ PinName pin_miso;
+ PinName pin_mosi;
+ PinName pin_sclk;
+ PinName pin_ssel;
};
struct i2c_s {
I2CName i2c;
+ uint32_t slave;
};
struct pwmout_s {
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/pinmap.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/pinmap.c Fri Jun 27 07:30:09 2014 +0100
@@ -28,10 +28,9 @@
*******************************************************************************
*/
#include "mbed_assert.h"
-#include "device.h"
#include "pinmap.h"
+#include "PortNames.h"
#include "error.h"
-#include "stm32f4xx_hal.h"
// GPIO mode look-up table
static const uint32_t gpio_mode[12] = {
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/port_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/port_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -31,7 +31,6 @@
#include "pinmap.h"
#include "gpio_api.h"
#include "error.h"
-#include "stm32f4xx_hal.h"
#if DEVICE_PORTIN || DEVICE_PORTOUT
@@ -67,8 +66,7 @@
if (obj->mask & (1 << i)) { // If the pin is used
if (dir == PIN_OUTPUT) {
pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
- }
- else { // PIN_INPUT
+ } else { // PIN_INPUT
pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
}
}
@@ -91,8 +89,7 @@
int port_read(port_t *obj) {
if (obj->direction == PIN_OUTPUT) {
return (*obj->reg_out & obj->mask);
- }
- else { // PIN_INPUT
+ } else { // PIN_INPUT
return (*obj->reg_in & obj->mask);
}
}
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/pwmout_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/pwmout_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -27,30 +27,30 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
-#include "mbed_assert.h"
#include "pwmout_api.h"
+#if DEVICE_PWMOUT
+
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
-#include "stm32f4xx_hal.h"
// TIM5 cannot be used because already used by the us_ticker
static const PinMap PinMap_PWM[] = {
{PA_0, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1
- //{PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1
+// {PA_0, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH1
{PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2
- //{PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2
+// {PA_1, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH2
{PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3
- //{PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3
- //{PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1
+// {PA_2, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH3
+// {PA_2, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH1
{PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH4
- //{PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4
- //{PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2
+// {PA_3, PWM_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)}, // TIM5_CH4
+// {PA_3, PWM_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)}, // TIM9_CH2
{PA_5, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1
{PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1
{PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N
- //{PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2
+// {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2
{PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1
{PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2
{PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3
@@ -58,18 +58,18 @@
{PA_15, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH1
{PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N
- //{PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3
+// {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH3
{PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH3N
- //{PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4
+// {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH4
{PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH2
{PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH1
{PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)}, // TIM3_CH2
{PB_6, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH1
{PB_7, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH2
{PB_8, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH3
- //{PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1
+// {PB_8, PWM_10,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1
{PB_9, PWM_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)}, // TIM4_CH4
- //{PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1
+// {PB_9, PWM_11,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1
{PB_10, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)}, // TIM2_CH3
{PB_13, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH1N
{PB_14, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1)}, // TIM1_CH2N
@@ -84,20 +84,50 @@
};
static TIM_HandleTypeDef TimHandle;
+static uint8_t ClockDivider;
+/* 0, 1, 2, 3, 4, 5, 6, 7 */
+const uint8_t APBxPrescTable[]={ 0, 0, 0, 0, 1, 2, 3, 4 };
+extern const uint8_t AHBPrescTable[];
void pwmout_init(pwmout_t* obj, PinName pin) {
// Get the peripheral name from the pin and assign it to the object
obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
- MBED_ASSERT(obj->pwm != (PWMName)NC);
+
+ if (obj->pwm == (PWMName)NC) {
+ error("PWM error: pinout mapping failed.");
+ }
// Enable TIM clock
- if (obj->pwm == PWM_1) __TIM1_CLK_ENABLE();
+ /* APB1 Timers */
if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE();
if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE();
if (obj->pwm == PWM_4) __TIM4_CLK_ENABLE();
- if (obj->pwm == PWM_9) __TIM9_CLK_ENABLE();
+ /* APB2 Timers */
+ if (obj->pwm == PWM_1) __TIM1_CLK_ENABLE();
+ if (obj->pwm == PWM_9) __TIM9_CLK_ENABLE();
if (obj->pwm == PWM_10) __TIM10_CLK_ENABLE();
if (obj->pwm == PWM_11) __TIM11_CLK_ENABLE();
+ /* Decide APBx divider for timer base clock
+ * Auto detect the Clockdivider value according to AHB,APB1 and APB2 prescaler register.
+ */
+ ClockDivider = AHBPrescTable[ ( ( RCC->CFGR & RCC_CFGR_HPRE ) >> 4 ) ];
+ switch( obj->pwm ) {
+ /* APB1 low clock */
+ case PWM_2:
+ case PWM_3:
+ case PWM_4:
+ ClockDivider += APBxPrescTable[ ( (RCC->CFGR & RCC_CFGR_PPRE1 ) >> 13 ) ];
+ break;
+ /* APB2 fast clock */
+ case PWM_1:
+ case PWM_9:
+ case PWM_10:
+ case PWM_11:
+ ClockDivider += APBxPrescTable[ ( (RCC->CFGR & RCC_CFGR_PPRE2 ) >> 10 ) ];
+ break;
+ default:
+ break;
+ }
// Configure GPIO
pinmap_pinout(pin, PinMap_PWM);
@@ -110,10 +140,7 @@
}
void pwmout_free(pwmout_t* obj) {
- TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
-
- HAL_TIM_PWM_DeInit(&TimHandle);
-
+ // Configure GPIO
pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
}
@@ -144,15 +171,12 @@
switch (obj->pin) {
// Channels 1
case PA_0:
- //case PA_2:
case PA_5:
case PA_6:
case PA_8:
case PA_15:
case PB_4:
case PB_6:
- //case PB_8:
- //case PB_9:
case PC_6:
channel = TIM_CHANNEL_1;
break;
@@ -164,8 +188,6 @@
break;
// Channels 2
case PA_1:
- //case PA_3:
- //case PA_7:
case PA_9:
case PB_3:
case PB_5:
@@ -181,13 +203,10 @@
break;
// Channels 3
case PA_2:
- //case PA_3:
case PA_10:
- //case PB_0:
case PB_8:
case PB_10:
case PC_8:
- //case PC_9:
channel = TIM_CHANNEL_3;
break;
// Channels 3N
@@ -199,7 +218,6 @@
// Channels 4
case PA_3:
case PA_11:
- //case PB_1:
case PB_9:
case PC_9:
channel = TIM_CHANNEL_4;
@@ -211,8 +229,7 @@
HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel);
if (complementary_channel) {
HAL_TIMEx_PWMN_Start(&TimHandle, channel);
- }
- else {
+ } else {
HAL_TIM_PWM_Start(&TimHandle, channel);
}
}
@@ -240,8 +257,10 @@
__HAL_TIM_DISABLE(&TimHandle);
+ // Update the SystemCoreClock variable
+ SystemCoreClockUpdate();
TimHandle.Init.Period = us - 1;
- TimHandle.Init.Prescaler = (uint16_t)(SystemCoreClock / 2 / 1000000) - 1; // 1 µs tick
+ TimHandle.Init.Prescaler = (uint16_t)( ( SystemCoreClock >> ClockDivider ) / 1000000) - 1; // 1 µs tick
TimHandle.Init.ClockDivision = 0;
TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
HAL_TIM_PWM_Init(&TimHandle);
@@ -267,3 +286,5 @@
float value = (float)us / (float)obj->period;
pwmout_write(obj, value);
}
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/rtc_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/rtc_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -28,7 +28,8 @@
*******************************************************************************
*/
#include "rtc_api.h"
-#include "stm32f4xx_hal.h"
+
+#if DEVICE_RTC
#include "error.h"
static int rtc_inited = 0;
@@ -36,6 +37,9 @@
static RTC_HandleTypeDef RtcHandle;
void rtc_init(void) {
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ uint32_t rtc_freq = 0;
+
if (rtc_inited) return;
rtc_inited = 1;
@@ -44,36 +48,44 @@
// Enable Power clock
__PWR_CLK_ENABLE();
- // Allow access to RTC
+ // Enable access to Backup domain
HAL_PWR_EnableBkUpAccess();
// Reset Backup domain
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
+ // Enable LSE Oscillator
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* Mandatory, otherwise the PLL is reconfigured! */
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON; /* External 32.768 kHz clock on OSC_IN/OSC_OUT */
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+ // Connect LSE to RTC
+ __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+ rtc_freq = LSE_VALUE;
+ } else {
// Enable LSI clock
- RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
error("RTC error: LSI clock initialization failed.");
}
-
// Connect LSI to RTC
__HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
__HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+ // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture
+ rtc_freq = 32000;
+ }
- // Enable RTC clock
+ // Enable RTC
__HAL_RCC_RTC_ENABLE();
- // [TODO] This value is LSI typical value. To be measured precisely using a timer input capture
- uint32_t lsi_freq = 32000;
-
RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24;
RtcHandle.Init.AsynchPrediv = 127;
- RtcHandle.Init.SynchPrediv = (lsi_freq / 128) - 1;
+ RtcHandle.Init.SynchPrediv = (rtc_freq / 128) - 1;
RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
@@ -86,18 +98,22 @@
// Enable Power clock
__PWR_CLK_ENABLE();
- // Allow access to RTC
+ // Enable access to Backup domain
HAL_PWR_EnableBkUpAccess();
// Reset Backup domain
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
- // Disable LSI clock
+ // Disable access to Backup domain
+ HAL_PWR_DisableBkUpAccess();
+
+ // Disable LSI and LSE clocks
RCC_OscInitTypeDef RCC_OscInitStruct;
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
+ RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
rtc_inited = 0;
@@ -176,3 +192,5 @@
HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
}
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/serial_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/serial_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -27,11 +27,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
+#include "mbed_assert.h"
#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
#include "cmsis.h"
#include "pinmap.h"
#include <string.h>
-#include "stm32f4xx_hal.h"
static const PinMap PinMap_UART_TX[] = {
{PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
@@ -53,7 +56,7 @@
#define UART_NUM (3)
-static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0};
static uart_irq_handler irq_handler;
@@ -87,12 +90,15 @@
// Enable USART clock
if (obj->uart == UART_1) {
__USART1_CLK_ENABLE();
+ obj->index = 0;
}
if (obj->uart == UART_2) {
__USART2_CLK_ENABLE();
+ obj->index = 1;
}
if (obj->uart == UART_6) {
__USART6_CLK_ENABLE();
+ obj->index = 2;
}
// Configure the UART pins
@@ -107,12 +113,10 @@
obj->stopbits = UART_STOPBITS_1;
obj->parity = UART_PARITY_NONE;
- init_uart(obj);
+ obj->pin_tx = tx;
+ obj->pin_rx = rx;
- // The index is used by irq
- if (obj->uart == UART_1) obj->index = 0;
- if (obj->uart == UART_2) obj->index = 1;
- if (obj->uart == UART_6) obj->index = 2;
+ init_uart(obj);
// For stdio management
if (obj->uart == STDIO_UART) {
@@ -123,6 +127,27 @@
}
void serial_free(serial_t *obj) {
+ // Reset UART and disable clock
+ if (obj->uart == UART_1) {
+ __USART1_FORCE_RESET();
+ __USART1_RELEASE_RESET();
+ __USART1_CLK_DISABLE();
+ }
+ if (obj->uart == UART_2) {
+ __USART2_FORCE_RESET();
+ __USART2_RELEASE_RESET();
+ __USART2_CLK_DISABLE();
+ }
+ if (obj->uart == UART_6) {
+ __USART6_FORCE_RESET();
+ __USART6_RELEASE_RESET();
+ __USART6_CLK_DISABLE();
+ }
+
+ // Configure GPIOs
+ pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
serial_irq_ids[obj->index] = 0;
}
@@ -134,8 +159,7 @@
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
if (data_bits == 8) {
obj->databits = UART_WORDLENGTH_8B;
- }
- else {
+ } else {
obj->databits = UART_WORDLENGTH_9B;
}
@@ -155,8 +179,7 @@
if (stop_bits == 2) {
obj->stopbits = UART_STOPBITS_2;
- }
- else {
+ } else {
obj->stopbits = UART_STOPBITS_1;
}
@@ -167,10 +190,8 @@
* INTERRUPTS HANDLING
******************************************************************************/
-// Not part of mbed api
static void uart_irq(UARTName name, int id) {
UartHandle.Instance = (USART_TypeDef *)name;
-
if (serial_irq_ids[id] != 0) {
if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) {
irq_handler(serial_irq_ids[id], TxIrq);
@@ -183,10 +204,15 @@
}
}
-// Not part of mbed api
-static void uart1_irq(void) {uart_irq(UART_1, 0);}
-static void uart2_irq(void) {uart_irq(UART_2, 1);}
-static void uart6_irq(void) {uart_irq(UART_6, 2);}
+static void uart1_irq(void) {
+ uart_irq(UART_1, 0);
+}
+static void uart2_irq(void) {
+ uart_irq(UART_2, 1);
+}
+static void uart6_irq(void) {
+ uart_irq(UART_6, 2);
+}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
@@ -218,8 +244,7 @@
if (irq == RxIrq) {
__HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE);
- }
- else { // TxIrq
+ } else { // TxIrq
__HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC);
}
@@ -234,8 +259,7 @@
__HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE);
// Check if TxIrq is disabled too
if ((UartHandle.Instance->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1;
- }
- else { // TxIrq
+ } else { // TxIrq
__HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TXE);
// Check if RxIrq is disabled too
if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
@@ -295,3 +319,5 @@
void serial_break_clear(serial_t *obj) {
}
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/sleep.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/sleep.c Fri Jun 27 07:30:09 2014 +0100
@@ -28,24 +28,30 @@
*******************************************************************************
*/
#include "sleep_api.h"
-#include "cmsis.h"
-#include "stm32f4xx_hal.h"
-// This function is in the system_stm32f4xx.c file
-extern void SystemClock_Config(void);
+#if DEVICE_SLEEP
+
+#include "cmsis.h"
static TIM_HandleTypeDef TimMasterHandle;
-void sleep(void)
-{
+void sleep(void) {
+ TimMasterHandle.Instance = TIM5;
+ // Disable HAL tick interrupt
+ __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
// Request to enter SLEEP mode
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+
+ // Enable HAL tick interrupt
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
}
-void deepsleep(void)
-{
+void deepsleep(void) {
// Request to enter STOP mode with regulator in low power mode
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
// After wake-up from STOP reconfigure the PLL
- SystemClock_Config();
+ SetSysClock();
}
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/spi_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/spi_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -27,6 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
+#include "mbed_assert.h"
#include "spi_api.h"
#if DEVICE_SPI
@@ -34,12 +35,11 @@
#include <math.h>
#include "cmsis.h"
#include "pinmap.h"
-#include "stm32f4xx_hal.h"
static const PinMap PinMap_SPI_MOSI[] = {
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
- //{PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+// {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
@@ -49,7 +49,7 @@
static const PinMap PinMap_SPI_MISO[] = {
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
- //{PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+// {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
@@ -59,7 +59,7 @@
static const PinMap PinMap_SPI_SCLK[] = {
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
- //{PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
{PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
{PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
@@ -67,12 +67,12 @@
};
static const PinMap PinMap_SPI_SSEL[] = {
- {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF5_SPI1)},
- //{PA_4, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF6_SPI3)},
- {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF5_SPI1)},
- //{PA_15, SPI_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF6_SPI3)},
- {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF5_SPI2)},
- {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
{NC, NC, 0}
};
@@ -135,11 +135,15 @@
obj->cpha = SPI_PHASE_1EDGE;
obj->br_presc = SPI_BAUDRATEPRESCALER_256;
+ obj->pin_miso = miso;
+ obj->pin_mosi = mosi;
+ obj->pin_sclk = sclk;
+ obj->pin_ssel = ssel;
+
if (ssel == NC) { // SW NSS Master mode
obj->mode = SPI_MODE_MASTER;
obj->nss = SPI_NSS_SOFT;
- }
- else { // Slave
+ } else { // Slave
pinmap_pinout(ssel, PinMap_SPI_SSEL);
obj->mode = SPI_MODE_SLAVE;
obj->nss = SPI_NSS_HARD_INPUT;
@@ -149,18 +153,39 @@
}
void spi_free(spi_t *obj) {
- SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
- HAL_SPI_DeInit(&SpiHandle);
+ // Reset SPI and disable clock
+ if (obj->spi == SPI_1) {
+ __SPI1_FORCE_RESET();
+ __SPI1_RELEASE_RESET();
+ __SPI1_CLK_DISABLE();
+ }
+
+ if (obj->spi == SPI_2) {
+ __SPI2_FORCE_RESET();
+ __SPI2_RELEASE_RESET();
+ __SPI2_CLK_DISABLE();
+ }
+
+ if (obj->spi == SPI_3) {
+ __SPI3_FORCE_RESET();
+ __SPI3_RELEASE_RESET();
+ __SPI3_CLK_DISABLE();
+ }
+
+ // Configure GPIOs
+ pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
}
void spi_format(spi_t *obj, int bits, int mode, int slave) {
// Save new values
- if (bits == 8) {
+ if (bits == 16) {
+ obj->bits = SPI_DATASIZE_16BIT;
+ } else {
obj->bits = SPI_DATASIZE_8BIT;
}
- else {
- obj->bits = SPI_DATASIZE_16BIT;
- }
switch (mode) {
case 0:
@@ -184,8 +209,7 @@
if (slave == 0) {
obj->mode = SPI_MODE_MASTER;
obj->nss = SPI_NSS_SOFT;
- }
- else {
+ } else {
obj->mode = SPI_MODE_SLAVE;
obj->nss = SPI_NSS_HARD_INPUT;
}
@@ -197,26 +221,19 @@
// Note: The frequencies are obtained with SPI1 clock = 84 MHz (APB2 clock)
if (hz < 600000) {
obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 330 kHz
- }
- else if ((hz >= 600000) && (hz < 1000000)) {
+ } else if ((hz >= 600000) && (hz < 1000000)) {
obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 656 kHz
- }
- else if ((hz >= 1000000) && (hz < 2000000)) {
+ } else if ((hz >= 1000000) && (hz < 2000000)) {
obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 1.3 MHz
- }
- else if ((hz >= 2000000) && (hz < 5000000)) {
+ } else if ((hz >= 2000000) && (hz < 5000000)) {
obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 2.6 MHz
- }
- else if ((hz >= 5000000) && (hz < 10000000)) {
+ } else if ((hz >= 5000000) && (hz < 10000000)) {
obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 5.25 MHz
- }
- else if ((hz >= 10000000) && (hz < 21000000)) {
+ } else if ((hz >= 10000000) && (hz < 21000000)) {
obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 10.5 MHz
- }
- else if ((hz >= 21000000) && (hz < 42000000)) {
+ } else if ((hz >= 21000000) && (hz < 42000000)) {
obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 21 MHz
- }
- else { // >= 42000000
+ } else { // >= 42000000
obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 42 MHz
}
init_spi(obj);
@@ -263,11 +280,12 @@
}
int spi_slave_receive(spi_t *obj) {
- return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+ return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
};
int spi_slave_read(spi_t *obj) {
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+ while (!ssp_readable(obj));
return (int)spi->DR;
}
--- a/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/us_ticker.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_DISCO_F407VG/us_ticker.c Fri Jun 27 07:30:09 2014 +0100
@@ -28,12 +28,8 @@
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
-#include "stm32f4xx_hal.h"
-// 32-bit timer selection
#define TIM_MST TIM5
-#define TIM_MST_IRQ TIM5_IRQn
-#define TIM_MST_RCC __TIM5_CLK_ENABLE()
static TIM_HandleTypeDef TimMasterHandle;
static int us_ticker_inited = 0;
@@ -42,23 +38,9 @@
if (us_ticker_inited) return;
us_ticker_inited = 1;
- // Enable timer clock
- TIM_MST_RCC;
-
- // Configure time base
TimMasterHandle.Instance = TIM_MST;
- TimMasterHandle.Init.Period = 0xFFFFFFFF;
- TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 2 / 1000000) - 1; // 1 µs tick
- TimMasterHandle.Init.ClockDivision = 0;
- TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
- TimMasterHandle.Init.RepetitionCounter = 0;
- HAL_TIM_OC_Init(&TimMasterHandle);
- NVIC_SetVector(TIM_MST_IRQ, (uint32_t)us_ticker_irq_handler);
- NVIC_EnableIRQ(TIM_MST_IRQ);
-
- // Enable timer
- HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+ HAL_InitTick(0); // The passed value is not used
}
uint32_t us_ticker_read() {
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/serial_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/serial_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -71,7 +71,15 @@
USART_InitStructure.USART_StopBits = obj->stopbits;
USART_InitStructure.USART_Parity = obj->parity;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
- USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+
+ if (obj->pin_rx == NC) {
+ USART_InitStructure.USART_Mode = USART_Mode_Tx;
+ } else if (obj->pin_tx == NC) {
+ USART_InitStructure.USART_Mode = USART_Mode_Rx;
+ } else {
+ USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
+ }
+
USART_Init(usart, &USART_InitStructure);
USART_Cmd(usart, ENABLE);
@@ -147,10 +155,10 @@
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
- if (data_bits == 8) {
+ if (data_bits == 9) {
+ obj->databits = USART_WordLength_9b;
+ } else {
obj->databits = USART_WordLength_8b;
- } else {
- obj->databits = USART_WordLength_9b;
}
switch (parity) {
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/serial_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F072RB/serial_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -181,10 +181,10 @@
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
- if (data_bits == 8) {
+ if (data_bits == 9) {
+ obj->databits = UART_WORDLENGTH_9B;
+ } else {
obj->databits = UART_WORDLENGTH_8B;
- } else {
- obj->databits = UART_WORDLENGTH_9B;
}
switch (parity) {
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -74,7 +74,15 @@
USART_InitStructure.USART_StopBits = obj->stopbits;
USART_InitStructure.USART_Parity = obj->parity;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
- USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+
+ if (obj->pin_rx == NC) {
+ USART_InitStructure.USART_Mode = USART_Mode_Tx;
+ } else if (obj->pin_tx == NC) {
+ USART_InitStructure.USART_Mode = USART_Mode_Rx;
+ } else {
+ USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
+ }
+
USART_Init(usart, &USART_InitStructure);
USART_Cmd(usart, ENABLE);
@@ -156,10 +164,10 @@
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
- if (data_bits == 8) {
+ if (data_bits == 9) {
+ obj->databits = USART_WordLength_9b;
+ } else {
obj->databits = USART_WordLength_8b;
- } else {
- obj->databits = USART_WordLength_9b;
}
switch (parity) {
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/serial_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F302R8/serial_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -82,7 +82,15 @@
USART_InitStructure.USART_StopBits = obj->stopbits;
USART_InitStructure.USART_Parity = obj->parity;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
- USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+
+ if (obj->pin_rx == NC) {
+ USART_InitStructure.USART_Mode = USART_Mode_Tx;
+ } else if (obj->pin_tx == NC) {
+ USART_InitStructure.USART_Mode = USART_Mode_Rx;
+ } else {
+ USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
+ }
+
USART_Init(usart, &USART_InitStructure);
USART_Cmd(usart, ENABLE);
@@ -167,10 +175,10 @@
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
- if (data_bits == 8) {
+ if (data_bits == 9) {
+ obj->databits = USART_WordLength_9b;
+ } else {
obj->databits = USART_WordLength_8b;
- } else {
- obj->databits = USART_WordLength_9b;
}
switch (parity) {
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/serial_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_F401RE/serial_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -73,7 +73,14 @@
UartHandle.Init.StopBits = obj->stopbits;
UartHandle.Init.Parity = obj->parity;
UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- UartHandle.Init.Mode = UART_MODE_TX_RX;
+
+ if (obj->pin_rx == NC) {
+ UartHandle.Init.Mode = UART_MODE_TX;
+ } else if (obj->pin_tx == NC) {
+ UartHandle.Init.Mode = UART_MODE_RX;
+ } else {
+ UartHandle.Init.Mode = UART_MODE_TX_RX;
+ }
HAL_UART_Init(&UartHandle);
}
@@ -157,10 +164,10 @@
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
- if (data_bits == 8) {
+ if (data_bits == 9) {
+ obj->databits = UART_WORDLENGTH_9B;
+ } else {
obj->databits = UART_WORDLENGTH_8B;
- } else {
- obj->databits = UART_WORDLENGTH_9B;
}
switch (parity) {
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/serial_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/serial_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -175,10 +175,10 @@
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
- if (data_bits == 8) {
+ if (data_bits == 9) {
+ obj->databits = UART_WORDLENGTH_9B;
+ } else {
obj->databits = UART_WORDLENGTH_8B;
- } else {
- obj->databits = UART_WORDLENGTH_9B;
}
switch (parity) {
@@ -303,7 +303,7 @@
void serial_putc(serial_t *obj, int c) {
USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
while (!serial_writable(obj));
- uart->TDR = (uint32_t)(c & 0xFF);
+ uart->TDR = (uint16_t)(c & 0xFF);
}
int serial_readable(serial_t *obj) {
--- a/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/serial_api.c Thu Jun 26 10:30:09 2014 +0100
+++ b/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/serial_api.c Fri Jun 27 07:30:09 2014 +0100
@@ -78,7 +78,15 @@
USART_InitStructure.USART_StopBits = obj->stopbits;
USART_InitStructure.USART_Parity = obj->parity;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
- USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+
+ if (obj->pin_rx == NC) {
+ USART_InitStructure.USART_Mode = USART_Mode_Tx;
+ } else if (obj->pin_tx == NC) {
+ USART_InitStructure.USART_Mode = USART_Mode_Rx;
+ } else {
+ USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
+ }
+
USART_Init(usart, &USART_InitStructure);
USART_Cmd(usart, ENABLE);
@@ -180,10 +188,10 @@
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
- if (data_bits == 8) {
+ if (data_bits == 9) {
+ obj->databits = USART_WordLength_9b;
+ } else {
obj->databits = USART_WordLength_8b;
- } else {
- obj->databits = USART_WordLength_9b;
}
switch (parity) {