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targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_adc.h@242:7074e42da0b2, 2014-06-27 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jun 27 07:30:09 2014 +0100
- Revision:
- 242:7074e42da0b2
- Parent:
- 133:d4dda5c437f0
Synchronized with git revision 124ef5e3add9e74a3221347a3fbeea7c8b3cf353
Full URL: https://github.com/mbedmicro/mbed/commit/124ef5e3add9e74a3221347a3fbeea7c8b3cf353/
[DISCO_F407VG] HAL update.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 133:d4dda5c437f0 | 1 | /** |
| mbed_official | 133:d4dda5c437f0 | 2 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 3 | * @file stm32f4xx_hal_adc.h |
| mbed_official | 133:d4dda5c437f0 | 4 | * @author MCD Application Team |
| mbed_official | 242:7074e42da0b2 | 5 | * @version V1.1.0RC2 |
| mbed_official | 242:7074e42da0b2 | 6 | * @date 14-May-2014 |
| mbed_official | 133:d4dda5c437f0 | 7 | * @brief Header file of ADC HAL extension module. |
| mbed_official | 133:d4dda5c437f0 | 8 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 9 | * @attention |
| mbed_official | 133:d4dda5c437f0 | 10 | * |
| mbed_official | 133:d4dda5c437f0 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 133:d4dda5c437f0 | 12 | * |
| mbed_official | 133:d4dda5c437f0 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 133:d4dda5c437f0 | 14 | * are permitted provided that the following conditions are met: |
| mbed_official | 133:d4dda5c437f0 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 133:d4dda5c437f0 | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 133:d4dda5c437f0 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 133:d4dda5c437f0 | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 133:d4dda5c437f0 | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 133:d4dda5c437f0 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 133:d4dda5c437f0 | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 133:d4dda5c437f0 | 22 | * without specific prior written permission. |
| mbed_official | 133:d4dda5c437f0 | 23 | * |
| mbed_official | 133:d4dda5c437f0 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 133:d4dda5c437f0 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 133:d4dda5c437f0 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 133:d4dda5c437f0 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 133:d4dda5c437f0 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 133:d4dda5c437f0 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 133:d4dda5c437f0 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 133:d4dda5c437f0 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 133:d4dda5c437f0 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 133:d4dda5c437f0 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 133:d4dda5c437f0 | 34 | * |
| mbed_official | 133:d4dda5c437f0 | 35 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 36 | */ |
| mbed_official | 133:d4dda5c437f0 | 37 | |
| mbed_official | 133:d4dda5c437f0 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 39 | #ifndef __STM32F4xx_ADC_H |
| mbed_official | 133:d4dda5c437f0 | 40 | #define __STM32F4xx_ADC_H |
| mbed_official | 133:d4dda5c437f0 | 41 | |
| mbed_official | 133:d4dda5c437f0 | 42 | #ifdef __cplusplus |
| mbed_official | 133:d4dda5c437f0 | 43 | extern "C" { |
| mbed_official | 133:d4dda5c437f0 | 44 | #endif |
| mbed_official | 133:d4dda5c437f0 | 45 | |
| mbed_official | 133:d4dda5c437f0 | 46 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 47 | #include "stm32f4xx_hal_def.h" |
| mbed_official | 133:d4dda5c437f0 | 48 | |
| mbed_official | 133:d4dda5c437f0 | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 133:d4dda5c437f0 | 50 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 51 | */ |
| mbed_official | 133:d4dda5c437f0 | 52 | |
| mbed_official | 133:d4dda5c437f0 | 53 | /** @addtogroup ADC |
| mbed_official | 133:d4dda5c437f0 | 54 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 55 | */ |
| mbed_official | 133:d4dda5c437f0 | 56 | |
| mbed_official | 133:d4dda5c437f0 | 57 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 58 | |
| mbed_official | 133:d4dda5c437f0 | 59 | /** |
| mbed_official | 133:d4dda5c437f0 | 60 | * @brief HAL State structures definition |
| mbed_official | 133:d4dda5c437f0 | 61 | */ |
| mbed_official | 133:d4dda5c437f0 | 62 | typedef enum |
| mbed_official | 133:d4dda5c437f0 | 63 | { |
| mbed_official | 133:d4dda5c437f0 | 64 | HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */ |
| mbed_official | 133:d4dda5c437f0 | 65 | HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */ |
| mbed_official | 133:d4dda5c437f0 | 66 | HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ |
| mbed_official | 133:d4dda5c437f0 | 67 | HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */ |
| mbed_official | 133:d4dda5c437f0 | 68 | HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Injected conversion is ongoing */ |
| mbed_official | 133:d4dda5c437f0 | 69 | HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Injected and regular conversion are ongoing */ |
| mbed_official | 133:d4dda5c437f0 | 70 | HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
| mbed_official | 133:d4dda5c437f0 | 71 | HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */ |
| mbed_official | 133:d4dda5c437f0 | 72 | HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */ |
| mbed_official | 133:d4dda5c437f0 | 73 | HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */ |
| mbed_official | 133:d4dda5c437f0 | 74 | HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Injected conversion is completed */ |
| mbed_official | 133:d4dda5c437f0 | 75 | HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Injected and regular conversion are completed */ |
| mbed_official | 133:d4dda5c437f0 | 76 | HAL_ADC_STATE_AWD = 0x06 /*!< ADC state analog watchdog */ |
| mbed_official | 133:d4dda5c437f0 | 77 | |
| mbed_official | 133:d4dda5c437f0 | 78 | }HAL_ADC_StateTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 79 | |
| mbed_official | 133:d4dda5c437f0 | 80 | /** |
| mbed_official | 133:d4dda5c437f0 | 81 | * @brief ADC Init structure definition |
| mbed_official | 133:d4dda5c437f0 | 82 | */ |
| mbed_official | 133:d4dda5c437f0 | 83 | typedef struct |
| mbed_official | 133:d4dda5c437f0 | 84 | { |
| mbed_official | 133:d4dda5c437f0 | 85 | uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for |
| mbed_official | 133:d4dda5c437f0 | 86 | all the ADCs. |
| mbed_official | 133:d4dda5c437f0 | 87 | This parameter can be a value of @ref ADC_ClockPrescaler */ |
| mbed_official | 133:d4dda5c437f0 | 88 | uint32_t Resolution; /*!< Configures the ADC resolution dual mode. |
| mbed_official | 133:d4dda5c437f0 | 89 | This parameter can be a value of @ref ADC_Resolution */ |
| mbed_official | 133:d4dda5c437f0 | 90 | uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. |
| mbed_official | 133:d4dda5c437f0 | 91 | This parameter can be a value of @ref ADC_data_align */ |
| mbed_official | 133:d4dda5c437f0 | 92 | uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or |
| mbed_official | 133:d4dda5c437f0 | 93 | Single (one channel) mode. |
| mbed_official | 133:d4dda5c437f0 | 94 | This parameter can be set to ENABLE or DISABLE */ |
| mbed_official | 133:d4dda5c437f0 | 95 | uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set |
| mbed_official | 133:d4dda5c437f0 | 96 | at the end of single channel conversion or at the end of all conversions. |
| mbed_official | 133:d4dda5c437f0 | 97 | This parameter can be a value of @ref ADC_EOCSelection */ |
| mbed_official | 133:d4dda5c437f0 | 98 | uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode. |
| mbed_official | 133:d4dda5c437f0 | 99 | This parameter can be set to ENABLE or DISABLE. */ |
| mbed_official | 133:d4dda5c437f0 | 100 | uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode. |
| mbed_official | 133:d4dda5c437f0 | 101 | This parameter can be set to ENABLE or DISABLE. */ |
| mbed_official | 133:d4dda5c437f0 | 102 | uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for |
| mbed_official | 133:d4dda5c437f0 | 103 | regular channel group. |
| mbed_official | 133:d4dda5c437f0 | 104 | This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ |
| mbed_official | 133:d4dda5c437f0 | 105 | uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not |
| mbed_official | 133:d4dda5c437f0 | 106 | for regular channels. |
| mbed_official | 133:d4dda5c437f0 | 107 | This parameter can be set to ENABLE or DISABLE. */ |
| mbed_official | 133:d4dda5c437f0 | 108 | uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done |
| mbed_official | 133:d4dda5c437f0 | 109 | using the sequencer for regular channel group. |
| mbed_official | 133:d4dda5c437f0 | 110 | This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ |
| mbed_official | 133:d4dda5c437f0 | 111 | uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger of a regular group. |
| mbed_official | 133:d4dda5c437f0 | 112 | This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ |
| mbed_official | 133:d4dda5c437f0 | 113 | uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion of a regular group. |
| mbed_official | 133:d4dda5c437f0 | 114 | This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ |
| mbed_official | 133:d4dda5c437f0 | 115 | }ADC_InitTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 116 | |
| mbed_official | 133:d4dda5c437f0 | 117 | /** |
| mbed_official | 133:d4dda5c437f0 | 118 | * @brief ADC handle Structure definition |
| mbed_official | 133:d4dda5c437f0 | 119 | */ |
| mbed_official | 133:d4dda5c437f0 | 120 | typedef struct |
| mbed_official | 133:d4dda5c437f0 | 121 | { |
| mbed_official | 133:d4dda5c437f0 | 122 | ADC_TypeDef *Instance; /*!< Register base address */ |
| mbed_official | 133:d4dda5c437f0 | 123 | |
| mbed_official | 133:d4dda5c437f0 | 124 | ADC_InitTypeDef Init; /*!< ADC required parameters */ |
| mbed_official | 133:d4dda5c437f0 | 125 | |
| mbed_official | 133:d4dda5c437f0 | 126 | __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ |
| mbed_official | 133:d4dda5c437f0 | 127 | |
| mbed_official | 133:d4dda5c437f0 | 128 | DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ |
| mbed_official | 133:d4dda5c437f0 | 129 | |
| mbed_official | 133:d4dda5c437f0 | 130 | HAL_LockTypeDef Lock; /*!< ADC locking object */ |
| mbed_official | 133:d4dda5c437f0 | 131 | |
| mbed_official | 133:d4dda5c437f0 | 132 | __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */ |
| mbed_official | 133:d4dda5c437f0 | 133 | |
| mbed_official | 133:d4dda5c437f0 | 134 | __IO uint32_t ErrorCode; /*!< ADC Error code */ |
| mbed_official | 133:d4dda5c437f0 | 135 | }ADC_HandleTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 136 | |
| mbed_official | 133:d4dda5c437f0 | 137 | /** |
| mbed_official | 133:d4dda5c437f0 | 138 | * @brief ADC Configuration regular Channel structure definition |
| mbed_official | 133:d4dda5c437f0 | 139 | */ |
| mbed_official | 133:d4dda5c437f0 | 140 | typedef struct |
| mbed_official | 133:d4dda5c437f0 | 141 | { |
| mbed_official | 242:7074e42da0b2 | 142 | uint32_t Channel; /*!< The ADC channel to configure. |
| mbed_official | 133:d4dda5c437f0 | 143 | This parameter can be a value of @ref ADC_channels */ |
| mbed_official | 242:7074e42da0b2 | 144 | uint32_t Rank; /*!< The rank in the regular group sequencer. |
| mbed_official | 133:d4dda5c437f0 | 145 | This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ |
| mbed_official | 133:d4dda5c437f0 | 146 | uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel. |
| mbed_official | 133:d4dda5c437f0 | 147 | This parameter can be a value of @ref ADC_sampling_times */ |
| mbed_official | 133:d4dda5c437f0 | 148 | uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ |
| mbed_official | 133:d4dda5c437f0 | 149 | }ADC_ChannelConfTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 150 | |
| mbed_official | 133:d4dda5c437f0 | 151 | /** |
| mbed_official | 133:d4dda5c437f0 | 152 | * @brief ADC Configuration multi-mode structure definition |
| mbed_official | 133:d4dda5c437f0 | 153 | */ |
| mbed_official | 133:d4dda5c437f0 | 154 | typedef struct |
| mbed_official | 133:d4dda5c437f0 | 155 | { |
| mbed_official | 133:d4dda5c437f0 | 156 | uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. |
| mbed_official | 242:7074e42da0b2 | 157 | This parameter can be a value of @ref ADC_analog_watchdog_selection */ |
| mbed_official | 133:d4dda5c437f0 | 158 | uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| mbed_official | 133:d4dda5c437f0 | 159 | This parameter must be a 12-bit value. */ |
| mbed_official | 133:d4dda5c437f0 | 160 | uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| mbed_official | 133:d4dda5c437f0 | 161 | This parameter must be a 12-bit value. */ |
| mbed_official | 133:d4dda5c437f0 | 162 | uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. |
| mbed_official | 133:d4dda5c437f0 | 163 | This parameter has an effect only if watchdog mode is configured on single channel |
| mbed_official | 242:7074e42da0b2 | 164 | This parameter can be a value of @ref ADC_channels */ |
| mbed_official | 133:d4dda5c437f0 | 165 | uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured |
| mbed_official | 133:d4dda5c437f0 | 166 | is interrupt mode or in polling mode. |
| mbed_official | 133:d4dda5c437f0 | 167 | This parameter can be set to ENABLE or DISABLE */ |
| mbed_official | 133:d4dda5c437f0 | 168 | uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ |
| mbed_official | 133:d4dda5c437f0 | 169 | }ADC_AnalogWDGConfTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 170 | |
| mbed_official | 133:d4dda5c437f0 | 171 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 172 | |
| mbed_official | 133:d4dda5c437f0 | 173 | /** @defgroup ADC_Exported_Constants |
| mbed_official | 133:d4dda5c437f0 | 174 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 175 | */ |
| mbed_official | 133:d4dda5c437f0 | 176 | |
| mbed_official | 133:d4dda5c437f0 | 177 | |
| mbed_official | 133:d4dda5c437f0 | 178 | /** @defgroup ADC_Error_Code |
| mbed_official | 133:d4dda5c437f0 | 179 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 180 | */ |
| mbed_official | 133:d4dda5c437f0 | 181 | |
| mbed_official | 133:d4dda5c437f0 | 182 | #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ |
| mbed_official | 133:d4dda5c437f0 | 183 | #define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */ |
| mbed_official | 133:d4dda5c437f0 | 184 | #define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */ |
| mbed_official | 133:d4dda5c437f0 | 185 | /** |
| mbed_official | 133:d4dda5c437f0 | 186 | * @} |
| mbed_official | 133:d4dda5c437f0 | 187 | */ |
| mbed_official | 133:d4dda5c437f0 | 188 | |
| mbed_official | 133:d4dda5c437f0 | 189 | |
| mbed_official | 133:d4dda5c437f0 | 190 | /** @defgroup ADC_ClockPrescaler |
| mbed_official | 133:d4dda5c437f0 | 191 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 192 | */ |
| mbed_official | 133:d4dda5c437f0 | 193 | #define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 194 | #define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) |
| mbed_official | 133:d4dda5c437f0 | 195 | #define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) |
| mbed_official | 133:d4dda5c437f0 | 196 | #define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) |
| mbed_official | 133:d4dda5c437f0 | 197 | #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \ |
| mbed_official | 133:d4dda5c437f0 | 198 | ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \ |
| mbed_official | 133:d4dda5c437f0 | 199 | ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \ |
| mbed_official | 133:d4dda5c437f0 | 200 | ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8)) |
| mbed_official | 133:d4dda5c437f0 | 201 | /** |
| mbed_official | 133:d4dda5c437f0 | 202 | * @} |
| mbed_official | 133:d4dda5c437f0 | 203 | */ |
| mbed_official | 133:d4dda5c437f0 | 204 | |
| mbed_official | 133:d4dda5c437f0 | 205 | /** @defgroup ADC_Resolution |
| mbed_official | 133:d4dda5c437f0 | 206 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 207 | */ |
| mbed_official | 133:d4dda5c437f0 | 208 | #define ADC_RESOLUTION12b ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 209 | #define ADC_RESOLUTION10b ((uint32_t)ADC_CR1_RES_0) |
| mbed_official | 133:d4dda5c437f0 | 210 | #define ADC_RESOLUTION8b ((uint32_t)ADC_CR1_RES_1) |
| mbed_official | 133:d4dda5c437f0 | 211 | #define ADC_RESOLUTION6b ((uint32_t)ADC_CR1_RES) |
| mbed_official | 133:d4dda5c437f0 | 212 | |
| mbed_official | 133:d4dda5c437f0 | 213 | #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \ |
| mbed_official | 133:d4dda5c437f0 | 214 | ((RESOLUTION) == ADC_RESOLUTION10b) || \ |
| mbed_official | 133:d4dda5c437f0 | 215 | ((RESOLUTION) == ADC_RESOLUTION8b) || \ |
| mbed_official | 133:d4dda5c437f0 | 216 | ((RESOLUTION) == ADC_RESOLUTION6b)) |
| mbed_official | 133:d4dda5c437f0 | 217 | /** |
| mbed_official | 133:d4dda5c437f0 | 218 | * @} |
| mbed_official | 133:d4dda5c437f0 | 219 | */ |
| mbed_official | 133:d4dda5c437f0 | 220 | |
| mbed_official | 133:d4dda5c437f0 | 221 | /** @defgroup ADC_External_trigger_edge_Regular |
| mbed_official | 133:d4dda5c437f0 | 222 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 223 | */ |
| mbed_official | 133:d4dda5c437f0 | 224 | #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 225 | #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) |
| mbed_official | 133:d4dda5c437f0 | 226 | #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) |
| mbed_official | 133:d4dda5c437f0 | 227 | #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) |
| mbed_official | 133:d4dda5c437f0 | 228 | |
| mbed_official | 133:d4dda5c437f0 | 229 | #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ |
| mbed_official | 133:d4dda5c437f0 | 230 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ |
| mbed_official | 133:d4dda5c437f0 | 231 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ |
| mbed_official | 133:d4dda5c437f0 | 232 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) |
| mbed_official | 133:d4dda5c437f0 | 233 | /** |
| mbed_official | 133:d4dda5c437f0 | 234 | * @} |
| mbed_official | 133:d4dda5c437f0 | 235 | */ |
| mbed_official | 133:d4dda5c437f0 | 236 | |
| mbed_official | 133:d4dda5c437f0 | 237 | /** @defgroup ADC_External_trigger_Source_Regular |
| mbed_official | 133:d4dda5c437f0 | 238 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 239 | */ |
| mbed_official | 133:d4dda5c437f0 | 240 | #define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 241 | #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) |
| mbed_official | 133:d4dda5c437f0 | 242 | #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) |
| mbed_official | 133:d4dda5c437f0 | 243 | #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
| mbed_official | 133:d4dda5c437f0 | 244 | #define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2) |
| mbed_official | 133:d4dda5c437f0 | 245 | #define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) |
| mbed_official | 133:d4dda5c437f0 | 246 | #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) |
| mbed_official | 133:d4dda5c437f0 | 247 | #define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
| mbed_official | 133:d4dda5c437f0 | 248 | #define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3) |
| mbed_official | 133:d4dda5c437f0 | 249 | #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) |
| mbed_official | 133:d4dda5c437f0 | 250 | #define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) |
| mbed_official | 133:d4dda5c437f0 | 251 | #define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
| mbed_official | 133:d4dda5c437f0 | 252 | #define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) |
| mbed_official | 133:d4dda5c437f0 | 253 | #define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) |
| mbed_official | 133:d4dda5c437f0 | 254 | #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) |
| mbed_official | 133:d4dda5c437f0 | 255 | #define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL) |
| mbed_official | 133:d4dda5c437f0 | 256 | |
| mbed_official | 133:d4dda5c437f0 | 257 | #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ |
| mbed_official | 133:d4dda5c437f0 | 258 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ |
| mbed_official | 133:d4dda5c437f0 | 259 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ |
| mbed_official | 133:d4dda5c437f0 | 260 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ |
| mbed_official | 133:d4dda5c437f0 | 261 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ |
| mbed_official | 133:d4dda5c437f0 | 262 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \ |
| mbed_official | 133:d4dda5c437f0 | 263 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ |
| mbed_official | 133:d4dda5c437f0 | 264 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ |
| mbed_official | 133:d4dda5c437f0 | 265 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ |
| mbed_official | 133:d4dda5c437f0 | 266 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ |
| mbed_official | 133:d4dda5c437f0 | 267 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ |
| mbed_official | 133:d4dda5c437f0 | 268 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \ |
| mbed_official | 133:d4dda5c437f0 | 269 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ |
| mbed_official | 133:d4dda5c437f0 | 270 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ |
| mbed_official | 133:d4dda5c437f0 | 271 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ |
| mbed_official | 133:d4dda5c437f0 | 272 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)) |
| mbed_official | 133:d4dda5c437f0 | 273 | /** |
| mbed_official | 133:d4dda5c437f0 | 274 | * @} |
| mbed_official | 133:d4dda5c437f0 | 275 | */ |
| mbed_official | 133:d4dda5c437f0 | 276 | |
| mbed_official | 133:d4dda5c437f0 | 277 | /** @defgroup ADC_data_align |
| mbed_official | 133:d4dda5c437f0 | 278 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 279 | */ |
| mbed_official | 133:d4dda5c437f0 | 280 | #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 281 | #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) |
| mbed_official | 133:d4dda5c437f0 | 282 | |
| mbed_official | 133:d4dda5c437f0 | 283 | #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ |
| mbed_official | 133:d4dda5c437f0 | 284 | ((ALIGN) == ADC_DATAALIGN_LEFT)) |
| mbed_official | 133:d4dda5c437f0 | 285 | /** |
| mbed_official | 133:d4dda5c437f0 | 286 | * @} |
| mbed_official | 133:d4dda5c437f0 | 287 | */ |
| mbed_official | 133:d4dda5c437f0 | 288 | |
| mbed_official | 133:d4dda5c437f0 | 289 | /** @defgroup ADC_channels |
| mbed_official | 133:d4dda5c437f0 | 290 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 291 | */ |
| mbed_official | 133:d4dda5c437f0 | 292 | #define ADC_CHANNEL_0 ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 293 | #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) |
| mbed_official | 133:d4dda5c437f0 | 294 | #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) |
| mbed_official | 133:d4dda5c437f0 | 295 | #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
| mbed_official | 133:d4dda5c437f0 | 296 | #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) |
| mbed_official | 133:d4dda5c437f0 | 297 | #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) |
| mbed_official | 133:d4dda5c437f0 | 298 | #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) |
| mbed_official | 133:d4dda5c437f0 | 299 | #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
| mbed_official | 133:d4dda5c437f0 | 300 | #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) |
| mbed_official | 133:d4dda5c437f0 | 301 | #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) |
| mbed_official | 133:d4dda5c437f0 | 302 | #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) |
| mbed_official | 133:d4dda5c437f0 | 303 | #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
| mbed_official | 133:d4dda5c437f0 | 304 | #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) |
| mbed_official | 133:d4dda5c437f0 | 305 | #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) |
| mbed_official | 133:d4dda5c437f0 | 306 | #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) |
| mbed_official | 133:d4dda5c437f0 | 307 | #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
| mbed_official | 133:d4dda5c437f0 | 308 | #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) |
| mbed_official | 133:d4dda5c437f0 | 309 | #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) |
| mbed_official | 133:d4dda5c437f0 | 310 | #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) |
| mbed_official | 133:d4dda5c437f0 | 311 | |
| mbed_official | 133:d4dda5c437f0 | 312 | #define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16) |
| mbed_official | 133:d4dda5c437f0 | 313 | #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) |
| mbed_official | 133:d4dda5c437f0 | 314 | #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) |
| mbed_official | 133:d4dda5c437f0 | 315 | |
| mbed_official | 133:d4dda5c437f0 | 316 | #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ |
| mbed_official | 133:d4dda5c437f0 | 317 | ((CHANNEL) == ADC_CHANNEL_1) || \ |
| mbed_official | 133:d4dda5c437f0 | 318 | ((CHANNEL) == ADC_CHANNEL_2) || \ |
| mbed_official | 133:d4dda5c437f0 | 319 | ((CHANNEL) == ADC_CHANNEL_3) || \ |
| mbed_official | 133:d4dda5c437f0 | 320 | ((CHANNEL) == ADC_CHANNEL_4) || \ |
| mbed_official | 133:d4dda5c437f0 | 321 | ((CHANNEL) == ADC_CHANNEL_5) || \ |
| mbed_official | 133:d4dda5c437f0 | 322 | ((CHANNEL) == ADC_CHANNEL_6) || \ |
| mbed_official | 133:d4dda5c437f0 | 323 | ((CHANNEL) == ADC_CHANNEL_7) || \ |
| mbed_official | 133:d4dda5c437f0 | 324 | ((CHANNEL) == ADC_CHANNEL_8) || \ |
| mbed_official | 133:d4dda5c437f0 | 325 | ((CHANNEL) == ADC_CHANNEL_9) || \ |
| mbed_official | 133:d4dda5c437f0 | 326 | ((CHANNEL) == ADC_CHANNEL_10) || \ |
| mbed_official | 133:d4dda5c437f0 | 327 | ((CHANNEL) == ADC_CHANNEL_11) || \ |
| mbed_official | 133:d4dda5c437f0 | 328 | ((CHANNEL) == ADC_CHANNEL_12) || \ |
| mbed_official | 133:d4dda5c437f0 | 329 | ((CHANNEL) == ADC_CHANNEL_13) || \ |
| mbed_official | 133:d4dda5c437f0 | 330 | ((CHANNEL) == ADC_CHANNEL_14) || \ |
| mbed_official | 133:d4dda5c437f0 | 331 | ((CHANNEL) == ADC_CHANNEL_15) || \ |
| mbed_official | 133:d4dda5c437f0 | 332 | ((CHANNEL) == ADC_CHANNEL_16) || \ |
| mbed_official | 133:d4dda5c437f0 | 333 | ((CHANNEL) == ADC_CHANNEL_17) || \ |
| mbed_official | 133:d4dda5c437f0 | 334 | ((CHANNEL) == ADC_CHANNEL_18)) |
| mbed_official | 133:d4dda5c437f0 | 335 | /** |
| mbed_official | 133:d4dda5c437f0 | 336 | * @} |
| mbed_official | 133:d4dda5c437f0 | 337 | */ |
| mbed_official | 133:d4dda5c437f0 | 338 | |
| mbed_official | 133:d4dda5c437f0 | 339 | /** @defgroup ADC_sampling_times |
| mbed_official | 133:d4dda5c437f0 | 340 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 341 | */ |
| mbed_official | 133:d4dda5c437f0 | 342 | #define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 343 | #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) |
| mbed_official | 133:d4dda5c437f0 | 344 | #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) |
| mbed_official | 133:d4dda5c437f0 | 345 | #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) |
| mbed_official | 133:d4dda5c437f0 | 346 | #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) |
| mbed_official | 133:d4dda5c437f0 | 347 | #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) |
| mbed_official | 133:d4dda5c437f0 | 348 | #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) |
| mbed_official | 133:d4dda5c437f0 | 349 | #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) |
| mbed_official | 133:d4dda5c437f0 | 350 | |
| mbed_official | 133:d4dda5c437f0 | 351 | #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \ |
| mbed_official | 133:d4dda5c437f0 | 352 | ((TIME) == ADC_SAMPLETIME_15CYCLES) || \ |
| mbed_official | 133:d4dda5c437f0 | 353 | ((TIME) == ADC_SAMPLETIME_28CYCLES) || \ |
| mbed_official | 133:d4dda5c437f0 | 354 | ((TIME) == ADC_SAMPLETIME_56CYCLES) || \ |
| mbed_official | 133:d4dda5c437f0 | 355 | ((TIME) == ADC_SAMPLETIME_84CYCLES) || \ |
| mbed_official | 133:d4dda5c437f0 | 356 | ((TIME) == ADC_SAMPLETIME_112CYCLES) || \ |
| mbed_official | 133:d4dda5c437f0 | 357 | ((TIME) == ADC_SAMPLETIME_144CYCLES) || \ |
| mbed_official | 133:d4dda5c437f0 | 358 | ((TIME) == ADC_SAMPLETIME_480CYCLES)) |
| mbed_official | 133:d4dda5c437f0 | 359 | /** |
| mbed_official | 133:d4dda5c437f0 | 360 | * @} |
| mbed_official | 133:d4dda5c437f0 | 361 | */ |
| mbed_official | 133:d4dda5c437f0 | 362 | |
| mbed_official | 133:d4dda5c437f0 | 363 | /** @defgroup ADC_EOCSelection |
| mbed_official | 133:d4dda5c437f0 | 364 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 365 | */ |
| mbed_official | 133:d4dda5c437f0 | 366 | #define EOC_SEQ_CONV ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 367 | #define EOC_SINGLE_CONV ((uint32_t)0x00000001) |
| mbed_official | 133:d4dda5c437f0 | 368 | #define EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */ |
| mbed_official | 133:d4dda5c437f0 | 369 | |
| mbed_official | 133:d4dda5c437f0 | 370 | #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == EOC_SINGLE_CONV) || \ |
| mbed_official | 133:d4dda5c437f0 | 371 | ((EOCSelection) == EOC_SEQ_CONV) || \ |
| mbed_official | 133:d4dda5c437f0 | 372 | ((EOCSelection) == EOC_SINGLE_SEQ_CONV)) |
| mbed_official | 133:d4dda5c437f0 | 373 | /** |
| mbed_official | 133:d4dda5c437f0 | 374 | * @} |
| mbed_official | 133:d4dda5c437f0 | 375 | */ |
| mbed_official | 133:d4dda5c437f0 | 376 | |
| mbed_official | 133:d4dda5c437f0 | 377 | /** @defgroup ADC_Event_type |
| mbed_official | 133:d4dda5c437f0 | 378 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 379 | */ |
| mbed_official | 133:d4dda5c437f0 | 380 | #define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) |
| mbed_official | 133:d4dda5c437f0 | 381 | #define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) |
| mbed_official | 133:d4dda5c437f0 | 382 | |
| mbed_official | 133:d4dda5c437f0 | 383 | #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \ |
| mbed_official | 133:d4dda5c437f0 | 384 | ((EVENT) == OVR_EVENT)) |
| mbed_official | 133:d4dda5c437f0 | 385 | /** |
| mbed_official | 133:d4dda5c437f0 | 386 | * @} |
| mbed_official | 133:d4dda5c437f0 | 387 | */ |
| mbed_official | 133:d4dda5c437f0 | 388 | |
| mbed_official | 133:d4dda5c437f0 | 389 | /** @defgroup ADC_analog_watchdog_selection |
| mbed_official | 133:d4dda5c437f0 | 390 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 391 | */ |
| mbed_official | 133:d4dda5c437f0 | 392 | #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) |
| mbed_official | 133:d4dda5c437f0 | 393 | #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) |
| mbed_official | 133:d4dda5c437f0 | 394 | #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
| mbed_official | 133:d4dda5c437f0 | 395 | #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) |
| mbed_official | 133:d4dda5c437f0 | 396 | #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) |
| mbed_official | 133:d4dda5c437f0 | 397 | #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
| mbed_official | 133:d4dda5c437f0 | 398 | #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 399 | |
| mbed_official | 133:d4dda5c437f0 | 400 | #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ |
| mbed_official | 133:d4dda5c437f0 | 401 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ |
| mbed_official | 133:d4dda5c437f0 | 402 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ |
| mbed_official | 133:d4dda5c437f0 | 403 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ |
| mbed_official | 133:d4dda5c437f0 | 404 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ |
| mbed_official | 133:d4dda5c437f0 | 405 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ |
| mbed_official | 133:d4dda5c437f0 | 406 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)) |
| mbed_official | 133:d4dda5c437f0 | 407 | /** |
| mbed_official | 133:d4dda5c437f0 | 408 | * @} |
| mbed_official | 133:d4dda5c437f0 | 409 | */ |
| mbed_official | 133:d4dda5c437f0 | 410 | |
| mbed_official | 133:d4dda5c437f0 | 411 | /** @defgroup ADC_interrupts_definition |
| mbed_official | 133:d4dda5c437f0 | 412 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 413 | */ |
| mbed_official | 133:d4dda5c437f0 | 414 | #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) |
| mbed_official | 133:d4dda5c437f0 | 415 | #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) |
| mbed_official | 133:d4dda5c437f0 | 416 | #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) |
| mbed_official | 133:d4dda5c437f0 | 417 | #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) |
| mbed_official | 133:d4dda5c437f0 | 418 | |
| mbed_official | 133:d4dda5c437f0 | 419 | #define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ |
| mbed_official | 133:d4dda5c437f0 | 420 | ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) |
| mbed_official | 133:d4dda5c437f0 | 421 | /** |
| mbed_official | 133:d4dda5c437f0 | 422 | * @} |
| mbed_official | 133:d4dda5c437f0 | 423 | */ |
| mbed_official | 133:d4dda5c437f0 | 424 | |
| mbed_official | 133:d4dda5c437f0 | 425 | /** @defgroup ADC_flags_definition |
| mbed_official | 133:d4dda5c437f0 | 426 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 427 | */ |
| mbed_official | 133:d4dda5c437f0 | 428 | #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) |
| mbed_official | 133:d4dda5c437f0 | 429 | #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) |
| mbed_official | 133:d4dda5c437f0 | 430 | #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) |
| mbed_official | 133:d4dda5c437f0 | 431 | #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) |
| mbed_official | 133:d4dda5c437f0 | 432 | #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) |
| mbed_official | 133:d4dda5c437f0 | 433 | #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) |
| mbed_official | 133:d4dda5c437f0 | 434 | /** |
| mbed_official | 133:d4dda5c437f0 | 435 | * @} |
| mbed_official | 133:d4dda5c437f0 | 436 | */ |
| mbed_official | 133:d4dda5c437f0 | 437 | |
| mbed_official | 133:d4dda5c437f0 | 438 | /** @defgroup ADC_channels_type |
| mbed_official | 133:d4dda5c437f0 | 439 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 440 | */ |
| mbed_official | 133:d4dda5c437f0 | 441 | #define ALL_CHANNELS ((uint32_t)0x00000001) |
| mbed_official | 133:d4dda5c437f0 | 442 | #define REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */ |
| mbed_official | 133:d4dda5c437f0 | 443 | #define INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */ |
| mbed_official | 133:d4dda5c437f0 | 444 | |
| mbed_official | 133:d4dda5c437f0 | 445 | #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ALL_CHANNELS) || \ |
| mbed_official | 133:d4dda5c437f0 | 446 | ((CHANNEL_TYPE) == REGULAR_CHANNELS) || \ |
| mbed_official | 133:d4dda5c437f0 | 447 | ((CHANNEL_TYPE) == INJECTED_CHANNELS)) |
| mbed_official | 133:d4dda5c437f0 | 448 | /** |
| mbed_official | 133:d4dda5c437f0 | 449 | * @} |
| mbed_official | 133:d4dda5c437f0 | 450 | */ |
| mbed_official | 133:d4dda5c437f0 | 451 | |
| mbed_official | 133:d4dda5c437f0 | 452 | /** @defgroup ADC_thresholds |
| mbed_official | 133:d4dda5c437f0 | 453 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 454 | */ |
| mbed_official | 133:d4dda5c437f0 | 455 | #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF)) |
| mbed_official | 133:d4dda5c437f0 | 456 | /** |
| mbed_official | 133:d4dda5c437f0 | 457 | * @} |
| mbed_official | 133:d4dda5c437f0 | 458 | */ |
| mbed_official | 133:d4dda5c437f0 | 459 | |
| mbed_official | 133:d4dda5c437f0 | 460 | /** @defgroup ADC_regular_length |
| mbed_official | 133:d4dda5c437f0 | 461 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 462 | */ |
| mbed_official | 133:d4dda5c437f0 | 463 | #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16))) |
| mbed_official | 133:d4dda5c437f0 | 464 | /** |
| mbed_official | 133:d4dda5c437f0 | 465 | * @} |
| mbed_official | 133:d4dda5c437f0 | 466 | */ |
| mbed_official | 133:d4dda5c437f0 | 467 | |
| mbed_official | 133:d4dda5c437f0 | 468 | /** @defgroup ADC_regular_rank |
| mbed_official | 133:d4dda5c437f0 | 469 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 470 | */ |
| mbed_official | 133:d4dda5c437f0 | 471 | #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16))) |
| mbed_official | 133:d4dda5c437f0 | 472 | /** |
| mbed_official | 133:d4dda5c437f0 | 473 | * @} |
| mbed_official | 133:d4dda5c437f0 | 474 | */ |
| mbed_official | 133:d4dda5c437f0 | 475 | |
| mbed_official | 133:d4dda5c437f0 | 476 | /** @defgroup ADC_regular_discontinuous_mode_number |
| mbed_official | 133:d4dda5c437f0 | 477 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 478 | */ |
| mbed_official | 133:d4dda5c437f0 | 479 | #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) |
| mbed_official | 133:d4dda5c437f0 | 480 | /** |
| mbed_official | 133:d4dda5c437f0 | 481 | * @} |
| mbed_official | 133:d4dda5c437f0 | 482 | */ |
| mbed_official | 133:d4dda5c437f0 | 483 | |
| mbed_official | 133:d4dda5c437f0 | 484 | /** @defgroup ADC_range_verification |
| mbed_official | 133:d4dda5c437f0 | 485 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 486 | */ |
| mbed_official | 133:d4dda5c437f0 | 487 | #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ |
| mbed_official | 133:d4dda5c437f0 | 488 | ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \ |
| mbed_official | 133:d4dda5c437f0 | 489 | (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \ |
| mbed_official | 133:d4dda5c437f0 | 490 | (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \ |
| mbed_official | 133:d4dda5c437f0 | 491 | (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F)))) |
| mbed_official | 133:d4dda5c437f0 | 492 | /** |
| mbed_official | 133:d4dda5c437f0 | 493 | * @} |
| mbed_official | 133:d4dda5c437f0 | 494 | */ |
| mbed_official | 133:d4dda5c437f0 | 495 | |
| mbed_official | 133:d4dda5c437f0 | 496 | /** |
| mbed_official | 133:d4dda5c437f0 | 497 | * @} |
| mbed_official | 133:d4dda5c437f0 | 498 | */ |
| mbed_official | 133:d4dda5c437f0 | 499 | |
| mbed_official | 133:d4dda5c437f0 | 500 | /* Exported macro ------------------------------------------------------------*/ |
| mbed_official | 242:7074e42da0b2 | 501 | |
| mbed_official | 242:7074e42da0b2 | 502 | /** @brief Reset ADC handle state |
| mbed_official | 242:7074e42da0b2 | 503 | * @param __HANDLE__: ADC handle |
| mbed_official | 242:7074e42da0b2 | 504 | * @retval None |
| mbed_official | 242:7074e42da0b2 | 505 | */ |
| mbed_official | 242:7074e42da0b2 | 506 | #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) |
| mbed_official | 242:7074e42da0b2 | 507 | |
| mbed_official | 133:d4dda5c437f0 | 508 | /** |
| mbed_official | 133:d4dda5c437f0 | 509 | * @brief Enable the ADC peripheral. |
| mbed_official | 133:d4dda5c437f0 | 510 | * @param __HANDLE__: ADC handle |
| mbed_official | 133:d4dda5c437f0 | 511 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 512 | */ |
| mbed_official | 133:d4dda5c437f0 | 513 | #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) |
| mbed_official | 133:d4dda5c437f0 | 514 | |
| mbed_official | 133:d4dda5c437f0 | 515 | /** |
| mbed_official | 133:d4dda5c437f0 | 516 | * @brief Disable the ADC peripheral. |
| mbed_official | 133:d4dda5c437f0 | 517 | * @param __HANDLE__: ADC handle |
| mbed_official | 133:d4dda5c437f0 | 518 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 519 | */ |
| mbed_official | 133:d4dda5c437f0 | 520 | #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) |
| mbed_official | 133:d4dda5c437f0 | 521 | |
| mbed_official | 133:d4dda5c437f0 | 522 | /** |
| mbed_official | 133:d4dda5c437f0 | 523 | * @brief Set ADC Regular channel sequence length. |
| mbed_official | 133:d4dda5c437f0 | 524 | * @param _NbrOfConversion_: Regular channel sequence length. |
| mbed_official | 133:d4dda5c437f0 | 525 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 526 | */ |
| mbed_official | 133:d4dda5c437f0 | 527 | #define __HAL_ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20) |
| mbed_official | 133:d4dda5c437f0 | 528 | |
| mbed_official | 133:d4dda5c437f0 | 529 | /** |
| mbed_official | 133:d4dda5c437f0 | 530 | * @brief Set the ADC's sample time for channel numbers between 10 and 18. |
| mbed_official | 133:d4dda5c437f0 | 531 | * @param _SAMPLETIME_: Sample time parameter. |
| mbed_official | 133:d4dda5c437f0 | 532 | * @param _CHANNELNB_: Channel number. |
| mbed_official | 133:d4dda5c437f0 | 533 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 534 | */ |
| mbed_official | 133:d4dda5c437f0 | 535 | #define __HAL_ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10))) |
| mbed_official | 133:d4dda5c437f0 | 536 | |
| mbed_official | 133:d4dda5c437f0 | 537 | /** |
| mbed_official | 133:d4dda5c437f0 | 538 | * @brief Set the ADC's sample time for channel numbers between 0 and 9. |
| mbed_official | 133:d4dda5c437f0 | 539 | * @param _SAMPLETIME_: Sample time parameter. |
| mbed_official | 133:d4dda5c437f0 | 540 | * @param _CHANNELNB_: Channel number. |
| mbed_official | 133:d4dda5c437f0 | 541 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 542 | */ |
| mbed_official | 133:d4dda5c437f0 | 543 | #define __HAL_ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_))) |
| mbed_official | 133:d4dda5c437f0 | 544 | |
| mbed_official | 133:d4dda5c437f0 | 545 | /** |
| mbed_official | 133:d4dda5c437f0 | 546 | * @brief Set the selected regular channel rank for rank between 1 and 6. |
| mbed_official | 133:d4dda5c437f0 | 547 | * @param _CHANNELNB_: Channel number. |
| mbed_official | 133:d4dda5c437f0 | 548 | * @param _RANKNB_: Rank number. |
| mbed_official | 133:d4dda5c437f0 | 549 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 550 | */ |
| mbed_official | 133:d4dda5c437f0 | 551 | #define __HAL_ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1))) |
| mbed_official | 133:d4dda5c437f0 | 552 | |
| mbed_official | 133:d4dda5c437f0 | 553 | /** |
| mbed_official | 133:d4dda5c437f0 | 554 | * @brief Set the selected regular channel rank for rank between 7 and 12. |
| mbed_official | 133:d4dda5c437f0 | 555 | * @param _CHANNELNB_: Channel number. |
| mbed_official | 133:d4dda5c437f0 | 556 | * @param _RANKNB_: Rank number. |
| mbed_official | 133:d4dda5c437f0 | 557 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 558 | */ |
| mbed_official | 133:d4dda5c437f0 | 559 | #define __HAL_ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7))) |
| mbed_official | 133:d4dda5c437f0 | 560 | |
| mbed_official | 133:d4dda5c437f0 | 561 | /** |
| mbed_official | 133:d4dda5c437f0 | 562 | * @brief Set the selected regular channel rank for rank between 13 and 16. |
| mbed_official | 133:d4dda5c437f0 | 563 | * @param _CHANNELNB_: Channel number. |
| mbed_official | 133:d4dda5c437f0 | 564 | * @param _RANKNB_: Rank number. |
| mbed_official | 133:d4dda5c437f0 | 565 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 566 | */ |
| mbed_official | 133:d4dda5c437f0 | 567 | #define __HAL_ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13))) |
| mbed_official | 133:d4dda5c437f0 | 568 | |
| mbed_official | 133:d4dda5c437f0 | 569 | /** |
| mbed_official | 133:d4dda5c437f0 | 570 | * @brief Enable ADC continuous conversion mode. |
| mbed_official | 133:d4dda5c437f0 | 571 | * @param _CONTINUOUS_MODE_: Continuous mode. |
| mbed_official | 133:d4dda5c437f0 | 572 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 573 | */ |
| mbed_official | 133:d4dda5c437f0 | 574 | #define __HAL_ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1) |
| mbed_official | 133:d4dda5c437f0 | 575 | |
| mbed_official | 133:d4dda5c437f0 | 576 | /** |
| mbed_official | 133:d4dda5c437f0 | 577 | * @brief Configures the number of discontinuous conversions for the regular group channels. |
| mbed_official | 133:d4dda5c437f0 | 578 | * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions. |
| mbed_official | 133:d4dda5c437f0 | 579 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 580 | */ |
| mbed_official | 133:d4dda5c437f0 | 581 | #define __HAL_ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << 13) |
| mbed_official | 133:d4dda5c437f0 | 582 | |
| mbed_official | 133:d4dda5c437f0 | 583 | /** |
| mbed_official | 133:d4dda5c437f0 | 584 | * @brief Enable ADC scan mode. |
| mbed_official | 133:d4dda5c437f0 | 585 | * @param _SCANCONV_MODE_: Scan conversion mode. |
| mbed_official | 133:d4dda5c437f0 | 586 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 587 | */ |
| mbed_official | 133:d4dda5c437f0 | 588 | #define __HAL_ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8) |
| mbed_official | 133:d4dda5c437f0 | 589 | |
| mbed_official | 133:d4dda5c437f0 | 590 | /** |
| mbed_official | 133:d4dda5c437f0 | 591 | * @brief Enable the ADC end of conversion selection. |
| mbed_official | 133:d4dda5c437f0 | 592 | * @param _EOCSelection_MODE_: End of conversion selection mode. |
| mbed_official | 133:d4dda5c437f0 | 593 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 594 | */ |
| mbed_official | 133:d4dda5c437f0 | 595 | #define __HAL_ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10) |
| mbed_official | 133:d4dda5c437f0 | 596 | |
| mbed_official | 133:d4dda5c437f0 | 597 | /** |
| mbed_official | 133:d4dda5c437f0 | 598 | * @brief Enable the ADC DMA continuous request. |
| mbed_official | 133:d4dda5c437f0 | 599 | * @param _DMAContReq_MODE_: DMA continuous request mode. |
| mbed_official | 133:d4dda5c437f0 | 600 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 601 | */ |
| mbed_official | 133:d4dda5c437f0 | 602 | #define __HAL_ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9) |
| mbed_official | 133:d4dda5c437f0 | 603 | |
| mbed_official | 133:d4dda5c437f0 | 604 | /** |
| mbed_official | 133:d4dda5c437f0 | 605 | * @brief Enable the ADC end of conversion interrupt. |
| mbed_official | 133:d4dda5c437f0 | 606 | * @param __HANDLE__: specifies the ADC Handle. |
| mbed_official | 133:d4dda5c437f0 | 607 | * @param __INTERRUPT__: ADC Interrupt. |
| mbed_official | 133:d4dda5c437f0 | 608 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 609 | */ |
| mbed_official | 133:d4dda5c437f0 | 610 | #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) |
| mbed_official | 133:d4dda5c437f0 | 611 | |
| mbed_official | 133:d4dda5c437f0 | 612 | /** |
| mbed_official | 133:d4dda5c437f0 | 613 | * @brief Disable the ADC end of conversion interrupt. |
| mbed_official | 133:d4dda5c437f0 | 614 | * @param __HANDLE__: specifies the ADC Handle. |
| mbed_official | 133:d4dda5c437f0 | 615 | * @param __INTERRUPT__: ADC interrupt. |
| mbed_official | 133:d4dda5c437f0 | 616 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 617 | */ |
| mbed_official | 133:d4dda5c437f0 | 618 | #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) |
| mbed_official | 133:d4dda5c437f0 | 619 | |
| mbed_official | 133:d4dda5c437f0 | 620 | /** @brief Check if the specified ADC interrupt source is enabled or disabled. |
| mbed_official | 133:d4dda5c437f0 | 621 | * @param __HANDLE__: specifies the ADC Handle. |
| mbed_official | 133:d4dda5c437f0 | 622 | * @param __INTERRUPT__: specifies the ADC interrupt source to check. |
| mbed_official | 133:d4dda5c437f0 | 623 | * @retval The new state of __IT__ (TRUE or FALSE). |
| mbed_official | 133:d4dda5c437f0 | 624 | */ |
| mbed_official | 133:d4dda5c437f0 | 625 | #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| mbed_official | 133:d4dda5c437f0 | 626 | |
| mbed_official | 133:d4dda5c437f0 | 627 | /** |
| mbed_official | 133:d4dda5c437f0 | 628 | * @brief Clear the ADC's pending flags. |
| mbed_official | 133:d4dda5c437f0 | 629 | * @param __HANDLE__: specifies the ADC Handle. |
| mbed_official | 133:d4dda5c437f0 | 630 | * @param __FLAG__: ADC flag. |
| mbed_official | 133:d4dda5c437f0 | 631 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 632 | */ |
| mbed_official | 133:d4dda5c437f0 | 633 | #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) &= ~(__FLAG__)) |
| mbed_official | 133:d4dda5c437f0 | 634 | |
| mbed_official | 133:d4dda5c437f0 | 635 | /** |
| mbed_official | 133:d4dda5c437f0 | 636 | * @brief Get the selected ADC's flag status. |
| mbed_official | 133:d4dda5c437f0 | 637 | * @param __HANDLE__: specifies the ADC Handle. |
| mbed_official | 133:d4dda5c437f0 | 638 | * @param __FLAG__: ADC flag. |
| mbed_official | 133:d4dda5c437f0 | 639 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 640 | */ |
| mbed_official | 133:d4dda5c437f0 | 641 | #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| mbed_official | 133:d4dda5c437f0 | 642 | |
| mbed_official | 133:d4dda5c437f0 | 643 | /** |
| mbed_official | 133:d4dda5c437f0 | 644 | * @brief Return resolution bits in CR1 register. |
| mbed_official | 133:d4dda5c437f0 | 645 | * @param __HANDLE__: ADC handle |
| mbed_official | 133:d4dda5c437f0 | 646 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 647 | */ |
| mbed_official | 133:d4dda5c437f0 | 648 | #define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) |
| mbed_official | 133:d4dda5c437f0 | 649 | |
| mbed_official | 133:d4dda5c437f0 | 650 | /* Include ADC HAL Extension module */ |
| mbed_official | 133:d4dda5c437f0 | 651 | #include "stm32f4xx_hal_adc_ex.h" |
| mbed_official | 133:d4dda5c437f0 | 652 | |
| mbed_official | 133:d4dda5c437f0 | 653 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 654 | /* Initialization/de-initialization functions ***********************************/ |
| mbed_official | 133:d4dda5c437f0 | 655 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 656 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); |
| mbed_official | 133:d4dda5c437f0 | 657 | void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 658 | void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 659 | |
| mbed_official | 133:d4dda5c437f0 | 660 | /* I/O operation functions ******************************************************/ |
| mbed_official | 133:d4dda5c437f0 | 661 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 662 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 663 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
| mbed_official | 133:d4dda5c437f0 | 664 | |
| mbed_official | 133:d4dda5c437f0 | 665 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); |
| mbed_official | 133:d4dda5c437f0 | 666 | |
| mbed_official | 133:d4dda5c437f0 | 667 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 668 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 669 | |
| mbed_official | 133:d4dda5c437f0 | 670 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 671 | |
| mbed_official | 133:d4dda5c437f0 | 672 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
| mbed_official | 133:d4dda5c437f0 | 673 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 674 | |
| mbed_official | 133:d4dda5c437f0 | 675 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 676 | |
| mbed_official | 133:d4dda5c437f0 | 677 | void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 678 | void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 679 | void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 680 | void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); |
| mbed_official | 133:d4dda5c437f0 | 681 | |
| mbed_official | 133:d4dda5c437f0 | 682 | /* Peripheral Control functions *************************************************/ |
| mbed_official | 133:d4dda5c437f0 | 683 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); |
| mbed_official | 133:d4dda5c437f0 | 684 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); |
| mbed_official | 133:d4dda5c437f0 | 685 | |
| mbed_official | 133:d4dda5c437f0 | 686 | /* Peripheral State functions ***************************************************/ |
| mbed_official | 133:d4dda5c437f0 | 687 | HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc); |
| mbed_official | 133:d4dda5c437f0 | 688 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); |
| mbed_official | 133:d4dda5c437f0 | 689 | |
| mbed_official | 133:d4dda5c437f0 | 690 | /** |
| mbed_official | 133:d4dda5c437f0 | 691 | * @} |
| mbed_official | 133:d4dda5c437f0 | 692 | */ |
| mbed_official | 133:d4dda5c437f0 | 693 | |
| mbed_official | 133:d4dda5c437f0 | 694 | /** |
| mbed_official | 133:d4dda5c437f0 | 695 | * @} |
| mbed_official | 133:d4dda5c437f0 | 696 | */ |
| mbed_official | 133:d4dda5c437f0 | 697 | |
| mbed_official | 133:d4dda5c437f0 | 698 | #ifdef __cplusplus |
| mbed_official | 133:d4dda5c437f0 | 699 | } |
| mbed_official | 133:d4dda5c437f0 | 700 | #endif |
| mbed_official | 133:d4dda5c437f0 | 701 | |
| mbed_official | 133:d4dda5c437f0 | 702 | #endif /*__STM32F4xx_ADC_H */ |
| mbed_official | 133:d4dda5c437f0 | 703 | |
| mbed_official | 133:d4dda5c437f0 | 704 | |
| mbed_official | 133:d4dda5c437f0 | 705 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |