Sigve Sebastian Farstad
mbed w/ spi bug fig
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mbed official
targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_i2s.h@242:7074e42da0b2, 2014-06-27 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jun 27 07:30:09 2014 +0100
- Revision:
- 242:7074e42da0b2
- Parent:
- 133:d4dda5c437f0
Synchronized with git revision 124ef5e3add9e74a3221347a3fbeea7c8b3cf353
Full URL: https://github.com/mbedmicro/mbed/commit/124ef5e3add9e74a3221347a3fbeea7c8b3cf353/
[DISCO_F407VG] HAL update.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 133:d4dda5c437f0 | 1 | /** |
| mbed_official | 133:d4dda5c437f0 | 2 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 3 | * @file stm32f4xx_hal_i2s.h |
| mbed_official | 133:d4dda5c437f0 | 4 | * @author MCD Application Team |
| mbed_official | 242:7074e42da0b2 | 5 | * @version V1.1.0RC2 |
| mbed_official | 242:7074e42da0b2 | 6 | * @date 14-May-2014 |
| mbed_official | 133:d4dda5c437f0 | 7 | * @brief Header file of I2S HAL module. |
| mbed_official | 133:d4dda5c437f0 | 8 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 9 | * @attention |
| mbed_official | 133:d4dda5c437f0 | 10 | * |
| mbed_official | 133:d4dda5c437f0 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 133:d4dda5c437f0 | 12 | * |
| mbed_official | 133:d4dda5c437f0 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 133:d4dda5c437f0 | 14 | * are permitted provided that the following conditions are met: |
| mbed_official | 133:d4dda5c437f0 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 133:d4dda5c437f0 | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 133:d4dda5c437f0 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 133:d4dda5c437f0 | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 133:d4dda5c437f0 | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 133:d4dda5c437f0 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 133:d4dda5c437f0 | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 133:d4dda5c437f0 | 22 | * without specific prior written permission. |
| mbed_official | 133:d4dda5c437f0 | 23 | * |
| mbed_official | 133:d4dda5c437f0 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 133:d4dda5c437f0 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 133:d4dda5c437f0 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 133:d4dda5c437f0 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 133:d4dda5c437f0 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 133:d4dda5c437f0 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 133:d4dda5c437f0 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 133:d4dda5c437f0 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 133:d4dda5c437f0 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 133:d4dda5c437f0 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 133:d4dda5c437f0 | 34 | * |
| mbed_official | 133:d4dda5c437f0 | 35 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 36 | */ |
| mbed_official | 133:d4dda5c437f0 | 37 | |
| mbed_official | 133:d4dda5c437f0 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 39 | #ifndef __STM32F4xx_HAL_I2S_H |
| mbed_official | 133:d4dda5c437f0 | 40 | #define __STM32F4xx_HAL_I2S_H |
| mbed_official | 133:d4dda5c437f0 | 41 | |
| mbed_official | 133:d4dda5c437f0 | 42 | #ifdef __cplusplus |
| mbed_official | 133:d4dda5c437f0 | 43 | extern "C" { |
| mbed_official | 133:d4dda5c437f0 | 44 | #endif |
| mbed_official | 133:d4dda5c437f0 | 45 | |
| mbed_official | 133:d4dda5c437f0 | 46 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 47 | #include "stm32f4xx_hal_def.h" |
| mbed_official | 133:d4dda5c437f0 | 48 | |
| mbed_official | 133:d4dda5c437f0 | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 133:d4dda5c437f0 | 50 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 51 | */ |
| mbed_official | 133:d4dda5c437f0 | 52 | |
| mbed_official | 133:d4dda5c437f0 | 53 | /** @addtogroup I2S |
| mbed_official | 133:d4dda5c437f0 | 54 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 55 | */ |
| mbed_official | 133:d4dda5c437f0 | 56 | |
| mbed_official | 133:d4dda5c437f0 | 57 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 58 | /** |
| mbed_official | 133:d4dda5c437f0 | 59 | * @brief I2S Init structure definition |
| mbed_official | 133:d4dda5c437f0 | 60 | */ |
| mbed_official | 133:d4dda5c437f0 | 61 | typedef struct |
| mbed_official | 133:d4dda5c437f0 | 62 | { |
| mbed_official | 133:d4dda5c437f0 | 63 | uint32_t Mode; /*!< Specifies the I2S operating mode. |
| mbed_official | 133:d4dda5c437f0 | 64 | This parameter can be a value of @ref I2S_Mode */ |
| mbed_official | 133:d4dda5c437f0 | 65 | |
| mbed_official | 133:d4dda5c437f0 | 66 | uint32_t Standard; /*!< Specifies the standard used for the I2S communication. |
| mbed_official | 133:d4dda5c437f0 | 67 | This parameter can be a value of @ref I2S_Standard */ |
| mbed_official | 133:d4dda5c437f0 | 68 | |
| mbed_official | 133:d4dda5c437f0 | 69 | uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. |
| mbed_official | 133:d4dda5c437f0 | 70 | This parameter can be a value of @ref I2S_Data_Format */ |
| mbed_official | 133:d4dda5c437f0 | 71 | |
| mbed_official | 133:d4dda5c437f0 | 72 | uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. |
| mbed_official | 133:d4dda5c437f0 | 73 | This parameter can be a value of @ref I2S_MCLK_Output */ |
| mbed_official | 133:d4dda5c437f0 | 74 | |
| mbed_official | 133:d4dda5c437f0 | 75 | uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. |
| mbed_official | 133:d4dda5c437f0 | 76 | This parameter can be a value of @ref I2S_Audio_Frequency */ |
| mbed_official | 133:d4dda5c437f0 | 77 | |
| mbed_official | 133:d4dda5c437f0 | 78 | uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. |
| mbed_official | 133:d4dda5c437f0 | 79 | This parameter can be a value of @ref I2S_Clock_Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 80 | |
| mbed_official | 133:d4dda5c437f0 | 81 | uint32_t ClockSource; /*!< Specifies the I2S Clock Source. |
| mbed_official | 133:d4dda5c437f0 | 82 | This parameter can be a value of @ref I2S_Clock_Source */ |
| mbed_official | 133:d4dda5c437f0 | 83 | |
| mbed_official | 133:d4dda5c437f0 | 84 | uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode. |
| mbed_official | 133:d4dda5c437f0 | 85 | This parameter can be a value of @ref I2S_FullDuplex_Mode */ |
| mbed_official | 133:d4dda5c437f0 | 86 | |
| mbed_official | 133:d4dda5c437f0 | 87 | }I2S_InitTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 88 | |
| mbed_official | 133:d4dda5c437f0 | 89 | /** |
| mbed_official | 133:d4dda5c437f0 | 90 | * @brief HAL State structures definition |
| mbed_official | 133:d4dda5c437f0 | 91 | */ |
| mbed_official | 133:d4dda5c437f0 | 92 | typedef enum |
| mbed_official | 133:d4dda5c437f0 | 93 | { |
| mbed_official | 133:d4dda5c437f0 | 94 | HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */ |
| mbed_official | 133:d4dda5c437f0 | 95 | HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */ |
| mbed_official | 133:d4dda5c437f0 | 96 | HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */ |
| mbed_official | 133:d4dda5c437f0 | 97 | HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ |
| mbed_official | 133:d4dda5c437f0 | 98 | HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ |
| mbed_official | 133:d4dda5c437f0 | 99 | HAL_I2S_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ |
| mbed_official | 133:d4dda5c437f0 | 100 | HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */ |
| mbed_official | 133:d4dda5c437f0 | 101 | HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */ |
| mbed_official | 133:d4dda5c437f0 | 102 | |
| mbed_official | 133:d4dda5c437f0 | 103 | }HAL_I2S_StateTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 104 | |
| mbed_official | 133:d4dda5c437f0 | 105 | /** |
| mbed_official | 133:d4dda5c437f0 | 106 | * @brief HAL I2S Error Code structure definition |
| mbed_official | 133:d4dda5c437f0 | 107 | */ |
| mbed_official | 133:d4dda5c437f0 | 108 | typedef enum |
| mbed_official | 133:d4dda5c437f0 | 109 | { |
| mbed_official | 133:d4dda5c437f0 | 110 | HAL_I2S_ERROR_NONE = 0x00, /*!< No error */ |
| mbed_official | 133:d4dda5c437f0 | 111 | HAL_I2S_ERROR_UDR = 0x01, /*!< I2S Underrun error */ |
| mbed_official | 133:d4dda5c437f0 | 112 | HAL_I2S_ERROR_OVR = 0x02, /*!< I2S Overrun error */ |
| mbed_official | 133:d4dda5c437f0 | 113 | HAL_I2SEX_ERROR_UDR = 0x04, /*!< I2S extended Underrun error */ |
| mbed_official | 133:d4dda5c437f0 | 114 | HAL_I2SEX_ERROR_OVR = 0x08, /*!< I2S extended Overrun error */ |
| mbed_official | 133:d4dda5c437f0 | 115 | HAL_I2S_ERROR_FRE = 0x10, /*!< I2S Frame format error */ |
| mbed_official | 133:d4dda5c437f0 | 116 | HAL_I2S_ERROR_DMA = 0x20 /*!< DMA transfer error */ |
| mbed_official | 133:d4dda5c437f0 | 117 | }HAL_I2S_ErrorTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 118 | |
| mbed_official | 133:d4dda5c437f0 | 119 | /** |
| mbed_official | 133:d4dda5c437f0 | 120 | * @brief I2S handle Structure definition |
| mbed_official | 133:d4dda5c437f0 | 121 | */ |
| mbed_official | 133:d4dda5c437f0 | 122 | typedef struct |
| mbed_official | 133:d4dda5c437f0 | 123 | { |
| mbed_official | 133:d4dda5c437f0 | 124 | SPI_TypeDef *Instance; /* I2S registers base address */ |
| mbed_official | 133:d4dda5c437f0 | 125 | |
| mbed_official | 133:d4dda5c437f0 | 126 | I2S_InitTypeDef Init; /* I2S communication parameters */ |
| mbed_official | 133:d4dda5c437f0 | 127 | |
| mbed_official | 133:d4dda5c437f0 | 128 | uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */ |
| mbed_official | 133:d4dda5c437f0 | 129 | |
| mbed_official | 133:d4dda5c437f0 | 130 | __IO uint16_t TxXferSize; /* I2S Tx transfer size */ |
| mbed_official | 133:d4dda5c437f0 | 131 | |
| mbed_official | 133:d4dda5c437f0 | 132 | __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */ |
| mbed_official | 133:d4dda5c437f0 | 133 | |
| mbed_official | 133:d4dda5c437f0 | 134 | uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */ |
| mbed_official | 133:d4dda5c437f0 | 135 | |
| mbed_official | 133:d4dda5c437f0 | 136 | __IO uint16_t RxXferSize; /* I2S Rx transfer size */ |
| mbed_official | 133:d4dda5c437f0 | 137 | |
| mbed_official | 133:d4dda5c437f0 | 138 | __IO uint16_t RxXferCount; /* I2S Rx transfer counter */ |
| mbed_official | 133:d4dda5c437f0 | 139 | |
| mbed_official | 133:d4dda5c437f0 | 140 | DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */ |
| mbed_official | 133:d4dda5c437f0 | 141 | |
| mbed_official | 133:d4dda5c437f0 | 142 | DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */ |
| mbed_official | 133:d4dda5c437f0 | 143 | |
| mbed_official | 133:d4dda5c437f0 | 144 | __IO HAL_LockTypeDef Lock; /* I2S locking object */ |
| mbed_official | 133:d4dda5c437f0 | 145 | |
| mbed_official | 133:d4dda5c437f0 | 146 | __IO HAL_I2S_StateTypeDef State; /* I2S communication state */ |
| mbed_official | 133:d4dda5c437f0 | 147 | |
| mbed_official | 133:d4dda5c437f0 | 148 | __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */ |
| mbed_official | 133:d4dda5c437f0 | 149 | |
| mbed_official | 133:d4dda5c437f0 | 150 | }I2S_HandleTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 151 | |
| mbed_official | 133:d4dda5c437f0 | 152 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 153 | |
| mbed_official | 133:d4dda5c437f0 | 154 | /** @defgroup I2S_Exported_Constants |
| mbed_official | 133:d4dda5c437f0 | 155 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 156 | */ |
| mbed_official | 133:d4dda5c437f0 | 157 | #define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE)) |
| mbed_official | 133:d4dda5c437f0 | 158 | |
| mbed_official | 133:d4dda5c437f0 | 159 | /** @defgroup I2S_Clock_Source |
| mbed_official | 133:d4dda5c437f0 | 160 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 161 | */ |
| mbed_official | 133:d4dda5c437f0 | 162 | #define I2S_CLOCK_PLL ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 163 | #define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001) |
| mbed_official | 133:d4dda5c437f0 | 164 | |
| mbed_official | 133:d4dda5c437f0 | 165 | #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \ |
| mbed_official | 133:d4dda5c437f0 | 166 | ((CLOCK) == I2S_CLOCK_PLL)) |
| mbed_official | 133:d4dda5c437f0 | 167 | /** |
| mbed_official | 133:d4dda5c437f0 | 168 | * @} |
| mbed_official | 133:d4dda5c437f0 | 169 | */ |
| mbed_official | 133:d4dda5c437f0 | 170 | |
| mbed_official | 133:d4dda5c437f0 | 171 | /** @defgroup I2S_Mode |
| mbed_official | 133:d4dda5c437f0 | 172 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 173 | */ |
| mbed_official | 133:d4dda5c437f0 | 174 | #define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 175 | #define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100) |
| mbed_official | 133:d4dda5c437f0 | 176 | #define I2S_MODE_MASTER_TX ((uint32_t)0x00000200) |
| mbed_official | 133:d4dda5c437f0 | 177 | #define I2S_MODE_MASTER_RX ((uint32_t)0x00000300) |
| mbed_official | 133:d4dda5c437f0 | 178 | |
| mbed_official | 133:d4dda5c437f0 | 179 | #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \ |
| mbed_official | 133:d4dda5c437f0 | 180 | ((MODE) == I2S_MODE_SLAVE_RX) || \ |
| mbed_official | 133:d4dda5c437f0 | 181 | ((MODE) == I2S_MODE_MASTER_TX) || \ |
| mbed_official | 133:d4dda5c437f0 | 182 | ((MODE) == I2S_MODE_MASTER_RX)) |
| mbed_official | 133:d4dda5c437f0 | 183 | /** |
| mbed_official | 133:d4dda5c437f0 | 184 | * @} |
| mbed_official | 133:d4dda5c437f0 | 185 | */ |
| mbed_official | 133:d4dda5c437f0 | 186 | |
| mbed_official | 133:d4dda5c437f0 | 187 | /** @defgroup I2S_Standard |
| mbed_official | 133:d4dda5c437f0 | 188 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 189 | */ |
| mbed_official | 242:7074e42da0b2 | 190 | #define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 191 | #define I2S_STANDARD_MSB ((uint32_t)0x00000010) |
| mbed_official | 133:d4dda5c437f0 | 192 | #define I2S_STANDARD_LSB ((uint32_t)0x00000020) |
| mbed_official | 133:d4dda5c437f0 | 193 | #define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030) |
| mbed_official | 133:d4dda5c437f0 | 194 | #define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0) |
| mbed_official | 133:d4dda5c437f0 | 195 | |
| mbed_official | 242:7074e42da0b2 | 196 | #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \ |
| mbed_official | 133:d4dda5c437f0 | 197 | ((STANDARD) == I2S_STANDARD_MSB) || \ |
| mbed_official | 133:d4dda5c437f0 | 198 | ((STANDARD) == I2S_STANDARD_LSB) || \ |
| mbed_official | 133:d4dda5c437f0 | 199 | ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \ |
| mbed_official | 133:d4dda5c437f0 | 200 | ((STANDARD) == I2S_STANDARD_PCM_LONG)) |
| mbed_official | 242:7074e42da0b2 | 201 | /** @defgroup I2S_Legacy |
| mbed_official | 242:7074e42da0b2 | 202 | * @{ |
| mbed_official | 242:7074e42da0b2 | 203 | */ |
| mbed_official | 242:7074e42da0b2 | 204 | #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS |
| mbed_official | 242:7074e42da0b2 | 205 | /** |
| mbed_official | 242:7074e42da0b2 | 206 | * @} |
| mbed_official | 242:7074e42da0b2 | 207 | */ |
| mbed_official | 242:7074e42da0b2 | 208 | |
| mbed_official | 133:d4dda5c437f0 | 209 | /** |
| mbed_official | 133:d4dda5c437f0 | 210 | * @} |
| mbed_official | 133:d4dda5c437f0 | 211 | */ |
| mbed_official | 133:d4dda5c437f0 | 212 | |
| mbed_official | 133:d4dda5c437f0 | 213 | /** @defgroup I2S_Data_Format |
| mbed_official | 133:d4dda5c437f0 | 214 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 215 | */ |
| mbed_official | 133:d4dda5c437f0 | 216 | #define I2S_DATAFORMAT_16B ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 217 | #define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001) |
| mbed_official | 133:d4dda5c437f0 | 218 | #define I2S_DATAFORMAT_24B ((uint32_t)0x00000003) |
| mbed_official | 133:d4dda5c437f0 | 219 | #define I2S_DATAFORMAT_32B ((uint32_t)0x00000005) |
| mbed_official | 133:d4dda5c437f0 | 220 | |
| mbed_official | 133:d4dda5c437f0 | 221 | #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \ |
| mbed_official | 133:d4dda5c437f0 | 222 | ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \ |
| mbed_official | 133:d4dda5c437f0 | 223 | ((FORMAT) == I2S_DATAFORMAT_24B) || \ |
| mbed_official | 133:d4dda5c437f0 | 224 | ((FORMAT) == I2S_DATAFORMAT_32B)) |
| mbed_official | 133:d4dda5c437f0 | 225 | /** |
| mbed_official | 133:d4dda5c437f0 | 226 | * @} |
| mbed_official | 133:d4dda5c437f0 | 227 | */ |
| mbed_official | 133:d4dda5c437f0 | 228 | |
| mbed_official | 133:d4dda5c437f0 | 229 | /** @defgroup I2S_MCLK_Output |
| mbed_official | 133:d4dda5c437f0 | 230 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 231 | */ |
| mbed_official | 133:d4dda5c437f0 | 232 | #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE) |
| mbed_official | 133:d4dda5c437f0 | 233 | #define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 234 | |
| mbed_official | 133:d4dda5c437f0 | 235 | #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \ |
| mbed_official | 133:d4dda5c437f0 | 236 | ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE)) |
| mbed_official | 133:d4dda5c437f0 | 237 | /** |
| mbed_official | 133:d4dda5c437f0 | 238 | * @} |
| mbed_official | 133:d4dda5c437f0 | 239 | */ |
| mbed_official | 133:d4dda5c437f0 | 240 | |
| mbed_official | 133:d4dda5c437f0 | 241 | /** @defgroup I2S_Audio_Frequency |
| mbed_official | 133:d4dda5c437f0 | 242 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 243 | */ |
| mbed_official | 133:d4dda5c437f0 | 244 | #define I2S_AUDIOFREQ_192K ((uint32_t)192000) |
| mbed_official | 133:d4dda5c437f0 | 245 | #define I2S_AUDIOFREQ_96K ((uint32_t)96000) |
| mbed_official | 133:d4dda5c437f0 | 246 | #define I2S_AUDIOFREQ_48K ((uint32_t)48000) |
| mbed_official | 133:d4dda5c437f0 | 247 | #define I2S_AUDIOFREQ_44K ((uint32_t)44100) |
| mbed_official | 133:d4dda5c437f0 | 248 | #define I2S_AUDIOFREQ_32K ((uint32_t)32000) |
| mbed_official | 133:d4dda5c437f0 | 249 | #define I2S_AUDIOFREQ_22K ((uint32_t)22050) |
| mbed_official | 133:d4dda5c437f0 | 250 | #define I2S_AUDIOFREQ_16K ((uint32_t)16000) |
| mbed_official | 133:d4dda5c437f0 | 251 | #define I2S_AUDIOFREQ_11K ((uint32_t)11025) |
| mbed_official | 133:d4dda5c437f0 | 252 | #define I2S_AUDIOFREQ_8K ((uint32_t)8000) |
| mbed_official | 133:d4dda5c437f0 | 253 | #define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2) |
| mbed_official | 133:d4dda5c437f0 | 254 | |
| mbed_official | 133:d4dda5c437f0 | 255 | #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \ |
| mbed_official | 133:d4dda5c437f0 | 256 | ((FREQ) <= I2S_AUDIOFREQ_192K)) || \ |
| mbed_official | 133:d4dda5c437f0 | 257 | ((FREQ) == I2S_AUDIOFREQ_DEFAULT)) |
| mbed_official | 133:d4dda5c437f0 | 258 | /** |
| mbed_official | 133:d4dda5c437f0 | 259 | * @} |
| mbed_official | 133:d4dda5c437f0 | 260 | */ |
| mbed_official | 133:d4dda5c437f0 | 261 | |
| mbed_official | 133:d4dda5c437f0 | 262 | /** @defgroup I2S_FullDuplex_Mode |
| mbed_official | 133:d4dda5c437f0 | 263 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 264 | */ |
| mbed_official | 133:d4dda5c437f0 | 265 | #define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 266 | #define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001) |
| mbed_official | 133:d4dda5c437f0 | 267 | |
| mbed_official | 133:d4dda5c437f0 | 268 | #define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \ |
| mbed_official | 133:d4dda5c437f0 | 269 | ((MODE) == I2S_FULLDUPLEXMODE_ENABLE)) |
| mbed_official | 133:d4dda5c437f0 | 270 | /** |
| mbed_official | 133:d4dda5c437f0 | 271 | * @} |
| mbed_official | 133:d4dda5c437f0 | 272 | */ |
| mbed_official | 133:d4dda5c437f0 | 273 | |
| mbed_official | 133:d4dda5c437f0 | 274 | /** @defgroup I2S_Clock_Polarity |
| mbed_official | 133:d4dda5c437f0 | 275 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 276 | */ |
| mbed_official | 133:d4dda5c437f0 | 277 | #define I2S_CPOL_LOW ((uint32_t)0x00000000) |
| mbed_official | 133:d4dda5c437f0 | 278 | #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL) |
| mbed_official | 133:d4dda5c437f0 | 279 | |
| mbed_official | 133:d4dda5c437f0 | 280 | #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \ |
| mbed_official | 133:d4dda5c437f0 | 281 | ((CPOL) == I2S_CPOL_HIGH)) |
| mbed_official | 133:d4dda5c437f0 | 282 | /** |
| mbed_official | 133:d4dda5c437f0 | 283 | * @} |
| mbed_official | 133:d4dda5c437f0 | 284 | */ |
| mbed_official | 133:d4dda5c437f0 | 285 | |
| mbed_official | 133:d4dda5c437f0 | 286 | /** @defgroup I2S_Interrupt_configuration_definition |
| mbed_official | 133:d4dda5c437f0 | 287 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 288 | */ |
| mbed_official | 133:d4dda5c437f0 | 289 | #define I2S_IT_TXE SPI_CR2_TXEIE |
| mbed_official | 133:d4dda5c437f0 | 290 | #define I2S_IT_RXNE SPI_CR2_RXNEIE |
| mbed_official | 133:d4dda5c437f0 | 291 | #define I2S_IT_ERR SPI_CR2_ERRIE |
| mbed_official | 133:d4dda5c437f0 | 292 | /** |
| mbed_official | 133:d4dda5c437f0 | 293 | * @} |
| mbed_official | 133:d4dda5c437f0 | 294 | */ |
| mbed_official | 133:d4dda5c437f0 | 295 | |
| mbed_official | 133:d4dda5c437f0 | 296 | /** @defgroup I2S_Flag_definition |
| mbed_official | 133:d4dda5c437f0 | 297 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 298 | */ |
| mbed_official | 133:d4dda5c437f0 | 299 | #define I2S_FLAG_TXE SPI_SR_TXE |
| mbed_official | 133:d4dda5c437f0 | 300 | #define I2S_FLAG_RXNE SPI_SR_RXNE |
| mbed_official | 133:d4dda5c437f0 | 301 | |
| mbed_official | 133:d4dda5c437f0 | 302 | #define I2S_FLAG_UDR SPI_SR_UDR |
| mbed_official | 133:d4dda5c437f0 | 303 | #define I2S_FLAG_OVR SPI_SR_OVR |
| mbed_official | 133:d4dda5c437f0 | 304 | #define I2S_FLAG_FRE SPI_SR_FRE |
| mbed_official | 133:d4dda5c437f0 | 305 | |
| mbed_official | 133:d4dda5c437f0 | 306 | #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE |
| mbed_official | 133:d4dda5c437f0 | 307 | #define I2S_FLAG_BSY SPI_SR_BSY |
| mbed_official | 133:d4dda5c437f0 | 308 | /** |
| mbed_official | 133:d4dda5c437f0 | 309 | * @} |
| mbed_official | 133:d4dda5c437f0 | 310 | */ |
| mbed_official | 133:d4dda5c437f0 | 311 | |
| mbed_official | 133:d4dda5c437f0 | 312 | /** |
| mbed_official | 133:d4dda5c437f0 | 313 | * @} |
| mbed_official | 133:d4dda5c437f0 | 314 | */ |
| mbed_official | 133:d4dda5c437f0 | 315 | |
| mbed_official | 133:d4dda5c437f0 | 316 | /* Exported macro ------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 317 | |
| mbed_official | 242:7074e42da0b2 | 318 | |
| mbed_official | 242:7074e42da0b2 | 319 | /** @brief Reset I2S handle state |
| mbed_official | 242:7074e42da0b2 | 320 | * @param __HANDLE__: specifies the I2S Handle. |
| mbed_official | 242:7074e42da0b2 | 321 | * @retval None |
| mbed_official | 242:7074e42da0b2 | 322 | */ |
| mbed_official | 242:7074e42da0b2 | 323 | #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) |
| mbed_official | 242:7074e42da0b2 | 324 | |
| mbed_official | 133:d4dda5c437f0 | 325 | /** @brief Enable or disable the specified SPI peripheral (in I2S mode). |
| mbed_official | 133:d4dda5c437f0 | 326 | * @param __HANDLE__: specifies the I2S Handle. |
| mbed_official | 133:d4dda5c437f0 | 327 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 328 | */ |
| mbed_official | 133:d4dda5c437f0 | 329 | #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE) |
| mbed_official | 133:d4dda5c437f0 | 330 | #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE) |
| mbed_official | 133:d4dda5c437f0 | 331 | |
| mbed_official | 133:d4dda5c437f0 | 332 | /** @brief Enable or disable the specified I2S interrupts. |
| mbed_official | 133:d4dda5c437f0 | 333 | * @param __HANDLE__: specifies the I2S Handle. |
| mbed_official | 133:d4dda5c437f0 | 334 | * @param __INTERRUPT__: specifies the interrupt source to enable or disable. |
| mbed_official | 133:d4dda5c437f0 | 335 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 336 | * @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
| mbed_official | 133:d4dda5c437f0 | 337 | * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
| mbed_official | 133:d4dda5c437f0 | 338 | * @arg I2S_IT_ERR: Error interrupt enable |
| mbed_official | 133:d4dda5c437f0 | 339 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 340 | */ |
| mbed_official | 133:d4dda5c437f0 | 341 | #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) |
| mbed_official | 133:d4dda5c437f0 | 342 | #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__)) |
| mbed_official | 133:d4dda5c437f0 | 343 | |
| mbed_official | 133:d4dda5c437f0 | 344 | /** @brief Checks if the specified I2S interrupt source is enabled or disabled. |
| mbed_official | 133:d4dda5c437f0 | 345 | * @param __HANDLE__: specifies the I2S Handle. |
| mbed_official | 133:d4dda5c437f0 | 346 | * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. |
| mbed_official | 133:d4dda5c437f0 | 347 | * @param __INTERRUPT__: specifies the I2S interrupt source to check. |
| mbed_official | 133:d4dda5c437f0 | 348 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 349 | * @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
| mbed_official | 133:d4dda5c437f0 | 350 | * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
| mbed_official | 133:d4dda5c437f0 | 351 | * @arg I2S_IT_ERR: Error interrupt enable |
| mbed_official | 133:d4dda5c437f0 | 352 | * @retval The new state of __IT__ (TRUE or FALSE). |
| mbed_official | 133:d4dda5c437f0 | 353 | */ |
| mbed_official | 133:d4dda5c437f0 | 354 | #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| mbed_official | 133:d4dda5c437f0 | 355 | |
| mbed_official | 133:d4dda5c437f0 | 356 | /** @brief Checks whether the specified I2S flag is set or not. |
| mbed_official | 133:d4dda5c437f0 | 357 | * @param __HANDLE__: specifies the I2S Handle. |
| mbed_official | 133:d4dda5c437f0 | 358 | * @param __FLAG__: specifies the flag to check. |
| mbed_official | 133:d4dda5c437f0 | 359 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 360 | * @arg I2S_FLAG_RXNE: Receive buffer not empty flag |
| mbed_official | 133:d4dda5c437f0 | 361 | * @arg I2S_FLAG_TXE: Transmit buffer empty flag |
| mbed_official | 133:d4dda5c437f0 | 362 | * @arg I2S_FLAG_UDR: Underrun flag |
| mbed_official | 133:d4dda5c437f0 | 363 | * @arg I2S_FLAG_OVR: Overrun flag |
| mbed_official | 133:d4dda5c437f0 | 364 | * @arg I2S_FLAG_FRE: Frame error flag |
| mbed_official | 133:d4dda5c437f0 | 365 | * @arg I2S_FLAG_CHSIDE: Channel Side flag |
| mbed_official | 133:d4dda5c437f0 | 366 | * @arg I2S_FLAG_BSY: Busy flag |
| mbed_official | 133:d4dda5c437f0 | 367 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| mbed_official | 133:d4dda5c437f0 | 368 | */ |
| mbed_official | 133:d4dda5c437f0 | 369 | #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| mbed_official | 133:d4dda5c437f0 | 370 | |
| mbed_official | 133:d4dda5c437f0 | 371 | /** @brief Clears the I2S OVR pending flag. |
| mbed_official | 133:d4dda5c437f0 | 372 | * @param __HANDLE__: specifies the I2S Handle. |
| mbed_official | 133:d4dda5c437f0 | 373 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 374 | */ |
| mbed_official | 133:d4dda5c437f0 | 375 | #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\ |
| mbed_official | 133:d4dda5c437f0 | 376 | (__HANDLE__)->Instance->SR;}while(0) |
| mbed_official | 133:d4dda5c437f0 | 377 | /** @brief Clears the I2S UDR pending flag. |
| mbed_official | 133:d4dda5c437f0 | 378 | * @param __HANDLE__: specifies the I2S Handle. |
| mbed_official | 133:d4dda5c437f0 | 379 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 380 | */ |
| mbed_official | 133:d4dda5c437f0 | 381 | #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR) |
| mbed_official | 133:d4dda5c437f0 | 382 | |
| mbed_official | 133:d4dda5c437f0 | 383 | /* Include I2S Extension module */ |
| mbed_official | 133:d4dda5c437f0 | 384 | #include "stm32f4xx_hal_i2s_ex.h" |
| mbed_official | 133:d4dda5c437f0 | 385 | |
| mbed_official | 133:d4dda5c437f0 | 386 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 387 | |
| mbed_official | 133:d4dda5c437f0 | 388 | /* Initialization/de-initialization functions **********************************/ |
| mbed_official | 133:d4dda5c437f0 | 389 | HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 390 | HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 391 | void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 392 | void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 393 | |
| mbed_official | 133:d4dda5c437f0 | 394 | /* I/O operation functions *****************************************************/ |
| mbed_official | 133:d4dda5c437f0 | 395 | /* Blocking mode: Polling */ |
| mbed_official | 133:d4dda5c437f0 | 396 | HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); |
| mbed_official | 133:d4dda5c437f0 | 397 | HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); |
| mbed_official | 133:d4dda5c437f0 | 398 | |
| mbed_official | 133:d4dda5c437f0 | 399 | /* Non-Blocking mode: Interrupt */ |
| mbed_official | 133:d4dda5c437f0 | 400 | HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
| mbed_official | 133:d4dda5c437f0 | 401 | HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
| mbed_official | 133:d4dda5c437f0 | 402 | void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 403 | |
| mbed_official | 133:d4dda5c437f0 | 404 | /* Non-Blocking mode: DMA */ |
| mbed_official | 133:d4dda5c437f0 | 405 | HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
| mbed_official | 133:d4dda5c437f0 | 406 | HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
| mbed_official | 133:d4dda5c437f0 | 407 | |
| mbed_official | 133:d4dda5c437f0 | 408 | HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 409 | HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 410 | HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 411 | |
| mbed_official | 133:d4dda5c437f0 | 412 | /* Peripheral Control and State functions **************************************/ |
| mbed_official | 133:d4dda5c437f0 | 413 | HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 414 | HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 415 | |
| mbed_official | 133:d4dda5c437f0 | 416 | /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ |
| mbed_official | 133:d4dda5c437f0 | 417 | void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 418 | void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 419 | void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 420 | void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 421 | void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); |
| mbed_official | 133:d4dda5c437f0 | 422 | |
| mbed_official | 133:d4dda5c437f0 | 423 | void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 133:d4dda5c437f0 | 424 | void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 133:d4dda5c437f0 | 425 | void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 133:d4dda5c437f0 | 426 | void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 133:d4dda5c437f0 | 427 | void I2S_DMAError(DMA_HandleTypeDef *hdma); |
| mbed_official | 133:d4dda5c437f0 | 428 | HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout); |
| mbed_official | 133:d4dda5c437f0 | 429 | |
| mbed_official | 133:d4dda5c437f0 | 430 | /** |
| mbed_official | 133:d4dda5c437f0 | 431 | * @} |
| mbed_official | 133:d4dda5c437f0 | 432 | */ |
| mbed_official | 133:d4dda5c437f0 | 433 | |
| mbed_official | 133:d4dda5c437f0 | 434 | /** |
| mbed_official | 133:d4dda5c437f0 | 435 | * @} |
| mbed_official | 133:d4dda5c437f0 | 436 | */ |
| mbed_official | 133:d4dda5c437f0 | 437 | |
| mbed_official | 133:d4dda5c437f0 | 438 | #ifdef __cplusplus |
| mbed_official | 133:d4dda5c437f0 | 439 | } |
| mbed_official | 133:d4dda5c437f0 | 440 | #endif |
| mbed_official | 133:d4dda5c437f0 | 441 | |
| mbed_official | 133:d4dda5c437f0 | 442 | |
| mbed_official | 133:d4dda5c437f0 | 443 | #endif /* __STM32F4xx_HAL_I2S_H */ |
| mbed_official | 133:d4dda5c437f0 | 444 | |
| mbed_official | 133:d4dda5c437f0 | 445 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |