mbed-src - mbed w/ spi bug fig

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mbed w/ spi bug fig

targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc.c@242:7074e42da0b2, 2014-06-27 (annotated)

Committer:: mbed_official
Date:: Fri Jun 27 07:30:09 2014 +0100
Revision:: 242:7074e42da0b2
Parent:: 133:d4dda5c437f0

Synchronized with git revision 124ef5e3add9e74a3221347a3fbeea7c8b3cf353



Full URL: https://github.com/mbedmicro/mbed/commit/124ef5e3add9e74a3221347a3fbeea7c8b3cf353/



[DISCO_F407VG] HAL update.

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	133:d4dda5c437f0	1	/**
mbed_official	133:d4dda5c437f0	2	******************************************************************************
mbed_official	133:d4dda5c437f0	3	* @file stm32f4xx_hal_rcc.c
mbed_official	133:d4dda5c437f0	4	* @author MCD Application Team
mbed_official	242:7074e42da0b2	5	* @version V1.1.0RC2
mbed_official	242:7074e42da0b2	6	* @date 14-May-2014
mbed_official	133:d4dda5c437f0	7	* @brief RCC HAL module driver.
mbed_official	133:d4dda5c437f0	8	* This file provides firmware functions to manage the following
mbed_official	133:d4dda5c437f0	9	* functionalities of the Reset and Clock Control (RCC) peripheral:
mbed_official	133:d4dda5c437f0	10	* + Initialization and de-initialization functions
mbed_official	133:d4dda5c437f0	11	* + Peripheral Control functions
mbed_official	133:d4dda5c437f0	12	*
mbed_official	133:d4dda5c437f0	13	@verbatim
mbed_official	133:d4dda5c437f0	14	==============================================================================
mbed_official	133:d4dda5c437f0	15	##### RCC specific features #####
mbed_official	133:d4dda5c437f0	16	==============================================================================
mbed_official	133:d4dda5c437f0	17	[..]
mbed_official	133:d4dda5c437f0	18	After reset the device is running from Internal High Speed oscillator
mbed_official	133:d4dda5c437f0	19	(HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
mbed_official	133:d4dda5c437f0	20	and I-Cache are disabled, and all peripherals are off except internal
mbed_official	133:d4dda5c437f0	21	SRAM, Flash and JTAG.
mbed_official	133:d4dda5c437f0	22	(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
mbed_official	133:d4dda5c437f0	23	all peripherals mapped on these busses are running at HSI speed.
mbed_official	133:d4dda5c437f0	24	(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
mbed_official	133:d4dda5c437f0	25	(+) All GPIOs are in input floating state, except the JTAG pins which
mbed_official	133:d4dda5c437f0	26	are assigned to be used for debug purpose.
mbed_official	133:d4dda5c437f0	27
mbed_official	133:d4dda5c437f0	28	[..]
mbed_official	133:d4dda5c437f0	29	Once the device started from reset, the user application has to:
mbed_official	133:d4dda5c437f0	30	(+) Configure the clock source to be used to drive the System clock
mbed_official	133:d4dda5c437f0	31	(if the application needs higher frequency/performance)
mbed_official	133:d4dda5c437f0	32	(+) Configure the System clock frequency and Flash settings
mbed_official	133:d4dda5c437f0	33	(+) Configure the AHB and APB busses prescalers
mbed_official	133:d4dda5c437f0	34	(+) Enable the clock for the peripheral(s) to be used
mbed_official	133:d4dda5c437f0	35	(+) Configure the clock source(s) for peripherals which clocks are not
mbed_official	133:d4dda5c437f0	36	derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
mbed_official	133:d4dda5c437f0	37
mbed_official	133:d4dda5c437f0	38	@endverbatim
mbed_official	133:d4dda5c437f0	39	******************************************************************************
mbed_official	133:d4dda5c437f0	40	* @attention
mbed_official	133:d4dda5c437f0	41	*
mbed_official	133:d4dda5c437f0	42	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	133:d4dda5c437f0	43	*
mbed_official	133:d4dda5c437f0	44	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	133:d4dda5c437f0	45	* are permitted provided that the following conditions are met:
mbed_official	133:d4dda5c437f0	46	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	133:d4dda5c437f0	47	* this list of conditions and the following disclaimer.
mbed_official	133:d4dda5c437f0	48	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	133:d4dda5c437f0	49	* this list of conditions and the following disclaimer in the documentation
mbed_official	133:d4dda5c437f0	50	* and/or other materials provided with the distribution.
mbed_official	133:d4dda5c437f0	51	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	133:d4dda5c437f0	52	* may be used to endorse or promote products derived from this software
mbed_official	133:d4dda5c437f0	53	* without specific prior written permission.
mbed_official	133:d4dda5c437f0	54	*
mbed_official	133:d4dda5c437f0	55	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	133:d4dda5c437f0	56	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	133:d4dda5c437f0	57	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	133:d4dda5c437f0	58	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	133:d4dda5c437f0	59	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	133:d4dda5c437f0	60	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	133:d4dda5c437f0	61	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	133:d4dda5c437f0	62	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	133:d4dda5c437f0	63	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	133:d4dda5c437f0	64	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	133:d4dda5c437f0	65	*
mbed_official	133:d4dda5c437f0	66	******************************************************************************
mbed_official	133:d4dda5c437f0	67	*/
mbed_official	133:d4dda5c437f0	68
mbed_official	133:d4dda5c437f0	69	/* Includes ------------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	70	#include "stm32f4xx_hal.h"
mbed_official	133:d4dda5c437f0	71
mbed_official	133:d4dda5c437f0	72	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	133:d4dda5c437f0	73	* @{
mbed_official	133:d4dda5c437f0	74	*/
mbed_official	133:d4dda5c437f0	75
mbed_official	133:d4dda5c437f0	76	/** @defgroup RCC
mbed_official	133:d4dda5c437f0	77	* @brief RCC HAL module driver
mbed_official	133:d4dda5c437f0	78	* @{
mbed_official	133:d4dda5c437f0	79	*/
mbed_official	133:d4dda5c437f0	80
mbed_official	133:d4dda5c437f0	81	#ifdef HAL_RCC_MODULE_ENABLED
mbed_official	133:d4dda5c437f0	82
mbed_official	133:d4dda5c437f0	83	/* Private typedef -----------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	84	/* Private define ------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	85	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
mbed_official	133:d4dda5c437f0	86	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	133:d4dda5c437f0	87	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	133:d4dda5c437f0	88	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	133:d4dda5c437f0	89	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
mbed_official	133:d4dda5c437f0	90
mbed_official	133:d4dda5c437f0	91	/* Private macro -------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	92	#define __MCO1_CLK_ENABLE() __GPIOA_CLK_ENABLE()
mbed_official	133:d4dda5c437f0	93	#define MCO1_GPIO_PORT GPIOA
mbed_official	133:d4dda5c437f0	94	#define MCO1_PIN GPIO_PIN_8
mbed_official	133:d4dda5c437f0	95
mbed_official	133:d4dda5c437f0	96	#define __MCO2_CLK_ENABLE() __GPIOC_CLK_ENABLE()
mbed_official	133:d4dda5c437f0	97	#define MCO2_GPIO_PORT GPIOC
mbed_official	133:d4dda5c437f0	98	#define MCO2_PIN GPIO_PIN_9
mbed_official	133:d4dda5c437f0	99
mbed_official	133:d4dda5c437f0	100	/* Private variables ---------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	101	const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official	133:d4dda5c437f0	102
mbed_official	133:d4dda5c437f0	103	/* Private function prototypes -----------------------------------------------*/
mbed_official	133:d4dda5c437f0	104	/* Private functions ---------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	105
mbed_official	133:d4dda5c437f0	106	/** @defgroup RCC_Private_Functions
mbed_official	133:d4dda5c437f0	107	* @{
mbed_official	133:d4dda5c437f0	108	*/
mbed_official	133:d4dda5c437f0	109
mbed_official	133:d4dda5c437f0	110	/** @defgroup RCC_Group1 Initialization and de-initialization functions
mbed_official	133:d4dda5c437f0	111	* @brief Initialization and Configuration functions
mbed_official	133:d4dda5c437f0	112	*
mbed_official	133:d4dda5c437f0	113	@verbatim
mbed_official	133:d4dda5c437f0	114	===============================================================================
mbed_official	133:d4dda5c437f0	115	##### Initialization and de-initialization functions #####
mbed_official	133:d4dda5c437f0	116	===============================================================================
mbed_official	133:d4dda5c437f0	117	[..]
mbed_official	242:7074e42da0b2	118	This section provides functions allowing to configure the internal/external oscillators
mbed_official	133:d4dda5c437f0	119	(HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
mbed_official	133:d4dda5c437f0	120	and APB2).
mbed_official	133:d4dda5c437f0	121
mbed_official	133:d4dda5c437f0	122	[..] Internal/external clock and PLL configuration
mbed_official	133:d4dda5c437f0	123	(#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
mbed_official	133:d4dda5c437f0	124	the PLL as System clock source.
mbed_official	133:d4dda5c437f0	125
mbed_official	133:d4dda5c437f0	126	(#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
mbed_official	133:d4dda5c437f0	127	clock source.
mbed_official	133:d4dda5c437f0	128
mbed_official	133:d4dda5c437f0	129	(#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
mbed_official	133:d4dda5c437f0	130	through the PLL as System clock source. Can be used also as RTC clock source.
mbed_official	133:d4dda5c437f0	131
mbed_official	133:d4dda5c437f0	132	(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
mbed_official	133:d4dda5c437f0	133
mbed_official	133:d4dda5c437f0	134	(#) PLL (clocked by HSI or HSE), featuring two different output clocks:
mbed_official	133:d4dda5c437f0	135	(++) The first output is used to generate the high speed system clock (up to 168 MHz)
mbed_official	133:d4dda5c437f0	136	(++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
mbed_official	133:d4dda5c437f0	137	the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
mbed_official	133:d4dda5c437f0	138
mbed_official	133:d4dda5c437f0	139	(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
mbed_official	133:d4dda5c437f0	140	and if a HSE clock failure occurs(HSE used directly or through PLL as System
mbed_official	133:d4dda5c437f0	141	clock source), the System clockis automatically switched to HSI and an interrupt
mbed_official	133:d4dda5c437f0	142	is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
mbed_official	133:d4dda5c437f0	143	(Non-Maskable Interrupt) exception vector.
mbed_official	133:d4dda5c437f0	144
mbed_official	133:d4dda5c437f0	145	(#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
mbed_official	133:d4dda5c437f0	146	clock (through a configurable prescaler) on PA8 pin.
mbed_official	133:d4dda5c437f0	147
mbed_official	133:d4dda5c437f0	148	(#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
mbed_official	133:d4dda5c437f0	149	clock (through a configurable prescaler) on PC9 pin.
mbed_official	133:d4dda5c437f0	150
mbed_official	133:d4dda5c437f0	151	[..] System, AHB and APB busses clocks configuration
mbed_official	133:d4dda5c437f0	152	(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
mbed_official	133:d4dda5c437f0	153	HSE and PLL.
mbed_official	133:d4dda5c437f0	154	The AHB clock (HCLK) is derived from System clock through configurable
mbed_official	133:d4dda5c437f0	155	prescaler and used to clock the CPU, memory and peripherals mapped
mbed_official	133:d4dda5c437f0	156	on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
mbed_official	133:d4dda5c437f0	157	from AHB clock through configurable prescalers and used to clock
mbed_official	133:d4dda5c437f0	158	the peripherals mapped on these busses. You can use
mbed_official	133:d4dda5c437f0	159	"HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
mbed_official	133:d4dda5c437f0	160
mbed_official	133:d4dda5c437f0	161	-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
mbed_official	133:d4dda5c437f0	162	(+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
mbed_official	133:d4dda5c437f0	163	from an external clock mapped on the I2S_CKIN pin.
mbed_official	133:d4dda5c437f0	164	You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
mbed_official	133:d4dda5c437f0	165	(+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
mbed_official	133:d4dda5c437f0	166	from an external clock mapped on the I2S_CKIN pin.
mbed_official	133:d4dda5c437f0	167	You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
mbed_official	133:d4dda5c437f0	168	(+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
mbed_official	133:d4dda5c437f0	169	divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
mbed_official	133:d4dda5c437f0	170	macros to configure this clock.
mbed_official	133:d4dda5c437f0	171	(+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
mbed_official	133:d4dda5c437f0	172	to work correctly, while the SDIO require a frequency equal or lower than
mbed_official	133:d4dda5c437f0	173	to 48. This clock is derived of the main PLL through PLLQ divider.
mbed_official	133:d4dda5c437f0	174	(+@) IWDG clock which is always the LSI clock.
mbed_official	133:d4dda5c437f0	175
mbed_official	133:d4dda5c437f0	176	(#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
mbed_official	133:d4dda5c437f0	177	frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
mbed_official	133:d4dda5c437f0	178	Depending on the device voltage range, the maximum frequency should
mbed_official	242:7074e42da0b2	179	be adapted accordingly (refer to the product datasheets for more details).
mbed_official	242:7074e42da0b2	180
mbed_official	133:d4dda5c437f0	181	(#) For the STM32F42xxx and STM32F43xxx devices, the maximum frequency
mbed_official	133:d4dda5c437f0	182	of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
mbed_official	133:d4dda5c437f0	183	Depending on the device voltage range, the maximum frequency should
mbed_official	242:7074e42da0b2	184	be adapted accordingly (refer to the product datasheets for more details).
mbed_official	242:7074e42da0b2	185
mbed_official	133:d4dda5c437f0	186	(#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
mbed_official	133:d4dda5c437f0	187	PCLK2 84 MHz and PCLK1 42 MHz.
mbed_official	133:d4dda5c437f0	188	Depending on the device voltage range, the maximum frequency should
mbed_official	242:7074e42da0b2	189	be adapted accordingly (refer to the product datasheets for more details).
mbed_official	133:d4dda5c437f0	190	@endverbatim
mbed_official	133:d4dda5c437f0	191	* @{
mbed_official	133:d4dda5c437f0	192	*/
mbed_official	133:d4dda5c437f0	193
mbed_official	133:d4dda5c437f0	194	/**
mbed_official	133:d4dda5c437f0	195	* @brief Resets the RCC clock configuration to the default reset state.
mbed_official	133:d4dda5c437f0	196	* @note The default reset state of the clock configuration is given below:
mbed_official	133:d4dda5c437f0	197	* - HSI ON and used as system clock source
mbed_official	133:d4dda5c437f0	198	* - HSE, PLL and PLLI2S OFF
mbed_official	133:d4dda5c437f0	199	* - AHB, APB1 and APB2 prescaler set to 1.
mbed_official	133:d4dda5c437f0	200	* - CSS, MCO1 and MCO2 OFF
mbed_official	133:d4dda5c437f0	201	* - All interrupts disabled
mbed_official	133:d4dda5c437f0	202	* @note This function doesn't modify the configuration of the
mbed_official	133:d4dda5c437f0	203	* - Peripheral clocks
mbed_official	133:d4dda5c437f0	204	* - LSI, LSE and RTC clocks
mbed_official	133:d4dda5c437f0	205	* @param None
mbed_official	133:d4dda5c437f0	206	* @retval None
mbed_official	133:d4dda5c437f0	207	*/
mbed_official	133:d4dda5c437f0	208	void HAL_RCC_DeInit(void)
mbed_official	133:d4dda5c437f0	209	{
mbed_official	133:d4dda5c437f0	210	/* Set HSION bit */
mbed_official	133:d4dda5c437f0	211	SET_BIT(RCC->CR, RCC_CR_HSION \| RCC_CR_HSITRIM_4);
mbed_official	133:d4dda5c437f0	212
mbed_official	133:d4dda5c437f0	213	/* Reset CFGR register */
mbed_official	133:d4dda5c437f0	214	CLEAR_REG(RCC->CFGR);
mbed_official	133:d4dda5c437f0	215
mbed_official	133:d4dda5c437f0	216	/* Reset HSEON, CSSON, PLLON, PLLI2S */
mbed_official	133:d4dda5c437f0	217	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_CSSON \| RCC_CR_PLLON\| RCC_CR_PLLI2SON);
mbed_official	133:d4dda5c437f0	218
mbed_official	133:d4dda5c437f0	219	/* Reset PLLCFGR register */
mbed_official	133:d4dda5c437f0	220	CLEAR_REG(RCC->PLLCFGR);
mbed_official	133:d4dda5c437f0	221	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLN_6 \| RCC_PLLCFGR_PLLN_7 \| RCC_PLLCFGR_PLLQ_2);
mbed_official	133:d4dda5c437f0	222
mbed_official	133:d4dda5c437f0	223	/* Reset PLLI2SCFGR register */
mbed_official	133:d4dda5c437f0	224	CLEAR_REG(RCC->PLLI2SCFGR);
mbed_official	133:d4dda5c437f0	225	SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 \| RCC_PLLI2SCFGR_PLLI2SN_7 \| RCC_PLLI2SCFGR_PLLI2SR_1);
mbed_official	133:d4dda5c437f0	226
mbed_official	133:d4dda5c437f0	227	/* Reset HSEBYP bit */
mbed_official	133:d4dda5c437f0	228	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
mbed_official	133:d4dda5c437f0	229
mbed_official	133:d4dda5c437f0	230	/* Disable all interrupts */
mbed_official	133:d4dda5c437f0	231	CLEAR_REG(RCC->CIR);
mbed_official	133:d4dda5c437f0	232	}
mbed_official	133:d4dda5c437f0	233
mbed_official	133:d4dda5c437f0	234	/**
mbed_official	133:d4dda5c437f0	235	* @brief Initializes the RCC Oscillators according to the specified parameters in the
mbed_official	133:d4dda5c437f0	236	* RCC_OscInitTypeDef.
mbed_official	133:d4dda5c437f0	237	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official	133:d4dda5c437f0	238	* contains the configuration information for the RCC Oscillators.
mbed_official	133:d4dda5c437f0	239	* @note The PLL is not disabled when used as system clock.
mbed_official	133:d4dda5c437f0	240	* @retval HAL status
mbed_official	133:d4dda5c437f0	241	*/
mbed_official	133:d4dda5c437f0	242	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official	133:d4dda5c437f0	243	{
mbed_official	242:7074e42da0b2	244	uint32_t tickstart = 0;
mbed_official	133:d4dda5c437f0	245
mbed_official	133:d4dda5c437f0	246	/* Check the parameters */
mbed_official	133:d4dda5c437f0	247	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
mbed_official	133:d4dda5c437f0	248	/------------------------------- HSE Configuration ------------------------/
mbed_official	133:d4dda5c437f0	249	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
mbed_official	133:d4dda5c437f0	250	{
mbed_official	133:d4dda5c437f0	251	/* Check the parameters */
mbed_official	133:d4dda5c437f0	252	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
mbed_official	133:d4dda5c437f0	253	/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
mbed_official	133:d4dda5c437f0	254	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
mbed_official	133:d4dda5c437f0	255	{
mbed_official	133:d4dda5c437f0	256	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
mbed_official	133:d4dda5c437f0	257	{
mbed_official	133:d4dda5c437f0	258	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	259	}
mbed_official	133:d4dda5c437f0	260	}
mbed_official	133:d4dda5c437f0	261	else
mbed_official	133:d4dda5c437f0	262	{
mbed_official	133:d4dda5c437f0	263	/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
mbed_official	133:d4dda5c437f0	264	__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
mbed_official	133:d4dda5c437f0	265
mbed_official	242:7074e42da0b2	266	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	267	tickstart = HAL_GetTick();
mbed_official	133:d4dda5c437f0	268
mbed_official	133:d4dda5c437f0	269	/* Wait till HSE is disabled */
mbed_official	133:d4dda5c437f0	270	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
mbed_official	133:d4dda5c437f0	271	{
mbed_official	242:7074e42da0b2	272	if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	273	{
mbed_official	133:d4dda5c437f0	274	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	275	}
mbed_official	133:d4dda5c437f0	276	}
mbed_official	133:d4dda5c437f0	277
mbed_official	133:d4dda5c437f0	278	/* Set the new HSE configuration ---------------------------------------*/
mbed_official	133:d4dda5c437f0	279	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
mbed_official	133:d4dda5c437f0	280
mbed_official	133:d4dda5c437f0	281	/* Check the HSE State */
mbed_official	133:d4dda5c437f0	282	if((RCC_OscInitStruct->HSEState) == RCC_HSE_ON)
mbed_official	133:d4dda5c437f0	283	{
mbed_official	242:7074e42da0b2	284	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	285	tickstart = HAL_GetTick();
mbed_official	133:d4dda5c437f0	286
mbed_official	133:d4dda5c437f0	287	/* Wait till HSE is ready */
mbed_official	133:d4dda5c437f0	288	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official	133:d4dda5c437f0	289	{
mbed_official	242:7074e42da0b2	290	if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	291	{
mbed_official	133:d4dda5c437f0	292	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	293	}
mbed_official	133:d4dda5c437f0	294	}
mbed_official	133:d4dda5c437f0	295	}
mbed_official	133:d4dda5c437f0	296	else
mbed_official	133:d4dda5c437f0	297	{
mbed_official	242:7074e42da0b2	298	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	299	tickstart = HAL_GetTick();
mbed_official	133:d4dda5c437f0	300
mbed_official	133:d4dda5c437f0	301	/* Wait till HSE is bypassed or disabled */
mbed_official	133:d4dda5c437f0	302	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
mbed_official	133:d4dda5c437f0	303	{
mbed_official	242:7074e42da0b2	304	if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	305	{
mbed_official	133:d4dda5c437f0	306	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	307	}
mbed_official	133:d4dda5c437f0	308	}
mbed_official	133:d4dda5c437f0	309	}
mbed_official	133:d4dda5c437f0	310	}
mbed_official	133:d4dda5c437f0	311	}
mbed_official	133:d4dda5c437f0	312	/----------------------------- HSI Configuration --------------------------/
mbed_official	133:d4dda5c437f0	313	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
mbed_official	133:d4dda5c437f0	314	{
mbed_official	133:d4dda5c437f0	315	/* Check the parameters */
mbed_official	133:d4dda5c437f0	316	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
mbed_official	133:d4dda5c437f0	317	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
mbed_official	133:d4dda5c437f0	318
mbed_official	133:d4dda5c437f0	319	/* When the HSI is used as system clock it will not disabled */
mbed_official	133:d4dda5c437f0	320	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
mbed_official	133:d4dda5c437f0	321	{
mbed_official	133:d4dda5c437f0	322	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
mbed_official	133:d4dda5c437f0	323	{
mbed_official	133:d4dda5c437f0	324	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	325	}
mbed_official	133:d4dda5c437f0	326	}
mbed_official	133:d4dda5c437f0	327	else
mbed_official	133:d4dda5c437f0	328	{
mbed_official	133:d4dda5c437f0	329	/* Check the HSI State */
mbed_official	133:d4dda5c437f0	330	if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
mbed_official	133:d4dda5c437f0	331	{
mbed_official	133:d4dda5c437f0	332	/* Enable the Internal High Speed oscillator (HSI). */
mbed_official	133:d4dda5c437f0	333	__HAL_RCC_HSI_ENABLE();
mbed_official	133:d4dda5c437f0	334
mbed_official	242:7074e42da0b2	335	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	336	tickstart = HAL_GetTick();
mbed_official	133:d4dda5c437f0	337
mbed_official	133:d4dda5c437f0	338	/* Wait till HSI is ready */
mbed_official	133:d4dda5c437f0	339	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official	133:d4dda5c437f0	340	{
mbed_official	242:7074e42da0b2	341	if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	342	{
mbed_official	133:d4dda5c437f0	343	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	344	}
mbed_official	133:d4dda5c437f0	345	}
mbed_official	133:d4dda5c437f0	346
mbed_official	133:d4dda5c437f0	347	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
mbed_official	133:d4dda5c437f0	348	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
mbed_official	133:d4dda5c437f0	349	}
mbed_official	133:d4dda5c437f0	350	else
mbed_official	133:d4dda5c437f0	351	{
mbed_official	133:d4dda5c437f0	352	/* Disable the Internal High Speed oscillator (HSI). */
mbed_official	133:d4dda5c437f0	353	__HAL_RCC_HSI_DISABLE();
mbed_official	133:d4dda5c437f0	354
mbed_official	242:7074e42da0b2	355	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	356	tickstart = HAL_GetTick();
mbed_official	133:d4dda5c437f0	357
mbed_official	133:d4dda5c437f0	358	/* Wait till HSI is ready */
mbed_official	133:d4dda5c437f0	359	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official	133:d4dda5c437f0	360	{
mbed_official	242:7074e42da0b2	361	if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	362	{
mbed_official	133:d4dda5c437f0	363	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	364	}
mbed_official	133:d4dda5c437f0	365	}
mbed_official	133:d4dda5c437f0	366	}
mbed_official	133:d4dda5c437f0	367	}
mbed_official	133:d4dda5c437f0	368	}
mbed_official	133:d4dda5c437f0	369	/------------------------------ LSI Configuration -------------------------/
mbed_official	133:d4dda5c437f0	370	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
mbed_official	133:d4dda5c437f0	371	{
mbed_official	133:d4dda5c437f0	372	/* Check the parameters */
mbed_official	133:d4dda5c437f0	373	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
mbed_official	133:d4dda5c437f0	374
mbed_official	133:d4dda5c437f0	375	/* Check the LSI State */
mbed_official	133:d4dda5c437f0	376	if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
mbed_official	133:d4dda5c437f0	377	{
mbed_official	133:d4dda5c437f0	378	/* Enable the Internal Low Speed oscillator (LSI). */
mbed_official	133:d4dda5c437f0	379	__HAL_RCC_LSI_ENABLE();
mbed_official	242:7074e42da0b2	380
mbed_official	242:7074e42da0b2	381	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	382	tickstart = HAL_GetTick();
mbed_official	242:7074e42da0b2	383
mbed_official	133:d4dda5c437f0	384	/* Wait till LSI is ready */
mbed_official	133:d4dda5c437f0	385	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
mbed_official	133:d4dda5c437f0	386	{
mbed_official	242:7074e42da0b2	387	if((int32_t) (HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	388	{
mbed_official	133:d4dda5c437f0	389	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	390	}
mbed_official	133:d4dda5c437f0	391	}
mbed_official	133:d4dda5c437f0	392	}
mbed_official	133:d4dda5c437f0	393	else
mbed_official	133:d4dda5c437f0	394	{
mbed_official	133:d4dda5c437f0	395	/* Disable the Internal Low Speed oscillator (LSI). */
mbed_official	133:d4dda5c437f0	396	__HAL_RCC_LSI_DISABLE();
mbed_official	242:7074e42da0b2	397
mbed_official	242:7074e42da0b2	398	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	399	tickstart = HAL_GetTick();
mbed_official	133:d4dda5c437f0	400
mbed_official	133:d4dda5c437f0	401	/* Wait till LSI is ready */
mbed_official	133:d4dda5c437f0	402	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
mbed_official	133:d4dda5c437f0	403	{
mbed_official	242:7074e42da0b2	404	if((int32_t) (HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	405	{
mbed_official	133:d4dda5c437f0	406	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	407	}
mbed_official	133:d4dda5c437f0	408	}
mbed_official	133:d4dda5c437f0	409	}
mbed_official	133:d4dda5c437f0	410	}
mbed_official	133:d4dda5c437f0	411	/------------------------------ LSE Configuration -------------------------/
mbed_official	133:d4dda5c437f0	412	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
mbed_official	133:d4dda5c437f0	413	{
mbed_official	133:d4dda5c437f0	414	/* Check the parameters */
mbed_official	133:d4dda5c437f0	415	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
mbed_official	133:d4dda5c437f0	416
mbed_official	133:d4dda5c437f0	417	/* Enable Power Clock*/
mbed_official	133:d4dda5c437f0	418	__PWR_CLK_ENABLE();
mbed_official	133:d4dda5c437f0	419
mbed_official	133:d4dda5c437f0	420	/* Enable write access to Backup domain */
mbed_official	133:d4dda5c437f0	421	PWR->CR \|= PWR_CR_DBP;
mbed_official	133:d4dda5c437f0	422
mbed_official	133:d4dda5c437f0	423	/* Wait for Backup domain Write protection disable */
mbed_official	242:7074e42da0b2	424	tickstart = HAL_GetTick();
mbed_official	133:d4dda5c437f0	425
mbed_official	133:d4dda5c437f0	426	while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official	133:d4dda5c437f0	427	{
mbed_official	242:7074e42da0b2	428	if((int32_t) (HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	429	{
mbed_official	133:d4dda5c437f0	430	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	431	}
mbed_official	133:d4dda5c437f0	432	}
mbed_official	242:7074e42da0b2	433
mbed_official	133:d4dda5c437f0	434	/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
mbed_official	133:d4dda5c437f0	435	__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
mbed_official	133:d4dda5c437f0	436
mbed_official	242:7074e42da0b2	437	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	438	tickstart = HAL_GetTick();
mbed_official	242:7074e42da0b2	439
mbed_official	133:d4dda5c437f0	440	/* Wait till LSE is ready */
mbed_official	133:d4dda5c437f0	441	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
mbed_official	133:d4dda5c437f0	442	{
mbed_official	242:7074e42da0b2	443	if((int32_t) (HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	444	{
mbed_official	133:d4dda5c437f0	445	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	446	}
mbed_official	133:d4dda5c437f0	447	}
mbed_official	133:d4dda5c437f0	448
mbed_official	133:d4dda5c437f0	449	/* Set the new LSE configuration -----------------------------------------*/
mbed_official	133:d4dda5c437f0	450	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
mbed_official	133:d4dda5c437f0	451	/* Check the LSE State */
mbed_official	133:d4dda5c437f0	452	if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
mbed_official	133:d4dda5c437f0	453	{
mbed_official	242:7074e42da0b2	454	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	455	tickstart = HAL_GetTick();
mbed_official	133:d4dda5c437f0	456
mbed_official	133:d4dda5c437f0	457	/* Wait till LSE is ready */
mbed_official	133:d4dda5c437f0	458	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official	133:d4dda5c437f0	459	{
mbed_official	242:7074e42da0b2	460	if((int32_t) (HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	461	{
mbed_official	133:d4dda5c437f0	462	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	463	}
mbed_official	133:d4dda5c437f0	464	}
mbed_official	133:d4dda5c437f0	465	}
mbed_official	133:d4dda5c437f0	466	else
mbed_official	133:d4dda5c437f0	467	{
mbed_official	242:7074e42da0b2	468	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	469	tickstart = HAL_GetTick();
mbed_official	133:d4dda5c437f0	470
mbed_official	133:d4dda5c437f0	471	/* Wait till LSE is ready */
mbed_official	133:d4dda5c437f0	472	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
mbed_official	133:d4dda5c437f0	473	{
mbed_official	242:7074e42da0b2	474	if((int32_t) (HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	475	{
mbed_official	133:d4dda5c437f0	476	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	477	}
mbed_official	133:d4dda5c437f0	478	}
mbed_official	133:d4dda5c437f0	479	}
mbed_official	133:d4dda5c437f0	480	}
mbed_official	133:d4dda5c437f0	481	/-------------------------------- PLL Configuration -----------------------/
mbed_official	133:d4dda5c437f0	482	/* Check the parameters */
mbed_official	133:d4dda5c437f0	483	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
mbed_official	133:d4dda5c437f0	484	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
mbed_official	133:d4dda5c437f0	485	{
mbed_official	133:d4dda5c437f0	486	/* Check if the PLL is used as system clock or not */
mbed_official	133:d4dda5c437f0	487	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
mbed_official	133:d4dda5c437f0	488	{
mbed_official	133:d4dda5c437f0	489	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
mbed_official	133:d4dda5c437f0	490	{
mbed_official	133:d4dda5c437f0	491	/* Check the parameters */
mbed_official	133:d4dda5c437f0	492	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
mbed_official	133:d4dda5c437f0	493	assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
mbed_official	133:d4dda5c437f0	494	assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
mbed_official	133:d4dda5c437f0	495	assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
mbed_official	133:d4dda5c437f0	496	assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
mbed_official	133:d4dda5c437f0	497
mbed_official	133:d4dda5c437f0	498	/* Disable the main PLL. */
mbed_official	133:d4dda5c437f0	499	__HAL_RCC_PLL_DISABLE();
mbed_official	242:7074e42da0b2	500
mbed_official	242:7074e42da0b2	501	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	502	tickstart = HAL_GetTick();
mbed_official	242:7074e42da0b2	503
mbed_official	133:d4dda5c437f0	504	/* Wait till PLL is ready */
mbed_official	133:d4dda5c437f0	505	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
mbed_official	133:d4dda5c437f0	506	{
mbed_official	242:7074e42da0b2	507	if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	508	{
mbed_official	133:d4dda5c437f0	509	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	510	}
mbed_official	133:d4dda5c437f0	511	}
mbed_official	133:d4dda5c437f0	512
mbed_official	133:d4dda5c437f0	513	/* Configure the main PLL clock source, multiplication and division factors. */
mbed_official	133:d4dda5c437f0	514	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
mbed_official	133:d4dda5c437f0	515	RCC_OscInitStruct->PLL.PLLM,
mbed_official	133:d4dda5c437f0	516	RCC_OscInitStruct->PLL.PLLN,
mbed_official	133:d4dda5c437f0	517	RCC_OscInitStruct->PLL.PLLP,
mbed_official	133:d4dda5c437f0	518	RCC_OscInitStruct->PLL.PLLQ);
mbed_official	133:d4dda5c437f0	519	/* Enable the main PLL. */
mbed_official	133:d4dda5c437f0	520	__HAL_RCC_PLL_ENABLE();
mbed_official	133:d4dda5c437f0	521
mbed_official	242:7074e42da0b2	522	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	523	tickstart = HAL_GetTick();
mbed_official	242:7074e42da0b2	524
mbed_official	133:d4dda5c437f0	525	/* Wait till PLL is ready */
mbed_official	133:d4dda5c437f0	526	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official	133:d4dda5c437f0	527	{
mbed_official	242:7074e42da0b2	528	if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	529	{
mbed_official	133:d4dda5c437f0	530	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	531	}
mbed_official	133:d4dda5c437f0	532	}
mbed_official	133:d4dda5c437f0	533	}
mbed_official	133:d4dda5c437f0	534	else
mbed_official	133:d4dda5c437f0	535	{
mbed_official	133:d4dda5c437f0	536	/* Disable the main PLL. */
mbed_official	133:d4dda5c437f0	537	__HAL_RCC_PLL_DISABLE();
mbed_official	242:7074e42da0b2	538
mbed_official	242:7074e42da0b2	539	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	540	tickstart = HAL_GetTick();
mbed_official	242:7074e42da0b2	541
mbed_official	133:d4dda5c437f0	542	/* Wait till PLL is ready */
mbed_official	133:d4dda5c437f0	543	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
mbed_official	133:d4dda5c437f0	544	{
mbed_official	242:7074e42da0b2	545	if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	546	{
mbed_official	133:d4dda5c437f0	547	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	548	}
mbed_official	133:d4dda5c437f0	549	}
mbed_official	133:d4dda5c437f0	550	}
mbed_official	133:d4dda5c437f0	551	}
mbed_official	133:d4dda5c437f0	552	else
mbed_official	133:d4dda5c437f0	553	{
mbed_official	133:d4dda5c437f0	554	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	555	}
mbed_official	133:d4dda5c437f0	556	}
mbed_official	133:d4dda5c437f0	557	return HAL_OK;
mbed_official	133:d4dda5c437f0	558	}
mbed_official	133:d4dda5c437f0	559
mbed_official	133:d4dda5c437f0	560	/**
mbed_official	133:d4dda5c437f0	561	* @brief Initializes the CPU, AHB and APB busses clocks according to the specified
mbed_official	133:d4dda5c437f0	562	* parameters in the RCC_ClkInitStruct.
mbed_official	133:d4dda5c437f0	563	* @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official	133:d4dda5c437f0	564	* contains the configuration information for the RCC peripheral.
mbed_official	133:d4dda5c437f0	565	* @param FLatency: FLASH Latency, this parameter depend on device selected
mbed_official	133:d4dda5c437f0	566	*
mbed_official	133:d4dda5c437f0	567	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official	133:d4dda5c437f0	568	* and updated by HAL_RCC_GetHCLKFreq() function called within this function
mbed_official	133:d4dda5c437f0	569	*
mbed_official	133:d4dda5c437f0	570	* @note The HSI is used (enabled by hardware) as system clock source after
mbed_official	133:d4dda5c437f0	571	* startup from Reset, wake-up from STOP and STANDBY mode, or in case
mbed_official	133:d4dda5c437f0	572	* of failure of the HSE used directly or indirectly as system clock
mbed_official	133:d4dda5c437f0	573	* (if the Clock Security System CSS is enabled).
mbed_official	133:d4dda5c437f0	574	*
mbed_official	133:d4dda5c437f0	575	* @note A switch from one clock source to another occurs only if the target
mbed_official	133:d4dda5c437f0	576	* clock source is ready (clock stable after startup delay or PLL locked).
mbed_official	133:d4dda5c437f0	577	* If a clock source which is not yet ready is selected, the switch will
mbed_official	133:d4dda5c437f0	578	* occur when the clock source will be ready.
mbed_official	133:d4dda5c437f0	579	*
mbed_official	133:d4dda5c437f0	580	* @note Depending on the device voltage range, the software has to set correctly
mbed_official	133:d4dda5c437f0	581	* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
mbed_official	133:d4dda5c437f0	582	* (for more details refer to section above "Initialization/de-initialization functions")
mbed_official	133:d4dda5c437f0	583	* @retval None
mbed_official	133:d4dda5c437f0	584	*/
mbed_official	133:d4dda5c437f0	585	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
mbed_official	133:d4dda5c437f0	586	{
mbed_official	242:7074e42da0b2	587	uint32_t tickstart = 0;
mbed_official	133:d4dda5c437f0	588
mbed_official	133:d4dda5c437f0	589	/* Check the parameters */
mbed_official	133:d4dda5c437f0	590	assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
mbed_official	133:d4dda5c437f0	591	assert_param(IS_FLASH_LATENCY(FLatency));
mbed_official	133:d4dda5c437f0	592
mbed_official	133:d4dda5c437f0	593	/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
mbed_official	133:d4dda5c437f0	594	must be correctly programmed according to the frequency of the CPU clock
mbed_official	133:d4dda5c437f0	595	(HCLK) and the supply voltage of the device. */
mbed_official	133:d4dda5c437f0	596
mbed_official	133:d4dda5c437f0	597	/* Increasing the CPU frequency */
mbed_official	133:d4dda5c437f0	598	if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
mbed_official	133:d4dda5c437f0	599	{
mbed_official	133:d4dda5c437f0	600	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official	133:d4dda5c437f0	601	__HAL_FLASH_SET_LATENCY(FLatency);
mbed_official	133:d4dda5c437f0	602
mbed_official	133:d4dda5c437f0	603	/* Check that the new number of wait states is taken into account to access the Flash
mbed_official	133:d4dda5c437f0	604	memory by reading the FLASH_ACR register */
mbed_official	133:d4dda5c437f0	605	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official	133:d4dda5c437f0	606	{
mbed_official	133:d4dda5c437f0	607	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	608	}
mbed_official	133:d4dda5c437f0	609
mbed_official	242:7074e42da0b2	610	/-------------------------- HCLK Configuration --------------------------/
mbed_official	242:7074e42da0b2	611	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
mbed_official	242:7074e42da0b2	612	{
mbed_official	242:7074e42da0b2	613	assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
mbed_official	242:7074e42da0b2	614	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
mbed_official	242:7074e42da0b2	615	}
mbed_official	242:7074e42da0b2	616
mbed_official	133:d4dda5c437f0	617	/------------------------- SYSCLK Configuration ---------------------------/
mbed_official	133:d4dda5c437f0	618	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
mbed_official	133:d4dda5c437f0	619	{
mbed_official	133:d4dda5c437f0	620	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
mbed_official	133:d4dda5c437f0	621
mbed_official	133:d4dda5c437f0	622	/* HSE is selected as System Clock Source */
mbed_official	133:d4dda5c437f0	623	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official	133:d4dda5c437f0	624	{
mbed_official	133:d4dda5c437f0	625	/* Check the HSE ready flag */
mbed_official	133:d4dda5c437f0	626	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official	133:d4dda5c437f0	627	{
mbed_official	133:d4dda5c437f0	628	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	629	}
mbed_official	133:d4dda5c437f0	630	}
mbed_official	133:d4dda5c437f0	631	/* PLL is selected as System Clock Source */
mbed_official	133:d4dda5c437f0	632	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official	133:d4dda5c437f0	633	{
mbed_official	133:d4dda5c437f0	634	/* Check the PLL ready flag */
mbed_official	133:d4dda5c437f0	635	if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official	133:d4dda5c437f0	636	{
mbed_official	133:d4dda5c437f0	637	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	638	}
mbed_official	133:d4dda5c437f0	639	}
mbed_official	133:d4dda5c437f0	640	/* HSI is selected as System Clock Source */
mbed_official	133:d4dda5c437f0	641	else
mbed_official	133:d4dda5c437f0	642	{
mbed_official	133:d4dda5c437f0	643	/* Check the HSI ready flag */
mbed_official	133:d4dda5c437f0	644	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official	133:d4dda5c437f0	645	{
mbed_official	133:d4dda5c437f0	646	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	647	}
mbed_official	133:d4dda5c437f0	648	}
mbed_official	133:d4dda5c437f0	649	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
mbed_official	133:d4dda5c437f0	650
mbed_official	242:7074e42da0b2	651	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	652	tickstart = HAL_GetTick();
mbed_official	133:d4dda5c437f0	653
mbed_official	133:d4dda5c437f0	654	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official	133:d4dda5c437f0	655	{
mbed_official	133:d4dda5c437f0	656	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
mbed_official	133:d4dda5c437f0	657	{
mbed_official	242:7074e42da0b2	658	if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	659	{
mbed_official	133:d4dda5c437f0	660	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	661	}
mbed_official	133:d4dda5c437f0	662	}
mbed_official	133:d4dda5c437f0	663	}
mbed_official	133:d4dda5c437f0	664	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official	133:d4dda5c437f0	665	{
mbed_official	133:d4dda5c437f0	666	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
mbed_official	133:d4dda5c437f0	667	{
mbed_official	242:7074e42da0b2	668	if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	669	{
mbed_official	133:d4dda5c437f0	670	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	671	}
mbed_official	133:d4dda5c437f0	672	}
mbed_official	133:d4dda5c437f0	673	}
mbed_official	133:d4dda5c437f0	674	else
mbed_official	133:d4dda5c437f0	675	{
mbed_official	133:d4dda5c437f0	676	while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
mbed_official	133:d4dda5c437f0	677	{
mbed_official	242:7074e42da0b2	678	if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	679	{
mbed_official	133:d4dda5c437f0	680	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	681	}
mbed_official	133:d4dda5c437f0	682	}
mbed_official	133:d4dda5c437f0	683	}
mbed_official	133:d4dda5c437f0	684	}
mbed_official	133:d4dda5c437f0	685	}
mbed_official	133:d4dda5c437f0	686	/* Decreasing the CPU frequency */
mbed_official	133:d4dda5c437f0	687	else
mbed_official	133:d4dda5c437f0	688	{
mbed_official	242:7074e42da0b2	689	/-------------------------- HCLK Configuration --------------------------/
mbed_official	242:7074e42da0b2	690	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
mbed_official	242:7074e42da0b2	691	{
mbed_official	242:7074e42da0b2	692	assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
mbed_official	242:7074e42da0b2	693	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
mbed_official	242:7074e42da0b2	694	}
mbed_official	242:7074e42da0b2	695
mbed_official	242:7074e42da0b2	696	/------------------------- SYSCLK Configuration -------------------------/
mbed_official	133:d4dda5c437f0	697	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
mbed_official	133:d4dda5c437f0	698	{
mbed_official	133:d4dda5c437f0	699	assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
mbed_official	133:d4dda5c437f0	700
mbed_official	133:d4dda5c437f0	701	/* HSE is selected as System Clock Source */
mbed_official	133:d4dda5c437f0	702	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official	133:d4dda5c437f0	703	{
mbed_official	133:d4dda5c437f0	704	/* Check the HSE ready flag */
mbed_official	133:d4dda5c437f0	705	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official	133:d4dda5c437f0	706	{
mbed_official	133:d4dda5c437f0	707	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	708	}
mbed_official	133:d4dda5c437f0	709	}
mbed_official	133:d4dda5c437f0	710	/* PLL is selected as System Clock Source */
mbed_official	133:d4dda5c437f0	711	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official	133:d4dda5c437f0	712	{
mbed_official	133:d4dda5c437f0	713	/* Check the PLL ready flag */
mbed_official	133:d4dda5c437f0	714	if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official	133:d4dda5c437f0	715	{
mbed_official	133:d4dda5c437f0	716	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	717	}
mbed_official	133:d4dda5c437f0	718	}
mbed_official	133:d4dda5c437f0	719	/* HSI is selected as System Clock Source */
mbed_official	133:d4dda5c437f0	720	else
mbed_official	133:d4dda5c437f0	721	{
mbed_official	133:d4dda5c437f0	722	/* Check the HSI ready flag */
mbed_official	133:d4dda5c437f0	723	if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official	133:d4dda5c437f0	724	{
mbed_official	133:d4dda5c437f0	725	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	726	}
mbed_official	133:d4dda5c437f0	727	}
mbed_official	133:d4dda5c437f0	728	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
mbed_official	133:d4dda5c437f0	729
mbed_official	242:7074e42da0b2	730	/* Get Start Tick*/
mbed_official	242:7074e42da0b2	731	tickstart = HAL_GetTick();
mbed_official	133:d4dda5c437f0	732
mbed_official	133:d4dda5c437f0	733	if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official	133:d4dda5c437f0	734	{
mbed_official	133:d4dda5c437f0	735	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
mbed_official	133:d4dda5c437f0	736	{
mbed_official	242:7074e42da0b2	737	if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	738	{
mbed_official	133:d4dda5c437f0	739	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	740	}
mbed_official	133:d4dda5c437f0	741	}
mbed_official	133:d4dda5c437f0	742	}
mbed_official	133:d4dda5c437f0	743	else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official	133:d4dda5c437f0	744	{
mbed_official	133:d4dda5c437f0	745	while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
mbed_official	133:d4dda5c437f0	746	{
mbed_official	242:7074e42da0b2	747	if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	748	{
mbed_official	133:d4dda5c437f0	749	return HAL_TIMEOUT;
mbed_official	133:d4dda5c437f0	750	}
mbed_official	133:d4dda5c437f0	751	}
mbed_official	133:d4dda5c437f0	752	}
mbed_official	133:d4dda5c437f0	753	else
mbed_official	133:d4dda5c437f0	754	{
mbed_official	133:d4dda5c437f0	755	while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
mbed_official	133:d4dda5c437f0	756	{
mbed_official	242:7074e42da0b2	757	if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official	133:d4dda5c437f0	758	{
mbed_official	133:d4dda5c437f0	759	return HAL_TIMEOUT;
mbed_official	242:7074e42da0b2	760	}
mbed_official	133:d4dda5c437f0	761	}
mbed_official	133:d4dda5c437f0	762	}
mbed_official	133:d4dda5c437f0	763	}
mbed_official	133:d4dda5c437f0	764
mbed_official	133:d4dda5c437f0	765	/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official	133:d4dda5c437f0	766	__HAL_FLASH_SET_LATENCY(FLatency);
mbed_official	133:d4dda5c437f0	767
mbed_official	133:d4dda5c437f0	768	/* Check that the new number of wait states is taken into account to access the Flash
mbed_official	133:d4dda5c437f0	769	memory by reading the FLASH_ACR register */
mbed_official	133:d4dda5c437f0	770	if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official	133:d4dda5c437f0	771	{
mbed_official	133:d4dda5c437f0	772	return HAL_ERROR;
mbed_official	133:d4dda5c437f0	773	}
mbed_official	133:d4dda5c437f0	774	}
mbed_official	242:7074e42da0b2	775
mbed_official	133:d4dda5c437f0	776	/-------------------------- PCLK1 Configuration ---------------------------/
mbed_official	133:d4dda5c437f0	777	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
mbed_official	133:d4dda5c437f0	778	{
mbed_official	133:d4dda5c437f0	779	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
mbed_official	133:d4dda5c437f0	780	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
mbed_official	133:d4dda5c437f0	781	}
mbed_official	133:d4dda5c437f0	782
mbed_official	133:d4dda5c437f0	783	/-------------------------- PCLK2 Configuration ---------------------------/
mbed_official	133:d4dda5c437f0	784	if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
mbed_official	133:d4dda5c437f0	785	{
mbed_official	133:d4dda5c437f0	786	assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
mbed_official	133:d4dda5c437f0	787	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
mbed_official	133:d4dda5c437f0	788	}
mbed_official	133:d4dda5c437f0	789
mbed_official	242:7074e42da0b2	790	/* Configure the source of time base considering new system clocks settings*/
mbed_official	242:7074e42da0b2	791	HAL_InitTick (TICK_INT_PRIORITY);
mbed_official	133:d4dda5c437f0	792
mbed_official	133:d4dda5c437f0	793	return HAL_OK;
mbed_official	133:d4dda5c437f0	794	}
mbed_official	133:d4dda5c437f0	795
mbed_official	133:d4dda5c437f0	796	/**
mbed_official	133:d4dda5c437f0	797	* @}
mbed_official	133:d4dda5c437f0	798	*/
mbed_official	133:d4dda5c437f0	799
mbed_official	133:d4dda5c437f0	800	/** @defgroup RCC_Group2 Peripheral Control functions
mbed_official	133:d4dda5c437f0	801	* @brief RCC clocks control functions
mbed_official	133:d4dda5c437f0	802	*
mbed_official	133:d4dda5c437f0	803	@verbatim
mbed_official	133:d4dda5c437f0	804	===============================================================================
mbed_official	133:d4dda5c437f0	805	##### Peripheral Control functions #####
mbed_official	133:d4dda5c437f0	806	===============================================================================
mbed_official	133:d4dda5c437f0	807	[..]
mbed_official	133:d4dda5c437f0	808	This subsection provides a set of functions allowing to control the RCC Clocks
mbed_official	133:d4dda5c437f0	809	frequencies.
mbed_official	133:d4dda5c437f0	810
mbed_official	133:d4dda5c437f0	811	@endverbatim
mbed_official	133:d4dda5c437f0	812	* @{
mbed_official	133:d4dda5c437f0	813	*/
mbed_official	133:d4dda5c437f0	814
mbed_official	133:d4dda5c437f0	815	/**
mbed_official	133:d4dda5c437f0	816	* @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
mbed_official	133:d4dda5c437f0	817	* @note PA8/PC9 should be configured in alternate function mode.
mbed_official	133:d4dda5c437f0	818	* @param RCC_MCOx: specifies the output direction for the clock source.
mbed_official	133:d4dda5c437f0	819	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	820	* @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
mbed_official	133:d4dda5c437f0	821	* @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
mbed_official	133:d4dda5c437f0	822	* @param RCC_MCOSource: specifies the clock source to output.
mbed_official	133:d4dda5c437f0	823	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	824	* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
mbed_official	133:d4dda5c437f0	825	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
mbed_official	133:d4dda5c437f0	826	* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
mbed_official	133:d4dda5c437f0	827	* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
mbed_official	133:d4dda5c437f0	828	* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
mbed_official	133:d4dda5c437f0	829	* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
mbed_official	133:d4dda5c437f0	830	* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
mbed_official	133:d4dda5c437f0	831	* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
mbed_official	133:d4dda5c437f0	832	* @param RCC_MCODiv: specifies the MCOx prescaler.
mbed_official	133:d4dda5c437f0	833	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	834	* @arg RCC_MCODIV_1: no division applied to MCOx clock
mbed_official	133:d4dda5c437f0	835	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
mbed_official	133:d4dda5c437f0	836	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
mbed_official	133:d4dda5c437f0	837	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
mbed_official	133:d4dda5c437f0	838	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
mbed_official	133:d4dda5c437f0	839	* @retval None
mbed_official	133:d4dda5c437f0	840	*/
mbed_official	133:d4dda5c437f0	841	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
mbed_official	133:d4dda5c437f0	842	{
mbed_official	133:d4dda5c437f0	843	GPIO_InitTypeDef GPIO_InitStruct;
mbed_official	133:d4dda5c437f0	844	/* Check the parameters */
mbed_official	133:d4dda5c437f0	845	assert_param(IS_RCC_MCO(RCC_MCOx));
mbed_official	133:d4dda5c437f0	846	assert_param(IS_RCC_MCODIV(RCC_MCODiv));
mbed_official	133:d4dda5c437f0	847	/* RCC_MCO1 */
mbed_official	133:d4dda5c437f0	848	if(RCC_MCOx == RCC_MCO1)
mbed_official	133:d4dda5c437f0	849	{
mbed_official	133:d4dda5c437f0	850	assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
mbed_official	133:d4dda5c437f0	851
mbed_official	133:d4dda5c437f0	852	/* MCO1 Clock Enable */
mbed_official	133:d4dda5c437f0	853	__MCO1_CLK_ENABLE();
mbed_official	133:d4dda5c437f0	854
mbed_official	133:d4dda5c437f0	855	/* Configue the MCO1 pin in alternate function mode */
mbed_official	133:d4dda5c437f0	856	GPIO_InitStruct.Pin = MCO1_PIN;
mbed_official	133:d4dda5c437f0	857	GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
mbed_official	133:d4dda5c437f0	858	GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
mbed_official	133:d4dda5c437f0	859	GPIO_InitStruct.Pull = GPIO_NOPULL;
mbed_official	133:d4dda5c437f0	860	GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
mbed_official	133:d4dda5c437f0	861	HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
mbed_official	133:d4dda5c437f0	862
mbed_official	133:d4dda5c437f0	863	/* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
mbed_official	133:d4dda5c437f0	864	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 \| RCC_CFGR_MCO1PRE), (RCC_MCOSource \| RCC_MCODiv));
mbed_official	133:d4dda5c437f0	865	}
mbed_official	133:d4dda5c437f0	866	else
mbed_official	133:d4dda5c437f0	867	{
mbed_official	133:d4dda5c437f0	868	assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
mbed_official	133:d4dda5c437f0	869
mbed_official	133:d4dda5c437f0	870	/* MCO2 Clock Enable */
mbed_official	133:d4dda5c437f0	871	__MCO2_CLK_ENABLE();
mbed_official	133:d4dda5c437f0	872
mbed_official	133:d4dda5c437f0	873	/* Configue the MCO2 pin in alternate function mode */
mbed_official	133:d4dda5c437f0	874	GPIO_InitStruct.Pin = MCO2_PIN;
mbed_official	133:d4dda5c437f0	875	GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
mbed_official	133:d4dda5c437f0	876	GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
mbed_official	133:d4dda5c437f0	877	GPIO_InitStruct.Pull = GPIO_NOPULL;
mbed_official	133:d4dda5c437f0	878	GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
mbed_official	133:d4dda5c437f0	879	HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
mbed_official	133:d4dda5c437f0	880
mbed_official	133:d4dda5c437f0	881	/* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
mbed_official	133:d4dda5c437f0	882	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 \| RCC_CFGR_MCO2PRE), (RCC_MCOSource \| (RCC_MCODiv << 3)));
mbed_official	133:d4dda5c437f0	883	}
mbed_official	133:d4dda5c437f0	884	}
mbed_official	133:d4dda5c437f0	885
mbed_official	133:d4dda5c437f0	886	/**
mbed_official	133:d4dda5c437f0	887	* @brief Enables the Clock Security System.
mbed_official	133:d4dda5c437f0	888	* @note If a failure is detected on the HSE oscillator clock, this oscillator
mbed_official	133:d4dda5c437f0	889	* is automatically disabled and an interrupt is generated to inform the
mbed_official	133:d4dda5c437f0	890	* software about the failure (Clock Security System Interrupt, CSSI),
mbed_official	133:d4dda5c437f0	891	* allowing the MCU to perform rescue operations. The CSSI is linked to
mbed_official	133:d4dda5c437f0	892	* the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
mbed_official	133:d4dda5c437f0	893	* @param None
mbed_official	133:d4dda5c437f0	894	* @retval None
mbed_official	133:d4dda5c437f0	895	*/
mbed_official	133:d4dda5c437f0	896	void HAL_RCC_EnableCSS(void)
mbed_official	133:d4dda5c437f0	897	{
mbed_official	133:d4dda5c437f0	898	(__IO uint32_t ) CR_CSSON_BB = (uint32_t)ENABLE;
mbed_official	133:d4dda5c437f0	899	}
mbed_official	133:d4dda5c437f0	900
mbed_official	133:d4dda5c437f0	901	/**
mbed_official	133:d4dda5c437f0	902	* @brief Disables the Clock Security System.
mbed_official	133:d4dda5c437f0	903	* @param None
mbed_official	133:d4dda5c437f0	904	* @retval None
mbed_official	133:d4dda5c437f0	905	*/
mbed_official	133:d4dda5c437f0	906	void HAL_RCC_DisableCSS(void)
mbed_official	133:d4dda5c437f0	907	{
mbed_official	133:d4dda5c437f0	908	(__IO uint32_t ) CR_CSSON_BB = (uint32_t)DISABLE;
mbed_official	133:d4dda5c437f0	909	}
mbed_official	133:d4dda5c437f0	910
mbed_official	133:d4dda5c437f0	911	/**
mbed_official	133:d4dda5c437f0	912	* @brief Returns the SYSCLK frequency
mbed_official	133:d4dda5c437f0	913	*
mbed_official	133:d4dda5c437f0	914	* @note The system frequency computed by this function is not the real
mbed_official	133:d4dda5c437f0	915	* frequency in the chip. It is calculated based on the predefined
mbed_official	133:d4dda5c437f0	916	* constant and the selected clock source:
mbed_official	133:d4dda5c437f0	917	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
mbed_official	133:d4dda5c437f0	918	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
mbed_official	133:d4dda5c437f0	919	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
mbed_official	133:d4dda5c437f0	920	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official	133:d4dda5c437f0	921	* @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official	133:d4dda5c437f0	922	* 16 MHz) but the real value may vary depending on the variations
mbed_official	133:d4dda5c437f0	923	* in voltage and temperature.
mbed_official	133:d4dda5c437f0	924	* @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official	133:d4dda5c437f0	925	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official	133:d4dda5c437f0	926	* frequency of the crystal used. Otherwise, this function may
mbed_official	133:d4dda5c437f0	927	* have wrong result.
mbed_official	133:d4dda5c437f0	928	*
mbed_official	133:d4dda5c437f0	929	* @note The result of this function could be not correct when using fractional
mbed_official	133:d4dda5c437f0	930	* value for HSE crystal.
mbed_official	133:d4dda5c437f0	931	*
mbed_official	133:d4dda5c437f0	932	* @note This function can be used by the user application to compute the
mbed_official	133:d4dda5c437f0	933	* baudrate for the communication peripherals or configure other parameters.
mbed_official	133:d4dda5c437f0	934	*
mbed_official	133:d4dda5c437f0	935	* @note Each time SYSCLK changes, this function must be called to update the
mbed_official	133:d4dda5c437f0	936	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official	133:d4dda5c437f0	937	*
mbed_official	133:d4dda5c437f0	938	*
mbed_official	133:d4dda5c437f0	939	* @param None
mbed_official	133:d4dda5c437f0	940	* @retval SYSCLK frequency
mbed_official	133:d4dda5c437f0	941	*/
mbed_official	133:d4dda5c437f0	942	uint32_t HAL_RCC_GetSysClockFreq(void)
mbed_official	133:d4dda5c437f0	943	{
mbed_official	133:d4dda5c437f0	944	uint32_t pllm = 0, pllvco = 0, pllp = 0;
mbed_official	133:d4dda5c437f0	945	uint32_t sysclockfreq = 0;
mbed_official	133:d4dda5c437f0	946
mbed_official	133:d4dda5c437f0	947	/* Get SYSCLK source -------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	948	switch (RCC->CFGR & RCC_CFGR_SWS)
mbed_official	133:d4dda5c437f0	949	{
mbed_official	133:d4dda5c437f0	950	case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
mbed_official	133:d4dda5c437f0	951	{
mbed_official	133:d4dda5c437f0	952	sysclockfreq = HSI_VALUE;
mbed_official	133:d4dda5c437f0	953	break;
mbed_official	133:d4dda5c437f0	954	}
mbed_official	133:d4dda5c437f0	955	case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
mbed_official	133:d4dda5c437f0	956	{
mbed_official	133:d4dda5c437f0	957	sysclockfreq = HSE_VALUE;
mbed_official	133:d4dda5c437f0	958	break;
mbed_official	133:d4dda5c437f0	959	}
mbed_official	133:d4dda5c437f0	960	case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
mbed_official	133:d4dda5c437f0	961	{
mbed_official	133:d4dda5c437f0	962	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
mbed_official	133:d4dda5c437f0	963	SYSCLK = PLL_VCO / PLLP */
mbed_official	133:d4dda5c437f0	964	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official	133:d4dda5c437f0	965	if (__RCC_PLLSRC() != 0)
mbed_official	133:d4dda5c437f0	966	{
mbed_official	133:d4dda5c437f0	967	/* HSE used as PLL clock source */
mbed_official	133:d4dda5c437f0	968	pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
mbed_official	133:d4dda5c437f0	969	}
mbed_official	133:d4dda5c437f0	970	else
mbed_official	133:d4dda5c437f0	971	{
mbed_official	133:d4dda5c437f0	972	/* HSI used as PLL clock source */
mbed_official	133:d4dda5c437f0	973	pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
mbed_official	133:d4dda5c437f0	974	}
mbed_official	133:d4dda5c437f0	975	pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
mbed_official	133:d4dda5c437f0	976
mbed_official	133:d4dda5c437f0	977	sysclockfreq = pllvco/pllp;
mbed_official	133:d4dda5c437f0	978	break;
mbed_official	133:d4dda5c437f0	979	}
mbed_official	133:d4dda5c437f0	980	default:
mbed_official	133:d4dda5c437f0	981	{
mbed_official	133:d4dda5c437f0	982	sysclockfreq = HSI_VALUE;
mbed_official	133:d4dda5c437f0	983	break;
mbed_official	133:d4dda5c437f0	984	}
mbed_official	133:d4dda5c437f0	985	}
mbed_official	133:d4dda5c437f0	986	return sysclockfreq;
mbed_official	133:d4dda5c437f0	987	}
mbed_official	133:d4dda5c437f0	988
mbed_official	133:d4dda5c437f0	989	/**
mbed_official	133:d4dda5c437f0	990	* @brief Returns the HCLK frequency
mbed_official	133:d4dda5c437f0	991	* @note Each time HCLK changes, this function must be called to update the
mbed_official	133:d4dda5c437f0	992	* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official	133:d4dda5c437f0	993	*
mbed_official	133:d4dda5c437f0	994	* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official	133:d4dda5c437f0	995	* and updated within this function
mbed_official	133:d4dda5c437f0	996	* @param None
mbed_official	133:d4dda5c437f0	997	* @retval HCLK frequency
mbed_official	133:d4dda5c437f0	998	*/
mbed_official	133:d4dda5c437f0	999	uint32_t HAL_RCC_GetHCLKFreq(void)
mbed_official	133:d4dda5c437f0	1000	{
mbed_official	133:d4dda5c437f0	1001	SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
mbed_official	133:d4dda5c437f0	1002	return SystemCoreClock;
mbed_official	133:d4dda5c437f0	1003	}
mbed_official	133:d4dda5c437f0	1004
mbed_official	133:d4dda5c437f0	1005	/**
mbed_official	133:d4dda5c437f0	1006	* @brief Returns the PCLK1 frequency
mbed_official	133:d4dda5c437f0	1007	* @note Each time PCLK1 changes, this function must be called to update the
mbed_official	133:d4dda5c437f0	1008	* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
mbed_official	133:d4dda5c437f0	1009	* @param None
mbed_official	133:d4dda5c437f0	1010	* @retval PCLK1 frequency
mbed_official	133:d4dda5c437f0	1011	*/
mbed_official	133:d4dda5c437f0	1012	uint32_t HAL_RCC_GetPCLK1Freq(void)
mbed_official	133:d4dda5c437f0	1013	{
mbed_official	133:d4dda5c437f0	1014	/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
mbed_official	133:d4dda5c437f0	1015	return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
mbed_official	133:d4dda5c437f0	1016	}
mbed_official	133:d4dda5c437f0	1017
mbed_official	133:d4dda5c437f0	1018	/**
mbed_official	133:d4dda5c437f0	1019	* @brief Returns the PCLK2 frequency
mbed_official	133:d4dda5c437f0	1020	* @note Each time PCLK2 changes, this function must be called to update the
mbed_official	133:d4dda5c437f0	1021	* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
mbed_official	133:d4dda5c437f0	1022	* @param None
mbed_official	133:d4dda5c437f0	1023	* @retval PCLK2 frequency
mbed_official	133:d4dda5c437f0	1024	*/
mbed_official	133:d4dda5c437f0	1025	uint32_t HAL_RCC_GetPCLK2Freq(void)
mbed_official	133:d4dda5c437f0	1026	{
mbed_official	133:d4dda5c437f0	1027	/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
mbed_official	133:d4dda5c437f0	1028	return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
mbed_official	133:d4dda5c437f0	1029	}
mbed_official	133:d4dda5c437f0	1030
mbed_official	133:d4dda5c437f0	1031	/**
mbed_official	133:d4dda5c437f0	1032	* @brief Configures the RCC_OscInitStruct according to the internal
mbed_official	133:d4dda5c437f0	1033	* RCC configuration registers.
mbed_official	133:d4dda5c437f0	1034	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official	133:d4dda5c437f0	1035	* will be configured.
mbed_official	133:d4dda5c437f0	1036	* @retval None
mbed_official	133:d4dda5c437f0	1037	*/
mbed_official	133:d4dda5c437f0	1038	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official	133:d4dda5c437f0	1039	{
mbed_official	133:d4dda5c437f0	1040	/* Set all possible values for the Oscillator type parameter ---------------*/
mbed_official	133:d4dda5c437f0	1041	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
mbed_official	133:d4dda5c437f0	1042
mbed_official	133:d4dda5c437f0	1043	/* Get the HSE configuration -----------------------------------------------*/
mbed_official	133:d4dda5c437f0	1044	if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
mbed_official	133:d4dda5c437f0	1045	{
mbed_official	133:d4dda5c437f0	1046	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
mbed_official	133:d4dda5c437f0	1047	}
mbed_official	133:d4dda5c437f0	1048	else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
mbed_official	133:d4dda5c437f0	1049	{
mbed_official	133:d4dda5c437f0	1050	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
mbed_official	133:d4dda5c437f0	1051	}
mbed_official	133:d4dda5c437f0	1052	else
mbed_official	133:d4dda5c437f0	1053	{
mbed_official	133:d4dda5c437f0	1054	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
mbed_official	133:d4dda5c437f0	1055	}
mbed_official	133:d4dda5c437f0	1056
mbed_official	133:d4dda5c437f0	1057	/* Get the HSI configuration -----------------------------------------------*/
mbed_official	133:d4dda5c437f0	1058	if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
mbed_official	133:d4dda5c437f0	1059	{
mbed_official	133:d4dda5c437f0	1060	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
mbed_official	133:d4dda5c437f0	1061	}
mbed_official	133:d4dda5c437f0	1062	else
mbed_official	133:d4dda5c437f0	1063	{
mbed_official	133:d4dda5c437f0	1064	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
mbed_official	133:d4dda5c437f0	1065	}
mbed_official	133:d4dda5c437f0	1066
mbed_official	133:d4dda5c437f0	1067	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
mbed_official	133:d4dda5c437f0	1068
mbed_official	133:d4dda5c437f0	1069	/* Get the LSE configuration -----------------------------------------------*/
mbed_official	133:d4dda5c437f0	1070	if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
mbed_official	133:d4dda5c437f0	1071	{
mbed_official	133:d4dda5c437f0	1072	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
mbed_official	133:d4dda5c437f0	1073	}
mbed_official	133:d4dda5c437f0	1074	else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
mbed_official	133:d4dda5c437f0	1075	{
mbed_official	133:d4dda5c437f0	1076	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
mbed_official	133:d4dda5c437f0	1077	}
mbed_official	133:d4dda5c437f0	1078	else
mbed_official	133:d4dda5c437f0	1079	{
mbed_official	133:d4dda5c437f0	1080	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
mbed_official	133:d4dda5c437f0	1081	}
mbed_official	133:d4dda5c437f0	1082
mbed_official	133:d4dda5c437f0	1083	/* Get the LSI configuration -----------------------------------------------*/
mbed_official	133:d4dda5c437f0	1084	if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
mbed_official	133:d4dda5c437f0	1085	{
mbed_official	133:d4dda5c437f0	1086	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
mbed_official	133:d4dda5c437f0	1087	}
mbed_official	133:d4dda5c437f0	1088	else
mbed_official	133:d4dda5c437f0	1089	{
mbed_official	133:d4dda5c437f0	1090	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
mbed_official	133:d4dda5c437f0	1091	}
mbed_official	133:d4dda5c437f0	1092
mbed_official	133:d4dda5c437f0	1093	/* Get the PLL configuration -----------------------------------------------*/
mbed_official	133:d4dda5c437f0	1094	if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
mbed_official	133:d4dda5c437f0	1095	{
mbed_official	133:d4dda5c437f0	1096	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
mbed_official	133:d4dda5c437f0	1097	}
mbed_official	133:d4dda5c437f0	1098	else
mbed_official	133:d4dda5c437f0	1099	{
mbed_official	133:d4dda5c437f0	1100	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
mbed_official	133:d4dda5c437f0	1101	}
mbed_official	133:d4dda5c437f0	1102	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
mbed_official	133:d4dda5c437f0	1103	RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
mbed_official	133:d4dda5c437f0	1104	RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
mbed_official	133:d4dda5c437f0	1105	RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
mbed_official	133:d4dda5c437f0	1106	RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
mbed_official	133:d4dda5c437f0	1107	}
mbed_official	133:d4dda5c437f0	1108
mbed_official	133:d4dda5c437f0	1109	/**
mbed_official	133:d4dda5c437f0	1110	* @brief Configures the RCC_ClkInitStruct according to the internal
mbed_official	133:d4dda5c437f0	1111	* RCC configuration registers.
mbed_official	133:d4dda5c437f0	1112	* @param RCC_OscInitStruct: pointer to an RCC_ClkInitTypeDef structure that
mbed_official	133:d4dda5c437f0	1113	* will be configured.
mbed_official	133:d4dda5c437f0	1114	* @param pFLatency: Pointer on the Flash Latency.
mbed_official	133:d4dda5c437f0	1115	* @retval None
mbed_official	133:d4dda5c437f0	1116	*/
mbed_official	133:d4dda5c437f0	1117	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency)
mbed_official	133:d4dda5c437f0	1118	{
mbed_official	133:d4dda5c437f0	1119	/* Set all possible values for the Clock type parameter --------------------*/
mbed_official	133:d4dda5c437f0	1120	RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2;
mbed_official	133:d4dda5c437f0	1121
mbed_official	133:d4dda5c437f0	1122	/* Get the SYSCLK configuration --------------------------------------------*/
mbed_official	133:d4dda5c437f0	1123	RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
mbed_official	133:d4dda5c437f0	1124
mbed_official	133:d4dda5c437f0	1125	/* Get the HCLK configuration ----------------------------------------------*/
mbed_official	133:d4dda5c437f0	1126	RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
mbed_official	133:d4dda5c437f0	1127
mbed_official	133:d4dda5c437f0	1128	/* Get the APB1 configuration ----------------------------------------------*/
mbed_official	133:d4dda5c437f0	1129	RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
mbed_official	133:d4dda5c437f0	1130
mbed_official	133:d4dda5c437f0	1131	/* Get the APB2 configuration ----------------------------------------------*/
mbed_official	133:d4dda5c437f0	1132	RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
mbed_official	133:d4dda5c437f0	1133
mbed_official	133:d4dda5c437f0	1134	/* Get the Flash Wait State (Latency) configuration ------------------------*/
mbed_official	133:d4dda5c437f0	1135	*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
mbed_official	133:d4dda5c437f0	1136	}
mbed_official	133:d4dda5c437f0	1137
mbed_official	133:d4dda5c437f0	1138	/**
mbed_official	133:d4dda5c437f0	1139	* @brief This function handles the RCC CSS interrupt request.
mbed_official	133:d4dda5c437f0	1140	* @note This API should be called under the NMI_Handler().
mbed_official	133:d4dda5c437f0	1141	* @param None
mbed_official	133:d4dda5c437f0	1142	* @retval None
mbed_official	133:d4dda5c437f0	1143	*/
mbed_official	133:d4dda5c437f0	1144	void HAL_RCC_NMI_IRQHandler(void)
mbed_official	133:d4dda5c437f0	1145	{
mbed_official	133:d4dda5c437f0	1146	/* Check RCC CSSF flag */
mbed_official	133:d4dda5c437f0	1147	if(__HAL_RCC_GET_IT(RCC_IT_CSS))
mbed_official	133:d4dda5c437f0	1148	{
mbed_official	133:d4dda5c437f0	1149	/* RCC Clock Security System interrupt user callback */
mbed_official	133:d4dda5c437f0	1150	HAL_RCC_CCSCallback();
mbed_official	133:d4dda5c437f0	1151
mbed_official	133:d4dda5c437f0	1152	/* Clear RCC CSS pending bit */
mbed_official	133:d4dda5c437f0	1153	__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
mbed_official	133:d4dda5c437f0	1154	}
mbed_official	133:d4dda5c437f0	1155	}
mbed_official	133:d4dda5c437f0	1156
mbed_official	133:d4dda5c437f0	1157	/**
mbed_official	133:d4dda5c437f0	1158	* @brief RCC Clock Security System interrupt callback
mbed_official	133:d4dda5c437f0	1159	* @param none
mbed_official	133:d4dda5c437f0	1160	* @retval none
mbed_official	133:d4dda5c437f0	1161	*/
mbed_official	133:d4dda5c437f0	1162	__weak void HAL_RCC_CCSCallback(void)
mbed_official	133:d4dda5c437f0	1163	{
mbed_official	133:d4dda5c437f0	1164	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	133:d4dda5c437f0	1165	the HAL_RCC_CCSCallback could be implemented in the user file
mbed_official	133:d4dda5c437f0	1166	*/
mbed_official	133:d4dda5c437f0	1167	}
mbed_official	133:d4dda5c437f0	1168
mbed_official	133:d4dda5c437f0	1169	/**
mbed_official	133:d4dda5c437f0	1170	* @}
mbed_official	133:d4dda5c437f0	1171	*/
mbed_official	133:d4dda5c437f0	1172
mbed_official	133:d4dda5c437f0	1173	/**
mbed_official	133:d4dda5c437f0	1174	* @}
mbed_official	133:d4dda5c437f0	1175	*/
mbed_official	133:d4dda5c437f0	1176
mbed_official	133:d4dda5c437f0	1177	#endif /* HAL_RCC_MODULE_ENABLED */
mbed_official	133:d4dda5c437f0	1178	/**
mbed_official	133:d4dda5c437f0	1179	* @}
mbed_official	133:d4dda5c437f0	1180	*/
mbed_official	133:d4dda5c437f0	1181
mbed_official	133:d4dda5c437f0	1182	/**
mbed_official	133:d4dda5c437f0	1183	* @}
mbed_official	133:d4dda5c437f0	1184	*/
mbed_official	133:d4dda5c437f0	1185
mbed_official	133:d4dda5c437f0	1186	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	18 Jul 2014
Imports:	22
Forks:	0
Commits:	251
Dependents:	1
Dependencies:	0
Followers:	3

targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc.c@242:7074e42da0b2, 2014-06-27 (annotated)

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