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mbed w/ spi bug fig

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targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dma.h@242:7074e42da0b2, 2014-06-27 (annotated)

Committer:
mbed_official
Date:
Fri Jun 27 07:30:09 2014 +0100
Revision:
242:7074e42da0b2
Parent:
133:d4dda5c437f0 
Synchronized with git revision 124ef5e3add9e74a3221347a3fbeea7c8b3cf353



Full URL: https://github.com/mbedmicro/mbed/commit/124ef5e3add9e74a3221347a3fbeea7c8b3cf353/



[DISCO_F407VG] HAL update.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f4xx_hal_dma.h
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 242:7074e42da0b2 5 * @version V1.1.0RC2
mbed_official 242:7074e42da0b2 6 * @date 14-May-2014
mbed_official 133:d4dda5c437f0 7 * @brief Header file of DMA HAL module.
mbed_official 133:d4dda5c437f0 8 ******************************************************************************
mbed_official 133:d4dda5c437f0 9 * @attention
mbed_official 133:d4dda5c437f0 10 *
mbed_official 133:d4dda5c437f0 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 12 *
mbed_official 133:d4dda5c437f0 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 14 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 16 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 19 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 21 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 22 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 23 *
mbed_official 133:d4dda5c437f0 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 34 *
mbed_official 133:d4dda5c437f0 35 ******************************************************************************
mbed_official 133:d4dda5c437f0 36 */
mbed_official 133:d4dda5c437f0 37
mbed_official 133:d4dda5c437f0 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 133:d4dda5c437f0 39 #ifndef __STM32F4xx_HAL_DMA_H
mbed_official 133:d4dda5c437f0 40 #define __STM32F4xx_HAL_DMA_H
mbed_official 133:d4dda5c437f0 41
mbed_official 133:d4dda5c437f0 42 #ifdef __cplusplus
mbed_official 133:d4dda5c437f0 43 extern "C" {
mbed_official 133:d4dda5c437f0 44 #endif
mbed_official 133:d4dda5c437f0 45
mbed_official 133:d4dda5c437f0 46 /* Includes ------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 47 #include "stm32f4xx_hal_def.h"
mbed_official 133:d4dda5c437f0 48
mbed_official 133:d4dda5c437f0 49 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 133:d4dda5c437f0 50 * @{
mbed_official 133:d4dda5c437f0 51 */
mbed_official 133:d4dda5c437f0 52
mbed_official 133:d4dda5c437f0 53 /** @addtogroup DMA
mbed_official 133:d4dda5c437f0 54 * @{
mbed_official 133:d4dda5c437f0 55 */
mbed_official 133:d4dda5c437f0 56
mbed_official 242:7074e42da0b2 57 /* Exported types ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 58
mbed_official 133:d4dda5c437f0 59 /**
mbed_official 242:7074e42da0b2 60 * @brief DMA Configuration Structure definition
mbed_official 133:d4dda5c437f0 61 */
mbed_official 133:d4dda5c437f0 62 typedef struct
mbed_official 133:d4dda5c437f0 63 {
mbed_official 133:d4dda5c437f0 64 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
mbed_official 133:d4dda5c437f0 65 This parameter can be a value of @ref DMA_Channel_selection */
mbed_official 242:7074e42da0b2 66
mbed_official 133:d4dda5c437f0 67 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
mbed_official 133:d4dda5c437f0 68 from memory to memory or from peripheral to memory.
mbed_official 133:d4dda5c437f0 69 This parameter can be a value of @ref DMA_Data_transfer_direction */
mbed_official 133:d4dda5c437f0 70
mbed_official 133:d4dda5c437f0 71 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
mbed_official 242:7074e42da0b2 72 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
mbed_official 242:7074e42da0b2 73
mbed_official 133:d4dda5c437f0 74 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
mbed_official 133:d4dda5c437f0 75 This parameter can be a value of @ref DMA_Memory_incremented_mode */
mbed_official 242:7074e42da0b2 76
mbed_official 133:d4dda5c437f0 77 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
mbed_official 242:7074e42da0b2 78 This parameter can be a value of @ref DMA_Peripheral_data_size */
mbed_official 133:d4dda5c437f0 79
mbed_official 133:d4dda5c437f0 80 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
mbed_official 133:d4dda5c437f0 81 This parameter can be a value of @ref DMA_Memory_data_size */
mbed_official 242:7074e42da0b2 82
mbed_official 133:d4dda5c437f0 83 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
mbed_official 133:d4dda5c437f0 84 This parameter can be a value of @ref DMA_mode
mbed_official 133:d4dda5c437f0 85 @note The circular buffer mode cannot be used if the memory-to-memory
mbed_official 242:7074e42da0b2 86 data transfer is configured on the selected Stream */
mbed_official 133:d4dda5c437f0 87
mbed_official 133:d4dda5c437f0 88 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
mbed_official 133:d4dda5c437f0 89 This parameter can be a value of @ref DMA_Priority_level */
mbed_official 133:d4dda5c437f0 90
mbed_official 133:d4dda5c437f0 91 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
mbed_official 133:d4dda5c437f0 92 This parameter can be a value of @ref DMA_FIFO_direct_mode
mbed_official 133:d4dda5c437f0 93 @note The Direct mode (FIFO mode disabled) cannot be used if the
mbed_official 133:d4dda5c437f0 94 memory-to-memory data transfer is configured on the selected stream */
mbed_official 242:7074e42da0b2 95
mbed_official 133:d4dda5c437f0 96 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
mbed_official 133:d4dda5c437f0 97 This parameter can be a value of @ref DMA_FIFO_threshold_level */
mbed_official 242:7074e42da0b2 98
mbed_official 133:d4dda5c437f0 99 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
mbed_official 133:d4dda5c437f0 100 It specifies the amount of data to be transferred in a single non interruptable
mbed_official 242:7074e42da0b2 101 transaction.
mbed_official 133:d4dda5c437f0 102 This parameter can be a value of @ref DMA_Memory_burst
mbed_official 133:d4dda5c437f0 103 @note The burst mode is possible only if the address Increment mode is enabled. */
mbed_official 242:7074e42da0b2 104
mbed_official 133:d4dda5c437f0 105 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
mbed_official 133:d4dda5c437f0 106 It specifies the amount of data to be transferred in a single non interruptable
mbed_official 133:d4dda5c437f0 107 transaction.
mbed_official 133:d4dda5c437f0 108 This parameter can be a value of @ref DMA_Peripheral_burst
mbed_official 133:d4dda5c437f0 109 @note The burst mode is possible only if the address Increment mode is enabled. */
mbed_official 133:d4dda5c437f0 110 }DMA_InitTypeDef;
mbed_official 133:d4dda5c437f0 111
mbed_official 133:d4dda5c437f0 112 /**
mbed_official 242:7074e42da0b2 113 * @brief HAL DMA State structures definition
mbed_official 242:7074e42da0b2 114 */
mbed_official 133:d4dda5c437f0 115 typedef enum
mbed_official 133:d4dda5c437f0 116 {
mbed_official 242:7074e42da0b2 117 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
mbed_official 133:d4dda5c437f0 118 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
mbed_official 133:d4dda5c437f0 119 HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
mbed_official 242:7074e42da0b2 120 HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
mbed_official 133:d4dda5c437f0 121 HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
mbed_official 242:7074e42da0b2 122 HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
mbed_official 133:d4dda5c437f0 123 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
mbed_official 133:d4dda5c437f0 124 HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
mbed_official 242:7074e42da0b2 125 HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
mbed_official 242:7074e42da0b2 126 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
mbed_official 133:d4dda5c437f0 127 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
mbed_official 133:d4dda5c437f0 128 }HAL_DMA_StateTypeDef;
mbed_official 133:d4dda5c437f0 129
mbed_official 133:d4dda5c437f0 130 /**
mbed_official 242:7074e42da0b2 131 * @brief HAL DMA Error Code structure definition
mbed_official 242:7074e42da0b2 132 */
mbed_official 133:d4dda5c437f0 133 typedef enum
mbed_official 133:d4dda5c437f0 134 {
mbed_official 133:d4dda5c437f0 135 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
mbed_official 133:d4dda5c437f0 136 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
mbed_official 133:d4dda5c437f0 137 }HAL_DMA_LevelCompleteTypeDef;
mbed_official 133:d4dda5c437f0 138
mbed_official 133:d4dda5c437f0 139 /**
mbed_official 242:7074e42da0b2 140 * @brief DMA handle Structure definition
mbed_official 242:7074e42da0b2 141 */
mbed_official 133:d4dda5c437f0 142 typedef struct __DMA_HandleTypeDef
mbed_official 242:7074e42da0b2 143 {
mbed_official 133:d4dda5c437f0 144 DMA_Stream_TypeDef *Instance; /*!< Register base address */
mbed_official 242:7074e42da0b2 145
mbed_official 133:d4dda5c437f0 146 DMA_InitTypeDef Init; /*!< DMA communication parameters */
mbed_official 242:7074e42da0b2 147
mbed_official 133:d4dda5c437f0 148 HAL_LockTypeDef Lock; /*!< DMA locking object */
mbed_official 242:7074e42da0b2 149
mbed_official 133:d4dda5c437f0 150 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
mbed_official 242:7074e42da0b2 151
mbed_official 133:d4dda5c437f0 152 void *Parent; /*!< Parent object state */
mbed_official 242:7074e42da0b2 153
mbed_official 133:d4dda5c437f0 154 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
mbed_official 242:7074e42da0b2 155
mbed_official 133:d4dda5c437f0 156 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
mbed_official 242:7074e42da0b2 157
mbed_official 133:d4dda5c437f0 158 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
mbed_official 242:7074e42da0b2 159
mbed_official 133:d4dda5c437f0 160 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
mbed_official 133:d4dda5c437f0 161
mbed_official 133:d4dda5c437f0 162 __IO uint32_t ErrorCode; /*!< DMA Error code */
mbed_official 242:7074e42da0b2 163 }DMA_HandleTypeDef;
mbed_official 133:d4dda5c437f0 164
mbed_official 133:d4dda5c437f0 165 /* Exported constants --------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 166
mbed_official 133:d4dda5c437f0 167 /** @defgroup DMA_Exported_Constants
mbed_official 133:d4dda5c437f0 168 * @{
mbed_official 133:d4dda5c437f0 169 */
mbed_official 133:d4dda5c437f0 170
mbed_official 133:d4dda5c437f0 171 /** @defgroup DMA_Error_Code
mbed_official 133:d4dda5c437f0 172 * @{
mbed_official 133:d4dda5c437f0 173 */
mbed_official 133:d4dda5c437f0 174 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
mbed_official 133:d4dda5c437f0 175 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
mbed_official 242:7074e42da0b2 176 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
mbed_official 133:d4dda5c437f0 177 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
mbed_official 133:d4dda5c437f0 178 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
mbed_official 133:d4dda5c437f0 179 /**
mbed_official 133:d4dda5c437f0 180 * @}
mbed_official 133:d4dda5c437f0 181 */
mbed_official 133:d4dda5c437f0 182
mbed_official 133:d4dda5c437f0 183 /** @defgroup DMA_Channel_selection
mbed_official 133:d4dda5c437f0 184 * @{
mbed_official 133:d4dda5c437f0 185 */
mbed_official 133:d4dda5c437f0 186 #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
mbed_official 133:d4dda5c437f0 187 #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
mbed_official 133:d4dda5c437f0 188 #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
mbed_official 133:d4dda5c437f0 189 #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
mbed_official 133:d4dda5c437f0 190 #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
mbed_official 133:d4dda5c437f0 191 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
mbed_official 133:d4dda5c437f0 192 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
mbed_official 133:d4dda5c437f0 193 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
mbed_official 133:d4dda5c437f0 194
mbed_official 133:d4dda5c437f0 195 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
mbed_official 133:d4dda5c437f0 196 ((CHANNEL) == DMA_CHANNEL_1) || \
mbed_official 133:d4dda5c437f0 197 ((CHANNEL) == DMA_CHANNEL_2) || \
mbed_official 133:d4dda5c437f0 198 ((CHANNEL) == DMA_CHANNEL_3) || \
mbed_official 133:d4dda5c437f0 199 ((CHANNEL) == DMA_CHANNEL_4) || \
mbed_official 133:d4dda5c437f0 200 ((CHANNEL) == DMA_CHANNEL_5) || \
mbed_official 133:d4dda5c437f0 201 ((CHANNEL) == DMA_CHANNEL_6) || \
mbed_official 133:d4dda5c437f0 202 ((CHANNEL) == DMA_CHANNEL_7))
mbed_official 133:d4dda5c437f0 203 /**
mbed_official 133:d4dda5c437f0 204 * @}
mbed_official 133:d4dda5c437f0 205 */
mbed_official 133:d4dda5c437f0 206
mbed_official 133:d4dda5c437f0 207 /** @defgroup DMA_Data_transfer_direction
mbed_official 133:d4dda5c437f0 208 * @{
mbed_official 133:d4dda5c437f0 209 */
mbed_official 133:d4dda5c437f0 210 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
mbed_official 133:d4dda5c437f0 211 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
mbed_official 133:d4dda5c437f0 212 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
mbed_official 133:d4dda5c437f0 213
mbed_official 133:d4dda5c437f0 214 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
mbed_official 133:d4dda5c437f0 215 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
mbed_official 133:d4dda5c437f0 216 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
mbed_official 133:d4dda5c437f0 217 /**
mbed_official 133:d4dda5c437f0 218 * @}
mbed_official 133:d4dda5c437f0 219 */
mbed_official 133:d4dda5c437f0 220
mbed_official 133:d4dda5c437f0 221 /** @defgroup DMA_Data_buffer_size
mbed_official 133:d4dda5c437f0 222 * @{
mbed_official 133:d4dda5c437f0 223 */
mbed_official 133:d4dda5c437f0 224 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
mbed_official 133:d4dda5c437f0 225 /**
mbed_official 133:d4dda5c437f0 226 * @}
mbed_official 133:d4dda5c437f0 227 */
mbed_official 133:d4dda5c437f0 228
mbed_official 133:d4dda5c437f0 229 /** @defgroup DMA_Peripheral_incremented_mode
mbed_official 133:d4dda5c437f0 230 * @{
mbed_official 133:d4dda5c437f0 231 */
mbed_official 133:d4dda5c437f0 232 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
mbed_official 133:d4dda5c437f0 233 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
mbed_official 133:d4dda5c437f0 234
mbed_official 133:d4dda5c437f0 235 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
mbed_official 133:d4dda5c437f0 236 ((STATE) == DMA_PINC_DISABLE))
mbed_official 133:d4dda5c437f0 237 /**
mbed_official 133:d4dda5c437f0 238 * @}
mbed_official 133:d4dda5c437f0 239 */
mbed_official 133:d4dda5c437f0 240
mbed_official 133:d4dda5c437f0 241 /** @defgroup DMA_Memory_incremented_mode
mbed_official 133:d4dda5c437f0 242 * @{
mbed_official 133:d4dda5c437f0 243 */
mbed_official 133:d4dda5c437f0 244 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
mbed_official 133:d4dda5c437f0 245 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
mbed_official 133:d4dda5c437f0 246
mbed_official 133:d4dda5c437f0 247 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
mbed_official 133:d4dda5c437f0 248 ((STATE) == DMA_MINC_DISABLE))
mbed_official 133:d4dda5c437f0 249 /**
mbed_official 133:d4dda5c437f0 250 * @}
mbed_official 133:d4dda5c437f0 251 */
mbed_official 133:d4dda5c437f0 252
mbed_official 133:d4dda5c437f0 253 /** @defgroup DMA_Peripheral_data_size
mbed_official 133:d4dda5c437f0 254 * @{
mbed_official 133:d4dda5c437f0 255 */
mbed_official 133:d4dda5c437f0 256 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
mbed_official 133:d4dda5c437f0 257 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
mbed_official 133:d4dda5c437f0 258 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
mbed_official 133:d4dda5c437f0 259
mbed_official 133:d4dda5c437f0 260 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
mbed_official 133:d4dda5c437f0 261 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
mbed_official 133:d4dda5c437f0 262 ((SIZE) == DMA_PDATAALIGN_WORD))
mbed_official 133:d4dda5c437f0 263 /**
mbed_official 133:d4dda5c437f0 264 * @}
mbed_official 133:d4dda5c437f0 265 */
mbed_official 133:d4dda5c437f0 266
mbed_official 133:d4dda5c437f0 267
mbed_official 133:d4dda5c437f0 268 /** @defgroup DMA_Memory_data_size
mbed_official 133:d4dda5c437f0 269 * @{
mbed_official 133:d4dda5c437f0 270 */
mbed_official 133:d4dda5c437f0 271 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
mbed_official 133:d4dda5c437f0 272 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
mbed_official 133:d4dda5c437f0 273 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
mbed_official 133:d4dda5c437f0 274
mbed_official 133:d4dda5c437f0 275 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
mbed_official 133:d4dda5c437f0 276 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
mbed_official 133:d4dda5c437f0 277 ((SIZE) == DMA_MDATAALIGN_WORD ))
mbed_official 133:d4dda5c437f0 278 /**
mbed_official 133:d4dda5c437f0 279 * @}
mbed_official 133:d4dda5c437f0 280 */
mbed_official 133:d4dda5c437f0 281
mbed_official 133:d4dda5c437f0 282 /** @defgroup DMA_mode
mbed_official 133:d4dda5c437f0 283 * @{
mbed_official 133:d4dda5c437f0 284 */
mbed_official 133:d4dda5c437f0 285 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
mbed_official 133:d4dda5c437f0 286 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
mbed_official 133:d4dda5c437f0 287 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
mbed_official 133:d4dda5c437f0 288
mbed_official 133:d4dda5c437f0 289 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
mbed_official 133:d4dda5c437f0 290 ((MODE) == DMA_CIRCULAR) || \
mbed_official 133:d4dda5c437f0 291 ((MODE) == DMA_PFCTRL))
mbed_official 133:d4dda5c437f0 292 /**
mbed_official 133:d4dda5c437f0 293 * @}
mbed_official 133:d4dda5c437f0 294 */
mbed_official 133:d4dda5c437f0 295
mbed_official 133:d4dda5c437f0 296 /** @defgroup DMA_Priority_level
mbed_official 133:d4dda5c437f0 297 * @{
mbed_official 133:d4dda5c437f0 298 */
mbed_official 133:d4dda5c437f0 299 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
mbed_official 133:d4dda5c437f0 300 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
mbed_official 133:d4dda5c437f0 301 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
mbed_official 133:d4dda5c437f0 302 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
mbed_official 133:d4dda5c437f0 303
mbed_official 133:d4dda5c437f0 304 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
mbed_official 133:d4dda5c437f0 305 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
mbed_official 133:d4dda5c437f0 306 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
mbed_official 133:d4dda5c437f0 307 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
mbed_official 133:d4dda5c437f0 308 /**
mbed_official 133:d4dda5c437f0 309 * @}
mbed_official 133:d4dda5c437f0 310 */
mbed_official 133:d4dda5c437f0 311
mbed_official 133:d4dda5c437f0 312 /** @defgroup DMA_FIFO_direct_mode
mbed_official 133:d4dda5c437f0 313 * @{
mbed_official 133:d4dda5c437f0 314 */
mbed_official 133:d4dda5c437f0 315 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
mbed_official 133:d4dda5c437f0 316 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
mbed_official 133:d4dda5c437f0 317
mbed_official 133:d4dda5c437f0 318 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
mbed_official 133:d4dda5c437f0 319 ((STATE) == DMA_FIFOMODE_ENABLE))
mbed_official 133:d4dda5c437f0 320 /**
mbed_official 133:d4dda5c437f0 321 * @}
mbed_official 133:d4dda5c437f0 322 */
mbed_official 133:d4dda5c437f0 323
mbed_official 133:d4dda5c437f0 324 /** @defgroup DMA_FIFO_threshold_level
mbed_official 133:d4dda5c437f0 325 * @{
mbed_official 133:d4dda5c437f0 326 */
mbed_official 133:d4dda5c437f0 327 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
mbed_official 133:d4dda5c437f0 328 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
mbed_official 133:d4dda5c437f0 329 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
mbed_official 133:d4dda5c437f0 330 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
mbed_official 133:d4dda5c437f0 331
mbed_official 133:d4dda5c437f0 332 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
mbed_official 133:d4dda5c437f0 333 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
mbed_official 133:d4dda5c437f0 334 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
mbed_official 133:d4dda5c437f0 335 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
mbed_official 133:d4dda5c437f0 336 /**
mbed_official 133:d4dda5c437f0 337 * @}
mbed_official 133:d4dda5c437f0 338 */
mbed_official 133:d4dda5c437f0 339
mbed_official 133:d4dda5c437f0 340 /** @defgroup DMA_Memory_burst
mbed_official 133:d4dda5c437f0 341 * @{
mbed_official 133:d4dda5c437f0 342 */
mbed_official 133:d4dda5c437f0 343 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 344 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
mbed_official 133:d4dda5c437f0 345 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
mbed_official 133:d4dda5c437f0 346 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
mbed_official 133:d4dda5c437f0 347
mbed_official 133:d4dda5c437f0 348 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
mbed_official 133:d4dda5c437f0 349 ((BURST) == DMA_MBURST_INC4) || \
mbed_official 133:d4dda5c437f0 350 ((BURST) == DMA_MBURST_INC8) || \
mbed_official 133:d4dda5c437f0 351 ((BURST) == DMA_MBURST_INC16))
mbed_official 133:d4dda5c437f0 352 /**
mbed_official 133:d4dda5c437f0 353 * @}
mbed_official 133:d4dda5c437f0 354 */
mbed_official 133:d4dda5c437f0 355
mbed_official 133:d4dda5c437f0 356 /** @defgroup DMA_Peripheral_burst
mbed_official 133:d4dda5c437f0 357 * @{
mbed_official 133:d4dda5c437f0 358 */
mbed_official 133:d4dda5c437f0 359 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
mbed_official 133:d4dda5c437f0 360 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
mbed_official 133:d4dda5c437f0 361 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
mbed_official 133:d4dda5c437f0 362 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
mbed_official 133:d4dda5c437f0 363
mbed_official 133:d4dda5c437f0 364 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
mbed_official 133:d4dda5c437f0 365 ((BURST) == DMA_PBURST_INC4) || \
mbed_official 133:d4dda5c437f0 366 ((BURST) == DMA_PBURST_INC8) || \
mbed_official 133:d4dda5c437f0 367 ((BURST) == DMA_PBURST_INC16))
mbed_official 133:d4dda5c437f0 368 /**
mbed_official 133:d4dda5c437f0 369 * @}
mbed_official 133:d4dda5c437f0 370 */
mbed_official 133:d4dda5c437f0 371
mbed_official 133:d4dda5c437f0 372 /** @defgroup DMA_interrupt_enable_definitions
mbed_official 133:d4dda5c437f0 373 * @{
mbed_official 133:d4dda5c437f0 374 */
mbed_official 133:d4dda5c437f0 375 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
mbed_official 133:d4dda5c437f0 376 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
mbed_official 133:d4dda5c437f0 377 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
mbed_official 133:d4dda5c437f0 378 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
mbed_official 133:d4dda5c437f0 379 #define DMA_IT_FE ((uint32_t)0x00000080)
mbed_official 133:d4dda5c437f0 380 /**
mbed_official 133:d4dda5c437f0 381 * @}
mbed_official 133:d4dda5c437f0 382 */
mbed_official 133:d4dda5c437f0 383
mbed_official 133:d4dda5c437f0 384 /** @defgroup DMA_flag_definitions
mbed_official 133:d4dda5c437f0 385 * @{
mbed_official 133:d4dda5c437f0 386 */
mbed_official 133:d4dda5c437f0 387 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
mbed_official 133:d4dda5c437f0 388 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
mbed_official 133:d4dda5c437f0 389 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
mbed_official 133:d4dda5c437f0 390 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
mbed_official 133:d4dda5c437f0 391 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
mbed_official 133:d4dda5c437f0 392 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
mbed_official 133:d4dda5c437f0 393 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
mbed_official 133:d4dda5c437f0 394 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
mbed_official 133:d4dda5c437f0 395 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
mbed_official 133:d4dda5c437f0 396 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
mbed_official 133:d4dda5c437f0 397 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
mbed_official 133:d4dda5c437f0 398 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
mbed_official 133:d4dda5c437f0 399 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
mbed_official 133:d4dda5c437f0 400 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
mbed_official 133:d4dda5c437f0 401 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
mbed_official 133:d4dda5c437f0 402 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
mbed_official 133:d4dda5c437f0 403 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
mbed_official 133:d4dda5c437f0 404 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
mbed_official 133:d4dda5c437f0 405 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
mbed_official 133:d4dda5c437f0 406 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
mbed_official 133:d4dda5c437f0 407 /**
mbed_official 133:d4dda5c437f0 408 * @}
mbed_official 133:d4dda5c437f0 409 */
mbed_official 133:d4dda5c437f0 410
mbed_official 133:d4dda5c437f0 411 /**
mbed_official 133:d4dda5c437f0 412 * @}
mbed_official 133:d4dda5c437f0 413 */
mbed_official 133:d4dda5c437f0 414
mbed_official 133:d4dda5c437f0 415 /* Exported macro ------------------------------------------------------------*/
mbed_official 242:7074e42da0b2 416
mbed_official 242:7074e42da0b2 417 /** @brief Reset DMA handle state
mbed_official 242:7074e42da0b2 418 * @param __HANDLE__: specifies the DMA handle.
mbed_official 242:7074e42da0b2 419 * @retval None
mbed_official 242:7074e42da0b2 420 */
mbed_official 242:7074e42da0b2 421 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
mbed_official 242:7074e42da0b2 422
mbed_official 133:d4dda5c437f0 423 /**
mbed_official 133:d4dda5c437f0 424 * @brief Return the current DMA Stream FIFO filled level.
mbed_official 133:d4dda5c437f0 425 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 426 * @retval The FIFO filling state.
mbed_official 133:d4dda5c437f0 427 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
mbed_official 133:d4dda5c437f0 428 * and not empty.
mbed_official 133:d4dda5c437f0 429 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
mbed_official 133:d4dda5c437f0 430 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
mbed_official 133:d4dda5c437f0 431 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
mbed_official 133:d4dda5c437f0 432 * - DMA_FIFOStatus_Empty: when FIFO is empty
mbed_official 133:d4dda5c437f0 433 * - DMA_FIFOStatus_Full: when FIFO is full
mbed_official 133:d4dda5c437f0 434 */
mbed_official 133:d4dda5c437f0 435 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
mbed_official 133:d4dda5c437f0 436
mbed_official 133:d4dda5c437f0 437 /**
mbed_official 133:d4dda5c437f0 438 * @brief Enable the specified DMA Stream.
mbed_official 133:d4dda5c437f0 439 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 440 * @retval None
mbed_official 133:d4dda5c437f0 441 */
mbed_official 133:d4dda5c437f0 442 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
mbed_official 133:d4dda5c437f0 443
mbed_official 133:d4dda5c437f0 444 /**
mbed_official 133:d4dda5c437f0 445 * @brief Disable the specified DMA Stream.
mbed_official 133:d4dda5c437f0 446 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 447 * @retval None
mbed_official 133:d4dda5c437f0 448 */
mbed_official 133:d4dda5c437f0 449 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
mbed_official 133:d4dda5c437f0 450
mbed_official 133:d4dda5c437f0 451 /* Interrupt & Flag management */
mbed_official 133:d4dda5c437f0 452
mbed_official 133:d4dda5c437f0 453 /**
mbed_official 133:d4dda5c437f0 454 * @brief Return the current DMA Stream transfer complete flag.
mbed_official 133:d4dda5c437f0 455 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 456 * @retval The specified transfer complete flag index.
mbed_official 133:d4dda5c437f0 457 */
mbed_official 133:d4dda5c437f0 458 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
mbed_official 133:d4dda5c437f0 459 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
mbed_official 133:d4dda5c437f0 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
mbed_official 133:d4dda5c437f0 461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
mbed_official 133:d4dda5c437f0 462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
mbed_official 133:d4dda5c437f0 463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
mbed_official 133:d4dda5c437f0 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
mbed_official 133:d4dda5c437f0 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
mbed_official 133:d4dda5c437f0 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
mbed_official 133:d4dda5c437f0 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
mbed_official 133:d4dda5c437f0 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
mbed_official 133:d4dda5c437f0 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
mbed_official 133:d4dda5c437f0 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
mbed_official 133:d4dda5c437f0 471 DMA_FLAG_TCIF3_7)
mbed_official 133:d4dda5c437f0 472
mbed_official 133:d4dda5c437f0 473 /**
mbed_official 133:d4dda5c437f0 474 * @brief Return the current DMA Stream half transfer complete flag.
mbed_official 133:d4dda5c437f0 475 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 476 * @retval The specified half transfer complete flag index.
mbed_official 133:d4dda5c437f0 477 */
mbed_official 133:d4dda5c437f0 478 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
mbed_official 133:d4dda5c437f0 479 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
mbed_official 133:d4dda5c437f0 480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
mbed_official 133:d4dda5c437f0 481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
mbed_official 133:d4dda5c437f0 482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
mbed_official 133:d4dda5c437f0 483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
mbed_official 133:d4dda5c437f0 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
mbed_official 133:d4dda5c437f0 485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
mbed_official 133:d4dda5c437f0 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
mbed_official 133:d4dda5c437f0 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
mbed_official 133:d4dda5c437f0 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
mbed_official 133:d4dda5c437f0 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
mbed_official 133:d4dda5c437f0 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
mbed_official 133:d4dda5c437f0 491 DMA_FLAG_HTIF3_7)
mbed_official 133:d4dda5c437f0 492
mbed_official 133:d4dda5c437f0 493 /**
mbed_official 133:d4dda5c437f0 494 * @brief Return the current DMA Stream transfer error flag.
mbed_official 133:d4dda5c437f0 495 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 496 * @retval The specified transfer error flag index.
mbed_official 133:d4dda5c437f0 497 */
mbed_official 133:d4dda5c437f0 498 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
mbed_official 133:d4dda5c437f0 499 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
mbed_official 133:d4dda5c437f0 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
mbed_official 133:d4dda5c437f0 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
mbed_official 133:d4dda5c437f0 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
mbed_official 133:d4dda5c437f0 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
mbed_official 133:d4dda5c437f0 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
mbed_official 133:d4dda5c437f0 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
mbed_official 133:d4dda5c437f0 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
mbed_official 133:d4dda5c437f0 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
mbed_official 133:d4dda5c437f0 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
mbed_official 133:d4dda5c437f0 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
mbed_official 133:d4dda5c437f0 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
mbed_official 133:d4dda5c437f0 511 DMA_FLAG_TEIF3_7)
mbed_official 133:d4dda5c437f0 512
mbed_official 133:d4dda5c437f0 513 /**
mbed_official 133:d4dda5c437f0 514 * @brief Return the current DMA Stream FIFO error flag.
mbed_official 133:d4dda5c437f0 515 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 516 * @retval The specified FIFO error flag index.
mbed_official 133:d4dda5c437f0 517 */
mbed_official 133:d4dda5c437f0 518 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
mbed_official 133:d4dda5c437f0 519 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
mbed_official 133:d4dda5c437f0 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
mbed_official 133:d4dda5c437f0 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
mbed_official 133:d4dda5c437f0 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
mbed_official 133:d4dda5c437f0 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
mbed_official 133:d4dda5c437f0 524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
mbed_official 133:d4dda5c437f0 525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
mbed_official 133:d4dda5c437f0 526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
mbed_official 133:d4dda5c437f0 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
mbed_official 133:d4dda5c437f0 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
mbed_official 133:d4dda5c437f0 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
mbed_official 133:d4dda5c437f0 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
mbed_official 133:d4dda5c437f0 531 DMA_FLAG_FEIF3_7)
mbed_official 133:d4dda5c437f0 532
mbed_official 133:d4dda5c437f0 533 /**
mbed_official 133:d4dda5c437f0 534 * @brief Return the current DMA Stream direct mode error flag.
mbed_official 133:d4dda5c437f0 535 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 536 * @retval The specified direct mode error flag index.
mbed_official 133:d4dda5c437f0 537 */
mbed_official 133:d4dda5c437f0 538 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
mbed_official 133:d4dda5c437f0 539 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
mbed_official 133:d4dda5c437f0 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
mbed_official 133:d4dda5c437f0 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
mbed_official 133:d4dda5c437f0 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
mbed_official 133:d4dda5c437f0 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
mbed_official 133:d4dda5c437f0 544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
mbed_official 133:d4dda5c437f0 545 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
mbed_official 133:d4dda5c437f0 546 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
mbed_official 133:d4dda5c437f0 547 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
mbed_official 133:d4dda5c437f0 548 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
mbed_official 133:d4dda5c437f0 549 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
mbed_official 133:d4dda5c437f0 550 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
mbed_official 133:d4dda5c437f0 551 DMA_FLAG_DMEIF3_7)
mbed_official 133:d4dda5c437f0 552
mbed_official 133:d4dda5c437f0 553 /**
mbed_official 133:d4dda5c437f0 554 * @brief Get the DMA Stream pending flags.
mbed_official 133:d4dda5c437f0 555 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 556 * @param __FLAG__: Get the specified flag.
mbed_official 133:d4dda5c437f0 557 * This parameter can be any combination of the following values:
mbed_official 133:d4dda5c437f0 558 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
mbed_official 133:d4dda5c437f0 559 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
mbed_official 133:d4dda5c437f0 560 * @arg DMA_FLAG_TEIFx: Transfer error flag.
mbed_official 133:d4dda5c437f0 561 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
mbed_official 133:d4dda5c437f0 562 * @arg DMA_FLAG_FEIFx: FIFO error flag.
mbed_official 133:d4dda5c437f0 563 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
mbed_official 133:d4dda5c437f0 564 * @retval The state of FLAG (SET or RESET).
mbed_official 133:d4dda5c437f0 565 */
mbed_official 133:d4dda5c437f0 566 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
mbed_official 133:d4dda5c437f0 567 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
mbed_official 133:d4dda5c437f0 568 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
mbed_official 133:d4dda5c437f0 569 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
mbed_official 133:d4dda5c437f0 570
mbed_official 133:d4dda5c437f0 571 /**
mbed_official 133:d4dda5c437f0 572 * @brief Clear the DMA Stream pending flags.
mbed_official 133:d4dda5c437f0 573 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 574 * @param __FLAG__: specifies the flag to clear.
mbed_official 133:d4dda5c437f0 575 * This parameter can be any combination of the following values:
mbed_official 133:d4dda5c437f0 576 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
mbed_official 133:d4dda5c437f0 577 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
mbed_official 133:d4dda5c437f0 578 * @arg DMA_FLAG_TEIFx: Transfer error flag.
mbed_official 133:d4dda5c437f0 579 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
mbed_official 133:d4dda5c437f0 580 * @arg DMA_FLAG_FEIFx: FIFO error flag.
mbed_official 133:d4dda5c437f0 581 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
mbed_official 133:d4dda5c437f0 582 * @retval None
mbed_official 133:d4dda5c437f0 583 */
mbed_official 133:d4dda5c437f0 584 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
mbed_official 133:d4dda5c437f0 585 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR |= (__FLAG__)) :\
mbed_official 133:d4dda5c437f0 586 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR |= (__FLAG__)) :\
mbed_official 133:d4dda5c437f0 587 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR |= (__FLAG__)) : (DMA1->LIFCR |= (__FLAG__)))
mbed_official 133:d4dda5c437f0 588
mbed_official 133:d4dda5c437f0 589 /**
mbed_official 133:d4dda5c437f0 590 * @brief Enable the specified DMA Stream interrupts.
mbed_official 133:d4dda5c437f0 591 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 592 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
mbed_official 133:d4dda5c437f0 593 * This parameter can be any combination of the following values:
mbed_official 133:d4dda5c437f0 594 * @arg DMA_IT_TC: Transfer complete interrupt mask.
mbed_official 133:d4dda5c437f0 595 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
mbed_official 133:d4dda5c437f0 596 * @arg DMA_IT_TE: Transfer error interrupt mask.
mbed_official 133:d4dda5c437f0 597 * @arg DMA_IT_FE: FIFO error interrupt mask.
mbed_official 133:d4dda5c437f0 598 * @arg DMA_IT_DME: Direct mode error interrupt.
mbed_official 133:d4dda5c437f0 599 * @retval None
mbed_official 133:d4dda5c437f0 600 */
mbed_official 133:d4dda5c437f0 601 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
mbed_official 133:d4dda5c437f0 602 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
mbed_official 133:d4dda5c437f0 603
mbed_official 133:d4dda5c437f0 604 /**
mbed_official 133:d4dda5c437f0 605 * @brief Disable the specified DMA Stream interrupts.
mbed_official 133:d4dda5c437f0 606 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 607 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
mbed_official 133:d4dda5c437f0 608 * This parameter can be any combination of the following values:
mbed_official 133:d4dda5c437f0 609 * @arg DMA_IT_TC: Transfer complete interrupt mask.
mbed_official 133:d4dda5c437f0 610 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
mbed_official 133:d4dda5c437f0 611 * @arg DMA_IT_TE: Transfer error interrupt mask.
mbed_official 133:d4dda5c437f0 612 * @arg DMA_IT_FE: FIFO error interrupt mask.
mbed_official 133:d4dda5c437f0 613 * @arg DMA_IT_DME: Direct mode error interrupt.
mbed_official 133:d4dda5c437f0 614 * @retval None
mbed_official 133:d4dda5c437f0 615 */
mbed_official 133:d4dda5c437f0 616 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
mbed_official 133:d4dda5c437f0 617 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
mbed_official 133:d4dda5c437f0 618
mbed_official 133:d4dda5c437f0 619 /**
mbed_official 133:d4dda5c437f0 620 * @brief Check whether the specified DMA Stream interrupt has occurred or not.
mbed_official 133:d4dda5c437f0 621 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 622 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
mbed_official 133:d4dda5c437f0 623 * This parameter can be one of the following values:
mbed_official 133:d4dda5c437f0 624 * @arg DMA_IT_TC: Transfer complete interrupt mask.
mbed_official 133:d4dda5c437f0 625 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
mbed_official 133:d4dda5c437f0 626 * @arg DMA_IT_TE: Transfer error interrupt mask.
mbed_official 133:d4dda5c437f0 627 * @arg DMA_IT_FE: FIFO error interrupt mask.
mbed_official 133:d4dda5c437f0 628 * @arg DMA_IT_DME: Direct mode error interrupt.
mbed_official 133:d4dda5c437f0 629 * @retval The state of DMA_IT.
mbed_official 133:d4dda5c437f0 630 */
mbed_official 133:d4dda5c437f0 631 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
mbed_official 133:d4dda5c437f0 632 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
mbed_official 133:d4dda5c437f0 633 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
mbed_official 133:d4dda5c437f0 634
mbed_official 133:d4dda5c437f0 635 /**
mbed_official 133:d4dda5c437f0 636 * @brief Writes the number of data units to be transferred on the DMA Stream.
mbed_official 133:d4dda5c437f0 637 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 638 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
mbed_official 133:d4dda5c437f0 639 * Number of data items depends only on the Peripheral data format.
mbed_official 133:d4dda5c437f0 640 *
mbed_official 133:d4dda5c437f0 641 * @note If Peripheral data format is Bytes: number of data units is equal
mbed_official 133:d4dda5c437f0 642 * to total number of bytes to be transferred.
mbed_official 133:d4dda5c437f0 643 *
mbed_official 133:d4dda5c437f0 644 * @note If Peripheral data format is Half-Word: number of data units is
mbed_official 133:d4dda5c437f0 645 * equal to total number of bytes to be transferred / 2.
mbed_official 133:d4dda5c437f0 646 *
mbed_official 133:d4dda5c437f0 647 * @note If Peripheral data format is Word: number of data units is equal
mbed_official 133:d4dda5c437f0 648 * to total number of bytes to be transferred / 4.
mbed_official 133:d4dda5c437f0 649 *
mbed_official 133:d4dda5c437f0 650 * @retval The number of remaining data units in the current DMAy Streamx transfer.
mbed_official 133:d4dda5c437f0 651 */
mbed_official 133:d4dda5c437f0 652 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
mbed_official 133:d4dda5c437f0 653
mbed_official 133:d4dda5c437f0 654 /**
mbed_official 133:d4dda5c437f0 655 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
mbed_official 133:d4dda5c437f0 656 * @param __HANDLE__: DMA handle
mbed_official 133:d4dda5c437f0 657 *
mbed_official 133:d4dda5c437f0 658 * @retval The number of remaining data units in the current DMA Stream transfer.
mbed_official 133:d4dda5c437f0 659 */
mbed_official 133:d4dda5c437f0 660 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
mbed_official 133:d4dda5c437f0 661
mbed_official 133:d4dda5c437f0 662
mbed_official 133:d4dda5c437f0 663 /* Include DMA HAL Extension module */
mbed_official 133:d4dda5c437f0 664 #include "stm32f4xx_hal_dma_ex.h"
mbed_official 133:d4dda5c437f0 665
mbed_official 133:d4dda5c437f0 666 /* Exported functions --------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 667
mbed_official 133:d4dda5c437f0 668 /* Initialization and de-initialization functions *****************************/
mbed_official 133:d4dda5c437f0 669 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 670 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 671
mbed_official 133:d4dda5c437f0 672 /* IO operation functions *****************************************************/
mbed_official 133:d4dda5c437f0 673 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
mbed_official 133:d4dda5c437f0 674 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
mbed_official 133:d4dda5c437f0 675 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 676 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
mbed_official 133:d4dda5c437f0 677 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 678
mbed_official 133:d4dda5c437f0 679 /* Peripheral State and Error functions ***************************************/
mbed_official 133:d4dda5c437f0 680 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 681 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
mbed_official 133:d4dda5c437f0 682
mbed_official 133:d4dda5c437f0 683 /**
mbed_official 133:d4dda5c437f0 684 * @}
mbed_official 133:d4dda5c437f0 685 */
mbed_official 133:d4dda5c437f0 686
mbed_official 133:d4dda5c437f0 687 /**
mbed_official 133:d4dda5c437f0 688 * @}
mbed_official 133:d4dda5c437f0 689 */
mbed_official 133:d4dda5c437f0 690
mbed_official 133:d4dda5c437f0 691 #ifdef __cplusplus
mbed_official 133:d4dda5c437f0 692 }
mbed_official 133:d4dda5c437f0 693 #endif
mbed_official 133:d4dda5c437f0 694
mbed_official 133:d4dda5c437f0 695 #endif /* __STM32F4xx_HAL_DMA_H */
mbed_official 133:d4dda5c437f0 696
mbed_official 133:d4dda5c437f0 697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/