mbed-src - mbed w/ spi bug fig

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mbed w/ spi bug fig

targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc.h@242:7074e42da0b2, 2014-06-27 (annotated)

Committer:: mbed_official
Date:: Fri Jun 27 07:30:09 2014 +0100
Revision:: 242:7074e42da0b2
Parent:: 133:d4dda5c437f0

Synchronized with git revision 124ef5e3add9e74a3221347a3fbeea7c8b3cf353



Full URL: https://github.com/mbedmicro/mbed/commit/124ef5e3add9e74a3221347a3fbeea7c8b3cf353/



[DISCO_F407VG] HAL update.

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	133:d4dda5c437f0	1	/**
mbed_official	133:d4dda5c437f0	2	******************************************************************************
mbed_official	133:d4dda5c437f0	3	* @file stm32f4xx_hal_rcc.h
mbed_official	133:d4dda5c437f0	4	* @author MCD Application Team
mbed_official	242:7074e42da0b2	5	* @version V1.1.0RC2
mbed_official	242:7074e42da0b2	6	* @date 14-May-2014
mbed_official	133:d4dda5c437f0	7	* @brief Header file of RCC HAL module.
mbed_official	133:d4dda5c437f0	8	******************************************************************************
mbed_official	133:d4dda5c437f0	9	* @attention
mbed_official	133:d4dda5c437f0	10	*
mbed_official	133:d4dda5c437f0	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	133:d4dda5c437f0	12	*
mbed_official	133:d4dda5c437f0	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	133:d4dda5c437f0	14	* are permitted provided that the following conditions are met:
mbed_official	133:d4dda5c437f0	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	133:d4dda5c437f0	16	* this list of conditions and the following disclaimer.
mbed_official	133:d4dda5c437f0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	133:d4dda5c437f0	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	133:d4dda5c437f0	19	* and/or other materials provided with the distribution.
mbed_official	133:d4dda5c437f0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	133:d4dda5c437f0	21	* may be used to endorse or promote products derived from this software
mbed_official	133:d4dda5c437f0	22	* without specific prior written permission.
mbed_official	133:d4dda5c437f0	23	*
mbed_official	133:d4dda5c437f0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	133:d4dda5c437f0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	133:d4dda5c437f0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	133:d4dda5c437f0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	133:d4dda5c437f0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	133:d4dda5c437f0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	133:d4dda5c437f0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	133:d4dda5c437f0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	133:d4dda5c437f0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	133:d4dda5c437f0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	133:d4dda5c437f0	34	*
mbed_official	133:d4dda5c437f0	35	******************************************************************************
mbed_official	133:d4dda5c437f0	36	*/
mbed_official	133:d4dda5c437f0	37
mbed_official	133:d4dda5c437f0	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	133:d4dda5c437f0	39	#ifndef __STM32F4xx_HAL_RCC_H
mbed_official	133:d4dda5c437f0	40	#define __STM32F4xx_HAL_RCC_H
mbed_official	133:d4dda5c437f0	41
mbed_official	133:d4dda5c437f0	42	#ifdef __cplusplus
mbed_official	133:d4dda5c437f0	43	extern "C" {
mbed_official	133:d4dda5c437f0	44	#endif
mbed_official	133:d4dda5c437f0	45
mbed_official	133:d4dda5c437f0	46	/* Includes ------------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	47	#include "stm32f4xx_hal_def.h"
mbed_official	133:d4dda5c437f0	48
mbed_official	133:d4dda5c437f0	49	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	133:d4dda5c437f0	50	* @{
mbed_official	133:d4dda5c437f0	51	*/
mbed_official	133:d4dda5c437f0	52
mbed_official	133:d4dda5c437f0	53	/** @addtogroup RCC
mbed_official	133:d4dda5c437f0	54	* @{
mbed_official	133:d4dda5c437f0	55	*/
mbed_official	133:d4dda5c437f0	56
mbed_official	133:d4dda5c437f0	57	/* Exported types ------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	58
mbed_official	133:d4dda5c437f0	59	/**
mbed_official	133:d4dda5c437f0	60	* @brief RCC PLL configuration structure definition
mbed_official	133:d4dda5c437f0	61	*/
mbed_official	133:d4dda5c437f0	62	typedef struct
mbed_official	133:d4dda5c437f0	63	{
mbed_official	133:d4dda5c437f0	64	uint32_t PLLState; /*!< The new state of the PLL.
mbed_official	133:d4dda5c437f0	65	This parameter can be a value of @ref RCC_PLL_Config */
mbed_official	133:d4dda5c437f0	66
mbed_official	133:d4dda5c437f0	67	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
mbed_official	133:d4dda5c437f0	68	This parameter must be a value of @ref RCC_PLL_Clock_Source */
mbed_official	133:d4dda5c437f0	69
mbed_official	242:7074e42da0b2	70	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
mbed_official	133:d4dda5c437f0	71	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
mbed_official	133:d4dda5c437f0	72
mbed_official	242:7074e42da0b2	73	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
mbed_official	133:d4dda5c437f0	74	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
mbed_official	133:d4dda5c437f0	75
mbed_official	242:7074e42da0b2	76	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
mbed_official	242:7074e42da0b2	77	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
mbed_official	133:d4dda5c437f0	78
mbed_official	242:7074e42da0b2	79	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
mbed_official	133:d4dda5c437f0	80	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
mbed_official	133:d4dda5c437f0	81
mbed_official	133:d4dda5c437f0	82	}RCC_PLLInitTypeDef;
mbed_official	133:d4dda5c437f0	83
mbed_official	133:d4dda5c437f0	84	/**
mbed_official	133:d4dda5c437f0	85	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
mbed_official	133:d4dda5c437f0	86	*/
mbed_official	133:d4dda5c437f0	87	typedef struct
mbed_official	133:d4dda5c437f0	88	{
mbed_official	133:d4dda5c437f0	89	uint32_t OscillatorType; /*!< The oscillators to be configured.
mbed_official	133:d4dda5c437f0	90	This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official	133:d4dda5c437f0	91
mbed_official	133:d4dda5c437f0	92	uint32_t HSEState; /*!< The new state of the HSE.
mbed_official	133:d4dda5c437f0	93	This parameter can be a value of @ref RCC_HSE_Config */
mbed_official	133:d4dda5c437f0	94
mbed_official	133:d4dda5c437f0	95	uint32_t LSEState; /*!< The new state of the LSE.
mbed_official	133:d4dda5c437f0	96	This parameter can be a value of @ref RCC_LSE_Config */
mbed_official	133:d4dda5c437f0	97
mbed_official	133:d4dda5c437f0	98	uint32_t HSIState; /*!< The new state of the HSI.
mbed_official	133:d4dda5c437f0	99	This parameter can be a value of @ref RCC_HSI_Config */
mbed_official	133:d4dda5c437f0	100
mbed_official	133:d4dda5c437f0	101	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
mbed_official	133:d4dda5c437f0	102	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	133:d4dda5c437f0	103
mbed_official	133:d4dda5c437f0	104	uint32_t LSIState; /*!< The new state of the LSI.
mbed_official	133:d4dda5c437f0	105	This parameter can be a value of @ref RCC_LSI_Config */
mbed_official	133:d4dda5c437f0	106
mbed_official	133:d4dda5c437f0	107	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
mbed_official	133:d4dda5c437f0	108
mbed_official	133:d4dda5c437f0	109	}RCC_OscInitTypeDef;
mbed_official	133:d4dda5c437f0	110
mbed_official	133:d4dda5c437f0	111	/**
mbed_official	133:d4dda5c437f0	112	* @brief RCC System, AHB and APB busses clock configuration structure definition
mbed_official	133:d4dda5c437f0	113	*/
mbed_official	133:d4dda5c437f0	114	typedef struct
mbed_official	133:d4dda5c437f0	115	{
mbed_official	133:d4dda5c437f0	116	uint32_t ClockType; /*!< The clock to be configured.
mbed_official	133:d4dda5c437f0	117	This parameter can be a value of @ref RCC_System_Clock_Type */
mbed_official	133:d4dda5c437f0	118
mbed_official	133:d4dda5c437f0	119	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
mbed_official	133:d4dda5c437f0	120	This parameter can be a value of @ref RCC_System_Clock_Source */
mbed_official	133:d4dda5c437f0	121
mbed_official	133:d4dda5c437f0	122	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
mbed_official	133:d4dda5c437f0	123	This parameter can be a value of @ref RCC_AHB_Clock_Source */
mbed_official	133:d4dda5c437f0	124
mbed_official	133:d4dda5c437f0	125	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	133:d4dda5c437f0	126	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	133:d4dda5c437f0	127
mbed_official	133:d4dda5c437f0	128	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	133:d4dda5c437f0	129	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	133:d4dda5c437f0	130
mbed_official	133:d4dda5c437f0	131	}RCC_ClkInitTypeDef;
mbed_official	133:d4dda5c437f0	132
mbed_official	133:d4dda5c437f0	133	/* Exported constants --------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	134	/** @defgroup RCC_Exported_Constants
mbed_official	133:d4dda5c437f0	135	* @{
mbed_official	133:d4dda5c437f0	136	*/
mbed_official	133:d4dda5c437f0	137
mbed_official	133:d4dda5c437f0	138	/** @defgroup RCC_BitAddress_AliasRegion
mbed_official	133:d4dda5c437f0	139	* @brief RCC registers bit address in the alias region
mbed_official	133:d4dda5c437f0	140	* @{
mbed_official	133:d4dda5c437f0	141	*/
mbed_official	133:d4dda5c437f0	142	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official	133:d4dda5c437f0	143	/* --- CR Register ---*/
mbed_official	133:d4dda5c437f0	144	/* Alias word address of HSION bit */
mbed_official	133:d4dda5c437f0	145	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
mbed_official	133:d4dda5c437f0	146	#define HSION_BitNumber 0x00
mbed_official	133:d4dda5c437f0	147	#define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
mbed_official	133:d4dda5c437f0	148	/* Alias word address of CSSON bit */
mbed_official	133:d4dda5c437f0	149	#define CSSON_BitNumber 0x13
mbed_official	133:d4dda5c437f0	150	#define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
mbed_official	133:d4dda5c437f0	151	/* Alias word address of PLLON bit */
mbed_official	133:d4dda5c437f0	152	#define PLLON_BitNumber 0x18
mbed_official	133:d4dda5c437f0	153	#define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
mbed_official	133:d4dda5c437f0	154	/* Alias word address of PLLI2SON bit */
mbed_official	133:d4dda5c437f0	155	#define PLLI2SON_BitNumber 0x1A
mbed_official	133:d4dda5c437f0	156	#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
mbed_official	133:d4dda5c437f0	157
mbed_official	133:d4dda5c437f0	158	/* --- CFGR Register ---*/
mbed_official	133:d4dda5c437f0	159	/* Alias word address of I2SSRC bit */
mbed_official	133:d4dda5c437f0	160	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
mbed_official	133:d4dda5c437f0	161	#define I2SSRC_BitNumber 0x17
mbed_official	133:d4dda5c437f0	162	#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
mbed_official	133:d4dda5c437f0	163
mbed_official	133:d4dda5c437f0	164	/* --- BDCR Register ---*/
mbed_official	133:d4dda5c437f0	165	/* Alias word address of RTCEN bit */
mbed_official	133:d4dda5c437f0	166	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
mbed_official	133:d4dda5c437f0	167	#define RTCEN_BitNumber 0x0F
mbed_official	133:d4dda5c437f0	168	#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
mbed_official	133:d4dda5c437f0	169	/* Alias word address of BDRST bit */
mbed_official	133:d4dda5c437f0	170	#define BDRST_BitNumber 0x10
mbed_official	133:d4dda5c437f0	171	#define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
mbed_official	133:d4dda5c437f0	172
mbed_official	133:d4dda5c437f0	173	/* --- CSR Register ---*/
mbed_official	133:d4dda5c437f0	174	/* Alias word address of LSION bit */
mbed_official	133:d4dda5c437f0	175	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
mbed_official	133:d4dda5c437f0	176	#define LSION_BitNumber 0x00
mbed_official	133:d4dda5c437f0	177	#define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
mbed_official	133:d4dda5c437f0	178
mbed_official	133:d4dda5c437f0	179	/* CR register byte 3 (Bits[23:16]) base address */
mbed_official	133:d4dda5c437f0	180	#define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
mbed_official	133:d4dda5c437f0	181
mbed_official	133:d4dda5c437f0	182	/* CIR register byte 2 (Bits[15:8]) base address */
mbed_official	133:d4dda5c437f0	183	#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
mbed_official	133:d4dda5c437f0	184
mbed_official	133:d4dda5c437f0	185	/* CIR register byte 3 (Bits[23:16]) base address */
mbed_official	133:d4dda5c437f0	186	#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
mbed_official	133:d4dda5c437f0	187
mbed_official	133:d4dda5c437f0	188	/* BDCR register base address */
mbed_official	133:d4dda5c437f0	189	#define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
mbed_official	133:d4dda5c437f0	190
mbed_official	133:d4dda5c437f0	191
mbed_official	133:d4dda5c437f0	192	#define DBP_TIMEOUT_VALUE ((uint32_t)100)
mbed_official	242:7074e42da0b2	193	#define LSE_TIMEOUT_VALUE ((uint32_t)500)
mbed_official	133:d4dda5c437f0	194	/**
mbed_official	133:d4dda5c437f0	195	* @}
mbed_official	133:d4dda5c437f0	196	*/
mbed_official	133:d4dda5c437f0	197
mbed_official	133:d4dda5c437f0	198	/** @defgroup RCC_Oscillator_Type
mbed_official	133:d4dda5c437f0	199	* @{
mbed_official	133:d4dda5c437f0	200	*/
mbed_official	133:d4dda5c437f0	201	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	202	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	203	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	204	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
mbed_official	133:d4dda5c437f0	205	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
mbed_official	133:d4dda5c437f0	206
mbed_official	133:d4dda5c437f0	207	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
mbed_official	133:d4dda5c437f0	208	/**
mbed_official	133:d4dda5c437f0	209	* @}
mbed_official	133:d4dda5c437f0	210	*/
mbed_official	133:d4dda5c437f0	211
mbed_official	133:d4dda5c437f0	212	/** @defgroup RCC_HSE_Config
mbed_official	133:d4dda5c437f0	213	* @{
mbed_official	133:d4dda5c437f0	214	*/
mbed_official	133:d4dda5c437f0	215	#define RCC_HSE_OFF ((uint8_t)0x00)
mbed_official	133:d4dda5c437f0	216	#define RCC_HSE_ON ((uint8_t)0x01)
mbed_official	133:d4dda5c437f0	217	#define RCC_HSE_BYPASS ((uint8_t)0x05)
mbed_official	133:d4dda5c437f0	218
mbed_official	133:d4dda5c437f0	219	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
mbed_official	133:d4dda5c437f0	220	((HSE) == RCC_HSE_BYPASS))
mbed_official	133:d4dda5c437f0	221	/**
mbed_official	133:d4dda5c437f0	222	* @}
mbed_official	133:d4dda5c437f0	223	*/
mbed_official	133:d4dda5c437f0	224
mbed_official	133:d4dda5c437f0	225	/** @defgroup RCC_LSE_Config
mbed_official	133:d4dda5c437f0	226	* @{
mbed_official	133:d4dda5c437f0	227	*/
mbed_official	133:d4dda5c437f0	228	#define RCC_LSE_OFF ((uint8_t)0x00)
mbed_official	133:d4dda5c437f0	229	#define RCC_LSE_ON ((uint8_t)0x01)
mbed_official	133:d4dda5c437f0	230	#define RCC_LSE_BYPASS ((uint8_t)0x05)
mbed_official	133:d4dda5c437f0	231
mbed_official	133:d4dda5c437f0	232	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
mbed_official	133:d4dda5c437f0	233	((LSE) == RCC_LSE_BYPASS))
mbed_official	133:d4dda5c437f0	234	/**
mbed_official	133:d4dda5c437f0	235	* @}
mbed_official	133:d4dda5c437f0	236	*/
mbed_official	133:d4dda5c437f0	237
mbed_official	133:d4dda5c437f0	238	/** @defgroup RCC_HSI_Config
mbed_official	133:d4dda5c437f0	239	* @{
mbed_official	133:d4dda5c437f0	240	*/
mbed_official	133:d4dda5c437f0	241	#define RCC_HSI_OFF ((uint8_t)0x00)
mbed_official	133:d4dda5c437f0	242	#define RCC_HSI_ON ((uint8_t)0x01)
mbed_official	133:d4dda5c437f0	243
mbed_official	133:d4dda5c437f0	244	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
mbed_official	133:d4dda5c437f0	245	/**
mbed_official	133:d4dda5c437f0	246	* @}
mbed_official	133:d4dda5c437f0	247	*/
mbed_official	133:d4dda5c437f0	248
mbed_official	133:d4dda5c437f0	249	/** @defgroup RCC_LSI_Config
mbed_official	133:d4dda5c437f0	250	* @{
mbed_official	133:d4dda5c437f0	251	*/
mbed_official	133:d4dda5c437f0	252	#define RCC_LSI_OFF ((uint8_t)0x00)
mbed_official	133:d4dda5c437f0	253	#define RCC_LSI_ON ((uint8_t)0x01)
mbed_official	133:d4dda5c437f0	254
mbed_official	133:d4dda5c437f0	255	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
mbed_official	133:d4dda5c437f0	256	/**
mbed_official	133:d4dda5c437f0	257	* @}
mbed_official	133:d4dda5c437f0	258	*/
mbed_official	133:d4dda5c437f0	259
mbed_official	133:d4dda5c437f0	260	/** @defgroup RCC_PLL_Config
mbed_official	133:d4dda5c437f0	261	* @{
mbed_official	133:d4dda5c437f0	262	*/
mbed_official	133:d4dda5c437f0	263	#define RCC_PLL_NONE ((uint8_t)0x00)
mbed_official	133:d4dda5c437f0	264	#define RCC_PLL_OFF ((uint8_t)0x01)
mbed_official	133:d4dda5c437f0	265	#define RCC_PLL_ON ((uint8_t)0x02)
mbed_official	133:d4dda5c437f0	266
mbed_official	133:d4dda5c437f0	267	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
mbed_official	133:d4dda5c437f0	268	/**
mbed_official	133:d4dda5c437f0	269	* @}
mbed_official	133:d4dda5c437f0	270	*/
mbed_official	133:d4dda5c437f0	271
mbed_official	133:d4dda5c437f0	272	/** @defgroup RCC_PLLP_Clock_Divider
mbed_official	133:d4dda5c437f0	273	* @{
mbed_official	133:d4dda5c437f0	274	*/
mbed_official	133:d4dda5c437f0	275	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	276	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
mbed_official	133:d4dda5c437f0	277	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
mbed_official	133:d4dda5c437f0	278	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
mbed_official	133:d4dda5c437f0	279	/**
mbed_official	133:d4dda5c437f0	280	* @}
mbed_official	133:d4dda5c437f0	281	*/
mbed_official	133:d4dda5c437f0	282
mbed_official	133:d4dda5c437f0	283	/** @defgroup RCC_PLL_Clock_Source
mbed_official	133:d4dda5c437f0	284	* @{
mbed_official	133:d4dda5c437f0	285	*/
mbed_official	133:d4dda5c437f0	286	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
mbed_official	133:d4dda5c437f0	287	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
mbed_official	133:d4dda5c437f0	288
mbed_official	133:d4dda5c437f0	289	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	133:d4dda5c437f0	290	((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official	133:d4dda5c437f0	291	#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
mbed_official	133:d4dda5c437f0	292	#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
mbed_official	133:d4dda5c437f0	293	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) \|\| ((VALUE) == 4) \|\| ((VALUE) == 6) \|\| ((VALUE) == 8))
mbed_official	133:d4dda5c437f0	294	#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
mbed_official	133:d4dda5c437f0	295
mbed_official	133:d4dda5c437f0	296	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
mbed_official	133:d4dda5c437f0	297	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
mbed_official	133:d4dda5c437f0	298
mbed_official	133:d4dda5c437f0	299	/**
mbed_official	133:d4dda5c437f0	300	* @}
mbed_official	133:d4dda5c437f0	301	*/
mbed_official	133:d4dda5c437f0	302
mbed_official	133:d4dda5c437f0	303	/** @defgroup RCC_System_Clock_Type
mbed_official	133:d4dda5c437f0	304	* @{
mbed_official	133:d4dda5c437f0	305	*/
mbed_official	133:d4dda5c437f0	306	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	307	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	308	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
mbed_official	133:d4dda5c437f0	309	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
mbed_official	133:d4dda5c437f0	310
mbed_official	133:d4dda5c437f0	311	#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
mbed_official	133:d4dda5c437f0	312	/**
mbed_official	133:d4dda5c437f0	313	* @}
mbed_official	133:d4dda5c437f0	314	*/
mbed_official	133:d4dda5c437f0	315
mbed_official	133:d4dda5c437f0	316	/** @defgroup RCC_System_Clock_Source
mbed_official	133:d4dda5c437f0	317	* @{
mbed_official	133:d4dda5c437f0	318	*/
mbed_official	133:d4dda5c437f0	319	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
mbed_official	133:d4dda5c437f0	320	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
mbed_official	133:d4dda5c437f0	321	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
mbed_official	133:d4dda5c437f0	322
mbed_official	133:d4dda5c437f0	323	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	133:d4dda5c437f0	324	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	133:d4dda5c437f0	325	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official	133:d4dda5c437f0	326	/**
mbed_official	133:d4dda5c437f0	327	* @}
mbed_official	133:d4dda5c437f0	328	*/
mbed_official	133:d4dda5c437f0	329
mbed_official	133:d4dda5c437f0	330	/** @defgroup RCC_AHB_Clock_Source
mbed_official	133:d4dda5c437f0	331	* @{
mbed_official	133:d4dda5c437f0	332	*/
mbed_official	133:d4dda5c437f0	333	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
mbed_official	133:d4dda5c437f0	334	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
mbed_official	133:d4dda5c437f0	335	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
mbed_official	133:d4dda5c437f0	336	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
mbed_official	133:d4dda5c437f0	337	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
mbed_official	133:d4dda5c437f0	338	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
mbed_official	133:d4dda5c437f0	339	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
mbed_official	133:d4dda5c437f0	340	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
mbed_official	133:d4dda5c437f0	341	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
mbed_official	133:d4dda5c437f0	342
mbed_official	133:d4dda5c437f0	343	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
mbed_official	133:d4dda5c437f0	344	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
mbed_official	133:d4dda5c437f0	345	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
mbed_official	133:d4dda5c437f0	346	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
mbed_official	133:d4dda5c437f0	347	((HCLK) == RCC_SYSCLK_DIV512))
mbed_official	133:d4dda5c437f0	348	/**
mbed_official	133:d4dda5c437f0	349	* @}
mbed_official	133:d4dda5c437f0	350	*/
mbed_official	133:d4dda5c437f0	351
mbed_official	133:d4dda5c437f0	352	/** @defgroup RCC_APB1_APB2_Clock_Source
mbed_official	133:d4dda5c437f0	353	* @{
mbed_official	133:d4dda5c437f0	354	*/
mbed_official	133:d4dda5c437f0	355	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
mbed_official	133:d4dda5c437f0	356	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
mbed_official	133:d4dda5c437f0	357	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
mbed_official	133:d4dda5c437f0	358	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
mbed_official	133:d4dda5c437f0	359	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
mbed_official	133:d4dda5c437f0	360
mbed_official	133:d4dda5c437f0	361	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
mbed_official	133:d4dda5c437f0	362	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
mbed_official	133:d4dda5c437f0	363	((PCLK) == RCC_HCLK_DIV16))
mbed_official	133:d4dda5c437f0	364	/**
mbed_official	133:d4dda5c437f0	365	* @}
mbed_official	133:d4dda5c437f0	366	*/
mbed_official	133:d4dda5c437f0	367
mbed_official	133:d4dda5c437f0	368	/** @defgroup RCC_RTC_Clock_Source
mbed_official	133:d4dda5c437f0	369	* @{
mbed_official	133:d4dda5c437f0	370	*/
mbed_official	133:d4dda5c437f0	371	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
mbed_official	133:d4dda5c437f0	372	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
mbed_official	133:d4dda5c437f0	373	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
mbed_official	133:d4dda5c437f0	374	#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
mbed_official	133:d4dda5c437f0	375	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
mbed_official	133:d4dda5c437f0	376	#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
mbed_official	133:d4dda5c437f0	377	#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
mbed_official	133:d4dda5c437f0	378	#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
mbed_official	133:d4dda5c437f0	379	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
mbed_official	133:d4dda5c437f0	380	#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
mbed_official	133:d4dda5c437f0	381	#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
mbed_official	133:d4dda5c437f0	382	#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
mbed_official	133:d4dda5c437f0	383	#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
mbed_official	133:d4dda5c437f0	384	#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
mbed_official	133:d4dda5c437f0	385	#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
mbed_official	133:d4dda5c437f0	386	#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
mbed_official	133:d4dda5c437f0	387	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
mbed_official	133:d4dda5c437f0	388	#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
mbed_official	133:d4dda5c437f0	389	#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
mbed_official	133:d4dda5c437f0	390	#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
mbed_official	133:d4dda5c437f0	391	#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
mbed_official	133:d4dda5c437f0	392	#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
mbed_official	133:d4dda5c437f0	393	#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
mbed_official	133:d4dda5c437f0	394	#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
mbed_official	133:d4dda5c437f0	395	#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
mbed_official	133:d4dda5c437f0	396	#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
mbed_official	133:d4dda5c437f0	397	#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
mbed_official	133:d4dda5c437f0	398	#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
mbed_official	133:d4dda5c437f0	399	#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
mbed_official	133:d4dda5c437f0	400	#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
mbed_official	133:d4dda5c437f0	401	#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
mbed_official	133:d4dda5c437f0	402	#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
mbed_official	133:d4dda5c437f0	403	/**
mbed_official	133:d4dda5c437f0	404	* @}
mbed_official	133:d4dda5c437f0	405	*/
mbed_official	133:d4dda5c437f0	406
mbed_official	133:d4dda5c437f0	407	/** @defgroup RCC_I2S_Clock_Source
mbed_official	133:d4dda5c437f0	408	* @{
mbed_official	133:d4dda5c437f0	409	*/
mbed_official	133:d4dda5c437f0	410	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	411	#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	412	/**
mbed_official	133:d4dda5c437f0	413	* @}
mbed_official	133:d4dda5c437f0	414	*/
mbed_official	133:d4dda5c437f0	415
mbed_official	133:d4dda5c437f0	416	/** @defgroup RCC_MCO_Index
mbed_official	133:d4dda5c437f0	417	* @{
mbed_official	133:d4dda5c437f0	418	*/
mbed_official	133:d4dda5c437f0	419	#define RCC_MCO1 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	420	#define RCC_MCO2 ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	421
mbed_official	133:d4dda5c437f0	422	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
mbed_official	133:d4dda5c437f0	423	/**
mbed_official	133:d4dda5c437f0	424	* @}
mbed_official	133:d4dda5c437f0	425	*/
mbed_official	133:d4dda5c437f0	426
mbed_official	133:d4dda5c437f0	427	/** @defgroup RCC_MCO1_Clock_Source
mbed_official	133:d4dda5c437f0	428	* @{
mbed_official	133:d4dda5c437f0	429	*/
mbed_official	133:d4dda5c437f0	430	#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	431	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
mbed_official	133:d4dda5c437f0	432	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
mbed_official	133:d4dda5c437f0	433	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
mbed_official	133:d4dda5c437f0	434
mbed_official	133:d4dda5c437f0	435	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
mbed_official	133:d4dda5c437f0	436	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
mbed_official	133:d4dda5c437f0	437	/**
mbed_official	133:d4dda5c437f0	438	* @}
mbed_official	133:d4dda5c437f0	439	*/
mbed_official	133:d4dda5c437f0	440
mbed_official	133:d4dda5c437f0	441	/** @defgroup RCC_MCO2_Clock_Source
mbed_official	133:d4dda5c437f0	442	* @{
mbed_official	133:d4dda5c437f0	443	*/
mbed_official	133:d4dda5c437f0	444	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	445	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
mbed_official	133:d4dda5c437f0	446	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
mbed_official	133:d4dda5c437f0	447	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
mbed_official	133:d4dda5c437f0	448
mbed_official	133:d4dda5c437f0	449	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
mbed_official	133:d4dda5c437f0	450	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
mbed_official	133:d4dda5c437f0	451	/**
mbed_official	133:d4dda5c437f0	452	* @}
mbed_official	133:d4dda5c437f0	453	*/
mbed_official	133:d4dda5c437f0	454
mbed_official	133:d4dda5c437f0	455	/** @defgroup RCC_MCOx_Clock_Prescaler
mbed_official	133:d4dda5c437f0	456	* @{
mbed_official	133:d4dda5c437f0	457	*/
mbed_official	133:d4dda5c437f0	458	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	459	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
mbed_official	133:d4dda5c437f0	460	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
mbed_official	133:d4dda5c437f0	461	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
mbed_official	133:d4dda5c437f0	462	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
mbed_official	133:d4dda5c437f0	463
mbed_official	133:d4dda5c437f0	464	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
mbed_official	133:d4dda5c437f0	465	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
mbed_official	133:d4dda5c437f0	466	((DIV) == RCC_MCODIV_5))
mbed_official	133:d4dda5c437f0	467	/**
mbed_official	133:d4dda5c437f0	468	* @}
mbed_official	133:d4dda5c437f0	469	*/
mbed_official	133:d4dda5c437f0	470
mbed_official	133:d4dda5c437f0	471	/** @defgroup RCC_Interrupt
mbed_official	133:d4dda5c437f0	472	* @{
mbed_official	133:d4dda5c437f0	473	*/
mbed_official	133:d4dda5c437f0	474	#define RCC_IT_LSIRDY ((uint8_t)0x01)
mbed_official	133:d4dda5c437f0	475	#define RCC_IT_LSERDY ((uint8_t)0x02)
mbed_official	133:d4dda5c437f0	476	#define RCC_IT_HSIRDY ((uint8_t)0x04)
mbed_official	133:d4dda5c437f0	477	#define RCC_IT_HSERDY ((uint8_t)0x08)
mbed_official	133:d4dda5c437f0	478	#define RCC_IT_PLLRDY ((uint8_t)0x10)
mbed_official	133:d4dda5c437f0	479	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
mbed_official	133:d4dda5c437f0	480	#define RCC_IT_CSS ((uint8_t)0x80)
mbed_official	133:d4dda5c437f0	481	/**
mbed_official	133:d4dda5c437f0	482	* @}
mbed_official	133:d4dda5c437f0	483	*/
mbed_official	133:d4dda5c437f0	484
mbed_official	133:d4dda5c437f0	485	/** @defgroup RCC_Flag
mbed_official	133:d4dda5c437f0	486	* Elements values convention: 0XXYYYYYb
mbed_official	133:d4dda5c437f0	487	* - YYYYY : Flag position in the register
mbed_official	133:d4dda5c437f0	488	* - 0XX : Register index
mbed_official	133:d4dda5c437f0	489	* - 01: CR register
mbed_official	133:d4dda5c437f0	490	* - 10: BDCR register
mbed_official	133:d4dda5c437f0	491	* - 11: CSR register
mbed_official	133:d4dda5c437f0	492	* @{
mbed_official	133:d4dda5c437f0	493	*/
mbed_official	133:d4dda5c437f0	494	/* Flags in the CR register */
mbed_official	133:d4dda5c437f0	495	#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
mbed_official	133:d4dda5c437f0	496	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
mbed_official	133:d4dda5c437f0	497	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
mbed_official	133:d4dda5c437f0	498	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
mbed_official	133:d4dda5c437f0	499
mbed_official	133:d4dda5c437f0	500	/* Flags in the BDCR register */
mbed_official	133:d4dda5c437f0	501	#define RCC_FLAG_LSERDY ((uint8_t)0x41)
mbed_official	133:d4dda5c437f0	502
mbed_official	133:d4dda5c437f0	503	/* Flags in the CSR register */
mbed_official	133:d4dda5c437f0	504	#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
mbed_official	133:d4dda5c437f0	505	#define RCC_FLAG_BORRST ((uint8_t)0x79)
mbed_official	133:d4dda5c437f0	506	#define RCC_FLAG_PINRST ((uint8_t)0x7A)
mbed_official	133:d4dda5c437f0	507	#define RCC_FLAG_PORRST ((uint8_t)0x7B)
mbed_official	133:d4dda5c437f0	508	#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
mbed_official	133:d4dda5c437f0	509	#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
mbed_official	133:d4dda5c437f0	510	#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
mbed_official	133:d4dda5c437f0	511	#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
mbed_official	133:d4dda5c437f0	512
mbed_official	133:d4dda5c437f0	513	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
mbed_official	133:d4dda5c437f0	514	/**
mbed_official	133:d4dda5c437f0	515	* @}
mbed_official	133:d4dda5c437f0	516	*/
mbed_official	133:d4dda5c437f0	517
mbed_official	133:d4dda5c437f0	518	/**
mbed_official	133:d4dda5c437f0	519	* @}
mbed_official	133:d4dda5c437f0	520	*/
mbed_official	133:d4dda5c437f0	521	/* Exported macro ------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	522
mbed_official	133:d4dda5c437f0	523	/** @brief Enable or disable the AHB1 peripheral clock.
mbed_official	133:d4dda5c437f0	524	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	133:d4dda5c437f0	525	* is disabled and the application software has to enable this clock before
mbed_official	133:d4dda5c437f0	526	* using it.
mbed_official	133:d4dda5c437f0	527	*/
mbed_official	133:d4dda5c437f0	528	#define __GPIOA_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOAEN))
mbed_official	133:d4dda5c437f0	529	#define __GPIOB_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOBEN))
mbed_official	133:d4dda5c437f0	530	#define __GPIOC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOCEN))
mbed_official	133:d4dda5c437f0	531	#define __GPIOD_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIODEN))
mbed_official	133:d4dda5c437f0	532	#define __GPIOE_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOEEN))
mbed_official	133:d4dda5c437f0	533	#define __GPIOH_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOHEN))
mbed_official	133:d4dda5c437f0	534	#define __CRC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_CRCEN))
mbed_official	133:d4dda5c437f0	535	#define __BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_BKPSRAMEN))
mbed_official	133:d4dda5c437f0	536	#define __CCMDATARAMEN_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_CCMDATARAMEN))
mbed_official	133:d4dda5c437f0	537	#define __DMA1_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_DMA1EN))
mbed_official	133:d4dda5c437f0	538	#define __DMA2_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_DMA2EN))
mbed_official	133:d4dda5c437f0	539
mbed_official	133:d4dda5c437f0	540	#define __GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
mbed_official	133:d4dda5c437f0	541	#define __GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
mbed_official	133:d4dda5c437f0	542	#define __GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
mbed_official	133:d4dda5c437f0	543	#define __GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
mbed_official	133:d4dda5c437f0	544	#define __GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
mbed_official	133:d4dda5c437f0	545	#define __GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
mbed_official	133:d4dda5c437f0	546	#define __CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
mbed_official	133:d4dda5c437f0	547	#define __BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
mbed_official	133:d4dda5c437f0	548	#define __CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
mbed_official	133:d4dda5c437f0	549	#define __DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
mbed_official	133:d4dda5c437f0	550	#define __DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
mbed_official	133:d4dda5c437f0	551
mbed_official	133:d4dda5c437f0	552	/** @brief Enable or disable the AHB2 peripheral clock.
mbed_official	133:d4dda5c437f0	553	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	133:d4dda5c437f0	554	* is disabled and the application software has to enable this clock before
mbed_official	133:d4dda5c437f0	555	* using it.
mbed_official	133:d4dda5c437f0	556	*/
mbed_official	133:d4dda5c437f0	557	#define __USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
mbed_official	133:d4dda5c437f0	558	__SYSCFG_CLK_ENABLE();\
mbed_official	133:d4dda5c437f0	559	}while(0)
mbed_official	133:d4dda5c437f0	560
mbed_official	133:d4dda5c437f0	561
mbed_official	133:d4dda5c437f0	562	#define __USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
mbed_official	133:d4dda5c437f0	563	__SYSCFG_CLK_DISABLE();\
mbed_official	133:d4dda5c437f0	564	}while(0)
mbed_official	133:d4dda5c437f0	565
mbed_official	133:d4dda5c437f0	566	#define __RNG_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_RNGEN))
mbed_official	133:d4dda5c437f0	567	#define __RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
mbed_official	133:d4dda5c437f0	568	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	133:d4dda5c437f0	569	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	133:d4dda5c437f0	570	* is disabled and the application software has to enable this clock before
mbed_official	133:d4dda5c437f0	571	* using it.
mbed_official	133:d4dda5c437f0	572	*/
mbed_official	133:d4dda5c437f0	573	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
mbed_official	133:d4dda5c437f0	574	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
mbed_official	133:d4dda5c437f0	575	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
mbed_official	133:d4dda5c437f0	576	#define __TIM5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM5EN))
mbed_official	133:d4dda5c437f0	577	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
mbed_official	133:d4dda5c437f0	578	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
mbed_official	133:d4dda5c437f0	579	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
mbed_official	133:d4dda5c437f0	580	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
mbed_official	133:d4dda5c437f0	581	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
mbed_official	133:d4dda5c437f0	582	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
mbed_official	133:d4dda5c437f0	583	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
mbed_official	133:d4dda5c437f0	584	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
mbed_official	133:d4dda5c437f0	585
mbed_official	133:d4dda5c437f0	586	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
mbed_official	133:d4dda5c437f0	587	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official	133:d4dda5c437f0	588	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
mbed_official	133:d4dda5c437f0	589	#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
mbed_official	133:d4dda5c437f0	590	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
mbed_official	133:d4dda5c437f0	591	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	133:d4dda5c437f0	592	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
mbed_official	133:d4dda5c437f0	593	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
mbed_official	133:d4dda5c437f0	594	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
mbed_official	133:d4dda5c437f0	595	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	133:d4dda5c437f0	596	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
mbed_official	133:d4dda5c437f0	597	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
mbed_official	133:d4dda5c437f0	598
mbed_official	133:d4dda5c437f0	599	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	133:d4dda5c437f0	600	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	133:d4dda5c437f0	601	* is disabled and the application software has to enable this clock before
mbed_official	133:d4dda5c437f0	602	* using it.
mbed_official	133:d4dda5c437f0	603	*/
mbed_official	133:d4dda5c437f0	604	#define __TIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM1EN))
mbed_official	133:d4dda5c437f0	605	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
mbed_official	133:d4dda5c437f0	606	#define __USART6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART6EN))
mbed_official	133:d4dda5c437f0	607	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
mbed_official	133:d4dda5c437f0	608	#define __SDIO_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDIOEN))
mbed_official	133:d4dda5c437f0	609	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
mbed_official	133:d4dda5c437f0	610	#define __SPI4_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI4EN))
mbed_official	133:d4dda5c437f0	611	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
mbed_official	133:d4dda5c437f0	612	#define __TIM9_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM9EN))
mbed_official	133:d4dda5c437f0	613	#define __TIM10_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM10EN))
mbed_official	133:d4dda5c437f0	614	#define __TIM11_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM11EN))
mbed_official	133:d4dda5c437f0	615
mbed_official	133:d4dda5c437f0	616	#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
mbed_official	133:d4dda5c437f0	617	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
mbed_official	133:d4dda5c437f0	618	#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
mbed_official	133:d4dda5c437f0	619	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
mbed_official	133:d4dda5c437f0	620	#define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
mbed_official	133:d4dda5c437f0	621	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official	133:d4dda5c437f0	622	#define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
mbed_official	133:d4dda5c437f0	623	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
mbed_official	133:d4dda5c437f0	624	#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
mbed_official	133:d4dda5c437f0	625	#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
mbed_official	133:d4dda5c437f0	626	#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
mbed_official	133:d4dda5c437f0	627
mbed_official	133:d4dda5c437f0	628	/** @brief Force or release AHB1 peripheral reset.
mbed_official	133:d4dda5c437f0	629	*/
mbed_official	133:d4dda5c437f0	630	#define __AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
mbed_official	133:d4dda5c437f0	631	#define __GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
mbed_official	133:d4dda5c437f0	632	#define __GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
mbed_official	133:d4dda5c437f0	633	#define __GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
mbed_official	133:d4dda5c437f0	634	#define __GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
mbed_official	133:d4dda5c437f0	635	#define __GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
mbed_official	133:d4dda5c437f0	636	#define __GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
mbed_official	133:d4dda5c437f0	637	#define __CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
mbed_official	133:d4dda5c437f0	638	#define __DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
mbed_official	133:d4dda5c437f0	639	#define __DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
mbed_official	133:d4dda5c437f0	640
mbed_official	133:d4dda5c437f0	641	#define __AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
mbed_official	133:d4dda5c437f0	642	#define __GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
mbed_official	133:d4dda5c437f0	643	#define __GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
mbed_official	133:d4dda5c437f0	644	#define __GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
mbed_official	133:d4dda5c437f0	645	#define __GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
mbed_official	133:d4dda5c437f0	646	#define __GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
mbed_official	133:d4dda5c437f0	647	#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
mbed_official	133:d4dda5c437f0	648	#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
mbed_official	133:d4dda5c437f0	649	#define __GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
mbed_official	133:d4dda5c437f0	650	#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
mbed_official	133:d4dda5c437f0	651	#define __CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
mbed_official	133:d4dda5c437f0	652	#define __DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
mbed_official	133:d4dda5c437f0	653	#define __DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
mbed_official	133:d4dda5c437f0	654
mbed_official	133:d4dda5c437f0	655	/** @brief Force or release AHB2 peripheral reset.
mbed_official	133:d4dda5c437f0	656	*/
mbed_official	133:d4dda5c437f0	657	#define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
mbed_official	133:d4dda5c437f0	658	#define __OTGFS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
mbed_official	133:d4dda5c437f0	659
mbed_official	133:d4dda5c437f0	660	#define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
mbed_official	133:d4dda5c437f0	661	#define __OTGFS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
mbed_official	133:d4dda5c437f0	662
mbed_official	133:d4dda5c437f0	663	#define __RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
mbed_official	133:d4dda5c437f0	664	#define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
mbed_official	133:d4dda5c437f0	665
mbed_official	133:d4dda5c437f0	666	/** @brief Force or release APB1 peripheral reset.
mbed_official	133:d4dda5c437f0	667	*/
mbed_official	133:d4dda5c437f0	668	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
mbed_official	133:d4dda5c437f0	669	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
mbed_official	133:d4dda5c437f0	670	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	133:d4dda5c437f0	671	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
mbed_official	133:d4dda5c437f0	672	#define __TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
mbed_official	133:d4dda5c437f0	673	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
mbed_official	133:d4dda5c437f0	674	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	133:d4dda5c437f0	675	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
mbed_official	133:d4dda5c437f0	676	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
mbed_official	133:d4dda5c437f0	677	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
mbed_official	133:d4dda5c437f0	678	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	133:d4dda5c437f0	679	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
mbed_official	133:d4dda5c437f0	680	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
mbed_official	133:d4dda5c437f0	681
mbed_official	133:d4dda5c437f0	682	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
mbed_official	133:d4dda5c437f0	683	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
mbed_official	133:d4dda5c437f0	684	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official	133:d4dda5c437f0	685	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
mbed_official	133:d4dda5c437f0	686	#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
mbed_official	133:d4dda5c437f0	687	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
mbed_official	133:d4dda5c437f0	688	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	133:d4dda5c437f0	689	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
mbed_official	133:d4dda5c437f0	690	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
mbed_official	133:d4dda5c437f0	691	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
mbed_official	133:d4dda5c437f0	692	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	133:d4dda5c437f0	693	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
mbed_official	133:d4dda5c437f0	694	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
mbed_official	133:d4dda5c437f0	695
mbed_official	133:d4dda5c437f0	696	/** @brief Force or release APB2 peripheral reset.
mbed_official	133:d4dda5c437f0	697	*/
mbed_official	133:d4dda5c437f0	698	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
mbed_official	133:d4dda5c437f0	699	#define __TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
mbed_official	133:d4dda5c437f0	700	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
mbed_official	133:d4dda5c437f0	701	#define __USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
mbed_official	133:d4dda5c437f0	702	#define __ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
mbed_official	133:d4dda5c437f0	703	#define __SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
mbed_official	133:d4dda5c437f0	704	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	133:d4dda5c437f0	705	#define __SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
mbed_official	133:d4dda5c437f0	706	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
mbed_official	133:d4dda5c437f0	707	#define __TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
mbed_official	133:d4dda5c437f0	708	#define __TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
mbed_official	133:d4dda5c437f0	709	#define __TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
mbed_official	133:d4dda5c437f0	710
mbed_official	133:d4dda5c437f0	711	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
mbed_official	133:d4dda5c437f0	712	#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
mbed_official	133:d4dda5c437f0	713	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
mbed_official	133:d4dda5c437f0	714	#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
mbed_official	133:d4dda5c437f0	715	#define __ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
mbed_official	133:d4dda5c437f0	716	#define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
mbed_official	133:d4dda5c437f0	717	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official	133:d4dda5c437f0	718	#define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
mbed_official	133:d4dda5c437f0	719	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
mbed_official	133:d4dda5c437f0	720	#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
mbed_official	133:d4dda5c437f0	721	#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
mbed_official	133:d4dda5c437f0	722	#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
mbed_official	133:d4dda5c437f0	723
mbed_official	133:d4dda5c437f0	724	/** @brief Force or release AHB3 peripheral reset.
mbed_official	133:d4dda5c437f0	725	*/
mbed_official	133:d4dda5c437f0	726	#define __AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
mbed_official	133:d4dda5c437f0	727	#define __AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
mbed_official	133:d4dda5c437f0	728
mbed_official	133:d4dda5c437f0	729	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	133:d4dda5c437f0	730	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	133:d4dda5c437f0	731	* power consumption.
mbed_official	133:d4dda5c437f0	732	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	133:d4dda5c437f0	733	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	133:d4dda5c437f0	734	*/
mbed_official	133:d4dda5c437f0	735	#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
mbed_official	133:d4dda5c437f0	736	#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
mbed_official	133:d4dda5c437f0	737	#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
mbed_official	133:d4dda5c437f0	738	#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
mbed_official	133:d4dda5c437f0	739	#define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
mbed_official	133:d4dda5c437f0	740	#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
mbed_official	133:d4dda5c437f0	741	#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
mbed_official	133:d4dda5c437f0	742	#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
mbed_official	133:d4dda5c437f0	743	#define __SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
mbed_official	133:d4dda5c437f0	744	#define __BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
mbed_official	133:d4dda5c437f0	745	#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
mbed_official	133:d4dda5c437f0	746	#define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
mbed_official	133:d4dda5c437f0	747
mbed_official	133:d4dda5c437f0	748	#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
mbed_official	133:d4dda5c437f0	749	#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
mbed_official	133:d4dda5c437f0	750	#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
mbed_official	133:d4dda5c437f0	751	#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
mbed_official	133:d4dda5c437f0	752	#define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
mbed_official	133:d4dda5c437f0	753	#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
mbed_official	133:d4dda5c437f0	754	#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
mbed_official	133:d4dda5c437f0	755	#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
mbed_official	133:d4dda5c437f0	756	#define __SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
mbed_official	133:d4dda5c437f0	757	#define __BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
mbed_official	133:d4dda5c437f0	758	#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
mbed_official	133:d4dda5c437f0	759	#define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
mbed_official	133:d4dda5c437f0	760
mbed_official	133:d4dda5c437f0	761	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	133:d4dda5c437f0	762	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	133:d4dda5c437f0	763	* power consumption.
mbed_official	133:d4dda5c437f0	764	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	133:d4dda5c437f0	765	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	133:d4dda5c437f0	766	*/
mbed_official	133:d4dda5c437f0	767	#define __OTGFS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
mbed_official	133:d4dda5c437f0	768
mbed_official	133:d4dda5c437f0	769	#define __OTGFS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
mbed_official	133:d4dda5c437f0	770
mbed_official	133:d4dda5c437f0	771	#define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
mbed_official	133:d4dda5c437f0	772	#define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
mbed_official	133:d4dda5c437f0	773
mbed_official	133:d4dda5c437f0	774	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	133:d4dda5c437f0	775	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	133:d4dda5c437f0	776	* power consumption.
mbed_official	133:d4dda5c437f0	777	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	133:d4dda5c437f0	778	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	133:d4dda5c437f0	779	*/
mbed_official	133:d4dda5c437f0	780	#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
mbed_official	133:d4dda5c437f0	781	#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
mbed_official	133:d4dda5c437f0	782	#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
mbed_official	133:d4dda5c437f0	783	#define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
mbed_official	133:d4dda5c437f0	784	#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
mbed_official	133:d4dda5c437f0	785	#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
mbed_official	133:d4dda5c437f0	786	#define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
mbed_official	133:d4dda5c437f0	787	#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
mbed_official	133:d4dda5c437f0	788	#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
mbed_official	133:d4dda5c437f0	789	#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
mbed_official	133:d4dda5c437f0	790	#define __I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
mbed_official	133:d4dda5c437f0	791	#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
mbed_official	133:d4dda5c437f0	792
mbed_official	133:d4dda5c437f0	793	#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
mbed_official	133:d4dda5c437f0	794	#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
mbed_official	133:d4dda5c437f0	795	#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
mbed_official	133:d4dda5c437f0	796	#define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
mbed_official	133:d4dda5c437f0	797	#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
mbed_official	133:d4dda5c437f0	798	#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
mbed_official	133:d4dda5c437f0	799	#define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
mbed_official	133:d4dda5c437f0	800	#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
mbed_official	133:d4dda5c437f0	801	#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
mbed_official	133:d4dda5c437f0	802	#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
mbed_official	133:d4dda5c437f0	803	#define __I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
mbed_official	133:d4dda5c437f0	804	#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
mbed_official	133:d4dda5c437f0	805
mbed_official	133:d4dda5c437f0	806	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	133:d4dda5c437f0	807	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	133:d4dda5c437f0	808	* power consumption.
mbed_official	133:d4dda5c437f0	809	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	133:d4dda5c437f0	810	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	133:d4dda5c437f0	811	*/
mbed_official	133:d4dda5c437f0	812	#define __TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
mbed_official	133:d4dda5c437f0	813	#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
mbed_official	133:d4dda5c437f0	814	#define __USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
mbed_official	133:d4dda5c437f0	815	#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
mbed_official	133:d4dda5c437f0	816	#define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
mbed_official	133:d4dda5c437f0	817	#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
mbed_official	133:d4dda5c437f0	818	#define __SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
mbed_official	133:d4dda5c437f0	819	#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
mbed_official	133:d4dda5c437f0	820	#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
mbed_official	133:d4dda5c437f0	821	#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
mbed_official	133:d4dda5c437f0	822	#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
mbed_official	133:d4dda5c437f0	823
mbed_official	133:d4dda5c437f0	824	#define __TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
mbed_official	133:d4dda5c437f0	825	#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
mbed_official	133:d4dda5c437f0	826	#define __USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
mbed_official	133:d4dda5c437f0	827	#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
mbed_official	133:d4dda5c437f0	828	#define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
mbed_official	133:d4dda5c437f0	829	#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
mbed_official	133:d4dda5c437f0	830	#define __SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
mbed_official	133:d4dda5c437f0	831	#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
mbed_official	133:d4dda5c437f0	832	#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
mbed_official	133:d4dda5c437f0	833	#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
mbed_official	133:d4dda5c437f0	834	#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
mbed_official	133:d4dda5c437f0	835
mbed_official	133:d4dda5c437f0	836	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	133:d4dda5c437f0	837	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	133:d4dda5c437f0	838	* It is used (enabled by hardware) as system clock source after startup
mbed_official	133:d4dda5c437f0	839	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
mbed_official	133:d4dda5c437f0	840	* of the HSE used directly or indirectly as system clock (if the Clock
mbed_official	133:d4dda5c437f0	841	* Security System CSS is enabled).
mbed_official	133:d4dda5c437f0	842	* @note HSI can not be stopped if it is used as system clock source. In this case,
mbed_official	133:d4dda5c437f0	843	* you have to select another source of the system clock then stop the HSI.
mbed_official	133:d4dda5c437f0	844	* @note After enabling the HSI, the application software should wait on HSIRDY
mbed_official	133:d4dda5c437f0	845	* flag to be set indicating that HSI clock is stable and can be used as
mbed_official	133:d4dda5c437f0	846	* system clock source.
mbed_official	133:d4dda5c437f0	847	* This parameter can be: ENABLE or DISABLE.
mbed_official	133:d4dda5c437f0	848	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	133:d4dda5c437f0	849	* clock cycles.
mbed_official	133:d4dda5c437f0	850	*/
mbed_official	133:d4dda5c437f0	851	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) CR_HSION_BB = ENABLE)
mbed_official	133:d4dda5c437f0	852	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) CR_HSION_BB = DISABLE)
mbed_official	133:d4dda5c437f0	853
mbed_official	133:d4dda5c437f0	854	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
mbed_official	133:d4dda5c437f0	855	* @note The calibration is used to compensate for the variations in voltage
mbed_official	133:d4dda5c437f0	856	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	133:d4dda5c437f0	857	* @param __HSICalibrationValue__: specifies the calibration trimming value.
mbed_official	133:d4dda5c437f0	858	* This parameter must be a number between 0 and 0x1F.
mbed_official	133:d4dda5c437f0	859	*/
mbed_official	133:d4dda5c437f0	860	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
mbed_official	133:d4dda5c437f0	861	RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
mbed_official	133:d4dda5c437f0	862
mbed_official	133:d4dda5c437f0	863	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
mbed_official	133:d4dda5c437f0	864	* @note After enabling the LSI, the application software should wait on
mbed_official	133:d4dda5c437f0	865	* LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official	133:d4dda5c437f0	866	* be used to clock the IWDG and/or the RTC.
mbed_official	133:d4dda5c437f0	867	* @note LSI can not be disabled if the IWDG is running.
mbed_official	133:d4dda5c437f0	868	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official	133:d4dda5c437f0	869	* clock cycles.
mbed_official	133:d4dda5c437f0	870	*/
mbed_official	133:d4dda5c437f0	871	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) CSR_LSION_BB = ENABLE)
mbed_official	133:d4dda5c437f0	872	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) CSR_LSION_BB = DISABLE)
mbed_official	133:d4dda5c437f0	873
mbed_official	133:d4dda5c437f0	874	/**
mbed_official	133:d4dda5c437f0	875	* @brief Macro to configure the External High Speed oscillator (HSE).
mbed_official	133:d4dda5c437f0	876	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official	133:d4dda5c437f0	877	* software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official	133:d4dda5c437f0	878	* is stable and can be used to clock the PLL and/or system clock.
mbed_official	133:d4dda5c437f0	879	* @note HSE state can not be changed if it is used directly or through the
mbed_official	133:d4dda5c437f0	880	* PLL as system clock. In this case, you have to select another source
mbed_official	133:d4dda5c437f0	881	* of the system clock then change the HSE state (ex. disable it).
mbed_official	133:d4dda5c437f0	882	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	133:d4dda5c437f0	883	* @note This function reset the CSSON bit, so if the clock security system(CSS)
mbed_official	133:d4dda5c437f0	884	* was previously enabled you have to enable it again after calling this
mbed_official	133:d4dda5c437f0	885	* function.
mbed_official	133:d4dda5c437f0	886	* @param __STATE__: specifies the new state of the HSE.
mbed_official	133:d4dda5c437f0	887	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	888	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official	133:d4dda5c437f0	889	* 6 HSE oscillator clock cycles.
mbed_official	133:d4dda5c437f0	890	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
mbed_official	133:d4dda5c437f0	891	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
mbed_official	133:d4dda5c437f0	892	*/
mbed_official	133:d4dda5c437f0	893	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t ) CR_BYTE2_ADDRESS = (__STATE__))
mbed_official	133:d4dda5c437f0	894
mbed_official	133:d4dda5c437f0	895	/**
mbed_official	133:d4dda5c437f0	896	* @brief Macro to configure the External Low Speed oscillator (LSE).
mbed_official	133:d4dda5c437f0	897	* @note As the LSE is in the Backup domain and write access is denied to
mbed_official	133:d4dda5c437f0	898	* this domain after reset, you have to enable write access using
mbed_official	133:d4dda5c437f0	899	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
mbed_official	133:d4dda5c437f0	900	* (to be done once after reset).
mbed_official	133:d4dda5c437f0	901	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
mbed_official	133:d4dda5c437f0	902	* software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official	133:d4dda5c437f0	903	* is stable and can be used to clock the RTC.
mbed_official	133:d4dda5c437f0	904	* @param __STATE__: specifies the new state of the LSE.
mbed_official	133:d4dda5c437f0	905	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	906	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official	133:d4dda5c437f0	907	* 6 LSE oscillator clock cycles.
mbed_official	133:d4dda5c437f0	908	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
mbed_official	133:d4dda5c437f0	909	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
mbed_official	133:d4dda5c437f0	910	*/
mbed_official	133:d4dda5c437f0	911	#define __HAL_RCC_LSE_CONFIG(__STATE__) ((__IO uint8_t ) BDCR_BYTE0_ADDRESS = (__STATE__))
mbed_official	133:d4dda5c437f0	912
mbed_official	133:d4dda5c437f0	913	/** @brief Macros to enable or disable the the RTC clock.
mbed_official	133:d4dda5c437f0	914	* @note These macros must be used only after the RTC clock source was selected.
mbed_official	133:d4dda5c437f0	915	*/
mbed_official	133:d4dda5c437f0	916	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) BDCR_RTCEN_BB = ENABLE)
mbed_official	133:d4dda5c437f0	917	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) BDCR_RTCEN_BB = DISABLE)
mbed_official	133:d4dda5c437f0	918
mbed_official	133:d4dda5c437f0	919	/** @brief Macros to configure the RTC clock (RTCCLK).
mbed_official	133:d4dda5c437f0	920	* @note As the RTC clock configuration bits are in the Backup domain and write
mbed_official	133:d4dda5c437f0	921	* access is denied to this domain after reset, you have to enable write
mbed_official	133:d4dda5c437f0	922	* access using the Power Backup Access macro before to configure
mbed_official	133:d4dda5c437f0	923	* the RTC clock source (to be done once after reset).
mbed_official	133:d4dda5c437f0	924	* @note Once the RTC clock is configured it can't be changed unless the
mbed_official	133:d4dda5c437f0	925	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
mbed_official	133:d4dda5c437f0	926	* a Power On Reset (POR).
mbed_official	133:d4dda5c437f0	927	* @param __RTCCLKSource__: specifies the RTC clock source.
mbed_official	133:d4dda5c437f0	928	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	929	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
mbed_official	133:d4dda5c437f0	930	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
mbed_official	133:d4dda5c437f0	931	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
mbed_official	133:d4dda5c437f0	932	* as RTC clock, where x:[2,31]
mbed_official	133:d4dda5c437f0	933	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official	133:d4dda5c437f0	934	* work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official	133:d4dda5c437f0	935	* However, when the HSE clock is used as RTC clock source, the RTC
mbed_official	133:d4dda5c437f0	936	* cannot be used in STOP and STANDBY modes.
mbed_official	133:d4dda5c437f0	937	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
mbed_official	133:d4dda5c437f0	938	* RTC clock source).
mbed_official	133:d4dda5c437f0	939	*/
mbed_official	133:d4dda5c437f0	940	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
mbed_official	133:d4dda5c437f0	941	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
mbed_official	133:d4dda5c437f0	942
mbed_official	133:d4dda5c437f0	943	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
mbed_official	133:d4dda5c437f0	944	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFF); \
mbed_official	133:d4dda5c437f0	945	} while (0)
mbed_official	133:d4dda5c437f0	946
mbed_official	133:d4dda5c437f0	947	/** @brief Macros to force or release the Backup domain reset.
mbed_official	133:d4dda5c437f0	948	* @note This function resets the RTC peripheral (including the backup registers)
mbed_official	133:d4dda5c437f0	949	* and the RTC clock source selection in RCC_CSR register.
mbed_official	133:d4dda5c437f0	950	* @note The BKPSRAM is not affected by this reset.
mbed_official	133:d4dda5c437f0	951	*/
mbed_official	133:d4dda5c437f0	952	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) BDCR_BDRST_BB = ENABLE)
mbed_official	133:d4dda5c437f0	953	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) BDCR_BDRST_BB = DISABLE)
mbed_official	133:d4dda5c437f0	954
mbed_official	133:d4dda5c437f0	955	/** @brief Macros to enable or disable the main PLL.
mbed_official	133:d4dda5c437f0	956	* @note After enabling the main PLL, the application software should wait on
mbed_official	133:d4dda5c437f0	957	* PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official	133:d4dda5c437f0	958	* be used as system clock source.
mbed_official	133:d4dda5c437f0	959	* @note The main PLL can not be disabled if it is used as system clock source
mbed_official	133:d4dda5c437f0	960	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	133:d4dda5c437f0	961	*/
mbed_official	133:d4dda5c437f0	962	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) CR_PLLON_BB = ENABLE)
mbed_official	133:d4dda5c437f0	963	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) CR_PLLON_BB = DISABLE)
mbed_official	133:d4dda5c437f0	964
mbed_official	133:d4dda5c437f0	965	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
mbed_official	133:d4dda5c437f0	966	* @note This function must be used only when the main PLL is disabled.
mbed_official	133:d4dda5c437f0	967	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
mbed_official	133:d4dda5c437f0	968	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	969	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	133:d4dda5c437f0	970	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	133:d4dda5c437f0	971	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
mbed_official	133:d4dda5c437f0	972	* @param __PLLM__: specifies the division factor for PLL VCO input clock
mbed_official	133:d4dda5c437f0	973	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
mbed_official	133:d4dda5c437f0	974	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
mbed_official	133:d4dda5c437f0	975	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
mbed_official	133:d4dda5c437f0	976	* of 2 MHz to limit PLL jitter.
mbed_official	133:d4dda5c437f0	977	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
mbed_official	133:d4dda5c437f0	978	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	133:d4dda5c437f0	979	* @note You have to set the PLLN parameter correctly to ensure that the VCO
mbed_official	133:d4dda5c437f0	980	* output frequency is between 192 and 432 MHz.
mbed_official	133:d4dda5c437f0	981	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
mbed_official	133:d4dda5c437f0	982	* This parameter must be a number in the range {2, 4, 6, or 8}.
mbed_official	133:d4dda5c437f0	983	* @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
mbed_official	133:d4dda5c437f0	984	* the System clock frequency.
mbed_official	133:d4dda5c437f0	985	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
mbed_official	133:d4dda5c437f0	986	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	133:d4dda5c437f0	987	* @note If the USB OTG FS is used in your application, you have to set the
mbed_official	133:d4dda5c437f0	988	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
mbed_official	133:d4dda5c437f0	989	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
mbed_official	133:d4dda5c437f0	990	* correctly.
mbed_official	133:d4dda5c437f0	991	*/
mbed_official	133:d4dda5c437f0	992	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
mbed_official	133:d4dda5c437f0	993	(RCC->PLLCFGR = (0x20000000 \| (__PLLM__) \| ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
mbed_official	133:d4dda5c437f0	994	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| (__RCC_PLLSource__) \| \
mbed_official	133:d4dda5c437f0	995	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
mbed_official	133:d4dda5c437f0	996
mbed_official	133:d4dda5c437f0	997	/** @brief Macro to configure the I2S clock source (I2SCLK).
mbed_official	133:d4dda5c437f0	998	* @note This function must be called before enabling the I2S APB clock.
mbed_official	133:d4dda5c437f0	999	* @param __SOURCE__: specifies the I2S clock source.
mbed_official	133:d4dda5c437f0	1000	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	1001	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
mbed_official	133:d4dda5c437f0	1002	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
mbed_official	133:d4dda5c437f0	1003	* used as I2S clock source.
mbed_official	133:d4dda5c437f0	1004	*/
mbed_official	133:d4dda5c437f0	1005	#define __HAL_RCC_I2SCLK(__SOURCE__) ((__IO uint32_t ) CFGR_I2SSRC_BB = (__SOURCE__))
mbed_official	133:d4dda5c437f0	1006
mbed_official	133:d4dda5c437f0	1007	/** @brief Macros to enable or disable the PLLI2S.
mbed_official	133:d4dda5c437f0	1008	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	133:d4dda5c437f0	1009	*/
mbed_official	133:d4dda5c437f0	1010	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) CR_PLLI2SON_BB = ENABLE)
mbed_official	133:d4dda5c437f0	1011	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) CR_PLLI2SON_BB = DISABLE)
mbed_official	133:d4dda5c437f0	1012
mbed_official	133:d4dda5c437f0	1013	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
mbed_official	133:d4dda5c437f0	1014	* @note This macro must be used only when the PLLI2S is disabled.
mbed_official	133:d4dda5c437f0	1015	* @note PLLI2S clock source is common with the main PLL (configured in
mbed_official	133:d4dda5c437f0	1016	* HAL_RCC_ClockConfig() API).
mbed_official	133:d4dda5c437f0	1017	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
mbed_official	133:d4dda5c437f0	1018	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	133:d4dda5c437f0	1019	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
mbed_official	133:d4dda5c437f0	1020	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official	133:d4dda5c437f0	1021	* @param __PLLI2SR__: specifies the division factor for I2S clock
mbed_official	133:d4dda5c437f0	1022	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	133:d4dda5c437f0	1023	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
mbed_official	133:d4dda5c437f0	1024	* on the I2S clock frequency.
mbed_official	133:d4dda5c437f0	1025	*/
mbed_official	133:d4dda5c437f0	1026	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \| ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
mbed_official	133:d4dda5c437f0	1027
mbed_official	133:d4dda5c437f0	1028	/** @brief Macro to get the clock source used as system clock.
mbed_official	133:d4dda5c437f0	1029	* @retval The clock source used as system clock. The returned value can be one
mbed_official	133:d4dda5c437f0	1030	* of the following:
mbed_official	133:d4dda5c437f0	1031	* - RCC_CFGR_SWS_HSI: HSI used as system clock.
mbed_official	133:d4dda5c437f0	1032	* - RCC_CFGR_SWS_HSE: HSE used as system clock.
mbed_official	133:d4dda5c437f0	1033	* - RCC_CFGR_SWS_PLL: PLL used as system clock.
mbed_official	133:d4dda5c437f0	1034	*/
mbed_official	133:d4dda5c437f0	1035	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
mbed_official	133:d4dda5c437f0	1036
mbed_official	133:d4dda5c437f0	1037	/** @brief Macro to get the oscillator used as PLL clock source.
mbed_official	133:d4dda5c437f0	1038	* @retval The oscillator used as PLL clock source. The returned value can be one
mbed_official	133:d4dda5c437f0	1039	* of the following:
mbed_official	133:d4dda5c437f0	1040	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
mbed_official	133:d4dda5c437f0	1041	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
mbed_official	133:d4dda5c437f0	1042	*/
mbed_official	133:d4dda5c437f0	1043	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
mbed_official	133:d4dda5c437f0	1044
mbed_official	133:d4dda5c437f0	1045	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
mbed_official	133:d4dda5c437f0	1046	* the selected interrupts).
mbed_official	133:d4dda5c437f0	1047	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
mbed_official	133:d4dda5c437f0	1048	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1049	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	133:d4dda5c437f0	1050	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	133:d4dda5c437f0	1051	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	133:d4dda5c437f0	1052	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	133:d4dda5c437f0	1053	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	133:d4dda5c437f0	1054	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official	133:d4dda5c437f0	1055	*/
mbed_official	133:d4dda5c437f0	1056	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1057
mbed_official	133:d4dda5c437f0	1058	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
mbed_official	133:d4dda5c437f0	1059	* the selected interrupts).
mbed_official	133:d4dda5c437f0	1060	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
mbed_official	133:d4dda5c437f0	1061	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1062	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	133:d4dda5c437f0	1063	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	133:d4dda5c437f0	1064	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	133:d4dda5c437f0	1065	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	133:d4dda5c437f0	1066	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	133:d4dda5c437f0	1067	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official	133:d4dda5c437f0	1068	*/
mbed_official	133:d4dda5c437f0	1069	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1070
mbed_official	133:d4dda5c437f0	1071	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
mbed_official	133:d4dda5c437f0	1072	* bits to clear the selected interrupt pending bits.
mbed_official	133:d4dda5c437f0	1073	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	133:d4dda5c437f0	1074	* This parameter can be any combination of the following values:
mbed_official	133:d4dda5c437f0	1075	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	133:d4dda5c437f0	1076	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	133:d4dda5c437f0	1077	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	133:d4dda5c437f0	1078	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	133:d4dda5c437f0	1079	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	133:d4dda5c437f0	1080	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official	133:d4dda5c437f0	1081	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	133:d4dda5c437f0	1082	*/
mbed_official	133:d4dda5c437f0	1083	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1084
mbed_official	133:d4dda5c437f0	1085	/** @brief Check the RCC's interrupt has occurred or not.
mbed_official	133:d4dda5c437f0	1086	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
mbed_official	133:d4dda5c437f0	1087	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	1088	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	133:d4dda5c437f0	1089	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	133:d4dda5c437f0	1090	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	133:d4dda5c437f0	1091	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	133:d4dda5c437f0	1092	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	133:d4dda5c437f0	1093	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official	133:d4dda5c437f0	1094	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	133:d4dda5c437f0	1095	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
mbed_official	133:d4dda5c437f0	1096	*/
mbed_official	133:d4dda5c437f0	1097	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
mbed_official	133:d4dda5c437f0	1098
mbed_official	133:d4dda5c437f0	1099	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
mbed_official	133:d4dda5c437f0	1100	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
mbed_official	133:d4dda5c437f0	1101	*/
mbed_official	133:d4dda5c437f0	1102	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
mbed_official	133:d4dda5c437f0	1103
mbed_official	133:d4dda5c437f0	1104	/** @brief Check RCC flag is set or not.
mbed_official	133:d4dda5c437f0	1105	* @param __FLAG__: specifies the flag to check.
mbed_official	133:d4dda5c437f0	1106	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	1107	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
mbed_official	133:d4dda5c437f0	1108	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
mbed_official	133:d4dda5c437f0	1109	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
mbed_official	133:d4dda5c437f0	1110	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
mbed_official	133:d4dda5c437f0	1111	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
mbed_official	133:d4dda5c437f0	1112	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
mbed_official	133:d4dda5c437f0	1113	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
mbed_official	133:d4dda5c437f0	1114	* @arg RCC_FLAG_PINRST: Pin reset.
mbed_official	133:d4dda5c437f0	1115	* @arg RCC_FLAG_PORRST: POR/PDR reset.
mbed_official	133:d4dda5c437f0	1116	* @arg RCC_FLAG_SFTRST: Software reset.
mbed_official	133:d4dda5c437f0	1117	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
mbed_official	133:d4dda5c437f0	1118	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
mbed_official	133:d4dda5c437f0	1119	* @arg RCC_FLAG_LPWRRST: Low Power reset.
mbed_official	133:d4dda5c437f0	1120	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	133:d4dda5c437f0	1121	*/
mbed_official	133:d4dda5c437f0	1122	#define RCC_FLAG_MASK ((uint8_t)0x1F)
mbed_official	133:d4dda5c437f0	1123	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
mbed_official	133:d4dda5c437f0	1124
mbed_official	133:d4dda5c437f0	1125	#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
mbed_official	133:d4dda5c437f0	1126
mbed_official	133:d4dda5c437f0	1127
mbed_official	133:d4dda5c437f0	1128	/* Include RCC HAL Extension module */
mbed_official	133:d4dda5c437f0	1129	#include "stm32f4xx_hal_rcc_ex.h"
mbed_official	133:d4dda5c437f0	1130
mbed_official	133:d4dda5c437f0	1131	/* Exported functions --------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	1132
mbed_official	133:d4dda5c437f0	1133	/* Initialization and de-initialization functions ******************************/
mbed_official	133:d4dda5c437f0	1134	void HAL_RCC_DeInit(void);
mbed_official	133:d4dda5c437f0	1135	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	133:d4dda5c437f0	1136	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
mbed_official	133:d4dda5c437f0	1137
mbed_official	133:d4dda5c437f0	1138	/* Peripheral Control functions ************************************************/
mbed_official	133:d4dda5c437f0	1139	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
mbed_official	133:d4dda5c437f0	1140	void HAL_RCC_EnableCSS(void);
mbed_official	133:d4dda5c437f0	1141	void HAL_RCC_DisableCSS(void);
mbed_official	133:d4dda5c437f0	1142	uint32_t HAL_RCC_GetSysClockFreq(void);
mbed_official	133:d4dda5c437f0	1143	uint32_t HAL_RCC_GetHCLKFreq(void);
mbed_official	133:d4dda5c437f0	1144	uint32_t HAL_RCC_GetPCLK1Freq(void);
mbed_official	133:d4dda5c437f0	1145	uint32_t HAL_RCC_GetPCLK2Freq(void);
mbed_official	133:d4dda5c437f0	1146	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	133:d4dda5c437f0	1147	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
mbed_official	133:d4dda5c437f0	1148
mbed_official	133:d4dda5c437f0	1149	/* CSS NMI IRQ handler */
mbed_official	133:d4dda5c437f0	1150	void HAL_RCC_NMI_IRQHandler(void);
mbed_official	133:d4dda5c437f0	1151
mbed_official	133:d4dda5c437f0	1152	/* User Callbacks in non blocking mode (IT mode) */
mbed_official	133:d4dda5c437f0	1153	void HAL_RCC_CCSCallback(void);
mbed_official	133:d4dda5c437f0	1154
mbed_official	133:d4dda5c437f0	1155	/**
mbed_official	133:d4dda5c437f0	1156	* @}
mbed_official	133:d4dda5c437f0	1157	*/
mbed_official	133:d4dda5c437f0	1158
mbed_official	133:d4dda5c437f0	1159	/**
mbed_official	133:d4dda5c437f0	1160	* @}
mbed_official	133:d4dda5c437f0	1161	*/
mbed_official	133:d4dda5c437f0	1162
mbed_official	133:d4dda5c437f0	1163	#ifdef __cplusplus
mbed_official	133:d4dda5c437f0	1164	}
mbed_official	133:d4dda5c437f0	1165	#endif
mbed_official	133:d4dda5c437f0	1166
mbed_official	133:d4dda5c437f0	1167	#endif /* __STM32F4xx_HAL_RCC_H */
mbed_official	133:d4dda5c437f0	1168
mbed_official	133:d4dda5c437f0	1169	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	18 Jul 2014
Imports:	22
Forks:	0
Commits:	251
Dependents:	1
Dependencies:	0
Followers:	3

targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc.h@242:7074e42da0b2, 2014-06-27 (annotated)

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