Sigve Sebastian Farstad
mbed w/ spi bug fig
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mbed official
targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_dcmi.h@242:7074e42da0b2, 2014-06-27 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jun 27 07:30:09 2014 +0100
- Revision:
- 242:7074e42da0b2
- Parent:
- 133:d4dda5c437f0
Synchronized with git revision 124ef5e3add9e74a3221347a3fbeea7c8b3cf353
Full URL: https://github.com/mbedmicro/mbed/commit/124ef5e3add9e74a3221347a3fbeea7c8b3cf353/
[DISCO_F407VG] HAL update.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 133:d4dda5c437f0 | 1 | /** |
| mbed_official | 133:d4dda5c437f0 | 2 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 3 | * @file stm32f4xx_hal_dcmi.h |
| mbed_official | 133:d4dda5c437f0 | 4 | * @author MCD Application Team |
| mbed_official | 242:7074e42da0b2 | 5 | * @version V1.1.0RC2 |
| mbed_official | 242:7074e42da0b2 | 6 | * @date 14-May-2014 |
| mbed_official | 133:d4dda5c437f0 | 7 | * @brief Header file of DCMI HAL module. |
| mbed_official | 133:d4dda5c437f0 | 8 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 9 | * @attention |
| mbed_official | 133:d4dda5c437f0 | 10 | * |
| mbed_official | 133:d4dda5c437f0 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 133:d4dda5c437f0 | 12 | * |
| mbed_official | 133:d4dda5c437f0 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 133:d4dda5c437f0 | 14 | * are permitted provided that the following conditions are met: |
| mbed_official | 133:d4dda5c437f0 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 133:d4dda5c437f0 | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 133:d4dda5c437f0 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 133:d4dda5c437f0 | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 133:d4dda5c437f0 | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 133:d4dda5c437f0 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 133:d4dda5c437f0 | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 133:d4dda5c437f0 | 22 | * without specific prior written permission. |
| mbed_official | 133:d4dda5c437f0 | 23 | * |
| mbed_official | 133:d4dda5c437f0 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 133:d4dda5c437f0 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 133:d4dda5c437f0 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 133:d4dda5c437f0 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 133:d4dda5c437f0 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 133:d4dda5c437f0 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 133:d4dda5c437f0 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 133:d4dda5c437f0 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 133:d4dda5c437f0 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 133:d4dda5c437f0 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 133:d4dda5c437f0 | 34 | * |
| mbed_official | 133:d4dda5c437f0 | 35 | ****************************************************************************** |
| mbed_official | 133:d4dda5c437f0 | 36 | */ |
| mbed_official | 133:d4dda5c437f0 | 37 | |
| mbed_official | 133:d4dda5c437f0 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 39 | #ifndef __STM32F4xx_HAL_DCMI_H |
| mbed_official | 133:d4dda5c437f0 | 40 | #define __STM32F4xx_HAL_DCMI_H |
| mbed_official | 133:d4dda5c437f0 | 41 | |
| mbed_official | 133:d4dda5c437f0 | 42 | #ifdef __cplusplus |
| mbed_official | 133:d4dda5c437f0 | 43 | extern "C" { |
| mbed_official | 133:d4dda5c437f0 | 44 | #endif |
| mbed_official | 133:d4dda5c437f0 | 45 | |
| mbed_official | 133:d4dda5c437f0 | 46 | #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 133:d4dda5c437f0 | 47 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 48 | #include "stm32f4xx_hal_def.h" |
| mbed_official | 133:d4dda5c437f0 | 49 | |
| mbed_official | 133:d4dda5c437f0 | 50 | |
| mbed_official | 133:d4dda5c437f0 | 51 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 133:d4dda5c437f0 | 52 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 53 | */ |
| mbed_official | 133:d4dda5c437f0 | 54 | |
| mbed_official | 133:d4dda5c437f0 | 55 | /** @addtogroup DCMI |
| mbed_official | 133:d4dda5c437f0 | 56 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 57 | */ |
| mbed_official | 133:d4dda5c437f0 | 58 | |
| mbed_official | 133:d4dda5c437f0 | 59 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 60 | |
| mbed_official | 133:d4dda5c437f0 | 61 | /** |
| mbed_official | 242:7074e42da0b2 | 62 | * @brief DCMI Error source |
| mbed_official | 242:7074e42da0b2 | 63 | */ |
| mbed_official | 133:d4dda5c437f0 | 64 | typedef enum |
| mbed_official | 133:d4dda5c437f0 | 65 | { |
| mbed_official | 133:d4dda5c437f0 | 66 | DCMI_ERROR_SYNC = 1, /*!< Synchronisation error */ |
| mbed_official | 133:d4dda5c437f0 | 67 | DCMI_OVERRUN = 2, /*!< DCMI Overrun */ |
| mbed_official | 242:7074e42da0b2 | 68 | }DCMI_ErrorTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 69 | |
| mbed_official | 133:d4dda5c437f0 | 70 | /** |
| mbed_official | 242:7074e42da0b2 | 71 | * @brief DCMI Embedded Synchronisation CODE Init structure definition |
| mbed_official | 133:d4dda5c437f0 | 72 | */ |
| mbed_official | 133:d4dda5c437f0 | 73 | typedef struct |
| mbed_official | 133:d4dda5c437f0 | 74 | { |
| mbed_official | 133:d4dda5c437f0 | 75 | uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ |
| mbed_official | 133:d4dda5c437f0 | 76 | uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */ |
| mbed_official | 133:d4dda5c437f0 | 77 | uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */ |
| mbed_official | 133:d4dda5c437f0 | 78 | uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ |
| mbed_official | 133:d4dda5c437f0 | 79 | }DCMI_CodesInitTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 80 | |
| mbed_official | 133:d4dda5c437f0 | 81 | /** |
| mbed_official | 242:7074e42da0b2 | 82 | * @brief DCMI Init structure definition |
| mbed_official | 133:d4dda5c437f0 | 83 | */ |
| mbed_official | 133:d4dda5c437f0 | 84 | typedef struct |
| mbed_official | 133:d4dda5c437f0 | 85 | { |
| mbed_official | 133:d4dda5c437f0 | 86 | uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. |
| mbed_official | 133:d4dda5c437f0 | 87 | This parameter can be a value of @ref DCMI_Synchronization_Mode */ |
| mbed_official | 133:d4dda5c437f0 | 88 | |
| mbed_official | 133:d4dda5c437f0 | 89 | uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. |
| mbed_official | 133:d4dda5c437f0 | 90 | This parameter can be a value of @ref DCMI_PIXCK_Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 91 | |
| mbed_official | 133:d4dda5c437f0 | 92 | uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. |
| mbed_official | 133:d4dda5c437f0 | 93 | This parameter can be a value of @ref DCMI_VSYNC_Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 94 | |
| mbed_official | 133:d4dda5c437f0 | 95 | uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. |
| mbed_official | 133:d4dda5c437f0 | 96 | This parameter can be a value of @ref DCMI_HSYNC_Polarity */ |
| mbed_official | 133:d4dda5c437f0 | 97 | |
| mbed_official | 133:d4dda5c437f0 | 98 | uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. |
| mbed_official | 133:d4dda5c437f0 | 99 | This parameter can be a value of @ref DCMI_Capture_Rate */ |
| mbed_official | 133:d4dda5c437f0 | 100 | |
| mbed_official | 133:d4dda5c437f0 | 101 | uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. |
| mbed_official | 133:d4dda5c437f0 | 102 | This parameter can be a value of @ref DCMI_Extended_Data_Mode */ |
| mbed_official | 242:7074e42da0b2 | 103 | |
| mbed_official | 133:d4dda5c437f0 | 104 | DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */ |
| mbed_official | 242:7074e42da0b2 | 105 | |
| mbed_official | 133:d4dda5c437f0 | 106 | uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. |
| mbed_official | 242:7074e42da0b2 | 107 | This parameter can be a value of @ref DCMI_MODE_JPEG */ |
| mbed_official | 242:7074e42da0b2 | 108 | |
| mbed_official | 133:d4dda5c437f0 | 109 | }DCMI_InitTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 110 | |
| mbed_official | 133:d4dda5c437f0 | 111 | /** |
| mbed_official | 242:7074e42da0b2 | 112 | * @brief HAL DCMI State structures definition |
| mbed_official | 133:d4dda5c437f0 | 113 | */ |
| mbed_official | 133:d4dda5c437f0 | 114 | typedef enum |
| mbed_official | 133:d4dda5c437f0 | 115 | { |
| mbed_official | 133:d4dda5c437f0 | 116 | HAL_DCMI_STATE_RESET = 0x00, /*!< DCMI not yet initialized or disabled */ |
| mbed_official | 133:d4dda5c437f0 | 117 | HAL_DCMI_STATE_READY = 0x01, /*!< DCMI initialized and ready for use */ |
| mbed_official | 133:d4dda5c437f0 | 118 | HAL_DCMI_STATE_BUSY = 0x02, /*!< DCMI internal processing is ongoing */ |
| mbed_official | 133:d4dda5c437f0 | 119 | HAL_DCMI_STATE_TIMEOUT = 0x03, /*!< DCMI timeout state */ |
| mbed_official | 133:d4dda5c437f0 | 120 | HAL_DCMI_STATE_ERROR = 0x04 /*!< DCMI error state */ |
| mbed_official | 133:d4dda5c437f0 | 121 | }HAL_DCMI_StateTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 122 | |
| mbed_official | 133:d4dda5c437f0 | 123 | /** |
| mbed_official | 242:7074e42da0b2 | 124 | * @brief DCMI handle Structure definition |
| mbed_official | 242:7074e42da0b2 | 125 | */ |
| mbed_official | 133:d4dda5c437f0 | 126 | typedef struct |
| mbed_official | 242:7074e42da0b2 | 127 | { |
| mbed_official | 133:d4dda5c437f0 | 128 | DCMI_TypeDef *Instance; /*!< DCMI Register base address */ |
| mbed_official | 242:7074e42da0b2 | 129 | |
| mbed_official | 133:d4dda5c437f0 | 130 | DCMI_InitTypeDef Init; /*!< DCMI parameters */ |
| mbed_official | 242:7074e42da0b2 | 131 | |
| mbed_official | 133:d4dda5c437f0 | 132 | HAL_LockTypeDef Lock; /*!< DCMI locking object */ |
| mbed_official | 242:7074e42da0b2 | 133 | |
| mbed_official | 133:d4dda5c437f0 | 134 | __IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */ |
| mbed_official | 242:7074e42da0b2 | 135 | |
| mbed_official | 133:d4dda5c437f0 | 136 | __IO uint32_t XferCount; /*!< DMA transfer counter */ |
| mbed_official | 242:7074e42da0b2 | 137 | |
| mbed_official | 133:d4dda5c437f0 | 138 | __IO uint32_t XferSize; /*!< DMA transfer size */ |
| mbed_official | 242:7074e42da0b2 | 139 | |
| mbed_official | 242:7074e42da0b2 | 140 | uint32_t XferTransferNumber; /*!< DMA transfer number */ |
| mbed_official | 133:d4dda5c437f0 | 141 | |
| mbed_official | 242:7074e42da0b2 | 142 | uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */ |
| mbed_official | 242:7074e42da0b2 | 143 | |
| mbed_official | 133:d4dda5c437f0 | 144 | DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */ |
| mbed_official | 133:d4dda5c437f0 | 145 | |
| mbed_official | 242:7074e42da0b2 | 146 | __IO uint32_t ErrorCode; /*!< DCMI Error code */ |
| mbed_official | 242:7074e42da0b2 | 147 | |
| mbed_official | 242:7074e42da0b2 | 148 | }DCMI_HandleTypeDef; |
| mbed_official | 133:d4dda5c437f0 | 149 | |
| mbed_official | 133:d4dda5c437f0 | 150 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 151 | |
| mbed_official | 133:d4dda5c437f0 | 152 | /** @defgroup DCMI_Exported_Constants |
| mbed_official | 133:d4dda5c437f0 | 153 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 154 | */ |
| mbed_official | 133:d4dda5c437f0 | 155 | |
| mbed_official | 133:d4dda5c437f0 | 156 | /** @defgroup DCMI_Error_Code |
| mbed_official | 133:d4dda5c437f0 | 157 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 158 | */ |
| mbed_official | 133:d4dda5c437f0 | 159 | #define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ |
| mbed_official | 133:d4dda5c437f0 | 160 | #define HAL_DCMI_ERROR_OVF ((uint32_t)0x00000001) /*!< Overflow error */ |
| mbed_official | 242:7074e42da0b2 | 161 | #define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */ |
| mbed_official | 133:d4dda5c437f0 | 162 | #define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ |
| mbed_official | 133:d4dda5c437f0 | 163 | /** |
| mbed_official | 133:d4dda5c437f0 | 164 | * @} |
| mbed_official | 242:7074e42da0b2 | 165 | */ |
| mbed_official | 133:d4dda5c437f0 | 166 | |
| mbed_official | 242:7074e42da0b2 | 167 | /** @defgroup DCMI_Capture_Mode |
| mbed_official | 133:d4dda5c437f0 | 168 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 169 | */ |
| mbed_official | 133:d4dda5c437f0 | 170 | #define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously |
| mbed_official | 133:d4dda5c437f0 | 171 | into the destination memory through the DMA */ |
| mbed_official | 133:d4dda5c437f0 | 172 | #define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of |
| mbed_official | 133:d4dda5c437f0 | 173 | frame and then transfers a single frame through the DMA */ |
| mbed_official | 133:d4dda5c437f0 | 174 | |
| mbed_official | 133:d4dda5c437f0 | 175 | #define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \ |
| mbed_official | 133:d4dda5c437f0 | 176 | ((MODE) == DCMI_MODE_SNAPSHOT)) |
| mbed_official | 133:d4dda5c437f0 | 177 | /** |
| mbed_official | 133:d4dda5c437f0 | 178 | * @} |
| mbed_official | 242:7074e42da0b2 | 179 | */ |
| mbed_official | 133:d4dda5c437f0 | 180 | |
| mbed_official | 133:d4dda5c437f0 | 181 | /** @defgroup DCMI_Synchronization_Mode |
| mbed_official | 133:d4dda5c437f0 | 182 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 183 | */ |
| mbed_official | 133:d4dda5c437f0 | 184 | #define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000) /*!< Hardware synchronization data capture (frame/line start/stop) |
| mbed_official | 133:d4dda5c437f0 | 185 | is synchronized with the HSYNC/VSYNC signals */ |
| mbed_official | 133:d4dda5c437f0 | 186 | #define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with |
| mbed_official | 133:d4dda5c437f0 | 187 | synchronization codes embedded in the data flow */ |
| mbed_official | 242:7074e42da0b2 | 188 | |
| mbed_official | 133:d4dda5c437f0 | 189 | #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \ |
| mbed_official | 133:d4dda5c437f0 | 190 | ((MODE) == DCMI_SYNCHRO_EMBEDDED)) |
| mbed_official | 133:d4dda5c437f0 | 191 | /** |
| mbed_official | 133:d4dda5c437f0 | 192 | * @} |
| mbed_official | 242:7074e42da0b2 | 193 | */ |
| mbed_official | 133:d4dda5c437f0 | 194 | |
| mbed_official | 242:7074e42da0b2 | 195 | /** @defgroup DCMI_PIXCK_Polarity |
| mbed_official | 133:d4dda5c437f0 | 196 | * @{ |
| mbed_official | 242:7074e42da0b2 | 197 | */ |
| mbed_official | 133:d4dda5c437f0 | 198 | #define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */ |
| mbed_official | 133:d4dda5c437f0 | 199 | #define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */ |
| mbed_official | 133:d4dda5c437f0 | 200 | |
| mbed_official | 133:d4dda5c437f0 | 201 | #define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \ |
| mbed_official | 133:d4dda5c437f0 | 202 | ((POLARITY) == DCMI_PCKPOLARITY_RISING)) |
| mbed_official | 133:d4dda5c437f0 | 203 | /** |
| mbed_official | 133:d4dda5c437f0 | 204 | * @} |
| mbed_official | 242:7074e42da0b2 | 205 | */ |
| mbed_official | 133:d4dda5c437f0 | 206 | |
| mbed_official | 242:7074e42da0b2 | 207 | /** @defgroup DCMI_VSYNC_Polarity |
| mbed_official | 133:d4dda5c437f0 | 208 | * @{ |
| mbed_official | 242:7074e42da0b2 | 209 | */ |
| mbed_official | 133:d4dda5c437f0 | 210 | #define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */ |
| mbed_official | 133:d4dda5c437f0 | 211 | #define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */ |
| mbed_official | 133:d4dda5c437f0 | 212 | |
| mbed_official | 133:d4dda5c437f0 | 213 | #define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \ |
| mbed_official | 133:d4dda5c437f0 | 214 | ((POLARITY) == DCMI_VSPOLARITY_HIGH)) |
| mbed_official | 133:d4dda5c437f0 | 215 | /** |
| mbed_official | 133:d4dda5c437f0 | 216 | * @} |
| mbed_official | 242:7074e42da0b2 | 217 | */ |
| mbed_official | 133:d4dda5c437f0 | 218 | |
| mbed_official | 242:7074e42da0b2 | 219 | /** @defgroup DCMI_HSYNC_Polarity |
| mbed_official | 133:d4dda5c437f0 | 220 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 221 | */ |
| mbed_official | 133:d4dda5c437f0 | 222 | #define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */ |
| mbed_official | 133:d4dda5c437f0 | 223 | #define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */ |
| mbed_official | 133:d4dda5c437f0 | 224 | |
| mbed_official | 133:d4dda5c437f0 | 225 | #define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \ |
| mbed_official | 133:d4dda5c437f0 | 226 | ((POLARITY) == DCMI_HSPOLARITY_HIGH)) |
| mbed_official | 133:d4dda5c437f0 | 227 | /** |
| mbed_official | 133:d4dda5c437f0 | 228 | * @} |
| mbed_official | 242:7074e42da0b2 | 229 | */ |
| mbed_official | 133:d4dda5c437f0 | 230 | |
| mbed_official | 133:d4dda5c437f0 | 231 | /** @defgroup DCMI_MODE_JPEG |
| mbed_official | 133:d4dda5c437f0 | 232 | * @{ |
| mbed_official | 242:7074e42da0b2 | 233 | */ |
| mbed_official | 133:d4dda5c437f0 | 234 | #define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< Mode JPEG Disabled */ |
| mbed_official | 133:d4dda5c437f0 | 235 | #define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */ |
| mbed_official | 133:d4dda5c437f0 | 236 | |
| mbed_official | 133:d4dda5c437f0 | 237 | #define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \ |
| mbed_official | 133:d4dda5c437f0 | 238 | ((JPEG_MODE) == DCMI_JPEG_ENABLE)) |
| mbed_official | 133:d4dda5c437f0 | 239 | /** |
| mbed_official | 133:d4dda5c437f0 | 240 | * @} |
| mbed_official | 242:7074e42da0b2 | 241 | */ |
| mbed_official | 133:d4dda5c437f0 | 242 | |
| mbed_official | 133:d4dda5c437f0 | 243 | /** @defgroup DCMI_Capture_Rate |
| mbed_official | 133:d4dda5c437f0 | 244 | * @{ |
| mbed_official | 242:7074e42da0b2 | 245 | */ |
| mbed_official | 133:d4dda5c437f0 | 246 | #define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */ |
| mbed_official | 133:d4dda5c437f0 | 247 | #define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */ |
| mbed_official | 133:d4dda5c437f0 | 248 | #define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */ |
| mbed_official | 133:d4dda5c437f0 | 249 | |
| mbed_official | 133:d4dda5c437f0 | 250 | #define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \ |
| mbed_official | 133:d4dda5c437f0 | 251 | ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \ |
| mbed_official | 133:d4dda5c437f0 | 252 | ((RATE) == DCMI_CR_ALTERNATE_4_FRAME)) |
| mbed_official | 133:d4dda5c437f0 | 253 | /** |
| mbed_official | 133:d4dda5c437f0 | 254 | * @} |
| mbed_official | 242:7074e42da0b2 | 255 | */ |
| mbed_official | 133:d4dda5c437f0 | 256 | |
| mbed_official | 133:d4dda5c437f0 | 257 | /** @defgroup DCMI_Extended_Data_Mode |
| mbed_official | 133:d4dda5c437f0 | 258 | * @{ |
| mbed_official | 242:7074e42da0b2 | 259 | */ |
| mbed_official | 133:d4dda5c437f0 | 260 | #define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */ |
| mbed_official | 133:d4dda5c437f0 | 261 | #define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */ |
| mbed_official | 133:d4dda5c437f0 | 262 | #define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */ |
| mbed_official | 133:d4dda5c437f0 | 263 | #define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */ |
| mbed_official | 133:d4dda5c437f0 | 264 | |
| mbed_official | 133:d4dda5c437f0 | 265 | #define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \ |
| mbed_official | 133:d4dda5c437f0 | 266 | ((DATA) == DCMI_EXTEND_DATA_10B) || \ |
| mbed_official | 133:d4dda5c437f0 | 267 | ((DATA) == DCMI_EXTEND_DATA_12B) || \ |
| mbed_official | 133:d4dda5c437f0 | 268 | ((DATA) == DCMI_EXTEND_DATA_14B)) |
| mbed_official | 133:d4dda5c437f0 | 269 | /** |
| mbed_official | 133:d4dda5c437f0 | 270 | * @} |
| mbed_official | 242:7074e42da0b2 | 271 | */ |
| mbed_official | 133:d4dda5c437f0 | 272 | |
| mbed_official | 133:d4dda5c437f0 | 273 | /** @defgroup DCMI_Window_Coordinate |
| mbed_official | 133:d4dda5c437f0 | 274 | * @{ |
| mbed_official | 242:7074e42da0b2 | 275 | */ |
| mbed_official | 133:d4dda5c437f0 | 276 | #define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */ |
| mbed_official | 133:d4dda5c437f0 | 277 | |
| mbed_official | 133:d4dda5c437f0 | 278 | #define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE) |
| mbed_official | 133:d4dda5c437f0 | 279 | /** |
| mbed_official | 133:d4dda5c437f0 | 280 | * @} |
| mbed_official | 133:d4dda5c437f0 | 281 | */ |
| mbed_official | 133:d4dda5c437f0 | 282 | |
| mbed_official | 133:d4dda5c437f0 | 283 | /** @defgroup DCMI_Window_Height |
| mbed_official | 133:d4dda5c437f0 | 284 | * @{ |
| mbed_official | 133:d4dda5c437f0 | 285 | */ |
| mbed_official | 133:d4dda5c437f0 | 286 | #define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF) /*!< Window Height */ |
| mbed_official | 133:d4dda5c437f0 | 287 | |
| mbed_official | 133:d4dda5c437f0 | 288 | #define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT) |
| mbed_official | 133:d4dda5c437f0 | 289 | /** |
| mbed_official | 133:d4dda5c437f0 | 290 | * @} |
| mbed_official | 242:7074e42da0b2 | 291 | */ |
| mbed_official | 133:d4dda5c437f0 | 292 | |
| mbed_official | 242:7074e42da0b2 | 293 | /** @defgroup DCMI_interrupt_sources |
| mbed_official | 133:d4dda5c437f0 | 294 | * @{ |
| mbed_official | 242:7074e42da0b2 | 295 | */ |
| mbed_official | 133:d4dda5c437f0 | 296 | #define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) |
| mbed_official | 133:d4dda5c437f0 | 297 | #define DCMI_IT_OVF ((uint32_t)DCMI_IER_OVF_IE) |
| mbed_official | 133:d4dda5c437f0 | 298 | #define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) |
| mbed_official | 133:d4dda5c437f0 | 299 | #define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) |
| mbed_official | 133:d4dda5c437f0 | 300 | #define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) |
| mbed_official | 133:d4dda5c437f0 | 301 | |
| mbed_official | 133:d4dda5c437f0 | 302 | #define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000)) |
| mbed_official | 133:d4dda5c437f0 | 303 | |
| mbed_official | 133:d4dda5c437f0 | 304 | #define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \ |
| mbed_official | 133:d4dda5c437f0 | 305 | ((IT) == DCMI_IT_OVF) || \ |
| mbed_official | 133:d4dda5c437f0 | 306 | ((IT) == DCMI_IT_ERR) || \ |
| mbed_official | 133:d4dda5c437f0 | 307 | ((IT) == DCMI_IT_VSYNC) || \ |
| mbed_official | 133:d4dda5c437f0 | 308 | ((IT) == DCMI_IT_LINE)) |
| mbed_official | 133:d4dda5c437f0 | 309 | /** |
| mbed_official | 133:d4dda5c437f0 | 310 | * @} |
| mbed_official | 242:7074e42da0b2 | 311 | */ |
| mbed_official | 133:d4dda5c437f0 | 312 | |
| mbed_official | 242:7074e42da0b2 | 313 | /** @defgroup DCMI_Flags |
| mbed_official | 133:d4dda5c437f0 | 314 | * @{ |
| mbed_official | 242:7074e42da0b2 | 315 | */ |
| mbed_official | 242:7074e42da0b2 | 316 | |
| mbed_official | 133:d4dda5c437f0 | 317 | /** |
| mbed_official | 242:7074e42da0b2 | 318 | * @brief DCMI SR register |
| mbed_official | 133:d4dda5c437f0 | 319 | */ |
| mbed_official | 133:d4dda5c437f0 | 320 | #define DCMI_FLAG_HSYNC ((uint32_t)0x2001) |
| mbed_official | 133:d4dda5c437f0 | 321 | #define DCMI_FLAG_VSYNC ((uint32_t)0x2002) |
| mbed_official | 133:d4dda5c437f0 | 322 | #define DCMI_FLAG_FNE ((uint32_t)0x2004) |
| mbed_official | 133:d4dda5c437f0 | 323 | /** |
| mbed_official | 133:d4dda5c437f0 | 324 | * @brief DCMI RISR register |
| mbed_official | 133:d4dda5c437f0 | 325 | */ |
| mbed_official | 133:d4dda5c437f0 | 326 | #define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS) |
| mbed_official | 133:d4dda5c437f0 | 327 | #define DCMI_FLAG_OVFRI ((uint32_t)DCMI_RISR_OVF_RIS) |
| mbed_official | 133:d4dda5c437f0 | 328 | #define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS) |
| mbed_official | 133:d4dda5c437f0 | 329 | #define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS) |
| mbed_official | 133:d4dda5c437f0 | 330 | #define DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS) |
| mbed_official | 133:d4dda5c437f0 | 331 | /** |
| mbed_official | 133:d4dda5c437f0 | 332 | * @brief DCMI MISR register |
| mbed_official | 133:d4dda5c437f0 | 333 | */ |
| mbed_official | 133:d4dda5c437f0 | 334 | #define DCMI_FLAG_FRAMEMI ((uint32_t)0x1001) |
| mbed_official | 133:d4dda5c437f0 | 335 | #define DCMI_FLAG_OVFMI ((uint32_t)0x1002) |
| mbed_official | 133:d4dda5c437f0 | 336 | #define DCMI_FLAG_ERRMI ((uint32_t)0x1004) |
| mbed_official | 133:d4dda5c437f0 | 337 | #define DCMI_FLAG_VSYNCMI ((uint32_t)0x1008) |
| mbed_official | 133:d4dda5c437f0 | 338 | #define DCMI_FLAG_LINEMI ((uint32_t)0x1010) |
| mbed_official | 133:d4dda5c437f0 | 339 | #define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \ |
| mbed_official | 133:d4dda5c437f0 | 340 | ((FLAG) == DCMI_FLAG_VSYNC) || \ |
| mbed_official | 133:d4dda5c437f0 | 341 | ((FLAG) == DCMI_FLAG_FNE) || \ |
| mbed_official | 133:d4dda5c437f0 | 342 | ((FLAG) == DCMI_FLAG_FRAMERI) || \ |
| mbed_official | 133:d4dda5c437f0 | 343 | ((FLAG) == DCMI_FLAG_OVFRI) || \ |
| mbed_official | 133:d4dda5c437f0 | 344 | ((FLAG) == DCMI_FLAG_ERRRI) || \ |
| mbed_official | 133:d4dda5c437f0 | 345 | ((FLAG) == DCMI_FLAG_VSYNCRI) || \ |
| mbed_official | 133:d4dda5c437f0 | 346 | ((FLAG) == DCMI_FLAG_LINERI) || \ |
| mbed_official | 133:d4dda5c437f0 | 347 | ((FLAG) == DCMI_FLAG_FRAMEMI) || \ |
| mbed_official | 133:d4dda5c437f0 | 348 | ((FLAG) == DCMI_FLAG_OVFMI) || \ |
| mbed_official | 133:d4dda5c437f0 | 349 | ((FLAG) == DCMI_FLAG_ERRMI) || \ |
| mbed_official | 133:d4dda5c437f0 | 350 | ((FLAG) == DCMI_FLAG_VSYNCMI) || \ |
| mbed_official | 133:d4dda5c437f0 | 351 | ((FLAG) == DCMI_FLAG_LINEMI)) |
| mbed_official | 133:d4dda5c437f0 | 352 | |
| mbed_official | 133:d4dda5c437f0 | 353 | #define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000)) |
| mbed_official | 133:d4dda5c437f0 | 354 | /** |
| mbed_official | 133:d4dda5c437f0 | 355 | * @} |
| mbed_official | 133:d4dda5c437f0 | 356 | */ |
| mbed_official | 133:d4dda5c437f0 | 357 | |
| mbed_official | 133:d4dda5c437f0 | 358 | /** |
| mbed_official | 133:d4dda5c437f0 | 359 | * @} |
| mbed_official | 133:d4dda5c437f0 | 360 | */ |
| mbed_official | 133:d4dda5c437f0 | 361 | |
| mbed_official | 133:d4dda5c437f0 | 362 | /* Exported macro ------------------------------------------------------------*/ |
| mbed_official | 242:7074e42da0b2 | 363 | |
| mbed_official | 242:7074e42da0b2 | 364 | /** @brief Reset DCMI handle state |
| mbed_official | 242:7074e42da0b2 | 365 | * @param __HANDLE__: specifies the DCMI handle. |
| mbed_official | 242:7074e42da0b2 | 366 | * @retval None |
| mbed_official | 242:7074e42da0b2 | 367 | */ |
| mbed_official | 242:7074e42da0b2 | 368 | #define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET) |
| mbed_official | 242:7074e42da0b2 | 369 | |
| mbed_official | 133:d4dda5c437f0 | 370 | /** |
| mbed_official | 133:d4dda5c437f0 | 371 | * @brief Enable the DCMI. |
| mbed_official | 133:d4dda5c437f0 | 372 | * @param __HANDLE__: DCMI handle |
| mbed_official | 133:d4dda5c437f0 | 373 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 374 | */ |
| mbed_official | 133:d4dda5c437f0 | 375 | #define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE) |
| mbed_official | 133:d4dda5c437f0 | 376 | |
| mbed_official | 133:d4dda5c437f0 | 377 | /** |
| mbed_official | 133:d4dda5c437f0 | 378 | * @brief Disable the DCMI. |
| mbed_official | 133:d4dda5c437f0 | 379 | * @param __HANDLE__: DCMI handle |
| mbed_official | 133:d4dda5c437f0 | 380 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 381 | */ |
| mbed_official | 133:d4dda5c437f0 | 382 | #define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE)) |
| mbed_official | 133:d4dda5c437f0 | 383 | |
| mbed_official | 133:d4dda5c437f0 | 384 | /* Interrupt & Flag management */ |
| mbed_official | 133:d4dda5c437f0 | 385 | /** |
| mbed_official | 133:d4dda5c437f0 | 386 | * @brief Get the DCMI pending flags. |
| mbed_official | 133:d4dda5c437f0 | 387 | * @param __HANDLE__: DCMI handle |
| mbed_official | 133:d4dda5c437f0 | 388 | * @param __FLAG__: Get the specified flag. |
| mbed_official | 133:d4dda5c437f0 | 389 | * This parameter can be any combination of the following values: |
| mbed_official | 133:d4dda5c437f0 | 390 | * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask |
| mbed_official | 133:d4dda5c437f0 | 391 | * @arg DCMI_FLAG_OVFRI: Overflow flag mask |
| mbed_official | 133:d4dda5c437f0 | 392 | * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask |
| mbed_official | 133:d4dda5c437f0 | 393 | * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask |
| mbed_official | 133:d4dda5c437f0 | 394 | * @arg DCMI_FLAG_LINERI: Line flag mask |
| mbed_official | 133:d4dda5c437f0 | 395 | * @retval The state of FLAG. |
| mbed_official | 133:d4dda5c437f0 | 396 | */ |
| mbed_official | 133:d4dda5c437f0 | 397 | #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\ |
| mbed_official | 133:d4dda5c437f0 | 398 | ((((__FLAG__) & 0x3000) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\ |
| mbed_official | 133:d4dda5c437f0 | 399 | (((__FLAG__) & 0x2000) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__))) |
| mbed_official | 133:d4dda5c437f0 | 400 | |
| mbed_official | 133:d4dda5c437f0 | 401 | /** |
| mbed_official | 133:d4dda5c437f0 | 402 | * @brief Clear the DCMI pending flags. |
| mbed_official | 133:d4dda5c437f0 | 403 | * @param __HANDLE__: DCMI handle |
| mbed_official | 133:d4dda5c437f0 | 404 | * @param __FLAG__: specifies the flag to clear. |
| mbed_official | 133:d4dda5c437f0 | 405 | * This parameter can be any combination of the following values: |
| mbed_official | 133:d4dda5c437f0 | 406 | * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask |
| mbed_official | 133:d4dda5c437f0 | 407 | * @arg DCMI_FLAG_OVFRI: Overflow flag mask |
| mbed_official | 133:d4dda5c437f0 | 408 | * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask |
| mbed_official | 133:d4dda5c437f0 | 409 | * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask |
| mbed_official | 133:d4dda5c437f0 | 410 | * @arg DCMI_FLAG_LINERI: Line flag mask |
| mbed_official | 133:d4dda5c437f0 | 411 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 412 | */ |
| mbed_official | 133:d4dda5c437f0 | 413 | #define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR |= (__FLAG__)) |
| mbed_official | 133:d4dda5c437f0 | 414 | |
| mbed_official | 133:d4dda5c437f0 | 415 | /** |
| mbed_official | 133:d4dda5c437f0 | 416 | * @brief Enable the specified DCMI interrupts. |
| mbed_official | 133:d4dda5c437f0 | 417 | * @param __HANDLE__: DCMI handle |
| mbed_official | 133:d4dda5c437f0 | 418 | * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. |
| mbed_official | 133:d4dda5c437f0 | 419 | * This parameter can be any combination of the following values: |
| mbed_official | 133:d4dda5c437f0 | 420 | * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 421 | * @arg DCMI_IT_OVF: Overflow interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 422 | * @arg DCMI_IT_ERR: Synchronization error interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 423 | * @arg DCMI_IT_VSYNC: VSYNC interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 424 | * @arg DCMI_IT_LINE: Line interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 425 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 426 | */ |
| mbed_official | 133:d4dda5c437f0 | 427 | #define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) |
| mbed_official | 133:d4dda5c437f0 | 428 | |
| mbed_official | 133:d4dda5c437f0 | 429 | /** |
| mbed_official | 133:d4dda5c437f0 | 430 | * @brief Disable the specified DCMI interrupts. |
| mbed_official | 133:d4dda5c437f0 | 431 | * @param __HANDLE__: DCMI handle |
| mbed_official | 133:d4dda5c437f0 | 432 | * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. |
| mbed_official | 133:d4dda5c437f0 | 433 | * This parameter can be any combination of the following values: |
| mbed_official | 133:d4dda5c437f0 | 434 | * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 435 | * @arg DCMI_IT_OVF: Overflow interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 436 | * @arg DCMI_IT_ERR: Synchronization error interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 437 | * @arg DCMI_IT_VSYNC: VSYNC interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 438 | * @arg DCMI_IT_LINE: Line interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 439 | * @retval None |
| mbed_official | 133:d4dda5c437f0 | 440 | */ |
| mbed_official | 133:d4dda5c437f0 | 441 | #define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) |
| mbed_official | 133:d4dda5c437f0 | 442 | |
| mbed_official | 133:d4dda5c437f0 | 443 | /** |
| mbed_official | 133:d4dda5c437f0 | 444 | * @brief Check whether the specified DCMI interrupt has occurred or not. |
| mbed_official | 133:d4dda5c437f0 | 445 | * @param __HANDLE__: DCMI handle |
| mbed_official | 133:d4dda5c437f0 | 446 | * @param __INTERRUPT__: specifies the DCMI interrupt source to check. |
| mbed_official | 133:d4dda5c437f0 | 447 | * This parameter can be one of the following values: |
| mbed_official | 133:d4dda5c437f0 | 448 | * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 449 | * @arg DCMI_IT_OVF: Overflow interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 450 | * @arg DCMI_IT_ERR: Synchronization error interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 451 | * @arg DCMI_IT_VSYNC: VSYNC interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 452 | * @arg DCMI_IT_LINE: Line interrupt mask |
| mbed_official | 133:d4dda5c437f0 | 453 | * @retval The state of INTERRUPT. |
| mbed_official | 133:d4dda5c437f0 | 454 | */ |
| mbed_official | 133:d4dda5c437f0 | 455 | #define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) |
| mbed_official | 133:d4dda5c437f0 | 456 | |
| mbed_official | 242:7074e42da0b2 | 457 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 133:d4dda5c437f0 | 458 | |
| mbed_official | 242:7074e42da0b2 | 459 | /* Initialization and de-initialization functions *****************************/ |
| mbed_official | 133:d4dda5c437f0 | 460 | HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 461 | HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 462 | void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 463 | void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 464 | |
| mbed_official | 242:7074e42da0b2 | 465 | /* IO operation functions *****************************************************/ |
| mbed_official | 133:d4dda5c437f0 | 466 | HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length); |
| mbed_official | 133:d4dda5c437f0 | 467 | HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 468 | void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 469 | void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 470 | void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 471 | void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 472 | void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 473 | |
| mbed_official | 242:7074e42da0b2 | 474 | /* Peripheral Control functions ***********************************************/ |
| mbed_official | 133:d4dda5c437f0 | 475 | HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize); |
| mbed_official | 133:d4dda5c437f0 | 476 | HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 477 | HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 478 | |
| mbed_official | 242:7074e42da0b2 | 479 | /* Peripheral State functions *************************************************/ |
| mbed_official | 133:d4dda5c437f0 | 480 | HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 481 | uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); |
| mbed_official | 133:d4dda5c437f0 | 482 | |
| mbed_official | 133:d4dda5c437f0 | 483 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 133:d4dda5c437f0 | 484 | /** |
| mbed_official | 133:d4dda5c437f0 | 485 | * @} |
| mbed_official | 133:d4dda5c437f0 | 486 | */ |
| mbed_official | 133:d4dda5c437f0 | 487 | |
| mbed_official | 133:d4dda5c437f0 | 488 | /** |
| mbed_official | 133:d4dda5c437f0 | 489 | * @} |
| mbed_official | 133:d4dda5c437f0 | 490 | */ |
| mbed_official | 133:d4dda5c437f0 | 491 | |
| mbed_official | 133:d4dda5c437f0 | 492 | #ifdef __cplusplus |
| mbed_official | 133:d4dda5c437f0 | 493 | } |
| mbed_official | 133:d4dda5c437f0 | 494 | #endif |
| mbed_official | 133:d4dda5c437f0 | 495 | |
| mbed_official | 133:d4dda5c437f0 | 496 | #endif /* __STM32F4xx_HAL_DCMI_H */ |
| mbed_official | 133:d4dda5c437f0 | 497 | |
| mbed_official | 133:d4dda5c437f0 | 498 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |