mbed-src - mbed w/ spi bug fig

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mbed w/ spi bug fig

targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc_ex.h@242:7074e42da0b2, 2014-06-27 (annotated)

Committer:: mbed_official
Date:: Fri Jun 27 07:30:09 2014 +0100
Revision:: 242:7074e42da0b2
Parent:: 133:d4dda5c437f0

Synchronized with git revision 124ef5e3add9e74a3221347a3fbeea7c8b3cf353



Full URL: https://github.com/mbedmicro/mbed/commit/124ef5e3add9e74a3221347a3fbeea7c8b3cf353/



[DISCO_F407VG] HAL update.

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	133:d4dda5c437f0	1	/**
mbed_official	133:d4dda5c437f0	2	******************************************************************************
mbed_official	133:d4dda5c437f0	3	* @file stm32f4xx_hal_rcc_ex.h
mbed_official	133:d4dda5c437f0	4	* @author MCD Application Team
mbed_official	242:7074e42da0b2	5	* @version V1.1.0RC2
mbed_official	242:7074e42da0b2	6	* @date 14-May-2014
mbed_official	133:d4dda5c437f0	7	* @brief Header file of RCC HAL Extension module.
mbed_official	133:d4dda5c437f0	8	******************************************************************************
mbed_official	133:d4dda5c437f0	9	* @attention
mbed_official	133:d4dda5c437f0	10	*
mbed_official	133:d4dda5c437f0	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	133:d4dda5c437f0	12	*
mbed_official	133:d4dda5c437f0	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	133:d4dda5c437f0	14	* are permitted provided that the following conditions are met:
mbed_official	133:d4dda5c437f0	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	133:d4dda5c437f0	16	* this list of conditions and the following disclaimer.
mbed_official	133:d4dda5c437f0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	133:d4dda5c437f0	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	133:d4dda5c437f0	19	* and/or other materials provided with the distribution.
mbed_official	133:d4dda5c437f0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	133:d4dda5c437f0	21	* may be used to endorse or promote products derived from this software
mbed_official	133:d4dda5c437f0	22	* without specific prior written permission.
mbed_official	133:d4dda5c437f0	23	*
mbed_official	133:d4dda5c437f0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	133:d4dda5c437f0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	133:d4dda5c437f0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	133:d4dda5c437f0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	133:d4dda5c437f0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	133:d4dda5c437f0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	133:d4dda5c437f0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	133:d4dda5c437f0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	133:d4dda5c437f0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	133:d4dda5c437f0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	133:d4dda5c437f0	34	*
mbed_official	133:d4dda5c437f0	35	******************************************************************************
mbed_official	133:d4dda5c437f0	36	*/
mbed_official	133:d4dda5c437f0	37
mbed_official	133:d4dda5c437f0	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	133:d4dda5c437f0	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
mbed_official	133:d4dda5c437f0	40	#define __STM32F4xx_HAL_RCC_EX_H
mbed_official	133:d4dda5c437f0	41
mbed_official	133:d4dda5c437f0	42	#ifdef __cplusplus
mbed_official	133:d4dda5c437f0	43	extern "C" {
mbed_official	133:d4dda5c437f0	44	#endif
mbed_official	133:d4dda5c437f0	45
mbed_official	133:d4dda5c437f0	46	/* Includes ------------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	47	#include "stm32f4xx_hal_def.h"
mbed_official	133:d4dda5c437f0	48
mbed_official	133:d4dda5c437f0	49	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	133:d4dda5c437f0	50	* @{
mbed_official	133:d4dda5c437f0	51	*/
mbed_official	133:d4dda5c437f0	52
mbed_official	133:d4dda5c437f0	53	/** @addtogroup RCCEx
mbed_official	133:d4dda5c437f0	54	* @{
mbed_official	133:d4dda5c437f0	55	*/
mbed_official	133:d4dda5c437f0	56
mbed_official	133:d4dda5c437f0	57	/* Exported types ------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	58	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	59	/**
mbed_official	133:d4dda5c437f0	60	* @brief PLLI2S Clock structure definition
mbed_official	133:d4dda5c437f0	61	*/
mbed_official	133:d4dda5c437f0	62	typedef struct
mbed_official	133:d4dda5c437f0	63	{
mbed_official	242:7074e42da0b2	64	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official	242:7074e42da0b2	65	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	133:d4dda5c437f0	66	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official	133:d4dda5c437f0	67
mbed_official	242:7074e42da0b2	68	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
mbed_official	242:7074e42da0b2	69	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	133:d4dda5c437f0	70	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official	133:d4dda5c437f0	71
mbed_official	133:d4dda5c437f0	72	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
mbed_official	242:7074e42da0b2	73	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	133:d4dda5c437f0	74	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
mbed_official	133:d4dda5c437f0	75	}RCC_PLLI2SInitTypeDef;
mbed_official	133:d4dda5c437f0	76
mbed_official	133:d4dda5c437f0	77	/**
mbed_official	133:d4dda5c437f0	78	* @brief PLLSAI Clock structure definition
mbed_official	133:d4dda5c437f0	79	*/
mbed_official	133:d4dda5c437f0	80	typedef struct
mbed_official	133:d4dda5c437f0	81	{
mbed_official	133:d4dda5c437f0	82	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official	242:7074e42da0b2	83	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	133:d4dda5c437f0	84	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
mbed_official	133:d4dda5c437f0	85
mbed_official	133:d4dda5c437f0	86	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
mbed_official	242:7074e42da0b2	87	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	133:d4dda5c437f0	88	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
mbed_official	133:d4dda5c437f0	89
mbed_official	133:d4dda5c437f0	90	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
mbed_official	242:7074e42da0b2	91	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	133:d4dda5c437f0	92	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
mbed_official	133:d4dda5c437f0	93
mbed_official	133:d4dda5c437f0	94	}RCC_PLLSAIInitTypeDef;
mbed_official	133:d4dda5c437f0	95	/**
mbed_official	133:d4dda5c437f0	96	* @brief RCC extended clocks structure definition
mbed_official	133:d4dda5c437f0	97	*/
mbed_official	133:d4dda5c437f0	98	typedef struct
mbed_official	133:d4dda5c437f0	99	{
mbed_official	133:d4dda5c437f0	100	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	133:d4dda5c437f0	101	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	133:d4dda5c437f0	102
mbed_official	242:7074e42da0b2	103	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
mbed_official	133:d4dda5c437f0	104	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official	133:d4dda5c437f0	105
mbed_official	242:7074e42da0b2	106	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
mbed_official	133:d4dda5c437f0	107	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
mbed_official	133:d4dda5c437f0	108
mbed_official	242:7074e42da0b2	109	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
mbed_official	133:d4dda5c437f0	110	This parameter must be a number between Min_Data = 1 and Max_Data = 32
mbed_official	133:d4dda5c437f0	111	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
mbed_official	133:d4dda5c437f0	112
mbed_official	133:d4dda5c437f0	113	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
mbed_official	133:d4dda5c437f0	114	This parameter must be a number between Min_Data = 1 and Max_Data = 32
mbed_official	133:d4dda5c437f0	115	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
mbed_official	133:d4dda5c437f0	116
mbed_official	133:d4dda5c437f0	117	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
mbed_official	133:d4dda5c437f0	118	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
mbed_official	133:d4dda5c437f0	119
mbed_official	242:7074e42da0b2	120	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
mbed_official	133:d4dda5c437f0	121	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	133:d4dda5c437f0	122
mbed_official	242:7074e42da0b2	123	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
mbed_official	133:d4dda5c437f0	124	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
mbed_official	133:d4dda5c437f0	125
mbed_official	133:d4dda5c437f0	126	}RCC_PeriphCLKInitTypeDef;
mbed_official	133:d4dda5c437f0	127	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	128
mbed_official	133:d4dda5c437f0	129	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\| defined(STM32F401xC) \|\| defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	130	/**
mbed_official	133:d4dda5c437f0	131	* @brief PLLI2S Clock structure definition
mbed_official	133:d4dda5c437f0	132	*/
mbed_official	133:d4dda5c437f0	133	typedef struct
mbed_official	133:d4dda5c437f0	134	{
mbed_official	242:7074e42da0b2	135	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official	133:d4dda5c437f0	136	This parameter must be a number between Min_Data = 192 and Max_Data = 432
mbed_official	133:d4dda5c437f0	137	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official	133:d4dda5c437f0	138
mbed_official	242:7074e42da0b2	139	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
mbed_official	242:7074e42da0b2	140	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	133:d4dda5c437f0	141	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official	133:d4dda5c437f0	142
mbed_official	133:d4dda5c437f0	143	}RCC_PLLI2SInitTypeDef;
mbed_official	133:d4dda5c437f0	144
mbed_official	133:d4dda5c437f0	145
mbed_official	133:d4dda5c437f0	146	/**
mbed_official	133:d4dda5c437f0	147	* @brief RCC extended clocks structure definition
mbed_official	133:d4dda5c437f0	148	*/
mbed_official	133:d4dda5c437f0	149	typedef struct
mbed_official	133:d4dda5c437f0	150	{
mbed_official	133:d4dda5c437f0	151	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	133:d4dda5c437f0	152	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	133:d4dda5c437f0	153
mbed_official	242:7074e42da0b2	154	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
mbed_official	133:d4dda5c437f0	155	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official	133:d4dda5c437f0	156
mbed_official	242:7074e42da0b2	157	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
mbed_official	133:d4dda5c437f0	158	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	133:d4dda5c437f0	159
mbed_official	133:d4dda5c437f0	160	}RCC_PeriphCLKInitTypeDef;
mbed_official	133:d4dda5c437f0	161	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE */
mbed_official	133:d4dda5c437f0	162	/* Exported constants --------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	163	/** @defgroup RCCEx_Exported_Constants
mbed_official	133:d4dda5c437f0	164	* @{
mbed_official	133:d4dda5c437f0	165	*/
mbed_official	133:d4dda5c437f0	166
mbed_official	133:d4dda5c437f0	167	/** @defgroup RCCEx_Periph_Clock_Selection
mbed_official	133:d4dda5c437f0	168	* @{
mbed_official	133:d4dda5c437f0	169	*/
mbed_official	133:d4dda5c437f0	170	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	171	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	172	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	173	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
mbed_official	133:d4dda5c437f0	174	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
mbed_official	133:d4dda5c437f0	175	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
mbed_official	133:d4dda5c437f0	176	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
mbed_official	133:d4dda5c437f0	177	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
mbed_official	133:d4dda5c437f0	178	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	179
mbed_official	133:d4dda5c437f0	180	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\| defined(STM32F401xC) \|\| defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	181	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
mbed_official	133:d4dda5c437f0	182	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
mbed_official	133:d4dda5c437f0	183	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
mbed_official	133:d4dda5c437f0	184	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE */
mbed_official	133:d4dda5c437f0	185
mbed_official	133:d4dda5c437f0	186	/**
mbed_official	133:d4dda5c437f0	187	* @}
mbed_official	133:d4dda5c437f0	188	*/
mbed_official	133:d4dda5c437f0	189
mbed_official	133:d4dda5c437f0	190	/** @defgroup RCCEx_BitAddress_AliasRegion
mbed_official	133:d4dda5c437f0	191	* @brief RCC registers bit address in the alias region
mbed_official	133:d4dda5c437f0	192	* @{
mbed_official	133:d4dda5c437f0	193	*/
mbed_official	133:d4dda5c437f0	194	/* --- CR Register ---*/
mbed_official	133:d4dda5c437f0	195	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	196	/* Alias word address of PLLSAION bit */
mbed_official	133:d4dda5c437f0	197	#define PLLSAION_BitNumber 0x1C
mbed_official	133:d4dda5c437f0	198	#define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
mbed_official	133:d4dda5c437f0	199
mbed_official	133:d4dda5c437f0	200	/* --- DCKCFGR Register ---*/
mbed_official	133:d4dda5c437f0	201	/* Alias word address of TIMPRE bit */
mbed_official	133:d4dda5c437f0	202	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
mbed_official	133:d4dda5c437f0	203	#define TIMPRE_BitNumber 0x18
mbed_official	133:d4dda5c437f0	204	#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
mbed_official	133:d4dda5c437f0	205	/**
mbed_official	133:d4dda5c437f0	206	* @}
mbed_official	133:d4dda5c437f0	207	*/
mbed_official	133:d4dda5c437f0	208
mbed_official	133:d4dda5c437f0	209	/** @defgroup RCCEx_PLLI2S_Clock_Source
mbed_official	133:d4dda5c437f0	210	* @{
mbed_official	133:d4dda5c437f0	211	*/
mbed_official	133:d4dda5c437f0	212	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
mbed_official	133:d4dda5c437f0	213	/**
mbed_official	133:d4dda5c437f0	214	* @}
mbed_official	133:d4dda5c437f0	215	*/
mbed_official	133:d4dda5c437f0	216
mbed_official	133:d4dda5c437f0	217	/** @defgroup RCCEx_PLLSAI_Clock_Source
mbed_official	133:d4dda5c437f0	218	* @{
mbed_official	133:d4dda5c437f0	219	*/
mbed_official	133:d4dda5c437f0	220	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
mbed_official	133:d4dda5c437f0	221	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
mbed_official	133:d4dda5c437f0	222	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
mbed_official	133:d4dda5c437f0	223	/**
mbed_official	133:d4dda5c437f0	224	* @}
mbed_official	133:d4dda5c437f0	225	*/
mbed_official	133:d4dda5c437f0	226
mbed_official	133:d4dda5c437f0	227	/** @defgroup RCCEx_PLLSAI_DIVQ
mbed_official	133:d4dda5c437f0	228	* @{
mbed_official	133:d4dda5c437f0	229	*/
mbed_official	133:d4dda5c437f0	230	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
mbed_official	133:d4dda5c437f0	231	/**
mbed_official	133:d4dda5c437f0	232	* @}
mbed_official	133:d4dda5c437f0	233	*/
mbed_official	133:d4dda5c437f0	234
mbed_official	133:d4dda5c437f0	235	/** @defgroup RCCEx_PLLI2S_DIVQ
mbed_official	133:d4dda5c437f0	236	* @{
mbed_official	133:d4dda5c437f0	237	*/
mbed_official	133:d4dda5c437f0	238	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
mbed_official	133:d4dda5c437f0	239
mbed_official	133:d4dda5c437f0	240	/**
mbed_official	133:d4dda5c437f0	241	* @}
mbed_official	133:d4dda5c437f0	242	*/
mbed_official	133:d4dda5c437f0	243
mbed_official	133:d4dda5c437f0	244	/** @defgroup RCCEx_PLLSAI_DIVR
mbed_official	133:d4dda5c437f0	245	* @{
mbed_official	133:d4dda5c437f0	246	*/
mbed_official	133:d4dda5c437f0	247	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	248	#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
mbed_official	133:d4dda5c437f0	249	#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
mbed_official	133:d4dda5c437f0	250	#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
mbed_official	133:d4dda5c437f0	251	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
mbed_official	133:d4dda5c437f0	252	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
mbed_official	133:d4dda5c437f0	253	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
mbed_official	133:d4dda5c437f0	254	((VALUE) == RCC_PLLSAIDIVR_16))
mbed_official	133:d4dda5c437f0	255
mbed_official	133:d4dda5c437f0	256	/**
mbed_official	133:d4dda5c437f0	257	* @}
mbed_official	133:d4dda5c437f0	258	*/
mbed_official	133:d4dda5c437f0	259
mbed_official	133:d4dda5c437f0	260	/** @defgroup RCCEx_SAI_BlockA_Clock_Source
mbed_official	133:d4dda5c437f0	261	* @{
mbed_official	133:d4dda5c437f0	262	*/
mbed_official	133:d4dda5c437f0	263	#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	264	#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
mbed_official	133:d4dda5c437f0	265	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
mbed_official	133:d4dda5c437f0	266	/**
mbed_official	133:d4dda5c437f0	267	* @}
mbed_official	133:d4dda5c437f0	268	*/
mbed_official	133:d4dda5c437f0	269
mbed_official	133:d4dda5c437f0	270	/** @defgroup RCCEx_SAI_BlockB_Clock_Source
mbed_official	133:d4dda5c437f0	271	* @{
mbed_official	133:d4dda5c437f0	272	*/
mbed_official	133:d4dda5c437f0	273	#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
mbed_official	133:d4dda5c437f0	274	#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
mbed_official	133:d4dda5c437f0	275	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
mbed_official	133:d4dda5c437f0	276	/**
mbed_official	133:d4dda5c437f0	277	* @}
mbed_official	133:d4dda5c437f0	278	*/
mbed_official	133:d4dda5c437f0	279
mbed_official	133:d4dda5c437f0	280	/** @defgroup RCCEx_TIM_PRescaler_Selection
mbed_official	133:d4dda5c437f0	281	* @{
mbed_official	133:d4dda5c437f0	282	*/
mbed_official	133:d4dda5c437f0	283	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
mbed_official	133:d4dda5c437f0	284	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
mbed_official	133:d4dda5c437f0	285	/**
mbed_official	133:d4dda5c437f0	286	* @}
mbed_official	133:d4dda5c437f0	287	*/
mbed_official	133:d4dda5c437f0	288	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	289	/**
mbed_official	133:d4dda5c437f0	290	* @}
mbed_official	133:d4dda5c437f0	291	*/
mbed_official	133:d4dda5c437f0	292
mbed_official	133:d4dda5c437f0	293	/**
mbed_official	133:d4dda5c437f0	294	* @}
mbed_official	133:d4dda5c437f0	295	*/
mbed_official	133:d4dda5c437f0	296
mbed_official	133:d4dda5c437f0	297	/* Exported macro ------------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	298
mbed_official	133:d4dda5c437f0	299	/** @brief Enables or disables the AHB1 peripheral clock.
mbed_official	133:d4dda5c437f0	300	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	133:d4dda5c437f0	301	* is disabled and the application software has to enable this clock before
mbed_official	133:d4dda5c437f0	302	* using it.
mbed_official	133:d4dda5c437f0	303	*/
mbed_official	133:d4dda5c437f0	304
mbed_official	133:d4dda5c437f0	305	#if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	306	#define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOIEN))
mbed_official	133:d4dda5c437f0	307	#define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOFEN))
mbed_official	133:d4dda5c437f0	308	#define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOGEN))
mbed_official	133:d4dda5c437f0	309	#define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACEN))
mbed_official	133:d4dda5c437f0	310	#define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACTXEN))
mbed_official	133:d4dda5c437f0	311	#define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACRXEN))
mbed_official	133:d4dda5c437f0	312	#define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_ETHMACPTPEN))
mbed_official	133:d4dda5c437f0	313	#define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_OTGHSEN))
mbed_official	133:d4dda5c437f0	314	#define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_OTGHSULPIEN))
mbed_official	133:d4dda5c437f0	315
mbed_official	133:d4dda5c437f0	316	#define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
mbed_official	133:d4dda5c437f0	317	#define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
mbed_official	133:d4dda5c437f0	318	#define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
mbed_official	133:d4dda5c437f0	319	#define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
mbed_official	133:d4dda5c437f0	320	#define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
mbed_official	133:d4dda5c437f0	321	#define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
mbed_official	133:d4dda5c437f0	322	#define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
mbed_official	133:d4dda5c437f0	323	#define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
mbed_official	133:d4dda5c437f0	324	#define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
mbed_official	133:d4dda5c437f0	325	#endif /* !(STM32F401xC && STM32F401xE) */
mbed_official	133:d4dda5c437f0	326
mbed_official	133:d4dda5c437f0	327	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	328	#define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOJEN))
mbed_official	133:d4dda5c437f0	329	#define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOKEN))
mbed_official	133:d4dda5c437f0	330	#define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_DMA2DEN))
mbed_official	133:d4dda5c437f0	331
mbed_official	133:d4dda5c437f0	332	#define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
mbed_official	133:d4dda5c437f0	333	#define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
mbed_official	133:d4dda5c437f0	334	#define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
mbed_official	133:d4dda5c437f0	335	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	336
mbed_official	133:d4dda5c437f0	337	#if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	338	/**
mbed_official	133:d4dda5c437f0	339	* @brief Enable ETHERNET clock.
mbed_official	133:d4dda5c437f0	340	*/
mbed_official	133:d4dda5c437f0	341	#define __ETH_CLK_ENABLE() do { \
mbed_official	133:d4dda5c437f0	342	__ETHMAC_CLK_ENABLE(); \
mbed_official	133:d4dda5c437f0	343	__ETHMACTX_CLK_ENABLE(); \
mbed_official	133:d4dda5c437f0	344	__ETHMACRX_CLK_ENABLE(); \
mbed_official	133:d4dda5c437f0	345	} while(0)
mbed_official	133:d4dda5c437f0	346
mbed_official	133:d4dda5c437f0	347	/**
mbed_official	133:d4dda5c437f0	348	* @brief Disable ETHERNET clock.
mbed_official	133:d4dda5c437f0	349	*/
mbed_official	133:d4dda5c437f0	350	#define __ETH_CLK_DISABLE() do { \
mbed_official	133:d4dda5c437f0	351	__ETHMACTX_CLK_DISABLE(); \
mbed_official	133:d4dda5c437f0	352	__ETHMACRX_CLK_DISABLE(); \
mbed_official	133:d4dda5c437f0	353	__ETHMAC_CLK_DISABLE(); \
mbed_official	133:d4dda5c437f0	354	} while(0)
mbed_official	133:d4dda5c437f0	355	#endif /* !(STM32F401xC && STM32F401xE) */
mbed_official	133:d4dda5c437f0	356
mbed_official	133:d4dda5c437f0	357	/** @brief Enable or disable the AHB2 peripheral clock.
mbed_official	133:d4dda5c437f0	358	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	133:d4dda5c437f0	359	* is disabled and the application software has to enable this clock before
mbed_official	133:d4dda5c437f0	360	* using it.
mbed_official	133:d4dda5c437f0	361	*/
mbed_official	133:d4dda5c437f0	362	#if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	363	#define __DCMI_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_DCMIEN))
mbed_official	133:d4dda5c437f0	364	#define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
mbed_official	133:d4dda5c437f0	365	#endif /* !(STM32F401xC && STM32F401xE) */
mbed_official	133:d4dda5c437f0	366
mbed_official	133:d4dda5c437f0	367	#if defined(STM32F415xx) \|\| defined(STM32F417xx) \|\| defined(STM32F437xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	368	#define __CRYP_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_CRYPEN))
mbed_official	133:d4dda5c437f0	369	#define __HASH_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_HASHEN))
mbed_official	133:d4dda5c437f0	370
mbed_official	133:d4dda5c437f0	371	#define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
mbed_official	133:d4dda5c437f0	372	#define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
mbed_official	133:d4dda5c437f0	373
mbed_official	133:d4dda5c437f0	374	#endif /* STM32F415xx \|\| STM32F417xx \|\| STM32F437xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	375
mbed_official	133:d4dda5c437f0	376	/** @brief Enables or disables the AHB3 peripheral clock.
mbed_official	133:d4dda5c437f0	377	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	133:d4dda5c437f0	378	* is disabled and the application software has to enable this clock before
mbed_official	133:d4dda5c437f0	379	* using it.
mbed_official	133:d4dda5c437f0	380	*/
mbed_official	133:d4dda5c437f0	381	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
mbed_official	133:d4dda5c437f0	382	#define __FSMC_CLK_ENABLE() (RCC->AHB3ENR \|= (RCC_AHB3ENR_FSMCEN))
mbed_official	133:d4dda5c437f0	383	#define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
mbed_official	133:d4dda5c437f0	384	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
mbed_official	133:d4dda5c437f0	385
mbed_official	133:d4dda5c437f0	386	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	387	#define __FMC_CLK_ENABLE() (RCC->AHB3ENR \|= (RCC_AHB3ENR_FMCEN))
mbed_official	133:d4dda5c437f0	388	#define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
mbed_official	133:d4dda5c437f0	389	#endif /* STM32F415xx \|\| STM32F417xx \|\| STM32F437xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	390
mbed_official	133:d4dda5c437f0	391
mbed_official	133:d4dda5c437f0	392	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	133:d4dda5c437f0	393	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	133:d4dda5c437f0	394	* is disabled and the application software has to enable this clock before
mbed_official	133:d4dda5c437f0	395	* using it.
mbed_official	133:d4dda5c437f0	396	*/
mbed_official	133:d4dda5c437f0	397	#if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	398	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
mbed_official	133:d4dda5c437f0	399	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
mbed_official	133:d4dda5c437f0	400	#define __TIM12_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM12EN))
mbed_official	133:d4dda5c437f0	401	#define __TIM13_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM13EN))
mbed_official	133:d4dda5c437f0	402	#define __TIM14_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM14EN))
mbed_official	133:d4dda5c437f0	403	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
mbed_official	133:d4dda5c437f0	404	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
mbed_official	133:d4dda5c437f0	405	#define __UART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART4EN))
mbed_official	133:d4dda5c437f0	406	#define __UART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART5EN))
mbed_official	133:d4dda5c437f0	407	#define __CAN1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CAN1EN))
mbed_official	133:d4dda5c437f0	408	#define __CAN2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CAN2EN))
mbed_official	133:d4dda5c437f0	409	#define __DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
mbed_official	133:d4dda5c437f0	410
mbed_official	133:d4dda5c437f0	411	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official	133:d4dda5c437f0	412	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official	133:d4dda5c437f0	413	#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
mbed_official	133:d4dda5c437f0	414	#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
mbed_official	133:d4dda5c437f0	415	#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official	133:d4dda5c437f0	416	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
mbed_official	133:d4dda5c437f0	417	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
mbed_official	133:d4dda5c437f0	418	#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
mbed_official	133:d4dda5c437f0	419	#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
mbed_official	133:d4dda5c437f0	420	#define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
mbed_official	133:d4dda5c437f0	421	#define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
mbed_official	133:d4dda5c437f0	422	#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official	133:d4dda5c437f0	423	#endif /* !(STM32F401xC && STM32F401xE) */
mbed_official	133:d4dda5c437f0	424
mbed_official	133:d4dda5c437f0	425	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	426	#define __UART7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART7EN))
mbed_official	133:d4dda5c437f0	427	#define __UART8_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART8EN))
mbed_official	133:d4dda5c437f0	428
mbed_official	133:d4dda5c437f0	429	#define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
mbed_official	133:d4dda5c437f0	430	#define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
mbed_official	133:d4dda5c437f0	431	#endif /* STM32F415xx \|\| STM32F417xx \|\| STM32F437xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	432
mbed_official	133:d4dda5c437f0	433	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	133:d4dda5c437f0	434	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	133:d4dda5c437f0	435	* is disabled and the application software has to enable this clock before
mbed_official	133:d4dda5c437f0	436	* using it.
mbed_official	133:d4dda5c437f0	437	*/
mbed_official	133:d4dda5c437f0	438	#if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	439	#define __TIM8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM8EN))
mbed_official	133:d4dda5c437f0	440	#define __ADC2_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC2EN))
mbed_official	133:d4dda5c437f0	441	#define __ADC3_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC3EN))
mbed_official	133:d4dda5c437f0	442
mbed_official	133:d4dda5c437f0	443	#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
mbed_official	133:d4dda5c437f0	444	#define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
mbed_official	133:d4dda5c437f0	445	#define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
mbed_official	133:d4dda5c437f0	446	#endif /* !(STM32F401xC && STM32F401xE) */
mbed_official	133:d4dda5c437f0	447
mbed_official	133:d4dda5c437f0	448	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	449	#define __SPI5_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI5EN))
mbed_official	133:d4dda5c437f0	450	#define __SPI6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI6EN))
mbed_official	133:d4dda5c437f0	451	#define __SAI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SAI1EN))
mbed_official	133:d4dda5c437f0	452	#define __LTDC_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_LTDCEN))
mbed_official	133:d4dda5c437f0	453
mbed_official	133:d4dda5c437f0	454	#define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
mbed_official	133:d4dda5c437f0	455	#define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
mbed_official	133:d4dda5c437f0	456	#define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
mbed_official	133:d4dda5c437f0	457	#define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
mbed_official	133:d4dda5c437f0	458	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	459
mbed_official	133:d4dda5c437f0	460	/** @brief Force or release AHB1 peripheral reset.
mbed_official	133:d4dda5c437f0	461	*/
mbed_official	133:d4dda5c437f0	462	#if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	463	#define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
mbed_official	133:d4dda5c437f0	464	#define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
mbed_official	133:d4dda5c437f0	465	#define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
mbed_official	133:d4dda5c437f0	466	#define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
mbed_official	133:d4dda5c437f0	467	#define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
mbed_official	133:d4dda5c437f0	468
mbed_official	133:d4dda5c437f0	469	#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
mbed_official	133:d4dda5c437f0	470	#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
mbed_official	133:d4dda5c437f0	471	#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
mbed_official	133:d4dda5c437f0	472	#define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
mbed_official	133:d4dda5c437f0	473	#define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
mbed_official	133:d4dda5c437f0	474	#endif /* !STM32F401xC && STM32F401xE */
mbed_official	133:d4dda5c437f0	475
mbed_official	133:d4dda5c437f0	476	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	477	#define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
mbed_official	133:d4dda5c437f0	478	#define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
mbed_official	133:d4dda5c437f0	479	#define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
mbed_official	133:d4dda5c437f0	480
mbed_official	133:d4dda5c437f0	481	#define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
mbed_official	133:d4dda5c437f0	482	#define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
mbed_official	133:d4dda5c437f0	483	#define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
mbed_official	133:d4dda5c437f0	484	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	485
mbed_official	133:d4dda5c437f0	486	/** @brief Force or release AHB2 peripheral reset.
mbed_official	133:d4dda5c437f0	487	*/
mbed_official	133:d4dda5c437f0	488	#if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	489	#define __DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
mbed_official	133:d4dda5c437f0	490	#define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
mbed_official	133:d4dda5c437f0	491	#endif /* !STM32F401xC && STM32F401xE */
mbed_official	133:d4dda5c437f0	492
mbed_official	133:d4dda5c437f0	493	#if defined(STM32F415xx) \|\| defined(STM32F417xx) \|\| defined(STM32F437xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	494	#define __CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
mbed_official	133:d4dda5c437f0	495	#define __HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
mbed_official	133:d4dda5c437f0	496
mbed_official	133:d4dda5c437f0	497	#define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
mbed_official	133:d4dda5c437f0	498	#define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
mbed_official	133:d4dda5c437f0	499
mbed_official	133:d4dda5c437f0	500	#endif /* STM32F415xx \|\| STM32F417xx \|\| STM32F437xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	501
mbed_official	133:d4dda5c437f0	502	/** @brief Force or release AHB3 peripheral reset
mbed_official	133:d4dda5c437f0	503	*/
mbed_official	133:d4dda5c437f0	504	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
mbed_official	133:d4dda5c437f0	505	#define __FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
mbed_official	133:d4dda5c437f0	506	#define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
mbed_official	133:d4dda5c437f0	507	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
mbed_official	133:d4dda5c437f0	508
mbed_official	133:d4dda5c437f0	509	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	510	#define __FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
mbed_official	133:d4dda5c437f0	511	#define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
mbed_official	133:d4dda5c437f0	512	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	513
mbed_official	133:d4dda5c437f0	514	/** @brief Force or release APB1 peripheral reset.
mbed_official	133:d4dda5c437f0	515	*/
mbed_official	133:d4dda5c437f0	516	#if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	517	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
mbed_official	133:d4dda5c437f0	518	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
mbed_official	133:d4dda5c437f0	519	#define __TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
mbed_official	133:d4dda5c437f0	520	#define __TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
mbed_official	133:d4dda5c437f0	521	#define __TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
mbed_official	133:d4dda5c437f0	522	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
mbed_official	133:d4dda5c437f0	523	#define __UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
mbed_official	133:d4dda5c437f0	524	#define __UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
mbed_official	133:d4dda5c437f0	525	#define __CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
mbed_official	133:d4dda5c437f0	526	#define __CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
mbed_official	133:d4dda5c437f0	527	#define __DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
mbed_official	133:d4dda5c437f0	528
mbed_official	133:d4dda5c437f0	529	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official	133:d4dda5c437f0	530	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official	133:d4dda5c437f0	531	#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
mbed_official	133:d4dda5c437f0	532	#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
mbed_official	133:d4dda5c437f0	533	#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official	133:d4dda5c437f0	534	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
mbed_official	133:d4dda5c437f0	535	#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
mbed_official	133:d4dda5c437f0	536	#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
mbed_official	133:d4dda5c437f0	537	#define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
mbed_official	133:d4dda5c437f0	538	#define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
mbed_official	133:d4dda5c437f0	539	#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official	133:d4dda5c437f0	540	#endif /* !STM32F401xC && STM32F401xE */
mbed_official	133:d4dda5c437f0	541
mbed_official	133:d4dda5c437f0	542	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	543	#define __UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
mbed_official	133:d4dda5c437f0	544	#define __UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
mbed_official	133:d4dda5c437f0	545
mbed_official	133:d4dda5c437f0	546	#define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
mbed_official	133:d4dda5c437f0	547	#define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
mbed_official	133:d4dda5c437f0	548	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	549
mbed_official	133:d4dda5c437f0	550	/** @brief Force or release APB2 peripheral reset.
mbed_official	133:d4dda5c437f0	551	*/
mbed_official	133:d4dda5c437f0	552	#if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	553	#define __TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
mbed_official	133:d4dda5c437f0	554	#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
mbed_official	133:d4dda5c437f0	555	#endif /* !STM32F401xC && STM32F401xE */
mbed_official	133:d4dda5c437f0	556
mbed_official	133:d4dda5c437f0	557	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	558	#define __SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
mbed_official	133:d4dda5c437f0	559	#define __SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
mbed_official	133:d4dda5c437f0	560	#define __SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
mbed_official	133:d4dda5c437f0	561	#define __LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
mbed_official	133:d4dda5c437f0	562
mbed_official	133:d4dda5c437f0	563	#define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
mbed_official	133:d4dda5c437f0	564	#define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
mbed_official	133:d4dda5c437f0	565	#define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
mbed_official	133:d4dda5c437f0	566	#define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
mbed_official	133:d4dda5c437f0	567	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	568
mbed_official	133:d4dda5c437f0	569
mbed_official	133:d4dda5c437f0	570	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	133:d4dda5c437f0	571	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	133:d4dda5c437f0	572	* power consumption.
mbed_official	133:d4dda5c437f0	573	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	133:d4dda5c437f0	574	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	133:d4dda5c437f0	575	*/
mbed_official	133:d4dda5c437f0	576	#if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	577	#define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
mbed_official	133:d4dda5c437f0	578	#define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
mbed_official	133:d4dda5c437f0	579	#define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
mbed_official	133:d4dda5c437f0	580	#define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
mbed_official	133:d4dda5c437f0	581	#define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
mbed_official	133:d4dda5c437f0	582	#define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official	133:d4dda5c437f0	583	#define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official	133:d4dda5c437f0	584	#define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official	133:d4dda5c437f0	585	#define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
mbed_official	133:d4dda5c437f0	586	#define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official	133:d4dda5c437f0	587
mbed_official	133:d4dda5c437f0	588	#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
mbed_official	133:d4dda5c437f0	589	#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
mbed_official	133:d4dda5c437f0	590	#define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
mbed_official	133:d4dda5c437f0	591	#define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
mbed_official	133:d4dda5c437f0	592	#define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
mbed_official	133:d4dda5c437f0	593	#define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official	133:d4dda5c437f0	594	#define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official	133:d4dda5c437f0	595	#define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official	133:d4dda5c437f0	596	#define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
mbed_official	133:d4dda5c437f0	597	#define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official	133:d4dda5c437f0	598	#endif /* !STM32F401xC && STM32F401xE */
mbed_official	133:d4dda5c437f0	599
mbed_official	133:d4dda5c437f0	600	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	601	#define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
mbed_official	133:d4dda5c437f0	602	#define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
mbed_official	133:d4dda5c437f0	603	#define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
mbed_official	133:d4dda5c437f0	604	#define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
mbed_official	133:d4dda5c437f0	605
mbed_official	133:d4dda5c437f0	606	#define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
mbed_official	133:d4dda5c437f0	607	#define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
mbed_official	133:d4dda5c437f0	608	#define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
mbed_official	133:d4dda5c437f0	609	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	610
mbed_official	133:d4dda5c437f0	611	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	133:d4dda5c437f0	612	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	133:d4dda5c437f0	613	* power consumption.
mbed_official	133:d4dda5c437f0	614	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	133:d4dda5c437f0	615	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	133:d4dda5c437f0	616	*/
mbed_official	133:d4dda5c437f0	617	#if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	618	#define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
mbed_official	133:d4dda5c437f0	619	#define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
mbed_official	133:d4dda5c437f0	620	#endif /* !STM32F401xC && STM32F401xE */
mbed_official	133:d4dda5c437f0	621
mbed_official	133:d4dda5c437f0	622	#if defined(STM32F415xx) \|\| defined(STM32F417xx) \|\| defined(STM32F437xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	623	#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
mbed_official	133:d4dda5c437f0	624	#define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
mbed_official	133:d4dda5c437f0	625
mbed_official	133:d4dda5c437f0	626	#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
mbed_official	133:d4dda5c437f0	627	#define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
mbed_official	133:d4dda5c437f0	628
mbed_official	133:d4dda5c437f0	629	#endif /* STM32F415xx \|\| STM32F417xx \|\| STM32F437xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	630
mbed_official	133:d4dda5c437f0	631	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
mbed_official	133:d4dda5c437f0	632	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	133:d4dda5c437f0	633	* power consumption.
mbed_official	133:d4dda5c437f0	634	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	133:d4dda5c437f0	635	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	133:d4dda5c437f0	636	*/
mbed_official	133:d4dda5c437f0	637	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
mbed_official	133:d4dda5c437f0	638	#define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
mbed_official	133:d4dda5c437f0	639	#define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
mbed_official	133:d4dda5c437f0	640	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
mbed_official	133:d4dda5c437f0	641
mbed_official	133:d4dda5c437f0	642	#if defined(STM32F415xx) \|\| defined(STM32F417xx) \|\| defined(STM32F437xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	643	#define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
mbed_official	133:d4dda5c437f0	644	#define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
mbed_official	133:d4dda5c437f0	645	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	646
mbed_official	133:d4dda5c437f0	647	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	133:d4dda5c437f0	648	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	133:d4dda5c437f0	649	* power consumption.
mbed_official	133:d4dda5c437f0	650	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	133:d4dda5c437f0	651	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	133:d4dda5c437f0	652	*/
mbed_official	133:d4dda5c437f0	653	#if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	654	#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
mbed_official	133:d4dda5c437f0	655	#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
mbed_official	133:d4dda5c437f0	656	#define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
mbed_official	133:d4dda5c437f0	657	#define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
mbed_official	133:d4dda5c437f0	658	#define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
mbed_official	133:d4dda5c437f0	659	#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
mbed_official	133:d4dda5c437f0	660	#define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
mbed_official	133:d4dda5c437f0	661	#define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
mbed_official	133:d4dda5c437f0	662	#define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
mbed_official	133:d4dda5c437f0	663	#define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
mbed_official	133:d4dda5c437f0	664	#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
mbed_official	133:d4dda5c437f0	665
mbed_official	133:d4dda5c437f0	666	#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
mbed_official	133:d4dda5c437f0	667	#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
mbed_official	133:d4dda5c437f0	668	#define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
mbed_official	133:d4dda5c437f0	669	#define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
mbed_official	133:d4dda5c437f0	670	#define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
mbed_official	133:d4dda5c437f0	671	#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
mbed_official	133:d4dda5c437f0	672	#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
mbed_official	133:d4dda5c437f0	673	#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
mbed_official	133:d4dda5c437f0	674	#define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
mbed_official	133:d4dda5c437f0	675	#define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
mbed_official	133:d4dda5c437f0	676	#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
mbed_official	133:d4dda5c437f0	677	#endif /* !STM32F401xC && STM32F401xE */
mbed_official	133:d4dda5c437f0	678
mbed_official	133:d4dda5c437f0	679	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	680	#define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
mbed_official	133:d4dda5c437f0	681	#define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
mbed_official	133:d4dda5c437f0	682
mbed_official	133:d4dda5c437f0	683	#define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
mbed_official	133:d4dda5c437f0	684	#define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
mbed_official	133:d4dda5c437f0	685	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	686
mbed_official	133:d4dda5c437f0	687	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	133:d4dda5c437f0	688	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	133:d4dda5c437f0	689	* power consumption.
mbed_official	133:d4dda5c437f0	690	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	133:d4dda5c437f0	691	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	133:d4dda5c437f0	692	*/
mbed_official	133:d4dda5c437f0	693	#if !defined(STM32F401xC) && !defined(STM32F401xE)
mbed_official	133:d4dda5c437f0	694	#define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
mbed_official	133:d4dda5c437f0	695	#define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
mbed_official	133:d4dda5c437f0	696	#define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
mbed_official	133:d4dda5c437f0	697
mbed_official	133:d4dda5c437f0	698	#define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
mbed_official	133:d4dda5c437f0	699	#define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
mbed_official	133:d4dda5c437f0	700	#define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
mbed_official	133:d4dda5c437f0	701	#endif /* !STM32F401xC && STM32F401xE */
mbed_official	133:d4dda5c437f0	702
mbed_official	133:d4dda5c437f0	703	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	704	#define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
mbed_official	133:d4dda5c437f0	705	#define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
mbed_official	133:d4dda5c437f0	706	#define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
mbed_official	133:d4dda5c437f0	707	#define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
mbed_official	133:d4dda5c437f0	708
mbed_official	133:d4dda5c437f0	709	#define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
mbed_official	133:d4dda5c437f0	710	#define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
mbed_official	133:d4dda5c437f0	711	#define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
mbed_official	133:d4dda5c437f0	712	#define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
mbed_official	133:d4dda5c437f0	713	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	714
mbed_official	133:d4dda5c437f0	715	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
mbed_official	133:d4dda5c437f0	716
mbed_official	133:d4dda5c437f0	717	/** @brief Macro to configure the Timers clocks prescalers
mbed_official	133:d4dda5c437f0	718	* @note This feature is only available with STM32F429x/439x Devices.
mbed_official	133:d4dda5c437f0	719	* @param __PRESC__ : specifies the Timers clocks prescalers selection
mbed_official	133:d4dda5c437f0	720	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	721	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
mbed_official	133:d4dda5c437f0	722	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
mbed_official	133:d4dda5c437f0	723	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
mbed_official	133:d4dda5c437f0	724	* division by 4 or more.
mbed_official	133:d4dda5c437f0	725	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
mbed_official	133:d4dda5c437f0	726	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
mbed_official	133:d4dda5c437f0	727	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
mbed_official	133:d4dda5c437f0	728	* to division by 8 or more.
mbed_official	133:d4dda5c437f0	729	*/
mbed_official	133:d4dda5c437f0	730	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) DCKCFGR_TIMPRE_BB = (__PRESC__))
mbed_official	133:d4dda5c437f0	731
mbed_official	133:d4dda5c437f0	732	/** @brief Macros to Enable or Disable the PLLISAI.
mbed_official	133:d4dda5c437f0	733	* @note The PLLSAI is only available with STM32F429x/439x Devices.
mbed_official	133:d4dda5c437f0	734	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	133:d4dda5c437f0	735	*/
mbed_official	133:d4dda5c437f0	736	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) CR_PLLSAION_BB = ENABLE)
mbed_official	133:d4dda5c437f0	737	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) CR_PLLSAION_BB = DISABLE)
mbed_official	133:d4dda5c437f0	738
mbed_official	133:d4dda5c437f0	739	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
mbed_official	133:d4dda5c437f0	740	* @note The PLLSAI is only available with STM32F429x/439x Devices.
mbed_official	133:d4dda5c437f0	741	* @note This function must be used only when the PLLSAI is disabled.
mbed_official	133:d4dda5c437f0	742	* @note PLLSAI clock source is common with the main PLL (configured in
mbed_official	133:d4dda5c437f0	743	* RCC_PLLConfig function )
mbed_official	133:d4dda5c437f0	744	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
mbed_official	133:d4dda5c437f0	745	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	133:d4dda5c437f0	746	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
mbed_official	133:d4dda5c437f0	747	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official	133:d4dda5c437f0	748	* @param __PLLSAIQ__: specifies the division factor for SAI1 clock
mbed_official	133:d4dda5c437f0	749	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	133:d4dda5c437f0	750	* @param __PLLSAIR__: specifies the division factor for LTDC clock
mbed_official	133:d4dda5c437f0	751	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	133:d4dda5c437f0	752	*/
mbed_official	133:d4dda5c437f0	753	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) \| ((__PLLSAIQ__) << 24) \| ((__PLLSAIR__) << 28))
mbed_official	133:d4dda5c437f0	754
mbed_official	133:d4dda5c437f0	755	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
mbed_official	133:d4dda5c437f0	756	* @note This macro must be used only when the PLLI2S is disabled.
mbed_official	133:d4dda5c437f0	757	* @note PLLI2S clock source is common with the main PLL (configured in
mbed_official	133:d4dda5c437f0	758	* HAL_RCC_ClockConfig() API)
mbed_official	133:d4dda5c437f0	759	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official	133:d4dda5c437f0	760	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official	133:d4dda5c437f0	761	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
mbed_official	133:d4dda5c437f0	762	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official	133:d4dda5c437f0	763	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
mbed_official	133:d4dda5c437f0	764	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official	133:d4dda5c437f0	765	* @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
mbed_official	133:d4dda5c437f0	766	* and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
mbed_official	133:d4dda5c437f0	767	* @param __PLLI2SR__: specifies the division factor for I2S clock
mbed_official	133:d4dda5c437f0	768	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official	133:d4dda5c437f0	769	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
mbed_official	133:d4dda5c437f0	770	* on the I2S clock frequency.
mbed_official	133:d4dda5c437f0	771	*/
mbed_official	133:d4dda5c437f0	772	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) \| ((__PLLI2SQ__) << 24) \| ((__PLLI2SR__) << 28))
mbed_official	133:d4dda5c437f0	773
mbed_official	133:d4dda5c437f0	774	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
mbed_official	133:d4dda5c437f0	775	* @note The SAI peripheral is only available with STM32F429x/439x Devices.
mbed_official	133:d4dda5c437f0	776	* @note This function must be called before enabling the PLLI2S.
mbed_official	133:d4dda5c437f0	777	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
mbed_official	133:d4dda5c437f0	778	* This parameter must be a number between 1 and 32.
mbed_official	133:d4dda5c437f0	779	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
mbed_official	133:d4dda5c437f0	780	*/
mbed_official	133:d4dda5c437f0	781	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
mbed_official	133:d4dda5c437f0	782
mbed_official	133:d4dda5c437f0	783	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
mbed_official	133:d4dda5c437f0	784	* @note The SAI peripheral is only available with STM32F429x/439x Devices.
mbed_official	133:d4dda5c437f0	785	* @note This function must be called before enabling the PLLSAI.
mbed_official	133:d4dda5c437f0	786	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
mbed_official	133:d4dda5c437f0	787	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
mbed_official	133:d4dda5c437f0	788	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
mbed_official	133:d4dda5c437f0	789	*/
mbed_official	133:d4dda5c437f0	790	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
mbed_official	133:d4dda5c437f0	791
mbed_official	133:d4dda5c437f0	792	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
mbed_official	133:d4dda5c437f0	793	*
mbed_official	133:d4dda5c437f0	794	* @note The LTDC peripheral is only available with STM32F429x/439x Devices.
mbed_official	133:d4dda5c437f0	795	* @note This function must be called before enabling the PLLSAI.
mbed_official	133:d4dda5c437f0	796	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
mbed_official	133:d4dda5c437f0	797	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
mbed_official	133:d4dda5c437f0	798	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
mbed_official	133:d4dda5c437f0	799	*/
mbed_official	133:d4dda5c437f0	800	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
mbed_official	133:d4dda5c437f0	801
mbed_official	133:d4dda5c437f0	802	/** @brief Macro to configure SAI1BlockA clock source selection.
mbed_official	133:d4dda5c437f0	803	* @note The SAI peripheral is only available with STM32F429x/439x Devices.
mbed_official	133:d4dda5c437f0	804	* @note This function must be called before enabling PLLSAI, PLLI2S and
mbed_official	133:d4dda5c437f0	805	* the SAI clock.
mbed_official	133:d4dda5c437f0	806	* @param __SOURCE__: specifies the SAI Block A clock source.
mbed_official	133:d4dda5c437f0	807	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	808	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
mbed_official	133:d4dda5c437f0	809	* as SAI1 Block A clock.
mbed_official	133:d4dda5c437f0	810	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
mbed_official	133:d4dda5c437f0	811	* as SAI1 Block A clock.
mbed_official	133:d4dda5c437f0	812	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
mbed_official	133:d4dda5c437f0	813	* used as SAI1 Block A clock.
mbed_official	133:d4dda5c437f0	814	*/
mbed_official	133:d4dda5c437f0	815	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
mbed_official	133:d4dda5c437f0	816
mbed_official	133:d4dda5c437f0	817	/** @brief Macro to configure SAI1BlockB clock source selection.
mbed_official	133:d4dda5c437f0	818	* @note The SAI peripheral is only available with STM32F429x/439x Devices.
mbed_official	133:d4dda5c437f0	819	* @note This function must be called before enabling PLLSAI, PLLI2S and
mbed_official	133:d4dda5c437f0	820	* the SAI clock.
mbed_official	133:d4dda5c437f0	821	* @param __SOURCE__: specifies the SAI Block B clock source.
mbed_official	133:d4dda5c437f0	822	* This parameter can be one of the following values:
mbed_official	133:d4dda5c437f0	823	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
mbed_official	133:d4dda5c437f0	824	* as SAI1 Block B clock.
mbed_official	133:d4dda5c437f0	825	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
mbed_official	133:d4dda5c437f0	826	* as SAI1 Block B clock.
mbed_official	133:d4dda5c437f0	827	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
mbed_official	133:d4dda5c437f0	828	* used as SAI1 Block B clock.
mbed_official	133:d4dda5c437f0	829	*/
mbed_official	133:d4dda5c437f0	830	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
mbed_official	133:d4dda5c437f0	831
mbed_official	133:d4dda5c437f0	832	/** @brief Enable PLLSAI_RDY interrupt.
mbed_official	133:d4dda5c437f0	833	*/
mbed_official	133:d4dda5c437f0	834	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
mbed_official	133:d4dda5c437f0	835
mbed_official	133:d4dda5c437f0	836	/** @brief Disable PLLSAI_RDY interrupt.
mbed_official	133:d4dda5c437f0	837	*/
mbed_official	133:d4dda5c437f0	838	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
mbed_official	133:d4dda5c437f0	839
mbed_official	133:d4dda5c437f0	840	/** @brief Clear the PLLSAI RDY interrupt pending bits.
mbed_official	133:d4dda5c437f0	841	*/
mbed_official	133:d4dda5c437f0	842	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
mbed_official	133:d4dda5c437f0	843
mbed_official	133:d4dda5c437f0	844	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
mbed_official	133:d4dda5c437f0	845	* @retval The new state (TRUE or FALSE).
mbed_official	133:d4dda5c437f0	846	*/
mbed_official	133:d4dda5c437f0	847	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
mbed_official	133:d4dda5c437f0	848
mbed_official	133:d4dda5c437f0	849	/** @brief Check PLLSAI RDY flag is set or not.
mbed_official	133:d4dda5c437f0	850	* @retval The new state (TRUE or FALSE).
mbed_official	133:d4dda5c437f0	851	*/
mbed_official	133:d4dda5c437f0	852	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
mbed_official	133:d4dda5c437f0	853
mbed_official	133:d4dda5c437f0	854	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	133:d4dda5c437f0	855
mbed_official	133:d4dda5c437f0	856	/* Exported functions --------------------------------------------------------*/
mbed_official	133:d4dda5c437f0	857	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	133:d4dda5c437f0	858	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	133:d4dda5c437f0	859
mbed_official	133:d4dda5c437f0	860	/**
mbed_official	133:d4dda5c437f0	861	* @}
mbed_official	133:d4dda5c437f0	862	*/
mbed_official	133:d4dda5c437f0	863
mbed_official	133:d4dda5c437f0	864	/**
mbed_official	133:d4dda5c437f0	865	* @}
mbed_official	133:d4dda5c437f0	866	*/
mbed_official	133:d4dda5c437f0	867
mbed_official	133:d4dda5c437f0	868	#ifdef __cplusplus
mbed_official	133:d4dda5c437f0	869	}
mbed_official	133:d4dda5c437f0	870	#endif
mbed_official	133:d4dda5c437f0	871
mbed_official	133:d4dda5c437f0	872	#endif /* __STM32F4xx_HAL_RCC_EX_H */
mbed_official	133:d4dda5c437f0	873
mbed_official	133:d4dda5c437f0	874	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	18 Jul 2014
Imports:	22
Forks:	0
Commits:	251
Dependents:	1
Dependencies:	0
Followers:	3

targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc_ex.h@242:7074e42da0b2, 2014-06-27 (annotated)

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