Sigve Sebastian Farstad / mbed-src

mbed w/ spi bug fig

Dependents:   display-puck

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_hal_rcc_ex.c@242:7074e42da0b2, 2014-06-27 (annotated)

Committer:
mbed_official
Date:
Fri Jun 27 07:30:09 2014 +0100
Revision:
242:7074e42da0b2
Parent:
133:d4dda5c437f0 
Synchronized with git revision 124ef5e3add9e74a3221347a3fbeea7c8b3cf353



Full URL: https://github.com/mbedmicro/mbed/commit/124ef5e3add9e74a3221347a3fbeea7c8b3cf353/



[DISCO_F407VG] HAL update.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f4xx_hal_rcc_ex.c
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 242:7074e42da0b2 5 * @version V1.1.0RC2
mbed_official 242:7074e42da0b2 6 * @date 14-May-2014
mbed_official 133:d4dda5c437f0 7 * @brief Extension RCC HAL module driver.
mbed_official 133:d4dda5c437f0 8 * This file provides firmware functions to manage the following
mbed_official 133:d4dda5c437f0 9 * functionalities RCC extension peripheral:
mbed_official 133:d4dda5c437f0 10 * + Extended Peripheral Control functions
mbed_official 133:d4dda5c437f0 11 *
mbed_official 133:d4dda5c437f0 12 ******************************************************************************
mbed_official 133:d4dda5c437f0 13 * @attention
mbed_official 133:d4dda5c437f0 14 *
mbed_official 133:d4dda5c437f0 15 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 16 *
mbed_official 133:d4dda5c437f0 17 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 18 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 19 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 20 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 22 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 23 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 25 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 26 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 27 *
mbed_official 133:d4dda5c437f0 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 38 *
mbed_official 133:d4dda5c437f0 39 ******************************************************************************
mbed_official 133:d4dda5c437f0 40 */
mbed_official 133:d4dda5c437f0 41
mbed_official 133:d4dda5c437f0 42 /* Includes ------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 43 #include "stm32f4xx_hal.h"
mbed_official 133:d4dda5c437f0 44
mbed_official 133:d4dda5c437f0 45 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 133:d4dda5c437f0 46 * @{
mbed_official 133:d4dda5c437f0 47 */
mbed_official 133:d4dda5c437f0 48
mbed_official 133:d4dda5c437f0 49 /** @defgroup RCC
mbed_official 133:d4dda5c437f0 50 * @brief RCC HAL module driver
mbed_official 133:d4dda5c437f0 51 * @{
mbed_official 133:d4dda5c437f0 52 */
mbed_official 133:d4dda5c437f0 53
mbed_official 133:d4dda5c437f0 54 #ifdef HAL_RCC_MODULE_ENABLED
mbed_official 133:d4dda5c437f0 55
mbed_official 133:d4dda5c437f0 56 /* Private typedef -----------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 57 /* Private define ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 58 #define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
mbed_official 133:d4dda5c437f0 59 #define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
mbed_official 133:d4dda5c437f0 60 /* Private macro -------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 61 /* Private variables ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 62 /* Private function prototypes -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 63 /* Private functions ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 64
mbed_official 133:d4dda5c437f0 65 /** @defgroup RCCEx_Private_Functions
mbed_official 133:d4dda5c437f0 66 * @{
mbed_official 133:d4dda5c437f0 67 */
mbed_official 133:d4dda5c437f0 68
mbed_official 133:d4dda5c437f0 69 /** @defgroup RCCEx_Group1 Extended Peripheral Control functions
mbed_official 133:d4dda5c437f0 70 * @brief Extended Peripheral Control functions
mbed_official 133:d4dda5c437f0 71 *
mbed_official 133:d4dda5c437f0 72 @verbatim
mbed_official 133:d4dda5c437f0 73 ===============================================================================
mbed_official 133:d4dda5c437f0 74 ##### Extended Peripheral Control functions #####
mbed_official 133:d4dda5c437f0 75 ===============================================================================
mbed_official 133:d4dda5c437f0 76 [..]
mbed_official 133:d4dda5c437f0 77 This subsection provides a set of functions allowing to control the RCC Clocks
mbed_official 133:d4dda5c437f0 78 frequencies.
mbed_official 133:d4dda5c437f0 79 [..]
mbed_official 133:d4dda5c437f0 80 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
mbed_official 133:d4dda5c437f0 81 select the RTC clock source; in this case the Backup domain will be reset in
mbed_official 133:d4dda5c437f0 82 order to modify the RTC Clock source, as consequence RTC registers (including
mbed_official 133:d4dda5c437f0 83 the backup registers) and RCC_BDCR register are set to their reset values.
mbed_official 133:d4dda5c437f0 84
mbed_official 133:d4dda5c437f0 85 @endverbatim
mbed_official 133:d4dda5c437f0 86 * @{
mbed_official 133:d4dda5c437f0 87 */
mbed_official 133:d4dda5c437f0 88 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 133:d4dda5c437f0 89 /**
mbed_official 133:d4dda5c437f0 90 * @brief Initializes the RCC extended peripherals clocks according to the specified
mbed_official 133:d4dda5c437f0 91 * parameters in the RCC_PeriphCLKInitTypeDef.
mbed_official 133:d4dda5c437f0 92 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official 133:d4dda5c437f0 93 * contains the configuration information for the Extended Peripherals
mbed_official 133:d4dda5c437f0 94 * clocks(I2S, SAI, LTDC RTC and TIM).
mbed_official 133:d4dda5c437f0 95 *
mbed_official 133:d4dda5c437f0 96 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
mbed_official 133:d4dda5c437f0 97 * the RTC clock source; in this case the Backup domain will be reset in
mbed_official 133:d4dda5c437f0 98 * order to modify the RTC Clock source, as consequence RTC registers (including
mbed_official 133:d4dda5c437f0 99 * the backup registers) and RCC_BDCR register are set to their reset values.
mbed_official 133:d4dda5c437f0 100 *
mbed_official 133:d4dda5c437f0 101 * @retval HAL status
mbed_official 133:d4dda5c437f0 102 */
mbed_official 133:d4dda5c437f0 103 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official 133:d4dda5c437f0 104 {
mbed_official 133:d4dda5c437f0 105 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 106 uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 107
mbed_official 133:d4dda5c437f0 108 /* Check the parameters */
mbed_official 133:d4dda5c437f0 109 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
mbed_official 133:d4dda5c437f0 110
mbed_official 133:d4dda5c437f0 111 /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------------*/
mbed_official 133:d4dda5c437f0 112
mbed_official 133:d4dda5c437f0 113 /*----------------------- Common configuration SAI/I2S ---------------------------*/
mbed_official 133:d4dda5c437f0 114 /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
mbed_official 133:d4dda5c437f0 115 factor is common parameters for both peripherals */
mbed_official 133:d4dda5c437f0 116 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
mbed_official 133:d4dda5c437f0 117 (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
mbed_official 133:d4dda5c437f0 118 {
mbed_official 133:d4dda5c437f0 119 /* check for Parameters */
mbed_official 133:d4dda5c437f0 120 assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
mbed_official 133:d4dda5c437f0 121
mbed_official 133:d4dda5c437f0 122 /* Disable the PLLI2S */
mbed_official 133:d4dda5c437f0 123 __HAL_RCC_PLLI2S_DISABLE();
mbed_official 133:d4dda5c437f0 124 /* Get new Timeout value */
mbed_official 133:d4dda5c437f0 125 timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
mbed_official 133:d4dda5c437f0 126 /* Wait till PLLI2S is disabled */
mbed_official 133:d4dda5c437f0 127 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
mbed_official 133:d4dda5c437f0 128 {
mbed_official 133:d4dda5c437f0 129 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 130 {
mbed_official 133:d4dda5c437f0 131 /* return in case of Timeout detected */
mbed_official 133:d4dda5c437f0 132 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 133 }
mbed_official 133:d4dda5c437f0 134 }
mbed_official 133:d4dda5c437f0 135
mbed_official 133:d4dda5c437f0 136 /*---------------------------- I2S configuration -------------------------------*/
mbed_official 133:d4dda5c437f0 137 /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
mbed_official 133:d4dda5c437f0 138 only for I2S configuration */
mbed_official 133:d4dda5c437f0 139 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
mbed_official 133:d4dda5c437f0 140 {
mbed_official 133:d4dda5c437f0 141 /* check for Parameters */
mbed_official 133:d4dda5c437f0 142 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
mbed_official 133:d4dda5c437f0 143 /* Configure the PLLI2S division factors */
mbed_official 133:d4dda5c437f0 144 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
mbed_official 133:d4dda5c437f0 145 /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
mbed_official 133:d4dda5c437f0 146 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
mbed_official 133:d4dda5c437f0 147 }
mbed_official 133:d4dda5c437f0 148
mbed_official 133:d4dda5c437f0 149 /*---------------------------- SAI configuration -------------------------------*/
mbed_official 133:d4dda5c437f0 150 /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
mbed_official 133:d4dda5c437f0 151 be added only for SAI configuration */
mbed_official 133:d4dda5c437f0 152 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
mbed_official 133:d4dda5c437f0 153 {
mbed_official 133:d4dda5c437f0 154 /* Check the PLLI2S division factors */
mbed_official 133:d4dda5c437f0 155 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
mbed_official 133:d4dda5c437f0 156 assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
mbed_official 133:d4dda5c437f0 157
mbed_official 133:d4dda5c437f0 158 /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
mbed_official 133:d4dda5c437f0 159 tmpreg = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official 133:d4dda5c437f0 160 /* Configure the PLLI2S division factors */
mbed_official 133:d4dda5c437f0 161 /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
mbed_official 133:d4dda5c437f0 162 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
mbed_official 133:d4dda5c437f0 163 /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
mbed_official 133:d4dda5c437f0 164 __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg);
mbed_official 133:d4dda5c437f0 165 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
mbed_official 133:d4dda5c437f0 166 __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
mbed_official 133:d4dda5c437f0 167 }
mbed_official 133:d4dda5c437f0 168
mbed_official 133:d4dda5c437f0 169 /* Enable the PLLI2S */
mbed_official 133:d4dda5c437f0 170 __HAL_RCC_PLLI2S_ENABLE();
mbed_official 133:d4dda5c437f0 171 /* Get new Timeout value */
mbed_official 133:d4dda5c437f0 172 timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
mbed_official 133:d4dda5c437f0 173 /* Wait till PLLI2S is ready */
mbed_official 133:d4dda5c437f0 174 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
mbed_official 133:d4dda5c437f0 175 {
mbed_official 133:d4dda5c437f0 176 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 177 {
mbed_official 133:d4dda5c437f0 178 /* return in case of Timeout detected */
mbed_official 133:d4dda5c437f0 179 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 180 }
mbed_official 133:d4dda5c437f0 181 }
mbed_official 133:d4dda5c437f0 182 }
mbed_official 133:d4dda5c437f0 183
mbed_official 133:d4dda5c437f0 184 /*----------------------- SAI/LTDC Configuration (PLLSAI) -------------------------*/
mbed_official 133:d4dda5c437f0 185
mbed_official 133:d4dda5c437f0 186 /*----------------------- Common configuration SAI/LTDC ---------------------------*/
mbed_official 133:d4dda5c437f0 187 /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
mbed_official 133:d4dda5c437f0 188 factor is common parameters for both peripherals */
mbed_official 133:d4dda5c437f0 189 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
mbed_official 133:d4dda5c437f0 190 (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
mbed_official 133:d4dda5c437f0 191 {
mbed_official 133:d4dda5c437f0 192 /* Check the PLLSAI division factors */
mbed_official 133:d4dda5c437f0 193 assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
mbed_official 133:d4dda5c437f0 194
mbed_official 133:d4dda5c437f0 195 /* Disable PLLSAI Clock */
mbed_official 133:d4dda5c437f0 196 __HAL_RCC_PLLSAI_DISABLE();
mbed_official 133:d4dda5c437f0 197 /* Get new Timeout value */
mbed_official 133:d4dda5c437f0 198 timeout = HAL_GetTick() + PLLSAI_TIMEOUT_VALUE;
mbed_official 133:d4dda5c437f0 199 /* Wait till PLLSAI is disabled */
mbed_official 133:d4dda5c437f0 200 while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
mbed_official 133:d4dda5c437f0 201 {
mbed_official 133:d4dda5c437f0 202 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 203 {
mbed_official 133:d4dda5c437f0 204 /* return in case of Timeout detected */
mbed_official 133:d4dda5c437f0 205 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 206 }
mbed_official 133:d4dda5c437f0 207 }
mbed_official 133:d4dda5c437f0 208
mbed_official 133:d4dda5c437f0 209 /*---------------------------- SAI configuration -------------------------------*/
mbed_official 133:d4dda5c437f0 210 /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
mbed_official 133:d4dda5c437f0 211 be added only for SAI configuration */
mbed_official 133:d4dda5c437f0 212 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
mbed_official 133:d4dda5c437f0 213 {
mbed_official 133:d4dda5c437f0 214 assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
mbed_official 133:d4dda5c437f0 215 assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
mbed_official 133:d4dda5c437f0 216
mbed_official 133:d4dda5c437f0 217 /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
mbed_official 133:d4dda5c437f0 218 tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
mbed_official 133:d4dda5c437f0 219 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
mbed_official 133:d4dda5c437f0 220 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
mbed_official 133:d4dda5c437f0 221 /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
mbed_official 133:d4dda5c437f0 222 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg);
mbed_official 133:d4dda5c437f0 223 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
mbed_official 133:d4dda5c437f0 224 __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
mbed_official 133:d4dda5c437f0 225 }
mbed_official 133:d4dda5c437f0 226
mbed_official 133:d4dda5c437f0 227 /*---------------------------- LTDC configuration -------------------------------*/
mbed_official 133:d4dda5c437f0 228 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
mbed_official 133:d4dda5c437f0 229 {
mbed_official 133:d4dda5c437f0 230 assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
mbed_official 133:d4dda5c437f0 231 assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
mbed_official 133:d4dda5c437f0 232
mbed_official 133:d4dda5c437f0 233 /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
mbed_official 133:d4dda5c437f0 234 tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
mbed_official 133:d4dda5c437f0 235 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
mbed_official 133:d4dda5c437f0 236 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
mbed_official 133:d4dda5c437f0 237 /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
mbed_official 133:d4dda5c437f0 238 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg, PeriphClkInit->PLLSAI.PLLSAIR);
mbed_official 133:d4dda5c437f0 239 /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
mbed_official 133:d4dda5c437f0 240 __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
mbed_official 133:d4dda5c437f0 241 }
mbed_official 133:d4dda5c437f0 242 /* Enable PLLSAI Clock */
mbed_official 133:d4dda5c437f0 243 __HAL_RCC_PLLSAI_ENABLE();
mbed_official 133:d4dda5c437f0 244 /* Get new Timeout value */
mbed_official 133:d4dda5c437f0 245 timeout = HAL_GetTick() + PLLSAI_TIMEOUT_VALUE;
mbed_official 133:d4dda5c437f0 246 /* Wait till PLLSAI is ready */
mbed_official 133:d4dda5c437f0 247 while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
mbed_official 133:d4dda5c437f0 248 {
mbed_official 133:d4dda5c437f0 249 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 250 {
mbed_official 133:d4dda5c437f0 251 /* return in case of Timeout detected */
mbed_official 133:d4dda5c437f0 252 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 253 }
mbed_official 133:d4dda5c437f0 254 }
mbed_official 133:d4dda5c437f0 255 }
mbed_official 133:d4dda5c437f0 256
mbed_official 133:d4dda5c437f0 257
mbed_official 133:d4dda5c437f0 258 /*---------------------------- RTC configuration -------------------------------*/
mbed_official 133:d4dda5c437f0 259 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
mbed_official 133:d4dda5c437f0 260 {
mbed_official 133:d4dda5c437f0 261 /* Enable Power Clock*/
mbed_official 133:d4dda5c437f0 262 __PWR_CLK_ENABLE();
mbed_official 133:d4dda5c437f0 263
mbed_official 133:d4dda5c437f0 264 /* Enable write access to Backup domain */
mbed_official 133:d4dda5c437f0 265 PWR->CR |= PWR_CR_DBP;
mbed_official 133:d4dda5c437f0 266
mbed_official 133:d4dda5c437f0 267 /* Wait for Backup domain Write protection disable */
mbed_official 133:d4dda5c437f0 268 timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE;
mbed_official 133:d4dda5c437f0 269
mbed_official 133:d4dda5c437f0 270 while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official 133:d4dda5c437f0 271 {
mbed_official 133:d4dda5c437f0 272 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 273 {
mbed_official 133:d4dda5c437f0 274 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 275 }
mbed_official 133:d4dda5c437f0 276 }
mbed_official 133:d4dda5c437f0 277
mbed_official 133:d4dda5c437f0 278 /* Reset the Backup domain only if the RTC Clock source selction is modified */
mbed_official 133:d4dda5c437f0 279 if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
mbed_official 133:d4dda5c437f0 280 {
mbed_official 133:d4dda5c437f0 281 /* Store the content of BDCR register before the reset of Backup Domain */
mbed_official 133:d4dda5c437f0 282 tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
mbed_official 133:d4dda5c437f0 283 /* RTC Clock selection can be changed only if the Backup Domain is reset */
mbed_official 133:d4dda5c437f0 284 __HAL_RCC_BACKUPRESET_FORCE();
mbed_official 133:d4dda5c437f0 285 __HAL_RCC_BACKUPRESET_RELEASE();
mbed_official 133:d4dda5c437f0 286 /* Restore the Content of BDCR register */
mbed_official 133:d4dda5c437f0 287 RCC->BDCR = tmpreg;
mbed_official 133:d4dda5c437f0 288 }
mbed_official 133:d4dda5c437f0 289
mbed_official 133:d4dda5c437f0 290 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
mbed_official 133:d4dda5c437f0 291 if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
mbed_official 133:d4dda5c437f0 292 {
mbed_official 133:d4dda5c437f0 293 /* Get timeout */
mbed_official 133:d4dda5c437f0 294 timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
mbed_official 133:d4dda5c437f0 295
mbed_official 133:d4dda5c437f0 296 /* Wait till LSE is ready */
mbed_official 133:d4dda5c437f0 297 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official 133:d4dda5c437f0 298 {
mbed_official 133:d4dda5c437f0 299 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 300 {
mbed_official 133:d4dda5c437f0 301 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 302 }
mbed_official 133:d4dda5c437f0 303 }
mbed_official 133:d4dda5c437f0 304 }
mbed_official 133:d4dda5c437f0 305 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
mbed_official 133:d4dda5c437f0 306 }
mbed_official 133:d4dda5c437f0 307
mbed_official 133:d4dda5c437f0 308 /*---------------------------- TIM configuration -------------------------------*/
mbed_official 133:d4dda5c437f0 309 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
mbed_official 133:d4dda5c437f0 310 {
mbed_official 133:d4dda5c437f0 311 __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
mbed_official 133:d4dda5c437f0 312 }
mbed_official 133:d4dda5c437f0 313 return HAL_OK;
mbed_official 133:d4dda5c437f0 314 }
mbed_official 133:d4dda5c437f0 315
mbed_official 133:d4dda5c437f0 316 /**
mbed_official 133:d4dda5c437f0 317 * @brief Configures the RCC_OscInitStruct according to the internal
mbed_official 133:d4dda5c437f0 318 * RCC configuration registers.
mbed_official 242:7074e42da0b2 319 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official 242:7074e42da0b2 320 * will be configured.
mbed_official 133:d4dda5c437f0 321 * @retval None
mbed_official 133:d4dda5c437f0 322 */
mbed_official 133:d4dda5c437f0 323 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official 133:d4dda5c437f0 324 {
mbed_official 133:d4dda5c437f0 325 uint32_t tempreg;
mbed_official 133:d4dda5c437f0 326
mbed_official 133:d4dda5c437f0 327 /* Set all possible values for the extended clock type parameter------------*/
mbed_official 133:d4dda5c437f0 328 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
mbed_official 133:d4dda5c437f0 329
mbed_official 133:d4dda5c437f0 330 /* Get the PLLI2S Clock configuration -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 331 PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
mbed_official 133:d4dda5c437f0 332 PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official 133:d4dda5c437f0 333 PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
mbed_official 133:d4dda5c437f0 334 /* Get the PLLSAI Clock configuration -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 335 PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
mbed_official 133:d4dda5c437f0 336 PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
mbed_official 133:d4dda5c437f0 337 PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
mbed_official 133:d4dda5c437f0 338 /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 339 PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
mbed_official 133:d4dda5c437f0 340 PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
mbed_official 133:d4dda5c437f0 341 PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
mbed_official 133:d4dda5c437f0 342 /* Get the RTC Clock configuration -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 343 tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
mbed_official 133:d4dda5c437f0 344 PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
mbed_official 133:d4dda5c437f0 345
mbed_official 133:d4dda5c437f0 346 if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
mbed_official 133:d4dda5c437f0 347 {
mbed_official 133:d4dda5c437f0 348 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
mbed_official 133:d4dda5c437f0 349 }
mbed_official 133:d4dda5c437f0 350 else
mbed_official 133:d4dda5c437f0 351 {
mbed_official 133:d4dda5c437f0 352 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
mbed_official 133:d4dda5c437f0 353 }
mbed_official 133:d4dda5c437f0 354 }
mbed_official 133:d4dda5c437f0 355 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 133:d4dda5c437f0 356
mbed_official 133:d4dda5c437f0 357 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
mbed_official 133:d4dda5c437f0 358 /**
mbed_official 133:d4dda5c437f0 359 * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
mbed_official 133:d4dda5c437f0 360 * RCC_PeriphCLKInitTypeDef.
mbed_official 133:d4dda5c437f0 361 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official 133:d4dda5c437f0 362 * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
mbed_official 133:d4dda5c437f0 363 *
mbed_official 133:d4dda5c437f0 364 * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
mbed_official 133:d4dda5c437f0 365 * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
mbed_official 133:d4dda5c437f0 366 * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
mbed_official 133:d4dda5c437f0 367 *
mbed_official 133:d4dda5c437f0 368 * @retval HAL status
mbed_official 133:d4dda5c437f0 369 */
mbed_official 133:d4dda5c437f0 370 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official 133:d4dda5c437f0 371 {
mbed_official 133:d4dda5c437f0 372 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 373 uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 374
mbed_official 133:d4dda5c437f0 375 /* Check the parameters */
mbed_official 133:d4dda5c437f0 376 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
mbed_official 133:d4dda5c437f0 377
mbed_official 133:d4dda5c437f0 378 /*---------------------------- I2S configuration -------------------------------*/
mbed_official 133:d4dda5c437f0 379 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
mbed_official 133:d4dda5c437f0 380 {
mbed_official 133:d4dda5c437f0 381 /* check for Parameters */
mbed_official 133:d4dda5c437f0 382 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
mbed_official 133:d4dda5c437f0 383 assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
mbed_official 133:d4dda5c437f0 384
mbed_official 133:d4dda5c437f0 385 /* Disable the PLLI2S */
mbed_official 133:d4dda5c437f0 386 __HAL_RCC_PLLI2S_DISABLE();
mbed_official 133:d4dda5c437f0 387 /* Get new Timeout value */
mbed_official 133:d4dda5c437f0 388 timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
mbed_official 133:d4dda5c437f0 389 /* Wait till PLLI2S is disabled */
mbed_official 133:d4dda5c437f0 390 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
mbed_official 133:d4dda5c437f0 391 {
mbed_official 133:d4dda5c437f0 392 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 393 {
mbed_official 133:d4dda5c437f0 394 /* return in case of Timeout detected */
mbed_official 133:d4dda5c437f0 395 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 396 }
mbed_official 133:d4dda5c437f0 397 }
mbed_official 133:d4dda5c437f0 398 /* Configure the PLLI2S division factors */
mbed_official 133:d4dda5c437f0 399 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
mbed_official 133:d4dda5c437f0 400 /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
mbed_official 133:d4dda5c437f0 401 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
mbed_official 133:d4dda5c437f0 402
mbed_official 133:d4dda5c437f0 403 /* Enable the PLLI2S */
mbed_official 133:d4dda5c437f0 404 __HAL_RCC_PLLI2S_ENABLE();
mbed_official 133:d4dda5c437f0 405 /* Get new Timeout value */
mbed_official 133:d4dda5c437f0 406 timeout = HAL_GetTick() + PLLI2S_TIMEOUT_VALUE;
mbed_official 133:d4dda5c437f0 407 /* Wait till PLLI2S is ready */
mbed_official 133:d4dda5c437f0 408 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
mbed_official 133:d4dda5c437f0 409 {
mbed_official 133:d4dda5c437f0 410 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 411 {
mbed_official 133:d4dda5c437f0 412 /* return in case of Timeout detected */
mbed_official 133:d4dda5c437f0 413 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 414 }
mbed_official 133:d4dda5c437f0 415 }
mbed_official 133:d4dda5c437f0 416 }
mbed_official 133:d4dda5c437f0 417
mbed_official 133:d4dda5c437f0 418 /*---------------------------- RTC configuration -------------------------------*/
mbed_official 133:d4dda5c437f0 419 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
mbed_official 133:d4dda5c437f0 420 {
mbed_official 133:d4dda5c437f0 421 /* Enable Power Clock*/
mbed_official 133:d4dda5c437f0 422 __PWR_CLK_ENABLE();
mbed_official 133:d4dda5c437f0 423
mbed_official 133:d4dda5c437f0 424 /* Enable write access to Backup domain */
mbed_official 133:d4dda5c437f0 425 PWR->CR |= PWR_CR_DBP;
mbed_official 133:d4dda5c437f0 426
mbed_official 133:d4dda5c437f0 427 /* Wait for Backup domain Write protection disable */
mbed_official 133:d4dda5c437f0 428 timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE;
mbed_official 133:d4dda5c437f0 429
mbed_official 133:d4dda5c437f0 430 while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official 133:d4dda5c437f0 431 {
mbed_official 133:d4dda5c437f0 432 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 433 {
mbed_official 133:d4dda5c437f0 434 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 435 }
mbed_official 133:d4dda5c437f0 436 }
mbed_official 133:d4dda5c437f0 437
mbed_official 133:d4dda5c437f0 438 /* Reset the Backup domain only if the RTC Clock source selction is modified */
mbed_official 133:d4dda5c437f0 439 if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
mbed_official 133:d4dda5c437f0 440 {
mbed_official 133:d4dda5c437f0 441 /* Store the content of BDCR register before the reset of Backup Domain */
mbed_official 133:d4dda5c437f0 442 tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
mbed_official 133:d4dda5c437f0 443 /* RTC Clock selection can be changed only if the Backup Domain is reset */
mbed_official 133:d4dda5c437f0 444 __HAL_RCC_BACKUPRESET_FORCE();
mbed_official 133:d4dda5c437f0 445 __HAL_RCC_BACKUPRESET_RELEASE();
mbed_official 133:d4dda5c437f0 446 /* Restore the Content of BDCR register */
mbed_official 133:d4dda5c437f0 447 RCC->BDCR = tmpreg;
mbed_official 133:d4dda5c437f0 448 }
mbed_official 133:d4dda5c437f0 449
mbed_official 133:d4dda5c437f0 450 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
mbed_official 133:d4dda5c437f0 451 if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
mbed_official 133:d4dda5c437f0 452 {
mbed_official 133:d4dda5c437f0 453 /* Get timeout */
mbed_official 133:d4dda5c437f0 454 timeout = HAL_GetTick() + LSE_TIMEOUT_VALUE;
mbed_official 133:d4dda5c437f0 455
mbed_official 133:d4dda5c437f0 456 /* Wait till LSE is ready */
mbed_official 133:d4dda5c437f0 457 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official 133:d4dda5c437f0 458 {
mbed_official 133:d4dda5c437f0 459 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 460 {
mbed_official 133:d4dda5c437f0 461 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 462 }
mbed_official 133:d4dda5c437f0 463 }
mbed_official 133:d4dda5c437f0 464 }
mbed_official 133:d4dda5c437f0 465 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
mbed_official 133:d4dda5c437f0 466 }
mbed_official 133:d4dda5c437f0 467
mbed_official 133:d4dda5c437f0 468 return HAL_OK;
mbed_official 133:d4dda5c437f0 469 }
mbed_official 133:d4dda5c437f0 470
mbed_official 133:d4dda5c437f0 471 /**
mbed_official 133:d4dda5c437f0 472 * @brief Configures the RCC_OscInitStruct according to the internal
mbed_official 133:d4dda5c437f0 473 * RCC configuration registers.
mbed_official 242:7074e42da0b2 474 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official 133:d4dda5c437f0 475 * will be configured.
mbed_official 133:d4dda5c437f0 476 * @retval None
mbed_official 133:d4dda5c437f0 477 */
mbed_official 133:d4dda5c437f0 478 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official 133:d4dda5c437f0 479 {
mbed_official 133:d4dda5c437f0 480 uint32_t tempreg;
mbed_official 133:d4dda5c437f0 481
mbed_official 133:d4dda5c437f0 482 /* Set all possible values for the extended clock type parameter------------*/
mbed_official 133:d4dda5c437f0 483 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
mbed_official 133:d4dda5c437f0 484
mbed_official 133:d4dda5c437f0 485 /* Get the PLLI2S Clock configuration -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 486 PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
mbed_official 133:d4dda5c437f0 487 PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official 133:d4dda5c437f0 488
mbed_official 133:d4dda5c437f0 489 /* Get the RTC Clock configuration -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 490 tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
mbed_official 133:d4dda5c437f0 491 PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
mbed_official 133:d4dda5c437f0 492
mbed_official 133:d4dda5c437f0 493 }
mbed_official 133:d4dda5c437f0 494 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
mbed_official 133:d4dda5c437f0 495 /**
mbed_official 133:d4dda5c437f0 496 * @}
mbed_official 133:d4dda5c437f0 497 */
mbed_official 133:d4dda5c437f0 498
mbed_official 133:d4dda5c437f0 499 /**
mbed_official 133:d4dda5c437f0 500 * @}
mbed_official 133:d4dda5c437f0 501 */
mbed_official 133:d4dda5c437f0 502
mbed_official 133:d4dda5c437f0 503 #endif /* HAL_RCC_MODULE_ENABLED */
mbed_official 133:d4dda5c437f0 504 /**
mbed_official 133:d4dda5c437f0 505 * @}
mbed_official 133:d4dda5c437f0 506 */
mbed_official 133:d4dda5c437f0 507
mbed_official 133:d4dda5c437f0 508 /**
mbed_official 133:d4dda5c437f0 509 * @}
mbed_official 133:d4dda5c437f0 510 */
mbed_official 133:d4dda5c437f0 511
mbed_official 133:d4dda5c437f0 512 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/