Sigve Sebastian Farstad / mbed-src

mbed w/ spi bug fig

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targets/cmsis/TARGET_STM/TARGET_DISCO_F407VG/stm32f4xx_ll_fmc.c@242:7074e42da0b2, 2014-06-27 (annotated)

Committer:
mbed_official
Date:
Fri Jun 27 07:30:09 2014 +0100
Revision:
242:7074e42da0b2
Parent:
133:d4dda5c437f0 
Synchronized with git revision 124ef5e3add9e74a3221347a3fbeea7c8b3cf353



Full URL: https://github.com/mbedmicro/mbed/commit/124ef5e3add9e74a3221347a3fbeea7c8b3cf353/



[DISCO_F407VG] HAL update.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 133:d4dda5c437f0 1 /**
mbed_official 133:d4dda5c437f0 2 ******************************************************************************
mbed_official 133:d4dda5c437f0 3 * @file stm32f4xx_ll_fmc.c
mbed_official 133:d4dda5c437f0 4 * @author MCD Application Team
mbed_official 242:7074e42da0b2 5 * @version V1.1.0RC2
mbed_official 242:7074e42da0b2 6 * @date 14-May-2014
mbed_official 133:d4dda5c437f0 7 * @brief FMC Low Layer HAL module driver.
mbed_official 133:d4dda5c437f0 8 *
mbed_official 133:d4dda5c437f0 9 * This file provides firmware functions to manage the following
mbed_official 133:d4dda5c437f0 10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
mbed_official 133:d4dda5c437f0 11 * + Initialization/de-initialization functions
mbed_official 133:d4dda5c437f0 12 * + Peripheral Control functions
mbed_official 133:d4dda5c437f0 13 * + Peripheral State functions
mbed_official 133:d4dda5c437f0 14 *
mbed_official 133:d4dda5c437f0 15 @verbatim
mbed_official 133:d4dda5c437f0 16 ==============================================================================
mbed_official 133:d4dda5c437f0 17 ##### FMC peripheral features #####
mbed_official 133:d4dda5c437f0 18 ==============================================================================
mbed_official 133:d4dda5c437f0 19 [..] The Flexible memory controller (FMC) includes three memory controllers:
mbed_official 133:d4dda5c437f0 20 (+) The NOR/PSRAM memory controller
mbed_official 133:d4dda5c437f0 21 (+) The NAND/PC Card memory controller
mbed_official 133:d4dda5c437f0 22 (+) The Synchronous DRAM (SDRAM) controller
mbed_official 133:d4dda5c437f0 23
mbed_official 133:d4dda5c437f0 24 [..] The FMC functional block makes the interface with synchronous and asynchronous static
mbed_official 133:d4dda5c437f0 25 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
mbed_official 133:d4dda5c437f0 26 (+) to translate AHB transactions into the appropriate external device protocol
mbed_official 133:d4dda5c437f0 27 (+) to meet the access time requirements of the external memory devices
mbed_official 133:d4dda5c437f0 28
mbed_official 133:d4dda5c437f0 29 [..] All external memories share the addresses, data and control signals with the controller.
mbed_official 133:d4dda5c437f0 30 Each external device is accessed by means of a unique Chip Select. The FMC performs
mbed_official 133:d4dda5c437f0 31 only one access at a time to an external device.
mbed_official 133:d4dda5c437f0 32 The main features of the FMC controller are the following:
mbed_official 133:d4dda5c437f0 33 (+) Interface with static-memory mapped devices including:
mbed_official 133:d4dda5c437f0 34 (++) Static random access memory (SRAM)
mbed_official 133:d4dda5c437f0 35 (++) Read-only memory (ROM)
mbed_official 133:d4dda5c437f0 36 (++) NOR Flash memory/OneNAND Flash memory
mbed_official 133:d4dda5c437f0 37 (++) PSRAM (4 memory banks)
mbed_official 133:d4dda5c437f0 38 (++) 16-bit PC Card compatible devices
mbed_official 133:d4dda5c437f0 39 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
mbed_official 133:d4dda5c437f0 40 data
mbed_official 133:d4dda5c437f0 41 (+) Interface with synchronous DRAM (SDRAM) memories
mbed_official 133:d4dda5c437f0 42 (+) Independent Chip Select control for each memory bank
mbed_official 133:d4dda5c437f0 43 (+) Independent configuration for each memory bank
mbed_official 133:d4dda5c437f0 44
mbed_official 133:d4dda5c437f0 45 @endverbatim
mbed_official 133:d4dda5c437f0 46 ******************************************************************************
mbed_official 133:d4dda5c437f0 47 * @attention
mbed_official 133:d4dda5c437f0 48 *
mbed_official 133:d4dda5c437f0 49 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 133:d4dda5c437f0 50 *
mbed_official 133:d4dda5c437f0 51 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 133:d4dda5c437f0 52 * are permitted provided that the following conditions are met:
mbed_official 133:d4dda5c437f0 53 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 133:d4dda5c437f0 54 * this list of conditions and the following disclaimer.
mbed_official 133:d4dda5c437f0 55 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 133:d4dda5c437f0 56 * this list of conditions and the following disclaimer in the documentation
mbed_official 133:d4dda5c437f0 57 * and/or other materials provided with the distribution.
mbed_official 133:d4dda5c437f0 58 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 133:d4dda5c437f0 59 * may be used to endorse or promote products derived from this software
mbed_official 133:d4dda5c437f0 60 * without specific prior written permission.
mbed_official 133:d4dda5c437f0 61 *
mbed_official 133:d4dda5c437f0 62 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 133:d4dda5c437f0 63 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 133:d4dda5c437f0 64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 133:d4dda5c437f0 65 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 133:d4dda5c437f0 66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 133:d4dda5c437f0 67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 133:d4dda5c437f0 68 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 133:d4dda5c437f0 69 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 133:d4dda5c437f0 70 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 133:d4dda5c437f0 71 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 133:d4dda5c437f0 72 *
mbed_official 133:d4dda5c437f0 73 ******************************************************************************
mbed_official 133:d4dda5c437f0 74 */
mbed_official 133:d4dda5c437f0 75
mbed_official 133:d4dda5c437f0 76 /* Includes ------------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 77 #include "stm32f4xx_hal.h"
mbed_official 133:d4dda5c437f0 78
mbed_official 133:d4dda5c437f0 79 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 133:d4dda5c437f0 80 * @{
mbed_official 133:d4dda5c437f0 81 */
mbed_official 133:d4dda5c437f0 82
mbed_official 133:d4dda5c437f0 83 /** @defgroup FMC
mbed_official 133:d4dda5c437f0 84 * @brief FMC driver modules
mbed_official 133:d4dda5c437f0 85 * @{
mbed_official 133:d4dda5c437f0 86 */
mbed_official 133:d4dda5c437f0 87
mbed_official 133:d4dda5c437f0 88 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
mbed_official 133:d4dda5c437f0 89
mbed_official 133:d4dda5c437f0 90 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 133:d4dda5c437f0 91
mbed_official 133:d4dda5c437f0 92 /* Private typedef -----------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 93 /* Private define ------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 94 /* Private macro -------------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 95 /* Private variables ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 96 /* Private function prototypes -----------------------------------------------*/
mbed_official 133:d4dda5c437f0 97 /* Private functions ---------------------------------------------------------*/
mbed_official 133:d4dda5c437f0 98
mbed_official 133:d4dda5c437f0 99 /** @defgroup FMC_Private_Functions
mbed_official 133:d4dda5c437f0 100 * @{
mbed_official 133:d4dda5c437f0 101 */
mbed_official 133:d4dda5c437f0 102
mbed_official 133:d4dda5c437f0 103 /** @defgroup FMC_NORSRAM Controller functions
mbed_official 133:d4dda5c437f0 104 * @brief NORSRAM Controller functions
mbed_official 133:d4dda5c437f0 105 *
mbed_official 133:d4dda5c437f0 106 @verbatim
mbed_official 133:d4dda5c437f0 107 ==============================================================================
mbed_official 133:d4dda5c437f0 108 ##### How to use NORSRAM device driver #####
mbed_official 133:d4dda5c437f0 109 ==============================================================================
mbed_official 133:d4dda5c437f0 110
mbed_official 133:d4dda5c437f0 111 [..]
mbed_official 133:d4dda5c437f0 112 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
mbed_official 133:d4dda5c437f0 113 to run the NORSRAM external devices.
mbed_official 133:d4dda5c437f0 114
mbed_official 133:d4dda5c437f0 115 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
mbed_official 133:d4dda5c437f0 116 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
mbed_official 133:d4dda5c437f0 117 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
mbed_official 133:d4dda5c437f0 118 (+) FMC NORSRAM bank extended timing configuration using the function
mbed_official 133:d4dda5c437f0 119 FMC_NORSRAM_Extended_Timing_Init()
mbed_official 133:d4dda5c437f0 120 (+) FMC NORSRAM bank enable/disable write operation using the functions
mbed_official 133:d4dda5c437f0 121 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
mbed_official 133:d4dda5c437f0 122
mbed_official 133:d4dda5c437f0 123
mbed_official 133:d4dda5c437f0 124 @endverbatim
mbed_official 133:d4dda5c437f0 125 * @{
mbed_official 133:d4dda5c437f0 126 */
mbed_official 133:d4dda5c437f0 127
mbed_official 133:d4dda5c437f0 128 /** @defgroup HAL_FMC_NORSRAM_Group1 Initialization/de-initialization functions
mbed_official 133:d4dda5c437f0 129 * @brief Initialization and Configuration functions
mbed_official 133:d4dda5c437f0 130 *
mbed_official 133:d4dda5c437f0 131 @verbatim
mbed_official 133:d4dda5c437f0 132 ==============================================================================
mbed_official 133:d4dda5c437f0 133 ##### Initialization and de_initialization functions #####
mbed_official 133:d4dda5c437f0 134 ==============================================================================
mbed_official 133:d4dda5c437f0 135 [..]
mbed_official 133:d4dda5c437f0 136 This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 137 (+) Initialize and configure the FMC NORSRAM interface
mbed_official 133:d4dda5c437f0 138 (+) De-initialize the FMC NORSRAM interface
mbed_official 133:d4dda5c437f0 139 (+) Configure the FMC clock and associated GPIOs
mbed_official 133:d4dda5c437f0 140
mbed_official 133:d4dda5c437f0 141 @endverbatim
mbed_official 133:d4dda5c437f0 142 * @{
mbed_official 133:d4dda5c437f0 143 */
mbed_official 133:d4dda5c437f0 144
mbed_official 133:d4dda5c437f0 145 /**
mbed_official 133:d4dda5c437f0 146 * @brief Initialize the FMC_NORSRAM device according to the specified
mbed_official 133:d4dda5c437f0 147 * control parameters in the FMC_NORSRAM_InitTypeDef
mbed_official 133:d4dda5c437f0 148 * @param Device: Pointer to NORSRAM device instance
mbed_official 133:d4dda5c437f0 149 * @param Init: Pointer to NORSRAM Initialization structure
mbed_official 133:d4dda5c437f0 150 * @retval HAL status
mbed_official 133:d4dda5c437f0 151 */
mbed_official 133:d4dda5c437f0 152 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
mbed_official 133:d4dda5c437f0 153 {
mbed_official 133:d4dda5c437f0 154 uint32_t tmpr = 0;
mbed_official 133:d4dda5c437f0 155
mbed_official 133:d4dda5c437f0 156 /* Check the parameters */
mbed_official 133:d4dda5c437f0 157 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 158 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
mbed_official 133:d4dda5c437f0 159 assert_param(IS_FMC_MUX(Init->DataAddressMux));
mbed_official 133:d4dda5c437f0 160 assert_param(IS_FMC_MEMORY(Init->MemoryType));
mbed_official 133:d4dda5c437f0 161 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
mbed_official 133:d4dda5c437f0 162 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
mbed_official 133:d4dda5c437f0 163 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
mbed_official 133:d4dda5c437f0 164 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
mbed_official 133:d4dda5c437f0 165 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
mbed_official 133:d4dda5c437f0 166 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
mbed_official 133:d4dda5c437f0 167 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
mbed_official 133:d4dda5c437f0 168 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
mbed_official 133:d4dda5c437f0 169 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
mbed_official 133:d4dda5c437f0 170 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
mbed_official 133:d4dda5c437f0 171 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
mbed_official 133:d4dda5c437f0 172
mbed_official 133:d4dda5c437f0 173 /* Set NORSRAM device control parameters */
mbed_official 133:d4dda5c437f0 174 tmpr = (uint32_t)(Init->DataAddressMux |\
mbed_official 133:d4dda5c437f0 175 Init->MemoryType |\
mbed_official 133:d4dda5c437f0 176 Init->MemoryDataWidth |\
mbed_official 133:d4dda5c437f0 177 Init->BurstAccessMode |\
mbed_official 133:d4dda5c437f0 178 Init->WaitSignalPolarity |\
mbed_official 133:d4dda5c437f0 179 Init->WrapMode |\
mbed_official 133:d4dda5c437f0 180 Init->WaitSignalActive |\
mbed_official 133:d4dda5c437f0 181 Init->WriteOperation |\
mbed_official 133:d4dda5c437f0 182 Init->WaitSignal |\
mbed_official 133:d4dda5c437f0 183 Init->ExtendedMode |\
mbed_official 133:d4dda5c437f0 184 Init->AsynchronousWait |\
mbed_official 133:d4dda5c437f0 185 Init->WriteBurst |\
mbed_official 133:d4dda5c437f0 186 Init->ContinuousClock
mbed_official 133:d4dda5c437f0 187 );
mbed_official 133:d4dda5c437f0 188
mbed_official 133:d4dda5c437f0 189 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
mbed_official 133:d4dda5c437f0 190 {
mbed_official 133:d4dda5c437f0 191 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
mbed_official 133:d4dda5c437f0 192 }
mbed_official 133:d4dda5c437f0 193
mbed_official 133:d4dda5c437f0 194 Device->BTCR[Init->NSBank] = tmpr;
mbed_official 133:d4dda5c437f0 195
mbed_official 133:d4dda5c437f0 196 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
mbed_official 133:d4dda5c437f0 197 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
mbed_official 133:d4dda5c437f0 198 {
mbed_official 133:d4dda5c437f0 199 Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
mbed_official 133:d4dda5c437f0 200 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\
mbed_official 133:d4dda5c437f0 201 Init->ContinuousClock);
mbed_official 133:d4dda5c437f0 202 }
mbed_official 133:d4dda5c437f0 203
mbed_official 133:d4dda5c437f0 204 return HAL_OK;
mbed_official 133:d4dda5c437f0 205 }
mbed_official 133:d4dda5c437f0 206
mbed_official 133:d4dda5c437f0 207
mbed_official 133:d4dda5c437f0 208 /**
mbed_official 133:d4dda5c437f0 209 * @brief DeInitialize the FMC_NORSRAM peripheral
mbed_official 133:d4dda5c437f0 210 * @param Device: Pointer to NORSRAM device instance
mbed_official 133:d4dda5c437f0 211 * @param ExDevice: Pointer to NORSRAM extended mode device instance
mbed_official 133:d4dda5c437f0 212 * @param Bank: NORSRAM bank number
mbed_official 133:d4dda5c437f0 213 * @retval HAL status
mbed_official 133:d4dda5c437f0 214 */
mbed_official 133:d4dda5c437f0 215 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
mbed_official 133:d4dda5c437f0 216 {
mbed_official 133:d4dda5c437f0 217 /* Check the parameters */
mbed_official 133:d4dda5c437f0 218 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 219 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
mbed_official 133:d4dda5c437f0 220 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 133:d4dda5c437f0 221
mbed_official 133:d4dda5c437f0 222 /* Disable the FMC_NORSRAM device */
mbed_official 133:d4dda5c437f0 223 __FMC_NORSRAM_DISABLE(Device, Bank);
mbed_official 133:d4dda5c437f0 224
mbed_official 133:d4dda5c437f0 225 /* De-initialize the FMC_NORSRAM device */
mbed_official 133:d4dda5c437f0 226 /* FMC_NORSRAM_BANK1 */
mbed_official 133:d4dda5c437f0 227 if(Bank == FMC_NORSRAM_BANK1)
mbed_official 133:d4dda5c437f0 228 {
mbed_official 133:d4dda5c437f0 229 Device->BTCR[Bank] = 0x000030DB;
mbed_official 133:d4dda5c437f0 230 }
mbed_official 133:d4dda5c437f0 231 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
mbed_official 133:d4dda5c437f0 232 else
mbed_official 133:d4dda5c437f0 233 {
mbed_official 133:d4dda5c437f0 234 Device->BTCR[Bank] = 0x000030D2;
mbed_official 133:d4dda5c437f0 235 }
mbed_official 133:d4dda5c437f0 236
mbed_official 133:d4dda5c437f0 237 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
mbed_official 133:d4dda5c437f0 238 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
mbed_official 133:d4dda5c437f0 239
mbed_official 133:d4dda5c437f0 240 return HAL_OK;
mbed_official 133:d4dda5c437f0 241 }
mbed_official 133:d4dda5c437f0 242
mbed_official 133:d4dda5c437f0 243
mbed_official 133:d4dda5c437f0 244 /**
mbed_official 133:d4dda5c437f0 245 * @brief Initialize the FMC_NORSRAM Timing according to the specified
mbed_official 133:d4dda5c437f0 246 * parameters in the FMC_NORSRAM_TimingTypeDef
mbed_official 133:d4dda5c437f0 247 * @param Device: Pointer to NORSRAM device instance
mbed_official 133:d4dda5c437f0 248 * @param Timing: Pointer to NORSRAM Timing structure
mbed_official 133:d4dda5c437f0 249 * @param Bank: NORSRAM bank number
mbed_official 133:d4dda5c437f0 250 * @retval HAL status
mbed_official 133:d4dda5c437f0 251 */
mbed_official 133:d4dda5c437f0 252 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 133:d4dda5c437f0 253 {
mbed_official 133:d4dda5c437f0 254 uint32_t tmpr = 0;
mbed_official 133:d4dda5c437f0 255
mbed_official 133:d4dda5c437f0 256 /* Check the parameters */
mbed_official 133:d4dda5c437f0 257 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 258 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
mbed_official 133:d4dda5c437f0 259 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
mbed_official 133:d4dda5c437f0 260 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
mbed_official 133:d4dda5c437f0 261 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
mbed_official 133:d4dda5c437f0 262 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
mbed_official 133:d4dda5c437f0 263 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
mbed_official 133:d4dda5c437f0 264 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
mbed_official 133:d4dda5c437f0 265 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 133:d4dda5c437f0 266
mbed_official 133:d4dda5c437f0 267 /* Set FMC_NORSRAM device timing parameters */
mbed_official 133:d4dda5c437f0 268 tmpr = (uint32_t)(Timing->AddressSetupTime |\
mbed_official 133:d4dda5c437f0 269 ((Timing->AddressHoldTime) << 4) |\
mbed_official 133:d4dda5c437f0 270 ((Timing->DataSetupTime) << 8) |\
mbed_official 133:d4dda5c437f0 271 ((Timing->BusTurnAroundDuration) << 16) |\
mbed_official 133:d4dda5c437f0 272 (((Timing->CLKDivision)-1) << 20) |\
mbed_official 133:d4dda5c437f0 273 (((Timing->DataLatency)-2) << 24) |\
mbed_official 133:d4dda5c437f0 274 (Timing->AccessMode)
mbed_official 133:d4dda5c437f0 275 );
mbed_official 133:d4dda5c437f0 276
mbed_official 133:d4dda5c437f0 277 Device->BTCR[Bank + 1] = tmpr;
mbed_official 133:d4dda5c437f0 278
mbed_official 133:d4dda5c437f0 279 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
mbed_official 133:d4dda5c437f0 280 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
mbed_official 133:d4dda5c437f0 281 {
mbed_official 133:d4dda5c437f0 282 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
mbed_official 133:d4dda5c437f0 283 tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
mbed_official 133:d4dda5c437f0 284 Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
mbed_official 133:d4dda5c437f0 285 }
mbed_official 133:d4dda5c437f0 286
mbed_official 133:d4dda5c437f0 287 return HAL_OK;
mbed_official 133:d4dda5c437f0 288 }
mbed_official 133:d4dda5c437f0 289
mbed_official 133:d4dda5c437f0 290 /**
mbed_official 133:d4dda5c437f0 291 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
mbed_official 133:d4dda5c437f0 292 * parameters in the FMC_NORSRAM_TimingTypeDef
mbed_official 133:d4dda5c437f0 293 * @param Device: Pointer to NORSRAM device instance
mbed_official 133:d4dda5c437f0 294 * @param Timing: Pointer to NORSRAM Timing structure
mbed_official 133:d4dda5c437f0 295 * @param Bank: NORSRAM bank number
mbed_official 133:d4dda5c437f0 296 * @retval HAL status
mbed_official 133:d4dda5c437f0 297 */
mbed_official 133:d4dda5c437f0 298 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
mbed_official 133:d4dda5c437f0 299 {
mbed_official 133:d4dda5c437f0 300 /* Check the parameters */
mbed_official 133:d4dda5c437f0 301 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
mbed_official 133:d4dda5c437f0 302
mbed_official 133:d4dda5c437f0 303 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
mbed_official 133:d4dda5c437f0 304 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
mbed_official 133:d4dda5c437f0 305 {
mbed_official 133:d4dda5c437f0 306 /* Check the parameters */
mbed_official 133:d4dda5c437f0 307 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
mbed_official 133:d4dda5c437f0 308 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
mbed_official 133:d4dda5c437f0 309 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
mbed_official 133:d4dda5c437f0 310 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
mbed_official 133:d4dda5c437f0 311 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
mbed_official 133:d4dda5c437f0 312 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
mbed_official 133:d4dda5c437f0 313 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
mbed_official 133:d4dda5c437f0 314 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
mbed_official 133:d4dda5c437f0 315 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 133:d4dda5c437f0 316
mbed_official 133:d4dda5c437f0 317 Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
mbed_official 133:d4dda5c437f0 318 ((Timing->AddressHoldTime) << 4) |\
mbed_official 133:d4dda5c437f0 319 ((Timing->DataSetupTime) << 8) |\
mbed_official 133:d4dda5c437f0 320 ((Timing->BusTurnAroundDuration) << 16) |\
mbed_official 133:d4dda5c437f0 321 (((Timing->CLKDivision)-1) << 20) |\
mbed_official 133:d4dda5c437f0 322 (((Timing->DataLatency)-2) << 24) |\
mbed_official 133:d4dda5c437f0 323 (Timing->AccessMode));
mbed_official 133:d4dda5c437f0 324 }
mbed_official 133:d4dda5c437f0 325 else
mbed_official 133:d4dda5c437f0 326 {
mbed_official 133:d4dda5c437f0 327 Device->BWTR[Bank] = 0x0FFFFFFF;
mbed_official 133:d4dda5c437f0 328 }
mbed_official 133:d4dda5c437f0 329
mbed_official 133:d4dda5c437f0 330 return HAL_OK;
mbed_official 133:d4dda5c437f0 331 }
mbed_official 133:d4dda5c437f0 332
mbed_official 133:d4dda5c437f0 333
mbed_official 133:d4dda5c437f0 334 /**
mbed_official 133:d4dda5c437f0 335 * @}
mbed_official 133:d4dda5c437f0 336 */
mbed_official 133:d4dda5c437f0 337
mbed_official 133:d4dda5c437f0 338
mbed_official 133:d4dda5c437f0 339 /** @defgroup HAL_FMC_NORSRAM_Group3 Control functions
mbed_official 133:d4dda5c437f0 340 * @brief management functions
mbed_official 133:d4dda5c437f0 341 *
mbed_official 133:d4dda5c437f0 342 @verbatim
mbed_official 133:d4dda5c437f0 343 ==============================================================================
mbed_official 133:d4dda5c437f0 344 ##### FMC_NORSRAM Control functions #####
mbed_official 133:d4dda5c437f0 345 ==============================================================================
mbed_official 133:d4dda5c437f0 346 [..]
mbed_official 133:d4dda5c437f0 347 This subsection provides a set of functions allowing to control dynamically
mbed_official 133:d4dda5c437f0 348 the FMC NORSRAM interface.
mbed_official 133:d4dda5c437f0 349
mbed_official 133:d4dda5c437f0 350 @endverbatim
mbed_official 133:d4dda5c437f0 351 * @{
mbed_official 133:d4dda5c437f0 352 */
mbed_official 133:d4dda5c437f0 353
mbed_official 133:d4dda5c437f0 354 /**
mbed_official 133:d4dda5c437f0 355 * @brief Enables dynamically FMC_NORSRAM write operation.
mbed_official 133:d4dda5c437f0 356 * @param Device: Pointer to NORSRAM device instance
mbed_official 133:d4dda5c437f0 357 * @param Bank: NORSRAM bank number
mbed_official 133:d4dda5c437f0 358 * @retval HAL status
mbed_official 133:d4dda5c437f0 359 */
mbed_official 133:d4dda5c437f0 360 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
mbed_official 133:d4dda5c437f0 361 {
mbed_official 133:d4dda5c437f0 362 /* Check the parameters */
mbed_official 133:d4dda5c437f0 363 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 364 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 133:d4dda5c437f0 365
mbed_official 133:d4dda5c437f0 366 /* Enable write operation */
mbed_official 133:d4dda5c437f0 367 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
mbed_official 133:d4dda5c437f0 368
mbed_official 133:d4dda5c437f0 369 return HAL_OK;
mbed_official 133:d4dda5c437f0 370 }
mbed_official 133:d4dda5c437f0 371
mbed_official 133:d4dda5c437f0 372 /**
mbed_official 133:d4dda5c437f0 373 * @brief Disables dynamically FMC_NORSRAM write operation.
mbed_official 133:d4dda5c437f0 374 * @param Device: Pointer to NORSRAM device instance
mbed_official 133:d4dda5c437f0 375 * @param Bank: NORSRAM bank number
mbed_official 133:d4dda5c437f0 376 * @retval HAL status
mbed_official 133:d4dda5c437f0 377 */
mbed_official 133:d4dda5c437f0 378 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
mbed_official 133:d4dda5c437f0 379 {
mbed_official 133:d4dda5c437f0 380 /* Check the parameters */
mbed_official 133:d4dda5c437f0 381 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 382 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 133:d4dda5c437f0 383
mbed_official 133:d4dda5c437f0 384 /* Disable write operation */
mbed_official 133:d4dda5c437f0 385 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
mbed_official 133:d4dda5c437f0 386
mbed_official 133:d4dda5c437f0 387 return HAL_OK;
mbed_official 133:d4dda5c437f0 388 }
mbed_official 133:d4dda5c437f0 389
mbed_official 133:d4dda5c437f0 390 /**
mbed_official 133:d4dda5c437f0 391 * @}
mbed_official 133:d4dda5c437f0 392 */
mbed_official 133:d4dda5c437f0 393
mbed_official 133:d4dda5c437f0 394 /**
mbed_official 133:d4dda5c437f0 395 * @}
mbed_official 133:d4dda5c437f0 396 */
mbed_official 133:d4dda5c437f0 397
mbed_official 133:d4dda5c437f0 398 /** @defgroup FMC_PCCARD Controller functions
mbed_official 133:d4dda5c437f0 399 * @brief PCCARD Controller functions
mbed_official 133:d4dda5c437f0 400 *
mbed_official 133:d4dda5c437f0 401 @verbatim
mbed_official 133:d4dda5c437f0 402 ==============================================================================
mbed_official 133:d4dda5c437f0 403 ##### How to use NAND device driver #####
mbed_official 133:d4dda5c437f0 404 ==============================================================================
mbed_official 133:d4dda5c437f0 405 [..]
mbed_official 133:d4dda5c437f0 406 This driver contains a set of APIs to interface with the FMC NAND banks in order
mbed_official 133:d4dda5c437f0 407 to run the NAND external devices.
mbed_official 133:d4dda5c437f0 408
mbed_official 133:d4dda5c437f0 409 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
mbed_official 133:d4dda5c437f0 410 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
mbed_official 133:d4dda5c437f0 411 (+) FMC NAND bank common space timing configuration using the function
mbed_official 133:d4dda5c437f0 412 FMC_NAND_CommonSpace_Timing_Init()
mbed_official 133:d4dda5c437f0 413 (+) FMC NAND bank attribute space timing configuration using the function
mbed_official 133:d4dda5c437f0 414 FMC_NAND_AttributeSpace_Timing_Init()
mbed_official 133:d4dda5c437f0 415 (+) FMC NAND bank enable/disable ECC correction feature using the functions
mbed_official 133:d4dda5c437f0 416 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
mbed_official 133:d4dda5c437f0 417 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
mbed_official 133:d4dda5c437f0 418
mbed_official 133:d4dda5c437f0 419 @endverbatim
mbed_official 133:d4dda5c437f0 420 * @{
mbed_official 133:d4dda5c437f0 421 */
mbed_official 133:d4dda5c437f0 422
mbed_official 133:d4dda5c437f0 423 /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
mbed_official 133:d4dda5c437f0 424 * @brief Initialization and Configuration functions
mbed_official 133:d4dda5c437f0 425 *
mbed_official 133:d4dda5c437f0 426 @verbatim
mbed_official 133:d4dda5c437f0 427 ==============================================================================
mbed_official 133:d4dda5c437f0 428 ##### Initialization and de_initialization functions #####
mbed_official 133:d4dda5c437f0 429 ==============================================================================
mbed_official 133:d4dda5c437f0 430 [..]
mbed_official 133:d4dda5c437f0 431 This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 432 (+) Initialize and configure the FMC NAND interface
mbed_official 133:d4dda5c437f0 433 (+) De-initialize the FMC NAND interface
mbed_official 133:d4dda5c437f0 434 (+) Configure the FMC clock and associated GPIOs
mbed_official 133:d4dda5c437f0 435
mbed_official 133:d4dda5c437f0 436 @endverbatim
mbed_official 133:d4dda5c437f0 437 * @{
mbed_official 133:d4dda5c437f0 438 */
mbed_official 133:d4dda5c437f0 439
mbed_official 133:d4dda5c437f0 440 /**
mbed_official 133:d4dda5c437f0 441 * @brief Initializes the FMC_NAND device according to the specified
mbed_official 133:d4dda5c437f0 442 * control parameters in the FMC_NAND_HandleTypeDef
mbed_official 133:d4dda5c437f0 443 * @param Device: Pointer to NAND device instance
mbed_official 133:d4dda5c437f0 444 * @param Init: Pointer to NAND Initialization structure
mbed_official 133:d4dda5c437f0 445 * @retval HAL status
mbed_official 133:d4dda5c437f0 446 */
mbed_official 133:d4dda5c437f0 447 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
mbed_official 133:d4dda5c437f0 448 {
mbed_official 133:d4dda5c437f0 449 uint32_t tmppcr = 0;
mbed_official 133:d4dda5c437f0 450
mbed_official 133:d4dda5c437f0 451 /* Check the parameters */
mbed_official 133:d4dda5c437f0 452 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 133:d4dda5c437f0 453 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
mbed_official 133:d4dda5c437f0 454 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
mbed_official 133:d4dda5c437f0 455 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
mbed_official 133:d4dda5c437f0 456 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
mbed_official 133:d4dda5c437f0 457 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
mbed_official 133:d4dda5c437f0 458 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
mbed_official 133:d4dda5c437f0 459 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
mbed_official 133:d4dda5c437f0 460
mbed_official 133:d4dda5c437f0 461 /* Set NAND device control parameters */
mbed_official 133:d4dda5c437f0 462 tmppcr = (uint32_t)(Init->Waitfeature |\
mbed_official 133:d4dda5c437f0 463 FMC_PCR_MEMORY_TYPE_NAND |\
mbed_official 133:d4dda5c437f0 464 Init->MemoryDataWidth |\
mbed_official 133:d4dda5c437f0 465 Init->EccComputation |\
mbed_official 133:d4dda5c437f0 466 Init->ECCPageSize |\
mbed_official 133:d4dda5c437f0 467 ((Init->TCLRSetupTime) << 9) |\
mbed_official 133:d4dda5c437f0 468 ((Init->TARSetupTime) << 13)
mbed_official 133:d4dda5c437f0 469 );
mbed_official 133:d4dda5c437f0 470
mbed_official 133:d4dda5c437f0 471 if(Init->NandBank == FMC_NAND_BANK2)
mbed_official 133:d4dda5c437f0 472 {
mbed_official 133:d4dda5c437f0 473 /* NAND bank 2 registers configuration */
mbed_official 133:d4dda5c437f0 474 Device->PCR2 = tmppcr;
mbed_official 133:d4dda5c437f0 475 }
mbed_official 133:d4dda5c437f0 476 else
mbed_official 133:d4dda5c437f0 477 {
mbed_official 133:d4dda5c437f0 478 /* NAND bank 3 registers configuration */
mbed_official 133:d4dda5c437f0 479 Device->PCR3 = tmppcr;
mbed_official 133:d4dda5c437f0 480 }
mbed_official 133:d4dda5c437f0 481
mbed_official 133:d4dda5c437f0 482 return HAL_OK;
mbed_official 133:d4dda5c437f0 483
mbed_official 133:d4dda5c437f0 484 }
mbed_official 133:d4dda5c437f0 485
mbed_official 133:d4dda5c437f0 486 /**
mbed_official 133:d4dda5c437f0 487 * @brief Initializes the FMC_NAND Common space Timing according to the specified
mbed_official 133:d4dda5c437f0 488 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 133:d4dda5c437f0 489 * @param Device: Pointer to NAND device instance
mbed_official 133:d4dda5c437f0 490 * @param Timing: Pointer to NAND timing structure
mbed_official 133:d4dda5c437f0 491 * @param Bank: NAND bank number
mbed_official 133:d4dda5c437f0 492 * @retval HAL status
mbed_official 133:d4dda5c437f0 493 */
mbed_official 133:d4dda5c437f0 494 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 133:d4dda5c437f0 495 {
mbed_official 133:d4dda5c437f0 496 uint32_t tmppmem = 0;
mbed_official 133:d4dda5c437f0 497
mbed_official 133:d4dda5c437f0 498 /* Check the parameters */
mbed_official 133:d4dda5c437f0 499 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 133:d4dda5c437f0 500 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 133:d4dda5c437f0 501 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 133:d4dda5c437f0 502 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 133:d4dda5c437f0 503 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 133:d4dda5c437f0 504 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 133:d4dda5c437f0 505
mbed_official 133:d4dda5c437f0 506 /* Set FMC_NAND device timing parameters */
mbed_official 133:d4dda5c437f0 507 tmppmem = (uint32_t)(Timing->SetupTime |\
mbed_official 133:d4dda5c437f0 508 ((Timing->WaitSetupTime) << 8) |\
mbed_official 133:d4dda5c437f0 509 ((Timing->HoldSetupTime) << 16) |\
mbed_official 133:d4dda5c437f0 510 ((Timing->HiZSetupTime) << 24)
mbed_official 133:d4dda5c437f0 511 );
mbed_official 133:d4dda5c437f0 512
mbed_official 133:d4dda5c437f0 513 if(Bank == FMC_NAND_BANK2)
mbed_official 133:d4dda5c437f0 514 {
mbed_official 133:d4dda5c437f0 515 /* NAND bank 2 registers configuration */
mbed_official 133:d4dda5c437f0 516 Device->PMEM2 = tmppmem;
mbed_official 133:d4dda5c437f0 517 }
mbed_official 133:d4dda5c437f0 518 else
mbed_official 133:d4dda5c437f0 519 {
mbed_official 133:d4dda5c437f0 520 /* NAND bank 3 registers configuration */
mbed_official 133:d4dda5c437f0 521 Device->PMEM3 = tmppmem;
mbed_official 133:d4dda5c437f0 522 }
mbed_official 133:d4dda5c437f0 523
mbed_official 133:d4dda5c437f0 524 return HAL_OK;
mbed_official 133:d4dda5c437f0 525 }
mbed_official 133:d4dda5c437f0 526
mbed_official 133:d4dda5c437f0 527 /**
mbed_official 133:d4dda5c437f0 528 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
mbed_official 133:d4dda5c437f0 529 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 133:d4dda5c437f0 530 * @param Device: Pointer to NAND device instance
mbed_official 133:d4dda5c437f0 531 * @param Timing: Pointer to NAND timing structure
mbed_official 133:d4dda5c437f0 532 * @param Bank: NAND bank number
mbed_official 133:d4dda5c437f0 533 * @retval HAL status
mbed_official 133:d4dda5c437f0 534 */
mbed_official 133:d4dda5c437f0 535 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 133:d4dda5c437f0 536 {
mbed_official 133:d4dda5c437f0 537 uint32_t tmppatt = 0;
mbed_official 133:d4dda5c437f0 538
mbed_official 133:d4dda5c437f0 539 /* Check the parameters */
mbed_official 133:d4dda5c437f0 540 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 133:d4dda5c437f0 541 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 133:d4dda5c437f0 542 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 133:d4dda5c437f0 543 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 133:d4dda5c437f0 544 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 133:d4dda5c437f0 545 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 133:d4dda5c437f0 546
mbed_official 133:d4dda5c437f0 547 /* Set FMC_NAND device timing parameters */
mbed_official 133:d4dda5c437f0 548 tmppatt = (uint32_t)(Timing->SetupTime |\
mbed_official 133:d4dda5c437f0 549 ((Timing->WaitSetupTime) << 8) |\
mbed_official 133:d4dda5c437f0 550 ((Timing->HoldSetupTime) << 16) |\
mbed_official 133:d4dda5c437f0 551 ((Timing->HiZSetupTime) << 24)
mbed_official 133:d4dda5c437f0 552 );
mbed_official 133:d4dda5c437f0 553
mbed_official 133:d4dda5c437f0 554 if(Bank == FMC_NAND_BANK2)
mbed_official 133:d4dda5c437f0 555 {
mbed_official 133:d4dda5c437f0 556 /* NAND bank 2 registers configuration */
mbed_official 133:d4dda5c437f0 557 Device->PATT2 = tmppatt;
mbed_official 133:d4dda5c437f0 558 }
mbed_official 133:d4dda5c437f0 559 else
mbed_official 133:d4dda5c437f0 560 {
mbed_official 133:d4dda5c437f0 561 /* NAND bank 3 registers configuration */
mbed_official 133:d4dda5c437f0 562 Device->PATT3 = tmppatt;
mbed_official 133:d4dda5c437f0 563 }
mbed_official 133:d4dda5c437f0 564
mbed_official 133:d4dda5c437f0 565 return HAL_OK;
mbed_official 133:d4dda5c437f0 566 }
mbed_official 133:d4dda5c437f0 567
mbed_official 133:d4dda5c437f0 568
mbed_official 133:d4dda5c437f0 569 /**
mbed_official 133:d4dda5c437f0 570 * @brief DeInitializes the FMC_NAND device
mbed_official 133:d4dda5c437f0 571 * @param Device: Pointer to NAND device instance
mbed_official 133:d4dda5c437f0 572 * @param Bank: NAND bank number
mbed_official 133:d4dda5c437f0 573 * @retval HAL status
mbed_official 133:d4dda5c437f0 574 */
mbed_official 133:d4dda5c437f0 575 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
mbed_official 133:d4dda5c437f0 576 {
mbed_official 133:d4dda5c437f0 577 /* Check the parameters */
mbed_official 133:d4dda5c437f0 578 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 133:d4dda5c437f0 579 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 133:d4dda5c437f0 580
mbed_official 133:d4dda5c437f0 581 /* Disable the NAND Bank */
mbed_official 133:d4dda5c437f0 582 __FMC_NAND_DISABLE(Device, Bank);
mbed_official 133:d4dda5c437f0 583
mbed_official 133:d4dda5c437f0 584 /* De-initialize the NAND Bank */
mbed_official 133:d4dda5c437f0 585 if(Bank == FMC_NAND_BANK2)
mbed_official 133:d4dda5c437f0 586 {
mbed_official 133:d4dda5c437f0 587 /* Set the FMC_NAND_BANK2 registers to their reset values */
mbed_official 133:d4dda5c437f0 588 Device->PCR2 = 0x00000018;
mbed_official 133:d4dda5c437f0 589 Device->SR2 = 0x00000040;
mbed_official 133:d4dda5c437f0 590 Device->PMEM2 = 0xFCFCFCFC;
mbed_official 133:d4dda5c437f0 591 Device->PATT2 = 0xFCFCFCFC;
mbed_official 133:d4dda5c437f0 592 }
mbed_official 133:d4dda5c437f0 593 /* FMC_Bank3_NAND */
mbed_official 133:d4dda5c437f0 594 else
mbed_official 133:d4dda5c437f0 595 {
mbed_official 133:d4dda5c437f0 596 /* Set the FMC_NAND_BANK3 registers to their reset values */
mbed_official 133:d4dda5c437f0 597 Device->PCR3 = 0x00000018;
mbed_official 133:d4dda5c437f0 598 Device->SR3 = 0x00000040;
mbed_official 133:d4dda5c437f0 599 Device->PMEM3 = 0xFCFCFCFC;
mbed_official 133:d4dda5c437f0 600 Device->PATT3 = 0xFCFCFCFC;
mbed_official 133:d4dda5c437f0 601 }
mbed_official 133:d4dda5c437f0 602
mbed_official 133:d4dda5c437f0 603 return HAL_OK;
mbed_official 133:d4dda5c437f0 604 }
mbed_official 133:d4dda5c437f0 605
mbed_official 133:d4dda5c437f0 606 /**
mbed_official 133:d4dda5c437f0 607 * @}
mbed_official 133:d4dda5c437f0 608 */
mbed_official 133:d4dda5c437f0 609
mbed_official 133:d4dda5c437f0 610
mbed_official 133:d4dda5c437f0 611 /** @defgroup HAL_FMC_NAND_Group3 Control functions
mbed_official 133:d4dda5c437f0 612 * @brief management functions
mbed_official 133:d4dda5c437f0 613 *
mbed_official 133:d4dda5c437f0 614 @verbatim
mbed_official 133:d4dda5c437f0 615 ==============================================================================
mbed_official 133:d4dda5c437f0 616 ##### FMC_NAND Control functions #####
mbed_official 133:d4dda5c437f0 617 ==============================================================================
mbed_official 133:d4dda5c437f0 618 [..]
mbed_official 133:d4dda5c437f0 619 This subsection provides a set of functions allowing to control dynamically
mbed_official 133:d4dda5c437f0 620 the FMC NAND interface.
mbed_official 133:d4dda5c437f0 621
mbed_official 133:d4dda5c437f0 622 @endverbatim
mbed_official 133:d4dda5c437f0 623 * @{
mbed_official 133:d4dda5c437f0 624 */
mbed_official 133:d4dda5c437f0 625
mbed_official 133:d4dda5c437f0 626
mbed_official 133:d4dda5c437f0 627 /**
mbed_official 133:d4dda5c437f0 628 * @brief Enables dynamically FMC_NAND ECC feature.
mbed_official 133:d4dda5c437f0 629 * @param Device: Pointer to NAND device instance
mbed_official 133:d4dda5c437f0 630 * @param Bank: NAND bank number
mbed_official 133:d4dda5c437f0 631 * @retval HAL status
mbed_official 133:d4dda5c437f0 632 */
mbed_official 133:d4dda5c437f0 633 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
mbed_official 133:d4dda5c437f0 634 {
mbed_official 133:d4dda5c437f0 635 /* Check the parameters */
mbed_official 133:d4dda5c437f0 636 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 133:d4dda5c437f0 637 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 133:d4dda5c437f0 638
mbed_official 133:d4dda5c437f0 639 /* Enable ECC feature */
mbed_official 133:d4dda5c437f0 640 if(Bank == FMC_NAND_BANK2)
mbed_official 133:d4dda5c437f0 641 {
mbed_official 133:d4dda5c437f0 642 Device->PCR2 |= FMC_PCR2_ECCEN;
mbed_official 133:d4dda5c437f0 643 }
mbed_official 133:d4dda5c437f0 644 else
mbed_official 133:d4dda5c437f0 645 {
mbed_official 133:d4dda5c437f0 646 Device->PCR3 |= FMC_PCR3_ECCEN;
mbed_official 133:d4dda5c437f0 647 }
mbed_official 133:d4dda5c437f0 648
mbed_official 133:d4dda5c437f0 649 return HAL_OK;
mbed_official 133:d4dda5c437f0 650 }
mbed_official 133:d4dda5c437f0 651
mbed_official 133:d4dda5c437f0 652
mbed_official 133:d4dda5c437f0 653 /**
mbed_official 133:d4dda5c437f0 654 * @brief Disables dynamically FMC_NAND ECC feature.
mbed_official 133:d4dda5c437f0 655 * @param Device: Pointer to NAND device instance
mbed_official 133:d4dda5c437f0 656 * @param Bank: NAND bank number
mbed_official 133:d4dda5c437f0 657 * @retval HAL status
mbed_official 133:d4dda5c437f0 658 */
mbed_official 133:d4dda5c437f0 659 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
mbed_official 133:d4dda5c437f0 660 {
mbed_official 133:d4dda5c437f0 661 /* Check the parameters */
mbed_official 133:d4dda5c437f0 662 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 133:d4dda5c437f0 663 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 133:d4dda5c437f0 664
mbed_official 133:d4dda5c437f0 665 /* Disable ECC feature */
mbed_official 133:d4dda5c437f0 666 if(Bank == FMC_NAND_BANK2)
mbed_official 133:d4dda5c437f0 667 {
mbed_official 133:d4dda5c437f0 668 Device->PCR2 &= ~FMC_PCR2_ECCEN;
mbed_official 133:d4dda5c437f0 669 }
mbed_official 133:d4dda5c437f0 670 else
mbed_official 133:d4dda5c437f0 671 {
mbed_official 133:d4dda5c437f0 672 Device->PCR3 &= ~FMC_PCR3_ECCEN;
mbed_official 133:d4dda5c437f0 673 }
mbed_official 133:d4dda5c437f0 674
mbed_official 133:d4dda5c437f0 675 return HAL_OK;
mbed_official 133:d4dda5c437f0 676 }
mbed_official 133:d4dda5c437f0 677
mbed_official 133:d4dda5c437f0 678 /**
mbed_official 133:d4dda5c437f0 679 * @brief Disables dynamically FMC_NAND ECC feature.
mbed_official 133:d4dda5c437f0 680 * @param Device: Pointer to NAND device instance
mbed_official 133:d4dda5c437f0 681 * @param ECCval: Pointer to ECC value
mbed_official 133:d4dda5c437f0 682 * @param Bank: NAND bank number
mbed_official 133:d4dda5c437f0 683 * @param Timeout: Timeout wait value
mbed_official 133:d4dda5c437f0 684 * @retval HAL status
mbed_official 133:d4dda5c437f0 685 */
mbed_official 133:d4dda5c437f0 686 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 687 {
mbed_official 133:d4dda5c437f0 688 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 689
mbed_official 133:d4dda5c437f0 690 /* Check the parameters */
mbed_official 133:d4dda5c437f0 691 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 133:d4dda5c437f0 692 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 133:d4dda5c437f0 693
mbed_official 133:d4dda5c437f0 694 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 695
mbed_official 133:d4dda5c437f0 696 /* Wait untill FIFO is empty */
mbed_official 133:d4dda5c437f0 697 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT))
mbed_official 133:d4dda5c437f0 698 {
mbed_official 133:d4dda5c437f0 699 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 700 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 701 {
mbed_official 133:d4dda5c437f0 702 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 703 {
mbed_official 133:d4dda5c437f0 704 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 705 }
mbed_official 133:d4dda5c437f0 706 }
mbed_official 133:d4dda5c437f0 707 }
mbed_official 133:d4dda5c437f0 708
mbed_official 133:d4dda5c437f0 709 if(Bank == FMC_NAND_BANK2)
mbed_official 133:d4dda5c437f0 710 {
mbed_official 133:d4dda5c437f0 711 /* Get the ECCR2 register value */
mbed_official 133:d4dda5c437f0 712 *ECCval = (uint32_t)Device->ECCR2;
mbed_official 133:d4dda5c437f0 713 }
mbed_official 133:d4dda5c437f0 714 else
mbed_official 133:d4dda5c437f0 715 {
mbed_official 133:d4dda5c437f0 716 /* Get the ECCR3 register value */
mbed_official 133:d4dda5c437f0 717 *ECCval = (uint32_t)Device->ECCR3;
mbed_official 133:d4dda5c437f0 718 }
mbed_official 133:d4dda5c437f0 719
mbed_official 133:d4dda5c437f0 720 return HAL_OK;
mbed_official 133:d4dda5c437f0 721 }
mbed_official 133:d4dda5c437f0 722
mbed_official 133:d4dda5c437f0 723 /**
mbed_official 133:d4dda5c437f0 724 * @}
mbed_official 133:d4dda5c437f0 725 */
mbed_official 133:d4dda5c437f0 726
mbed_official 133:d4dda5c437f0 727 /**
mbed_official 133:d4dda5c437f0 728 * @}
mbed_official 133:d4dda5c437f0 729 */
mbed_official 133:d4dda5c437f0 730
mbed_official 133:d4dda5c437f0 731 /** @defgroup FMC_PCCARD Controller functions
mbed_official 133:d4dda5c437f0 732 * @brief PCCARD Controller functions
mbed_official 133:d4dda5c437f0 733 *
mbed_official 133:d4dda5c437f0 734 @verbatim
mbed_official 133:d4dda5c437f0 735 ==============================================================================
mbed_official 133:d4dda5c437f0 736 ##### How to use PCCARD device driver #####
mbed_official 133:d4dda5c437f0 737 ==============================================================================
mbed_official 133:d4dda5c437f0 738 [..]
mbed_official 133:d4dda5c437f0 739 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
mbed_official 133:d4dda5c437f0 740 to run the PCCARD/compact flash external devices.
mbed_official 133:d4dda5c437f0 741
mbed_official 133:d4dda5c437f0 742 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
mbed_official 133:d4dda5c437f0 743 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
mbed_official 133:d4dda5c437f0 744 (+) FMC PCCARD bank common space timing configuration using the function
mbed_official 133:d4dda5c437f0 745 FMC_PCCARD_CommonSpace_Timing_Init()
mbed_official 133:d4dda5c437f0 746 (+) FMC PCCARD bank attribute space timing configuration using the function
mbed_official 133:d4dda5c437f0 747 FMC_PCCARD_AttributeSpace_Timing_Init()
mbed_official 133:d4dda5c437f0 748 (+) FMC PCCARD bank IO space timing configuration using the function
mbed_official 133:d4dda5c437f0 749 FMC_PCCARD_IOSpace_Timing_Init()
mbed_official 133:d4dda5c437f0 750
mbed_official 133:d4dda5c437f0 751
mbed_official 133:d4dda5c437f0 752 @endverbatim
mbed_official 133:d4dda5c437f0 753 * @{
mbed_official 133:d4dda5c437f0 754 */
mbed_official 133:d4dda5c437f0 755
mbed_official 133:d4dda5c437f0 756 /** @defgroup HAL_FMC_PCCARD_Group1 Initialization/de-initialization functions
mbed_official 133:d4dda5c437f0 757 * @brief Initialization and Configuration functions
mbed_official 133:d4dda5c437f0 758 *
mbed_official 133:d4dda5c437f0 759 @verbatim
mbed_official 133:d4dda5c437f0 760 ==============================================================================
mbed_official 133:d4dda5c437f0 761 ##### Initialization and de_initialization functions #####
mbed_official 133:d4dda5c437f0 762 ==============================================================================
mbed_official 133:d4dda5c437f0 763 [..]
mbed_official 133:d4dda5c437f0 764 This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 765 (+) Initialize and configure the FMC PCCARD interface
mbed_official 133:d4dda5c437f0 766 (+) De-initialize the FMC PCCARD interface
mbed_official 133:d4dda5c437f0 767 (+) Configure the FMC clock and associated GPIOs
mbed_official 133:d4dda5c437f0 768
mbed_official 133:d4dda5c437f0 769 @endverbatim
mbed_official 133:d4dda5c437f0 770 * @{
mbed_official 133:d4dda5c437f0 771 */
mbed_official 133:d4dda5c437f0 772
mbed_official 133:d4dda5c437f0 773 /**
mbed_official 133:d4dda5c437f0 774 * @brief Initializes the FMC_PCCARD device according to the specified
mbed_official 133:d4dda5c437f0 775 * control parameters in the FMC_PCCARD_HandleTypeDef
mbed_official 133:d4dda5c437f0 776 * @param Device: Pointer to PCCARD device instance
mbed_official 133:d4dda5c437f0 777 * @param Init: Pointer to PCCARD Initialization structure
mbed_official 133:d4dda5c437f0 778 * @retval HAL status
mbed_official 133:d4dda5c437f0 779 */
mbed_official 133:d4dda5c437f0 780 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
mbed_official 133:d4dda5c437f0 781 {
mbed_official 133:d4dda5c437f0 782 /* Check the parameters */
mbed_official 133:d4dda5c437f0 783 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 133:d4dda5c437f0 784 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
mbed_official 133:d4dda5c437f0 785 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
mbed_official 133:d4dda5c437f0 786 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
mbed_official 133:d4dda5c437f0 787
mbed_official 133:d4dda5c437f0 788 /* Set FMC_PCCARD device control parameters */
mbed_official 133:d4dda5c437f0 789 Device->PCR4 = (uint32_t)(Init->Waitfeature |\
mbed_official 133:d4dda5c437f0 790 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
mbed_official 133:d4dda5c437f0 791 (Init->TCLRSetupTime << 9) |\
mbed_official 133:d4dda5c437f0 792 (Init->TARSetupTime << 13));
mbed_official 133:d4dda5c437f0 793
mbed_official 133:d4dda5c437f0 794 return HAL_OK;
mbed_official 133:d4dda5c437f0 795
mbed_official 133:d4dda5c437f0 796 }
mbed_official 133:d4dda5c437f0 797
mbed_official 133:d4dda5c437f0 798 /**
mbed_official 133:d4dda5c437f0 799 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
mbed_official 133:d4dda5c437f0 800 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 133:d4dda5c437f0 801 * @param Device: Pointer to PCCARD device instance
mbed_official 133:d4dda5c437f0 802 * @param Timing: Pointer to PCCARD timing structure
mbed_official 133:d4dda5c437f0 803 * @retval HAL status
mbed_official 133:d4dda5c437f0 804 */
mbed_official 133:d4dda5c437f0 805 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
mbed_official 133:d4dda5c437f0 806 {
mbed_official 133:d4dda5c437f0 807 /* Check the parameters */
mbed_official 133:d4dda5c437f0 808 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 133:d4dda5c437f0 809 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 133:d4dda5c437f0 810 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 133:d4dda5c437f0 811 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 133:d4dda5c437f0 812 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 133:d4dda5c437f0 813
mbed_official 133:d4dda5c437f0 814 /* Set PCCARD timing parameters */
mbed_official 133:d4dda5c437f0 815 Device->PMEM4 = (uint32_t)((Timing->SetupTime |\
mbed_official 133:d4dda5c437f0 816 ((Timing->WaitSetupTime) << 8) |\
mbed_official 133:d4dda5c437f0 817 (Timing->HoldSetupTime) << 16) |\
mbed_official 133:d4dda5c437f0 818 ((Timing->HiZSetupTime) << 24)
mbed_official 133:d4dda5c437f0 819 );
mbed_official 133:d4dda5c437f0 820
mbed_official 133:d4dda5c437f0 821 return HAL_OK;
mbed_official 133:d4dda5c437f0 822 }
mbed_official 133:d4dda5c437f0 823
mbed_official 133:d4dda5c437f0 824 /**
mbed_official 133:d4dda5c437f0 825 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
mbed_official 133:d4dda5c437f0 826 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 133:d4dda5c437f0 827 * @param Device: Pointer to PCCARD device instance
mbed_official 133:d4dda5c437f0 828 * @param Timing: Pointer to PCCARD timing structure
mbed_official 133:d4dda5c437f0 829 * @retval HAL status
mbed_official 133:d4dda5c437f0 830 */
mbed_official 133:d4dda5c437f0 831 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
mbed_official 133:d4dda5c437f0 832 {
mbed_official 133:d4dda5c437f0 833 /* Check the parameters */
mbed_official 133:d4dda5c437f0 834 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 133:d4dda5c437f0 835 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 133:d4dda5c437f0 836 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 133:d4dda5c437f0 837 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 133:d4dda5c437f0 838 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 133:d4dda5c437f0 839
mbed_official 133:d4dda5c437f0 840 /* Set PCCARD timing parameters */
mbed_official 133:d4dda5c437f0 841 Device->PATT4 = (uint32_t)((Timing->SetupTime |\
mbed_official 133:d4dda5c437f0 842 ((Timing->WaitSetupTime) << 8) |\
mbed_official 133:d4dda5c437f0 843 (Timing->HoldSetupTime) << 16) |\
mbed_official 133:d4dda5c437f0 844 ((Timing->HiZSetupTime) << 24)
mbed_official 133:d4dda5c437f0 845 );
mbed_official 133:d4dda5c437f0 846
mbed_official 133:d4dda5c437f0 847 return HAL_OK;
mbed_official 133:d4dda5c437f0 848 }
mbed_official 133:d4dda5c437f0 849
mbed_official 133:d4dda5c437f0 850 /**
mbed_official 133:d4dda5c437f0 851 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
mbed_official 133:d4dda5c437f0 852 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 133:d4dda5c437f0 853 * @param Device: Pointer to PCCARD device instance
mbed_official 133:d4dda5c437f0 854 * @param Timing: Pointer to PCCARD timing structure
mbed_official 133:d4dda5c437f0 855 * @retval HAL status
mbed_official 133:d4dda5c437f0 856 */
mbed_official 133:d4dda5c437f0 857 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
mbed_official 133:d4dda5c437f0 858 {
mbed_official 133:d4dda5c437f0 859 /* Check the parameters */
mbed_official 133:d4dda5c437f0 860 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 133:d4dda5c437f0 861 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 133:d4dda5c437f0 862 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 133:d4dda5c437f0 863 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 133:d4dda5c437f0 864 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 133:d4dda5c437f0 865
mbed_official 133:d4dda5c437f0 866 /* Set FMC_PCCARD device timing parameters */
mbed_official 133:d4dda5c437f0 867 Device->PIO4 = (uint32_t)((Timing->SetupTime |\
mbed_official 133:d4dda5c437f0 868 ((Timing->WaitSetupTime) << 8) |\
mbed_official 133:d4dda5c437f0 869 (Timing->HoldSetupTime) << 16) |\
mbed_official 133:d4dda5c437f0 870 ((Timing->HiZSetupTime) << 24)
mbed_official 133:d4dda5c437f0 871 );
mbed_official 133:d4dda5c437f0 872
mbed_official 133:d4dda5c437f0 873 return HAL_OK;
mbed_official 133:d4dda5c437f0 874 }
mbed_official 133:d4dda5c437f0 875
mbed_official 133:d4dda5c437f0 876 /**
mbed_official 133:d4dda5c437f0 877 * @brief DeInitializes the FMC_PCCARD device
mbed_official 133:d4dda5c437f0 878 * @param Device: Pointer to PCCARD device instance
mbed_official 133:d4dda5c437f0 879 * @retval HAL status
mbed_official 133:d4dda5c437f0 880 */
mbed_official 133:d4dda5c437f0 881 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
mbed_official 133:d4dda5c437f0 882 {
mbed_official 133:d4dda5c437f0 883 /* Check the parameters */
mbed_official 133:d4dda5c437f0 884 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 133:d4dda5c437f0 885
mbed_official 133:d4dda5c437f0 886 /* Disable the FMC_PCCARD device */
mbed_official 133:d4dda5c437f0 887 __FMC_PCCARD_DISABLE(Device);
mbed_official 133:d4dda5c437f0 888
mbed_official 133:d4dda5c437f0 889 /* De-initialize the FMC_PCCARD device */
mbed_official 133:d4dda5c437f0 890 Device->PCR4 = 0x00000018;
mbed_official 133:d4dda5c437f0 891 Device->SR4 = 0x00000000;
mbed_official 133:d4dda5c437f0 892 Device->PMEM4 = 0xFCFCFCFC;
mbed_official 133:d4dda5c437f0 893 Device->PATT4 = 0xFCFCFCFC;
mbed_official 133:d4dda5c437f0 894 Device->PIO4 = 0xFCFCFCFC;
mbed_official 133:d4dda5c437f0 895
mbed_official 133:d4dda5c437f0 896 return HAL_OK;
mbed_official 133:d4dda5c437f0 897 }
mbed_official 133:d4dda5c437f0 898
mbed_official 133:d4dda5c437f0 899 /**
mbed_official 133:d4dda5c437f0 900 * @}
mbed_official 133:d4dda5c437f0 901 */
mbed_official 133:d4dda5c437f0 902
mbed_official 133:d4dda5c437f0 903
mbed_official 133:d4dda5c437f0 904 /** @defgroup FMC_SDRAM Controller functions
mbed_official 133:d4dda5c437f0 905 * @brief SDRAM Controller functions
mbed_official 133:d4dda5c437f0 906 *
mbed_official 133:d4dda5c437f0 907 @verbatim
mbed_official 133:d4dda5c437f0 908 ==============================================================================
mbed_official 133:d4dda5c437f0 909 ##### How to use SDRAM device driver #####
mbed_official 133:d4dda5c437f0 910 ==============================================================================
mbed_official 133:d4dda5c437f0 911 [..]
mbed_official 133:d4dda5c437f0 912 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
mbed_official 133:d4dda5c437f0 913 to run the SDRAM external devices.
mbed_official 133:d4dda5c437f0 914
mbed_official 133:d4dda5c437f0 915 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
mbed_official 133:d4dda5c437f0 916 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
mbed_official 133:d4dda5c437f0 917 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
mbed_official 133:d4dda5c437f0 918 (+) FMC SDRAM bank enable/disable write operation using the functions
mbed_official 133:d4dda5c437f0 919 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
mbed_official 133:d4dda5c437f0 920 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
mbed_official 133:d4dda5c437f0 921
mbed_official 133:d4dda5c437f0 922 @endverbatim
mbed_official 133:d4dda5c437f0 923 * @{
mbed_official 133:d4dda5c437f0 924 */
mbed_official 133:d4dda5c437f0 925
mbed_official 133:d4dda5c437f0 926 /** @defgroup HAL_FMC_SDRAM_Group1 Initialization/de-initialization functions
mbed_official 133:d4dda5c437f0 927 * @brief Initialization and Configuration functions
mbed_official 133:d4dda5c437f0 928 *
mbed_official 133:d4dda5c437f0 929 @verbatim
mbed_official 133:d4dda5c437f0 930 ==============================================================================
mbed_official 133:d4dda5c437f0 931 ##### Initialization and de_initialization functions #####
mbed_official 133:d4dda5c437f0 932 ==============================================================================
mbed_official 133:d4dda5c437f0 933 [..]
mbed_official 133:d4dda5c437f0 934 This section provides functions allowing to:
mbed_official 133:d4dda5c437f0 935 (+) Initialize and configure the FMC SDRAM interface
mbed_official 133:d4dda5c437f0 936 (+) De-initialize the FMC SDRAM interface
mbed_official 133:d4dda5c437f0 937 (+) Configure the FMC clock and associated GPIOs
mbed_official 133:d4dda5c437f0 938
mbed_official 133:d4dda5c437f0 939 @endverbatim
mbed_official 133:d4dda5c437f0 940 * @{
mbed_official 133:d4dda5c437f0 941 */
mbed_official 133:d4dda5c437f0 942
mbed_official 133:d4dda5c437f0 943 /**
mbed_official 133:d4dda5c437f0 944 * @brief Initializes the FMC_SDRAM device according to the specified
mbed_official 133:d4dda5c437f0 945 * control parameters in the FMC_SDRAM_InitTypeDef
mbed_official 133:d4dda5c437f0 946 * @param Device: Pointer to SDRAM device instance
mbed_official 133:d4dda5c437f0 947 * @param Init: Pointer to SDRAM Initialization structure
mbed_official 133:d4dda5c437f0 948 * @retval HAL status
mbed_official 133:d4dda5c437f0 949 */
mbed_official 133:d4dda5c437f0 950 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
mbed_official 133:d4dda5c437f0 951 {
mbed_official 133:d4dda5c437f0 952 uint32_t tmpr1 = 0;
mbed_official 133:d4dda5c437f0 953 uint32_t tmpr2 = 0;
mbed_official 133:d4dda5c437f0 954
mbed_official 133:d4dda5c437f0 955 /* Check the parameters */
mbed_official 133:d4dda5c437f0 956 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 957 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
mbed_official 133:d4dda5c437f0 958 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
mbed_official 133:d4dda5c437f0 959 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
mbed_official 133:d4dda5c437f0 960 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
mbed_official 133:d4dda5c437f0 961 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
mbed_official 133:d4dda5c437f0 962 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
mbed_official 133:d4dda5c437f0 963 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
mbed_official 133:d4dda5c437f0 964 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
mbed_official 133:d4dda5c437f0 965 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
mbed_official 133:d4dda5c437f0 966 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
mbed_official 133:d4dda5c437f0 967
mbed_official 133:d4dda5c437f0 968 /* Set SDRAM bank configuration parameters */
mbed_official 133:d4dda5c437f0 969 if (Init->SDBank != FMC_SDRAM_BANK2)
mbed_official 133:d4dda5c437f0 970 {
mbed_official 133:d4dda5c437f0 971 Device->SDCR[FMC_SDRAM_BANK1] = (uint32_t)(Init->ColumnBitsNumber |\
mbed_official 133:d4dda5c437f0 972 Init->RowBitsNumber |\
mbed_official 133:d4dda5c437f0 973 Init->MemoryDataWidth |\
mbed_official 133:d4dda5c437f0 974 Init->InternalBankNumber |\
mbed_official 133:d4dda5c437f0 975 Init->CASLatency |\
mbed_official 133:d4dda5c437f0 976 Init->WriteProtection |\
mbed_official 133:d4dda5c437f0 977 Init->SDClockPeriod |\
mbed_official 133:d4dda5c437f0 978 Init->ReadBurst |\
mbed_official 133:d4dda5c437f0 979 Init->ReadPipeDelay
mbed_official 133:d4dda5c437f0 980 );
mbed_official 133:d4dda5c437f0 981 }
mbed_official 133:d4dda5c437f0 982 else /* FMC_Bank2_SDRAM */
mbed_official 133:d4dda5c437f0 983 {
mbed_official 133:d4dda5c437f0 984 tmpr1 = (uint32_t)(Init->SDClockPeriod |\
mbed_official 133:d4dda5c437f0 985 Init->ReadBurst |\
mbed_official 133:d4dda5c437f0 986 Init->ReadPipeDelay
mbed_official 133:d4dda5c437f0 987 );
mbed_official 133:d4dda5c437f0 988
mbed_official 133:d4dda5c437f0 989 tmpr2 = (uint32_t)(Init->ColumnBitsNumber |\
mbed_official 133:d4dda5c437f0 990 Init->RowBitsNumber |\
mbed_official 133:d4dda5c437f0 991 Init->MemoryDataWidth |\
mbed_official 133:d4dda5c437f0 992 Init->InternalBankNumber |\
mbed_official 133:d4dda5c437f0 993 Init->CASLatency |\
mbed_official 133:d4dda5c437f0 994 Init->WriteProtection
mbed_official 133:d4dda5c437f0 995 );
mbed_official 133:d4dda5c437f0 996
mbed_official 133:d4dda5c437f0 997 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
mbed_official 133:d4dda5c437f0 998 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
mbed_official 133:d4dda5c437f0 999 }
mbed_official 133:d4dda5c437f0 1000
mbed_official 133:d4dda5c437f0 1001 return HAL_OK;
mbed_official 133:d4dda5c437f0 1002 }
mbed_official 133:d4dda5c437f0 1003
mbed_official 133:d4dda5c437f0 1004 /**
mbed_official 133:d4dda5c437f0 1005 * @brief Initializes the FMC_SDRAM device timing according to the specified
mbed_official 133:d4dda5c437f0 1006 * parameters in the FMC_SDRAM_TimingTypeDef
mbed_official 133:d4dda5c437f0 1007 * @param Device: Pointer to SDRAM device instance
mbed_official 133:d4dda5c437f0 1008 * @param Timing: Pointer to SDRAM Timing structure
mbed_official 133:d4dda5c437f0 1009 * @param Bank: SDRAM bank number
mbed_official 133:d4dda5c437f0 1010 * @retval HAL status
mbed_official 133:d4dda5c437f0 1011 */
mbed_official 133:d4dda5c437f0 1012 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 133:d4dda5c437f0 1013 {
mbed_official 133:d4dda5c437f0 1014 uint32_t tmpr1 = 0;
mbed_official 133:d4dda5c437f0 1015 uint32_t tmpr2 = 0;
mbed_official 133:d4dda5c437f0 1016
mbed_official 133:d4dda5c437f0 1017 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1018 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 1019 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
mbed_official 133:d4dda5c437f0 1020 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
mbed_official 133:d4dda5c437f0 1021 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
mbed_official 133:d4dda5c437f0 1022 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
mbed_official 133:d4dda5c437f0 1023 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
mbed_official 133:d4dda5c437f0 1024 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
mbed_official 133:d4dda5c437f0 1025 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
mbed_official 133:d4dda5c437f0 1026 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 133:d4dda5c437f0 1027
mbed_official 133:d4dda5c437f0 1028 /* Set SDRAM device timing parameters */
mbed_official 133:d4dda5c437f0 1029 if (Bank != FMC_SDRAM_BANK2)
mbed_official 133:d4dda5c437f0 1030 {
mbed_official 133:d4dda5c437f0 1031 Device->SDTR[FMC_SDRAM_BANK1] = (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
mbed_official 133:d4dda5c437f0 1032 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
mbed_official 133:d4dda5c437f0 1033 (((Timing->SelfRefreshTime)-1) << 8) |\
mbed_official 133:d4dda5c437f0 1034 (((Timing->RowCycleDelay)-1) << 12) |\
mbed_official 133:d4dda5c437f0 1035 (((Timing->WriteRecoveryTime)-1) <<16) |\
mbed_official 133:d4dda5c437f0 1036 (((Timing->RPDelay)-1) << 20) |\
mbed_official 133:d4dda5c437f0 1037 (((Timing->RCDDelay)-1) << 24)
mbed_official 133:d4dda5c437f0 1038 );
mbed_official 133:d4dda5c437f0 1039 }
mbed_official 133:d4dda5c437f0 1040 else /* FMC_Bank2_SDRAM */
mbed_official 133:d4dda5c437f0 1041 {
mbed_official 133:d4dda5c437f0 1042
mbed_official 133:d4dda5c437f0 1043 tmpr1 = (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
mbed_official 133:d4dda5c437f0 1044 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
mbed_official 133:d4dda5c437f0 1045 (((Timing->SelfRefreshTime)-1) << 8) |\
mbed_official 133:d4dda5c437f0 1046 (((Timing->WriteRecoveryTime)-1) <<16) |\
mbed_official 133:d4dda5c437f0 1047 (((Timing->RCDDelay)-1) << 24)
mbed_official 133:d4dda5c437f0 1048 );
mbed_official 133:d4dda5c437f0 1049
mbed_official 133:d4dda5c437f0 1050 tmpr2 = (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
mbed_official 133:d4dda5c437f0 1051 (((Timing->RPDelay)-1) << 20)
mbed_official 133:d4dda5c437f0 1052 );
mbed_official 133:d4dda5c437f0 1053
mbed_official 133:d4dda5c437f0 1054 Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
mbed_official 133:d4dda5c437f0 1055 Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
mbed_official 133:d4dda5c437f0 1056 }
mbed_official 133:d4dda5c437f0 1057
mbed_official 133:d4dda5c437f0 1058 return HAL_OK;
mbed_official 133:d4dda5c437f0 1059 }
mbed_official 133:d4dda5c437f0 1060
mbed_official 133:d4dda5c437f0 1061 /**
mbed_official 133:d4dda5c437f0 1062 * @brief DeInitializes the FMC_SDRAM peripheral
mbed_official 133:d4dda5c437f0 1063 * @param Device: Pointer to SDRAM device instance
mbed_official 133:d4dda5c437f0 1064 * @retval HAL status
mbed_official 133:d4dda5c437f0 1065 */
mbed_official 133:d4dda5c437f0 1066 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 133:d4dda5c437f0 1067 {
mbed_official 133:d4dda5c437f0 1068 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1069 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 1070 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 133:d4dda5c437f0 1071
mbed_official 133:d4dda5c437f0 1072 /* De-initialize the SDRAM device */
mbed_official 133:d4dda5c437f0 1073 Device->SDCR[Bank] = 0x000002D0;
mbed_official 133:d4dda5c437f0 1074 Device->SDTR[Bank] = 0x0FFFFFFF;
mbed_official 133:d4dda5c437f0 1075 Device->SDCMR = 0x00000000;
mbed_official 133:d4dda5c437f0 1076 Device->SDRTR = 0x00000000;
mbed_official 133:d4dda5c437f0 1077 Device->SDSR = 0x00000000;
mbed_official 133:d4dda5c437f0 1078
mbed_official 133:d4dda5c437f0 1079 return HAL_OK;
mbed_official 133:d4dda5c437f0 1080 }
mbed_official 133:d4dda5c437f0 1081
mbed_official 133:d4dda5c437f0 1082 /**
mbed_official 133:d4dda5c437f0 1083 * @}
mbed_official 133:d4dda5c437f0 1084 */
mbed_official 133:d4dda5c437f0 1085
mbed_official 133:d4dda5c437f0 1086
mbed_official 133:d4dda5c437f0 1087 /** @defgroup HAL_FMC_SDRAM_Group3 Control functions
mbed_official 133:d4dda5c437f0 1088 * @brief management functions
mbed_official 133:d4dda5c437f0 1089 *
mbed_official 133:d4dda5c437f0 1090 @verbatim
mbed_official 133:d4dda5c437f0 1091 ==============================================================================
mbed_official 133:d4dda5c437f0 1092 ##### FMC_SDRAM Control functions #####
mbed_official 133:d4dda5c437f0 1093 ==============================================================================
mbed_official 133:d4dda5c437f0 1094 [..]
mbed_official 133:d4dda5c437f0 1095 This subsection provides a set of functions allowing to control dynamically
mbed_official 133:d4dda5c437f0 1096 the FMC SDRAM interface.
mbed_official 133:d4dda5c437f0 1097
mbed_official 133:d4dda5c437f0 1098 @endverbatim
mbed_official 133:d4dda5c437f0 1099 * @{
mbed_official 133:d4dda5c437f0 1100 */
mbed_official 133:d4dda5c437f0 1101
mbed_official 133:d4dda5c437f0 1102 /**
mbed_official 133:d4dda5c437f0 1103 * @brief Enables dynamically FMC_SDRAM write protection.
mbed_official 133:d4dda5c437f0 1104 * @param Device: Pointer to SDRAM device instance
mbed_official 133:d4dda5c437f0 1105 * @param Bank: SDRAM bank number
mbed_official 133:d4dda5c437f0 1106 * @retval HAL status
mbed_official 133:d4dda5c437f0 1107 */
mbed_official 133:d4dda5c437f0 1108 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 133:d4dda5c437f0 1109 {
mbed_official 133:d4dda5c437f0 1110 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1111 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 1112 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 133:d4dda5c437f0 1113
mbed_official 133:d4dda5c437f0 1114 /* Enable write protection */
mbed_official 133:d4dda5c437f0 1115 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
mbed_official 133:d4dda5c437f0 1116
mbed_official 133:d4dda5c437f0 1117 return HAL_OK;
mbed_official 133:d4dda5c437f0 1118 }
mbed_official 133:d4dda5c437f0 1119
mbed_official 133:d4dda5c437f0 1120 /**
mbed_official 133:d4dda5c437f0 1121 * @brief Disables dynamically FMC_SDRAM write protection.
mbed_official 133:d4dda5c437f0 1122 * @param hsdram: FMC_SDRAM handle
mbed_official 133:d4dda5c437f0 1123 * @retval HAL status
mbed_official 133:d4dda5c437f0 1124 */
mbed_official 133:d4dda5c437f0 1125 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 133:d4dda5c437f0 1126 {
mbed_official 133:d4dda5c437f0 1127 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1128 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 1129 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 133:d4dda5c437f0 1130
mbed_official 133:d4dda5c437f0 1131 /* Disable write protection */
mbed_official 133:d4dda5c437f0 1132 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
mbed_official 133:d4dda5c437f0 1133
mbed_official 133:d4dda5c437f0 1134 return HAL_OK;
mbed_official 133:d4dda5c437f0 1135 }
mbed_official 133:d4dda5c437f0 1136
mbed_official 133:d4dda5c437f0 1137 /**
mbed_official 133:d4dda5c437f0 1138 * @brief Send Command to the FMC SDRAM bank
mbed_official 133:d4dda5c437f0 1139 * @param Device: Pointer to SDRAM device instance
mbed_official 133:d4dda5c437f0 1140 * @param Command: Pointer to SDRAM command structure
mbed_official 133:d4dda5c437f0 1141 * @param Timing: Pointer to SDRAM Timing structure
mbed_official 133:d4dda5c437f0 1142 * @param Timeout: Timeout wait value
mbed_official 133:d4dda5c437f0 1143 * @retval HAL state
mbed_official 133:d4dda5c437f0 1144 */
mbed_official 133:d4dda5c437f0 1145 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
mbed_official 133:d4dda5c437f0 1146 {
mbed_official 133:d4dda5c437f0 1147 __IO uint32_t tmpr = 0;
mbed_official 133:d4dda5c437f0 1148 uint32_t timeout = 0;
mbed_official 133:d4dda5c437f0 1149
mbed_official 133:d4dda5c437f0 1150 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1151 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 1152 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
mbed_official 133:d4dda5c437f0 1153 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
mbed_official 133:d4dda5c437f0 1154 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
mbed_official 133:d4dda5c437f0 1155 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
mbed_official 133:d4dda5c437f0 1156
mbed_official 133:d4dda5c437f0 1157 /* Set command register */
mbed_official 133:d4dda5c437f0 1158 tmpr = (uint32_t)((Command->CommandMode) |\
mbed_official 133:d4dda5c437f0 1159 (Command->CommandTarget) |\
mbed_official 133:d4dda5c437f0 1160 (((Command->AutoRefreshNumber)-1) << 5) |\
mbed_official 133:d4dda5c437f0 1161 ((Command->ModeRegisterDefinition) << 9)
mbed_official 133:d4dda5c437f0 1162 );
mbed_official 133:d4dda5c437f0 1163
mbed_official 133:d4dda5c437f0 1164 Device->SDCMR = tmpr;
mbed_official 133:d4dda5c437f0 1165
mbed_official 133:d4dda5c437f0 1166 timeout = HAL_GetTick() + Timeout;
mbed_official 133:d4dda5c437f0 1167
mbed_official 133:d4dda5c437f0 1168 /* wait until command is send */
mbed_official 133:d4dda5c437f0 1169 while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
mbed_official 133:d4dda5c437f0 1170 {
mbed_official 133:d4dda5c437f0 1171 /* Check for the Timeout */
mbed_official 133:d4dda5c437f0 1172 if(Timeout != HAL_MAX_DELAY)
mbed_official 133:d4dda5c437f0 1173 {
mbed_official 133:d4dda5c437f0 1174 if(HAL_GetTick() >= timeout)
mbed_official 133:d4dda5c437f0 1175 {
mbed_official 133:d4dda5c437f0 1176 return HAL_TIMEOUT;
mbed_official 133:d4dda5c437f0 1177 }
mbed_official 133:d4dda5c437f0 1178 }
mbed_official 133:d4dda5c437f0 1179
mbed_official 133:d4dda5c437f0 1180 return HAL_ERROR;
mbed_official 133:d4dda5c437f0 1181 }
mbed_official 133:d4dda5c437f0 1182
mbed_official 133:d4dda5c437f0 1183 return HAL_OK;
mbed_official 133:d4dda5c437f0 1184 }
mbed_official 133:d4dda5c437f0 1185
mbed_official 133:d4dda5c437f0 1186 /**
mbed_official 133:d4dda5c437f0 1187 * @brief Program the SDRAM Memory Refresh rate.
mbed_official 133:d4dda5c437f0 1188 * @param Device: Pointer to SDRAM device instance
mbed_official 133:d4dda5c437f0 1189 * @param RefreshRate: The SDRAM refresh rate value.
mbed_official 133:d4dda5c437f0 1190 * @retval HAL state
mbed_official 133:d4dda5c437f0 1191 */
mbed_official 133:d4dda5c437f0 1192 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
mbed_official 133:d4dda5c437f0 1193 {
mbed_official 133:d4dda5c437f0 1194 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1195 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 1196 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
mbed_official 133:d4dda5c437f0 1197
mbed_official 133:d4dda5c437f0 1198 /* Set the refresh rate in command register */
mbed_official 133:d4dda5c437f0 1199 Device->SDRTR |= (RefreshRate<<1);
mbed_official 133:d4dda5c437f0 1200
mbed_official 133:d4dda5c437f0 1201 return HAL_OK;
mbed_official 133:d4dda5c437f0 1202 }
mbed_official 133:d4dda5c437f0 1203
mbed_official 133:d4dda5c437f0 1204 /**
mbed_official 133:d4dda5c437f0 1205 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
mbed_official 133:d4dda5c437f0 1206 * @param Device: Pointer to SDRAM device instance
mbed_official 133:d4dda5c437f0 1207 * @param AutoRefreshNumber: Specifies the auto Refresh number.
mbed_official 133:d4dda5c437f0 1208 * @retval None
mbed_official 133:d4dda5c437f0 1209 */
mbed_official 133:d4dda5c437f0 1210 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
mbed_official 133:d4dda5c437f0 1211 {
mbed_official 133:d4dda5c437f0 1212 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1213 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 1214 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
mbed_official 133:d4dda5c437f0 1215
mbed_official 133:d4dda5c437f0 1216 /* Set the Auto-refresh number in command register */
mbed_official 133:d4dda5c437f0 1217 Device->SDCMR |= (AutoRefreshNumber << 5);
mbed_official 133:d4dda5c437f0 1218
mbed_official 133:d4dda5c437f0 1219 return HAL_OK;
mbed_official 133:d4dda5c437f0 1220 }
mbed_official 133:d4dda5c437f0 1221
mbed_official 133:d4dda5c437f0 1222 /**
mbed_official 133:d4dda5c437f0 1223 * @brief Returns the indicated FMC SDRAM bank mode status.
mbed_official 133:d4dda5c437f0 1224 * @param Device: Pointer to SDRAM device instance
mbed_official 133:d4dda5c437f0 1225 * @param Bank: Defines the FMC SDRAM bank. This parameter can be
mbed_official 133:d4dda5c437f0 1226 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
mbed_official 133:d4dda5c437f0 1227 * @retval The FMC SDRAM bank mode status, could be on of the following values:
mbed_official 133:d4dda5c437f0 1228 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
mbed_official 133:d4dda5c437f0 1229 * FMC_SDRAM_POWER_DOWN_MODE.
mbed_official 133:d4dda5c437f0 1230 */
mbed_official 133:d4dda5c437f0 1231 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 133:d4dda5c437f0 1232 {
mbed_official 133:d4dda5c437f0 1233 uint32_t tmpreg = 0;
mbed_official 133:d4dda5c437f0 1234
mbed_official 133:d4dda5c437f0 1235 /* Check the parameters */
mbed_official 133:d4dda5c437f0 1236 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 133:d4dda5c437f0 1237 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 133:d4dda5c437f0 1238
mbed_official 133:d4dda5c437f0 1239 /* Get the corresponding bank mode */
mbed_official 133:d4dda5c437f0 1240 if(Bank == FMC_SDRAM_BANK1)
mbed_official 133:d4dda5c437f0 1241 {
mbed_official 133:d4dda5c437f0 1242 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
mbed_official 133:d4dda5c437f0 1243 }
mbed_official 133:d4dda5c437f0 1244 else
mbed_official 133:d4dda5c437f0 1245 {
mbed_official 133:d4dda5c437f0 1246 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
mbed_official 133:d4dda5c437f0 1247 }
mbed_official 133:d4dda5c437f0 1248
mbed_official 133:d4dda5c437f0 1249 /* Return the mode status */
mbed_official 133:d4dda5c437f0 1250 return tmpreg;
mbed_official 133:d4dda5c437f0 1251 }
mbed_official 133:d4dda5c437f0 1252
mbed_official 133:d4dda5c437f0 1253 /**
mbed_official 133:d4dda5c437f0 1254 * @}
mbed_official 133:d4dda5c437f0 1255 */
mbed_official 133:d4dda5c437f0 1256
mbed_official 133:d4dda5c437f0 1257 /**
mbed_official 133:d4dda5c437f0 1258 * @}
mbed_official 133:d4dda5c437f0 1259 */
mbed_official 133:d4dda5c437f0 1260
mbed_official 133:d4dda5c437f0 1261 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 133:d4dda5c437f0 1262
mbed_official 133:d4dda5c437f0 1263 #endif /* HAL_FMC_MODULE_ENABLED */
mbed_official 133:d4dda5c437f0 1264
mbed_official 133:d4dda5c437f0 1265 /**
mbed_official 133:d4dda5c437f0 1266 * @}
mbed_official 133:d4dda5c437f0 1267 */
mbed_official 133:d4dda5c437f0 1268
mbed_official 133:d4dda5c437f0 1269 /**
mbed_official 133:d4dda5c437f0 1270 * @}
mbed_official 133:d4dda5c437f0 1271 */
mbed_official 133:d4dda5c437f0 1272
mbed_official 133:d4dda5c437f0 1273 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/