Revision 13:0645d8841f51, committed 2013-08-05

Comitter:

bogdanm

Date:

Mon Aug 05 14:12:34 2013 +0300

Parent:

12:5fa2273de5db

Child:

14:096882eb0961

Commit message:

Update mbed sources to revision 64

Changed in this revision

--- a/api/AnalogIn.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/AnalogIn.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,103 +1,103 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGIN_H
-#define MBED_ANALOGIN_H
-
-#include "platform.h"
-
-#if DEVICE_ANALOGIN
-
-#include "analogin_api.h"
-
-namespace mbed {
-
-/** An analog input, used for reading the voltage on a pin
- *
- * Example:
- * @code
- * // Print messages when the AnalogIn is greater than 50%
- *
- * #include "mbed.h"
- *
- * AnalogIn temperature(p20);
- *
- * int main() {
- *     while(1) {
- *         if(temperature > 0.5) {
- *             printf("Too hot! (%f)", temperature.read());
- *         }
- *     }
- * }
- * @endcode
- */
-class AnalogIn {
-
-public:
-
-    /** Create an AnalogIn, connected to the specified pin
-     *
-     * @param pin AnalogIn pin to connect to
-     * @param name (optional) A string to identify the object
-     */
-    AnalogIn(PinName pin) {
-        analogin_init(&_adc, pin);
-    }
-
-    /** Read the input voltage, represented as a float in the range [0.0, 1.0]
-     *
-     * @returns A floating-point value representing the current input voltage, measured as a percentage
-     */
-    float read() {
-        return analogin_read(&_adc);
-    }
-
-    /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
-     *
-     * @returns
-     *   16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
-     */
-    unsigned short read_u16() {
-        return analogin_read_u16(&_adc);
-    }
-
-#ifdef MBED_OPERATORS
-    /** An operator shorthand for read()
-     *
-     * The float() operator can be used as a shorthand for read() to simplify common code sequences
-     *
-     * Example:
-     * @code
-     * float x = volume.read();
-     * float x = volume;
-     *
-     * if(volume.read() > 0.25) { ... }
-     * if(volume > 0.25) { ... }
-     * @endcode
-     */
-    operator float() {
-        return read();
-    }
-#endif
-
-protected:
-    analogin_t _adc;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_H
+#define MBED_ANALOGIN_H
+
+#include "platform.h"
+
+#if DEVICE_ANALOGIN
+
+#include "analogin_api.h"
+
+namespace mbed {
+
+/** An analog input, used for reading the voltage on a pin
+ *
+ * Example:
+ * @code
+ * // Print messages when the AnalogIn is greater than 50%
+ *
+ * #include "mbed.h"
+ *
+ * AnalogIn temperature(p20);
+ *
+ * int main() {
+ *     while(1) {
+ *         if(temperature > 0.5) {
+ *             printf("Too hot! (%f)", temperature.read());
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class AnalogIn {
+
+public:
+
+    /** Create an AnalogIn, connected to the specified pin
+     *
+     * @param pin AnalogIn pin to connect to
+     * @param name (optional) A string to identify the object
+     */
+    AnalogIn(PinName pin) {
+        analogin_init(&_adc, pin);
+    }
+
+    /** Read the input voltage, represented as a float in the range [0.0, 1.0]
+     *
+     * @returns A floating-point value representing the current input voltage, measured as a percentage
+     */
+    float read() {
+        return analogin_read(&_adc);
+    }
+
+    /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+     *
+     * @returns
+     *   16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
+     */
+    unsigned short read_u16() {
+        return analogin_read_u16(&_adc);
+    }
+
+#ifdef MBED_OPERATORS
+    /** An operator shorthand for read()
+     *
+     * The float() operator can be used as a shorthand for read() to simplify common code sequences
+     *
+     * Example:
+     * @code
+     * float x = volume.read();
+     * float x = volume;
+     *
+     * if(volume.read() > 0.25) { ... }
+     * if(volume > 0.25) { ... }
+     * @endcode
+     */
+    operator float() {
+        return read();
+    }
+#endif
+
+protected:
+    analogin_t _adc;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/AnalogOut.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/AnalogOut.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,121 +1,121 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGOUT_H
-#define MBED_ANALOGOUT_H
-
-#include "platform.h"
-
-#if DEVICE_ANALOGOUT
-
-#include "analogout_api.h"
-
-namespace mbed {
-
-/** An analog output, used for setting the voltage on a pin
- *
- * Example:
- * @code
- * // Make a sawtooth output
- *
- * #include "mbed.h"
- *
- * AnalogOut tri(p18);
- * int main() {
- *     while(1) {
- *         tri = tri + 0.01;
- *         wait_us(1);
- *         if(tri == 1) {
- *             tri = 0;
- *         }
- *     }
- * }
- * @endcode
- */
-class AnalogOut {
-
-public:
-
-    /** Create an AnalogOut connected to the specified pin
-     *
-     *  @param AnalogOut pin to connect to (18)
-     */
-    AnalogOut(PinName pin) {
-        analogout_init(&_dac, pin);
-    }
-
-    /** Set the output voltage, specified as a percentage (float)
-     *
-     *  @param value A floating-point value representing the output voltage,
-     *    specified as a percentage. The value should lie between
-     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
-     *    Values outside this range will be saturated to 0.0f or 1.0f.
-     */
-    void write(float value) {
-        analogout_write(&_dac, value);
-    }
-
-    /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
-     *
-     *  @param value 16-bit unsigned short representing the output voltage,
-     *            normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
-     */
-    void write_u16(unsigned short value) {
-        analogout_write_u16(&_dac, value);
-    }
-
-    /** Return the current output voltage setting, measured as a percentage (float)
-     *
-     *  @returns
-     *    A floating-point value representing the current voltage being output on the pin,
-     *    measured as a percentage. The returned value will lie between
-     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
-     *
-     *  @note
-     *    This value may not match exactly the value set by a previous write().
-     */
-    float read() {
-        return analogout_read(&_dac);
-    }
-
-#ifdef MBED_OPERATORS
-    /** An operator shorthand for write()
-     */
-    AnalogOut& operator= (float percent) {
-        write(percent);
-        return *this;
-    }
-
-    AnalogOut& operator= (AnalogOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** An operator shorthand for read()
-     */
-    operator float() {
-        return read();
-    }
-#endif
-
-protected:
-    dac_t _dac;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_H
+#define MBED_ANALOGOUT_H
+
+#include "platform.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "analogout_api.h"
+
+namespace mbed {
+
+/** An analog output, used for setting the voltage on a pin
+ *
+ * Example:
+ * @code
+ * // Make a sawtooth output
+ *
+ * #include "mbed.h"
+ *
+ * AnalogOut tri(p18);
+ * int main() {
+ *     while(1) {
+ *         tri = tri + 0.01;
+ *         wait_us(1);
+ *         if(tri == 1) {
+ *             tri = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class AnalogOut {
+
+public:
+
+    /** Create an AnalogOut connected to the specified pin
+     *
+     *  @param AnalogOut pin to connect to (18)
+     */
+    AnalogOut(PinName pin) {
+        analogout_init(&_dac, pin);
+    }
+
+    /** Set the output voltage, specified as a percentage (float)
+     *
+     *  @param value A floating-point value representing the output voltage,
+     *    specified as a percentage. The value should lie between
+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+     *    Values outside this range will be saturated to 0.0f or 1.0f.
+     */
+    void write(float value) {
+        analogout_write(&_dac, value);
+    }
+
+    /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+     *
+     *  @param value 16-bit unsigned short representing the output voltage,
+     *            normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
+     */
+    void write_u16(unsigned short value) {
+        analogout_write_u16(&_dac, value);
+    }
+
+    /** Return the current output voltage setting, measured as a percentage (float)
+     *
+     *  @returns
+     *    A floating-point value representing the current voltage being output on the pin,
+     *    measured as a percentage. The returned value will lie between
+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+     *
+     *  @note
+     *    This value may not match exactly the value set by a previous write().
+     */
+    float read() {
+        return analogout_read(&_dac);
+    }
+
+#ifdef MBED_OPERATORS
+    /** An operator shorthand for write()
+     */
+    AnalogOut& operator= (float percent) {
+        write(percent);
+        return *this;
+    }
+
+    AnalogOut& operator= (AnalogOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** An operator shorthand for read()
+     */
+    operator float() {
+        return read();
+    }
+#endif
+
+protected:
+    dac_t _dac;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/BusIn.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/BusIn.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,67 +1,67 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSIN_H
-#define MBED_BUSIN_H
-
-#include "platform.h"
-#include "DigitalIn.h"
-
-namespace mbed {
-
-/** A digital input bus, used for reading the state of a collection of pins
- */
-class BusIn {
-
-public:
-    /* Group: Configuration Methods */
-
-    /** Create an BusIn, connected to the specified pins
-     *
-     * @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)
-     *
-     * @note
-     *  It is only required to specify as many pin variables as is required
-     *  for the bus; the rest will default to NC (not connected)
-     */
-    BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
-          PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
-          PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
-          PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
-    BusIn(PinName pins[16]);
-
-    virtual ~BusIn();
-
-    /** Read the value of the input bus
-     *
-     *  @returns
-     *   An integer with each bit corresponding to the value read from the associated DigitalIn pin
-     */
-    int read();
-
-#ifdef MBED_OPERATORS
-    /** A shorthand for read()
-     */
-    operator int();
-#endif
-
-protected:
-    DigitalIn* _pin[16];
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSIN_H
+#define MBED_BUSIN_H
+
+#include "platform.h"
+#include "DigitalIn.h"
+
+namespace mbed {
+
+/** A digital input bus, used for reading the state of a collection of pins
+ */
+class BusIn {
+
+public:
+    /* Group: Configuration Methods */
+
+    /** Create an BusIn, connected to the specified pins
+     *
+     * @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)
+     *
+     * @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+          PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+          PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+          PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    BusIn(PinName pins[16]);
+
+    virtual ~BusIn();
+
+    /** Read the value of the input bus
+     *
+     *  @returns
+     *   An integer with each bit corresponding to the value read from the associated DigitalIn pin
+     */
+    int read();
+
+#ifdef MBED_OPERATORS
+    /** A shorthand for read()
+     */
+    operator int();
+#endif
+
+protected:
+    DigitalIn* _pin[16];
+};
+
+} // namespace mbed
+
+#endif

--- a/api/BusInOut.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/BusInOut.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,93 +1,93 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSINOUT_H
-#define MBED_BUSINOUT_H
-
-#include "DigitalInOut.h"
-
-namespace mbed {
-
-/** A digital input output bus, used for setting the state of a collection of pins
- */
-class BusInOut {
-
-public:
-
-    /** Create an BusInOut, connected to the specified pins
-     *
-     *  @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)
-     *
-     *  @note
-     *  It is only required to specify as many pin variables as is required
-     *  for the bus; the rest will default to NC (not connected)
-     */
-    BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
-             PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
-             PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
-             PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
-    BusInOut(PinName pins[16]);
-
-    virtual ~BusInOut();
-
-    /* Group: Access Methods */
-
-    /** Write the value to the output bus
-     *
-     *  @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
-     */
-    void write(int value);
-
-
-    /** Read the value currently output on the bus
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated DigitalInOut pin setting
-     */
-    int read();
-
-    /** Set as an output
-     */
-    void output();
-
-    /** Set as an input
-     */
-    void input();
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone
-     */
-    void mode(PinMode pull);
-
-#ifdef MBED_OPERATORS
-     /** A shorthand for write()
-     */
-    BusInOut& operator= (int v);
-    BusInOut& operator= (BusInOut& rhs);
-
-    /** A shorthand for read()
-     */
-    operator int();
-#endif
-
-protected:
-    DigitalInOut* _pin[16];
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSINOUT_H
+#define MBED_BUSINOUT_H
+
+#include "DigitalInOut.h"
+
+namespace mbed {
+
+/** A digital input output bus, used for setting the state of a collection of pins
+ */
+class BusInOut {
+
+public:
+
+    /** Create an BusInOut, connected to the specified pins
+     *
+     *  @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)
+     *
+     *  @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+             PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+             PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+             PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    BusInOut(PinName pins[16]);
+
+    virtual ~BusInOut();
+
+    /* Group: Access Methods */
+
+    /** Write the value to the output bus
+     *
+     *  @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
+     */
+    void write(int value);
+
+
+    /** Read the value currently output on the bus
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated DigitalInOut pin setting
+     */
+    int read();
+
+    /** Set as an output
+     */
+    void output();
+
+    /** Set as an input
+     */
+    void input();
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+#ifdef MBED_OPERATORS
+     /** A shorthand for write()
+     */
+    BusInOut& operator= (int v);
+    BusInOut& operator= (BusInOut& rhs);
+
+    /** A shorthand for read()
+     */
+    operator int();
+#endif
+
+protected:
+    DigitalInOut* _pin[16];
+};
+
+} // namespace mbed
+
+#endif

--- a/api/BusOut.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/BusOut.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,76 +1,76 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSOUT_H
-#define MBED_BUSOUT_H
-
-#include "DigitalOut.h"
-
-namespace mbed {
-
-/** A digital output bus, used for setting the state of a collection of pins
- */
-class BusOut {
-
-public:
-
-    /** Create an BusOut, connected to the specified pins
-     *
-     *  @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)
-     *
-     *  @note
-     *  It is only required to specify as many pin variables as is required
-     *  for the bus; the rest will default to NC (not connected)
-     */
-    BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
-           PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
-           PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
-           PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
-    BusOut(PinName pins[16]);
-
-    virtual ~BusOut();
-
-    /** Write the value to the output bus
-     *
-     *  @param value An integer specifying a bit to write for every corresponding DigitalOut pin
-     */
-    void write(int value);
-
-    /** Read the value currently output on the bus
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated DigitalOut pin setting
-     */
-    int read();
-
-#ifdef MBED_OPERATORS
-    /** A shorthand for write()
-     */
-    BusOut& operator= (int v);
-    BusOut& operator= (BusOut& rhs);
-
-    /** A shorthand for read()
-     */
-    operator int();
-#endif
-
-protected:
-    DigitalOut* _pin[16];
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSOUT_H
+#define MBED_BUSOUT_H
+
+#include "DigitalOut.h"
+
+namespace mbed {
+
+/** A digital output bus, used for setting the state of a collection of pins
+ */
+class BusOut {
+
+public:
+
+    /** Create an BusOut, connected to the specified pins
+     *
+     *  @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)
+     *
+     *  @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+           PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+           PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+           PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    BusOut(PinName pins[16]);
+
+    virtual ~BusOut();
+
+    /** Write the value to the output bus
+     *
+     *  @param value An integer specifying a bit to write for every corresponding DigitalOut pin
+     */
+    void write(int value);
+
+    /** Read the value currently output on the bus
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated DigitalOut pin setting
+     */
+    int read();
+
+#ifdef MBED_OPERATORS
+    /** A shorthand for write()
+     */
+    BusOut& operator= (int v);
+    BusOut& operator= (BusOut& rhs);
+
+    /** A shorthand for read()
+     */
+    operator int();
+#endif
+
+protected:
+    DigitalOut* _pin[16];
+};
+
+} // namespace mbed
+
+#endif

--- a/api/CAN.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/CAN.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,196 +1,196 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_H
-#define MBED_CAN_H
-
-#include "platform.h"
-
-#if DEVICE_CAN
-
-#include "can_api.h"
-#include "can_helper.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-/** CANMessage class
- */
-class CANMessage : public CAN_Message {
-
-public:
-    /** Creates empty CAN message.
-     */
-    CANMessage() {
-        len    = 8;
-        type   = CANData;
-        format = CANStandard;
-        id     = 0;
-        memset(data, 0, 8);
-    }
-
-    /** Creates CAN message with specific content.
-     */
-    CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
-      len    = _len & 0xF;
-      type   = _type;
-      format = _format;
-      id     = _id;
-      memcpy(data, _data, _len);
-    }
-
-    /** Creates CAN remote message.
-     */
-    CANMessage(int _id, CANFormat _format = CANStandard) {
-      len    = 0;
-      type   = CANRemote;
-      format = _format;
-      id     = _id;
-      memset(data, 0, 8);
-    }
-};
-
-/** A can bus client, used for communicating with can devices
- */
-class CAN {
-
-public:
-    /** Creates an CAN interface connected to specific pins.
-     *
-     *  @param rd read from transmitter
-     *  @param td transmit to transmitter
-     *
-     * Example:
-     * @code
-     * #include "mbed.h"
-     *
-     * Ticker ticker;
-     * DigitalOut led1(LED1);
-     * DigitalOut led2(LED2);
-     * CAN can1(p9, p10);
-     * CAN can2(p30, p29);
-     *
-     * char counter = 0;
-     *
-     * void send() {
-     *     if(can1.write(CANMessage(1337, &counter, 1))) {
-     *         printf("Message sent: %d\n", counter);
-     *         counter++;
-     *     }
-     *     led1 = !led1;
-     * }
-     *
-     * int main() {
-     *     ticker.attach(&send, 1);
-     *    CANMessage msg;
-     *     while(1) {
-     *         if(can2.read(msg)) {
-     *             printf("Message received: %d\n\n", msg.data[0]);
-     *             led2 = !led2;
-     *         }
-     *         wait(0.2);
-     *     }
-     * }
-     * @endcode
-     */
-    CAN(PinName rd, PinName td);
-    virtual ~CAN();
-
-    /** Set the frequency of the CAN interface
-     *
-     *  @param hz The bus frequency in hertz
-     *
-     *  @returns
-     *    1 if successful,
-     *    0 otherwise
-     */
-    int frequency(int hz);
-
-    /** Write a CANMessage to the bus.
-     *
-     *  @param msg The CANMessage to write.
-     *
-     *  @returns
-     *    0 if write failed,
-     *    1 if write was successful
-     */
-    int write(CANMessage msg);
-
-    /** Read a CANMessage from the bus.
-     *
-     *  @param msg A CANMessage to read to.
-     *
-     *  @returns
-     *    0 if no message arrived,
-     *    1 if message arrived
-     */
-    int read(CANMessage &msg);
-
-    /** Reset CAN interface.
-     *
-     * To use after error overflow.
-     */
-    void reset();
-
-    /** Puts or removes the CAN interface into silent monitoring mode
-     *
-     *  @param silent boolean indicating whether to go into silent mode or not
-     */
-    void monitor(bool silent);
-
-    /** Returns number of read errors to detect read overflow errors.
-     */
-    unsigned char rderror();
-
-    /** Returns number of write errors to detect write overflow errors.
-     */
-    unsigned char tderror();
-
-    /** Attach a function to call whenever a CAN frame received interrupt is
-     *  generated.
-     *
-     *  @param fptr A pointer to a void function, or 0 to set as none
-     */
-    void attach(void (*fptr)(void));
-
-   /** Attach a member function to call whenever a CAN frame received interrupt
-    *  is generated.
-    *
-    *  @param tptr pointer to the object to call the member function on
-    *  @param mptr pointer to the member function to be called
-    */
-   template<typename T>
-   void attach(T* tptr, void (T::*mptr)(void)) {
-        if((mptr != NULL) && (tptr != NULL)) {
-            _rxirq.attach(tptr, mptr);
-            setup_interrupt();
-        } else {
-            remove_interrupt();
-        }
-    }
-
-private:
-    can_t _can;
-    FunctionPointer _rxirq;
-
-    void setup_interrupt(void);
-    void remove_interrupt(void);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif    // MBED_CAN_H
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_H
+#define MBED_CAN_H
+
+#include "platform.h"
+
+#if DEVICE_CAN
+
+#include "can_api.h"
+#include "can_helper.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** CANMessage class
+ */
+class CANMessage : public CAN_Message {
+
+public:
+    /** Creates empty CAN message.
+     */
+    CANMessage() {
+        len    = 8;
+        type   = CANData;
+        format = CANStandard;
+        id     = 0;
+        memset(data, 0, 8);
+    }
+
+    /** Creates CAN message with specific content.
+     */
+    CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
+      len    = _len & 0xF;
+      type   = _type;
+      format = _format;
+      id     = _id;
+      memcpy(data, _data, _len);
+    }
+
+    /** Creates CAN remote message.
+     */
+    CANMessage(int _id, CANFormat _format = CANStandard) {
+      len    = 0;
+      type   = CANRemote;
+      format = _format;
+      id     = _id;
+      memset(data, 0, 8);
+    }
+};
+
+/** A can bus client, used for communicating with can devices
+ */
+class CAN {
+
+public:
+    /** Creates an CAN interface connected to specific pins.
+     *
+     *  @param rd read from transmitter
+     *  @param td transmit to transmitter
+     *
+     * Example:
+     * @code
+     * #include "mbed.h"
+     *
+     * Ticker ticker;
+     * DigitalOut led1(LED1);
+     * DigitalOut led2(LED2);
+     * CAN can1(p9, p10);
+     * CAN can2(p30, p29);
+     *
+     * char counter = 0;
+     *
+     * void send() {
+     *     if(can1.write(CANMessage(1337, &counter, 1))) {
+     *         printf("Message sent: %d\n", counter);
+     *         counter++;
+     *     }
+     *     led1 = !led1;
+     * }
+     *
+     * int main() {
+     *     ticker.attach(&send, 1);
+     *    CANMessage msg;
+     *     while(1) {
+     *         if(can2.read(msg)) {
+     *             printf("Message received: %d\n\n", msg.data[0]);
+     *             led2 = !led2;
+     *         }
+     *         wait(0.2);
+     *     }
+     * }
+     * @endcode
+     */
+    CAN(PinName rd, PinName td);
+    virtual ~CAN();
+
+    /** Set the frequency of the CAN interface
+     *
+     *  @param hz The bus frequency in hertz
+     *
+     *  @returns
+     *    1 if successful,
+     *    0 otherwise
+     */
+    int frequency(int hz);
+
+    /** Write a CANMessage to the bus.
+     *
+     *  @param msg The CANMessage to write.
+     *
+     *  @returns
+     *    0 if write failed,
+     *    1 if write was successful
+     */
+    int write(CANMessage msg);
+
+    /** Read a CANMessage from the bus.
+     *
+     *  @param msg A CANMessage to read to.
+     *
+     *  @returns
+     *    0 if no message arrived,
+     *    1 if message arrived
+     */
+    int read(CANMessage &msg);
+
+    /** Reset CAN interface.
+     *
+     * To use after error overflow.
+     */
+    void reset();
+
+    /** Puts or removes the CAN interface into silent monitoring mode
+     *
+     *  @param silent boolean indicating whether to go into silent mode or not
+     */
+    void monitor(bool silent);
+
+    /** Returns number of read errors to detect read overflow errors.
+     */
+    unsigned char rderror();
+
+    /** Returns number of write errors to detect write overflow errors.
+     */
+    unsigned char tderror();
+
+    /** Attach a function to call whenever a CAN frame received interrupt is
+     *  generated.
+     *
+     *  @param fptr A pointer to a void function, or 0 to set as none
+     */
+    void attach(void (*fptr)(void));
+
+   /** Attach a member function to call whenever a CAN frame received interrupt
+    *  is generated.
+    *
+    *  @param tptr pointer to the object to call the member function on
+    *  @param mptr pointer to the member function to be called
+    */
+   template<typename T>
+   void attach(T* tptr, void (T::*mptr)(void)) {
+        if((mptr != NULL) && (tptr != NULL)) {
+            _rxirq.attach(tptr, mptr);
+            setup_interrupt();
+        } else {
+            remove_interrupt();
+        }
+    }
+
+private:
+    can_t _can;
+    FunctionPointer _rxirq;
+
+    void setup_interrupt(void);
+    void remove_interrupt(void);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif    // MBED_CAN_H

--- a/api/DigitalIn.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/DigitalIn.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,90 +1,90 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALIN_H
-#define MBED_DIGITALIN_H
-
-#include "platform.h"
-
-#include "gpio_api.h"
-
-namespace mbed {
-
-/** A digital input, used for reading the state of a pin
- *
- * Example:
- * @code
- * // Flash an LED while a DigitalIn is true
- *
- * #include "mbed.h"
- *
- * DigitalIn enable(p5);
- * DigitalOut led(LED1);
- *
- * int main() {
- *     while(1) {
- *         if(enable) {
- *             led = !led;
- *         }
- *         wait(0.25);
- *     }
- * }
- * @endcode
- */
-class DigitalIn {
-
-public:
-    /** Create a DigitalIn connected to the specified pin
-     *
-     *  @param pin DigitalIn pin to connect to
-     *  @param name (optional) A string to identify the object
-     */
-    DigitalIn(PinName pin) {
-        gpio_init(&gpio, pin, PIN_INPUT);
-    }
-
-    /** Read the input, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    An integer representing the state of the input pin,
-     *    0 for logical 0, 1 for logical 1
-     */
-    int read() {
-        return gpio_read(&gpio);
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone, OpenDrain
-     */
-    void mode(PinMode pull) {
-        gpio_mode(&gpio, pull);
-    }
-
-#ifdef MBED_OPERATORS
-    /** An operator shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-#endif
-
-protected:
-    gpio_t gpio;
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALIN_H
+#define MBED_DIGITALIN_H
+
+#include "platform.h"
+
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital input, used for reading the state of a pin
+ *
+ * Example:
+ * @code
+ * // Flash an LED while a DigitalIn is true
+ *
+ * #include "mbed.h"
+ *
+ * DigitalIn enable(p5);
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         if(enable) {
+ *             led = !led;
+ *         }
+ *         wait(0.25);
+ *     }
+ * }
+ * @endcode
+ */
+class DigitalIn {
+
+public:
+    /** Create a DigitalIn connected to the specified pin
+     *
+     *  @param pin DigitalIn pin to connect to
+     *  @param name (optional) A string to identify the object
+     */
+    DigitalIn(PinName pin) {
+        gpio_init(&gpio, pin, PIN_INPUT);
+    }
+
+    /** Read the input, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    An integer representing the state of the input pin,
+     *    0 for logical 0, 1 for logical 1
+     */
+    int read() {
+        return gpio_read(&gpio);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode pull) {
+        gpio_mode(&gpio, pull);
+    }
+
+#ifdef MBED_OPERATORS
+    /** An operator shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+#endif
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif

--- a/api/DigitalInOut.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/DigitalInOut.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,103 +1,103 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALINOUT_H
-#define MBED_DIGITALINOUT_H
-
-#include "platform.h"
-
-#include "gpio_api.h"
-
-namespace mbed {
-
-/** A digital input/output, used for setting or reading a bi-directional pin
- */
-class DigitalInOut {
-
-public:
-    /** Create a DigitalInOut connected to the specified pin
-     *
-     *  @param pin DigitalInOut pin to connect to
-     */
-    DigitalInOut(PinName pin) {
-        gpio_init(&gpio, pin, PIN_INPUT);
-    }
-
-    /** Set the output, specified as 0 or 1 (int)
-     *
-     *  @param value An integer specifying the pin output value,
-     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
-     */
-    void write(int value) {
-        gpio_write(&gpio, value);
-    }
-
-    /** Return the output setting, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    an integer representing the output setting of the pin if it is an output,
-     *    or read the input if set as an input
-     */
-    int read() {
-        return gpio_read(&gpio);
-    }
-
-    /** Set as an output
-     */
-    void output() {
-        gpio_dir(&gpio, PIN_OUTPUT);
-    }
-
-    /** Set as an input
-     */
-    void input() {
-        gpio_dir(&gpio, PIN_INPUT);
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone, OpenDrain
-     */
-    void mode(PinMode pull) {
-        gpio_mode(&gpio, pull);
-    }
-
-#ifdef MBED_OPERATORS
-    /** A shorthand for write()
-     */
-    DigitalInOut& operator= (int value) {
-        write(value);
-        return *this;
-    }
-
-    DigitalInOut& operator= (DigitalInOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-#endif
-
-protected:
-    gpio_t gpio;
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALINOUT_H
+#define MBED_DIGITALINOUT_H
+
+#include "platform.h"
+
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital input/output, used for setting or reading a bi-directional pin
+ */
+class DigitalInOut {
+
+public:
+    /** Create a DigitalInOut connected to the specified pin
+     *
+     *  @param pin DigitalInOut pin to connect to
+     */
+    DigitalInOut(PinName pin) {
+        gpio_init(&gpio, pin, PIN_INPUT);
+    }
+
+    /** Set the output, specified as 0 or 1 (int)
+     *
+     *  @param value An integer specifying the pin output value,
+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
+     */
+    void write(int value) {
+        gpio_write(&gpio, value);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    an integer representing the output setting of the pin if it is an output,
+     *    or read the input if set as an input
+     */
+    int read() {
+        return gpio_read(&gpio);
+    }
+
+    /** Set as an output
+     */
+    void output() {
+        gpio_dir(&gpio, PIN_OUTPUT);
+    }
+
+    /** Set as an input
+     */
+    void input() {
+        gpio_dir(&gpio, PIN_INPUT);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode pull) {
+        gpio_mode(&gpio, pull);
+    }
+
+#ifdef MBED_OPERATORS
+    /** A shorthand for write()
+     */
+    DigitalInOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    DigitalInOut& operator= (DigitalInOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+#endif
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif

--- a/api/DigitalOut.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/DigitalOut.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,97 +1,97 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALOUT_H
-#define MBED_DIGITALOUT_H
-
-#include "platform.h"
-#include "gpio_api.h"
-
-namespace mbed {
-
-/** A digital output, used for setting the state of a pin
- *
- * Example:
- * @code
- * // Toggle a LED
- * #include "mbed.h"
- *
- * DigitalOut led(LED1);
- *
- * int main() {
- *     while(1) {
- *         led = !led;
- *         wait(0.2);
- *     }
- * }
- * @endcode
- */
-class DigitalOut {
-
-public:
-    /** Create a DigitalOut connected to the specified pin
-     *
-     *  @param pin DigitalOut pin to connect to
-     */
-    DigitalOut(PinName pin) {
-        gpio_init(&gpio, pin, PIN_OUTPUT);
-    }
-
-    /** Set the output, specified as 0 or 1 (int)
-     *
-     *  @param value An integer specifying the pin output value,
-     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
-     */
-    void write(int value) {
-        gpio_write(&gpio, value);
-    }
-
-    /** Return the output setting, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    an integer representing the output setting of the pin,
-     *    0 for logical 0, 1 for logical 1
-     */
-    int read() {
-        return gpio_read(&gpio);
-    }
-
-#ifdef MBED_OPERATORS
-    /** A shorthand for write()
-     */
-    DigitalOut& operator= (int value) {
-        write(value);
-        return *this;
-    }
-
-    DigitalOut& operator= (DigitalOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-#endif
-
-protected:
-    gpio_t gpio;
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALOUT_H
+#define MBED_DIGITALOUT_H
+
+#include "platform.h"
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital output, used for setting the state of a pin
+ *
+ * Example:
+ * @code
+ * // Toggle a LED
+ * #include "mbed.h"
+ *
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         led = !led;
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ */
+class DigitalOut {
+
+public:
+    /** Create a DigitalOut connected to the specified pin
+     *
+     *  @param pin DigitalOut pin to connect to
+     */
+    DigitalOut(PinName pin) {
+        gpio_init(&gpio, pin, PIN_OUTPUT);
+    }
+
+    /** Set the output, specified as 0 or 1 (int)
+     *
+     *  @param value An integer specifying the pin output value,
+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
+     */
+    void write(int value) {
+        gpio_write(&gpio, value);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    an integer representing the output setting of the pin,
+     *    0 for logical 0, 1 for logical 1
+     */
+    int read() {
+        return gpio_read(&gpio);
+    }
+
+#ifdef MBED_OPERATORS
+    /** A shorthand for write()
+     */
+    DigitalOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    DigitalOut& operator= (DigitalOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+#endif
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif

--- a/api/DirHandle.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/DirHandle.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,104 +1,104 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIRHANDLE_H
-#define MBED_DIRHANDLE_H
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-#   define NAME_MAX 255
-typedef int mode_t;
-
-#else
-#   include <sys/syslimits.h>
-#endif
-
-#include "FileHandle.h"
-
-struct dirent {
-    char d_name[NAME_MAX+1];
-};
-
-namespace mbed {
-
-/** Represents a directory stream. Objects of this type are returned
- *  by a FileSystemLike's opendir method. Implementations must define
- *  at least closedir, readdir and rewinddir.
- *
- *  If a FileSystemLike class defines the opendir method, then the
- *  directories of an object of that type can be accessed by
- *  DIR *d = opendir("/example/directory") (or opendir("/example")
- *  to open the root of the filesystem), and then using readdir(d) etc.
- *
- *  The root directory is considered to contain all FileLike and
- *  FileSystemLike objects, so the DIR* returned by opendir("/") will
- *  reflect this.
- */
-class DirHandle {
-
-public:
-    /** Closes the directory.
-     *
-     *  @returns
-     *    0 on success,
-     *   -1 on error.
-     */
-    virtual int closedir()=0;
-
-    /** Return the directory entry at the current position, and
-     *  advances the position to the next entry.
-     *
-     * @returns
-     *  A pointer to a dirent structure representing the
-     *  directory entry at the current position, or NULL on reaching
-     *  end of directory or error.
-     */
-    virtual struct dirent *readdir()=0;
-
-    /** Resets the position to the beginning of the directory.
-     */
-    virtual void rewinddir()=0;
-
-    /** Returns the current position of the DirHandle.
-     *
-     * @returns
-     *   the current position,
-     *  -1 on error.
-     */
-    virtual off_t telldir() { return -1; }
-
-    /** Sets the position of the DirHandle.
-     *
-     *  @param location The location to seek to. Must be a value returned by telldir.
-     */
-    virtual void seekdir(off_t location) { }
-
-    virtual ~DirHandle() {}
-};
-
-} // namespace mbed
-
-typedef mbed::DirHandle DIR;
-
-extern "C" {
-    DIR *opendir(const char*);
-    struct dirent *readdir(DIR *);
-    int closedir(DIR*);
-    void rewinddir(DIR*);
-    long telldir(DIR*);
-    void seekdir(DIR*, long);
-    int mkdir(const char *name, mode_t n);
-};
-
-#endif /* MBED_DIRHANDLE_H */
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIRHANDLE_H
+#define MBED_DIRHANDLE_H
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+#   define NAME_MAX 255
+typedef int mode_t;
+
+#else
+#   include <sys/syslimits.h>
+#endif
+
+#include "FileHandle.h"
+
+struct dirent {
+    char d_name[NAME_MAX+1];
+};
+
+namespace mbed {
+
+/** Represents a directory stream. Objects of this type are returned
+ *  by a FileSystemLike's opendir method. Implementations must define
+ *  at least closedir, readdir and rewinddir.
+ *
+ *  If a FileSystemLike class defines the opendir method, then the
+ *  directories of an object of that type can be accessed by
+ *  DIR *d = opendir("/example/directory") (or opendir("/example")
+ *  to open the root of the filesystem), and then using readdir(d) etc.
+ *
+ *  The root directory is considered to contain all FileLike and
+ *  FileSystemLike objects, so the DIR* returned by opendir("/") will
+ *  reflect this.
+ */
+class DirHandle {
+
+public:
+    /** Closes the directory.
+     *
+     *  @returns
+     *    0 on success,
+     *   -1 on error.
+     */
+    virtual int closedir()=0;
+
+    /** Return the directory entry at the current position, and
+     *  advances the position to the next entry.
+     *
+     * @returns
+     *  A pointer to a dirent structure representing the
+     *  directory entry at the current position, or NULL on reaching
+     *  end of directory or error.
+     */
+    virtual struct dirent *readdir()=0;
+
+    /** Resets the position to the beginning of the directory.
+     */
+    virtual void rewinddir()=0;
+
+    /** Returns the current position of the DirHandle.
+     *
+     * @returns
+     *   the current position,
+     *  -1 on error.
+     */
+    virtual off_t telldir() { return -1; }
+
+    /** Sets the position of the DirHandle.
+     *
+     *  @param location The location to seek to. Must be a value returned by telldir.
+     */
+    virtual void seekdir(off_t location) { }
+
+    virtual ~DirHandle() {}
+};
+
+} // namespace mbed
+
+typedef mbed::DirHandle DIR;
+
+extern "C" {
+    DIR *opendir(const char*);
+    struct dirent *readdir(DIR *);
+    int closedir(DIR*);
+    void rewinddir(DIR*);
+    long telldir(DIR*);
+    void seekdir(DIR*, long);
+    int mkdir(const char *name, mode_t n);
+};
+
+#endif /* MBED_DIRHANDLE_H */

--- a/api/Ethernet.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/Ethernet.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,170 +1,170 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ETHERNET_H
-#define MBED_ETHERNET_H
-
-#include "platform.h"
-
-#if DEVICE_ETHERNET
-
-namespace mbed {
-
-/** An ethernet interface, to use with the ethernet pins.
- *
- * Example:
- * @code
- * // Read destination and source from every ethernet packet
- *
- * #include "mbed.h"
- *
- * Ethernet eth;
- *
- * int main() {
- *     char buf[0x600];
- *
- *     while(1) {
- *         int size = eth.receive();
- *         if(size > 0) {
- *             eth.read(buf, size);
- *             printf("Destination:  %02X:%02X:%02X:%02X:%02X:%02X\n",
- *                     buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
- *             printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
- *                     buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
- *         }
- *
- *         wait(1);
- *     }
- * }
- * @endcode
- */
-class Ethernet {
-
-public:
-
-    /** Initialise the ethernet interface.
-     */
-    Ethernet();
-
-    /** Powers the hardware down.
-     */
-    virtual ~Ethernet();
-
-    enum Mode {
-        AutoNegotiate,
-        HalfDuplex10,
-        FullDuplex10,
-        HalfDuplex100,
-        FullDuplex100
-    };
-
-    /** Writes into an outgoing ethernet packet.
-     *
-     *  It will append size bytes of data to the previously written bytes.
-     *
-     *  @param data An array to write.
-     *  @param size The size of data.
-     *
-     *  @returns
-     *   The number of written bytes.
-     */
-    int write(const char *data, int size);
-
-    /** Send an outgoing ethernet packet.
-     *
-     *  After filling in the data in an ethernet packet it must be send.
-     *  Send will provide a new packet to write to.
-     *
-     *  @returns
-     *    0 if the sending was failed,
-     *    1 if the package is successfully sent.
-     */
-    int send();
-
-    /** Recevies an arrived ethernet packet.
-     *
-     *  Receiving an ethernet packet will drop the last received ethernet packet
-     *  and make a new ethernet packet ready to read.
-     *  If no ethernet packet is arrived it will return 0.
-     *
-     *  @returns
-     *    0 if no ethernet packet is arrived,
-     *    or the size of the arrived packet.
-     */
-    int receive();
-
-    /** Read from an recevied ethernet packet.
-     *
-     *  After receive returnd a number bigger than 0it is
-     *  possible to read bytes from this packet.
-     *  Read will write up to size bytes into data.
-     *
-     *  It is possible to use read multible times.
-     *  Each time read will start reading after the last read byte before.
-     *
-     *  @returns
-     *  The number of byte read.
-     */
-    int read(char *data, int size);
-
-    /** Gives the ethernet address of the mbed.
-     *
-     *  @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
-     */
-    void address(char *mac);
-
-    /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
-     *
-     *  @returns
-     *   0 if no ethernet link is pressent,
-     *   1 if an ethernet link is pressent.
-     *
-     * Example:
-     * @code
-     * // Using the Ethernet link function
-     * #include "mbed.h"
-     *
-     * Ethernet eth;
-     *
-     * int main() {
-     *     wait(1); // Needed after startup.
-     *     if (eth.link()) {
-     *          printf("online\n");
-     *     } else {
-     *          printf("offline\n");
-     *     }
-     * }
-     * @endcode
-     */
-    int link();
-
-    /** Sets the speed and duplex parameters of an ethernet link
-     *
-     * - AutoNegotiate      Auto negotiate speed and duplex
-     * - HalfDuplex10       10 Mbit, half duplex
-     * - FullDuplex10       10 Mbit, full duplex
-     * - HalfDuplex100      100 Mbit, half duplex
-     * - FullDuplex100      100 Mbit, full duplex
-     *
-     *  @param mode the speed and duplex mode to set the link to:
-     */
-    void set_link(Mode mode);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_H
+#define MBED_ETHERNET_H
+
+#include "platform.h"
+
+#if DEVICE_ETHERNET
+
+namespace mbed {
+
+/** An ethernet interface, to use with the ethernet pins.
+ *
+ * Example:
+ * @code
+ * // Read destination and source from every ethernet packet
+ *
+ * #include "mbed.h"
+ *
+ * Ethernet eth;
+ *
+ * int main() {
+ *     char buf[0x600];
+ *
+ *     while(1) {
+ *         int size = eth.receive();
+ *         if(size > 0) {
+ *             eth.read(buf, size);
+ *             printf("Destination:  %02X:%02X:%02X:%02X:%02X:%02X\n",
+ *                     buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ *             printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ *                     buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
+ *         }
+ *
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ */
+class Ethernet {
+
+public:
+
+    /** Initialise the ethernet interface.
+     */
+    Ethernet();
+
+    /** Powers the hardware down.
+     */
+    virtual ~Ethernet();
+
+    enum Mode {
+        AutoNegotiate,
+        HalfDuplex10,
+        FullDuplex10,
+        HalfDuplex100,
+        FullDuplex100
+    };
+
+    /** Writes into an outgoing ethernet packet.
+     *
+     *  It will append size bytes of data to the previously written bytes.
+     *
+     *  @param data An array to write.
+     *  @param size The size of data.
+     *
+     *  @returns
+     *   The number of written bytes.
+     */
+    int write(const char *data, int size);
+
+    /** Send an outgoing ethernet packet.
+     *
+     *  After filling in the data in an ethernet packet it must be send.
+     *  Send will provide a new packet to write to.
+     *
+     *  @returns
+     *    0 if the sending was failed,
+     *    1 if the package is successfully sent.
+     */
+    int send();
+
+    /** Recevies an arrived ethernet packet.
+     *
+     *  Receiving an ethernet packet will drop the last received ethernet packet
+     *  and make a new ethernet packet ready to read.
+     *  If no ethernet packet is arrived it will return 0.
+     *
+     *  @returns
+     *    0 if no ethernet packet is arrived,
+     *    or the size of the arrived packet.
+     */
+    int receive();
+
+    /** Read from an recevied ethernet packet.
+     *
+     *  After receive returnd a number bigger than 0it is
+     *  possible to read bytes from this packet.
+     *  Read will write up to size bytes into data.
+     *
+     *  It is possible to use read multible times.
+     *  Each time read will start reading after the last read byte before.
+     *
+     *  @returns
+     *  The number of byte read.
+     */
+    int read(char *data, int size);
+
+    /** Gives the ethernet address of the mbed.
+     *
+     *  @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
+     */
+    void address(char *mac);
+
+    /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
+     *
+     *  @returns
+     *   0 if no ethernet link is pressent,
+     *   1 if an ethernet link is pressent.
+     *
+     * Example:
+     * @code
+     * // Using the Ethernet link function
+     * #include "mbed.h"
+     *
+     * Ethernet eth;
+     *
+     * int main() {
+     *     wait(1); // Needed after startup.
+     *     if (eth.link()) {
+     *          printf("online\n");
+     *     } else {
+     *          printf("offline\n");
+     *     }
+     * }
+     * @endcode
+     */
+    int link();
+
+    /** Sets the speed and duplex parameters of an ethernet link
+     *
+     * - AutoNegotiate      Auto negotiate speed and duplex
+     * - HalfDuplex10       10 Mbit, half duplex
+     * - FullDuplex10       10 Mbit, full duplex
+     * - HalfDuplex100      100 Mbit, half duplex
+     * - FullDuplex100      100 Mbit, full duplex
+     *
+     *  @param mode the speed and duplex mode to set the link to:
+     */
+    void set_link(Mode mode);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/FileBase.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/FileBase.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,75 +1,75 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEBASE_H
-#define MBED_FILEBASE_H
-
-typedef int FILEHANDLE;
-
-#include <stdio.h>
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-#    define O_RDONLY 0
-#    define O_WRONLY 1
-#    define O_RDWR   2
-#    define O_CREAT  0x0200
-#    define O_TRUNC  0x0400
-#    define O_APPEND 0x0008
-
-#    define NAME_MAX 255
-
-typedef int mode_t;
-typedef int ssize_t;
-typedef long off_t;
-
-#else
-#    include <sys/fcntl.h>
-#    include <sys/types.h>
-#    include <sys/syslimits.h>
-#endif
-
-#include "platform.h"
-
-namespace mbed {
-
-typedef enum {
-    FilePathType,
-    FileSystemPathType
-} PathType;
-
-class FileBase {
-public:
-    FileBase(const char *name, PathType t);
-
-    virtual ~FileBase();
-
-    const char* getName(void);
-    PathType    getPathType(void);
-
-    static FileBase *lookup(const char *name, unsigned int len);
-
-    static FileBase *get(int n);
-
-protected:
-    static FileBase *_head;
-
-    FileBase   *_next;
-    const char *_name;
-    PathType    _path_type;
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEBASE_H
+#define MBED_FILEBASE_H
+
+typedef int FILEHANDLE;
+
+#include <stdio.h>
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+#    define O_RDONLY 0
+#    define O_WRONLY 1
+#    define O_RDWR   2
+#    define O_CREAT  0x0200
+#    define O_TRUNC  0x0400
+#    define O_APPEND 0x0008
+
+#    define NAME_MAX 255
+
+typedef int mode_t;
+typedef int ssize_t;
+typedef long off_t;
+
+#else
+#    include <sys/fcntl.h>
+#    include <sys/types.h>
+#    include <sys/syslimits.h>
+#endif
+
+#include "platform.h"
+
+namespace mbed {
+
+typedef enum {
+    FilePathType,
+    FileSystemPathType
+} PathType;
+
+class FileBase {
+public:
+    FileBase(const char *name, PathType t);
+
+    virtual ~FileBase();
+
+    const char* getName(void);
+    PathType    getPathType(void);
+
+    static FileBase *lookup(const char *name, unsigned int len);
+
+    static FileBase *get(int n);
+
+protected:
+    static FileBase *_head;
+
+    FileBase   *_next;
+    const char *_name;
+    PathType    _path_type;
+};
+
+} // namespace mbed
+
+#endif

--- a/api/FileHandle.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/FileHandle.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,119 +1,119 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEHANDLE_H
-#define MBED_FILEHANDLE_H
-
-typedef int FILEHANDLE;
-
-#include <stdio.h>
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-typedef int ssize_t;
-typedef long off_t;
-
-#else
-#   include <sys/types.h>
-#endif
-
-namespace mbed {
-
-/** An OO equivalent of the internal FILEHANDLE variable
- *  and associated _sys_* functions.
- *
- * FileHandle is an abstract class, needing at least sys_write and
- *  sys_read to be implmented for a simple interactive device.
- *
- * No one ever directly tals to/instanciates a FileHandle - it gets
- *  created by FileSystem, and wrapped up by stdio.
- */
-class FileHandle {
-
-public:
-    /** Write the contents of a buffer to the file
-     *
-     *  @param buffer the buffer to write from
-     *  @param length the number of characters to write
-     *
-     *  @returns
-     *  The number of characters written (possibly 0) on success, -1 on error.
-     */
-    virtual ssize_t write(const void* buffer, size_t length) = 0;
-
-    /** Close the file
-     *
-     *  @returns
-     *  Zero on success, -1 on error.
-     */
-    virtual int close() = 0;
-
-    /** Function read
-     *  Reads the contents of the file into a buffer
-     *
-     *  @param buffer the buffer to read in to
-     *  @param length the number of characters to read
-     *
-     *  @returns
-     *  The number of characters read (zero at end of file) on success, -1 on error.
-     */
-    virtual ssize_t read(void* buffer, size_t length) = 0;
-
-    /** Check if the handle is for a interactive terminal device.
-     * If so, line buffered behaviour is used by default
-     *
-     *  @returns
-     *    1 if it is a terminal,
-     *    0 otherwise
-     */
-    virtual int isatty() = 0;
-
-    /** Move the file position to a given offset from a given location.
-     *
-     *  @param offset The offset from whence to move to
-     *  @param whence SEEK_SET for the start of the file, SEEK_CUR for the
-     *   current file position, or SEEK_END for the end of the file.
-     *
-     *  @returns
-     *    new file position on success,
-     *    -1 on failure or unsupported
-     */
-    virtual off_t lseek(off_t offset, int whence) = 0;
-
-    /** Flush any buffers associated with the FileHandle, ensuring it
-     *  is up to date on disk
-     *
-     *  @returns
-     *    0 on success or un-needed,
-     *   -1 on error
-     */
-    virtual int fsync() = 0;
-
-    virtual off_t flen() {
-        /* remember our current position */
-        off_t pos = lseek(0, SEEK_CUR);
-        if(pos == -1) return -1;
-        /* seek to the end to get the file length */
-        off_t res = lseek(0, SEEK_END);
-        /* return to our old position */
-        lseek(pos, SEEK_SET);
-        return res;
-    }
-
-    virtual ~FileHandle();
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEHANDLE_H
+#define MBED_FILEHANDLE_H
+
+typedef int FILEHANDLE;
+
+#include <stdio.h>
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+typedef int ssize_t;
+typedef long off_t;
+
+#else
+#   include <sys/types.h>
+#endif
+
+namespace mbed {
+
+/** An OO equivalent of the internal FILEHANDLE variable
+ *  and associated _sys_* functions.
+ *
+ * FileHandle is an abstract class, needing at least sys_write and
+ *  sys_read to be implmented for a simple interactive device.
+ *
+ * No one ever directly tals to/instanciates a FileHandle - it gets
+ *  created by FileSystem, and wrapped up by stdio.
+ */
+class FileHandle {
+
+public:
+    /** Write the contents of a buffer to the file
+     *
+     *  @param buffer the buffer to write from
+     *  @param length the number of characters to write
+     *
+     *  @returns
+     *  The number of characters written (possibly 0) on success, -1 on error.
+     */
+    virtual ssize_t write(const void* buffer, size_t length) = 0;
+
+    /** Close the file
+     *
+     *  @returns
+     *  Zero on success, -1 on error.
+     */
+    virtual int close() = 0;
+
+    /** Function read
+     *  Reads the contents of the file into a buffer
+     *
+     *  @param buffer the buffer to read in to
+     *  @param length the number of characters to read
+     *
+     *  @returns
+     *  The number of characters read (zero at end of file) on success, -1 on error.
+     */
+    virtual ssize_t read(void* buffer, size_t length) = 0;
+
+    /** Check if the handle is for a interactive terminal device.
+     * If so, line buffered behaviour is used by default
+     *
+     *  @returns
+     *    1 if it is a terminal,
+     *    0 otherwise
+     */
+    virtual int isatty() = 0;
+
+    /** Move the file position to a given offset from a given location.
+     *
+     *  @param offset The offset from whence to move to
+     *  @param whence SEEK_SET for the start of the file, SEEK_CUR for the
+     *   current file position, or SEEK_END for the end of the file.
+     *
+     *  @returns
+     *    new file position on success,
+     *    -1 on failure or unsupported
+     */
+    virtual off_t lseek(off_t offset, int whence) = 0;
+
+    /** Flush any buffers associated with the FileHandle, ensuring it
+     *  is up to date on disk
+     *
+     *  @returns
+     *    0 on success or un-needed,
+     *   -1 on error
+     */
+    virtual int fsync() = 0;
+
+    virtual off_t flen() {
+        /* remember our current position */
+        off_t pos = lseek(0, SEEK_CUR);
+        if(pos == -1) return -1;
+        /* seek to the end to get the file length */
+        off_t res = lseek(0, SEEK_END);
+        /* return to our old position */
+        lseek(pos, SEEK_SET);
+        return res;
+    }
+
+    virtual ~FileHandle();
+};
+
+} // namespace mbed
+
+#endif

--- a/api/FileLike.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/FileLike.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,44 +1,44 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILELIKE_H
-#define MBED_FILELIKE_H
-
-#include "FileBase.h"
-#include "FileHandle.h"
-
-namespace mbed {
-
-/* Class FileLike
- *  A file-like object is one that can be opened with fopen by
- *  fopen("/name", mode). It is intersection of the classes Base and
- *  FileHandle.
- */
-class FileLike : public FileHandle, public FileBase {
-
-public:
-    /* Constructor FileLike
-     *
-     * Variables
-     *  name - The name to use to open the file.
-     */
-    FileLike(const char *name);
-
-    virtual ~FileLike();
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILELIKE_H
+#define MBED_FILELIKE_H
+
+#include "FileBase.h"
+#include "FileHandle.h"
+
+namespace mbed {
+
+/* Class FileLike
+ *  A file-like object is one that can be opened with fopen by
+ *  fopen("/name", mode). It is intersection of the classes Base and
+ *  FileHandle.
+ */
+class FileLike : public FileHandle, public FileBase {
+
+public:
+    /* Constructor FileLike
+     *
+     * Variables
+     *  name - The name to use to open the file.
+     */
+    FileLike(const char *name);
+
+    virtual ~FileLike();
+};
+
+} // namespace mbed
+
+#endif

--- a/api/FilePath.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/FilePath.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,45 +1,45 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEPATH_H
-#define MBED_FILEPATH_H
-
-#include "platform.h"
-
-#include "FileSystemLike.h"
-#include "FileLike.h"
-
-namespace mbed {
-
-class FilePath {
-public:
-    FilePath(const char* file_path);
-
-    const char* fileName(void);
-
-    bool          isFileSystem(void);
-    FileSystemLike* fileSystem(void);
-
-    bool    isFile(void);
-    FileLike* file(void);
-
-private:
-    const char* file_name;
-    FileBase* fb;
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEPATH_H
+#define MBED_FILEPATH_H
+
+#include "platform.h"
+
+#include "FileSystemLike.h"
+#include "FileLike.h"
+
+namespace mbed {
+
+class FilePath {
+public:
+    FilePath(const char* file_path);
+
+    const char* fileName(void);
+
+    bool          isFileSystem(void);
+    FileSystemLike* fileSystem(void);
+
+    bool    isFile(void);
+    FileLike* file(void);
+
+private:
+    const char* file_name;
+    FileBase* fb;
+};
+
+} // namespace mbed
+
+#endif

--- a/api/FileSystemLike.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/FileSystemLike.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,104 +1,104 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILESYSTEMLIKE_H
-#define MBED_FILESYSTEMLIKE_H
-
-#include "platform.h"
-
-#include "FileBase.h"
-#include "FileHandle.h"
-#include "DirHandle.h"
-
-namespace mbed {
-
-/** A filesystem-like object is one that can be used to open files
- *  though it by fopen("/name/filename", mode)
- *
- *  Implementations must define at least open (the default definitions
- *  of the rest of the functions just return error values).
- */
-class FileSystemLike : public FileBase {
-
-public:
-    /** FileSystemLike constructor
-     *
-     *  @param name The name to use for the filesystem.
-     */
-    FileSystemLike(const char *name);
-
-    virtual ~FileSystemLike();
-
-    static DirHandle *opendir();
-    friend class BaseDirHandle;
-
-    /** Opens a file from the filesystem
-     *
-     *  @param filename The name of the file to open.
-     *  @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with
-     *    zero or more of O_CREAT, O_TRUNC, or O_APPEND.
-     *
-     *  @returns
-     *    A pointer to a FileHandle object representing the
-     *   file on success, or NULL on failure.
-     */
-    virtual FileHandle *open(const char *filename, int flags) = 0;
-
-    /** Remove a file from the filesystem.
-     *
-     *  @param filename the name of the file to remove.
-     *  @param returns 0 on success, -1 on failure.
-     */
-    virtual int remove(const char *filename) { return -1; };
-
-    /** Rename a file in the filesystem.
-     *
-     *  @param oldname the name of the file to rename.
-     *  @param newname the name to rename it to.
-     *
-     *  @returns
-     *    0 on success,
-     *   -1 on failure.
-     */
-    virtual int rename(const char *oldname, const char *newname) { return -1; };
-
-    /** Opens a directory in the filesystem and returns a DirHandle
-     *   representing the directory stream.
-     *
-     *  @param name The name of the directory to open.
-     *
-     *  @returns
-     *    A DirHandle representing the directory stream, or
-     *   NULL on failure.
-     */
-    virtual DirHandle *opendir(const char *name) { return NULL; };
-
-    /** Creates a directory in the filesystem.
-     *
-     *  @param name The name of the directory to create.
-     *  @param mode The permissions to create the directory with.
-     *
-     *  @returns
-     *    0 on success,
-     *   -1 on failure.
-     */
-    virtual int mkdir(const char *name, mode_t mode) { return -1; }
-
-    // TODO other filesystem functions (mkdir, rm, rn, ls etc)
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILESYSTEMLIKE_H
+#define MBED_FILESYSTEMLIKE_H
+
+#include "platform.h"
+
+#include "FileBase.h"
+#include "FileHandle.h"
+#include "DirHandle.h"
+
+namespace mbed {
+
+/** A filesystem-like object is one that can be used to open files
+ *  though it by fopen("/name/filename", mode)
+ *
+ *  Implementations must define at least open (the default definitions
+ *  of the rest of the functions just return error values).
+ */
+class FileSystemLike : public FileBase {
+
+public:
+    /** FileSystemLike constructor
+     *
+     *  @param name The name to use for the filesystem.
+     */
+    FileSystemLike(const char *name);
+
+    virtual ~FileSystemLike();
+
+    static DirHandle *opendir();
+    friend class BaseDirHandle;
+
+    /** Opens a file from the filesystem
+     *
+     *  @param filename The name of the file to open.
+     *  @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with
+     *    zero or more of O_CREAT, O_TRUNC, or O_APPEND.
+     *
+     *  @returns
+     *    A pointer to a FileHandle object representing the
+     *   file on success, or NULL on failure.
+     */
+    virtual FileHandle *open(const char *filename, int flags) = 0;
+
+    /** Remove a file from the filesystem.
+     *
+     *  @param filename the name of the file to remove.
+     *  @param returns 0 on success, -1 on failure.
+     */
+    virtual int remove(const char *filename) { return -1; };
+
+    /** Rename a file in the filesystem.
+     *
+     *  @param oldname the name of the file to rename.
+     *  @param newname the name to rename it to.
+     *
+     *  @returns
+     *    0 on success,
+     *   -1 on failure.
+     */
+    virtual int rename(const char *oldname, const char *newname) { return -1; };
+
+    /** Opens a directory in the filesystem and returns a DirHandle
+     *   representing the directory stream.
+     *
+     *  @param name The name of the directory to open.
+     *
+     *  @returns
+     *    A DirHandle representing the directory stream, or
+     *   NULL on failure.
+     */
+    virtual DirHandle *opendir(const char *name) { return NULL; };
+
+    /** Creates a directory in the filesystem.
+     *
+     *  @param name The name of the directory to create.
+     *  @param mode The permissions to create the directory with.
+     *
+     *  @returns
+     *    0 on success,
+     *   -1 on failure.
+     */
+    virtual int mkdir(const char *name, mode_t mode) { return -1; }
+
+    // TODO other filesystem functions (mkdir, rm, rn, ls etc)
+};
+
+} // namespace mbed
+
+#endif

--- a/api/FunctionPointer.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/FunctionPointer.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,84 +1,84 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FUNCTIONPOINTER_H
-#define MBED_FUNCTIONPOINTER_H
-
-#include <string.h>
-
-namespace mbed {
-
-/** A class for storing and calling a pointer to a static or member void function
- */
-class FunctionPointer {
-public:
-
-    /** Create a FunctionPointer, attaching a static function
-     *
-     *  @param function The void static function to attach (default is none)
-     */
-    FunctionPointer(void (*function)(void) = 0);
-
-    /** Create a FunctionPointer, attaching a member function
-     *
-     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
-     *  @param function The address of the void member function to attach
-     */
-    template<typename T>
-    FunctionPointer(T *object, void (T::*member)(void)) {
-        attach(object, member);
-    }
-
-    /** Attach a static function
-     *
-     *  @param function The void static function to attach (default is none)
-     */
-    void attach(void (*function)(void) = 0);
-
-    /** Attach a member function
-     *
-     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
-     *  @param function The address of the void member function to attach
-     */
-    template<typename T>
-    void attach(T *object, void (T::*member)(void)) {
-        _object = static_cast<void*>(object);
-        memcpy(_member, (char*)&member, sizeof(member));
-        _membercaller = &FunctionPointer::membercaller<T>;
-        _function = 0;
-    }
-
-    /** Call the attached static or member function
-     */
-    void call();
-
-private:
-    template<typename T>
-    static void membercaller(void *object, char *member) {
-        T* o = static_cast<T*>(object);
-        void (T::*m)(void);
-        memcpy((char*)&m, member, sizeof(m));
-        (o->*m)();
-    }
-
-    void (*_function)(void);                // static function pointer - 0 if none attached
-    void *_object;                            // object this pointer - 0 if none attached
-    char _member[16];                        // raw member function pointer storage - converted back by registered _membercaller
-    void (*_membercaller)(void*, char*);    // registered membercaller function to convert back and call _member on _object
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FUNCTIONPOINTER_H
+#define MBED_FUNCTIONPOINTER_H
+
+#include <string.h>
+
+namespace mbed {
+
+/** A class for storing and calling a pointer to a static or member void function
+ */
+class FunctionPointer {
+public:
+
+    /** Create a FunctionPointer, attaching a static function
+     *
+     *  @param function The void static function to attach (default is none)
+     */
+    FunctionPointer(void (*function)(void) = 0);
+
+    /** Create a FunctionPointer, attaching a member function
+     *
+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
+     *  @param function The address of the void member function to attach
+     */
+    template<typename T>
+    FunctionPointer(T *object, void (T::*member)(void)) {
+        attach(object, member);
+    }
+
+    /** Attach a static function
+     *
+     *  @param function The void static function to attach (default is none)
+     */
+    void attach(void (*function)(void) = 0);
+
+    /** Attach a member function
+     *
+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
+     *  @param function The address of the void member function to attach
+     */
+    template<typename T>
+    void attach(T *object, void (T::*member)(void)) {
+        _object = static_cast<void*>(object);
+        memcpy(_member, (char*)&member, sizeof(member));
+        _membercaller = &FunctionPointer::membercaller<T>;
+        _function = 0;
+    }
+
+    /** Call the attached static or member function
+     */
+    void call();
+
+private:
+    template<typename T>
+    static void membercaller(void *object, char *member) {
+        T* o = static_cast<T*>(object);
+        void (T::*m)(void);
+        memcpy((char*)&m, member, sizeof(m));
+        (o->*m)();
+    }
+
+    void (*_function)(void);                // static function pointer - 0 if none attached
+    void *_object;                            // object this pointer - 0 if none attached
+    char _member[16];                        // raw member function pointer storage - converted back by registered _membercaller
+    void (*_membercaller)(void*, char*);    // registered membercaller function to convert back and call _member on _object
+};
+
+} // namespace mbed
+
+#endif

--- a/api/I2C.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/I2C.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,144 +1,144 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_H
-#define MBED_I2C_H
-
-#include "platform.h"
-
-#if DEVICE_I2C
-
-#include "i2c_api.h"
-
-namespace mbed {
-
-/** An I2C Master, used for communicating with I2C slave devices
- *
- * Example:
- * @code
- * // Read from I2C slave at address 0x62
- *
- * #include "mbed.h"
- *
- * I2C i2c(p28, p27);
- *
- * int main() {
- *     int address = 0x62;
- *     char data[2];
- *     i2c.read(address, data, 2);
- * }
- * @endcode
- */
-class I2C {
-
-public:
-    enum RxStatus {
-        NoData,
-        MasterGeneralCall,
-        MasterWrite,
-        MasterRead
-    };
-
-    enum Acknowledge {
-        NoACK = 0,
-        ACK   = 1
-    };
-
-    /** Create an I2C Master interface, connected to the specified pins
-     *
-     *  @param sda I2C data line pin
-     *  @param scl I2C clock line pin
-     */
-    I2C(PinName sda, PinName scl);
-
-    /** Set the frequency of the I2C interface
-     *
-     *  @param hz The bus frequency in hertz
-     */
-    void frequency(int hz);
-
-    /** Read from an I2C slave
-     *
-     * Performs a complete read transaction. The bottom bit of
-     * the address is forced to 1 to indicate a read.
-     *
-     *  @param address 8-bit I2C slave address [ addr | 1 ]
-     *  @param data Pointer to the byte-array to read data in to
-     *  @param length Number of bytes to read
-     *  @param repeated Repeated start, true - don't send stop at end
-     *
-     *  @returns
-     *       0 on success (ack),
-     *   non-0 on failure (nack)
-     */
-    int read(int address, char *data, int length, bool repeated = false);
-
-    /** Read a single byte from the I2C bus
-     *
-     *  @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
-     *
-     *  @returns
-     *    the byte read
-     */
-    int read(int ack);
-
-    /** Write to an I2C slave
-     *
-     * Performs a complete write transaction. The bottom bit of
-     * the address is forced to 0 to indicate a write.
-     *
-     *  @param address 8-bit I2C slave address [ addr | 0 ]
-     *  @param data Pointer to the byte-array data to send
-     *  @param length Number of bytes to send
-     *  @param repeated Repeated start, true - do not send stop at end
-     *
-     *  @returns
-     *       0 on success (ack),
-     *   non-0 on failure (nack)
-     */
-    int write(int address, const char *data, int length, bool repeated = false);
-
-    /** Write single byte out on the I2C bus
-     *
-     *  @param data data to write out on bus
-     *
-     *  @returns
-     *    '1' if an ACK was received,
-     *    '0' otherwise
-     */
-    int write(int data);
-
-    /** Creates a start condition on the I2C bus
-     */
-
-    void start(void);
-
-    /** Creates a stop condition on the I2C bus
-     */
-    void stop(void);
-
-protected:
-    void aquire();
-
-    i2c_t _i2c;
-    static I2C  *_owner;
-    int         _hz;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_H
+#define MBED_I2C_H
+
+#include "platform.h"
+
+#if DEVICE_I2C
+
+#include "i2c_api.h"
+
+namespace mbed {
+
+/** An I2C Master, used for communicating with I2C slave devices
+ *
+ * Example:
+ * @code
+ * // Read from I2C slave at address 0x62
+ *
+ * #include "mbed.h"
+ *
+ * I2C i2c(p28, p27);
+ *
+ * int main() {
+ *     int address = 0x62;
+ *     char data[2];
+ *     i2c.read(address, data, 2);
+ * }
+ * @endcode
+ */
+class I2C {
+
+public:
+    enum RxStatus {
+        NoData,
+        MasterGeneralCall,
+        MasterWrite,
+        MasterRead
+    };
+
+    enum Acknowledge {
+        NoACK = 0,
+        ACK   = 1
+    };
+
+    /** Create an I2C Master interface, connected to the specified pins
+     *
+     *  @param sda I2C data line pin
+     *  @param scl I2C clock line pin
+     */
+    I2C(PinName sda, PinName scl);
+
+    /** Set the frequency of the I2C interface
+     *
+     *  @param hz The bus frequency in hertz
+     */
+    void frequency(int hz);
+
+    /** Read from an I2C slave
+     *
+     * Performs a complete read transaction. The bottom bit of
+     * the address is forced to 1 to indicate a read.
+     *
+     *  @param address 8-bit I2C slave address [ addr | 1 ]
+     *  @param data Pointer to the byte-array to read data in to
+     *  @param length Number of bytes to read
+     *  @param repeated Repeated start, true - don't send stop at end
+     *
+     *  @returns
+     *       0 on success (ack),
+     *   non-0 on failure (nack)
+     */
+    int read(int address, char *data, int length, bool repeated = false);
+
+    /** Read a single byte from the I2C bus
+     *
+     *  @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
+     *
+     *  @returns
+     *    the byte read
+     */
+    int read(int ack);
+
+    /** Write to an I2C slave
+     *
+     * Performs a complete write transaction. The bottom bit of
+     * the address is forced to 0 to indicate a write.
+     *
+     *  @param address 8-bit I2C slave address [ addr | 0 ]
+     *  @param data Pointer to the byte-array data to send
+     *  @param length Number of bytes to send
+     *  @param repeated Repeated start, true - do not send stop at end
+     *
+     *  @returns
+     *       0 on success (ack),
+     *   non-0 on failure (nack)
+     */
+    int write(int address, const char *data, int length, bool repeated = false);
+
+    /** Write single byte out on the I2C bus
+     *
+     *  @param data data to write out on bus
+     *
+     *  @returns
+     *    '1' if an ACK was received,
+     *    '0' otherwise
+     */
+    int write(int data);
+
+    /** Creates a start condition on the I2C bus
+     */
+
+    void start(void);
+
+    /** Creates a stop condition on the I2C bus
+     */
+    void stop(void);
+
+protected:
+    void aquire();
+
+    i2c_t _i2c;
+    static I2C  *_owner;
+    int         _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/I2CSlave.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/I2CSlave.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,154 +1,154 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_SLAVE_H
-#define MBED_I2C_SLAVE_H
-
-#include "platform.h"
-
-#if DEVICE_I2CSLAVE
-
-#include "i2c_api.h"
-
-namespace mbed {
-
-/** An I2C Slave, used for communicating with an I2C Master device
- *
- * Example:
- * @code
- * // Simple I2C responder
- * #include <mbed.h>
- *
- * I2CSlave slave(p9, p10);
- *
- * int main() {
- *     char buf[10];
- *     char msg[] = "Slave!";
- *
- *     slave.address(0xA0);
- *     while (1) {
- *         int i = slave.receive();
- *         switch (i) {
- *             case I2CSlave::ReadAddressed:
- *                 slave.write(msg, strlen(msg) + 1); // Includes null char
- *                 break;
- *             case I2CSlave::WriteGeneral:
- *                 slave.read(buf, 10);
- *                 printf("Read G: %s\n", buf);
- *                 break;
- *             case I2CSlave::WriteAddressed:
- *                 slave.read(buf, 10);
- *                 printf("Read A: %s\n", buf);
- *                 break;
- *         }
- *         for(int i = 0; i < 10; i++) buf[i] = 0;    // Clear buffer
- *     }
- * }
- * @endcode
- */
-class I2CSlave {
-
-public:
-    enum RxStatus {
-        NoData         = 0,
-        ReadAddressed  = 1,
-        WriteGeneral   = 2,
-        WriteAddressed = 3
-    };
-
-    /** Create an I2C Slave interface, connected to the specified pins.
-     *
-     *  @param sda I2C data line pin
-     *  @param scl I2C clock line pin
-     */
-    I2CSlave(PinName sda, PinName scl);
-
-    /** Set the frequency of the I2C interface
-     *
-     *  @param hz The bus frequency in hertz
-     */
-    void frequency(int hz);
-
-    /** Checks to see if this I2C Slave has been addressed.
-     *
-     *  @returns
-     *  A status indicating if the device has been addressed, and how
-     *  - NoData            - the slave has not been addressed
-     *  - ReadAddressed     - the master has requested a read from this slave
-     *  - WriteAddressed    - the master is writing to this slave
-     *  - WriteGeneral      - the master is writing to all slave
-     */
-    int receive(void);
-
-    /** Read from an I2C master.
-     *
-     *  @param data pointer to the byte array to read data in to
-     *  @param length maximum number of bytes to read
-     *
-     *  @returns
-     *       0 on success,
-     *   non-0 otherwise
-     */
-    int read(char *data, int length);
-
-    /** Read a single byte from an I2C master.
-     *
-     *  @returns
-     *    the byte read
-     */
-    int read(void);
-
-    /** Write to an I2C master.
-     *
-     *  @param data pointer to the byte array to be transmitted
-     *  @param length the number of bytes to transmite
-     *
-     *  @returns
-     *       0 on success,
-     *   non-0 otherwise
-     */
-    int write(const char *data, int length);
-
-    /** Write a single byte to an I2C master.
-     *
-     *  @data the byte to write
-     *
-     *  @returns
-     *    '1' if an ACK was received,
-     *    '0' otherwise
-     */
-    int write(int data);
-
-    /** Sets the I2C slave address.
-     *
-     *  @param address The address to set for the slave (ignoring the least
-     *  signifcant bit). If set to 0, the slave will only respond to the
-     *  general call address.
-     */
-    void address(int address);
-
-    /** Reset the I2C slave back into the known ready receiving state.
-     */
-    void stop(void);
-
-protected:
-    i2c_t _i2c;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_SLAVE_H
+#define MBED_I2C_SLAVE_H
+
+#include "platform.h"
+
+#if DEVICE_I2CSLAVE
+
+#include "i2c_api.h"
+
+namespace mbed {
+
+/** An I2C Slave, used for communicating with an I2C Master device
+ *
+ * Example:
+ * @code
+ * // Simple I2C responder
+ * #include <mbed.h>
+ *
+ * I2CSlave slave(p9, p10);
+ *
+ * int main() {
+ *     char buf[10];
+ *     char msg[] = "Slave!";
+ *
+ *     slave.address(0xA0);
+ *     while (1) {
+ *         int i = slave.receive();
+ *         switch (i) {
+ *             case I2CSlave::ReadAddressed:
+ *                 slave.write(msg, strlen(msg) + 1); // Includes null char
+ *                 break;
+ *             case I2CSlave::WriteGeneral:
+ *                 slave.read(buf, 10);
+ *                 printf("Read G: %s\n", buf);
+ *                 break;
+ *             case I2CSlave::WriteAddressed:
+ *                 slave.read(buf, 10);
+ *                 printf("Read A: %s\n", buf);
+ *                 break;
+ *         }
+ *         for(int i = 0; i < 10; i++) buf[i] = 0;    // Clear buffer
+ *     }
+ * }
+ * @endcode
+ */
+class I2CSlave {
+
+public:
+    enum RxStatus {
+        NoData         = 0,
+        ReadAddressed  = 1,
+        WriteGeneral   = 2,
+        WriteAddressed = 3
+    };
+
+    /** Create an I2C Slave interface, connected to the specified pins.
+     *
+     *  @param sda I2C data line pin
+     *  @param scl I2C clock line pin
+     */
+    I2CSlave(PinName sda, PinName scl);
+
+    /** Set the frequency of the I2C interface
+     *
+     *  @param hz The bus frequency in hertz
+     */
+    void frequency(int hz);
+
+    /** Checks to see if this I2C Slave has been addressed.
+     *
+     *  @returns
+     *  A status indicating if the device has been addressed, and how
+     *  - NoData            - the slave has not been addressed
+     *  - ReadAddressed     - the master has requested a read from this slave
+     *  - WriteAddressed    - the master is writing to this slave
+     *  - WriteGeneral      - the master is writing to all slave
+     */
+    int receive(void);
+
+    /** Read from an I2C master.
+     *
+     *  @param data pointer to the byte array to read data in to
+     *  @param length maximum number of bytes to read
+     *
+     *  @returns
+     *       0 on success,
+     *   non-0 otherwise
+     */
+    int read(char *data, int length);
+
+    /** Read a single byte from an I2C master.
+     *
+     *  @returns
+     *    the byte read
+     */
+    int read(void);
+
+    /** Write to an I2C master.
+     *
+     *  @param data pointer to the byte array to be transmitted
+     *  @param length the number of bytes to transmite
+     *
+     *  @returns
+     *       0 on success,
+     *   non-0 otherwise
+     */
+    int write(const char *data, int length);
+
+    /** Write a single byte to an I2C master.
+     *
+     *  @data the byte to write
+     *
+     *  @returns
+     *    '1' if an ACK was received,
+     *    '0' otherwise
+     */
+    int write(int data);
+
+    /** Sets the I2C slave address.
+     *
+     *  @param address The address to set for the slave (ignoring the least
+     *  signifcant bit). If set to 0, the slave will only respond to the
+     *  general call address.
+     */
+    void address(int address);
+
+    /** Reset the I2C slave back into the known ready receiving state.
+     */
+    void stop(void);
+
+protected:
+    i2c_t _i2c;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/InterruptIn.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/InterruptIn.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,126 +1,126 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_INTERRUPTIN_H
-#define MBED_INTERRUPTIN_H
-
-#include "platform.h"
-
-#if DEVICE_INTERRUPTIN
-
-#include "gpio_api.h"
-#include "gpio_irq_api.h"
-
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-/** A digital interrupt input, used to call a function on a rising or falling edge
- *
- * Example:
- * @code
- * // Flash an LED while waiting for events
- *
- * #include "mbed.h"
- *
- * InterruptIn event(p16);
- * DigitalOut led(LED1);
- *
- * void trigger() {
- *     printf("triggered!\n");
- * }
- *
- * int main() {
- *     event.rise(&trigger);
- *     while(1) {
- *         led = !led;
- *         wait(0.25);
- *     }
- * }
- * @endcode
- */
-class InterruptIn {
-
-public:
-
-    /** Create an InterruptIn connected to the specified pin
-     *
-     *  @param pin InterruptIn pin to connect to
-     *  @param name (optional) A string to identify the object
-     */
-    InterruptIn(PinName pin);
-    virtual ~InterruptIn();
-
-     int read();
-#ifdef MBED_OPERATORS
-    operator int();
-
-#endif
-
-    /** Attach a function to call when a rising edge occurs on the input
-     *
-     *  @param fptr A pointer to a void function, or 0 to set as none
-     */
-    void rise(void (*fptr)(void));
-
-    /** Attach a member function to call when a rising edge occurs on the input
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     */
-    template<typename T>
-    void rise(T* tptr, void (T::*mptr)(void)) {
-        _rise.attach(tptr, mptr);
-        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
-    }
-
-    /** Attach a function to call when a falling edge occurs on the input
-     *
-     *  @param fptr A pointer to a void function, or 0 to set as none
-     */
-    void fall(void (*fptr)(void));
-
-    /** Attach a member function to call when a falling edge occurs on the input
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     */
-    template<typename T>
-    void fall(T* tptr, void (T::*mptr)(void)) {
-        _fall.attach(tptr, mptr);
-        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone
-     */
-    void mode(PinMode pull);
-
-    static void _irq_handler(uint32_t id, gpio_irq_event event);
-
-protected:
-    gpio_t gpio;
-    gpio_irq_t gpio_irq;
-
-    FunctionPointer _rise;
-    FunctionPointer _fall;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERRUPTIN_H
+#define MBED_INTERRUPTIN_H
+
+#include "platform.h"
+
+#if DEVICE_INTERRUPTIN
+
+#include "gpio_api.h"
+#include "gpio_irq_api.h"
+
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** A digital interrupt input, used to call a function on a rising or falling edge
+ *
+ * Example:
+ * @code
+ * // Flash an LED while waiting for events
+ *
+ * #include "mbed.h"
+ *
+ * InterruptIn event(p16);
+ * DigitalOut led(LED1);
+ *
+ * void trigger() {
+ *     printf("triggered!\n");
+ * }
+ *
+ * int main() {
+ *     event.rise(&trigger);
+ *     while(1) {
+ *         led = !led;
+ *         wait(0.25);
+ *     }
+ * }
+ * @endcode
+ */
+class InterruptIn {
+
+public:
+
+    /** Create an InterruptIn connected to the specified pin
+     *
+     *  @param pin InterruptIn pin to connect to
+     *  @param name (optional) A string to identify the object
+     */
+    InterruptIn(PinName pin);
+    virtual ~InterruptIn();
+
+     int read();
+#ifdef MBED_OPERATORS
+    operator int();
+
+#endif
+
+    /** Attach a function to call when a rising edge occurs on the input
+     *
+     *  @param fptr A pointer to a void function, or 0 to set as none
+     */
+    void rise(void (*fptr)(void));
+
+    /** Attach a member function to call when a rising edge occurs on the input
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     */
+    template<typename T>
+    void rise(T* tptr, void (T::*mptr)(void)) {
+        _rise.attach(tptr, mptr);
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+    }
+
+    /** Attach a function to call when a falling edge occurs on the input
+     *
+     *  @param fptr A pointer to a void function, or 0 to set as none
+     */
+    void fall(void (*fptr)(void));
+
+    /** Attach a member function to call when a falling edge occurs on the input
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     */
+    template<typename T>
+    void fall(T* tptr, void (T::*mptr)(void)) {
+        _fall.attach(tptr, mptr);
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+    static void _irq_handler(uint32_t id, gpio_irq_event event);
+
+protected:
+    gpio_t gpio;
+    gpio_irq_t gpio_irq;
+
+    FunctionPointer _rise;
+    FunctionPointer _fall;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/LocalFileSystem.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/LocalFileSystem.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,103 +1,103 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOCALFILESYSTEM_H
-#define MBED_LOCALFILESYSTEM_H
-
-#include "platform.h"
-
-#if DEVICE_LOCALFILESYSTEM
-
-#include "FileSystemLike.h"
-
-namespace mbed {
-
-FILEHANDLE local_file_open(const char* name, int flags);
-
-class LocalFileHandle : public FileHandle {
-
-public:
-    LocalFileHandle(FILEHANDLE fh);
-
-    virtual int close();
-
-    virtual ssize_t write(const void *buffer, size_t length);
-
-    virtual ssize_t read(void *buffer, size_t length);
-
-    virtual int isatty();
-
-    virtual off_t lseek(off_t position, int whence);
-
-    virtual int fsync();
-
-    virtual off_t flen();
-
-protected:
-    FILEHANDLE _fh;
-    int pos;
-};
-
-/** A filesystem for accessing the local mbed Microcontroller USB disk drive
- *
- *  This allows programs to read and write files on the same disk drive that is used to program the
- *  mbed Microcontroller. Once created, the standard C file access functions are used to open,
- *  read and write files.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * LocalFileSystem local("local");               // Create the local filesystem under the name "local"
- *
- * int main() {
- *     FILE *fp = fopen("/local/out.txt", "w");  // Open "out.txt" on the local file system for writing
- *     fprintf(fp, "Hello World!");
- *     fclose(fp);
- *     remove("/local/out.txt");                 // Removes the file "out.txt" from the local file system
- *
- *     DIR *d = opendir("/local");               // Opens the root directory of the local file system
- *     struct dirent *p;
- *     while((p = readdir(d)) != NULL) {         // Print the names of the files in the local file system
- *       printf("%s\n", p->d_name);              // to stdout.
- *     }
- *     closedir(d);
- * }
- * @endcode
- *
- * @note
- *  If the microcontroller program makes an access to the local drive, it will be marked as "removed"
- *  on the Host computer. This means it is no longer accessible from the Host Computer.
- *
- *  The drive will only re-appear when the microcontroller program exists. Note that if the program does
- *  not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
- */
-class LocalFileSystem : public FileSystemLike {
-
-public:
-    LocalFileSystem(const char* n) : FileSystemLike(n) {
-
-    }
-
-    virtual FileHandle *open(const char* name, int flags);
-    virtual int remove(const char *filename);
-    virtual DirHandle *opendir(const char *name);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOCALFILESYSTEM_H
+#define MBED_LOCALFILESYSTEM_H
+
+#include "platform.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "FileSystemLike.h"
+
+namespace mbed {
+
+FILEHANDLE local_file_open(const char* name, int flags);
+
+class LocalFileHandle : public FileHandle {
+
+public:
+    LocalFileHandle(FILEHANDLE fh);
+
+    virtual int close();
+
+    virtual ssize_t write(const void *buffer, size_t length);
+
+    virtual ssize_t read(void *buffer, size_t length);
+
+    virtual int isatty();
+
+    virtual off_t lseek(off_t position, int whence);
+
+    virtual int fsync();
+
+    virtual off_t flen();
+
+protected:
+    FILEHANDLE _fh;
+    int pos;
+};
+
+/** A filesystem for accessing the local mbed Microcontroller USB disk drive
+ *
+ *  This allows programs to read and write files on the same disk drive that is used to program the
+ *  mbed Microcontroller. Once created, the standard C file access functions are used to open,
+ *  read and write files.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * LocalFileSystem local("local");               // Create the local filesystem under the name "local"
+ *
+ * int main() {
+ *     FILE *fp = fopen("/local/out.txt", "w");  // Open "out.txt" on the local file system for writing
+ *     fprintf(fp, "Hello World!");
+ *     fclose(fp);
+ *     remove("/local/out.txt");                 // Removes the file "out.txt" from the local file system
+ *
+ *     DIR *d = opendir("/local");               // Opens the root directory of the local file system
+ *     struct dirent *p;
+ *     while((p = readdir(d)) != NULL) {         // Print the names of the files in the local file system
+ *       printf("%s\n", p->d_name);              // to stdout.
+ *     }
+ *     closedir(d);
+ * }
+ * @endcode
+ *
+ * @note
+ *  If the microcontroller program makes an access to the local drive, it will be marked as "removed"
+ *  on the Host computer. This means it is no longer accessible from the Host Computer.
+ *
+ *  The drive will only re-appear when the microcontroller program exists. Note that if the program does
+ *  not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
+ */
+class LocalFileSystem : public FileSystemLike {
+
+public:
+    LocalFileSystem(const char* n) : FileSystemLike(n) {
+
+    }
+
+    virtual FileHandle *open(const char* name, int flags);
+    virtual int remove(const char *filename);
+    virtual DirHandle *opendir(const char *name);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/PortIn.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/PortIn.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,93 +1,93 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTIN_H
-#define MBED_PORTIN_H
-
-#include "platform.h"
-
-#if DEVICE_PORTIN
-
-#include "port_api.h"
-
-namespace mbed {
-
-/** A multiple pin digital input
- *
- *  Example:
- * @code
- * // Switch on an LED if any of mbed pins 21-26 is high
- *
- * #include "mbed.h"
- *
- * PortIn     p(Port2, 0x0000003F);   // p21-p26
- * DigitalOut ind(LED4);
- *
- * int main() {
- *     while(1) {
- *         int pins = p.read();
- *         if(pins) {
- *             ind = 1;
- *         } else {
- *             ind = 0;
- *         }
- *     }
- * }
- * @endcode
- */
-class PortIn {
-public:
-
-    /** Create an PortIn, connected to the specified port
-     *
-     *  @param port Port to connect to (Port0-Port5)
-     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
-        */
-    PortIn(PortName port, int mask = 0xFFFFFFFF) {
-        port_init(&_port, port, mask, PIN_INPUT);
-    }
-
-    /** Read the value currently output on the port
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated port pin setting
-     */
-    int read() {
-        return port_read(&_port);
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone, OpenDrain
-     */
-    void mode(PinMode mode) {
-        port_mode(&_port, mode);
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-
-private:
-    port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTIN_H
+#define MBED_PORTIN_H
+
+#include "platform.h"
+
+#if DEVICE_PORTIN
+
+#include "port_api.h"
+
+namespace mbed {
+
+/** A multiple pin digital input
+ *
+ *  Example:
+ * @code
+ * // Switch on an LED if any of mbed pins 21-26 is high
+ *
+ * #include "mbed.h"
+ *
+ * PortIn     p(Port2, 0x0000003F);   // p21-p26
+ * DigitalOut ind(LED4);
+ *
+ * int main() {
+ *     while(1) {
+ *         int pins = p.read();
+ *         if(pins) {
+ *             ind = 1;
+ *         } else {
+ *             ind = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class PortIn {
+public:
+
+    /** Create an PortIn, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+        */
+    PortIn(PortName port, int mask = 0xFFFFFFFF) {
+        port_init(&_port, port, mask, PIN_INPUT);
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated port pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode mode) {
+        port_mode(&_port, mode);
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/PortInOut.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/PortInOut.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,104 +1,104 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTINOUT_H
-#define MBED_PORTINOUT_H
-
-#include "platform.h"
-
-#if DEVICE_PORTINOUT
-
-#include "port_api.h"
-
-namespace mbed {
-
-/** A multiple pin digital in/out used to set/read multiple bi-directional pins
- */
-class PortInOut {
-public:
-
-    /** Create an PortInOut, connected to the specified port
-     *
-     *  @param port Port to connect to (Port0-Port5)
-     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
-     */
-    PortInOut(PortName port, int mask = 0xFFFFFFFF) {
-        port_init(&_port, port, mask, PIN_INPUT);
-    }
-
-    /** Write the value to the output port
-     *
-     *  @param value An integer specifying a bit to write for every corresponding port pin
-     */
-    void write(int value) {
-        port_write(&_port, value);
-    }
-
-    /** Read the value currently output on the port
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated port pin setting
-     */
-    int read() {
-        return port_read(&_port);
-    }
-
-    /** Set as an output
-     */
-    void output() {
-        port_dir(&_port, PIN_OUTPUT);
-    }
-
-    /** Set as an input
-     */
-    void input() {
-        port_dir(&_port, PIN_INPUT);
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone, OpenDrain
-     */
-    void mode(PinMode mode) {
-        port_mode(&_port, mode);
-    }
-
-    /** A shorthand for write()
-     */
-    PortInOut& operator= (int value) {
-        write(value);
-        return *this;
-    }
-
-    PortInOut& operator= (PortInOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-
-private:
-    port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTINOUT_H
+#define MBED_PORTINOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PORTINOUT
+
+#include "port_api.h"
+
+namespace mbed {
+
+/** A multiple pin digital in/out used to set/read multiple bi-directional pins
+ */
+class PortInOut {
+public:
+
+    /** Create an PortInOut, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+     */
+    PortInOut(PortName port, int mask = 0xFFFFFFFF) {
+        port_init(&_port, port, mask, PIN_INPUT);
+    }
+
+    /** Write the value to the output port
+     *
+     *  @param value An integer specifying a bit to write for every corresponding port pin
+     */
+    void write(int value) {
+        port_write(&_port, value);
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated port pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** Set as an output
+     */
+    void output() {
+        port_dir(&_port, PIN_OUTPUT);
+    }
+
+    /** Set as an input
+     */
+    void input() {
+        port_dir(&_port, PIN_INPUT);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode mode) {
+        port_mode(&_port, mode);
+    }
+
+    /** A shorthand for write()
+     */
+    PortInOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    PortInOut& operator= (PortInOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/PortOut.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/PortOut.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,104 +1,104 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTOUT_H
-#define MBED_PORTOUT_H
-
-#include "platform.h"
-
-#if DEVICE_PORTOUT
-
-#include "port_api.h"
-
-namespace mbed {
-/** A multiple pin digital out
- *
- * Example:
- * @code
- * // Toggle all four LEDs
- *
- * #include "mbed.h"
- *
- * // LED1 = P1.18  LED2 = P1.20  LED3 = P1.21  LED4 = P1.23
- * #define LED_MASK 0x00B40000
- *
- * PortOut ledport(Port1, LED_MASK);
- *
- * int main() {
- *     while(1) {
- *         ledport = LED_MASK;
- *         wait(1);
- *         ledport = 0;
- *         wait(1);
- *     }
- * }
- * @endcode
- */
-class PortOut {
-public:
-
-    /** Create an PortOut, connected to the specified port
-     *
-     *  @param port Port to connect to (Port0-Port5)
-     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
-     */
-    PortOut(PortName port, int mask = 0xFFFFFFFF) {
-        port_init(&_port, port, mask, PIN_OUTPUT);
-    }
-
-    /** Write the value to the output port
-     *
-     *  @param value An integer specifying a bit to write for every corresponding PortOut pin
-     */
-    void write(int value) {
-        port_write(&_port, value);
-    }
-
-    /** Read the value currently output on the port
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated PortOut pin setting
-     */
-    int read() {
-        return port_read(&_port);
-    }
-
-    /** A shorthand for write()
-     */
-    PortOut& operator= (int value) {
-        write(value);
-        return *this;
-    }
-
-    PortOut& operator= (PortOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-
-private:
-    port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTOUT_H
+#define MBED_PORTOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PORTOUT
+
+#include "port_api.h"
+
+namespace mbed {
+/** A multiple pin digital out
+ *
+ * Example:
+ * @code
+ * // Toggle all four LEDs
+ *
+ * #include "mbed.h"
+ *
+ * // LED1 = P1.18  LED2 = P1.20  LED3 = P1.21  LED4 = P1.23
+ * #define LED_MASK 0x00B40000
+ *
+ * PortOut ledport(Port1, LED_MASK);
+ *
+ * int main() {
+ *     while(1) {
+ *         ledport = LED_MASK;
+ *         wait(1);
+ *         ledport = 0;
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ */
+class PortOut {
+public:
+
+    /** Create an PortOut, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+     */
+    PortOut(PortName port, int mask = 0xFFFFFFFF) {
+        port_init(&_port, port, mask, PIN_OUTPUT);
+    }
+
+    /** Write the value to the output port
+     *
+     *  @param value An integer specifying a bit to write for every corresponding PortOut pin
+     */
+    void write(int value) {
+        port_write(&_port, value);
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated PortOut pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** A shorthand for write()
+     */
+    PortOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    PortOut& operator= (PortOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/PwmOut.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/PwmOut.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,158 +1,158 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PWMOUT_H
-#define MBED_PWMOUT_H
-
-#include "platform.h"
-
-#if DEVICE_PWMOUT
-#include "pwmout_api.h"
-
-namespace mbed {
-
-/** A pulse-width modulation digital output
- *
- * Example
- * @code
- * // Fade a led on.
- * #include "mbed.h"
- *
- * PwmOut led(LED1);
- *
- * int main() {
- *     while(1) {
- *         led = led + 0.01;
- *         wait(0.2);
- *         if(led == 1.0) {
- *             led = 0;
- *         }
- *     }
- * }
- * @endcode
- *
- * @note
- *  On the LPC1768 and LPC2368, the PWMs all share the same
- *  period - if you change the period for one, you change it for all.
- *  Although routines that change the period maintain the duty cycle
- *  for its PWM, all other PWMs will require their duty cycle to be
- *  refreshed.
- */
-class PwmOut {
-
-public:
-
-    /** Create a PwmOut connected to the specified pin
-     *
-     *  @param pin PwmOut pin to connect to
-     */
-    PwmOut(PinName pin) {
-        pwmout_init(&_pwm, pin);
-    }
-
-    /** Set the ouput duty-cycle, specified as a percentage (float)
-     *
-     *  @param value A floating-point value representing the output duty-cycle,
-     *    specified as a percentage. The value should lie between
-     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
-     *    Values outside this range will be saturated to 0.0f or 1.0f.
-     */
-    void write(float value) {
-        pwmout_write(&_pwm, value);
-    }
-
-    /** Return the current output duty-cycle setting, measured as a percentage (float)
-     *
-     *  @returns
-     *    A floating-point value representing the current duty-cycle being output on the pin,
-     *    measured as a percentage. The returned value will lie between
-     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
-     *
-     *  @note
-     *  This value may not match exactly the value set by a previous <write>.
-     */
-    float read() {
-        return pwmout_read(&_pwm);
-    }
-
-    /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
-     *
-     *  @note
-     *   The resolution is currently in microseconds; periods smaller than this
-     *   will be set to zero.
-     */
-    void period(float seconds) {
-        pwmout_period(&_pwm, seconds);
-    }
-
-    /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
-     */
-    void period_ms(int ms) {
-        pwmout_period_ms(&_pwm, ms);
-    }
-
-    /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
-     */
-    void period_us(int us) {
-        pwmout_period_us(&_pwm, us);
-    }
-
-    /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
-     */
-    void pulsewidth(float seconds) {
-        pwmout_pulsewidth(&_pwm, seconds);
-    }
-
-    /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
-     */
-    void pulsewidth_ms(int ms) {
-        pwmout_pulsewidth_ms(&_pwm, ms);
-    }
-
-    /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
-     */
-    void pulsewidth_us(int us) {
-        pwmout_pulsewidth_us(&_pwm, us);
-    }
-
-#ifdef MBED_OPERATORS
-    /** A operator shorthand for write()
-     */
-    PwmOut& operator= (float value) {
-        write(value);
-        return *this;
-    }
-
-    PwmOut& operator= (PwmOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** An operator shorthand for read()
-     */
-    operator float() {
-        return read();
-    }
-#endif
-
-protected:
-    pwmout_t _pwm;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_H
+#define MBED_PWMOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PWMOUT
+#include "pwmout_api.h"
+
+namespace mbed {
+
+/** A pulse-width modulation digital output
+ *
+ * Example
+ * @code
+ * // Fade a led on.
+ * #include "mbed.h"
+ *
+ * PwmOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         led = led + 0.01;
+ *         wait(0.2);
+ *         if(led == 1.0) {
+ *             led = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ *
+ * @note
+ *  On the LPC1768 and LPC2368, the PWMs all share the same
+ *  period - if you change the period for one, you change it for all.
+ *  Although routines that change the period maintain the duty cycle
+ *  for its PWM, all other PWMs will require their duty cycle to be
+ *  refreshed.
+ */
+class PwmOut {
+
+public:
+
+    /** Create a PwmOut connected to the specified pin
+     *
+     *  @param pin PwmOut pin to connect to
+     */
+    PwmOut(PinName pin) {
+        pwmout_init(&_pwm, pin);
+    }
+
+    /** Set the ouput duty-cycle, specified as a percentage (float)
+     *
+     *  @param value A floating-point value representing the output duty-cycle,
+     *    specified as a percentage. The value should lie between
+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
+     *    Values outside this range will be saturated to 0.0f or 1.0f.
+     */
+    void write(float value) {
+        pwmout_write(&_pwm, value);
+    }
+
+    /** Return the current output duty-cycle setting, measured as a percentage (float)
+     *
+     *  @returns
+     *    A floating-point value representing the current duty-cycle being output on the pin,
+     *    measured as a percentage. The returned value will lie between
+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
+     *
+     *  @note
+     *  This value may not match exactly the value set by a previous <write>.
+     */
+    float read() {
+        return pwmout_read(&_pwm);
+    }
+
+    /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
+     *
+     *  @note
+     *   The resolution is currently in microseconds; periods smaller than this
+     *   will be set to zero.
+     */
+    void period(float seconds) {
+        pwmout_period(&_pwm, seconds);
+    }
+
+    /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
+     */
+    void period_ms(int ms) {
+        pwmout_period_ms(&_pwm, ms);
+    }
+
+    /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
+     */
+    void period_us(int us) {
+        pwmout_period_us(&_pwm, us);
+    }
+
+    /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
+     */
+    void pulsewidth(float seconds) {
+        pwmout_pulsewidth(&_pwm, seconds);
+    }
+
+    /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
+     */
+    void pulsewidth_ms(int ms) {
+        pwmout_pulsewidth_ms(&_pwm, ms);
+    }
+
+    /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
+     */
+    void pulsewidth_us(int us) {
+        pwmout_pulsewidth_us(&_pwm, us);
+    }
+
+#ifdef MBED_OPERATORS
+    /** A operator shorthand for write()
+     */
+    PwmOut& operator= (float value) {
+        write(value);
+        return *this;
+    }
+
+    PwmOut& operator= (PwmOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** An operator shorthand for read()
+     */
+    operator float() {
+        return read();
+    }
+#endif
+
+protected:
+    pwmout_t _pwm;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/SPI.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/SPI.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,109 +1,109 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPI_H
-#define MBED_SPI_H
-
-#include "platform.h"
-
-#if DEVICE_SPI
-
-#include "spi_api.h"
-
-namespace mbed {
-
-/** A SPI Master, used for communicating with SPI slave devices
- *
- * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
- *
- * Most SPI devices will also require Chip Select and Reset signals. These
- * can be controlled using <DigitalOut> pins
- *
- * Example:
- * @code
- * // Send a byte to a SPI slave, and record the response
- *
- * #include "mbed.h"
- *
- * SPI device(p5, p6, p7); // mosi, miso, sclk
- *
- * int main() {
- *     int response = device.write(0xFF);
- * }
- * @endcode
- */
-class SPI {
-
-public:
-
-    /** Create a SPI master connected to the specified pins
-     *
-     * Pin Options:
-     *  (5, 6, 7) or (11, 12, 13)
-     *
-     *  mosi or miso can be specfied as NC if not used
-     *
-     *  @param mosi SPI Master Out, Slave In pin
-     *  @param miso SPI Master In, Slave Out pin
-     *  @param sclk SPI Clock pin
-     */
-    SPI(PinName mosi, PinName miso, PinName sclk);
-
-    /** Configure the data transmission format
-     *
-     *  @param bits Number of bits per SPI frame (4 - 16)
-     *  @param mode Clock polarity and phase mode (0 - 3)
-     *
-     * @code
-     * mode | POL PHA
-     * -----+--------
-     *   0  |  0   0
-     *   1  |  0   1
-     *   2  |  1   0
-     *   3  |  1   1
-     * @endcode
-     */
-    void format(int bits, int mode = 0);
-
-    /** Set the spi bus clock frequency
-     *
-     *  @param hz SCLK frequency in hz (default = 1MHz)
-     */
-    void frequency(int hz = 1000000);
-
-    /** Write to the SPI Slave and return the response
-     *
-     *  @param value Data to be sent to the SPI slave
-     *
-     *  @returns
-     *    Response from the SPI slave
-    */
-    virtual int write(int value);
-
-protected:
-    spi_t _spi;
-
-    void aquire(void);
-    static SPI *_owner;
-    int _bits;
-    int _mode;
-    int _hz;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_H
+#define MBED_SPI_H
+
+#include "platform.h"
+
+#if DEVICE_SPI
+
+#include "spi_api.h"
+
+namespace mbed {
+
+/** A SPI Master, used for communicating with SPI slave devices
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Most SPI devices will also require Chip Select and Reset signals. These
+ * can be controlled using <DigitalOut> pins
+ *
+ * Example:
+ * @code
+ * // Send a byte to a SPI slave, and record the response
+ *
+ * #include "mbed.h"
+ *
+ * SPI device(p5, p6, p7); // mosi, miso, sclk
+ *
+ * int main() {
+ *     int response = device.write(0xFF);
+ * }
+ * @endcode
+ */
+class SPI {
+
+public:
+
+    /** Create a SPI master connected to the specified pins
+     *
+     * Pin Options:
+     *  (5, 6, 7) or (11, 12, 13)
+     *
+     *  mosi or miso can be specfied as NC if not used
+     *
+     *  @param mosi SPI Master Out, Slave In pin
+     *  @param miso SPI Master In, Slave Out pin
+     *  @param sclk SPI Clock pin
+     */
+    SPI(PinName mosi, PinName miso, PinName sclk);
+
+    /** Configure the data transmission format
+     *
+     *  @param bits Number of bits per SPI frame (4 - 16)
+     *  @param mode Clock polarity and phase mode (0 - 3)
+     *
+     * @code
+     * mode | POL PHA
+     * -----+--------
+     *   0  |  0   0
+     *   1  |  0   1
+     *   2  |  1   0
+     *   3  |  1   1
+     * @endcode
+     */
+    void format(int bits, int mode = 0);
+
+    /** Set the spi bus clock frequency
+     *
+     *  @param hz SCLK frequency in hz (default = 1MHz)
+     */
+    void frequency(int hz = 1000000);
+
+    /** Write to the SPI Slave and return the response
+     *
+     *  @param value Data to be sent to the SPI slave
+     *
+     *  @returns
+     *    Response from the SPI slave
+    */
+    virtual int write(int value);
+
+protected:
+    spi_t _spi;
+
+    void aquire(void);
+    static SPI *_owner;
+    int _bits;
+    int _mode;
+    int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/SPISlave.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/SPISlave.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,126 +1,126 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPISLAVE_H
-#define MBED_SPISLAVE_H
-
-#include "platform.h"
-
-#if DEVICE_SPISLAVE
-
-#include "spi_api.h"
-
-namespace mbed {
-
-/** A SPI slave, used for communicating with a SPI Master device
- *
- * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
- *
- * Example:
- * @code
- * // Reply to a SPI master as slave
- *
- * #include "mbed.h"
- *
- * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
- *
- * int main() {
- *     device.reply(0x00);              // Prime SPI with first reply
- *     while(1) {
- *         if(device.receive()) {
- *             int v = device.read();   // Read byte from master
- *             v = (v + 1) % 0x100;     // Add one to it, modulo 256
- *             device.reply(v);         // Make this the next reply
- *         }
- *     }
- * }
- * @endcode
- */
-class SPISlave {
-
-public:
-
-    /** Create a SPI slave connected to the specified pins
-     *
-     * Pin Options:
-     *  (5, 6, 7i, 8) or (11, 12, 13, 14)
-     *
-     *  mosi or miso can be specfied as NC if not used
-     *
-     *  @param mosi SPI Master Out, Slave In pin
-     *  @param miso SPI Master In, Slave Out pin
-     *  @param sclk SPI Clock pin
-     *  @param ssel SPI chip select pin
-     *  @param name (optional) A string to identify the object
-     */
-    SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
-
-    /** Configure the data transmission format
-     *
-     *  @param bits Number of bits per SPI frame (4 - 16)
-     *  @param mode Clock polarity and phase mode (0 - 3)
-     *
-     * @code
-     * mode | POL PHA
-     * -----+--------
-     *   0  |  0   0
-     *   1  |  0   1
-     *   2  |  1   0
-     *   3  |  1   1
-     * @endcode
-     */
-    void format(int bits, int mode = 0);
-
-    /** Set the spi bus clock frequency
-     *
-     *  @param hz SCLK frequency in hz (default = 1MHz)
-     */
-    void frequency(int hz = 1000000);
-
-    /** Polls the SPI to see if data has been received
-     *
-     *  @returns
-     *    0 if no data,
-     *    1 otherwise
-     */
-    int receive(void);
-
-    /** Retrieve  data from receive buffer as slave
-     *
-     *  @returns
-     *    the data in the receive buffer
-     */
-    int read(void);
-
-    /** Fill the transmission buffer with the value to be written out
-     *  as slave on the next received message from the master.
-     *
-     *  @param value the data to be transmitted next
-     */
-    void reply(int value);
-
-protected:
-    spi_t _spi;
-
-    int _bits;
-    int _mode;
-    int _hz;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPISLAVE_H
+#define MBED_SPISLAVE_H
+
+#include "platform.h"
+
+#if DEVICE_SPISLAVE
+
+#include "spi_api.h"
+
+namespace mbed {
+
+/** A SPI slave, used for communicating with a SPI Master device
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Example:
+ * @code
+ * // Reply to a SPI master as slave
+ *
+ * #include "mbed.h"
+ *
+ * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * int main() {
+ *     device.reply(0x00);              // Prime SPI with first reply
+ *     while(1) {
+ *         if(device.receive()) {
+ *             int v = device.read();   // Read byte from master
+ *             v = (v + 1) % 0x100;     // Add one to it, modulo 256
+ *             device.reply(v);         // Make this the next reply
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class SPISlave {
+
+public:
+
+    /** Create a SPI slave connected to the specified pins
+     *
+     * Pin Options:
+     *  (5, 6, 7i, 8) or (11, 12, 13, 14)
+     *
+     *  mosi or miso can be specfied as NC if not used
+     *
+     *  @param mosi SPI Master Out, Slave In pin
+     *  @param miso SPI Master In, Slave Out pin
+     *  @param sclk SPI Clock pin
+     *  @param ssel SPI chip select pin
+     *  @param name (optional) A string to identify the object
+     */
+    SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+    /** Configure the data transmission format
+     *
+     *  @param bits Number of bits per SPI frame (4 - 16)
+     *  @param mode Clock polarity and phase mode (0 - 3)
+     *
+     * @code
+     * mode | POL PHA
+     * -----+--------
+     *   0  |  0   0
+     *   1  |  0   1
+     *   2  |  1   0
+     *   3  |  1   1
+     * @endcode
+     */
+    void format(int bits, int mode = 0);
+
+    /** Set the spi bus clock frequency
+     *
+     *  @param hz SCLK frequency in hz (default = 1MHz)
+     */
+    void frequency(int hz = 1000000);
+
+    /** Polls the SPI to see if data has been received
+     *
+     *  @returns
+     *    0 if no data,
+     *    1 otherwise
+     */
+    int receive(void);
+
+    /** Retrieve  data from receive buffer as slave
+     *
+     *  @returns
+     *    the data in the receive buffer
+     */
+    int read(void);
+
+    /** Fill the transmission buffer with the value to be written out
+     *  as slave on the next received message from the master.
+     *
+     *  @param value the data to be transmitted next
+     */
+    void reply(int value);
+
+protected:
+    spi_t _spi;
+
+    int _bits;
+    int _mode;
+    int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/Serial.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/Serial.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,138 +1,143 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIAL_H
-#define MBED_SERIAL_H
-
-#include "platform.h"
-
-#if DEVICE_SERIAL
-
-#include "Stream.h"
-#include "FunctionPointer.h"
-#include "serial_api.h"
-
-namespace mbed {
-
-/** A serial port (UART) for communication with other serial devices
- *
- * Can be used for Full Duplex communication, or Simplex by specifying
- * one pin as NC (Not Connected)
- *
- * Example:
- * @code
- * // Print "Hello World" to the PC
- *
- * #include "mbed.h"
- *
- * Serial pc(USBTX, USBRX);
- *
- * int main() {
- *     pc.printf("Hello World\n");
- * }
- * @endcode
- */
-class Serial : public Stream {
-
-public:
-    /** Create a Serial port, connected to the specified transmit and receive pins
-     *
-     *  @param tx Transmit pin
-     *  @param rx Receive pin
-     *
-     *  @note
-     *    Either tx or rx may be specified as NC if unused
-     */
-    Serial(PinName tx, PinName rx, const char *name=NULL);
-
-    /** Set the baud rate of the serial port
-     *
-     *  @param baudrate The baudrate of the serial port (default = 9600).
-     */
-    void baud(int baudrate);
-
-    enum Parity {
-        None = 0,
-        Odd,
-        Even,
-        Forced1,
-        Forced0
-    };
-
-    enum IrqType {
-        RxIrq = 0,
-        TxIrq
-    };
-
-    /** Set the transmission format used by the Serial port
-     *
-     *  @param bits The number of bits in a word (5-8; default = 8)
-     *  @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None)
-     *  @param stop The number of stop bits (1 or 2; default = 1)
-     */
-    void format(int bits = 8, Parity parity=Serial::None, int stop_bits=1);
-
-    /** Determine if there is a character available to read
-     *
-     *  @returns
-     *    1 if there is a character available to read,
-     *    0 otherwise
-     */
-    int readable();
-
-    /** Determine if there is space available to write a character
-     *
-     *  @returns
-     *    1 if there is space to write a character,
-     *    0 otherwise
-     */
-    int writeable();
-
-    /** Attach a function to call whenever a serial interrupt is generated
-     *
-     *  @param fptr A pointer to a void function, or 0 to set as none
-     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
-     */
-    void attach(void (*fptr)(void), IrqType type=RxIrq);
-
-    /** Attach a member function to call whenever a serial interrupt is generated
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
-     */
-    template<typename T>
-    void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
-        if((mptr != NULL) && (tptr != NULL)) {
-            _irq[type].attach(tptr, mptr);
-            serial_irq_set(&_serial, (SerialIrq)type, 1);
-        }
-    }
-
-    static void _irq_handler(uint32_t id, SerialIrq irq_type);
-
-protected:
-    virtual int _getc();
-    virtual int _putc(int c);
-
-    serial_t        _serial;
-    FunctionPointer _irq[2];
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_H
+#define MBED_SERIAL_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "Stream.h"
+#include "FunctionPointer.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A serial port (UART) for communication with other serial devices
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * Example:
+ * @code
+ * // Print "Hello World" to the PC
+ *
+ * #include "mbed.h"
+ *
+ * Serial pc(USBTX, USBRX);
+ *
+ * int main() {
+ *     pc.printf("Hello World\n");
+ * }
+ * @endcode
+ */
+class Serial : public Stream {
+
+public:
+    /** Create a Serial port, connected to the specified transmit and receive pins
+     *
+     *  @param tx Transmit pin
+     *  @param rx Receive pin
+     *
+     *  @note
+     *    Either tx or rx may be specified as NC if unused
+     */
+    Serial(PinName tx, PinName rx, const char *name=NULL);
+
+    /** Set the baud rate of the serial port
+     *
+     *  @param baudrate The baudrate of the serial port (default = 9600).
+     */
+    void baud(int baudrate);
+
+    enum Parity {
+        None = 0,
+        Odd,
+        Even,
+        Forced1,
+        Forced0
+    };
+
+    enum IrqType {
+        RxIrq = 0,
+        TxIrq
+    };
+
+    /** Set the transmission format used by the Serial port
+     *
+     *  @param bits The number of bits in a word (5-8; default = 8)
+     *  @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None)
+     *  @param stop The number of stop bits (1 or 2; default = 1)
+     */
+    void format(int bits = 8, Parity parity=Serial::None, int stop_bits=1);
+
+    /** Determine if there is a character available to read
+     *
+     *  @returns
+     *    1 if there is a character available to read,
+     *    0 otherwise
+     */
+    int readable();
+
+    /** Determine if there is space available to write a character
+     *
+     *  @returns
+     *    1 if there is space to write a character,
+     *    0 otherwise
+     */
+    int writeable();
+
+    /** Attach a function to call whenever a serial interrupt is generated
+     *
+     *  @param fptr A pointer to a void function, or 0 to set as none
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     */
+    void attach(void (*fptr)(void), IrqType type=RxIrq);
+
+    /** Attach a member function to call whenever a serial interrupt is generated
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     */
+    template<typename T>
+    void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+        if((mptr != NULL) && (tptr != NULL)) {
+            _irq[type].attach(tptr, mptr);
+            serial_irq_set(&_serial, (SerialIrq)type, 1);
+        }
+    }
+
+    /** Generate a break condition on the serial line
+     */
+    void send_break();
+
+    static void _irq_handler(uint32_t id, SerialIrq irq_type);
+
+protected:
+    virtual int _getc();
+    virtual int _putc(int c);
+
+    serial_t        _serial;
+    FunctionPointer _irq[2];
+    int             _baud;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- a/api/Stream.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/Stream.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,56 +1,56 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_STREAM_H
-#define MBED_STREAM_H
-
-#include "platform.h"
-#include "FileLike.h"
-
-namespace mbed {
-
-class Stream : public FileLike {
-
-public:
-    Stream(const char *name=NULL);
-    virtual ~Stream();
-
-    int putc(int c);
-    int puts(const char *s);
-    int getc();
-    char *gets(char *s, int size);
-    int printf(const char* format, ...);
-    int scanf(const char* format, ...);
-
-    operator std::FILE*() {return _file;}
-
-protected:
-    virtual int close();
-    virtual ssize_t write(const void* buffer, size_t length);
-    virtual ssize_t read(void* buffer, size_t length);
-    virtual off_t lseek(off_t offset, int whence);
-    virtual int isatty();
-    virtual int fsync();
-    virtual off_t flen();
-
-    virtual int _putc(int c) = 0;
-    virtual int _getc() = 0;
-
-    std::FILE *_file;
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STREAM_H
+#define MBED_STREAM_H
+
+#include "platform.h"
+#include "FileLike.h"
+
+namespace mbed {
+
+class Stream : public FileLike {
+
+public:
+    Stream(const char *name=NULL);
+    virtual ~Stream();
+
+    int putc(int c);
+    int puts(const char *s);
+    int getc();
+    char *gets(char *s, int size);
+    int printf(const char* format, ...);
+    int scanf(const char* format, ...);
+
+    operator std::FILE*() {return _file;}
+
+protected:
+    virtual int close();
+    virtual ssize_t write(const void* buffer, size_t length);
+    virtual ssize_t read(void* buffer, size_t length);
+    virtual off_t lseek(off_t offset, int whence);
+    virtual int isatty();
+    virtual int fsync();
+    virtual off_t flen();
+
+    virtual int _putc(int c) = 0;
+    virtual int _getc() = 0;
+
+    std::FILE *_file;
+};
+
+} // namespace mbed
+
+#endif

--- a/api/Ticker.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/Ticker.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,117 +1,117 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TICKER_H
-#define MBED_TICKER_H
-
-#include "TimerEvent.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-/** A Ticker is used to call a function at a recurring interval
- *
- *  You can use as many seperate Ticker objects as you require.
- *
- * Example:
- * @code
- * // Toggle the blinking led after 5 seconds
- *
- * #include "mbed.h"
- *
- * Ticker timer;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- *
- * int flip = 0;
- *
- * void attime() {
- *     flip = !flip;
- * }
- *
- * int main() {
- *     timer.attach(&attime, 5);
- *     while(1) {
- *         if(flip == 0) {
- *             led1 = !led1;
- *         } else {
- *             led2 = !led2;
- *         }
- *         wait(0.2);
- *     }
- * }
- * @endcode
- */
-class Ticker : public TimerEvent {
-
-public:
-
-    /** Attach a function to be called by the Ticker, specifiying the interval in seconds
-     *
-     *  @param fptr pointer to the function to be called
-     *  @param t the time between calls in seconds
-     */
-    void attach(void (*fptr)(void), float t) {
-        attach_us(fptr, t * 1000000.0f);
-    }
-
-    /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     *  @param t the time between calls in seconds
-     */
-    template<typename T>
-    void attach(T* tptr, void (T::*mptr)(void), float t) {
-        attach_us(tptr, mptr, t * 1000000.0f);
-    }
-
-    /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
-     *
-     *  @param fptr pointer to the function to be called
-     *  @param t the time between calls in micro-seconds
-     */
-    void attach_us(void (*fptr)(void), unsigned int t) {
-        _function.attach(fptr);
-        setup(t);
-    }
-
-    /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     *  @param t the time between calls in micro-seconds
-     */
-    template<typename T>
-    void attach_us(T* tptr, void (T::*mptr)(void), unsigned int t) {
-        _function.attach(tptr, mptr);
-        setup(t);
-    }
-
-    /** Detach the function
-     */
-    void detach();
-
-protected:
-    void setup(unsigned int t);
-    virtual void handler();
-
-    unsigned int _delay;
-    FunctionPointer _function;
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_H
+#define MBED_TICKER_H
+
+#include "TimerEvent.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** A Ticker is used to call a function at a recurring interval
+ *
+ *  You can use as many seperate Ticker objects as you require.
+ *
+ * Example:
+ * @code
+ * // Toggle the blinking led after 5 seconds
+ *
+ * #include "mbed.h"
+ *
+ * Ticker timer;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * int flip = 0;
+ *
+ * void attime() {
+ *     flip = !flip;
+ * }
+ *
+ * int main() {
+ *     timer.attach(&attime, 5);
+ *     while(1) {
+ *         if(flip == 0) {
+ *             led1 = !led1;
+ *         } else {
+ *             led2 = !led2;
+ *         }
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ */
+class Ticker : public TimerEvent {
+
+public:
+
+    /** Attach a function to be called by the Ticker, specifiying the interval in seconds
+     *
+     *  @param fptr pointer to the function to be called
+     *  @param t the time between calls in seconds
+     */
+    void attach(void (*fptr)(void), float t) {
+        attach_us(fptr, t * 1000000.0f);
+    }
+
+    /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *  @param t the time between calls in seconds
+     */
+    template<typename T>
+    void attach(T* tptr, void (T::*mptr)(void), float t) {
+        attach_us(tptr, mptr, t * 1000000.0f);
+    }
+
+    /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
+     *
+     *  @param fptr pointer to the function to be called
+     *  @param t the time between calls in micro-seconds
+     */
+    void attach_us(void (*fptr)(void), unsigned int t) {
+        _function.attach(fptr);
+        setup(t);
+    }
+
+    /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *  @param t the time between calls in micro-seconds
+     */
+    template<typename T>
+    void attach_us(T* tptr, void (T::*mptr)(void), unsigned int t) {
+        _function.attach(tptr, mptr);
+        setup(t);
+    }
+
+    /** Detach the function
+     */
+    void detach();
+
+protected:
+    void setup(unsigned int t);
+    virtual void handler();
+
+    unsigned int _delay;
+    FunctionPointer _function;
+};
+
+} // namespace mbed
+
+#endif

--- a/api/Timeout.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/Timeout.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,59 +1,59 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMEOUT_H
-#define MBED_TIMEOUT_H
-
-#include "Ticker.h"
-
-namespace mbed {
-
-/** A Timeout is used to call a function at a point in the future
- *
- * You can use as many seperate Timeout objects as you require.
- *
- * Example:
- * @code
- * // Blink until timeout.
- *
- * #include "mbed.h"
- *
- * Timeout timeout;
- * DigitalOut led(LED1);
- *
- * int on = 1;
- *
- * void attimeout() {
- *     on = 0;
- * }
- *
- * int main() {
- *     timeout.attach(&attimeout, 5);
- *     while(on) {
- *         led = !led;
- *         wait(0.2);
- *     }
- * }
- * @endcode
- */
-class Timeout : public Ticker {
-
-protected:
-    virtual void handler();
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEOUT_H
+#define MBED_TIMEOUT_H
+
+#include "Ticker.h"
+
+namespace mbed {
+
+/** A Timeout is used to call a function at a point in the future
+ *
+ * You can use as many seperate Timeout objects as you require.
+ *
+ * Example:
+ * @code
+ * // Blink until timeout.
+ *
+ * #include "mbed.h"
+ *
+ * Timeout timeout;
+ * DigitalOut led(LED1);
+ *
+ * int on = 1;
+ *
+ * void attimeout() {
+ *     on = 0;
+ * }
+ *
+ * int main() {
+ *     timeout.attach(&attimeout, 5);
+ *     while(on) {
+ *         led = !led;
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ */
+class Timeout : public Ticker {
+
+protected:
+    virtual void handler();
+};
+
+} // namespace mbed
+
+#endif

--- a/api/Timer.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/Timer.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,88 +1,88 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMER_H
-#define MBED_TIMER_H
-
-#include "platform.h"
-
-namespace mbed {
-
-/** A general purpose timer
- *
- * Example:
- * @code
- * // Count the time to toggle a LED
- *
- * #include "mbed.h"
- *
- * Timer timer;
- * DigitalOut led(LED1);
- * int begin, end;
- *
- * int main() {
- *     timer.start();
- *     begin = timer.read_us();
- *     led = !led;
- *     end = timer.read_us();
- *     printf("Toggle the led takes %d us", end - begin);
- * }
- * @endcode
- */
-class Timer {
-
-public:
-    Timer();
-
-    /** Start the timer
-     */
-    void start();
-
-    /** Stop the timer
-     */
-    void stop();
-
-    /** Reset the timer to 0.
-     *
-     * If it was already counting, it will continue
-     */
-    void reset();
-
-    /** Get the time passed in seconds
-     */
-    float read();
-
-    /** Get the time passed in mili-seconds
-     */
-    int read_ms();
-
-    /** Get the time passed in micro-seconds
-     */
-    int read_us();
-
-#ifdef MBED_OPERATORS
-    operator float();
-#endif
-
-protected:
-    int slicetime();
-    int _running;          // whether the timer is running
-    unsigned int _start;   // the start time of the latest slice
-    int _time;             // any accumulated time from previous slices
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMER_H
+#define MBED_TIMER_H
+
+#include "platform.h"
+
+namespace mbed {
+
+/** A general purpose timer
+ *
+ * Example:
+ * @code
+ * // Count the time to toggle a LED
+ *
+ * #include "mbed.h"
+ *
+ * Timer timer;
+ * DigitalOut led(LED1);
+ * int begin, end;
+ *
+ * int main() {
+ *     timer.start();
+ *     begin = timer.read_us();
+ *     led = !led;
+ *     end = timer.read_us();
+ *     printf("Toggle the led takes %d us", end - begin);
+ * }
+ * @endcode
+ */
+class Timer {
+
+public:
+    Timer();
+
+    /** Start the timer
+     */
+    void start();
+
+    /** Stop the timer
+     */
+    void stop();
+
+    /** Reset the timer to 0.
+     *
+     * If it was already counting, it will continue
+     */
+    void reset();
+
+    /** Get the time passed in seconds
+     */
+    float read();
+
+    /** Get the time passed in mili-seconds
+     */
+    int read_ms();
+
+    /** Get the time passed in micro-seconds
+     */
+    int read_us();
+
+#ifdef MBED_OPERATORS
+    operator float();
+#endif
+
+protected:
+    int slicetime();
+    int _running;          // whether the timer is running
+    unsigned int _start;   // the start time of the latest slice
+    int _time;             // any accumulated time from previous slices
+};
+
+} // namespace mbed
+
+#endif

--- a/api/TimerEvent.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/TimerEvent.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,52 +1,52 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMEREVENT_H
-#define MBED_TIMEREVENT_H
-
-#include "us_ticker_api.h"
-
-namespace mbed {
-
-/** Base abstraction for timer interrupts
-*/
-class TimerEvent {
-public:
-    TimerEvent();
-
-    /** The handler registered with the underlying timer interrupt
-     */
-    static void irq(uint32_t id);
-
-    /** Destruction removes it...
-     */
-    virtual ~TimerEvent();
-
-protected:
-    // The handler called to service the timer event of the derived class
-    virtual void handler() = 0;
-
-    // insert in to linked list
-    void insert(unsigned int timestamp);
-
-    // remove from linked list, if in it
-    void remove();
-
-    ticker_event_t event;
-};
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEREVENT_H
+#define MBED_TIMEREVENT_H
+
+#include "us_ticker_api.h"
+
+namespace mbed {
+
+/** Base abstraction for timer interrupts
+*/
+class TimerEvent {
+public:
+    TimerEvent();
+
+    /** The handler registered with the underlying timer interrupt
+     */
+    static void irq(uint32_t id);
+
+    /** Destruction removes it...
+     */
+    virtual ~TimerEvent();
+
+protected:
+    // The handler called to service the timer event of the derived class
+    virtual void handler() = 0;
+
+    // insert in to linked list
+    void insert(unsigned int timestamp);
+
+    // remove from linked list, if in it
+    void remove();
+
+    ticker_event_t event;
+};
+
+} // namespace mbed
+
+#endif

--- a/api/can_helper.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/can_helper.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,52 +1,52 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_HELPER_H
-#define MBED_CAN_HELPER_H
-
-#if DEVICE_CAN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-enum CANFormat {
-    CANStandard = 0,
-    CANExtended = 1
-};
-typedef enum CANFormat CANFormat;
-
-enum CANType {
-    CANData   = 0,
-    CANRemote = 1
-};
-typedef enum CANType CANType;
-
-struct CAN_Message {
-    unsigned int   id;                 // 29 bit identifier
-    unsigned char  data[8];            // Data field
-    unsigned char  len;                // Length of data field in bytes
-    CANFormat      format;             // 0 - STANDARD, 1- EXTENDED IDENTIFIER
-    CANType        type;               // 0 - DATA FRAME, 1 - REMOTE FRAME
-};
-typedef struct CAN_Message CAN_Message;
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif
-
-#endif // MBED_CAN_HELPER_H
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_HELPER_H
+#define MBED_CAN_HELPER_H
+
+#if DEVICE_CAN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum CANFormat {
+    CANStandard = 0,
+    CANExtended = 1
+};
+typedef enum CANFormat CANFormat;
+
+enum CANType {
+    CANData   = 0,
+    CANRemote = 1
+};
+typedef enum CANType CANType;
+
+struct CAN_Message {
+    unsigned int   id;                 // 29 bit identifier
+    unsigned char  data[8];            // Data field
+    unsigned char  len;                // Length of data field in bytes
+    CANFormat      format;             // 0 - STANDARD, 1- EXTENDED IDENTIFIER
+    CANType        type;               // 0 - DATA FRAME, 1 - REMOTE FRAME
+};
+typedef struct CAN_Message CAN_Message;
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+
+#endif // MBED_CAN_HELPER_H

--- a/api/error.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/error.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,66 +1,66 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ERROR_H
-#define MBED_ERROR_H
-
-/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
- *
- * @code
- * #error "That shouldn't have happened!"
- * @endcode
- *
- * If the compiler evaluates this line, it will report the error and stop the compile.
- *
- * For example, you could use this to check some user-defined compile-time variables:
- *
- * @code
- * #define NUM_PORTS 7
- * #if (NUM_PORTS > 4)
- *     #error "NUM_PORTS must be less than 4"
- * #endif
- * @endcode
- *
- * Reporting Run-Time Errors:
- * To generate a fatal run-time error, you can use the mbed error() function.
- *
- * @code
- * error("That shouldn't have happened!");
- * @endcode
- *
- * If the mbed running the program executes this function, it will print the
- * message via the USB serial port, and then die with the blue lights of death!
- *
- * The message can use printf-style formatting, so you can report variables in the
- * message too. For example, you could use this to check a run-time condition:
- *
- * @code
- * if(x >= 5) {
- *     error("expected x to be less than 5, but got %d", x);
- * }
- * #endcode
- */
-
-#include <stdlib.h>
-#include "device.h"
-
-#ifdef DEVICE_STDIO_MESSAGES
-    #include <stdio.h>
-    #define error(...) (fprintf(stderr, __VA_ARGS__), exit(1))
-#else
-    #define error(...) (exit(1))
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ERROR_H
+#define MBED_ERROR_H
+
+/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
+ *
+ * @code
+ * #error "That shouldn't have happened!"
+ * @endcode
+ *
+ * If the compiler evaluates this line, it will report the error and stop the compile.
+ *
+ * For example, you could use this to check some user-defined compile-time variables:
+ *
+ * @code
+ * #define NUM_PORTS 7
+ * #if (NUM_PORTS > 4)
+ *     #error "NUM_PORTS must be less than 4"
+ * #endif
+ * @endcode
+ *
+ * Reporting Run-Time Errors:
+ * To generate a fatal run-time error, you can use the mbed error() function.
+ *
+ * @code
+ * error("That shouldn't have happened!");
+ * @endcode
+ *
+ * If the mbed running the program executes this function, it will print the
+ * message via the USB serial port, and then die with the blue lights of death!
+ *
+ * The message can use printf-style formatting, so you can report variables in the
+ * message too. For example, you could use this to check a run-time condition:
+ *
+ * @code
+ * if(x >= 5) {
+ *     error("expected x to be less than 5, but got %d", x);
+ * }
+ * #endcode
+ */
+
+#include <stdlib.h>
+#include "device.h"
+
+#ifdef DEVICE_STDIO_MESSAGES
+    #include <stdio.h>
+    #define error(...) (fprintf(stderr, __VA_ARGS__), exit(1))
+#else
+    #define error(...) (exit(1))
+#endif
+
+#endif

--- a/api/mbed.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/mbed.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,65 +1,65 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_H
-#define MBED_H
-
-#define MBED_LIBRARY_VERSION 30
-
-#include "platform.h"
-
-// Useful C libraries
-#include <math.h>
-#include <time.h>
-
-// mbed Debug libraries
-#include "error.h"
-#include "mbed_interface.h"
-
-// mbed Peripheral components
-#include "DigitalIn.h"
-#include "DigitalOut.h"
-#include "DigitalInOut.h"
-#include "BusIn.h"
-#include "BusOut.h"
-#include "BusInOut.h"
-#include "PortIn.h"
-#include "PortInOut.h"
-#include "PortOut.h"
-#include "AnalogIn.h"
-#include "AnalogOut.h"
-#include "PwmOut.h"
-#include "Serial.h"
-#include "SPI.h"
-#include "SPISlave.h"
-#include "I2C.h"
-#include "I2CSlave.h"
-#include "Ethernet.h"
-#include "CAN.h"
-
-// mbed Internal components
-#include "Timer.h"
-#include "Ticker.h"
-#include "Timeout.h"
-#include "LocalFileSystem.h"
-#include "InterruptIn.h"
-#include "wait_api.h"
-#include "sleep_api.h"
-#include "rtc_time.h"
-
-using namespace mbed;
-using namespace std;
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_H
+#define MBED_H
+
+#define MBED_LIBRARY_VERSION 30
+
+#include "platform.h"
+
+// Useful C libraries
+#include <math.h>
+#include <time.h>
+
+// mbed Debug libraries
+#include "error.h"
+#include "mbed_interface.h"
+
+// mbed Peripheral components
+#include "DigitalIn.h"
+#include "DigitalOut.h"
+#include "DigitalInOut.h"
+#include "BusIn.h"
+#include "BusOut.h"
+#include "BusInOut.h"
+#include "PortIn.h"
+#include "PortInOut.h"
+#include "PortOut.h"
+#include "AnalogIn.h"
+#include "AnalogOut.h"
+#include "PwmOut.h"
+#include "Serial.h"
+#include "SPI.h"
+#include "SPISlave.h"
+#include "I2C.h"
+#include "I2CSlave.h"
+#include "Ethernet.h"
+#include "CAN.h"
+
+// mbed Internal components
+#include "Timer.h"
+#include "Ticker.h"
+#include "Timeout.h"
+#include "LocalFileSystem.h"
+#include "InterruptIn.h"
+#include "wait_api.h"
+#include "sleep_api.h"
+#include "rtc_time.h"
+
+using namespace mbed;
+using namespace std;
+
+#endif

--- a/api/mbed_debug.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/mbed_debug.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,66 +1,66 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEBUG_H
-#define MBED_DEBUG_H
-#include "device.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef DEVICE_STDIO_MESSAGES
-#include <stdio.h>
-#include <stdarg.h>
-
-/** Output a debug message
- *
- * @param format printf-style format string, followed by variables
- */
-static inline void debug(const char *format, ...) {
-    va_list args;
-    va_start(args, format);
-    vfprintf(stderr, format, args);
-    va_end(args);
-}
-
-/** Conditionally output a debug message
- *
- * NOTE: If the condition is constant false (!= 1) and the compiler optimization
- * level is greater than 0, then the whole function will be compiled away.
- *
- * @param condition output only if condition is true (== 1)
- * @param format printf-style format string, followed by variables
- */
-static inline void debug_if(int condition, const char *format, ...) {
-    if (condition == 1) {
-        va_list args;
-        va_start(args, format);
-        vfprintf(stderr, format, args);
-        va_end(args);
-    }
-}
-
-#else
-static inline void debug(const char *format, ...) {}
-static inline void debug_if(int condition, const char *format, ...) {}
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEBUG_H
+#define MBED_DEBUG_H
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#include <stdarg.h>
+
+/** Output a debug message
+ *
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug(const char *format, ...) {
+    va_list args;
+    va_start(args, format);
+    vfprintf(stderr, format, args);
+    va_end(args);
+}
+
+/** Conditionally output a debug message
+ *
+ * NOTE: If the condition is constant false (!= 1) and the compiler optimization
+ * level is greater than 0, then the whole function will be compiled away.
+ *
+ * @param condition output only if condition is true (== 1)
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug_if(int condition, const char *format, ...) {
+    if (condition == 1) {
+        va_list args;
+        va_start(args, format);
+        vfprintf(stderr, format, args);
+        va_end(args);
+    }
+}
+
+#else
+static inline void debug(const char *format, ...) {}
+static inline void debug_if(int condition, const char *format, ...) {}
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/api/mbed_interface.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/mbed_interface.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,101 +1,101 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_INTERFACE_H
-#define MBED_INTERFACE_H
-
-#include "device.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_SEMIHOST
-
-/** Functions to control the mbed interface
- *
- * mbed Microcontrollers have a built-in interface to provide functionality such as
- * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
- * system. These functions provide means to control the interface suing semihost
- * calls it supports.
- */
-
-/** Determine whether the mbed interface is connected, based on whether debug is enabled
- *
- *  @returns
- *    1 if interface is connected,
- *    0 otherwise
- */
-int mbed_interface_connected(void);
-
-/** Instruct the mbed interface to reset, as if the reset button had been pressed
- *
- *  @returns
- *    1 if successful,
- *    0 otherwise (e.g. interface not present)
- */
-int mbed_interface_reset(void);
-
-/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
- * The interface will still support the USB serial aspect
- *
- *  @returns
- *    0 if successful,
- *   -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_disconnect(void);
-
-/** This will disconnect the debug aspect of the interface, and if the USB cable is not
- * connected, also power down the interface. If the USB cable is connected, the interface
- * will remain powered up and visible to the host
- *
- *  @returns
- *    0 if successful,
- *   -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_powerdown(void);
-
-/** This returns a string containing the 32-character UID of the mbed interface
- *  This is a weak function that can be overwritten if required
- *
- *  @param uid A 33-byte array to write the null terminated 32-byte string
- *
- *  @returns
- *    0 if successful,
- *   -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_uid(char *uid);
-
-#endif
-
-/** This returns a unique 6-byte MAC address, based on the interface UID
- * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
- *
- * This is a weak function that can be overwritten if you want to provide your own mechanism to
- * provide a MAC address.
- *
- *  @param mac A 6-byte array to write the MAC address
- */
-void mbed_mac_address(char *mac);
-
-/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
- */
-void mbed_die(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERFACE_H
+#define MBED_INTERFACE_H
+
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+/** Functions to control the mbed interface
+ *
+ * mbed Microcontrollers have a built-in interface to provide functionality such as
+ * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
+ * system. These functions provide means to control the interface suing semihost
+ * calls it supports.
+ */
+
+/** Determine whether the mbed interface is connected, based on whether debug is enabled
+ *
+ *  @returns
+ *    1 if interface is connected,
+ *    0 otherwise
+ */
+int mbed_interface_connected(void);
+
+/** Instruct the mbed interface to reset, as if the reset button had been pressed
+ *
+ *  @returns
+ *    1 if successful,
+ *    0 otherwise (e.g. interface not present)
+ */
+int mbed_interface_reset(void);
+
+/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
+ * The interface will still support the USB serial aspect
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_disconnect(void);
+
+/** This will disconnect the debug aspect of the interface, and if the USB cable is not
+ * connected, also power down the interface. If the USB cable is connected, the interface
+ * will remain powered up and visible to the host
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_powerdown(void);
+
+/** This returns a string containing the 32-character UID of the mbed interface
+ *  This is a weak function that can be overwritten if required
+ *
+ *  @param uid A 33-byte array to write the null terminated 32-byte string
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_uid(char *uid);
+
+#endif
+
+/** This returns a unique 6-byte MAC address, based on the interface UID
+ * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
+ *
+ * This is a weak function that can be overwritten if you want to provide your own mechanism to
+ * provide a MAC address.
+ *
+ *  @param mac A 6-byte array to write the MAC address
+ */
+void mbed_mac_address(char *mac);
+
+/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
+ */
+void mbed_die(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/api/platform.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/platform.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,30 +1,30 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PLATFORM_H
-#define MBED_PLATFORM_H
-
-#define MBED_OPERATORS    1
-
-#include "device.h"
-#include "PinNames.h"
-#include "PeripheralNames.h"
-
-#include <cstddef>
-#include <cstdlib>
-#include <cstdio>
-#include <cstring>
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PLATFORM_H
+#define MBED_PLATFORM_H
+
+#define MBED_OPERATORS    1
+
+#include "device.h"
+#include "PinNames.h"
+#include "PeripheralNames.h"
+
+#include <cstddef>
+#include <cstdlib>
+#include <cstdio>
+#include <cstring>
+
+#endif

--- a/api/rtc_time.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/rtc_time.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,74 +1,74 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <time.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Implementation of the C time.h functions
- *
- * Provides mechanisms to set and read the current time, based
- * on the microcontroller Real-Time Clock (RTC), plus some
- * standard C manipulation and formating functions.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * int main() {
- *     set_time(1256729737);  // Set RTC time to Wed, 28 Oct 2009 11:35:37
- *
- *     while(1) {
- *         time_t seconds = time(NULL);
- *
- *         printf("Time as seconds since January 1, 1970 = %d\n", seconds);
- *
- *         printf("Time as a basic string = %s", ctime(&seconds));
- *
- *         char buffer[32];
- *         strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
- *         printf("Time as a custom formatted string = %s", buffer);
- *
- *         wait(1);
- *     }
- * }
- * @endcode
- */
-
-/** Set the current time
- *
- * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
- * to the time represented by the number of seconds since January 1, 1970
- * (the UNIX timestamp).
- *
- * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * int main() {
- *     set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
- * }
- * @endcode
- */
-void set_time(time_t t);
-
-#ifdef __cplusplus
-}
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Implementation of the C time.h functions
+ *
+ * Provides mechanisms to set and read the current time, based
+ * on the microcontroller Real-Time Clock (RTC), plus some
+ * standard C manipulation and formating functions.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ *     set_time(1256729737);  // Set RTC time to Wed, 28 Oct 2009 11:35:37
+ *
+ *     while(1) {
+ *         time_t seconds = time(NULL);
+ *
+ *         printf("Time as seconds since January 1, 1970 = %d\n", seconds);
+ *
+ *         printf("Time as a basic string = %s", ctime(&seconds));
+ *
+ *         char buffer[32];
+ *         strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
+ *         printf("Time as a custom formatted string = %s", buffer);
+ *
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ */
+
+/** Set the current time
+ *
+ * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
+ * to the time represented by the number of seconds since January 1, 1970
+ * (the UNIX timestamp).
+ *
+ * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ *     set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
+ * }
+ * @endcode
+ */
+void set_time(time_t t);
+
+#ifdef __cplusplus
+}
+#endif

--- a/api/semihost_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/semihost_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,93 +1,93 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SEMIHOST_H
-#define MBED_SEMIHOST_H
-
-#include "device.h"
-#include "toolchain.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_SEMIHOST
-
-#ifndef __CC_ARM
-
-#if defined(__ICCARM__)
-inline int __semihost(int reason, const void *arg) {
-    return __semihosting(reason, (void*)arg);
-}
-#else
-
-#ifdef __thumb__
-#   define AngelSWI            0xAB
-#   define AngelSWIInsn        "bkpt"
-#   define AngelSWIAsm          bkpt
-#else
-#   define AngelSWI            0x123456
-#   define AngelSWIInsn        "swi"
-#   define AngelSWIAsm          swi
-#endif
-
-static inline int __semihost(int reason, const void *arg) {
-    int value;
-
-    asm volatile (
-       "mov r0, %1"          "\n\t"
-       "mov r1, %2"          "\n\t"
-       AngelSWIInsn " %a3"   "\n\t"
-       "mov %0, r0"
-       : "=r" (value)                                         /* output operands             */
-       : "r" (reason), "r" (arg), "i" (AngelSWI)              /* input operands              */
-       : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"   /* list of clobbered registers */
-    );
-
-    return value;
-}
-#endif
-#endif
-
-#if DEVICE_LOCALFILESYSTEM
-FILEHANDLE semihost_open(const char* name, int openmode);
-int semihost_close (FILEHANDLE fh);
-int semihost_read  (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode);
-int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode);
-int semihost_ensure(FILEHANDLE fh);
-long semihost_flen (FILEHANDLE fh);
-int semihost_seek  (FILEHANDLE fh, long position);
-int semihost_istty (FILEHANDLE fh);
-
-int semihost_remove(const char *name);
-int semihost_rename(const char *old_name, const char *new_name);
-#endif
-
-int semihost_uid(char *uid);
-int semihost_reset(void);
-int semihost_vbus(void);
-int semihost_powerdown(void);
-int semihost_exit(void);
-
-int semihost_connected(void);
-int semihost_disabledebug(void);
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SEMIHOST_H
+#define MBED_SEMIHOST_H
+
+#include "device.h"
+#include "toolchain.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+#ifndef __CC_ARM
+
+#if defined(__ICCARM__)
+inline int __semihost(int reason, const void *arg) {
+    return __semihosting(reason, (void*)arg);
+}
+#else
+
+#ifdef __thumb__
+#   define AngelSWI            0xAB
+#   define AngelSWIInsn        "bkpt"
+#   define AngelSWIAsm          bkpt
+#else
+#   define AngelSWI            0x123456
+#   define AngelSWIInsn        "swi"
+#   define AngelSWIAsm          swi
+#endif
+
+static inline int __semihost(int reason, const void *arg) {
+    int value;
+
+    asm volatile (
+       "mov r0, %1"          "\n\t"
+       "mov r1, %2"          "\n\t"
+       AngelSWIInsn " %a3"   "\n\t"
+       "mov %0, r0"
+       : "=r" (value)                                         /* output operands             */
+       : "r" (reason), "r" (arg), "i" (AngelSWI)              /* input operands              */
+       : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"   /* list of clobbered registers */
+    );
+
+    return value;
+}
+#endif
+#endif
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode);
+int semihost_close (FILEHANDLE fh);
+int semihost_read  (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode);
+int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode);
+int semihost_ensure(FILEHANDLE fh);
+long semihost_flen (FILEHANDLE fh);
+int semihost_seek  (FILEHANDLE fh, long position);
+int semihost_istty (FILEHANDLE fh);
+
+int semihost_remove(const char *name);
+int semihost_rename(const char *old_name, const char *new_name);
+#endif
+
+int semihost_uid(char *uid);
+int semihost_reset(void);
+int semihost_vbus(void);
+int semihost_powerdown(void);
+int semihost_exit(void);
+
+int semihost_connected(void);
+int semihost_disabledebug(void);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/api/toolchain.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/toolchain.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,35 +1,35 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TOOLCHAIN_H
-#define MBED_TOOLCHAIN_H
-
-#if defined(TOOLCHAIN_ARM) || defined(TOOLCHAIN_uARM)
-#include <rt_sys.h>
-#endif
-
-#ifndef FILEHANDLE
-typedef int FILEHANDLE;
-#endif
-
-#if defined (__ICCARM__)
-#   define WEAK     __weak
-#   define PACKED   __packed
-#else
-#   define WEAK     __attribute__((weak))
-#   define PACKED   __attribute__((packed))
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TOOLCHAIN_H
+#define MBED_TOOLCHAIN_H
+
+#if defined(TOOLCHAIN_ARM)
+#include <rt_sys.h>
+#endif
+
+#ifndef FILEHANDLE
+typedef int FILEHANDLE;
+#endif
+
+#if defined (__ICCARM__)
+#   define WEAK     __weak
+#   define PACKED   __packed
+#else
+#   define WEAK     __attribute__((weak))
+#   define PACKED   __attribute__((packed))
+#endif
+
+#endif

--- a/api/wait_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/api/wait_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,66 +1,66 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_WAIT_API_H
-#define MBED_WAIT_API_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Generic wait functions.
- *
- * These provide simple NOP type wait capabilities.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * DigitalOut heartbeat(LED1);
- *
- * int main() {
- *     while (1) {
- *         heartbeat = 1;
- *         wait(0.5);
- *         heartbeat = 0;
- *         wait(0.5);
- *     }
- * }
- */
-
-/** Waits for a number of seconds, with microsecond resolution (within
- *  the accuracy of single precision floating point).
- *
- *  @param s number of seconds to wait
- */
-void wait(float s);
-
-/** Waits a number of milliseconds.
- *
- *  @param ms the whole number of milliseconds to wait
- */
-void wait_ms(int ms);
-
-/** Waits a number of microseconds.
- *
- *  @param us the whole number of microseconds to wait
- */
-void wait_us(int us);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_WAIT_API_H
+#define MBED_WAIT_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Generic wait functions.
+ *
+ * These provide simple NOP type wait capabilities.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * DigitalOut heartbeat(LED1);
+ *
+ * int main() {
+ *     while (1) {
+ *         heartbeat = 1;
+ *         wait(0.5);
+ *         heartbeat = 0;
+ *         wait(0.5);
+ *     }
+ * }
+ */
+
+/** Waits for a number of seconds, with microsecond resolution (within
+ *  the accuracy of single precision floating point).
+ *
+ *  @param s number of seconds to wait
+ */
+void wait(float s);
+
+/** Waits a number of milliseconds.
+ *
+ *  @param ms the whole number of milliseconds to wait
+ */
+void wait_ms(int ms);
+
+/** Waits a number of microseconds.
+ *
+ *  @param us the whole number of microseconds to wait
+ */
+void wait_us(int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/common/BusIn.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/BusIn.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,58 +1,58 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "BusIn.h"
-
-namespace mbed {
-
-BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
-    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
-
-    for (int i=0; i<16; i++) {
-        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
-    }
-}
-
-BusIn::BusIn(PinName pins[16]) {
-    for (int i=0; i<16; i++) {
-        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
-    }
-}
-
-BusIn::~BusIn() {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            delete _pin[i];
-        }
-    }
-}
-
-int BusIn::read() {
-    int v = 0;
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            v |= _pin[i]->read() << i;
-        }
-    }
-    return v;
-}
-
-#ifdef MBED_OPERATORS
-BusIn::operator int() {
-    return read();
-}
-#endif
-
-} // namespace mbed
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusIn.h"
+
+namespace mbed {
+
+BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+    }
+}
+
+BusIn::BusIn(PinName pins[16]) {
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+    }
+}
+
+BusIn::~BusIn() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+int BusIn::read() {
+    int v = 0;
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    return v;
+}
+
+#ifdef MBED_OPERATORS
+BusIn::operator int() {
+    return read();
+}
+#endif
+
+} // namespace mbed

--- a/common/BusInOut.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/BusInOut.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,100 +1,100 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "BusInOut.h"
-
-namespace mbed {
-
-BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
-    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
-
-    for (int i=0; i<16; i++) {
-        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
-    }
-}
-
-BusInOut::BusInOut(PinName pins[16]) {
-    for (int i=0; i<16; i++) {
-        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
-    }
-}
-
-BusInOut::~BusInOut() {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            delete _pin[i];
-        }
-    }
-}
-
-void BusInOut::write(int value) {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            _pin[i]->write((value >> i) & 1);
-        }
-    }
-}
-
-int BusInOut::read() {
-    int v = 0;
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            v |= _pin[i]->read() << i;
-        }
-    }
-    return v;
-}
-
-void BusInOut::output() {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            _pin[i]->output();
-        }
-    }
-}
-
-void BusInOut::input() {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            _pin[i]->input();
-        }
-    }
-}
-
-void BusInOut::mode(PinMode pull) {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            _pin[i]->mode(pull);
-        }
-    }
-}
-
-#ifdef MBED_OPERATORS
-BusInOut& BusInOut::operator= (int v) {
-    write(v);
-    return *this;
-}
-
-BusInOut& BusInOut::operator= (BusInOut& rhs) {
-    write(rhs.read());
-    return *this;
-}
-
-BusInOut::operator int() {
-    return read();
-}
-#endif
-
-} // namespace mbed
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusInOut.h"
+
+namespace mbed {
+
+BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+    }
+}
+
+BusInOut::BusInOut(PinName pins[16]) {
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+    }
+}
+
+BusInOut::~BusInOut() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+void BusInOut::write(int value) {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->write((value >> i) & 1);
+        }
+    }
+}
+
+int BusInOut::read() {
+    int v = 0;
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    return v;
+}
+
+void BusInOut::output() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->output();
+        }
+    }
+}
+
+void BusInOut::input() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->input();
+        }
+    }
+}
+
+void BusInOut::mode(PinMode pull) {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->mode(pull);
+        }
+    }
+}
+
+#ifdef MBED_OPERATORS
+BusInOut& BusInOut::operator= (int v) {
+    write(v);
+    return *this;
+}
+
+BusInOut& BusInOut::operator= (BusInOut& rhs) {
+    write(rhs.read());
+    return *this;
+}
+
+BusInOut::operator int() {
+    return read();
+}
+#endif
+
+} // namespace mbed

--- a/common/BusOut.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/BusOut.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,76 +1,76 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "BusOut.h"
-
-namespace mbed {
-
-BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
-    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
-
-    for (int i=0; i<16; i++) {
-        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
-    }
-}
-
-BusOut::BusOut(PinName pins[16]) {
-    for (int i=0; i<16; i++) {
-        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
-    }
-}
-
-BusOut::~BusOut() {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            delete _pin[i];
-        }
-    }
-}
-
-void BusOut::write(int value) {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            _pin[i]->write((value >> i) & 1);
-        }
-    }
-}
-
-int BusOut::read() {
-    int v = 0;
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            v |= _pin[i]->read() << i;
-        }
-    }
-    return v;
-}
-
-#ifdef MBED_OPERATORS
-BusOut& BusOut::operator= (int v) {
-    write(v);
-    return *this;
-}
-
-BusOut& BusOut::operator= (BusOut& rhs) {
-    write(rhs.read());
-    return *this;
-}
-
-BusOut::operator int() {
-    return read();
-}
-#endif
-
-} // namespace mbed
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusOut.h"
+
+namespace mbed {
+
+BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+    }
+}
+
+BusOut::BusOut(PinName pins[16]) {
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+    }
+}
+
+BusOut::~BusOut() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+void BusOut::write(int value) {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->write((value >> i) & 1);
+        }
+    }
+}
+
+int BusOut::read() {
+    int v = 0;
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    return v;
+}
+
+#ifdef MBED_OPERATORS
+BusOut& BusOut::operator= (int v) {
+    write(v);
+    return *this;
+}
+
+BusOut& BusOut::operator= (BusOut& rhs) {
+    write(rhs.read());
+    return *this;
+}
+
+BusOut::operator int() {
+    return read();
+}
+#endif
+
+} // namespace mbed

--- a/common/CAN.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/CAN.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,119 +1,119 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "CAN.h"
-
-#if DEVICE_CAN
-
-#include "cmsis.h"
-
-namespace mbed {
-
-CAN::CAN(PinName rd, PinName td) {
-    can_init(&_can, rd, td);
-}
-
-CAN::~CAN() {
-    can_free(&_can);
-}
-
-int CAN::frequency(int f) {
-    return can_frequency(&_can, f);
-}
-
-int CAN::write(CANMessage msg) {
-    return can_write(&_can, msg, 0);
-}
-
-int CAN::read(CANMessage &msg) {
-    return can_read(&_can, &msg);
-}
-
-void CAN::reset() {
-    can_reset(&_can);
-}
-
-unsigned char CAN::rderror() {
-    return can_rderror(&_can);
-}
-
-unsigned char CAN::tderror() {
-    return can_tderror(&_can);
-}
-
-void CAN::monitor(bool silent) {
-    can_monitor(&_can, (silent) ? 1 : 0);
-}
-
-static FunctionPointer* can_obj[2] = { NULL };
-
-// Have to check that the CAN block is active before reading the Interrupt
-// Control Register, or the mbed hangs
-void can_irq(void) {
-    uint32_t icr;
-
-    if(LPC_SC->PCONP & (1 << 13)) {
-        icr = LPC_CAN1->ICR;
-
-        if(icr && (can_obj[0] != NULL)) {
-            can_obj[0]->call();
-        }
-    }
-
-    if(LPC_SC->PCONP & (1 << 14)) {
-        icr = LPC_CAN2->ICR;
-        if(icr && (can_obj[1] != NULL)) {
-            can_obj[1]->call();
-        }
-    }
-
-}
-
-void CAN::setup_interrupt(void) {
-    switch ((int)_can.dev) {
-        case CAN_1: can_obj[0] = &_rxirq; break;
-        case CAN_2: can_obj[1] = &_rxirq; break;
-    }
-    _can.dev->MOD |= 1;
-    _can.dev->IER |= 1;
-    _can.dev->MOD &= ~1;
-    NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq);
-    NVIC_EnableIRQ(CAN_IRQn);
-}
-
-void CAN::remove_interrupt(void) {
-    switch ((int)_can.dev) {
-        case CAN_1: can_obj[0] = NULL; break;
-        case CAN_2: can_obj[1] = NULL; break;
-    }
-
-    _can.dev->IER &= ~(1);
-    if ((can_obj[0] == NULL) && (can_obj[1] == NULL)) {
-        NVIC_DisableIRQ(CAN_IRQn);
-    }
-}
-
-void CAN::attach(void (*fptr)(void)) {
-    if (fptr != NULL) {
-        _rxirq.attach(fptr);
-        setup_interrupt();
-    } else {
-        remove_interrupt();
-    }
-}
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "CAN.h"
+
+#if DEVICE_CAN
+
+#include "cmsis.h"
+
+namespace mbed {
+
+CAN::CAN(PinName rd, PinName td) {
+    can_init(&_can, rd, td);
+}
+
+CAN::~CAN() {
+    can_free(&_can);
+}
+
+int CAN::frequency(int f) {
+    return can_frequency(&_can, f);
+}
+
+int CAN::write(CANMessage msg) {
+    return can_write(&_can, msg, 0);
+}
+
+int CAN::read(CANMessage &msg) {
+    return can_read(&_can, &msg);
+}
+
+void CAN::reset() {
+    can_reset(&_can);
+}
+
+unsigned char CAN::rderror() {
+    return can_rderror(&_can);
+}
+
+unsigned char CAN::tderror() {
+    return can_tderror(&_can);
+}
+
+void CAN::monitor(bool silent) {
+    can_monitor(&_can, (silent) ? 1 : 0);
+}
+
+static FunctionPointer* can_obj[2] = { NULL };
+
+// Have to check that the CAN block is active before reading the Interrupt
+// Control Register, or the mbed hangs
+void can_irq(void) {
+    uint32_t icr;
+
+    if(LPC_SC->PCONP & (1 << 13)) {
+        icr = LPC_CAN1->ICR;
+
+        if(icr && (can_obj[0] != NULL)) {
+            can_obj[0]->call();
+        }
+    }
+
+    if(LPC_SC->PCONP & (1 << 14)) {
+        icr = LPC_CAN2->ICR;
+        if(icr && (can_obj[1] != NULL)) {
+            can_obj[1]->call();
+        }
+    }
+
+}
+
+void CAN::setup_interrupt(void) {
+    switch ((int)_can.dev) {
+        case CAN_1: can_obj[0] = &_rxirq; break;
+        case CAN_2: can_obj[1] = &_rxirq; break;
+    }
+    _can.dev->MOD |= 1;
+    _can.dev->IER |= 1;
+    _can.dev->MOD &= ~1;
+    NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq);
+    NVIC_EnableIRQ(CAN_IRQn);
+}
+
+void CAN::remove_interrupt(void) {
+    switch ((int)_can.dev) {
+        case CAN_1: can_obj[0] = NULL; break;
+        case CAN_2: can_obj[1] = NULL; break;
+    }
+
+    _can.dev->IER &= ~(1);
+    if ((can_obj[0] == NULL) && (can_obj[1] == NULL)) {
+        NVIC_DisableIRQ(CAN_IRQn);
+    }
+}
+
+void CAN::attach(void (*fptr)(void)) {
+    if (fptr != NULL) {
+        _rxirq.attach(fptr);
+        setup_interrupt();
+    } else {
+        remove_interrupt();
+    }
+}
+
+} // namespace mbed
+
+#endif

--- a/common/Ethernet.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/Ethernet.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,73 +1,73 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Ethernet.h"
-
-#if DEVICE_ETHERNET
-
-#include "ethernet_api.h"
-
-namespace mbed {
-
-Ethernet::Ethernet() {
-    ethernet_init();
-}
-
-Ethernet::~Ethernet() {
-    ethernet_free();
-}
-
-int Ethernet::write(const char *data, int size) {
-    return ethernet_write(data, size);
-}
-
-int Ethernet::send() {
-    return ethernet_send();
-}
-
-int Ethernet::receive() {
-    return ethernet_receive();
-}
-
-int Ethernet::read(char *data, int size) {
-    return ethernet_read(data, size);
-}
-
-void Ethernet::address(char *mac) {
-    return ethernet_address(mac);
-}
-
-int Ethernet::link() {
-    return ethernet_link();
-}
-
-void Ethernet::set_link(Mode mode) {
-    int speed = -1;
-    int duplex = 0;
-
-    switch(mode) {
-        case AutoNegotiate : speed = -1; duplex = 0; break;
-        case HalfDuplex10  : speed = 0;  duplex = 0; break;
-        case FullDuplex10  : speed = 0;  duplex = 1; break;
-        case HalfDuplex100 : speed = 1;  duplex = 0; break;
-        case FullDuplex100 : speed = 1;  duplex = 1; break;
-    }
-
-    ethernet_set_link(speed, duplex);
-}
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Ethernet.h"
+
+#if DEVICE_ETHERNET
+
+#include "ethernet_api.h"
+
+namespace mbed {
+
+Ethernet::Ethernet() {
+    ethernet_init();
+}
+
+Ethernet::~Ethernet() {
+    ethernet_free();
+}
+
+int Ethernet::write(const char *data, int size) {
+    return ethernet_write(data, size);
+}
+
+int Ethernet::send() {
+    return ethernet_send();
+}
+
+int Ethernet::receive() {
+    return ethernet_receive();
+}
+
+int Ethernet::read(char *data, int size) {
+    return ethernet_read(data, size);
+}
+
+void Ethernet::address(char *mac) {
+    return ethernet_address(mac);
+}
+
+int Ethernet::link() {
+    return ethernet_link();
+}
+
+void Ethernet::set_link(Mode mode) {
+    int speed = -1;
+    int duplex = 0;
+
+    switch(mode) {
+        case AutoNegotiate : speed = -1; duplex = 0; break;
+        case HalfDuplex10  : speed = 0;  duplex = 0; break;
+        case FullDuplex10  : speed = 0;  duplex = 1; break;
+        case HalfDuplex100 : speed = 1;  duplex = 0; break;
+        case FullDuplex100 : speed = 1;  duplex = 1; break;
+    }
+
+    ethernet_set_link(speed, duplex);
+}
+
+} // namespace mbed
+
+#endif

--- a/common/FileBase.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/FileBase.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,83 +1,83 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FileBase.h"
-
-namespace mbed {
-
-FileBase *FileBase::_head = NULL;
-
-FileBase::FileBase(const char *name, PathType t) {
-    _name = name;
-    _path_type = t;
-
-    if (name != NULL) {
-        // put this object at head of the list
-        _next = _head;
-        _head = this;
-    } else {
-        _next = NULL;
-    }
-}
-
-FileBase::~FileBase() {
-    if (_name != NULL) {
-        // remove this object from the list
-        if (_head == this) { // first in the list, so just drop me
-            _head = _next;
-        } else {             // find the object before me, then drop me
-            FileBase *p = _head;
-            while (p->_next != this) {
-                p = p->_next;
-            }
-            p->_next = _next;
-        }
-    }
-}
-
-FileBase *FileBase::lookup(const char *name, unsigned int len) {
-    FileBase *p = _head;
-    while (p != NULL) {
-        /* Check that p->_name matches name and is the correct length */
-        if (p->_name != NULL && std::strncmp(p->_name, name, len) == 0 && std::strlen(p->_name) == len) {
-            return p;
-        }
-        p = p->_next;
-    }
-    return NULL;
-}
-
-FileBase *FileBase::get(int n) {
-    FileBase *p = _head;
-    int m = 0;
-    while (p != NULL) {
-        if (m == n) return p;
-
-        m++;
-        p = p->_next;
-    }
-    return NULL;
-}
-
-const char* FileBase::getName(void) {
-    return _name;
-}
-
-PathType FileBase::getPathType(void) {
-    return _path_type;
-}
-
-} // namespace mbed
-
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileBase.h"
+
+namespace mbed {
+
+FileBase *FileBase::_head = NULL;
+
+FileBase::FileBase(const char *name, PathType t) {
+    _name = name;
+    _path_type = t;
+
+    if (name != NULL) {
+        // put this object at head of the list
+        _next = _head;
+        _head = this;
+    } else {
+        _next = NULL;
+    }
+}
+
+FileBase::~FileBase() {
+    if (_name != NULL) {
+        // remove this object from the list
+        if (_head == this) { // first in the list, so just drop me
+            _head = _next;
+        } else {             // find the object before me, then drop me
+            FileBase *p = _head;
+            while (p->_next != this) {
+                p = p->_next;
+            }
+            p->_next = _next;
+        }
+    }
+}
+
+FileBase *FileBase::lookup(const char *name, unsigned int len) {
+    FileBase *p = _head;
+    while (p != NULL) {
+        /* Check that p->_name matches name and is the correct length */
+        if (p->_name != NULL && std::strncmp(p->_name, name, len) == 0 && std::strlen(p->_name) == len) {
+            return p;
+        }
+        p = p->_next;
+    }
+    return NULL;
+}
+
+FileBase *FileBase::get(int n) {
+    FileBase *p = _head;
+    int m = 0;
+    while (p != NULL) {
+        if (m == n) return p;
+
+        m++;
+        p = p->_next;
+    }
+    return NULL;
+}
+
+const char* FileBase::getName(void) {
+    return _name;
+}
+
+PathType FileBase::getPathType(void) {
+    return _path_type;
+}
+
+} // namespace mbed
+

--- a/common/FileLike.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/FileLike.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,28 +1,28 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FileLike.h"
-
-namespace mbed {
-
-FileLike::FileLike(const char *name) : FileHandle(), FileBase(name, FilePathType) {
-
-}
-
-FileLike::~FileLike() {
-
-}
-
-} // namespace mbed
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileLike.h"
+
+namespace mbed {
+
+FileLike::FileLike(const char *name) : FileHandle(), FileBase(name, FilePathType) {
+
+}
+
+FileLike::~FileLike() {
+
+}
+
+} // namespace mbed

--- a/common/FilePath.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/FilePath.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,71 +1,71 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FilePath.h"
-
-namespace mbed {
-
-FilePath::FilePath(const char* file_path) : file_name(NULL), fb(NULL) {
-    if ((file_path[0] != '/') || (file_path[1] == 0)) return;
-
-    const char* file_system = &file_path[1];
-    file_name = file_system;
-    int len = 0;
-    while (true) {
-        char c = *file_name;
-        if (c == '/') { // end of object name
-            file_name++; // point to one char after the '/'
-            break;
-        }
-        if (c == 0) { // end of object name, with no filename
-            break;
-        }
-        len++;
-        file_name++;
-    }
-
-    FileBase::lookup(file_system, len);
-
-
-    fb = FileBase::lookup(file_system, len);
-}
-
-const char* FilePath::fileName(void) {
-    return file_name;
-}
-
-bool FilePath::isFileSystem(void) {
-    return (fb->getPathType() == FileSystemPathType);
-}
-
-FileSystemLike* FilePath::fileSystem(void) {
-    if (isFileSystem()) {
-        return (FileSystemLike*)fb;
-    }
-    return NULL;
-}
-
-bool FilePath::isFile(void) {
-    return (fb->getPathType() == FilePathType);
-}
-
-FileLike* FilePath::file(void) {
-    if (isFile()) {
-        return (FileLike*)fb;
-    }
-    return NULL;
-}
-
-} // namespace mbed
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FilePath.h"
+
+namespace mbed {
+
+FilePath::FilePath(const char* file_path) : file_name(NULL), fb(NULL) {
+    if ((file_path[0] != '/') || (file_path[1] == 0)) return;
+
+    const char* file_system = &file_path[1];
+    file_name = file_system;
+    int len = 0;
+    while (true) {
+        char c = *file_name;
+        if (c == '/') { // end of object name
+            file_name++; // point to one char after the '/'
+            break;
+        }
+        if (c == 0) { // end of object name, with no filename
+            break;
+        }
+        len++;
+        file_name++;
+    }
+
+    FileBase::lookup(file_system, len);
+
+
+    fb = FileBase::lookup(file_system, len);
+}
+
+const char* FilePath::fileName(void) {
+    return file_name;
+}
+
+bool FilePath::isFileSystem(void) {
+    return (fb->getPathType() == FileSystemPathType);
+}
+
+FileSystemLike* FilePath::fileSystem(void) {
+    if (isFileSystem()) {
+        return (FileSystemLike*)fb;
+    }
+    return NULL;
+}
+
+bool FilePath::isFile(void) {
+    return (fb->getPathType() == FilePathType);
+}
+
+FileLike* FilePath::file(void) {
+    if (isFile()) {
+        return (FileLike*)fb;
+    }
+    return NULL;
+}
+
+} // namespace mbed

--- a/common/FileSystemLike.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/FileSystemLike.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,78 +1,78 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FileSystemLike.h"
-
-namespace mbed {
-
-class BaseDirHandle : public DirHandle {
-public:
-    /*
-      We keep track of our current location as the n'th object in the
-      FileSystemLike list. Using a Base* instead would cause problems if that
-      object were to be destroyed between readdirs.
-      Using this method does mean though that destroying/creating objects can
-      give unusual results from readdir.
-    */
-    off_t n;
-    struct dirent cur_entry;
-
-    BaseDirHandle() {
-        n = 0;
-    }
-
-    virtual int closedir() {
-        delete this;
-        return 0;
-    }
-
-    virtual struct dirent *readdir() {
-        FileBase *ptr = FileBase::get(n);
-        if (ptr == NULL) return NULL;
-
-        /* Increment n, so next readdir gets the next item */
-        n++;
-
-        /* Setup cur entry and return a pointer to it */
-        std::strncpy(cur_entry.d_name, ptr->getName(), NAME_MAX);
-        return &cur_entry;
-    }
-
-    virtual off_t telldir() {
-        return n;
-    }
-
-    virtual void seekdir(off_t offset) {
-        n = offset;
-    }
-
-    virtual void rewinddir() {
-        n = 0;
-    }
-};
-
-FileSystemLike::FileSystemLike(const char *name) : FileBase(name, FileSystemPathType) {
-
-}
-
-FileSystemLike::~FileSystemLike() {
-
-}
-
-DirHandle *FileSystemLike::opendir() {
-    return new BaseDirHandle();
-}
-
-} // namespace mbed
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileSystemLike.h"
+
+namespace mbed {
+
+class BaseDirHandle : public DirHandle {
+public:
+    /*
+      We keep track of our current location as the n'th object in the
+      FileSystemLike list. Using a Base* instead would cause problems if that
+      object were to be destroyed between readdirs.
+      Using this method does mean though that destroying/creating objects can
+      give unusual results from readdir.
+    */
+    off_t n;
+    struct dirent cur_entry;
+
+    BaseDirHandle() {
+        n = 0;
+    }
+
+    virtual int closedir() {
+        delete this;
+        return 0;
+    }
+
+    virtual struct dirent *readdir() {
+        FileBase *ptr = FileBase::get(n);
+        if (ptr == NULL) return NULL;
+
+        /* Increment n, so next readdir gets the next item */
+        n++;
+
+        /* Setup cur entry and return a pointer to it */
+        std::strncpy(cur_entry.d_name, ptr->getName(), NAME_MAX);
+        return &cur_entry;
+    }
+
+    virtual off_t telldir() {
+        return n;
+    }
+
+    virtual void seekdir(off_t offset) {
+        n = offset;
+    }
+
+    virtual void rewinddir() {
+        n = 0;
+    }
+};
+
+FileSystemLike::FileSystemLike(const char *name) : FileBase(name, FileSystemPathType) {
+
+}
+
+FileSystemLike::~FileSystemLike() {
+
+}
+
+DirHandle *FileSystemLike::opendir() {
+    return new BaseDirHandle();
+}
+
+} // namespace mbed

--- a/common/FunctionPointer.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/FunctionPointer.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,37 +1,37 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-FunctionPointer::FunctionPointer(void (*function)(void)) {
-    attach(function);
-}
-
-void FunctionPointer::attach(void (*function)(void)) {
-    _function = function;
-    _object = 0;
-}
-
-void FunctionPointer::call(void) {
-    if (_function) {
-        _function();
-    } else if (_object) {
-        _membercaller(_object, _member);
-    }
-}
-
-} // namespace mbed
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+FunctionPointer::FunctionPointer(void (*function)(void)) {
+    attach(function);
+}
+
+void FunctionPointer::attach(void (*function)(void)) {
+    _function = function;
+    _object = 0;
+}
+
+void FunctionPointer::call(void) {
+    if (_function) {
+        _function();
+    } else if (_object) {
+        _membercaller(_object, _member);
+    }
+}
+
+} // namespace mbed

--- a/common/I2C.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/I2C.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,92 +1,92 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "I2C.h"
-
-#if DEVICE_I2C
-
-namespace mbed {
-
-I2C *I2C::_owner = NULL;
-
-I2C::I2C(PinName sda, PinName scl) {
-    // The init function also set the frequency to 100000
-    i2c_init(&_i2c, sda, scl);
-    _hz = 100000;
-
-    // Used to avoid unnecessary frequency updates
-    _owner = this;
-}
-
-void I2C::frequency(int hz) {
-    _hz = hz;
-
-    // We want to update the frequency even if we are already the bus owners
-    i2c_frequency(&_i2c, _hz);
-
-    // Updating the frequency of the bus we become the owners of it
-    _owner = this;
-}
-
-void I2C::aquire() {
-    if (_owner != this) {
-        i2c_frequency(&_i2c, _hz);
-        _owner = this;
-    }
-}
-
-// write - Master Transmitter Mode
-int I2C::write(int address, const char* data, int length, bool repeated) {
-    aquire();
-
-    int stop = (repeated) ? 0 : 1;
-    int retval = i2c_write(&_i2c, address, data, length, stop);
-
-    return retval;
-}
-
-int I2C::write(int data) {
-    return i2c_byte_write(&_i2c, data);
-}
-
-// read - Master Reciever Mode
-int I2C::read(int address, char* data, int length, bool repeated) {
-    aquire();
-
-    int stop = (repeated) ? 0 : 1;
-    int retval = i2c_read(&_i2c, address, data, length, stop);
-
-    return retval;
-}
-
-int I2C::read(int ack) {
-    if (ack) {
-        return i2c_byte_read(&_i2c, 0);
-    } else {
-        return i2c_byte_read(&_i2c, 1);
-    }
-}
-
-void I2C::start(void) {
-    i2c_start(&_i2c);
-}
-
-void I2C::stop(void) {
-    i2c_stop(&_i2c);
-}
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "I2C.h"
+
+#if DEVICE_I2C
+
+namespace mbed {
+
+I2C *I2C::_owner = NULL;
+
+I2C::I2C(PinName sda, PinName scl) {
+    // The init function also set the frequency to 100000
+    i2c_init(&_i2c, sda, scl);
+    _hz = 100000;
+
+    // Used to avoid unnecessary frequency updates
+    _owner = this;
+}
+
+void I2C::frequency(int hz) {
+    _hz = hz;
+
+    // We want to update the frequency even if we are already the bus owners
+    i2c_frequency(&_i2c, _hz);
+
+    // Updating the frequency of the bus we become the owners of it
+    _owner = this;
+}
+
+void I2C::aquire() {
+    if (_owner != this) {
+        i2c_frequency(&_i2c, _hz);
+        _owner = this;
+    }
+}
+
+// write - Master Transmitter Mode
+int I2C::write(int address, const char* data, int length, bool repeated) {
+    aquire();
+
+    int stop = (repeated) ? 0 : 1;
+    int written = i2c_write(&_i2c, address, data, length, stop);
+
+    return length != written;
+}
+
+int I2C::write(int data) {
+    return i2c_byte_write(&_i2c, data);
+}
+
+// read - Master Reciever Mode
+int I2C::read(int address, char* data, int length, bool repeated) {
+    aquire();
+
+    int stop = (repeated) ? 0 : 1;
+    int read = i2c_read(&_i2c, address, data, length, stop);
+
+    return length != read;
+}
+
+int I2C::read(int ack) {
+    if (ack) {
+        return i2c_byte_read(&_i2c, 0);
+    } else {
+        return i2c_byte_read(&_i2c, 1);
+    }
+}
+
+void I2C::start(void) {
+    i2c_start(&_i2c);
+}
+
+void I2C::stop(void) {
+    i2c_stop(&_i2c);
+}
+
+} // namespace mbed
+
+#endif

--- a/common/I2CSlave.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/I2CSlave.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,63 +1,63 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "I2CSlave.h"
-
-#if DEVICE_I2CSLAVE
-
-namespace mbed {
-
-I2CSlave::I2CSlave(PinName sda, PinName scl) {
-    i2c_init(&_i2c, sda, scl);
-    i2c_frequency(&_i2c, 100000);
-    i2c_slave_mode(&_i2c, 1);
-}
-
-void I2CSlave::frequency(int hz) {
-    i2c_frequency(&_i2c, hz);
-}
-
-void I2CSlave::address(int address) {
-    int addr = (address & 0xFF) | 1;
-    i2c_slave_address(&_i2c, 0, addr, 0);
-}
-
-int I2CSlave::receive(void) {
-    return i2c_slave_receive(&_i2c);
-}
-
-int I2CSlave::read(char *data, int length) {
-    return i2c_slave_read(&_i2c, data, length);
-}
-
-int I2CSlave::read(void) {
-    return i2c_byte_read(&_i2c, 0);
-}
-
-int I2CSlave::write(const char *data, int length) {
-    return i2c_slave_write(&_i2c, data, length);
-}
-
-int I2CSlave::write(int data) {
-    return i2c_byte_write(&_i2c, data);
-}
-
-void I2CSlave::stop(void) {
-    i2c_stop(&_i2c);
-}
-
-}
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "I2CSlave.h"
+
+#if DEVICE_I2CSLAVE
+
+namespace mbed {
+
+I2CSlave::I2CSlave(PinName sda, PinName scl) {
+    i2c_init(&_i2c, sda, scl);
+    i2c_frequency(&_i2c, 100000);
+    i2c_slave_mode(&_i2c, 1);
+}
+
+void I2CSlave::frequency(int hz) {
+    i2c_frequency(&_i2c, hz);
+}
+
+void I2CSlave::address(int address) {
+    int addr = (address & 0xFF) | 1;
+    i2c_slave_address(&_i2c, 0, addr, 0);
+}
+
+int I2CSlave::receive(void) {
+    return i2c_slave_receive(&_i2c);
+}
+
+int I2CSlave::read(char *data, int length) {
+    return i2c_slave_read(&_i2c, data, length) != length;
+}
+
+int I2CSlave::read(void) {
+    return i2c_byte_read(&_i2c, 0);
+}
+
+int I2CSlave::write(const char *data, int length) {
+    return i2c_slave_write(&_i2c, data, length) != length;
+}
+
+int I2CSlave::write(int data) {
+    return i2c_byte_write(&_i2c, data);
+}
+
+void I2CSlave::stop(void) {
+    i2c_stop(&_i2c);
+}
+
+}
+
+#endif

--- a/common/InterruptIn.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/InterruptIn.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,74 +1,74 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "InterruptIn.h"
-
-#if DEVICE_INTERRUPTIN
-
-namespace mbed {
-
-InterruptIn::InterruptIn(PinName pin) {
-    gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
-    gpio_init(&gpio, pin, PIN_INPUT);
-}
-
-InterruptIn::~InterruptIn() {
-    gpio_irq_free(&gpio_irq);
-}
-
-int InterruptIn::read() {
-    return gpio_read(&gpio);
-}
-
-void InterruptIn::mode(PinMode pull) {
-    gpio_mode(&gpio, pull);
-}
-
-void InterruptIn::rise(void (*fptr)(void)) {
-    if (fptr) {
-        _rise.attach(fptr);
-        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
-    } else {
-        gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
-    }
-}
-
-void InterruptIn::fall(void (*fptr)(void)) {
-    if (fptr) {
-        _fall.attach(fptr);
-        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
-    } else {
-        gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
-    }
-}
-
-void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
-    InterruptIn *handler = (InterruptIn*)id;
-    switch (event) {
-        case IRQ_RISE: handler->_rise.call(); break;
-        case IRQ_FALL: handler->_fall.call(); break;
-        case IRQ_NONE: break;
-    }
-}
-
-#ifdef MBED_OPERATORS
-InterruptIn::operator int() {
-    return read();
-}
-#endif
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "InterruptIn.h"
+
+#if DEVICE_INTERRUPTIN
+
+namespace mbed {
+
+InterruptIn::InterruptIn(PinName pin) {
+    gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
+    gpio_init(&gpio, pin, PIN_INPUT);
+}
+
+InterruptIn::~InterruptIn() {
+    gpio_irq_free(&gpio_irq);
+}
+
+int InterruptIn::read() {
+    return gpio_read(&gpio);
+}
+
+void InterruptIn::mode(PinMode pull) {
+    gpio_mode(&gpio, pull);
+}
+
+void InterruptIn::rise(void (*fptr)(void)) {
+    if (fptr) {
+        _rise.attach(fptr);
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+    } else {
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
+    }
+}
+
+void InterruptIn::fall(void (*fptr)(void)) {
+    if (fptr) {
+        _fall.attach(fptr);
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+    } else {
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
+    }
+}
+
+void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
+    InterruptIn *handler = (InterruptIn*)id;
+    switch (event) {
+        case IRQ_RISE: handler->_rise.call(); break;
+        case IRQ_FALL: handler->_fall.call(); break;
+        case IRQ_NONE: break;
+    }
+}
+
+#ifdef MBED_OPERATORS
+InterruptIn::operator int() {
+    return read();
+}
+#endif
+
+} // namespace mbed
+
+#endif

--- a/common/LocalFileSystem.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/LocalFileSystem.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,226 +1,226 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "LocalFileSystem.h"
-
-#if DEVICE_LOCALFILESYSTEM
-
-#include "semihost_api.h"
-#include <string.h>
-#include <stdio.h>
-
-namespace mbed {
-
-/* Extension to FINFO type defined in RTL.h (in Keil RL) - adds 'create time'. */
-typedef struct {
-    unsigned char  hr;   /* Hours    [0..23]                  */
-    unsigned char  min;  /* Minutes  [0..59]                  */
-    unsigned char  sec;  /* Seconds  [0..59]                  */
-    unsigned char  day;  /* Day      [1..31]                  */
-    unsigned char  mon;  /* Month    [1..12]                  */
-    unsigned short year; /* Year     [1980..2107]             */
-} FTIME;
-
-typedef struct {         /* File Search info record           */
-    char  name[32];      /* File name                         */
-    long  size;          /* File size in bytes                */
-    int   fileID;        /* System File Identification        */
-    FTIME create_time;   /* Date & time file was created      */
-    FTIME write_time;    /* Date & time of last write         */
-} XFINFO;
-
-#define RESERVED_FOR_USER_APPLICATIONS (0x100) /* 0x100 - 0x1ff */
-#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
-
-static int xffind (const char *pattern, XFINFO *info) {
-    unsigned param[4];
-
-    param[0] = (unsigned long)pattern;
-    param[1] = (unsigned long)strlen(pattern);
-    param[2] = (unsigned long)info;
-    param[3] = (unsigned long)sizeof(XFINFO);
-
-    return __semihost(USR_XFFIND, param);
-}
-
-#define OPEN_R          0
-#define OPEN_B          1
-#define OPEN_PLUS       2
-#define OPEN_W          4
-#define OPEN_A          8
-#define OPEN_INVALID   -1
-
-int posix_to_semihost_open_flags(int flags) {
-    /* POSIX flags -> semihosting open mode */
-    int openmode;
-    if (flags & O_RDWR) {
-        /* a plus mode */
-        openmode = OPEN_PLUS;
-        if (flags & O_APPEND) {
-            openmode |= OPEN_A;
-        } else if (flags & O_TRUNC) {
-            openmode |= OPEN_W;
-        } else {
-            openmode |= OPEN_R;
-        }
-    } else if (flags & O_WRONLY) {
-        /* write or append */
-        if (flags & O_APPEND) {
-            openmode = OPEN_A;
-        } else {
-            openmode = OPEN_W;
-        }
-    } else if (flags == O_RDONLY) {
-        /* read mode */
-        openmode = OPEN_R;
-    } else {
-        /* invalid flags */
-        openmode = OPEN_INVALID;
-    }
-
-    return openmode;
-}
-
-FILEHANDLE local_file_open(const char* name, int flags) {
-    int openmode = posix_to_semihost_open_flags(flags);
-    if (openmode == OPEN_INVALID) {
-        return (FILEHANDLE)NULL;
-    }
-
-    FILEHANDLE fh = semihost_open(name, openmode);
-    if (fh == -1) {
-        return (FILEHANDLE)NULL;
-    }
-
-    return fh;
-}
-
-LocalFileHandle::LocalFileHandle(FILEHANDLE fh) {
-    _fh = fh;
-    pos = 0;
-}
-
-int LocalFileHandle::close() {
-    int retval = semihost_close(_fh);
-    delete this;
-    return retval;
-}
-
-ssize_t LocalFileHandle::write(const void *buffer, size_t length) {
-    ssize_t n = semihost_write(_fh, (const unsigned char*)buffer, length, 0); // number of characters not written
-    n = length - n; // number of characters written
-    pos += n;
-    return n;
-}
-
-ssize_t LocalFileHandle::read(void *buffer, size_t length) {
-    ssize_t n = semihost_read(_fh, (unsigned char*)buffer, length, 0); // number of characters not read
-    n = length - n; // number of characters read
-    pos += n;
-    return n;
-}
-
-int LocalFileHandle::isatty() {
-    return semihost_istty(_fh);
-}
-
-off_t LocalFileHandle::lseek(off_t position, int whence) {
-    if (whence == SEEK_CUR) {
-        position += pos;
-    } else if (whence == SEEK_END) {
-        position += semihost_flen(_fh);
-    } /* otherwise SEEK_SET, so position is fine */
-
-    /* Always seems to return -1, so just ignore for now. */
-    semihost_seek(_fh, position);
-    pos = position;
-    return position;
-}
-
-int LocalFileHandle::fsync() {
-    return semihost_ensure(_fh);
-}
-
-off_t LocalFileHandle::flen() {
-    return semihost_flen(_fh);
-}
-
-class LocalDirHandle : public DirHandle {
-
-public:
-    struct dirent cur_entry;
-    XFINFO info;
-
-    LocalDirHandle() {
-        info.fileID = 0;
-    }
-
-    virtual int closedir() {
-        delete this;
-        return 0;
-    }
-
-    virtual struct dirent *readdir() {
-        if (xffind("*", &info)!=0) {
-            return NULL;
-        }
-        memcpy(cur_entry.d_name, info.name, sizeof(info.name));
-        return &cur_entry;
-    }
-
-    virtual void rewinddir() {
-        info.fileID = 0;
-    }
-
-    virtual off_t telldir() {
-        return info.fileID;
-    }
-
-    virtual void seekdir(off_t offset) {
-        info.fileID = offset;
-    }
-};
-
-FileHandle *LocalFileSystem::open(const char* name, int flags) {
-    /* reject filenames with / in them */
-    for (const char *tmp = name; *tmp; tmp++) {
-        if (*tmp == '/') {
-            return NULL;
-        }
-    }
-
-    int openmode = posix_to_semihost_open_flags(flags);
-    if (openmode == OPEN_INVALID) {
-        return NULL;
-    }
-
-    FILEHANDLE fh = semihost_open(name, openmode);
-    if (fh == -1) {
-        return NULL;
-    }
-    return new LocalFileHandle(fh);
-}
-
-int LocalFileSystem::remove(const char *filename) {
-    return semihost_remove(filename);
-}
-
-DirHandle *LocalFileSystem::opendir(const char *name) {
-    return new LocalDirHandle();
-}
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "LocalFileSystem.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "semihost_api.h"
+#include <string.h>
+#include <stdio.h>
+
+namespace mbed {
+
+/* Extension to FINFO type defined in RTL.h (in Keil RL) - adds 'create time'. */
+typedef struct {
+    unsigned char  hr;   /* Hours    [0..23]                  */
+    unsigned char  min;  /* Minutes  [0..59]                  */
+    unsigned char  sec;  /* Seconds  [0..59]                  */
+    unsigned char  day;  /* Day      [1..31]                  */
+    unsigned char  mon;  /* Month    [1..12]                  */
+    unsigned short year; /* Year     [1980..2107]             */
+} FTIME;
+
+typedef struct {         /* File Search info record           */
+    char  name[32];      /* File name                         */
+    long  size;          /* File size in bytes                */
+    int   fileID;        /* System File Identification        */
+    FTIME create_time;   /* Date & time file was created      */
+    FTIME write_time;    /* Date & time of last write         */
+} XFINFO;
+
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) /* 0x100 - 0x1ff */
+#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
+
+static int xffind (const char *pattern, XFINFO *info) {
+    unsigned param[4];
+
+    param[0] = (unsigned long)pattern;
+    param[1] = (unsigned long)strlen(pattern);
+    param[2] = (unsigned long)info;
+    param[3] = (unsigned long)sizeof(XFINFO);
+
+    return __semihost(USR_XFFIND, param);
+}
+
+#define OPEN_R          0
+#define OPEN_B          1
+#define OPEN_PLUS       2
+#define OPEN_W          4
+#define OPEN_A          8
+#define OPEN_INVALID   -1
+
+int posix_to_semihost_open_flags(int flags) {
+    /* POSIX flags -> semihosting open mode */
+    int openmode;
+    if (flags & O_RDWR) {
+        /* a plus mode */
+        openmode = OPEN_PLUS;
+        if (flags & O_APPEND) {
+            openmode |= OPEN_A;
+        } else if (flags & O_TRUNC) {
+            openmode |= OPEN_W;
+        } else {
+            openmode |= OPEN_R;
+        }
+    } else if (flags & O_WRONLY) {
+        /* write or append */
+        if (flags & O_APPEND) {
+            openmode = OPEN_A;
+        } else {
+            openmode = OPEN_W;
+        }
+    } else if (flags == O_RDONLY) {
+        /* read mode */
+        openmode = OPEN_R;
+    } else {
+        /* invalid flags */
+        openmode = OPEN_INVALID;
+    }
+
+    return openmode;
+}
+
+FILEHANDLE local_file_open(const char* name, int flags) {
+    int openmode = posix_to_semihost_open_flags(flags);
+    if (openmode == OPEN_INVALID) {
+        return (FILEHANDLE)NULL;
+    }
+
+    FILEHANDLE fh = semihost_open(name, openmode);
+    if (fh == -1) {
+        return (FILEHANDLE)NULL;
+    }
+
+    return fh;
+}
+
+LocalFileHandle::LocalFileHandle(FILEHANDLE fh) {
+    _fh = fh;
+    pos = 0;
+}
+
+int LocalFileHandle::close() {
+    int retval = semihost_close(_fh);
+    delete this;
+    return retval;
+}
+
+ssize_t LocalFileHandle::write(const void *buffer, size_t length) {
+    ssize_t n = semihost_write(_fh, (const unsigned char*)buffer, length, 0); // number of characters not written
+    n = length - n; // number of characters written
+    pos += n;
+    return n;
+}
+
+ssize_t LocalFileHandle::read(void *buffer, size_t length) {
+    ssize_t n = semihost_read(_fh, (unsigned char*)buffer, length, 0); // number of characters not read
+    n = length - n; // number of characters read
+    pos += n;
+    return n;
+}
+
+int LocalFileHandle::isatty() {
+    return semihost_istty(_fh);
+}
+
+off_t LocalFileHandle::lseek(off_t position, int whence) {
+    if (whence == SEEK_CUR) {
+        position += pos;
+    } else if (whence == SEEK_END) {
+        position += semihost_flen(_fh);
+    } /* otherwise SEEK_SET, so position is fine */
+
+    /* Always seems to return -1, so just ignore for now. */
+    semihost_seek(_fh, position);
+    pos = position;
+    return position;
+}
+
+int LocalFileHandle::fsync() {
+    return semihost_ensure(_fh);
+}
+
+off_t LocalFileHandle::flen() {
+    return semihost_flen(_fh);
+}
+
+class LocalDirHandle : public DirHandle {
+
+public:
+    struct dirent cur_entry;
+    XFINFO info;
+
+    LocalDirHandle() {
+        info.fileID = 0;
+    }
+
+    virtual int closedir() {
+        delete this;
+        return 0;
+    }
+
+    virtual struct dirent *readdir() {
+        if (xffind("*", &info)!=0) {
+            return NULL;
+        }
+        memcpy(cur_entry.d_name, info.name, sizeof(info.name));
+        return &cur_entry;
+    }
+
+    virtual void rewinddir() {
+        info.fileID = 0;
+    }
+
+    virtual off_t telldir() {
+        return info.fileID;
+    }
+
+    virtual void seekdir(off_t offset) {
+        info.fileID = offset;
+    }
+};
+
+FileHandle *LocalFileSystem::open(const char* name, int flags) {
+    /* reject filenames with / in them */
+    for (const char *tmp = name; *tmp; tmp++) {
+        if (*tmp == '/') {
+            return NULL;
+        }
+    }
+
+    int openmode = posix_to_semihost_open_flags(flags);
+    if (openmode == OPEN_INVALID) {
+        return NULL;
+    }
+
+    FILEHANDLE fh = semihost_open(name, openmode);
+    if (fh == -1) {
+        return NULL;
+    }
+    return new LocalFileHandle(fh);
+}
+
+int LocalFileSystem::remove(const char *filename) {
+    return semihost_remove(filename);
+}
+
+DirHandle *LocalFileSystem::opendir(const char *name) {
+    return new LocalDirHandle();
+}
+
+} // namespace mbed
+
+#endif

--- a/common/SPI.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/SPI.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,62 +1,62 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "SPI.h"
-
-#if DEVICE_SPI
-
-namespace mbed {
-
-SPI::SPI(PinName mosi, PinName miso, PinName sclk) {
-    spi_init(&_spi, mosi, miso, sclk, NC);
-    _bits = 8;
-    _mode = 0;
-    _hz = 1000000;
-    spi_format(&_spi, _bits, _mode, 0);
-    spi_frequency(&_spi, _hz);
-}
-
-void SPI::format(int bits, int mode) {
-    _bits = bits;
-    _mode = mode;
-    SPI::_owner = NULL; // Not that elegant, but works. rmeyer
-    aquire();
-}
-
-void SPI::frequency(int hz) {
-    _hz = hz;
-    SPI::_owner = NULL; // Not that elegant, but works. rmeyer
-    aquire();
-}
-
-SPI* SPI::_owner = NULL;
-
-// ignore the fact there are multiple physical spis, and always update if it wasnt us last
-void SPI::aquire() {
-     if (_owner != this) {
-        spi_format(&_spi, _bits, _mode, 0);
-        spi_frequency(&_spi, _hz);
-        _owner = this;
-    }
-}
-
-int SPI::write(int value) {
-    aquire();
-    return spi_master_write(&_spi, value);
-}
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SPI.h"
+
+#if DEVICE_SPI
+
+namespace mbed {
+
+SPI::SPI(PinName mosi, PinName miso, PinName sclk) {
+    spi_init(&_spi, mosi, miso, sclk, NC);
+    _bits = 8;
+    _mode = 0;
+    _hz = 1000000;
+    spi_format(&_spi, _bits, _mode, 0);
+    spi_frequency(&_spi, _hz);
+}
+
+void SPI::format(int bits, int mode) {
+    _bits = bits;
+    _mode = mode;
+    SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+    aquire();
+}
+
+void SPI::frequency(int hz) {
+    _hz = hz;
+    SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+    aquire();
+}
+
+SPI* SPI::_owner = NULL;
+
+// ignore the fact there are multiple physical spis, and always update if it wasnt us last
+void SPI::aquire() {
+     if (_owner != this) {
+        spi_format(&_spi, _bits, _mode, 0);
+        spi_frequency(&_spi, _hz);
+        _owner = this;
+    }
+}
+
+int SPI::write(int value) {
+    aquire();
+    return spi_master_write(&_spi, value);
+}
+
+} // namespace mbed
+
+#endif

--- a/common/SPISlave.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/SPISlave.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,56 +1,56 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "SPISlave.h"
-
-#if DEVICE_SPISLAVE
-
-namespace mbed {
-
-SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) {
-    spi_init(&_spi, mosi, miso, sclk, ssel);
-    _bits = 8;
-    _mode = 0;
-    _hz = 1000000;
-    spi_format(&_spi, _bits, _mode, 1);
-    spi_frequency(&_spi, _hz);
-}
-
-void SPISlave::format(int bits, int mode) {
-    _bits = bits;
-    _mode = mode;
-    spi_format(&_spi, _bits, _mode, 1);
-}
-
-void SPISlave::frequency(int hz) {
-    _hz = hz;
-    spi_frequency(&_spi, _hz);
-}
-
-int SPISlave::receive(void) {
-    return(spi_slave_receive(&_spi));
-}
-
-int SPISlave::read(void) {
-    return(spi_slave_read(&_spi));
-}
-
-void SPISlave::reply(int value) {
-    spi_slave_write(&_spi, value);
-}
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SPISlave.h"
+
+#if DEVICE_SPISLAVE
+
+namespace mbed {
+
+SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    spi_init(&_spi, mosi, miso, sclk, ssel);
+    _bits = 8;
+    _mode = 0;
+    _hz = 1000000;
+    spi_format(&_spi, _bits, _mode, 1);
+    spi_frequency(&_spi, _hz);
+}
+
+void SPISlave::format(int bits, int mode) {
+    _bits = bits;
+    _mode = mode;
+    spi_format(&_spi, _bits, _mode, 1);
+}
+
+void SPISlave::frequency(int hz) {
+    _hz = hz;
+    spi_frequency(&_spi, _hz);
+}
+
+int SPISlave::receive(void) {
+    return(spi_slave_receive(&_spi));
+}
+
+int SPISlave::read(void) {
+    return(spi_slave_read(&_spi));
+}
+
+void SPISlave::reply(int value) {
+    spi_slave_write(&_spi, value);
+}
+
+} // namespace mbed
+
+#endif

--- a/common/Serial.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/Serial.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,70 +1,87 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Serial.h"
-
-#if DEVICE_SERIAL
-
-namespace mbed {
-
-Serial::Serial(PinName tx, PinName rx, const char *name) : Stream(name) {
-    serial_init(&_serial, tx, rx);
-    serial_irq_handler(&_serial, Serial::_irq_handler, (uint32_t)this);
-}
-
-void Serial::baud(int baudrate) {
-    serial_baud(&_serial, baudrate);
-}
-
-void Serial::format(int bits, Parity parity, int stop_bits) {
-    serial_format(&_serial, bits, (SerialParity)parity, stop_bits);
-}
-
-int Serial::readable() {
-    return serial_readable(&_serial);
-}
-
-
-int Serial::writeable() {
-    return serial_writable(&_serial);
-}
-
-void Serial::attach(void (*fptr)(void), IrqType type) {
-    if (fptr) {
-        _irq[type].attach(fptr);
-        serial_irq_set(&_serial, (SerialIrq)type, 1);
-    } else {
-        serial_irq_set(&_serial, (SerialIrq)type, 0);
-    }
-}
-
-
-void Serial::_irq_handler(uint32_t id, SerialIrq irq_type) {
-    Serial *handler = (Serial*)id;
-    handler->_irq[irq_type].call();
-}
-
-int Serial::_getc() {
-    return serial_getc(&_serial);
-}
-
-int Serial::_putc(int c) {
-    serial_putc(&_serial, c);
-    return c;
-}
-
-} // namespace mbed
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Serial.h"
+#include "wait_api.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+Serial::Serial(PinName tx, PinName rx, const char *name) : Stream(name) {
+    serial_init(&_serial, tx, rx);
+    _baud = 9600;
+    serial_irq_handler(&_serial, Serial::_irq_handler, (uint32_t)this);
+}
+
+void Serial::baud(int baudrate) {
+    serial_baud(&_serial, baudrate);
+    _baud = baudrate;
+}
+
+void Serial::format(int bits, Parity parity, int stop_bits) {
+    serial_format(&_serial, bits, (SerialParity)parity, stop_bits);
+}
+
+int Serial::readable() {
+    return serial_readable(&_serial);
+}
+
+
+int Serial::writeable() {
+    return serial_writable(&_serial);
+}
+
+void Serial::attach(void (*fptr)(void), IrqType type) {
+    if (fptr) {
+        _irq[type].attach(fptr);
+        serial_irq_set(&_serial, (SerialIrq)type, 1);
+    } else {
+        serial_irq_set(&_serial, (SerialIrq)type, 0);
+    }
+}
+
+
+void Serial::_irq_handler(uint32_t id, SerialIrq irq_type) {
+    Serial *handler = (Serial*)id;
+    handler->_irq[irq_type].call();
+}
+
+int Serial::_getc() {
+    return serial_getc(&_serial);
+}
+
+int Serial::_putc(int c) {
+    serial_putc(&_serial, c);
+    return c;
+}
+
+void Serial::send_break() {
+  // Wait for 1.5 frames before clearing the break condition
+  // This will have different effects on our platforms, but should
+  // ensure that we keep the break active for at least one frame.
+  // We consider a full frame (1 start bit + 8 data bits bits + 
+  // 1 parity bit + 2 stop bits = 12 bits) for computation.
+  // One bit time (in us) = 1000000/_baud
+  // Twelve bits: 12000000/baud delay
+  // 1.5 frames: 18000000/baud delay
+  serial_break_set(&_serial);
+  wait_us(18000000/_baud);
+  serial_break_clear(&_serial);
+}
+
+} // namespace mbed
+
+#endif

--- a/common/Stream.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/Stream.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,111 +1,111 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Stream.h"
-
-#include <cstdarg>
-
-namespace mbed {
-
-Stream::Stream(const char *name) : FileLike(name) {
-    /* open ourselves */
-    char buf[12]; /* :0x12345678 + null byte */
-    std::sprintf(buf, ":%p", this);
-    _file = std::fopen(buf, "w+");
-    setbuf(_file, NULL);
-}
-
-Stream::~Stream() {
-    fclose(_file);
-}
-
-int Stream::putc(int c) {
-    fflush(_file);
-    return std::fputc(c, _file);
-}
-int Stream::puts(const char *s) {
-    fflush(_file);
-    return std::fputs(s, _file);
-}
-int Stream::getc() {
-    fflush(_file);
-    return std::fgetc(_file);
-}
-char* Stream::gets(char *s, int size) {
-    fflush(_file);
-    return std::fgets(s,size,_file);
-}
-
-int Stream::close() {
-    return 0;
-}
-
-ssize_t Stream::write(const void* buffer, size_t length) {
-    const char* ptr = (const char*)buffer;
-    const char* end = ptr + length;
-    while (ptr != end) {
-        if (_putc(*ptr++) == EOF) {
-            break;
-        }
-    }
-    return ptr - (const char*)buffer;
-}
-
-ssize_t Stream::read(void* buffer, size_t length) {
-    char* ptr = (char*)buffer;
-    char* end = ptr + length;
-    while (ptr != end) {
-        int c = _getc();
-        if (c==EOF) break;
-        *ptr++ = c;
-    }
-    return ptr - (const char*)buffer;
-}
-
-off_t Stream::lseek(off_t offset, int whence) {
-    return 0;
-}
-
-int Stream::isatty() {
-    return 0;
-}
-
-int Stream::fsync() {
-    return 0;
-}
-
-off_t Stream::flen() {
-    return 0;
-}
-
-int Stream::printf(const char* format, ...) {
-    std::va_list arg;
-    va_start(arg, format);
-    fflush(_file);
-    int r = vfprintf(_file, format, arg);
-    va_end(arg);
-    return r;
-}
-
-int Stream::scanf(const char* format, ...) {
-    std::va_list arg;
-    va_start(arg, format);
-    fflush(_file);
-    int r = vfscanf(_file, format, arg);
-    va_end(arg);
-    return r;
-}
-
-} // namespace mbed
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Stream.h"
+
+#include <cstdarg>
+
+namespace mbed {
+
+Stream::Stream(const char *name) : FileLike(name) {
+    /* open ourselves */
+    char buf[12]; /* :0x12345678 + null byte */
+    std::sprintf(buf, ":%p", this);
+    _file = std::fopen(buf, "w+");
+    setbuf(_file, NULL);
+}
+
+Stream::~Stream() {
+    fclose(_file);
+}
+
+int Stream::putc(int c) {
+    fflush(_file);
+    return std::fputc(c, _file);
+}
+int Stream::puts(const char *s) {
+    fflush(_file);
+    return std::fputs(s, _file);
+}
+int Stream::getc() {
+    fflush(_file);
+    return std::fgetc(_file);
+}
+char* Stream::gets(char *s, int size) {
+    fflush(_file);
+    return std::fgets(s,size,_file);
+}
+
+int Stream::close() {
+    return 0;
+}
+
+ssize_t Stream::write(const void* buffer, size_t length) {
+    const char* ptr = (const char*)buffer;
+    const char* end = ptr + length;
+    while (ptr != end) {
+        if (_putc(*ptr++) == EOF) {
+            break;
+        }
+    }
+    return ptr - (const char*)buffer;
+}
+
+ssize_t Stream::read(void* buffer, size_t length) {
+    char* ptr = (char*)buffer;
+    char* end = ptr + length;
+    while (ptr != end) {
+        int c = _getc();
+        if (c==EOF) break;
+        *ptr++ = c;
+    }
+    return ptr - (const char*)buffer;
+}
+
+off_t Stream::lseek(off_t offset, int whence) {
+    return 0;
+}
+
+int Stream::isatty() {
+    return 0;
+}
+
+int Stream::fsync() {
+    return 0;
+}
+
+off_t Stream::flen() {
+    return 0;
+}
+
+int Stream::printf(const char* format, ...) {
+    std::va_list arg;
+    va_start(arg, format);
+    fflush(_file);
+    int r = vfprintf(_file, format, arg);
+    va_end(arg);
+    return r;
+}
+
+int Stream::scanf(const char* format, ...) {
+    std::va_list arg;
+    va_start(arg, format);
+    fflush(_file);
+    int r = vfscanf(_file, format, arg);
+    va_end(arg);
+    return r;
+}
+
+} // namespace mbed

--- a/common/Ticker.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/Ticker.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,39 +1,39 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Ticker.h"
-
-#include "TimerEvent.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-void Ticker::detach() {
-    remove();
-    _function.attach(0);
-}
-
-void Ticker::setup(unsigned int t) {
-    remove();
-    _delay = t;
-    insert(_delay + us_ticker_read());
-}
-
-void Ticker::handler() {
-    insert(event.timestamp + _delay);
-    _function.call();
-}
-
-} // namespace mbed
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Ticker.h"
+
+#include "TimerEvent.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+void Ticker::detach() {
+    remove();
+    _function.attach(0);
+}
+
+void Ticker::setup(unsigned int t) {
+    remove();
+    _delay = t;
+    insert(_delay + us_ticker_read());
+}
+
+void Ticker::handler() {
+    insert(event.timestamp + _delay);
+    _function.call();
+}
+
+} // namespace mbed

--- a/common/Timeout.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/Timeout.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,24 +1,24 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Timeout.h"
-
-namespace mbed {
-
-void Timeout::handler() {
-    _function.call();
-}
-
-} // namespace mbed
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Timeout.h"
+
+namespace mbed {
+
+void Timeout::handler() {
+    _function.call();
+}
+
+} // namespace mbed

--- a/common/Timer.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/Timer.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,66 +1,66 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Timer.h"
-#include "us_ticker_api.h"
-
-namespace mbed {
-
-Timer::Timer() {
-    reset();
-}
-
-void Timer::start() {
-    _start = us_ticker_read();
-    _running = 1;
-}
-
-void Timer::stop() {
-    _time += slicetime();
-    _running = 0;
-}
-
-int Timer::read_us() {
-    return _time + slicetime();
-}
-
-float Timer::read() {
-    return (float)read_us() / 1000000.0f;
-}
-
-int Timer::read_ms() {
-    return read_us() / 1000;
-}
-
-int Timer::slicetime() {
-    if (_running) {
-        return us_ticker_read() - _start;
-    } else {
-        return 0;
-    }
-}
-
-void Timer::reset() {
-    _start = us_ticker_read();
-    _time = 0;
-}
-
-#ifdef MBED_OPERATORS
-Timer::operator float() {
-    return read();
-}
-#endif
-
-} // namespace mbed
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Timer.h"
+#include "us_ticker_api.h"
+
+namespace mbed {
+
+Timer::Timer() {
+    reset();
+}
+
+void Timer::start() {
+    _start = us_ticker_read();
+    _running = 1;
+}
+
+void Timer::stop() {
+    _time += slicetime();
+    _running = 0;
+}
+
+int Timer::read_us() {
+    return _time + slicetime();
+}
+
+float Timer::read() {
+    return (float)read_us() / 1000000.0f;
+}
+
+int Timer::read_ms() {
+    return read_us() / 1000;
+}
+
+int Timer::slicetime() {
+    if (_running) {
+        return us_ticker_read() - _start;
+    } else {
+        return 0;
+    }
+}
+
+void Timer::reset() {
+    _start = us_ticker_read();
+    _time = 0;
+}
+
+#ifdef MBED_OPERATORS
+Timer::operator float() {
+    return read();
+}
+#endif
+
+} // namespace mbed

--- a/common/TimerEvent.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/TimerEvent.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -1,45 +1,45 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "TimerEvent.h"
-#include "cmsis.h"
-
-#include <stddef.h>
-
-namespace mbed {
-
-TimerEvent::TimerEvent() {
-    us_ticker_set_handler((&TimerEvent::irq));
-}
-
-void TimerEvent::irq(uint32_t id) {
-    TimerEvent *timer_event = (TimerEvent*)id;
-    timer_event->handler();
-}
-
-TimerEvent::~TimerEvent() {
-    remove();
-}
-
-// insert in to linked list
-void TimerEvent::insert(unsigned int timestamp) {
-    us_ticker_insert_event(&event, timestamp, (uint32_t)this);
-}
-
-void TimerEvent::remove() {
-    us_ticker_remove_event(&event);
-}
-
-} // namespace mbed
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "TimerEvent.h"
+#include "cmsis.h"
+
+#include <stddef.h>
+
+namespace mbed {
+
+TimerEvent::TimerEvent() {
+    us_ticker_set_handler((&TimerEvent::irq));
+}
+
+void TimerEvent::irq(uint32_t id) {
+    TimerEvent *timer_event = (TimerEvent*)id;
+    timer_event->handler();
+}
+
+TimerEvent::~TimerEvent() {
+    remove();
+}
+
+// insert in to linked list
+void TimerEvent::insert(unsigned int timestamp) {
+    us_ticker_insert_event(&event, timestamp, (uint32_t)this);
+}
+
+void TimerEvent::remove() {
+    us_ticker_remove_event(&event);
+}
+
+} // namespace mbed

--- a/common/mbed_interface.c	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/mbed_interface.c	Mon Aug 05 14:12:34 2013 +0300
@@ -1,107 +1,115 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stdio.h>
-#include "mbed_interface.h"
-
-#include "gpio_api.h"
-#include "wait_api.h"
-#include "semihost_api.h"
-#include "error.h"
-#include "toolchain.h"
-
-#if DEVICE_SEMIHOST
-
-// return true if a debugger is attached, indicating mbed interface is connected
-int mbed_interface_connected(void) {
-    return semihost_connected();
-}
-
-int mbed_interface_reset(void) {
-    if (mbed_interface_connected()) {
-        semihost_reset();
-        return 0;
-    } else {
-        return -1;
-    }
-}
-
-WEAK int mbed_interface_uid(char *uid);
-WEAK int mbed_interface_uid(char *uid) {
-    if (mbed_interface_connected()) {
-        return semihost_uid(uid); // Returns 0 if successful, -1 on failure
-    } else {
-        uid[0] = 0;
-        return -1;
-    }
-}
-
-int mbed_interface_disconnect(void) {
-    if (mbed_interface_connected()) {
-        return semihost_disabledebug();
-    } else {
-        return -1;
-    }
-}
-
-int mbed_interface_powerdown(void) {
-    if (mbed_interface_connected()) {
-        return semihost_powerdown();
-    } else {
-        return -1;
-    }
-}
-
-// for backward compatibility
-void mbed_reset(void) {
-    mbed_interface_reset();
-}
-
-WEAK int mbed_uid(char *uid);
-WEAK int mbed_uid(char *uid) {
-    return mbed_interface_uid(uid);
-}
-#endif
-
-WEAK void mbed_mac_address(char *mac);
-WEAK void mbed_mac_address(char *mac) {
-#if DEVICE_SEMIHOST
-    char uid[DEVICE_ID_LENGTH + 1];
-    int i;
-    
-    // if we have a UID, extract the MAC
-    if (mbed_interface_uid(uid) == 0) {
-        char *p = uid;
-#if defined(DEVICE_MAC_OFFSET)
-        p += DEVICE_MAC_OFFSET;
-#endif
-        for (i=0; i<6; i++) {
-            int byte;
-            sscanf(p, "%2x", &byte);
-            mac[i] = byte;
-            p += 2;
-        }
-    } else {  // else return a default MAC
-#endif
-        mac[0] = 0x00;
-        mac[1] = 0x02;
-        mac[2] = 0xF7;
-        mac[3] = 0xF0;
-        mac[4] = 0x00;
-        mac[5] = 0x00;
-#if DEVICE_SEMIHOST
-    }
-#endif
-}
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include "mbed_interface.h"
+
+#include "gpio_api.h"
+#include "wait_api.h"
+#include "semihost_api.h"
+#include "error.h"
+#include "toolchain.h"
+
+#if DEVICE_SEMIHOST
+
+// return true if a debugger is attached, indicating mbed interface is connected
+int mbed_interface_connected(void) {
+    return semihost_connected();
+}
+
+int mbed_interface_reset(void) {
+    if (mbed_interface_connected()) {
+        semihost_reset();
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+WEAK int mbed_interface_uid(char *uid);
+WEAK int mbed_interface_uid(char *uid) {
+    if (mbed_interface_connected()) {
+        return semihost_uid(uid); // Returns 0 if successful, -1 on failure
+    } else {
+        uid[0] = 0;
+        return -1;
+    }
+}
+
+int mbed_interface_disconnect(void) {
+    int res;
+    if (mbed_interface_connected()) {
+        if ((res = semihost_disabledebug()) != 0)
+            return res;
+        while (mbed_interface_connected());
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+int mbed_interface_powerdown(void) {
+    int res;
+    if (mbed_interface_connected()) {
+        if ((res = semihost_powerdown()) != 0)
+            return res;
+        while (mbed_interface_connected());
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+// for backward compatibility
+void mbed_reset(void) {
+    mbed_interface_reset();
+}
+
+WEAK int mbed_uid(char *uid);
+WEAK int mbed_uid(char *uid) {
+    return mbed_interface_uid(uid);
+}
+#endif
+
+WEAK void mbed_mac_address(char *mac);
+WEAK void mbed_mac_address(char *mac) {
+#if DEVICE_SEMIHOST
+    char uid[DEVICE_ID_LENGTH + 1];
+    int i;
+    
+    // if we have a UID, extract the MAC
+    if (mbed_interface_uid(uid) == 0) {
+        char *p = uid;
+#if defined(DEVICE_MAC_OFFSET)
+        p += DEVICE_MAC_OFFSET;
+#endif
+        for (i=0; i<6; i++) {
+            int byte;
+            sscanf(p, "%2x", &byte);
+            mac[i] = byte;
+            p += 2;
+        }
+    } else {  // else return a default MAC
+#endif
+        mac[0] = 0x00;
+        mac[1] = 0x02;
+        mac[2] = 0xF7;
+        mac[3] = 0xF0;
+        mac[4] = 0x00;
+        mac[5] = 0x00;
+#if DEVICE_SEMIHOST
+    }
+#endif
+}

--- a/common/pinmap_common.c	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/pinmap_common.c	Mon Aug 05 14:12:34 2013 +0300
@@ -22,6 +22,7 @@
     while (map->pin != NC) {
         if (map->pin == pin) {
             pin_function(pin, map->function);
+            
             pin_mode(pin, PullNone);
             return;
         }

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/common/retarget.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,427 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform.h"
+#include "FileHandle.h"
+#include "FileSystemLike.h"
+#include "FilePath.h"
+#include "serial_api.h"
+#include "toolchain.h"
+#include <errno.h>
+
+#if defined(__ARMCC_VERSION)
+#   include <rt_sys.h>
+#   define PREFIX(x)    _sys##x
+#   define OPEN_MAX     _SYS_OPEN
+#   ifdef __MICROLIB
+#       pragma import(__use_full_stdio)
+#   endif
+
+#elif defined(__ICCARM__)
+#   include <yfuns.h>
+#   define PREFIX(x)        _##x
+#   define OPEN_MAX         16
+
+#   define STDIN_FILENO     0
+#   define STDOUT_FILENO    1
+#   define STDERR_FILENO    2
+
+#else
+#   include <sys/stat.h>
+#   include <sys/unistd.h>
+#   include <sys/syslimits.h>
+#   define PREFIX(x)    x
+#endif
+
+using namespace mbed;
+
+#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+// Before version 5.03, we were using a patched version of microlib with proper names
+extern const char __stdin_name[]  = ":tt";
+extern const char __stdout_name[] = ":tt";
+extern const char __stderr_name[] = ":tt";
+
+#else
+extern const char __stdin_name[]  = "/stdin";
+extern const char __stdout_name[] = "/stdout";
+extern const char __stderr_name[] = "/stderr";
+#endif
+
+/* newlib has the filehandle field in the FILE struct as a short, so
+ * we can't just return a Filehandle* from _open and instead have to
+ * put it in a filehandles array and return the index into that array
+ * (or rather index+3, as filehandles 0-2 are stdin/out/err).
+ */
+static FileHandle *filehandles[OPEN_MAX];
+
+FileHandle::~FileHandle() {
+    /* Remove all open filehandles for this */
+    for (unsigned int fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+        if (filehandles[fh_i] == this) {
+            filehandles[fh_i] = NULL;
+        }
+    }
+}
+
+#if DEVICE_SERIAL
+extern int stdio_uart_inited;
+extern serial_t stdio_uart;
+#endif
+
+static void init_serial() {
+#if DEVICE_SERIAL
+    if (stdio_uart_inited) return;
+    serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
+#endif
+}
+
+static inline int openmode_to_posix(int openmode) {
+    int posix = openmode;
+#ifdef __ARMCC_VERSION
+    if (openmode & OPEN_PLUS) {
+        posix = O_RDWR;
+    } else if(openmode & OPEN_W) {
+        posix = O_WRONLY;
+    } else if(openmode & OPEN_A) {
+        posix = O_WRONLY|O_APPEND;
+    } else {
+        posix = O_RDONLY;
+    }
+    /* a, w, a+, w+ all create if file does not already exist */
+    if (openmode & (OPEN_A|OPEN_W)) {
+        posix |= O_CREAT;
+    }
+    /* w and w+ truncate */
+    if (openmode & OPEN_W) {
+        posix |= O_TRUNC;
+    }
+#elif defined(__ICCARM__)
+    switch (openmode & _LLIO_RDWRMASK) {
+        case _LLIO_RDONLY: posix = O_RDONLY; break;
+        case _LLIO_WRONLY: posix = O_WRONLY; break;
+        case _LLIO_RDWR  : posix = O_RDWR  ; break;
+    }
+    if (openmode & _LLIO_CREAT ) posix |= O_CREAT;
+    if (openmode & _LLIO_APPEND) posix |= O_APPEND;
+    if (openmode & _LLIO_TRUNC ) posix |= O_TRUNC;
+#endif
+    return posix;
+}
+
+extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
+    #if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+    // Before version 5.03, we were using a patched version of microlib with proper names
+    // This is the workaround that the microlib author suggested us
+    static int n = 0;
+    if (!std::strcmp(name, ":tt")) return n++;
+    
+    #else
+    /* Use the posix convention that stdin,out,err are filehandles 0,1,2.
+     */
+    if (std::strcmp(name, __stdin_name) == 0) {
+        init_serial();
+        return 0;
+    } else if (std::strcmp(name, __stdout_name) == 0) {
+        init_serial();
+        return 1;
+    } else if (std::strcmp(name, __stderr_name) == 0) {
+        init_serial();
+        return 2;
+    }
+    #endif
+    
+    // find the first empty slot in filehandles
+    unsigned int fh_i;
+    for (fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+        if (filehandles[fh_i] == NULL) break;
+    }
+    if (fh_i >= sizeof(filehandles)/sizeof(*filehandles)) {
+        return -1;
+    }
+
+    FileHandle *res;
+
+    /* FILENAME: ":0x12345678" describes a FileLike* */
+    if (name[0] == ':') {
+        void *p;
+        sscanf(name, ":%p", &p);
+        res = (FileHandle*)p;
+
+    /* FILENAME: "/file_system/file_name" */
+    } else {
+        FilePath path(name);
+
+        if (path.isFile()) {
+            res = path.file();
+        } else {
+            FileSystemLike *fs = path.fileSystem();
+            if (fs == NULL) return -1;
+            int posix_mode = openmode_to_posix(openmode);
+            res = fs->open(path.fileName(), posix_mode); /* NULL if fails */
+        }
+    }
+
+    if (res == NULL) return -1;
+    filehandles[fh_i] = res;
+
+    return fh_i + 3; // +3 as filehandles 0-2 are stdin/out/err
+}
+
+extern "C" int PREFIX(_close)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    filehandles[fh-3] = NULL;
+    if (fhc == NULL) return -1;
+
+    return fhc->close();
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t    __write (int        fh, const unsigned char *buffer, size_t length) {
+#else
+extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode) {
+#endif
+    int n; // n is the number of bytes written
+    if (fh < 3) {
+#if DEVICE_SERIAL
+        if (!stdio_uart_inited) init_serial();
+        for (unsigned int i = 0; i < length; i++) {
+            serial_putc(&stdio_uart, buffer[i]);
+        }
+#endif
+        n = length;
+    } else {
+        FileHandle* fhc = filehandles[fh-3];
+        if (fhc == NULL) return -1;
+
+        n = fhc->write(buffer, length);
+    }
+#ifdef __ARMCC_VERSION
+    return length-n;
+#else
+    return n;
+#endif
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t    __read (int        fh, unsigned char *buffer, size_t       length) {
+#else
+extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode) {
+#endif
+    int n; // n is the number of bytes read
+    if (fh < 3) {
+        // only read a character at a time from stdin
+#if DEVICE_SERIAL
+        *buffer = serial_getc(&stdio_uart);
+#endif
+        n = 1;
+    } else {
+        FileHandle* fhc = filehandles[fh-3];
+        if (fhc == NULL) return -1;
+
+        n = fhc->read(buffer, length);
+    }
+#ifdef __ARMCC_VERSION
+    return length-n;
+#else
+    return n;
+#endif
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_istty)(FILEHANDLE fh)
+#else
+extern "C" int _isatty(FILEHANDLE fh)
+#endif
+{
+    /* stdin, stdout and stderr should be tty */
+    if (fh < 3) return 1;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+    return fhc->isatty();
+}
+
+extern "C"
+#if defined(__ARMCC_VERSION)
+int _sys_seek(FILEHANDLE fh, long position)
+#elif defined(__ICCARM__)
+long __lseek(int fh, long offset, int whence)
+#else
+int _lseek(FILEHANDLE fh, int offset, int whence)
+#endif
+{
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+#if defined(__ARMCC_VERSION)
+    return fhc->lseek(position, SEEK_SET);
+#else
+    return fhc->lseek(offset, whence);
+#endif
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_ensure)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+    return fhc->fsync();
+}
+
+extern "C" long PREFIX(_flen)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+    return fhc->flen();
+}
+#endif
+
+
+#if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
+extern "C" int _fstat(int fd, struct stat *st) {
+    if ((STDOUT_FILENO == fd) || (STDERR_FILENO == fd) || (STDIN_FILENO == fd)) {
+        st->st_mode = S_IFCHR;
+        return  0;
+    }
+
+    errno = EBADF;
+    return -1;
+}
+#endif
+
+namespace std {
+extern "C" int remove(const char *path) {
+    FilePath fp(path);
+    FileSystemLike *fs = fp.fileSystem();
+    if (fs == NULL) return -1;
+
+    return fs->remove(fp.fileName());
+}
+
+extern "C" int rename(const char *oldname, const char *newname) {
+    return -1;
+}
+
+extern "C" char *tmpnam(char *s) {
+    return NULL;
+}
+
+extern "C" FILE *tmpfile() {
+    return NULL;
+}
+} // namespace std
+
+#ifdef __ARMCC_VERSION
+extern "C" char *_sys_command_string(char *cmd, int len) {
+    return NULL;
+}
+#endif
+
+extern "C" DIR *opendir(const char *path) {
+    /* root dir is FileSystemLike */
+    if (path[0] == '/' && path[1] == 0) {
+        return FileSystemLike::opendir();
+    }
+
+    FilePath fp(path);
+    FileSystemLike* fs = fp.fileSystem();
+    if (fs == NULL) return NULL;
+
+    return fs->opendir(fp.fileName());
+}
+
+extern "C" struct dirent *readdir(DIR *dir) {
+    return dir->readdir();
+}
+
+extern "C" int closedir(DIR *dir) {
+    return dir->closedir();
+}
+
+extern "C" void rewinddir(DIR *dir) {
+    dir->rewinddir();
+}
+
+extern "C" off_t telldir(DIR *dir) {
+    return dir->telldir();
+}
+
+extern "C" void seekdir(DIR *dir, off_t off) {
+    dir->seekdir(off);
+}
+
+extern "C" int mkdir(const char *path, mode_t mode) {
+    FilePath fp(path);
+    FileSystemLike *fs = fp.fileSystem();
+    if (fs == NULL) return -1;
+
+    return fs->mkdir(fp.fileName(), mode);
+}
+
+#if defined(TOOLCHAIN_GCC)
+/* prevents the exception handling name demangling code getting pulled in */
+#include "error.h"
+namespace __gnu_cxx {
+    void __verbose_terminate_handler() {
+        error("Exception");
+    }
+}
+extern "C" WEAK void __cxa_pure_virtual(void);
+extern "C" WEAK void __cxa_pure_virtual(void) {
+    exit(1);
+}
+
+#endif
+
+// ****************************************************************************
+// mbed_main is a function that is called before main()
+
+extern "C" WEAK void mbed_main(void);
+extern "C" WEAK void mbed_main(void) {
+}
+
+#if defined(TOOLCHAIN_ARM)
+extern "C" int $Super$$main(void);
+
+extern "C" int $Sub$$main(void) {
+    mbed_main();
+    return $Super$$main();
+}
+#elif defined(TOOLCHAIN_GCC)
+extern "C" int __real_main(void);
+
+extern "C" int __wrap_main(void) {
+    mbed_main();
+    return __real_main();
+}
+#elif defined(TOOLCHAIN_IAR)
+// IAR doesn't have the $Super/$Sub mechanism of armcc, nor something equivalent
+// to ld's --wrap. It does have a --redirect, but that doesn't help, since redirecting
+// 'main' to another symbol looses the original 'main' symbol. However, its startup
+// code will call a function to setup argc and argv (__iar_argc_argv) if it is defined.
+// Since mbed doesn't use argc/argv, we use this function to call our mbed_main.
+extern "C" void __iar_argc_argv() {
+    mbed_main();
+}
+#endif

--- a/common/rtc_time.c	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/rtc_time.c	Mon Aug 05 14:12:34 2013 +0300
@@ -1,55 +1,55 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "rtc_api.h"
-
-#include <time.h>
-#include "rtc_time.h"
-#include "us_ticker_api.h"
-
-#if defined (__ICCARM__)
-time_t __time32(time_t *timer)
-#else
-time_t time(time_t *timer)
-#endif
-{
-#if DEVICE_RTC
-    if (!(rtc_isenabled())) {
-        set_time(0);
-    }
-    time_t t = rtc_read();
-
-#else
-    time_t t = 0;
-#endif
-
-    if (timer != NULL) {
-        *timer = t;
-    }
-    return t;
-}
-
-void set_time(time_t t) {
-#if DEVICE_RTC
-    rtc_init();
-    rtc_write(t);
-#endif
-}
-
-clock_t clock() {
-    clock_t t = us_ticker_read();
-    t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
-    return t;
-}
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "rtc_api.h"
+
+#include <time.h>
+#include "rtc_time.h"
+#include "us_ticker_api.h"
+
+#if defined (__ICCARM__)
+time_t __time32(time_t *timer)
+#else
+time_t time(time_t *timer)
+#endif
+{
+#if DEVICE_RTC
+    if (!(rtc_isenabled())) {
+        set_time(0);
+    }
+    time_t t = rtc_read();
+
+#else
+    time_t t = 0;
+#endif
+
+    if (timer != NULL) {
+        *timer = t;
+    }
+    return t;
+}
+
+void set_time(time_t t) {
+#if DEVICE_RTC
+    rtc_init();
+    rtc_write(t);
+#endif
+}
+
+clock_t clock() {
+    clock_t t = us_ticker_read();
+    t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
+    return t;
+}

--- a/common/stdio.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,381 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "platform.h"
-#include "FileHandle.h"
-#include "FileSystemLike.h"
-#include "FilePath.h"
-#include "serial_api.h"
-#include <errno.h>
-
-#if defined(__ARMCC_VERSION)
-#   include <rt_sys.h>
-#   define PREFIX(x)    _sys##x
-#   define OPEN_MAX     _SYS_OPEN
-#   ifdef __MICROLIB
-#       pragma import(__use_full_stdio)
-#   endif
-
-#elif defined(__ICCARM__)
-#   include <yfuns.h>
-#   define PREFIX(x)        _##x
-#   define OPEN_MAX         16
-
-#   define STDIN_FILENO     0
-#   define STDOUT_FILENO    1
-#   define STDERR_FILENO    2
-
-#else
-#   include <sys/stat.h>
-#   include <sys/unistd.h>
-#   include <sys/syslimits.h>
-#   define PREFIX(x)    x
-#endif
-
-using namespace mbed;
-
-#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
-// Before version 5.03, we were using a patched version of microlib with proper names
-extern const char __stdin_name[]  = ":tt";
-extern const char __stdout_name[] = ":tt";
-extern const char __stderr_name[] = ":tt";
-
-#else
-extern const char __stdin_name[]  = "/stdin";
-extern const char __stdout_name[] = "/stdout";
-extern const char __stderr_name[] = "/stderr";
-#endif
-
-/* newlib has the filehandle field in the FILE struct as a short, so
- * we can't just return a Filehandle* from _open and instead have to
- * put it in a filehandles array and return the index into that array
- * (or rather index+3, as filehandles 0-2 are stdin/out/err).
- */
-static FileHandle *filehandles[OPEN_MAX];
-
-FileHandle::~FileHandle() {
-    /* Remove all open filehandles for this */
-    for (unsigned int fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
-        if (filehandles[fh_i] == this) {
-            filehandles[fh_i] = NULL;
-        }
-    }
-}
-
-#if DEVICE_SERIAL
-extern int stdio_uart_inited;
-extern serial_t stdio_uart;
-#endif
-
-static void init_serial() {
-#if DEVICE_SERIAL
-    if (stdio_uart_inited) return;
-    serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
-#endif
-}
-
-static inline int openmode_to_posix(int openmode) {
-    int posix = openmode;
-#ifdef __ARMCC_VERSION
-    if (openmode & OPEN_PLUS) {
-        posix = O_RDWR;
-    } else if(openmode & OPEN_W) {
-        posix = O_WRONLY;
-    } else if(openmode & OPEN_A) {
-        posix = O_WRONLY|O_APPEND;
-    } else {
-        posix = O_RDONLY;
-    }
-    /* a, w, a+, w+ all create if file does not already exist */
-    if (openmode & (OPEN_A|OPEN_W)) {
-        posix |= O_CREAT;
-    }
-    /* w and w+ truncate */
-    if (openmode & OPEN_W) {
-        posix |= O_TRUNC;
-    }
-#elif defined(__ICCARM__)
-    switch (openmode & _LLIO_RDWRMASK) {
-        case _LLIO_RDONLY: posix = O_RDONLY; break;
-        case _LLIO_WRONLY: posix = O_WRONLY; break;
-        case _LLIO_RDWR  : posix = O_RDWR  ; break;
-    }
-    if (openmode & _LLIO_CREAT ) posix |= O_CREAT;
-    if (openmode & _LLIO_APPEND) posix |= O_APPEND;
-    if (openmode & _LLIO_TRUNC ) posix |= O_TRUNC;
-#endif
-    return posix;
-}
-
-extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
-    /* Use the posix convention that stdin,out,err are filehandles 0,1,2.
-     */
-    if (std::strcmp(name, __stdin_name) == 0) {
-        init_serial();
-        return 0;
-    } else if (std::strcmp(name, __stdout_name) == 0) {
-        init_serial();
-        return 1;
-    } else if (std::strcmp(name, __stderr_name) == 0) {
-        init_serial();
-        return 2;
-    }
-
-    // find the first empty slot in filehandles
-    unsigned int fh_i;
-    for (fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
-        if (filehandles[fh_i] == NULL) break;
-    }
-    if (fh_i >= sizeof(filehandles)/sizeof(*filehandles)) {
-        return -1;
-    }
-
-    FileHandle *res;
-
-    /* FILENAME: ":0x12345678" describes a FileLike* */
-    if (name[0] == ':') {
-        void *p;
-        sscanf(name, ":%p", &p);
-        res = (FileHandle*)p;
-
-    /* FILENAME: "/file_system/file_name" */
-    } else {
-        FilePath path(name);
-
-        if (path.isFile()) {
-            res = path.file();
-        } else {
-            FileSystemLike *fs = path.fileSystem();
-            if (fs == NULL) return -1;
-            int posix_mode = openmode_to_posix(openmode);
-            res = fs->open(path.fileName(), posix_mode); /* NULL if fails */
-        }
-    }
-
-    if (res == NULL) return -1;
-    filehandles[fh_i] = res;
-
-    return fh_i + 3; // +3 as filehandles 0-2 are stdin/out/err
-}
-
-extern "C" int PREFIX(_close)(FILEHANDLE fh) {
-    if (fh < 3) return 0;
-
-    FileHandle* fhc = filehandles[fh-3];
-    filehandles[fh-3] = NULL;
-    if (fhc == NULL) return -1;
-
-    return fhc->close();
-}
-
-#if defined(__ICCARM__)
-extern "C" size_t    __write (int        fh, const unsigned char *buffer, size_t length) {
-#else
-extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode) {
-#endif
-    int n; // n is the number of bytes written
-    if (fh < 3) {
-#if DEVICE_SERIAL
-        if (!stdio_uart_inited) init_serial();
-        for (unsigned int i = 0; i < length; i++) {
-            serial_putc(&stdio_uart, buffer[i]);
-        }
-#endif
-        n = length;
-    } else {
-        FileHandle* fhc = filehandles[fh-3];
-        if (fhc == NULL) return -1;
-
-        n = fhc->write(buffer, length);
-    }
-#ifdef __ARMCC_VERSION
-    return length-n;
-#else
-    return n;
-#endif
-}
-
-#if defined(__ICCARM__)
-extern "C" size_t    __read (int        fh, unsigned char *buffer, size_t       length) {
-#else
-extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode) {
-#endif
-    int n; // n is the number of bytes read
-    if (fh < 3) {
-        // only read a character at a time from stdin
-#if DEVICE_SERIAL
-        *buffer = serial_getc(&stdio_uart);
-#endif
-        n = 1;
-    } else {
-        FileHandle* fhc = filehandles[fh-3];
-        if (fhc == NULL) return -1;
-
-        n = fhc->read(buffer, length);
-    }
-#ifdef __ARMCC_VERSION
-    return length-n;
-#else
-    return n;
-#endif
-}
-
-#ifdef __ARMCC_VERSION
-extern "C" int PREFIX(_istty)(FILEHANDLE fh)
-#else
-extern "C" int _isatty(FILEHANDLE fh)
-#endif
-{
-    /* stdin, stdout and stderr should be tty */
-    if (fh < 3) return 1;
-
-    FileHandle* fhc = filehandles[fh-3];
-    if (fhc == NULL) return -1;
-
-    return fhc->isatty();
-}
-
-extern "C"
-#if defined(__ARMCC_VERSION)
-int _sys_seek(FILEHANDLE fh, long position)
-#elif defined(__ICCARM__)
-long __lseek(int fh, long offset, int whence)
-#else
-int _lseek(FILEHANDLE fh, int offset, int whence)
-#endif
-{
-    if (fh < 3) return 0;
-
-    FileHandle* fhc = filehandles[fh-3];
-    if (fhc == NULL) return -1;
-
-#if defined(__ARMCC_VERSION)
-    return fhc->lseek(position, SEEK_SET);
-#else
-    return fhc->lseek(offset, whence);
-#endif
-}
-
-#ifdef __ARMCC_VERSION
-extern "C" int PREFIX(_ensure)(FILEHANDLE fh) {
-    if (fh < 3) return 0;
-
-    FileHandle* fhc = filehandles[fh-3];
-    if (fhc == NULL) return -1;
-
-    return fhc->fsync();
-}
-
-extern "C" long PREFIX(_flen)(FILEHANDLE fh) {
-    if (fh < 3) return 0;
-
-    FileHandle* fhc = filehandles[fh-3];
-    if (fhc == NULL) return -1;
-
-    return fhc->flen();
-}
-#endif
-
-
-#if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
-extern "C" int _fstat(int fd, struct stat *st) {
-    if ((STDOUT_FILENO == fd) || (STDERR_FILENO == fd) || (STDIN_FILENO == fd)) {
-        st->st_mode = S_IFCHR;
-        return  0;
-    }
-
-    errno = EBADF;
-    return -1;
-}
-#endif
-
-namespace std {
-extern "C" int remove(const char *path) {
-    FilePath fp(path);
-    FileSystemLike *fs = fp.fileSystem();
-    if (fs == NULL) return -1;
-
-    return fs->remove(fp.fileName());
-}
-
-extern "C" int rename(const char *oldname, const char *newname) {
-    return -1;
-}
-
-extern "C" char *tmpnam(char *s) {
-    return NULL;
-}
-
-extern "C" FILE *tmpfile() {
-    return NULL;
-}
-} // namespace std
-
-#ifdef __ARMCC_VERSION
-extern "C" char *_sys_command_string(char *cmd, int len) {
-    return NULL;
-}
-#endif
-
-extern "C" DIR *opendir(const char *path) {
-    /* root dir is FileSystemLike */
-    if (path[0] == '/' && path[1] == 0) {
-        return FileSystemLike::opendir();
-    }
-
-    FilePath fp(path);
-    FileSystemLike* fs = fp.fileSystem();
-    if (fs == NULL) return NULL;
-
-    return fs->opendir(fp.fileName());
-}
-
-extern "C" struct dirent *readdir(DIR *dir) {
-    return dir->readdir();
-}
-
-extern "C" int closedir(DIR *dir) {
-    return dir->closedir();
-}
-
-extern "C" void rewinddir(DIR *dir) {
-    dir->rewinddir();
-}
-
-extern "C" off_t telldir(DIR *dir) {
-    return dir->telldir();
-}
-
-extern "C" void seekdir(DIR *dir, off_t off) {
-    dir->seekdir(off);
-}
-
-extern "C" int mkdir(const char *path, mode_t mode) {
-    FilePath fp(path);
-    FileSystemLike *fs = fp.fileSystem();
-    if (fs == NULL) return -1;
-
-    return fs->mkdir(fp.fileName(), mode);
-}
-
-#if defined(TOOLCHAIN_GCC_CR) || defined(TOOLCHAIN_GCC_CS) || defined(TOOLCHAIN_GCC_ARM)
-/* prevents the exception handling name demangling code getting pulled in */
-#include "error.h"
-namespace __gnu_cxx {
-    void __verbose_terminate_handler() {
-        error("Exception");
-    }
-}
-#endif

--- a/common/wait_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ b/common/wait_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -1,30 +1,30 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "wait_api.h"
-#include "us_ticker_api.h"
-
-void wait(float s) {
-    wait_us(s * 1000000.0f);
-}
-
-void wait_ms(int ms) {
-    wait_us(ms * 1000);
-}
-
-void wait_us(int us) {
-    uint32_t start = us_ticker_read();
-    while ((us_ticker_read() - start) < us);
-}
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "wait_api.h"
+#include "us_ticker_api.h"
+
+void wait(float s) {
+    wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms) {
+    wait_us(ms * 1000);
+}
+
+void wait_us(int us) {
+    uint32_t start = us_ticker_read();
+    while ((us_ticker_read() - start) < us);
+}

--- a/hal/analogin_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/analogin_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,39 +1,39 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGIN_API_H
-#define MBED_ANALOGIN_API_H
-
-#include "device.h"
-
-#if DEVICE_ANALOGIN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct analogin_s analogin_t;
-
-void     analogin_init    (analogin_t *obj, PinName pin);
-float    analogin_read    (analogin_t *obj);
-uint16_t analogin_read_u16(analogin_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_API_H
+#define MBED_ANALOGIN_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct analogin_s analogin_t;
+
+void     analogin_init    (analogin_t *obj, PinName pin);
+float    analogin_read    (analogin_t *obj);
+uint16_t analogin_read_u16(analogin_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- a/hal/analogout_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/analogout_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,42 +1,42 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGOUT_API_H
-#define MBED_ANALOGOUT_API_H
-
-#include "device.h"
-
-#if DEVICE_ANALOGOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct dac_s dac_t;
-
-void     analogout_init     (dac_t *obj, PinName pin);
-void     analogout_free     (dac_t *obj);
-void     analogout_write    (dac_t *obj, float value);
-void     analogout_write_u16(dac_t *obj, uint16_t value);
-float    analogout_read     (dac_t *obj);
-uint16_t analogout_read_u16 (dac_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_API_H
+#define MBED_ANALOGOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct dac_s dac_t;
+
+void     analogout_init     (dac_t *obj, PinName pin);
+void     analogout_free     (dac_t *obj);
+void     analogout_write    (dac_t *obj, float value);
+void     analogout_write_u16(dac_t *obj, uint16_t value);
+float    analogout_read     (dac_t *obj);
+uint16_t analogout_read_u16 (dac_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- a/hal/can_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/can_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,49 +1,49 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_API_H
-#define MBED_CAN_API_H
-
-#include "device.h"
-
-#if DEVICE_CAN
-
-#include "PinNames.h"
-#include "PeripheralNames.h"
-#include "can_helper.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct can_s can_t;
-
-void          can_init     (can_t *obj, PinName rd, PinName td);
-void          can_free     (can_t *obj);
-int           can_frequency(can_t *obj, int hz);
-int           can_write    (can_t *obj, CAN_Message, int cc);
-int           can_read     (can_t *obj, CAN_Message *msg);
-void          can_reset    (can_t *obj);
-unsigned char can_rderror  (can_t *obj);
-unsigned char can_tderror  (can_t *obj);
-void          can_monitor  (can_t *obj, int silent);
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif    // MBED_CAN_API_H
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_API_H
+#define MBED_CAN_API_H
+
+#include "device.h"
+
+#if DEVICE_CAN
+
+#include "PinNames.h"
+#include "PeripheralNames.h"
+#include "can_helper.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct can_s can_t;
+
+void          can_init     (can_t *obj, PinName rd, PinName td);
+void          can_free     (can_t *obj);
+int           can_frequency(can_t *obj, int hz);
+int           can_write    (can_t *obj, CAN_Message, int cc);
+int           can_read     (can_t *obj, CAN_Message *msg);
+void          can_reset    (can_t *obj);
+unsigned char can_rderror  (can_t *obj);
+unsigned char can_tderror  (can_t *obj);
+void          can_monitor  (can_t *obj, int silent);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif    // MBED_CAN_API_H
+
+#endif

--- a/hal/ethernet_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/ethernet_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,63 +1,63 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ETHERNET_API_H
-#define MBED_ETHERNET_API_H
-
-#include "device.h"
-
-#if DEVICE_ETHERNET
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// Connection constants
-
-int ethernet_init(void);
-void ethernet_free(void);
-
-// write size bytes from data to ethernet buffer
-// return num bytes written
-// or -1 if size is too big
-int ethernet_write(const char *data, int size);
-
-// send ethernet write buffer, returning the packet size sent
-int ethernet_send(void);
-
-// recieve from ethernet buffer, returning packet size, or 0 if no packet
-int ethernet_receive(void);
-
-// read size bytes in to data, return actual num bytes read (0..size)
-// if data == NULL, throw the bytes away
-int ethernet_read(char *data, int size);
-
-// get the ethernet address
-void ethernet_address(char *mac);
-
-// see if the link is up
-int ethernet_link(void);
-
-// force link settings
-void ethernet_set_link(int speed, int duplex);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_API_H
+#define MBED_ETHERNET_API_H
+
+#include "device.h"
+
+#if DEVICE_ETHERNET
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Connection constants
+
+int ethernet_init(void);
+void ethernet_free(void);
+
+// write size bytes from data to ethernet buffer
+// return num bytes written
+// or -1 if size is too big
+int ethernet_write(const char *data, int size);
+
+// send ethernet write buffer, returning the packet size sent
+int ethernet_send(void);
+
+// recieve from ethernet buffer, returning packet size, or 0 if no packet
+int ethernet_receive(void);
+
+// read size bytes in to data, return actual num bytes read (0..size)
+// if data == NULL, throw the bytes away
+int ethernet_read(char *data, int size);
+
+// get the ethernet address
+void ethernet_address(char *mac);
+
+// see if the link is up
+int ethernet_link(void);
+
+// force link settings
+void ethernet_set_link(int speed, int duplex);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+

--- a/hal/gpio_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/gpio_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,40 +1,44 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_API_H
-#define MBED_GPIO_API_H
-
-#include "device.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Set the given pin as GPIO
- * @param pin The pin to be set as GPIO
- * @return The GPIO port mask for this pin
- **/
-uint32_t gpio_set(PinName pin);
-
-/* GPIO object */
-void gpio_init(gpio_t *obj, PinName pin, PinDirection direction);
-void gpio_mode(gpio_t *obj, PinMode mode);
-void gpio_dir (gpio_t *obj, PinDirection direction);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_API_H
+#define MBED_GPIO_API_H
+
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Set the given pin as GPIO
+ * @param pin The pin to be set as GPIO
+ * @return The GPIO port mask for this pin
+ **/
+uint32_t gpio_set(PinName pin);
+
+/* GPIO object */
+void gpio_init (gpio_t *obj, PinName pin, PinDirection direction);
+
+void gpio_mode (gpio_t *obj, PinMode mode);
+void gpio_dir  (gpio_t *obj, PinDirection direction);
+
+void gpio_write(gpio_t *obj, int value);
+int  gpio_read (gpio_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/hal/gpio_irq_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/gpio_irq_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,47 +1,47 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_IRQ_API_H
-#define MBED_GPIO_IRQ_API_H
-
-#include "device.h"
-
-#if DEVICE_INTERRUPTIN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    IRQ_NONE,
-    IRQ_RISE,
-    IRQ_FALL
-} gpio_irq_event;
-
-typedef struct gpio_irq_s gpio_irq_t;
-
-typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
-
-int  gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
-void gpio_irq_free(gpio_irq_t *obj);
-void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_IRQ_API_H
+#define MBED_GPIO_IRQ_API_H
+
+#include "device.h"
+
+#if DEVICE_INTERRUPTIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    IRQ_NONE,
+    IRQ_RISE,
+    IRQ_FALL
+} gpio_irq_event;
+
+typedef struct gpio_irq_s gpio_irq_t;
+
+typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
+
+int  gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
+void gpio_irq_free(gpio_irq_t *obj);
+void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- a/hal/i2c_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/i2c_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,53 +1,58 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_API_H
-#define MBED_I2C_API_H
-
-#include "device.h"
-
-#if DEVICE_I2C
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct i2c_s i2c_t;
-
-void i2c_init         (i2c_t *obj, PinName sda, PinName scl);
-void i2c_frequency    (i2c_t *obj, int hz);
-int  i2c_start        (i2c_t *obj);
-void i2c_stop         (i2c_t *obj);
-int  i2c_read         (i2c_t *obj, int address, char *data, int length, int stop);
-int  i2c_write        (i2c_t *obj, int address, const char *data, int length, int stop);
-void i2c_reset        (i2c_t *obj);
-int  i2c_byte_read    (i2c_t *obj, int last);
-int  i2c_byte_write   (i2c_t *obj, int data);
-
-#if DEVICE_I2CSLAVE
-void i2c_slave_mode   (i2c_t *obj, int enable_slave);
-int  i2c_slave_receive(i2c_t *obj);
-int  i2c_slave_read   (i2c_t *obj, char *data, int length);
-int  i2c_slave_write  (i2c_t *obj, const char *data, int length);
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_API_H
+#define MBED_I2C_API_H
+
+#include "device.h"
+
+#if DEVICE_I2C
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct i2c_s i2c_t;
+
+enum {
+  I2C_ERROR_NO_SLAVE = -1,
+  I2C_ERROR_BUS_BUSY = -2
+};
+
+void i2c_init         (i2c_t *obj, PinName sda, PinName scl);
+void i2c_frequency    (i2c_t *obj, int hz);
+int  i2c_start        (i2c_t *obj);
+int  i2c_stop         (i2c_t *obj);
+int  i2c_read         (i2c_t *obj, int address, char *data, int length, int stop);
+int  i2c_write        (i2c_t *obj, int address, const char *data, int length, int stop);
+void i2c_reset        (i2c_t *obj);
+int  i2c_byte_read    (i2c_t *obj, int last);
+int  i2c_byte_write   (i2c_t *obj, int data);
+
+#if DEVICE_I2CSLAVE
+void i2c_slave_mode   (i2c_t *obj, int enable_slave);
+int  i2c_slave_receive(i2c_t *obj);
+int  i2c_slave_read   (i2c_t *obj, char *data, int length);
+int  i2c_slave_write  (i2c_t *obj, const char *data, int length);
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- a/hal/port_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/port_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,42 +1,42 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTMAP_H
-#define MBED_PORTMAP_H
-
-#include "device.h"
-
-#if DEVICE_PORTIN || DEVICE_PORTOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct port_s port_t;
-
-PinName port_pin(PortName port, int pin_n);
-
-void port_init (port_t *obj, PortName port, int mask, PinDirection dir);
-void port_mode (port_t *obj, PinMode mode);
-void port_dir  (port_t *obj, PinDirection dir);
-void port_write(port_t *obj, int value);
-int  port_read (port_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTMAP_H
+#define MBED_PORTMAP_H
+
+#include "device.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct port_s port_t;
+
+PinName port_pin(PortName port, int pin_n);
+
+void port_init (port_t *obj, PortName port, int mask, PinDirection dir);
+void port_mode (port_t *obj, PinMode mode);
+void port_dir  (port_t *obj, PinDirection dir);
+void port_write(port_t *obj, int value);
+int  port_read (port_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif

--- a/hal/pwmout_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/pwmout_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,49 +1,49 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PWMOUT_API_H
-#define MBED_PWMOUT_API_H
-
-#include "device.h"
-
-#if DEVICE_PWMOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct pwmout_s pwmout_t;
-
-void pwmout_init         (pwmout_t* obj, PinName pin);
-void pwmout_free         (pwmout_t* obj);
-
-void  pwmout_write       (pwmout_t* obj, float percent);
-float pwmout_read        (pwmout_t* obj);
-
-void pwmout_period       (pwmout_t* obj, float seconds);
-void pwmout_period_ms    (pwmout_t* obj, int ms);
-void pwmout_period_us    (pwmout_t* obj, int us);
-
-void pwmout_pulsewidth   (pwmout_t* obj, float seconds);
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms);
-void pwmout_pulsewidth_us(pwmout_t* obj, int us);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_API_H
+#define MBED_PWMOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_PWMOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct pwmout_s pwmout_t;
+
+void pwmout_init         (pwmout_t* obj, PinName pin);
+void pwmout_free         (pwmout_t* obj);
+
+void  pwmout_write       (pwmout_t* obj, float percent);
+float pwmout_read        (pwmout_t* obj);
+
+void pwmout_period       (pwmout_t* obj, float seconds);
+void pwmout_period_ms    (pwmout_t* obj, int ms);
+void pwmout_period_us    (pwmout_t* obj, int us);
+
+void pwmout_pulsewidth   (pwmout_t* obj, float seconds);
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms);
+void pwmout_pulsewidth_us(pwmout_t* obj, int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- a/hal/rtc_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/rtc_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,42 +1,42 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_RTC_API_H
-#define MBED_RTC_API_H
-
-#include "device.h"
-
-#if DEVICE_RTC
-
-#include <time.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void rtc_init(void);
-void rtc_free(void);
-int rtc_isenabled(void);
-
-time_t rtc_read(void);
-void rtc_write(time_t t);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RTC_API_H
+#define MBED_RTC_API_H
+
+#include "device.h"
+
+#if DEVICE_RTC
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void rtc_init(void);
+void rtc_free(void);
+int rtc_isenabled(void);
+
+time_t rtc_read(void);
+void rtc_write(time_t t);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- a/hal/serial_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/serial_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,66 +1,69 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIAL_API_H
-#define MBED_SERIAL_API_H
-
-#include "device.h"
-
-#if DEVICE_SERIAL
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ParityNone = 0,
-    ParityOdd = 1,
-    ParityEven = 2,
-    ParityForced1 = 3,
-    ParityForced0 = 4
-} SerialParity;
-
-typedef enum {
-    RxIrq,
-    TxIrq
-} SerialIrq;
-
-typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
-
-typedef struct serial_s serial_t;
-
-void serial_init       (serial_t *obj, PinName tx, PinName rx);
-void serial_free       (serial_t *obj);
-void serial_baud       (serial_t *obj, int baudrate);
-void serial_format     (serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
-void serial_irq_set    (serial_t *obj, SerialIrq irq, uint32_t enable);
-
-int  serial_getc       (serial_t *obj);
-void serial_putc       (serial_t *obj, int c);
-int  serial_readable   (serial_t *obj);
-int  serial_writable   (serial_t *obj);
-void serial_clear      (serial_t *obj);
-
-void serial_pinout_tx(PinName tx);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_API_H
+#define MBED_SERIAL_API_H
+
+#include "device.h"
+
+#if DEVICE_SERIAL
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ParityNone = 0,
+    ParityOdd = 1,
+    ParityEven = 2,
+    ParityForced1 = 3,
+    ParityForced0 = 4
+} SerialParity;
+
+typedef enum {
+    RxIrq,
+    TxIrq
+} SerialIrq;
+
+typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
+
+typedef struct serial_s serial_t;
+
+void serial_init       (serial_t *obj, PinName tx, PinName rx);
+void serial_free       (serial_t *obj);
+void serial_baud       (serial_t *obj, int baudrate);
+void serial_format     (serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
+void serial_irq_set    (serial_t *obj, SerialIrq irq, uint32_t enable);
+
+int  serial_getc       (serial_t *obj);
+void serial_putc       (serial_t *obj, int c);
+int  serial_readable   (serial_t *obj);
+int  serial_writable   (serial_t *obj);
+void serial_clear      (serial_t *obj);
+
+void serial_break_set  (serial_t *obj);
+void serial_break_clear(serial_t *obj);
+
+void serial_pinout_tx(PinName tx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- a/hal/sleep_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/sleep_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,64 +1,64 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SLEEP_API_H
-#define MBED_SLEEP_API_H
-
-#include "device.h"
-
-#if DEVICE_SLEEP
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Send the microcontroller to sleep
- *
- * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
- * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
- * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
- * memory state are maintained, and the peripherals continue to work and can generate interrupts.
- *
- * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
- *
- * @note
- *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
- */
-void sleep(void);
-
-/** Send the microcontroller to deep sleep
- *
- * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
- * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
- * is still maintained.
- *
- * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
- *
- * @note
- *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
- */
-void deepsleep(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SLEEP_API_H
+#define MBED_SLEEP_API_H
+
+#include "device.h"
+
+#if DEVICE_SLEEP
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Send the microcontroller to sleep
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void sleep(void);
+
+/** Send the microcontroller to deep sleep
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void deepsleep(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- a/hal/spi_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/spi_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,45 +1,45 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPI_API_H
-#define MBED_SPI_API_H
-
-#include "device.h"
-
-#if DEVICE_SPI
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct spi_s spi_t;
-
-void spi_init         (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
-void spi_free         (spi_t *obj);
-void spi_format       (spi_t *obj, int bits, int mode, int slave);
-void spi_frequency    (spi_t *obj, int hz);
-int  spi_master_write (spi_t *obj, int value);
-int  spi_slave_receive(spi_t *obj);
-int  spi_slave_read   (spi_t *obj);
-void spi_slave_write  (spi_t *obj, int value);
-int  spi_busy         (spi_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_API_H
+#define MBED_SPI_API_H
+
+#include "device.h"
+
+#if DEVICE_SPI
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct spi_s spi_t;
+
+void spi_init         (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
+void spi_free         (spi_t *obj);
+void spi_format       (spi_t *obj, int bits, int mode, int slave);
+void spi_frequency    (spi_t *obj, int hz);
+int  spi_master_write (spi_t *obj, int value);
+int  spi_slave_receive(spi_t *obj);
+int  spi_slave_read   (spi_t *obj);
+void spi_slave_write  (spi_t *obj, int value);
+int  spi_busy         (spi_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- a/hal/us_ticker_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ b/hal/us_ticker_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -1,49 +1,49 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_US_TICKER_API_H
-#define MBED_US_TICKER_API_H
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-uint32_t us_ticker_read(void);
-
-typedef void (*ticker_event_handler)(uint32_t id);
-void us_ticker_set_handler(ticker_event_handler handler);
-
-typedef struct ticker_event_s {
-    uint32_t timestamp;
-    uint32_t id;
-    struct ticker_event_s *next;
-} ticker_event_t;
-
-void us_ticker_init(void);
-void us_ticker_set_interrupt(unsigned int timestamp);
-void us_ticker_disable_interrupt(void);
-void us_ticker_clear_interrupt(void);
-void us_ticker_irq_handler(void);
-
-void us_ticker_insert_event(ticker_event_t *obj, unsigned int timestamp, uint32_t id);
-void us_ticker_remove_event(ticker_event_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_US_TICKER_API_H
+#define MBED_US_TICKER_API_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+uint32_t us_ticker_read(void);
+
+typedef void (*ticker_event_handler)(uint32_t id);
+void us_ticker_set_handler(ticker_event_handler handler);
+
+typedef struct ticker_event_s {
+    uint32_t timestamp;
+    uint32_t id;
+    struct ticker_event_s *next;
+} ticker_event_t;
+
+void us_ticker_init(void);
+void us_ticker_set_interrupt(unsigned int timestamp);
+void us_ticker_disable_interrupt(void);
+void us_ticker_clear_interrupt(void);
+void us_ticker_irq_handler(void);
+
+void us_ticker_insert_event(ticker_event_t *obj, unsigned int timestamp, uint32_t id);
+void us_ticker_remove_event(ticker_event_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/MKL25Z4.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,4155 @@
+/*
+** ###################################################################
+**     Processor:           MKL25Z128VLK4
+**     Compilers:           ARM Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL25RM, Rev.1, Jun 2012
+**     Version:             rev. 1.1, 2012-06-21
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MKL25Z4
+**
+**     Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2012-06-13)
+**         Initial version.
+**     - rev. 1.1 (2012-06-21)
+**         Update according to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL25Z4.h
+ * @version 1.1
+ * @date 2012-06-21
+ * @brief CMSIS Peripheral Access Layer for MKL25Z4
+ *
+ * CMSIS Peripheral Access Layer for MKL25Z4
+ */
+
+#if !defined(MKL25Z4_H_)
+#define MKL25Z4_H_                               /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0001u
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M0 SV Hard Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M0 SV Call Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M0 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M0 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_IRQn                    = 0,                /**< DMA channel 0 transfer complete interrupt */
+  DMA1_IRQn                    = 1,                /**< DMA channel 1 transfer complete interrupt */
+  DMA2_IRQn                    = 2,                /**< DMA channel 2 transfer complete interrupt */
+  DMA3_IRQn                    = 3,                /**< DMA channel 3 transfer complete interrupt */
+  Reserved20_IRQn              = 4,                /**< Reserved interrupt 20 */
+  FTFA_IRQn                    = 5,                /**< FTFA interrupt */
+  LVD_LVW_IRQn                 = 6,                /**< Low Voltage Detect, Low Voltage Warning */
+  LLW_IRQn                     = 7,                /**< Low Leakage Wakeup */
+  I2C0_IRQn                    = 8,                /**< I2C0 interrupt */
+  I2C1_IRQn                    = 9,                /**< I2C0 interrupt 25 */
+  SPI0_IRQn                    = 10,               /**< SPI0 interrupt */
+  SPI1_IRQn                    = 11,               /**< SPI1 interrupt */
+  UART0_IRQn                   = 12,               /**< UART0 status/error interrupt */
+  UART1_IRQn                   = 13,               /**< UART1 status/error interrupt */
+  UART2_IRQn                   = 14,               /**< UART2 status/error interrupt */
+  ADC0_IRQn                    = 15,               /**< ADC0 interrupt */
+  CMP0_IRQn                    = 16,               /**< CMP0 interrupt */
+  TPM0_IRQn                    = 17,               /**< TPM0 fault, overflow and channels interrupt */
+  TPM1_IRQn                    = 18,               /**< TPM1 fault, overflow and channels interrupt */
+  TPM2_IRQn                    = 19,               /**< TPM2 fault, overflow and channels interrupt */
+  RTC_IRQn                     = 20,               /**< RTC interrupt */
+  RTC_Seconds_IRQn             = 21,               /**< RTC seconds interrupt */
+  PIT_IRQn                     = 22,               /**< PIT timer interrupt */
+  Reserved39_IRQn              = 23,               /**< Reserved interrupt 39 */
+  USB0_IRQn                    = 24,               /**< USB0 interrupt */
+  DAC0_IRQn                    = 25,               /**< DAC interrupt */
+  TSI0_IRQn                    = 26,               /**< TSI0 interrupt */
+  MCG_IRQn                     = 27,               /**< MCG interrupt */
+  LPTimer_IRQn                 = 28,               /**< LPTimer interrupt */
+  Reserved45_IRQn              = 29,               /**< Reserved interrupt 45 */
+  PORTA_IRQn                   = 30,               /**< Port A interrupt */
+  PORTD_IRQn                   = 31                /**< Port D interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M0 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV                  0x0000    /**< Core revision r0p0 */
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT                 1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               2         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h"              /* Core Peripheral Access Layer */
+#include "system_MKL25Z4.h"            /* Device specific configuration file */
+
+/**
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK                        0x1Fu
+#define ADC_SC1_ADCH_SHIFT                       0
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK                        0x20u
+#define ADC_SC1_DIFF_SHIFT                       5
+#define ADC_SC1_AIEN_MASK                        0x40u
+#define ADC_SC1_AIEN_SHIFT                       6
+#define ADC_SC1_COCO_MASK                        0x80u
+#define ADC_SC1_COCO_SHIFT                       7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK                     0x3u
+#define ADC_CFG1_ADICLK_SHIFT                    0
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK                       0xCu
+#define ADC_CFG1_MODE_SHIFT                      2
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK                     0x10u
+#define ADC_CFG1_ADLSMP_SHIFT                    4
+#define ADC_CFG1_ADIV_MASK                       0x60u
+#define ADC_CFG1_ADIV_SHIFT                      5
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK                      0x80u
+#define ADC_CFG1_ADLPC_SHIFT                     7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK                     0x3u
+#define ADC_CFG2_ADLSTS_SHIFT                    0
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK                      0x4u
+#define ADC_CFG2_ADHSC_SHIFT                     2
+#define ADC_CFG2_ADACKEN_MASK                    0x8u
+#define ADC_CFG2_ADACKEN_SHIFT                   3
+#define ADC_CFG2_MUXSEL_MASK                     0x10u
+#define ADC_CFG2_MUXSEL_SHIFT                    4
+/* R Bit Fields */
+#define ADC_R_D_MASK                             0xFFFFu
+#define ADC_R_D_SHIFT                            0
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK                          0xFFFFu
+#define ADC_CV1_CV_SHIFT                         0
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK                          0xFFFFu
+#define ADC_CV2_CV_SHIFT                         0
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK                      0x3u
+#define ADC_SC2_REFSEL_SHIFT                     0
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK                       0x4u
+#define ADC_SC2_DMAEN_SHIFT                      2
+#define ADC_SC2_ACREN_MASK                       0x8u
+#define ADC_SC2_ACREN_SHIFT                      3
+#define ADC_SC2_ACFGT_MASK                       0x10u
+#define ADC_SC2_ACFGT_SHIFT                      4
+#define ADC_SC2_ACFE_MASK                        0x20u
+#define ADC_SC2_ACFE_SHIFT                       5
+#define ADC_SC2_ADTRG_MASK                       0x40u
+#define ADC_SC2_ADTRG_SHIFT                      6
+#define ADC_SC2_ADACT_MASK                       0x80u
+#define ADC_SC2_ADACT_SHIFT                      7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK                        0x3u
+#define ADC_SC3_AVGS_SHIFT                       0
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK                        0x4u
+#define ADC_SC3_AVGE_SHIFT                       2
+#define ADC_SC3_ADCO_MASK                        0x8u
+#define ADC_SC3_ADCO_SHIFT                       3
+#define ADC_SC3_CALF_MASK                        0x40u
+#define ADC_SC3_CALF_SHIFT                       6
+#define ADC_SC3_CAL_MASK                         0x80u
+#define ADC_SC3_CAL_SHIFT                        7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK                         0xFFFFu
+#define ADC_OFS_OFS_SHIFT                        0
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK                           0xFFFFu
+#define ADC_PG_PG_SHIFT                          0
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK                           0xFFFFu
+#define ADC_MG_MG_SHIFT                          0
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK                       0x3Fu
+#define ADC_CLPD_CLPD_SHIFT                      0
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK                       0x3Fu
+#define ADC_CLPS_CLPS_SHIFT                      0
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK                       0x3FFu
+#define ADC_CLP4_CLP4_SHIFT                      0
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK                       0x1FFu
+#define ADC_CLP3_CLP3_SHIFT                      0
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK                       0xFFu
+#define ADC_CLP2_CLP2_SHIFT                      0
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK                       0x7Fu
+#define ADC_CLP1_CLP1_SHIFT                      0
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK                       0x3Fu
+#define ADC_CLP0_CLP0_SHIFT                      0
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK                       0x3Fu
+#define ADC_CLMD_CLMD_SHIFT                      0
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK                       0x3Fu
+#define ADC_CLMS_CLMS_SHIFT                      0
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK                       0x3FFu
+#define ADC_CLM4_CLM4_SHIFT                      0
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK                       0x1FFu
+#define ADC_CLM3_CLM3_SHIFT                      0
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK                       0xFFu
+#define ADC_CLM2_CLM2_SHIFT                      0
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK                       0x7Fu
+#define ADC_CLM1_CLM1_SHIFT                      0
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK                       0x3Fu
+#define ADC_CLM0_CLM0_SHIFT                      0
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/**
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASES                                { ADC0 }
+
+/**
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK                     0x3u
+#define CMP_CR0_HYSTCTR_SHIFT                    0
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT                 4
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK                          0x1u
+#define CMP_CR1_EN_SHIFT                         0
+#define CMP_CR1_OPE_MASK                         0x2u
+#define CMP_CR1_OPE_SHIFT                        1
+#define CMP_CR1_COS_MASK                         0x4u
+#define CMP_CR1_COS_SHIFT                        2
+#define CMP_CR1_INV_MASK                         0x8u
+#define CMP_CR1_INV_SHIFT                        3
+#define CMP_CR1_PMODE_MASK                       0x10u
+#define CMP_CR1_PMODE_SHIFT                      4
+#define CMP_CR1_TRIGM_MASK                       0x20u
+#define CMP_CR1_TRIGM_SHIFT                      5
+#define CMP_CR1_WE_MASK                          0x40u
+#define CMP_CR1_WE_SHIFT                         6
+#define CMP_CR1_SE_MASK                          0x80u
+#define CMP_CR1_SE_SHIFT                         7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK                    0xFFu
+#define CMP_FPR_FILT_PER_SHIFT                   0
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK                        0x1u
+#define CMP_SCR_COUT_SHIFT                       0
+#define CMP_SCR_CFF_MASK                         0x2u
+#define CMP_SCR_CFF_SHIFT                        1
+#define CMP_SCR_CFR_MASK                         0x4u
+#define CMP_SCR_CFR_SHIFT                        2
+#define CMP_SCR_IEF_MASK                         0x8u
+#define CMP_SCR_IEF_SHIFT                        3
+#define CMP_SCR_IER_MASK                         0x10u
+#define CMP_SCR_IER_SHIFT                        4
+#define CMP_SCR_DMAEN_MASK                       0x40u
+#define CMP_SCR_DMAEN_SHIFT                      6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK                     0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT                    0
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK                     0x40u
+#define CMP_DACCR_VRSEL_SHIFT                    6
+#define CMP_DACCR_DACEN_MASK                     0x80u
+#define CMP_DACCR_DACEN_SHIFT                    7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK                      0x7u
+#define CMP_MUXCR_MSEL_SHIFT                     0
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      0x38u
+#define CMP_MUXCR_PSEL_SHIFT                     3
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK                      0x40u
+#define CMP_MUXCR_PSTM_SHIFT                     6
+
+/**
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASES                                { CMP0 }
+
+/**
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[2];
+       uint8_t RESERVED_0[28];
+  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK                      0xFFu
+#define DAC_DATL_DATA0_SHIFT                     0
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK                      0xFu
+#define DAC_DATH_DATA1_SHIFT                     0
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK                    0x1u
+#define DAC_SR_DACBFRPBF_SHIFT                   0
+#define DAC_SR_DACBFRPTF_MASK                    0x2u
+#define DAC_SR_DACBFRPTF_SHIFT                   1
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK                     0x1u
+#define DAC_C0_DACBBIEN_SHIFT                    0
+#define DAC_C0_DACBTIEN_MASK                     0x2u
+#define DAC_C0_DACBTIEN_SHIFT                    1
+#define DAC_C0_LPEN_MASK                         0x8u
+#define DAC_C0_LPEN_SHIFT                        3
+#define DAC_C0_DACSWTRG_MASK                     0x10u
+#define DAC_C0_DACSWTRG_SHIFT                    4
+#define DAC_C0_DACTRGSEL_MASK                    0x20u
+#define DAC_C0_DACTRGSEL_SHIFT                   5
+#define DAC_C0_DACRFS_MASK                       0x40u
+#define DAC_C0_DACRFS_SHIFT                      6
+#define DAC_C0_DACEN_MASK                        0x80u
+#define DAC_C0_DACEN_SHIFT                       7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK                      0x1u
+#define DAC_C1_DACBFEN_SHIFT                     0
+#define DAC_C1_DACBFMD_MASK                      0x4u
+#define DAC_C1_DACBFMD_SHIFT                     2
+#define DAC_C1_DMAEN_MASK                        0x80u
+#define DAC_C1_DMAEN_SHIFT                       7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK                      0x1u
+#define DAC_C2_DACBFUP_SHIFT                     0
+#define DAC_C2_DACBFRP_MASK                      0x10u
+#define DAC_C2_DACBFRP_SHIFT                     4
+
+/**
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASES                                { DAC0 }
+
+/**
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    __IO uint8_t REQC_ARR[4];                        /**< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 */
+  };
+       uint8_t RESERVED_0[252];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t SAR;                               /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+    __IO uint32_t DAR;                               /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+    union {                                          /* offset: 0x108, array step: 0x10 */
+      __IO uint32_t DSR_BCR;                           /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+      struct {                                         /* offset: 0x108, array step: 0x10 */
+             uint8_t RESERVED_0[3];
+        __IO uint8_t DSR;                                /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+      } DMA_DSR_ACCESS8BIT;
+    };
+    __IO uint32_t DCR;                               /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+  } DMA[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* REQC_ARR Bit Fields */
+#define DMA_REQC_ARR_DMAC_MASK                   0xFu
+#define DMA_REQC_ARR_DMAC_SHIFT                  0
+#define DMA_REQC_ARR_DMAC(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK)
+#define DMA_REQC_ARR_CFSM_MASK                   0x80u
+#define DMA_REQC_ARR_CFSM_SHIFT                  7
+/* SAR Bit Fields */
+#define DMA_SAR_SAR_MASK                         0xFFFFFFFFu
+#define DMA_SAR_SAR_SHIFT                        0
+#define DMA_SAR_SAR(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
+/* DAR Bit Fields */
+#define DMA_DAR_DAR_MASK                         0xFFFFFFFFu
+#define DMA_DAR_DAR_SHIFT                        0
+#define DMA_DAR_DAR(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
+/* DSR_BCR Bit Fields */
+#define DMA_DSR_BCR_BCR_MASK                     0xFFFFFFu
+#define DMA_DSR_BCR_BCR_SHIFT                    0
+#define DMA_DSR_BCR_BCR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
+#define DMA_DSR_BCR_DONE_MASK                    0x1000000u
+#define DMA_DSR_BCR_DONE_SHIFT                   24
+#define DMA_DSR_BCR_BSY_MASK                     0x2000000u
+#define DMA_DSR_BCR_BSY_SHIFT                    25
+#define DMA_DSR_BCR_REQ_MASK                     0x4000000u
+#define DMA_DSR_BCR_REQ_SHIFT                    26
+#define DMA_DSR_BCR_BED_MASK                     0x10000000u
+#define DMA_DSR_BCR_BED_SHIFT                    28
+#define DMA_DSR_BCR_BES_MASK                     0x20000000u
+#define DMA_DSR_BCR_BES_SHIFT                    29
+#define DMA_DSR_BCR_CE_MASK                      0x40000000u
+#define DMA_DSR_BCR_CE_SHIFT                     30
+/* DCR Bit Fields */
+#define DMA_DCR_LCH2_MASK                        0x3u
+#define DMA_DCR_LCH2_SHIFT                       0
+#define DMA_DCR_LCH2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
+#define DMA_DCR_LCH1_MASK                        0xCu
+#define DMA_DCR_LCH1_SHIFT                       2
+#define DMA_DCR_LCH1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
+#define DMA_DCR_LINKCC_MASK                      0x30u
+#define DMA_DCR_LINKCC_SHIFT                     4
+#define DMA_DCR_LINKCC(x)                        (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
+#define DMA_DCR_D_REQ_MASK                       0x80u
+#define DMA_DCR_D_REQ_SHIFT                      7
+#define DMA_DCR_DMOD_MASK                        0xF00u
+#define DMA_DCR_DMOD_SHIFT                       8
+#define DMA_DCR_DMOD(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
+#define DMA_DCR_SMOD_MASK                        0xF000u
+#define DMA_DCR_SMOD_SHIFT                       12
+#define DMA_DCR_SMOD(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
+#define DMA_DCR_START_MASK                       0x10000u
+#define DMA_DCR_START_SHIFT                      16
+#define DMA_DCR_DSIZE_MASK                       0x60000u
+#define DMA_DCR_DSIZE_SHIFT                      17
+#define DMA_DCR_DSIZE(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
+#define DMA_DCR_DINC_MASK                        0x80000u
+#define DMA_DCR_DINC_SHIFT                       19
+#define DMA_DCR_SSIZE_MASK                       0x300000u
+#define DMA_DCR_SSIZE_SHIFT                      20
+#define DMA_DCR_SSIZE(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
+#define DMA_DCR_SINC_MASK                        0x400000u
+#define DMA_DCR_SINC_SHIFT                       22
+#define DMA_DCR_EADREQ_MASK                      0x800000u
+#define DMA_DCR_EADREQ_SHIFT                     23
+#define DMA_DCR_AA_MASK                          0x10000000u
+#define DMA_DCR_AA_SHIFT                         28
+#define DMA_DCR_CS_MASK                          0x20000000u
+#define DMA_DCR_CS_SHIFT                         29
+#define DMA_DCR_ERQ_MASK                         0x40000000u
+#define DMA_DCR_ERQ_SHIFT                        30
+#define DMA_DCR_EINT_MASK                        0x80000000u
+#define DMA_DCR_EINT_SHIFT                       31
+
+/**
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0                                     ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASES                                { DMA0 }
+
+/**
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[4];                           /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT                0
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT                  6
+#define DMAMUX_CHCFG_ENBL_MASK                   0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT                  7
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE                             (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0                                  ((DMAMUX_Type *)DMAMUX0_BASE)
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASES                             { DMAMUX0 }
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FGPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FGPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define FGPIO_PDOR_PDO_MASK                      0xFFFFFFFFu
+#define FGPIO_PDOR_PDO_SHIFT                     0
+#define FGPIO_PDOR_PDO(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define FGPIO_PSOR_PTSO_MASK                     0xFFFFFFFFu
+#define FGPIO_PSOR_PTSO_SHIFT                    0
+#define FGPIO_PSOR_PTSO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define FGPIO_PCOR_PTCO_MASK                     0xFFFFFFFFu
+#define FGPIO_PCOR_PTCO_SHIFT                    0
+#define FGPIO_PCOR_PTCO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define FGPIO_PTOR_PTTO_MASK                     0xFFFFFFFFu
+#define FGPIO_PTOR_PTTO_SHIFT                    0
+#define FGPIO_PTOR_PTTO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define FGPIO_PDIR_PDI_MASK                      0xFFFFFFFFu
+#define FGPIO_PDIR_PDI_SHIFT                     0
+#define FGPIO_PDIR_PDI(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define FGPIO_PDDR_PDD_MASK                      0xFFFFFFFFu
+#define FGPIO_PDDR_PDD_SHIFT                     0
+#define FGPIO_PDDR_PDD(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FPTA base address */
+#define FPTA_BASE                                (0xF80FF000u)
+/** Peripheral FPTA base pointer */
+#define FPTA                                     ((FGPIO_Type *)FPTA_BASE)
+/** Peripheral FPTB base address */
+#define FPTB_BASE                                (0xF80FF040u)
+/** Peripheral FPTB base pointer */
+#define FPTB                                     ((FGPIO_Type *)FPTB_BASE)
+/** Peripheral FPTC base address */
+#define FPTC_BASE                                (0xF80FF080u)
+/** Peripheral FPTC base pointer */
+#define FPTC                                     ((FGPIO_Type *)FPTC_BASE)
+/** Peripheral FPTD base address */
+#define FPTD_BASE                                (0xF80FF0C0u)
+/** Peripheral FPTD base pointer */
+#define FPTD                                     ((FGPIO_Type *)FPTD_BASE)
+/** Peripheral FPTE base address */
+#define FPTE_BASE                                (0xF80FF100u)
+/** Peripheral FPTE base pointer */
+#define FPTE                                     ((FGPIO_Type *)FPTE_BASE)
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASES                              { FPTA, FPTB, FPTC, FPTD, FPTE }
+
+/**
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FTFA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFA_FSTAT_MGSTAT0_MASK                  0x1u
+#define FTFA_FSTAT_MGSTAT0_SHIFT                 0
+#define FTFA_FSTAT_FPVIOL_MASK                   0x10u
+#define FTFA_FSTAT_FPVIOL_SHIFT                  4
+#define FTFA_FSTAT_ACCERR_MASK                   0x20u
+#define FTFA_FSTAT_ACCERR_SHIFT                  5
+#define FTFA_FSTAT_RDCOLERR_MASK                 0x40u
+#define FTFA_FSTAT_RDCOLERR_SHIFT                6
+#define FTFA_FSTAT_CCIF_MASK                     0x80u
+#define FTFA_FSTAT_CCIF_SHIFT                    7
+/* FCNFG Bit Fields */
+#define FTFA_FCNFG_ERSSUSP_MASK                  0x10u
+#define FTFA_FCNFG_ERSSUSP_SHIFT                 4
+#define FTFA_FCNFG_ERSAREQ_MASK                  0x20u
+#define FTFA_FCNFG_ERSAREQ_SHIFT                 5
+#define FTFA_FCNFG_RDCOLLIE_MASK                 0x40u
+#define FTFA_FCNFG_RDCOLLIE_SHIFT                6
+#define FTFA_FCNFG_CCIE_MASK                     0x80u
+#define FTFA_FCNFG_CCIE_SHIFT                    7
+/* FSEC Bit Fields */
+#define FTFA_FSEC_SEC_MASK                       0x3u
+#define FTFA_FSEC_SEC_SHIFT                      0
+#define FTFA_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK                    0xCu
+#define FTFA_FSEC_FSLACC_SHIFT                   2
+#define FTFA_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK                      0x30u
+#define FTFA_FSEC_MEEN_SHIFT                     4
+#define FTFA_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK                     0xC0u
+#define FTFA_FSEC_KEYEN_SHIFT                    6
+#define FTFA_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFA_FOPT_OPT_MASK                       0xFFu
+#define FTFA_FOPT_OPT_SHIFT                      0
+#define FTFA_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFA_FCCOB3_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB3_CCOBn_SHIFT                  0
+#define FTFA_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFA_FCCOB2_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB2_CCOBn_SHIFT                  0
+#define FTFA_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFA_FCCOB1_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB1_CCOBn_SHIFT                  0
+#define FTFA_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFA_FCCOB0_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB0_CCOBn_SHIFT                  0
+#define FTFA_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFA_FCCOB7_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB7_CCOBn_SHIFT                  0
+#define FTFA_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFA_FCCOB6_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB6_CCOBn_SHIFT                  0
+#define FTFA_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFA_FCCOB5_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB5_CCOBn_SHIFT                  0
+#define FTFA_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFA_FCCOB4_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB4_CCOBn_SHIFT                  0
+#define FTFA_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFA_FCCOBB_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOBB_CCOBn_SHIFT                  0
+#define FTFA_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFA_FCCOBA_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOBA_CCOBn_SHIFT                  0
+#define FTFA_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFA_FCCOB9_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB9_CCOBn_SHIFT                  0
+#define FTFA_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFA_FCCOB8_CCOBn_MASK                   0xFFu
+#define FTFA_FCCOB8_CCOBn_SHIFT                  0
+#define FTFA_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFA_FPROT3_PROT_MASK                    0xFFu
+#define FTFA_FPROT3_PROT_SHIFT                   0
+#define FTFA_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFA_FPROT2_PROT_MASK                    0xFFu
+#define FTFA_FPROT2_PROT_SHIFT                   0
+#define FTFA_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFA_FPROT1_PROT_MASK                    0xFFu
+#define FTFA_FPROT1_PROT_SHIFT                   0
+#define FTFA_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFA_FPROT0_PROT_MASK                    0xFFu
+#define FTFA_FPROT0_PROT_SHIFT                   0
+#define FTFA_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
+
+/**
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE                                (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA                                     ((FTFA_Type *)FTFA_BASE)
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASES                               { FTFA }
+
+/**
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT                      0
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT                     0
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT                     0
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT                     0
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT                      0
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT                      0
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE                                 (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA                                      ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE                                 (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB                                      ((GPIO_Type *)PTB_BASE)
+/** Peripheral PTC base address */
+#define PTC_BASE                                 (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC                                      ((GPIO_Type *)PTC_BASE)
+/** Peripheral PTD base address */
+#define PTD_BASE                                 (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD                                      ((GPIO_Type *)PTD_BASE)
+/** Peripheral PTE base address */
+#define PTE_BASE                                 (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE                                      ((GPIO_Type *)PTE_BASE)
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASES                               { PTA, PTB, PTC, PTD, PTE }
+
+/**
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK                           0xFEu
+#define I2C_A1_AD_SHIFT                          1
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK                           0x3Fu
+#define I2C_F_ICR_SHIFT                          0
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          0xC0u
+#define I2C_F_MULT_SHIFT                         6
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK                        0x1u
+#define I2C_C1_DMAEN_SHIFT                       0
+#define I2C_C1_WUEN_MASK                         0x2u
+#define I2C_C1_WUEN_SHIFT                        1
+#define I2C_C1_RSTA_MASK                         0x4u
+#define I2C_C1_RSTA_SHIFT                        2
+#define I2C_C1_TXAK_MASK                         0x8u
+#define I2C_C1_TXAK_SHIFT                        3
+#define I2C_C1_TX_MASK                           0x10u
+#define I2C_C1_TX_SHIFT                          4
+#define I2C_C1_MST_MASK                          0x20u
+#define I2C_C1_MST_SHIFT                         5
+#define I2C_C1_IICIE_MASK                        0x40u
+#define I2C_C1_IICIE_SHIFT                       6
+#define I2C_C1_IICEN_MASK                        0x80u
+#define I2C_C1_IICEN_SHIFT                       7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK                          0x1u
+#define I2C_S_RXAK_SHIFT                         0
+#define I2C_S_IICIF_MASK                         0x2u
+#define I2C_S_IICIF_SHIFT                        1
+#define I2C_S_SRW_MASK                           0x4u
+#define I2C_S_SRW_SHIFT                          2
+#define I2C_S_RAM_MASK                           0x8u
+#define I2C_S_RAM_SHIFT                          3
+#define I2C_S_ARBL_MASK                          0x10u
+#define I2C_S_ARBL_SHIFT                         4
+#define I2C_S_BUSY_MASK                          0x20u
+#define I2C_S_BUSY_SHIFT                         5
+#define I2C_S_IAAS_MASK                          0x40u
+#define I2C_S_IAAS_SHIFT                         6
+#define I2C_S_TCF_MASK                           0x80u
+#define I2C_S_TCF_SHIFT                          7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK                          0xFFu
+#define I2C_D_DATA_SHIFT                         0
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK                           0x7u
+#define I2C_C2_AD_SHIFT                          0
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         0x8u
+#define I2C_C2_RMEN_SHIFT                        3
+#define I2C_C2_SBRC_MASK                         0x10u
+#define I2C_C2_SBRC_SHIFT                        4
+#define I2C_C2_HDRS_MASK                         0x20u
+#define I2C_C2_HDRS_SHIFT                        5
+#define I2C_C2_ADEXT_MASK                        0x40u
+#define I2C_C2_ADEXT_SHIFT                       6
+#define I2C_C2_GCAEN_MASK                        0x80u
+#define I2C_C2_GCAEN_SHIFT                       7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK                         0x1Fu
+#define I2C_FLT_FLT_SHIFT                        0
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STOPIE_MASK                      0x20u
+#define I2C_FLT_STOPIE_SHIFT                     5
+#define I2C_FLT_STOPF_MASK                       0x40u
+#define I2C_FLT_STOPF_SHIFT                      6
+#define I2C_FLT_SHEN_MASK                        0x80u
+#define I2C_FLT_SHEN_SHIFT                       7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK                          0xFEu
+#define I2C_RA_RAD_SHIFT                         1
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK                     0x1u
+#define I2C_SMB_SHTF2IE_SHIFT                    0
+#define I2C_SMB_SHTF2_MASK                       0x2u
+#define I2C_SMB_SHTF2_SHIFT                      1
+#define I2C_SMB_SHTF1_MASK                       0x4u
+#define I2C_SMB_SHTF1_SHIFT                      2
+#define I2C_SMB_SLTF_MASK                        0x8u
+#define I2C_SMB_SLTF_SHIFT                       3
+#define I2C_SMB_TCKSEL_MASK                      0x10u
+#define I2C_SMB_TCKSEL_SHIFT                     4
+#define I2C_SMB_SIICAEN_MASK                     0x20u
+#define I2C_SMB_SIICAEN_SHIFT                    5
+#define I2C_SMB_ALERTEN_MASK                     0x40u
+#define I2C_SMB_ALERTEN_SHIFT                    6
+#define I2C_SMB_FACK_MASK                        0x80u
+#define I2C_SMB_FACK_SHIFT                       7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK                          0xFEu
+#define I2C_A2_SAD_SHIFT                         1
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK                       0xFFu
+#define I2C_SLTH_SSLT_SHIFT                      0
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK                       0xFFu
+#define I2C_SLTL_SSLT_SHIFT                      0
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASES                                { I2C0, I2C1 }
+
+/**
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
+  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
+  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
+  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
+  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
+  __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
+  __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
+  __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
+  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
+  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK                      0x3u
+#define LLWU_PE1_WUPE0_SHIFT                     0
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      0xCu
+#define LLWU_PE1_WUPE1_SHIFT                     2
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      0x30u
+#define LLWU_PE1_WUPE2_SHIFT                     4
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      0xC0u
+#define LLWU_PE1_WUPE3_SHIFT                     6
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK                      0x3u
+#define LLWU_PE2_WUPE4_SHIFT                     0
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      0xCu
+#define LLWU_PE2_WUPE5_SHIFT                     2
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      0x30u
+#define LLWU_PE2_WUPE6_SHIFT                     4
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      0xC0u
+#define LLWU_PE2_WUPE7_SHIFT                     6
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK                      0x3u
+#define LLWU_PE3_WUPE8_SHIFT                     0
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      0xCu
+#define LLWU_PE3_WUPE9_SHIFT                     2
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     0x30u
+#define LLWU_PE3_WUPE10_SHIFT                    4
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     0xC0u
+#define LLWU_PE3_WUPE11_SHIFT                    6
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK                     0x3u
+#define LLWU_PE4_WUPE12_SHIFT                    0
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     0xCu
+#define LLWU_PE4_WUPE13_SHIFT                    2
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     0x30u
+#define LLWU_PE4_WUPE14_SHIFT                    4
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     0xC0u
+#define LLWU_PE4_WUPE15_SHIFT                    6
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK                       0x1u
+#define LLWU_ME_WUME0_SHIFT                      0
+#define LLWU_ME_WUME1_MASK                       0x2u
+#define LLWU_ME_WUME1_SHIFT                      1
+#define LLWU_ME_WUME2_MASK                       0x4u
+#define LLWU_ME_WUME2_SHIFT                      2
+#define LLWU_ME_WUME3_MASK                       0x8u
+#define LLWU_ME_WUME3_SHIFT                      3
+#define LLWU_ME_WUME4_MASK                       0x10u
+#define LLWU_ME_WUME4_SHIFT                      4
+#define LLWU_ME_WUME5_MASK                       0x20u
+#define LLWU_ME_WUME5_SHIFT                      5
+#define LLWU_ME_WUME6_MASK                       0x40u
+#define LLWU_ME_WUME6_SHIFT                      6
+#define LLWU_ME_WUME7_MASK                       0x80u
+#define LLWU_ME_WUME7_SHIFT                      7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK                        0x1u
+#define LLWU_F1_WUF0_SHIFT                       0
+#define LLWU_F1_WUF1_MASK                        0x2u
+#define LLWU_F1_WUF1_SHIFT                       1
+#define LLWU_F1_WUF2_MASK                        0x4u
+#define LLWU_F1_WUF2_SHIFT                       2
+#define LLWU_F1_WUF3_MASK                        0x8u
+#define LLWU_F1_WUF3_SHIFT                       3
+#define LLWU_F1_WUF4_MASK                        0x10u
+#define LLWU_F1_WUF4_SHIFT                       4
+#define LLWU_F1_WUF5_MASK                        0x20u
+#define LLWU_F1_WUF5_SHIFT                       5
+#define LLWU_F1_WUF6_MASK                        0x40u
+#define LLWU_F1_WUF6_SHIFT                       6
+#define LLWU_F1_WUF7_MASK                        0x80u
+#define LLWU_F1_WUF7_SHIFT                       7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK                        0x1u
+#define LLWU_F2_WUF8_SHIFT                       0
+#define LLWU_F2_WUF9_MASK                        0x2u
+#define LLWU_F2_WUF9_SHIFT                       1
+#define LLWU_F2_WUF10_MASK                       0x4u
+#define LLWU_F2_WUF10_SHIFT                      2
+#define LLWU_F2_WUF11_MASK                       0x8u
+#define LLWU_F2_WUF11_SHIFT                      3
+#define LLWU_F2_WUF12_MASK                       0x10u
+#define LLWU_F2_WUF12_SHIFT                      4
+#define LLWU_F2_WUF13_MASK                       0x20u
+#define LLWU_F2_WUF13_SHIFT                      5
+#define LLWU_F2_WUF14_MASK                       0x40u
+#define LLWU_F2_WUF14_SHIFT                      6
+#define LLWU_F2_WUF15_MASK                       0x80u
+#define LLWU_F2_WUF15_SHIFT                      7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK                       0x1u
+#define LLWU_F3_MWUF0_SHIFT                      0
+#define LLWU_F3_MWUF1_MASK                       0x2u
+#define LLWU_F3_MWUF1_SHIFT                      1
+#define LLWU_F3_MWUF2_MASK                       0x4u
+#define LLWU_F3_MWUF2_SHIFT                      2
+#define LLWU_F3_MWUF3_MASK                       0x8u
+#define LLWU_F3_MWUF3_SHIFT                      3
+#define LLWU_F3_MWUF4_MASK                       0x10u
+#define LLWU_F3_MWUF4_SHIFT                      4
+#define LLWU_F3_MWUF5_MASK                       0x20u
+#define LLWU_F3_MWUF5_SHIFT                      5
+#define LLWU_F3_MWUF6_MASK                       0x40u
+#define LLWU_F3_MWUF6_SHIFT                      6
+#define LLWU_F3_MWUF7_MASK                       0x80u
+#define LLWU_F3_MWUF7_SHIFT                      7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK                  0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT                 0
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK                    0x60u
+#define LLWU_FILT1_FILTE_SHIFT                   5
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK                    0x80u
+#define LLWU_FILT1_FILTF_SHIFT                   7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK                  0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT                 0
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK                    0x60u
+#define LLWU_FILT2_FILTE_SHIFT                   5
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK                    0x80u
+#define LLWU_FILT2_FILTF_SHIFT                   7
+
+/**
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASES                               { LLWU }
+
+/**
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __I  uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK                       0x1u
+#define LPTMR_CSR_TEN_SHIFT                      0
+#define LPTMR_CSR_TMS_MASK                       0x2u
+#define LPTMR_CSR_TMS_SHIFT                      1
+#define LPTMR_CSR_TFC_MASK                       0x4u
+#define LPTMR_CSR_TFC_SHIFT                      2
+#define LPTMR_CSR_TPP_MASK                       0x8u
+#define LPTMR_CSR_TPP_SHIFT                      3
+#define LPTMR_CSR_TPS_MASK                       0x30u
+#define LPTMR_CSR_TPS_SHIFT                      4
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       0x40u
+#define LPTMR_CSR_TIE_SHIFT                      6
+#define LPTMR_CSR_TCF_MASK                       0x80u
+#define LPTMR_CSR_TCF_SHIFT                      7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK                       0x3u
+#define LPTMR_PSR_PCS_SHIFT                      0
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      0x4u
+#define LPTMR_PSR_PBYP_SHIFT                     2
+#define LPTMR_PSR_PRESCALE_MASK                  0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT                 3
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT                  0
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT                  0
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASES                              { LPTMR0 }
+
+/**
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
+  __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
+  __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
+  __IO uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
+  __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
+  __I  uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+  __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+  __I  uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
+  __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
+  __I  uint8_t C9;                                 /**< MCG Control 9 Register, offset: 0xE */
+  __I  uint8_t C10;                                /**< MCG Control 10 Register, offset: 0xF */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK                     0x1u
+#define MCG_C1_IREFSTEN_SHIFT                    0
+#define MCG_C1_IRCLKEN_MASK                      0x2u
+#define MCG_C1_IRCLKEN_SHIFT                     1
+#define MCG_C1_IREFS_MASK                        0x4u
+#define MCG_C1_IREFS_SHIFT                       2
+#define MCG_C1_FRDIV_MASK                        0x38u
+#define MCG_C1_FRDIV_SHIFT                       3
+#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK                         0xC0u
+#define MCG_C1_CLKS_SHIFT                        6
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK                         0x1u
+#define MCG_C2_IRCS_SHIFT                        0
+#define MCG_C2_LP_MASK                           0x2u
+#define MCG_C2_LP_SHIFT                          1
+#define MCG_C2_EREFS0_MASK                       0x4u
+#define MCG_C2_EREFS0_SHIFT                      2
+#define MCG_C2_HGO0_MASK                         0x8u
+#define MCG_C2_HGO0_SHIFT                        3
+#define MCG_C2_RANGE0_MASK                       0x30u
+#define MCG_C2_RANGE0_SHIFT                      4
+#define MCG_C2_RANGE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_LOCRE0_MASK                       0x80u
+#define MCG_C2_LOCRE0_SHIFT                      7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK                       0xFFu
+#define MCG_C3_SCTRIM_SHIFT                      0
+#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK                      0x1u
+#define MCG_C4_SCFTRIM_SHIFT                     0
+#define MCG_C4_FCTRIM_MASK                       0x1Eu
+#define MCG_C4_FCTRIM_SHIFT                      1
+#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK                     0x60u
+#define MCG_C4_DRST_DRS_SHIFT                    5
+#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK                        0x80u
+#define MCG_C4_DMX32_SHIFT                       7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK                       0x1Fu
+#define MCG_C5_PRDIV0_SHIFT                      0
+#define MCG_C5_PRDIV0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK                     0x20u
+#define MCG_C5_PLLSTEN0_SHIFT                    5
+#define MCG_C5_PLLCLKEN0_MASK                    0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT                   6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK                        0x1Fu
+#define MCG_C6_VDIV0_SHIFT                       0
+#define MCG_C6_VDIV0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK                         0x20u
+#define MCG_C6_CME0_SHIFT                        5
+#define MCG_C6_PLLS_MASK                         0x40u
+#define MCG_C6_PLLS_SHIFT                        6
+#define MCG_C6_LOLIE0_MASK                       0x80u
+#define MCG_C6_LOLIE0_SHIFT                      7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK                         0x1u
+#define MCG_S_IRCST_SHIFT                        0
+#define MCG_S_OSCINIT0_MASK                      0x2u
+#define MCG_S_OSCINIT0_SHIFT                     1
+#define MCG_S_CLKST_MASK                         0xCu
+#define MCG_S_CLKST_SHIFT                        2
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK                        0x10u
+#define MCG_S_IREFST_SHIFT                       4
+#define MCG_S_PLLST_MASK                         0x20u
+#define MCG_S_PLLST_SHIFT                        5
+#define MCG_S_LOCK0_MASK                         0x40u
+#define MCG_S_LOCK0_SHIFT                        6
+#define MCG_S_LOLS_MASK                          0x80u
+#define MCG_S_LOLS_SHIFT                         7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK                        0x1u
+#define MCG_SC_LOCS0_SHIFT                       0
+#define MCG_SC_FCRDIV_MASK                       0xEu
+#define MCG_SC_FCRDIV_SHIFT                      1
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK                     0x10u
+#define MCG_SC_FLTPRSRV_SHIFT                    4
+#define MCG_SC_ATMF_MASK                         0x20u
+#define MCG_SC_ATMF_SHIFT                        5
+#define MCG_SC_ATMS_MASK                         0x40u
+#define MCG_SC_ATMS_SHIFT                        6
+#define MCG_SC_ATME_MASK                         0x80u
+#define MCG_SC_ATME_SHIFT                        7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK                     0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT                    0
+#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK                     0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT                    0
+#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOLRE_MASK                        0x40u
+#define MCG_C8_LOLRE_SHIFT                       6
+
+/**
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG                                      ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASES                                { MCG }
+
+/**
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t PLACR;                             /**< Platform Control Register, offset: 0xC */
+       uint8_t RESERVED_1[48];
+  __IO uint32_t CPO;                               /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK                       0xFFu
+#define MCM_PLASC_ASC_SHIFT                      0
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK                       0xFFu
+#define MCM_PLAMC_AMC_SHIFT                      0
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK                       0x200u
+#define MCM_PLACR_ARB_SHIFT                      9
+#define MCM_PLACR_CFCC_MASK                      0x400u
+#define MCM_PLACR_CFCC_SHIFT                     10
+#define MCM_PLACR_DFCDA_MASK                     0x800u
+#define MCM_PLACR_DFCDA_SHIFT                    11
+#define MCM_PLACR_DFCIC_MASK                     0x1000u
+#define MCM_PLACR_DFCIC_SHIFT                    12
+#define MCM_PLACR_DFCC_MASK                      0x2000u
+#define MCM_PLACR_DFCC_SHIFT                     13
+#define MCM_PLACR_EFDS_MASK                      0x4000u
+#define MCM_PLACR_EFDS_SHIFT                     14
+#define MCM_PLACR_DFCS_MASK                      0x8000u
+#define MCM_PLACR_DFCS_SHIFT                     15
+#define MCM_PLACR_ESFC_MASK                      0x10000u
+#define MCM_PLACR_ESFC_SHIFT                     16
+/* CPO Bit Fields */
+#define MCM_CPO_CPOREQ_MASK                      0x1u
+#define MCM_CPO_CPOREQ_SHIFT                     0
+#define MCM_CPO_CPOACK_MASK                      0x2u
+#define MCM_CPO_CPOACK_SHIFT                     1
+#define MCM_CPO_CPOWOI_MASK                      0x4u
+#define MCM_CPO_CPOWOI_SHIFT                     2
+
+/**
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASES                                { MCM }
+
+/**
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MTB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t POSITION;                          /**< MTB Position Register, offset: 0x0 */
+  __IO uint32_t MASTER;                            /**< MTB Master Register, offset: 0x4 */
+  __IO uint32_t FLOW;                              /**< MTB Flow Register, offset: 0x8 */
+  __I  uint32_t BASE;                              /**< MTB Base Register, offset: 0xC */
+       uint8_t RESERVED_0[3824];
+  __I  uint32_t MODECTRL;                          /**< Integration Mode Control Register, offset: 0xF00 */
+       uint8_t RESERVED_1[156];
+  __I  uint32_t TAGSET;                            /**< Claim TAG Set Register, offset: 0xFA0 */
+  __I  uint32_t TAGCLEAR;                          /**< Claim TAG Clear Register, offset: 0xFA4 */
+       uint8_t RESERVED_2[8];
+  __I  uint32_t LOCKACCESS;                        /**< Lock Access Register, offset: 0xFB0 */
+  __I  uint32_t LOCKSTAT;                          /**< Lock Status Register, offset: 0xFB4 */
+  __I  uint32_t AUTHSTAT;                          /**< Authentication Status Register, offset: 0xFB8 */
+  __I  uint32_t DEVICEARCH;                        /**< Device Architecture Register, offset: 0xFBC */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
+  __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID[8];                       /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MTB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/* POSITION Bit Fields */
+#define MTB_POSITION_WRAP_MASK                   0x4u
+#define MTB_POSITION_WRAP_SHIFT                  2
+#define MTB_POSITION_POINTER_MASK                0xFFFFFFF8u
+#define MTB_POSITION_POINTER_SHIFT               3
+#define MTB_POSITION_POINTER(x)                  (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
+/* MASTER Bit Fields */
+#define MTB_MASTER_MASK_MASK                     0x1Fu
+#define MTB_MASTER_MASK_SHIFT                    0
+#define MTB_MASTER_MASK(x)                       (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK                 0x20u
+#define MTB_MASTER_TSTARTEN_SHIFT                5
+#define MTB_MASTER_TSTOPEN_MASK                  0x40u
+#define MTB_MASTER_TSTOPEN_SHIFT                 6
+#define MTB_MASTER_SFRWPRIV_MASK                 0x80u
+#define MTB_MASTER_SFRWPRIV_SHIFT                7
+#define MTB_MASTER_RAMPRIV_MASK                  0x100u
+#define MTB_MASTER_RAMPRIV_SHIFT                 8
+#define MTB_MASTER_HALTREQ_MASK                  0x200u
+#define MTB_MASTER_HALTREQ_SHIFT                 9
+#define MTB_MASTER_EN_MASK                       0x80000000u
+#define MTB_MASTER_EN_SHIFT                      31
+/* FLOW Bit Fields */
+#define MTB_FLOW_AUTOSTOP_MASK                   0x1u
+#define MTB_FLOW_AUTOSTOP_SHIFT                  0
+#define MTB_FLOW_AUTOHALT_MASK                   0x2u
+#define MTB_FLOW_AUTOHALT_SHIFT                  1
+#define MTB_FLOW_WATERMARK_MASK                  0xFFFFFFF8u
+#define MTB_FLOW_WATERMARK_SHIFT                 3
+#define MTB_FLOW_WATERMARK(x)                    (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
+/* BASE Bit Fields */
+#define MTB_BASE_BASEADDR_MASK                   0xFFFFFFFFu
+#define MTB_BASE_BASEADDR_SHIFT                  0
+#define MTB_BASE_BASEADDR(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
+/* MODECTRL Bit Fields */
+#define MTB_MODECTRL_MODECTRL_MASK               0xFFFFFFFFu
+#define MTB_MODECTRL_MODECTRL_SHIFT              0
+#define MTB_MODECTRL_MODECTRL(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
+/* TAGSET Bit Fields */
+#define MTB_TAGSET_TAGSET_MASK                   0xFFFFFFFFu
+#define MTB_TAGSET_TAGSET_SHIFT                  0
+#define MTB_TAGSET_TAGSET(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
+/* TAGCLEAR Bit Fields */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK               0xFFFFFFFFu
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT              0
+#define MTB_TAGCLEAR_TAGCLEAR(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
+/* LOCKACCESS Bit Fields */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK           0xFFFFFFFFu
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT          0
+#define MTB_LOCKACCESS_LOCKACCESS(x)             (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
+/* LOCKSTAT Bit Fields */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK               0xFFFFFFFFu
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT              0
+#define MTB_LOCKSTAT_LOCKSTAT(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
+/* AUTHSTAT Bit Fields */
+#define MTB_AUTHSTAT_BIT0_MASK                   0x1u
+#define MTB_AUTHSTAT_BIT0_SHIFT                  0
+#define MTB_AUTHSTAT_BIT1_MASK                   0x2u
+#define MTB_AUTHSTAT_BIT1_SHIFT                  1
+#define MTB_AUTHSTAT_BIT2_MASK                   0x4u
+#define MTB_AUTHSTAT_BIT2_SHIFT                  2
+#define MTB_AUTHSTAT_BIT3_MASK                   0x8u
+#define MTB_AUTHSTAT_BIT3_SHIFT                  3
+/* DEVICEARCH Bit Fields */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK           0xFFFFFFFFu
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT          0
+#define MTB_DEVICEARCH_DEVICEARCH(x)             (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
+/* DEVICECFG Bit Fields */
+#define MTB_DEVICECFG_DEVICECFG_MASK             0xFFFFFFFFu
+#define MTB_DEVICECFG_DEVICECFG_SHIFT            0
+#define MTB_DEVICECFG_DEVICECFG(x)               (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK         0xFFFFFFFFu
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT        0
+#define MTB_DEVICETYPID_DEVICETYPID(x)           (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTB_PERIPHID_PERIPHID_MASK               0xFFFFFFFFu
+#define MTB_PERIPHID_PERIPHID_SHIFT              0
+#define MTB_PERIPHID_PERIPHID(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTB_COMPID_COMPID_MASK                   0xFFFFFFFFu
+#define MTB_COMPID_COMPID_SHIFT                  0
+#define MTB_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE                                 (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB                                      ((MTB_Type *)MTB_BASE)
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASES                                { MTB }
+
+/**
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MTBDWT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t CTRL;                              /**< MTB DWT Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  struct {                                         /* offset: 0x20, array step: 0x10 */
+    __IO uint32_t COMP;                              /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+    __IO uint32_t MASK;                              /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+    __IO uint32_t FCT;                               /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+         uint8_t RESERVED_0[4];
+  } COMPARATOR[2];
+       uint8_t RESERVED_1[448];
+  __IO uint32_t TBCTRL;                            /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+       uint8_t RESERVED_2[3524];
+  __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
+  __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID[8];                       /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MTBDWT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK              0xFFFFFFFu
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT             0
+#define MTBDWT_CTRL_DWTCFGCTRL(x)                (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK                  0xF0000000u
+#define MTBDWT_CTRL_NUMCMP_SHIFT                 28
+#define MTBDWT_CTRL_NUMCMP(x)                    (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
+/* COMP Bit Fields */
+#define MTBDWT_COMP_COMP_MASK                    0xFFFFFFFFu
+#define MTBDWT_COMP_COMP_SHIFT                   0
+#define MTBDWT_COMP_COMP(x)                      (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
+/* MASK Bit Fields */
+#define MTBDWT_MASK_MASK_MASK                    0x1Fu
+#define MTBDWT_MASK_MASK_SHIFT                   0
+#define MTBDWT_MASK_MASK(x)                      (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
+/* FCT Bit Fields */
+#define MTBDWT_FCT_FUNCTION_MASK                 0xFu
+#define MTBDWT_FCT_FUNCTION_SHIFT                0
+#define MTBDWT_FCT_FUNCTION(x)                   (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK               0x100u
+#define MTBDWT_FCT_DATAVMATCH_SHIFT              8
+#define MTBDWT_FCT_DATAVSIZE_MASK                0xC00u
+#define MTBDWT_FCT_DATAVSIZE_SHIFT               10
+#define MTBDWT_FCT_DATAVSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK               0xF000u
+#define MTBDWT_FCT_DATAVADDR0_SHIFT              12
+#define MTBDWT_FCT_DATAVADDR0(x)                 (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK                  0x1000000u
+#define MTBDWT_FCT_MATCHED_SHIFT                 24
+/* TBCTRL Bit Fields */
+#define MTBDWT_TBCTRL_ACOMP0_MASK                0x1u
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT               0
+#define MTBDWT_TBCTRL_ACOMP1_MASK                0x2u
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT               1
+#define MTBDWT_TBCTRL_NUMCOMP_MASK               0xF0000000u
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT              28
+#define MTBDWT_TBCTRL_NUMCOMP(x)                 (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
+/* DEVICECFG Bit Fields */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK          0xFFFFFFFFu
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT         0
+#define MTBDWT_DEVICECFG_DEVICECFG(x)            (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK      0xFFFFFFFFu
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT     0
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x)        (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTBDWT_PERIPHID_PERIPHID_MASK            0xFFFFFFFFu
+#define MTBDWT_PERIPHID_PERIPHID_SHIFT           0
+#define MTBDWT_PERIPHID_PERIPHID(x)              (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTBDWT_COMPID_COMPID_MASK                0xFFFFFFFFu
+#define MTBDWT_COMPID_COMPID_SHIFT               0
+#define MTBDWT_COMPID_COMPID(x)                  (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE                              (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT                                   ((MTBDWT_Type *)MTBDWT_BASE)
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASES                             { MTBDWT }
+
+/**
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK                     0xFFu
+#define NV_BACKKEY3_KEY_SHIFT                    0
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK                     0xFFu
+#define NV_BACKKEY2_KEY_SHIFT                    0
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK                     0xFFu
+#define NV_BACKKEY1_KEY_SHIFT                    0
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK                     0xFFu
+#define NV_BACKKEY0_KEY_SHIFT                    0
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK                     0xFFu
+#define NV_BACKKEY7_KEY_SHIFT                    0
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK                     0xFFu
+#define NV_BACKKEY6_KEY_SHIFT                    0
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK                     0xFFu
+#define NV_BACKKEY5_KEY_SHIFT                    0
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK                     0xFFu
+#define NV_BACKKEY4_KEY_SHIFT                    0
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK                      0xFFu
+#define NV_FPROT3_PROT_SHIFT                     0
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK                      0xFFu
+#define NV_FPROT2_PROT_SHIFT                     0
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK                      0xFFu
+#define NV_FPROT1_PROT_SHIFT                     0
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK                      0xFFu
+#define NV_FPROT0_PROT_SHIFT                     0
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK                         0x3u
+#define NV_FSEC_SEC_SHIFT                        0
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      0xCu
+#define NV_FSEC_FSLACC_SHIFT                     2
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        0x30u
+#define NV_FSEC_MEEN_SHIFT                       4
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       0xC0u
+#define NV_FSEC_KEYEN_SHIFT                      6
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT0_MASK                     0x1u
+#define NV_FOPT_LPBOOT0_SHIFT                    0
+#define NV_FOPT_NMI_DIS_MASK                     0x4u
+#define NV_FOPT_NMI_DIS_SHIFT                    2
+#define NV_FOPT_RESET_PIN_CFG_MASK               0x8u
+#define NV_FOPT_RESET_PIN_CFG_SHIFT              3
+#define NV_FOPT_LPBOOT1_MASK                     0x10u
+#define NV_FOPT_LPBOOT1_SHIFT                    4
+#define NV_FOPT_FAST_INIT_MASK                   0x20u
+#define NV_FOPT_FAST_INIT_SHIFT                  5
+
+/**
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE                    (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig                         ((NV_Type *)FTFA_FlashConfig_BASE)
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASES                                 { FTFA_FlashConfig }
+
+/**
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK                        0x1u
+#define OSC_CR_SC16P_SHIFT                       0
+#define OSC_CR_SC8P_MASK                         0x2u
+#define OSC_CR_SC8P_SHIFT                        1
+#define OSC_CR_SC4P_MASK                         0x4u
+#define OSC_CR_SC4P_SHIFT                        2
+#define OSC_CR_SC2P_MASK                         0x8u
+#define OSC_CR_SC2P_SHIFT                        3
+#define OSC_CR_EREFSTEN_MASK                     0x20u
+#define OSC_CR_EREFSTEN_SHIFT                    5
+#define OSC_CR_ERCLKEN_MASK                      0x80u
+#define OSC_CR_ERCLKEN_SHIFT                     7
+
+/**
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE                                (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0                                     ((OSC_Type *)OSC0_BASE)
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASES                                { OSC0 }
+
+/**
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[220];
+  __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+  __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+       uint8_t RESERVED_1[24];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[2];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK                         0x1u
+#define PIT_MCR_FRZ_SHIFT                        0
+#define PIT_MCR_MDIS_MASK                        0x2u
+#define PIT_MCR_MDIS_SHIFT                       1
+/* LTMR64H Bit Fields */
+#define PIT_LTMR64H_LTH_MASK                     0xFFFFFFFFu
+#define PIT_LTMR64H_LTH_SHIFT                    0
+#define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
+/* LTMR64L Bit Fields */
+#define PIT_LTMR64L_LTL_MASK                     0xFFFFFFFFu
+#define PIT_LTMR64L_LTL_SHIFT                    0
+#define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT                      0
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT                       0
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK                       0x1u
+#define PIT_TCTRL_TEN_SHIFT                      0
+#define PIT_TCTRL_TIE_MASK                       0x2u
+#define PIT_TCTRL_TIE_SHIFT                      1
+#define PIT_TCTRL_CHN_MASK                       0x4u
+#define PIT_TCTRL_CHN_SHIFT                      2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK                        0x1u
+#define PIT_TFLG_TIF_SHIFT                       0
+
+/**
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASES                                { PIT }
+
+/**
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK                     0x3u
+#define PMC_LVDSC1_LVDV_SHIFT                    0
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK                    0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT                   4
+#define PMC_LVDSC1_LVDIE_MASK                    0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT                   5
+#define PMC_LVDSC1_LVDACK_MASK                   0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT                  6
+#define PMC_LVDSC1_LVDF_MASK                     0x80u
+#define PMC_LVDSC1_LVDF_SHIFT                    7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK                     0x3u
+#define PMC_LVDSC2_LVWV_SHIFT                    0
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK                    0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT                   5
+#define PMC_LVDSC2_LVWACK_MASK                   0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT                  6
+#define PMC_LVDSC2_LVWF_MASK                     0x80u
+#define PMC_LVDSC2_LVWF_SHIFT                    7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK                      0x1u
+#define PMC_REGSC_BGBE_SHIFT                     0
+#define PMC_REGSC_REGONS_MASK                    0x4u
+#define PMC_REGSC_REGONS_SHIFT                   2
+#define PMC_REGSC_ACKISO_MASK                    0x8u
+#define PMC_REGSC_ACKISO_SHIFT                   3
+#define PMC_REGSC_BGEN_MASK                      0x10u
+#define PMC_REGSC_BGEN_SHIFT                     4
+
+/**
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASES                                { PMC }
+
+/**
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK                         0x1u
+#define PORT_PCR_PS_SHIFT                        0
+#define PORT_PCR_PE_MASK                         0x2u
+#define PORT_PCR_PE_SHIFT                        1
+#define PORT_PCR_SRE_MASK                        0x4u
+#define PORT_PCR_SRE_SHIFT                       2
+#define PORT_PCR_PFE_MASK                        0x10u
+#define PORT_PCR_PFE_SHIFT                       4
+#define PORT_PCR_DSE_MASK                        0x40u
+#define PORT_PCR_DSE_SHIFT                       6
+#define PORT_PCR_MUX_MASK                        0x700u
+#define PORT_PCR_MUX_SHIFT                       8
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_IRQC_MASK                       0xF0000u
+#define PORT_PCR_IRQC_SHIFT                      16
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        0x1000000u
+#define PORT_PCR_ISF_SHIFT                       24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT                    0
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT                    16
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT                    0
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT                    16
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT                      0
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+
+/**
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASES                               { PORTA, PORTB, PORTC, PORTD, PORTE }
+
+/**
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
+  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
+  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK                     0x1u
+#define RCM_SRS0_WAKEUP_SHIFT                    0
+#define RCM_SRS0_LVD_MASK                        0x2u
+#define RCM_SRS0_LVD_SHIFT                       1
+#define RCM_SRS0_LOC_MASK                        0x4u
+#define RCM_SRS0_LOC_SHIFT                       2
+#define RCM_SRS0_LOL_MASK                        0x8u
+#define RCM_SRS0_LOL_SHIFT                       3
+#define RCM_SRS0_WDOG_MASK                       0x20u
+#define RCM_SRS0_WDOG_SHIFT                      5
+#define RCM_SRS0_PIN_MASK                        0x40u
+#define RCM_SRS0_PIN_SHIFT                       6
+#define RCM_SRS0_POR_MASK                        0x80u
+#define RCM_SRS0_POR_SHIFT                       7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_LOCKUP_MASK                     0x2u
+#define RCM_SRS1_LOCKUP_SHIFT                    1
+#define RCM_SRS1_SW_MASK                         0x4u
+#define RCM_SRS1_SW_SHIFT                        2
+#define RCM_SRS1_MDM_AP_MASK                     0x8u
+#define RCM_SRS1_MDM_AP_SHIFT                    3
+#define RCM_SRS1_SACKERR_MASK                    0x20u
+#define RCM_SRS1_SACKERR_SHIFT                   5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK                  0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 0
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK                   0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT                  2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK                  0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 0
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE                                 (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM                                      ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASES                                { RCM }
+
+/**
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ROM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t ENTRY[3];                          /**< Entry, array offset: 0x0, array step: 0x4 */
+  __I  uint32_t TABLEMARK;                         /**< End of Table Marker Register, offset: 0xC */
+       uint8_t RESERVED_0[4028];
+  __I  uint32_t SYSACCESS;                         /**< System Access Register, offset: 0xFCC */
+  __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
+  __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
+  __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
+  __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
+  __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
+  __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
+  __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
+  __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
+  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ROM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/* ENTRY Bit Fields */
+#define ROM_ENTRY_ENTRY_MASK                     0xFFFFFFFFu
+#define ROM_ENTRY_ENTRY_SHIFT                    0
+#define ROM_ENTRY_ENTRY(x)                       (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
+/* TABLEMARK Bit Fields */
+#define ROM_TABLEMARK_MARK_MASK                  0xFFFFFFFFu
+#define ROM_TABLEMARK_MARK_SHIFT                 0
+#define ROM_TABLEMARK_MARK(x)                    (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
+/* SYSACCESS Bit Fields */
+#define ROM_SYSACCESS_SYSACCESS_MASK             0xFFFFFFFFu
+#define ROM_SYSACCESS_SYSACCESS_SHIFT            0
+#define ROM_SYSACCESS_SYSACCESS(x)               (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
+/* PERIPHID4 Bit Fields */
+#define ROM_PERIPHID4_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID4_PERIPHID_SHIFT             0
+#define ROM_PERIPHID4_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
+/* PERIPHID5 Bit Fields */
+#define ROM_PERIPHID5_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID5_PERIPHID_SHIFT             0
+#define ROM_PERIPHID5_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
+/* PERIPHID6 Bit Fields */
+#define ROM_PERIPHID6_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID6_PERIPHID_SHIFT             0
+#define ROM_PERIPHID6_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
+/* PERIPHID7 Bit Fields */
+#define ROM_PERIPHID7_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID7_PERIPHID_SHIFT             0
+#define ROM_PERIPHID7_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
+/* PERIPHID0 Bit Fields */
+#define ROM_PERIPHID0_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID0_PERIPHID_SHIFT             0
+#define ROM_PERIPHID0_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
+/* PERIPHID1 Bit Fields */
+#define ROM_PERIPHID1_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID1_PERIPHID_SHIFT             0
+#define ROM_PERIPHID1_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
+/* PERIPHID2 Bit Fields */
+#define ROM_PERIPHID2_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID2_PERIPHID_SHIFT             0
+#define ROM_PERIPHID2_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
+/* PERIPHID3 Bit Fields */
+#define ROM_PERIPHID3_PERIPHID_MASK              0xFFFFFFFFu
+#define ROM_PERIPHID3_PERIPHID_SHIFT             0
+#define ROM_PERIPHID3_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define ROM_COMPID_COMPID_MASK                   0xFFFFFFFFu
+#define ROM_COMPID_COMPID_SHIFT                  0
+#define ROM_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE                                 (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM                                      ((ROM_Type *)ROM_BASE)
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASES                                { ROM }
+
+/**
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT                        0
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK                         0xFFFFu
+#define RTC_TPR_TPR_SHIFT                        0
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT                        0
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK                         0xFFu
+#define RTC_TCR_TCR_SHIFT                        0
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         0xFF00u
+#define RTC_TCR_CIR_SHIFT                        8
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         0xFF0000u
+#define RTC_TCR_TCV_SHIFT                        16
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         0xFF000000u
+#define RTC_TCR_CIC_SHIFT                        24
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK                          0x1u
+#define RTC_CR_SWR_SHIFT                         0
+#define RTC_CR_WPE_MASK                          0x2u
+#define RTC_CR_WPE_SHIFT                         1
+#define RTC_CR_SUP_MASK                          0x4u
+#define RTC_CR_SUP_SHIFT                         2
+#define RTC_CR_UM_MASK                           0x8u
+#define RTC_CR_UM_SHIFT                          3
+#define RTC_CR_OSCE_MASK                         0x100u
+#define RTC_CR_OSCE_SHIFT                        8
+#define RTC_CR_CLKO_MASK                         0x200u
+#define RTC_CR_CLKO_SHIFT                        9
+#define RTC_CR_SC16P_MASK                        0x400u
+#define RTC_CR_SC16P_SHIFT                       10
+#define RTC_CR_SC8P_MASK                         0x800u
+#define RTC_CR_SC8P_SHIFT                        11
+#define RTC_CR_SC4P_MASK                         0x1000u
+#define RTC_CR_SC4P_SHIFT                        12
+#define RTC_CR_SC2P_MASK                         0x2000u
+#define RTC_CR_SC2P_SHIFT                        13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK                          0x1u
+#define RTC_SR_TIF_SHIFT                         0
+#define RTC_SR_TOF_MASK                          0x2u
+#define RTC_SR_TOF_SHIFT                         1
+#define RTC_SR_TAF_MASK                          0x4u
+#define RTC_SR_TAF_SHIFT                         2
+#define RTC_SR_TCE_MASK                          0x10u
+#define RTC_SR_TCE_SHIFT                         4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK                          0x8u
+#define RTC_LR_TCL_SHIFT                         3
+#define RTC_LR_CRL_MASK                          0x10u
+#define RTC_LR_CRL_SHIFT                         4
+#define RTC_LR_SRL_MASK                          0x20u
+#define RTC_LR_SRL_SHIFT                         5
+#define RTC_LR_LRL_MASK                          0x40u
+#define RTC_LR_LRL_SHIFT                         6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK                        0x1u
+#define RTC_IER_TIIE_SHIFT                       0
+#define RTC_IER_TOIE_MASK                        0x2u
+#define RTC_IER_TOIE_SHIFT                       1
+#define RTC_IER_TAIE_MASK                        0x4u
+#define RTC_IER_TAIE_SHIFT                       2
+#define RTC_IER_TSIE_MASK                        0x10u
+#define RTC_IER_TSIE_SHIFT                       4
+#define RTC_IER_WPON_MASK                        0x80u
+#define RTC_IER_WPON_SHIFT                       7
+
+/**
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASES                                { RTC }
+
+/**
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
+  __IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
+       uint8_t RESERVED_0[4092];
+  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
+  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
+       uint8_t RESERVED_4[12];
+  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
+       uint8_t RESERVED_5[4];
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
+       uint8_t RESERVED_6[4];
+  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
+       uint8_t RESERVED_7[156];
+  __IO uint32_t COPC;                              /**< COP Control Register, offset: 0x1100 */
+  __O  uint32_t SRVCOP;                            /**< Service COP Register, offset: 0x1104 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_OSC32KSEL_MASK                 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT                18
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK                  0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT                 29
+#define SIM_SOPT1_USBSSTBY_MASK                  0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT                 30
+#define SIM_SOPT1_USBREGEN_MASK                  0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT                 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK                   0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT                  24
+#define SIM_SOPT1CFG_UVSWE_MASK                  0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT                 25
+#define SIM_SOPT1CFG_USSWE_MASK                  0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT                 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK              0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             4
+#define SIM_SOPT2_CLKOUTSEL_MASK                 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT                5
+#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK                 0x10000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT                16
+#define SIM_SOPT2_USBSRC_MASK                    0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT                   18
+#define SIM_SOPT2_TPMSRC_MASK                    0x3000000u
+#define SIM_SOPT2_TPMSRC_SHIFT                   24
+#define SIM_SOPT2_TPMSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_UART0SRC_MASK                  0xC000000u
+#define SIM_SOPT2_UART0SRC_SHIFT                 26
+#define SIM_SOPT2_UART0SRC(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_TPM1CH0SRC_MASK                0x40000u
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT               18
+#define SIM_SOPT4_TPM2CH0SRC_MASK                0x100000u
+#define SIM_SOPT4_TPM2CH0SRC_SHIFT               20
+#define SIM_SOPT4_TPM0CLKSEL_MASK                0x1000000u
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT               24
+#define SIM_SOPT4_TPM1CLKSEL_MASK                0x2000000u
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT               25
+#define SIM_SOPT4_TPM2CLKSEL_MASK                0x4000000u
+#define SIM_SOPT4_TPM2CLKSEL_SHIFT               26
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK                0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT               0
+#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK                0x4u
+#define SIM_SOPT5_UART0RXSRC_SHIFT               2
+#define SIM_SOPT5_UART1TXSRC_MASK                0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT               4
+#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK                0x40u
+#define SIM_SOPT5_UART1RXSRC_SHIFT               6
+#define SIM_SOPT5_UART0ODE_MASK                  0x10000u
+#define SIM_SOPT5_UART0ODE_SHIFT                 16
+#define SIM_SOPT5_UART1ODE_MASK                  0x20000u
+#define SIM_SOPT5_UART1ODE_SHIFT                 17
+#define SIM_SOPT5_UART2ODE_MASK                  0x40000u
+#define SIM_SOPT5_UART2ODE_SHIFT                 18
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK                      0xFu
+#define SIM_SDID_PINID_SHIFT                     0
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_DIEID_MASK                      0xF80u
+#define SIM_SDID_DIEID_SHIFT                     7
+#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK                      0xF000u
+#define SIM_SDID_REVID_SHIFT                     12
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SRAMSIZE_MASK                   0xF0000u
+#define SIM_SDID_SRAMSIZE_SHIFT                  16
+#define SIM_SDID_SRAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
+#define SIM_SDID_SERIESID_MASK                   0xF00000u
+#define SIM_SDID_SERIESID_SHIFT                  20
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT                  24
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK                      0xF0000000u
+#define SIM_SDID_FAMID_SHIFT                     28
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_I2C0_MASK                      0x40u
+#define SIM_SCGC4_I2C0_SHIFT                     6
+#define SIM_SCGC4_I2C1_MASK                      0x80u
+#define SIM_SCGC4_I2C1_SHIFT                     7
+#define SIM_SCGC4_UART0_MASK                     0x400u
+#define SIM_SCGC4_UART0_SHIFT                    10
+#define SIM_SCGC4_UART1_MASK                     0x800u
+#define SIM_SCGC4_UART1_SHIFT                    11
+#define SIM_SCGC4_UART2_MASK                     0x1000u
+#define SIM_SCGC4_UART2_SHIFT                    12
+#define SIM_SCGC4_USBOTG_MASK                    0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT                   18
+#define SIM_SCGC4_CMP_MASK                       0x80000u
+#define SIM_SCGC4_CMP_SHIFT                      19
+#define SIM_SCGC4_SPI0_MASK                      0x400000u
+#define SIM_SCGC4_SPI0_SHIFT                     22
+#define SIM_SCGC4_SPI1_MASK                      0x800000u
+#define SIM_SCGC4_SPI1_SHIFT                     23
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK                     0x1u
+#define SIM_SCGC5_LPTMR_SHIFT                    0
+#define SIM_SCGC5_TSI_MASK                       0x20u
+#define SIM_SCGC5_TSI_SHIFT                      5
+#define SIM_SCGC5_PORTA_MASK                     0x200u
+#define SIM_SCGC5_PORTA_SHIFT                    9
+#define SIM_SCGC5_PORTB_MASK                     0x400u
+#define SIM_SCGC5_PORTB_SHIFT                    10
+#define SIM_SCGC5_PORTC_MASK                     0x800u
+#define SIM_SCGC5_PORTC_SHIFT                    11
+#define SIM_SCGC5_PORTD_MASK                     0x1000u
+#define SIM_SCGC5_PORTD_SHIFT                    12
+#define SIM_SCGC5_PORTE_MASK                     0x2000u
+#define SIM_SCGC5_PORTE_SHIFT                    13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK                       0x1u
+#define SIM_SCGC6_FTF_SHIFT                      0
+#define SIM_SCGC6_DMAMUX_MASK                    0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT                   1
+#define SIM_SCGC6_PIT_MASK                       0x800000u
+#define SIM_SCGC6_PIT_SHIFT                      23
+#define SIM_SCGC6_TPM0_MASK                      0x1000000u
+#define SIM_SCGC6_TPM0_SHIFT                     24
+#define SIM_SCGC6_TPM1_MASK                      0x2000000u
+#define SIM_SCGC6_TPM1_SHIFT                     25
+#define SIM_SCGC6_TPM2_MASK                      0x4000000u
+#define SIM_SCGC6_TPM2_SHIFT                     26
+#define SIM_SCGC6_ADC0_MASK                      0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT                     27
+#define SIM_SCGC6_RTC_MASK                       0x20000000u
+#define SIM_SCGC6_RTC_SHIFT                      29
+#define SIM_SCGC6_DAC0_MASK                      0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT                     31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK                       0x100u
+#define SIM_SCGC7_DMA_SHIFT                      8
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK                 0x70000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                16
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                28
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK                  0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT                 0
+#define SIM_FCFG1_FLASHDOZE_MASK                 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT                1
+#define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT                   24
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR_MASK                   0x7F000000u
+#define SIM_FCFG2_MAXADDR_SHIFT                  24
+#define SIM_FCFG2_MAXADDR(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK                       0xFFFFu
+#define SIM_UIDMH_UID_SHIFT                      0
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT                      0
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT                       0
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/* COPC Bit Fields */
+#define SIM_COPC_COPW_MASK                       0x1u
+#define SIM_COPC_COPW_SHIFT                      0
+#define SIM_COPC_COPCLKS_MASK                    0x2u
+#define SIM_COPC_COPCLKS_SHIFT                   1
+#define SIM_COPC_COPT_MASK                       0xCu
+#define SIM_COPC_COPT_SHIFT                      2
+#define SIM_COPC_COPT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
+/* SRVCOP Bit Fields */
+#define SIM_SRVCOP_SRVCOP_MASK                   0xFFu
+#define SIM_SRVCOP_SRVCOP_SHIFT                  0
+#define SIM_SRVCOP_SRVCOP(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
+
+/**
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASES                                { SIM }
+
+/**
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
+  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
+  __IO uint8_t STOPCTRL;                           /**< Stop Control Register, offset: 0x2 */
+  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK                    0x2u
+#define SMC_PMPROT_AVLLS_SHIFT                   1
+#define SMC_PMPROT_ALLS_MASK                     0x8u
+#define SMC_PMPROT_ALLS_SHIFT                    3
+#define SMC_PMPROT_AVLP_MASK                     0x20u
+#define SMC_PMPROT_AVLP_SHIFT                    5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK                    0x7u
+#define SMC_PMCTRL_STOPM_SHIFT                   0
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK                    0x8u
+#define SMC_PMCTRL_STOPA_SHIFT                   3
+#define SMC_PMCTRL_RUNM_MASK                     0x60u
+#define SMC_PMCTRL_RUNM_SHIFT                    5
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+/* STOPCTRL Bit Fields */
+#define SMC_STOPCTRL_VLLSM_MASK                  0x7u
+#define SMC_STOPCTRL_VLLSM_SHIFT                 0
+#define SMC_STOPCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK                  0x20u
+#define SMC_STOPCTRL_PORPO_SHIFT                 5
+#define SMC_STOPCTRL_PSTOPO_MASK                 0xC0u
+#define SMC_STOPCTRL_PSTOPO_SHIFT                6
+#define SMC_STOPCTRL_PSTOPO(x)                   (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK                   0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT                  0
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/**
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE                                 (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC                                      ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASES                                { SMC }
+
+/**
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< SPI control register 1, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< SPI control register 2, offset: 0x1 */
+  __IO uint8_t BR;                                 /**< SPI baud rate register, offset: 0x2 */
+  __I  uint8_t S;                                  /**< SPI status register, offset: 0x3 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t D;                                  /**< SPI data register, offset: 0x5 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t M;                                  /**< SPI match register, offset: 0x7 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define SPI_C1_LSBFE_MASK                        0x1u
+#define SPI_C1_LSBFE_SHIFT                       0
+#define SPI_C1_SSOE_MASK                         0x2u
+#define SPI_C1_SSOE_SHIFT                        1
+#define SPI_C1_CPHA_MASK                         0x4u
+#define SPI_C1_CPHA_SHIFT                        2
+#define SPI_C1_CPOL_MASK                         0x8u
+#define SPI_C1_CPOL_SHIFT                        3
+#define SPI_C1_MSTR_MASK                         0x10u
+#define SPI_C1_MSTR_SHIFT                        4
+#define SPI_C1_SPTIE_MASK                        0x20u
+#define SPI_C1_SPTIE_SHIFT                       5
+#define SPI_C1_SPE_MASK                          0x40u
+#define SPI_C1_SPE_SHIFT                         6
+#define SPI_C1_SPIE_MASK                         0x80u
+#define SPI_C1_SPIE_SHIFT                        7
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK                         0x1u
+#define SPI_C2_SPC0_SHIFT                        0
+#define SPI_C2_SPISWAI_MASK                      0x2u
+#define SPI_C2_SPISWAI_SHIFT                     1
+#define SPI_C2_RXDMAE_MASK                       0x4u
+#define SPI_C2_RXDMAE_SHIFT                      2
+#define SPI_C2_BIDIROE_MASK                      0x8u
+#define SPI_C2_BIDIROE_SHIFT                     3
+#define SPI_C2_MODFEN_MASK                       0x10u
+#define SPI_C2_MODFEN_SHIFT                      4
+#define SPI_C2_TXDMAE_MASK                       0x20u
+#define SPI_C2_TXDMAE_SHIFT                      5
+#define SPI_C2_SPLPIE_MASK                       0x40u
+#define SPI_C2_SPLPIE_SHIFT                      6
+#define SPI_C2_SPMIE_MASK                        0x80u
+#define SPI_C2_SPMIE_SHIFT                       7
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK                          0xFu
+#define SPI_BR_SPR_SHIFT                         0
+#define SPI_BR_SPR(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK                         0x70u
+#define SPI_BR_SPPR_SHIFT                        4
+#define SPI_BR_SPPR(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* S Bit Fields */
+#define SPI_S_MODF_MASK                          0x10u
+#define SPI_S_MODF_SHIFT                         4
+#define SPI_S_SPTEF_MASK                         0x20u
+#define SPI_S_SPTEF_SHIFT                        5
+#define SPI_S_SPMF_MASK                          0x40u
+#define SPI_S_SPMF_SHIFT                         6
+#define SPI_S_SPRF_MASK                          0x80u
+#define SPI_S_SPRF_SHIFT                         7
+/* D Bit Fields */
+#define SPI_D_Bits_MASK                          0xFFu
+#define SPI_D_Bits_SHIFT                         0
+#define SPI_D_Bits(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
+/* M Bit Fields */
+#define SPI_M_Bits_MASK                          0xFFu
+#define SPI_M_Bits_SHIFT                         0
+#define SPI_M_Bits(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
+
+/**
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASES                                { SPI0, SPI1 }
+
+/**
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TPM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[6];
+       uint8_t RESERVED_0[20];
+  __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x50 */
+       uint8_t RESERVED_1[48];
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TPM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define TPM_SC_PS_MASK                           0x7u
+#define TPM_SC_PS_SHIFT                          0
+#define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK                         0x18u
+#define TPM_SC_CMOD_SHIFT                        3
+#define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK                        0x20u
+#define TPM_SC_CPWMS_SHIFT                       5
+#define TPM_SC_TOIE_MASK                         0x40u
+#define TPM_SC_TOIE_SHIFT                        6
+#define TPM_SC_TOF_MASK                          0x80u
+#define TPM_SC_TOF_SHIFT                         7
+#define TPM_SC_DMA_MASK                          0x100u
+#define TPM_SC_DMA_SHIFT                         8
+/* CNT Bit Fields */
+#define TPM_CNT_COUNT_MASK                       0xFFFFu
+#define TPM_CNT_COUNT_SHIFT                      0
+#define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define TPM_MOD_MOD_MASK                         0xFFFFu
+#define TPM_MOD_MOD_SHIFT                        0
+#define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define TPM_CnSC_DMA_MASK                        0x1u
+#define TPM_CnSC_DMA_SHIFT                       0
+#define TPM_CnSC_ELSA_MASK                       0x4u
+#define TPM_CnSC_ELSA_SHIFT                      2
+#define TPM_CnSC_ELSB_MASK                       0x8u
+#define TPM_CnSC_ELSB_SHIFT                      3
+#define TPM_CnSC_MSA_MASK                        0x10u
+#define TPM_CnSC_MSA_SHIFT                       4
+#define TPM_CnSC_MSB_MASK                        0x20u
+#define TPM_CnSC_MSB_SHIFT                       5
+#define TPM_CnSC_CHIE_MASK                       0x40u
+#define TPM_CnSC_CHIE_SHIFT                      6
+#define TPM_CnSC_CHF_MASK                        0x80u
+#define TPM_CnSC_CHF_SHIFT                       7
+/* CnV Bit Fields */
+#define TPM_CnV_VAL_MASK                         0xFFFFu
+#define TPM_CnV_VAL_SHIFT                        0
+#define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
+/* STATUS Bit Fields */
+#define TPM_STATUS_CH0F_MASK                     0x1u
+#define TPM_STATUS_CH0F_SHIFT                    0
+#define TPM_STATUS_CH1F_MASK                     0x2u
+#define TPM_STATUS_CH1F_SHIFT                    1
+#define TPM_STATUS_CH2F_MASK                     0x4u
+#define TPM_STATUS_CH2F_SHIFT                    2
+#define TPM_STATUS_CH3F_MASK                     0x8u
+#define TPM_STATUS_CH3F_SHIFT                    3
+#define TPM_STATUS_CH4F_MASK                     0x10u
+#define TPM_STATUS_CH4F_SHIFT                    4
+#define TPM_STATUS_CH5F_MASK                     0x20u
+#define TPM_STATUS_CH5F_SHIFT                    5
+#define TPM_STATUS_TOF_MASK                      0x100u
+#define TPM_STATUS_TOF_SHIFT                     8
+/* CONF Bit Fields */
+#define TPM_CONF_DOZEEN_MASK                     0x20u
+#define TPM_CONF_DOZEEN_SHIFT                    5
+#define TPM_CONF_DBGMODE_MASK                    0xC0u
+#define TPM_CONF_DBGMODE_SHIFT                   6
+#define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBEEN_MASK                     0x200u
+#define TPM_CONF_GTBEEN_SHIFT                    9
+#define TPM_CONF_CSOT_MASK                       0x10000u
+#define TPM_CONF_CSOT_SHIFT                      16
+#define TPM_CONF_CSOO_MASK                       0x20000u
+#define TPM_CONF_CSOO_SHIFT                      17
+#define TPM_CONF_CROT_MASK                       0x40000u
+#define TPM_CONF_CROT_SHIFT                      18
+#define TPM_CONF_TRGSEL_MASK                     0xF000000u
+#define TPM_CONF_TRGSEL_SHIFT                    24
+#define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE                                (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0                                     ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE                                (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1                                     ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE                                (0x4003A000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2                                     ((TPM_Type *)TPM2_BASE)
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASES                                { TPM0, TPM1, TPM2 }
+
+/**
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TSI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t GENCS;                             /**< TSI General Control and Status Register, offset: 0x0 */
+  __IO uint32_t DATA;                              /**< TSI DATA Register, offset: 0x4 */
+  __IO uint32_t TSHD;                              /**< TSI Threshold Register, offset: 0x8 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TSI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_CURSW_MASK                     0x2u
+#define TSI_GENCS_CURSW_SHIFT                    1
+#define TSI_GENCS_EOSF_MASK                      0x4u
+#define TSI_GENCS_EOSF_SHIFT                     2
+#define TSI_GENCS_SCNIP_MASK                     0x8u
+#define TSI_GENCS_SCNIP_SHIFT                    3
+#define TSI_GENCS_STM_MASK                       0x10u
+#define TSI_GENCS_STM_SHIFT                      4
+#define TSI_GENCS_STPE_MASK                      0x20u
+#define TSI_GENCS_STPE_SHIFT                     5
+#define TSI_GENCS_TSIIEN_MASK                    0x40u
+#define TSI_GENCS_TSIIEN_SHIFT                   6
+#define TSI_GENCS_TSIEN_MASK                     0x80u
+#define TSI_GENCS_TSIEN_SHIFT                    7
+#define TSI_GENCS_NSCN_MASK                      0x1F00u
+#define TSI_GENCS_NSCN_SHIFT                     8
+#define TSI_GENCS_NSCN(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_PS_MASK                        0xE000u
+#define TSI_GENCS_PS_SHIFT                       13
+#define TSI_GENCS_PS(x)                          (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
+#define TSI_GENCS_EXTCHRG_MASK                   0x70000u
+#define TSI_GENCS_EXTCHRG_SHIFT                  16
+#define TSI_GENCS_EXTCHRG(x)                     (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_DVOLT_MASK                     0x180000u
+#define TSI_GENCS_DVOLT_SHIFT                    19
+#define TSI_GENCS_DVOLT(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_REFCHRG_MASK                   0xE00000u
+#define TSI_GENCS_REFCHRG_SHIFT                  21
+#define TSI_GENCS_REFCHRG(x)                     (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_MODE_MASK                      0xF000000u
+#define TSI_GENCS_MODE_SHIFT                     24
+#define TSI_GENCS_MODE(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_ESOR_MASK                      0x10000000u
+#define TSI_GENCS_ESOR_SHIFT                     28
+#define TSI_GENCS_OUTRGF_MASK                    0x80000000u
+#define TSI_GENCS_OUTRGF_SHIFT                   31
+/* DATA Bit Fields */
+#define TSI_DATA_TSICNT_MASK                     0xFFFFu
+#define TSI_DATA_TSICNT_SHIFT                    0
+#define TSI_DATA_TSICNT(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_SWTS_MASK                       0x400000u
+#define TSI_DATA_SWTS_SHIFT                      22
+#define TSI_DATA_DMAEN_MASK                      0x800000u
+#define TSI_DATA_DMAEN_SHIFT                     23
+#define TSI_DATA_TSICH_MASK                      0xF0000000u
+#define TSI_DATA_TSICH_SHIFT                     28
+#define TSI_DATA_TSICH(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
+/* TSHD Bit Fields */
+#define TSI_TSHD_THRESL_MASK                     0xFFFFu
+#define TSI_TSHD_THRESL_SHIFT                    0
+#define TSI_TSHD_THRESL(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESH_MASK                     0xFFFF0000u
+#define TSI_TSHD_THRESH_SHIFT                    16
+#define TSI_TSHD_THRESH(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
+
+/**
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE                                (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0                                     ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASES                                { TSI0 }
+
+/**
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Register: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Register: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0x8 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK                        0x1Fu
+#define UART_BDH_SBR_SHIFT                       0
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK                       0x20u
+#define UART_BDH_SBNS_SHIFT                      5
+#define UART_BDH_RXEDGIE_MASK                    0x40u
+#define UART_BDH_RXEDGIE_SHIFT                   6
+#define UART_BDH_LBKDIE_MASK                     0x80u
+#define UART_BDH_LBKDIE_SHIFT                    7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK                        0xFFu
+#define UART_BDL_SBR_SHIFT                       0
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK                          0x1u
+#define UART_C1_PT_SHIFT                         0
+#define UART_C1_PE_MASK                          0x2u
+#define UART_C1_PE_SHIFT                         1
+#define UART_C1_ILT_MASK                         0x4u
+#define UART_C1_ILT_SHIFT                        2
+#define UART_C1_WAKE_MASK                        0x8u
+#define UART_C1_WAKE_SHIFT                       3
+#define UART_C1_M_MASK                           0x10u
+#define UART_C1_M_SHIFT                          4
+#define UART_C1_RSRC_MASK                        0x20u
+#define UART_C1_RSRC_SHIFT                       5
+#define UART_C1_UARTSWAI_MASK                    0x40u
+#define UART_C1_UARTSWAI_SHIFT                   6
+#define UART_C1_LOOPS_MASK                       0x80u
+#define UART_C1_LOOPS_SHIFT                      7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK                         0x1u
+#define UART_C2_SBK_SHIFT                        0
+#define UART_C2_RWU_MASK                         0x2u
+#define UART_C2_RWU_SHIFT                        1
+#define UART_C2_RE_MASK                          0x4u
+#define UART_C2_RE_SHIFT                         2
+#define UART_C2_TE_MASK                          0x8u
+#define UART_C2_TE_SHIFT                         3
+#define UART_C2_ILIE_MASK                        0x10u
+#define UART_C2_ILIE_SHIFT                       4
+#define UART_C2_RIE_MASK                         0x20u
+#define UART_C2_RIE_SHIFT                        5
+#define UART_C2_TCIE_MASK                        0x40u
+#define UART_C2_TCIE_SHIFT                       6
+#define UART_C2_TIE_MASK                         0x80u
+#define UART_C2_TIE_SHIFT                        7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK                          0x1u
+#define UART_S1_PF_SHIFT                         0
+#define UART_S1_FE_MASK                          0x2u
+#define UART_S1_FE_SHIFT                         1
+#define UART_S1_NF_MASK                          0x4u
+#define UART_S1_NF_SHIFT                         2
+#define UART_S1_OR_MASK                          0x8u
+#define UART_S1_OR_SHIFT                         3
+#define UART_S1_IDLE_MASK                        0x10u
+#define UART_S1_IDLE_SHIFT                       4
+#define UART_S1_RDRF_MASK                        0x20u
+#define UART_S1_RDRF_SHIFT                       5
+#define UART_S1_TC_MASK                          0x40u
+#define UART_S1_TC_SHIFT                         6
+#define UART_S1_TDRE_MASK                        0x80u
+#define UART_S1_TDRE_SHIFT                       7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK                         0x1u
+#define UART_S2_RAF_SHIFT                        0
+#define UART_S2_LBKDE_MASK                       0x2u
+#define UART_S2_LBKDE_SHIFT                      1
+#define UART_S2_BRK13_MASK                       0x4u
+#define UART_S2_BRK13_SHIFT                      2
+#define UART_S2_RWUID_MASK                       0x8u
+#define UART_S2_RWUID_SHIFT                      3
+#define UART_S2_RXINV_MASK                       0x10u
+#define UART_S2_RXINV_SHIFT                      4
+#define UART_S2_RXEDGIF_MASK                     0x40u
+#define UART_S2_RXEDGIF_SHIFT                    6
+#define UART_S2_LBKDIF_MASK                      0x80u
+#define UART_S2_LBKDIF_SHIFT                     7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK                        0x1u
+#define UART_C3_PEIE_SHIFT                       0
+#define UART_C3_FEIE_MASK                        0x2u
+#define UART_C3_FEIE_SHIFT                       1
+#define UART_C3_NEIE_MASK                        0x4u
+#define UART_C3_NEIE_SHIFT                       2
+#define UART_C3_ORIE_MASK                        0x8u
+#define UART_C3_ORIE_SHIFT                       3
+#define UART_C3_TXINV_MASK                       0x10u
+#define UART_C3_TXINV_SHIFT                      4
+#define UART_C3_TXDIR_MASK                       0x20u
+#define UART_C3_TXDIR_SHIFT                      5
+#define UART_C3_T8_MASK                          0x40u
+#define UART_C3_T8_SHIFT                         6
+#define UART_C3_R8_MASK                          0x80u
+#define UART_C3_R8_SHIFT                         7
+/* D Bit Fields */
+#define UART_D_R0T0_MASK                         0x1u
+#define UART_D_R0T0_SHIFT                        0
+#define UART_D_R1T1_MASK                         0x2u
+#define UART_D_R1T1_SHIFT                        1
+#define UART_D_R2T2_MASK                         0x4u
+#define UART_D_R2T2_SHIFT                        2
+#define UART_D_R3T3_MASK                         0x8u
+#define UART_D_R3T3_SHIFT                        3
+#define UART_D_R4T4_MASK                         0x10u
+#define UART_D_R4T4_SHIFT                        4
+#define UART_D_R5T5_MASK                         0x20u
+#define UART_D_R5T5_SHIFT                        5
+#define UART_D_R6T6_MASK                         0x40u
+#define UART_D_R6T6_SHIFT                        6
+#define UART_D_R7T7_MASK                         0x80u
+#define UART_D_R7T7_SHIFT                        7
+/* C4 Bit Fields */
+#define UART_C4_LBKDDMAS_MASK                    0x8u
+#define UART_C4_LBKDDMAS_SHIFT                   3
+#define UART_C4_ILDMAS_MASK                      0x10u
+#define UART_C4_ILDMAS_SHIFT                     4
+#define UART_C4_RDMAS_MASK                       0x20u
+#define UART_C4_RDMAS_SHIFT                      5
+#define UART_C4_TCDMAS_MASK                      0x40u
+#define UART_C4_TCDMAS_SHIFT                     6
+#define UART_C4_TDMAS_MASK                       0x80u
+#define UART_C4_TDMAS_SHIFT                      7
+
+/**
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART1 base address */
+#define UART1_BASE                               (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1                                    ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASES                               { UART1, UART2 }
+
+/**
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UARTLP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer
+ * @{
+ */
+
+/** UARTLP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Register High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Register Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __IO uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
+  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
+  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
+  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
+} UARTLP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UARTLP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UARTLP_Register_Masks UARTLP Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UARTLP_BDH_SBR_MASK                      0x1Fu
+#define UARTLP_BDH_SBR_SHIFT                     0
+#define UARTLP_BDH_SBR(x)                        (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK)
+#define UARTLP_BDH_SBNS_MASK                     0x20u
+#define UARTLP_BDH_SBNS_SHIFT                    5
+#define UARTLP_BDH_RXEDGIE_MASK                  0x40u
+#define UARTLP_BDH_RXEDGIE_SHIFT                 6
+#define UARTLP_BDH_LBKDIE_MASK                   0x80u
+#define UARTLP_BDH_LBKDIE_SHIFT                  7
+/* BDL Bit Fields */
+#define UARTLP_BDL_SBR_MASK                      0xFFu
+#define UARTLP_BDL_SBR_SHIFT                     0
+#define UARTLP_BDL_SBR(x)                        (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UARTLP_C1_PT_MASK                        0x1u
+#define UARTLP_C1_PT_SHIFT                       0
+#define UARTLP_C1_PE_MASK                        0x2u
+#define UARTLP_C1_PE_SHIFT                       1
+#define UARTLP_C1_ILT_MASK                       0x4u
+#define UARTLP_C1_ILT_SHIFT                      2
+#define UARTLP_C1_WAKE_MASK                      0x8u
+#define UARTLP_C1_WAKE_SHIFT                     3
+#define UARTLP_C1_M_MASK                         0x10u
+#define UARTLP_C1_M_SHIFT                        4
+#define UARTLP_C1_RSRC_MASK                      0x20u
+#define UARTLP_C1_RSRC_SHIFT                     5
+#define UARTLP_C1_DOZEEN_MASK                    0x40u
+#define UARTLP_C1_DOZEEN_SHIFT                   6
+#define UARTLP_C1_LOOPS_MASK                     0x80u
+#define UARTLP_C1_LOOPS_SHIFT                    7
+/* C2 Bit Fields */
+#define UARTLP_C2_SBK_MASK                       0x1u
+#define UARTLP_C2_SBK_SHIFT                      0
+#define UARTLP_C2_RWU_MASK                       0x2u
+#define UARTLP_C2_RWU_SHIFT                      1
+#define UARTLP_C2_RE_MASK                        0x4u
+#define UARTLP_C2_RE_SHIFT                       2
+#define UARTLP_C2_TE_MASK                        0x8u
+#define UARTLP_C2_TE_SHIFT                       3
+#define UARTLP_C2_ILIE_MASK                      0x10u
+#define UARTLP_C2_ILIE_SHIFT                     4
+#define UARTLP_C2_RIE_MASK                       0x20u
+#define UARTLP_C2_RIE_SHIFT                      5
+#define UARTLP_C2_TCIE_MASK                      0x40u
+#define UARTLP_C2_TCIE_SHIFT                     6
+#define UARTLP_C2_TIE_MASK                       0x80u
+#define UARTLP_C2_TIE_SHIFT                      7
+/* S1 Bit Fields */
+#define UARTLP_S1_PF_MASK                        0x1u
+#define UARTLP_S1_PF_SHIFT                       0
+#define UARTLP_S1_FE_MASK                        0x2u
+#define UARTLP_S1_FE_SHIFT                       1
+#define UARTLP_S1_NF_MASK                        0x4u
+#define UARTLP_S1_NF_SHIFT                       2
+#define UARTLP_S1_OR_MASK                        0x8u
+#define UARTLP_S1_OR_SHIFT                       3
+#define UARTLP_S1_IDLE_MASK                      0x10u
+#define UARTLP_S1_IDLE_SHIFT                     4
+#define UARTLP_S1_RDRF_MASK                      0x20u
+#define UARTLP_S1_RDRF_SHIFT                     5
+#define UARTLP_S1_TC_MASK                        0x40u
+#define UARTLP_S1_TC_SHIFT                       6
+#define UARTLP_S1_TDRE_MASK                      0x80u
+#define UARTLP_S1_TDRE_SHIFT                     7
+/* S2 Bit Fields */
+#define UARTLP_S2_RAF_MASK                       0x1u
+#define UARTLP_S2_RAF_SHIFT                      0
+#define UARTLP_S2_LBKDE_MASK                     0x2u
+#define UARTLP_S2_LBKDE_SHIFT                    1
+#define UARTLP_S2_BRK13_MASK                     0x4u
+#define UARTLP_S2_BRK13_SHIFT                    2
+#define UARTLP_S2_RWUID_MASK                     0x8u
+#define UARTLP_S2_RWUID_SHIFT                    3
+#define UARTLP_S2_RXINV_MASK                     0x10u
+#define UARTLP_S2_RXINV_SHIFT                    4
+#define UARTLP_S2_MSBF_MASK                      0x20u
+#define UARTLP_S2_MSBF_SHIFT                     5
+#define UARTLP_S2_RXEDGIF_MASK                   0x40u
+#define UARTLP_S2_RXEDGIF_SHIFT                  6
+#define UARTLP_S2_LBKDIF_MASK                    0x80u
+#define UARTLP_S2_LBKDIF_SHIFT                   7
+/* C3 Bit Fields */
+#define UARTLP_C3_PEIE_MASK                      0x1u
+#define UARTLP_C3_PEIE_SHIFT                     0
+#define UARTLP_C3_FEIE_MASK                      0x2u
+#define UARTLP_C3_FEIE_SHIFT                     1
+#define UARTLP_C3_NEIE_MASK                      0x4u
+#define UARTLP_C3_NEIE_SHIFT                     2
+#define UARTLP_C3_ORIE_MASK                      0x8u
+#define UARTLP_C3_ORIE_SHIFT                     3
+#define UARTLP_C3_TXINV_MASK                     0x10u
+#define UARTLP_C3_TXINV_SHIFT                    4
+#define UARTLP_C3_TXDIR_MASK                     0x20u
+#define UARTLP_C3_TXDIR_SHIFT                    5
+#define UARTLP_C3_R9T8_MASK                      0x40u
+#define UARTLP_C3_R9T8_SHIFT                     6
+#define UARTLP_C3_R8T9_MASK                      0x80u
+#define UARTLP_C3_R8T9_SHIFT                     7
+/* D Bit Fields */
+#define UARTLP_D_R0T0_MASK                       0x1u
+#define UARTLP_D_R0T0_SHIFT                      0
+#define UARTLP_D_R1T1_MASK                       0x2u
+#define UARTLP_D_R1T1_SHIFT                      1
+#define UARTLP_D_R2T2_MASK                       0x4u
+#define UARTLP_D_R2T2_SHIFT                      2
+#define UARTLP_D_R3T3_MASK                       0x8u
+#define UARTLP_D_R3T3_SHIFT                      3
+#define UARTLP_D_R4T4_MASK                       0x10u
+#define UARTLP_D_R4T4_SHIFT                      4
+#define UARTLP_D_R5T5_MASK                       0x20u
+#define UARTLP_D_R5T5_SHIFT                      5
+#define UARTLP_D_R6T6_MASK                       0x40u
+#define UARTLP_D_R6T6_SHIFT                      6
+#define UARTLP_D_R7T7_MASK                       0x80u
+#define UARTLP_D_R7T7_SHIFT                      7
+/* MA1 Bit Fields */
+#define UARTLP_MA1_MA_MASK                       0xFFu
+#define UARTLP_MA1_MA_SHIFT                      0
+#define UARTLP_MA1_MA(x)                         (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UARTLP_MA2_MA_MASK                       0xFFu
+#define UARTLP_MA2_MA_SHIFT                      0
+#define UARTLP_MA2_MA(x)                         (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UARTLP_C4_OSR_MASK                       0x1Fu
+#define UARTLP_C4_OSR_SHIFT                      0
+#define UARTLP_C4_OSR(x)                         (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK)
+#define UARTLP_C4_M10_MASK                       0x20u
+#define UARTLP_C4_M10_SHIFT                      5
+#define UARTLP_C4_MAEN2_MASK                     0x40u
+#define UARTLP_C4_MAEN2_SHIFT                    6
+#define UARTLP_C4_MAEN1_MASK                     0x80u
+#define UARTLP_C4_MAEN1_SHIFT                    7
+/* C5 Bit Fields */
+#define UARTLP_C5_RESYNCDIS_MASK                 0x1u
+#define UARTLP_C5_RESYNCDIS_SHIFT                0
+#define UARTLP_C5_BOTHEDGE_MASK                  0x2u
+#define UARTLP_C5_BOTHEDGE_SHIFT                 1
+#define UARTLP_C5_RDMAE_MASK                     0x20u
+#define UARTLP_C5_RDMAE_SHIFT                    5
+#define UARTLP_C5_TDMAE_MASK                     0x80u
+#define UARTLP_C5_TDMAE_SHIFT                    7
+
+/**
+ * @}
+ */ /* end of group UARTLP_Register_Masks */
+
+
+/* UARTLP - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE                               (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0                                    ((UARTLP_Type *)UART0_BASE)
+/** Array initializer of UARTLP peripheral base pointers */
+#define UARTLP_BASES                             { UART0 }
+
+/**
+ * @}
+ */ /* end of group UARTLP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[3];
+  __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status register, offset: 0x10 */
+       uint8_t RESERVED_4[3];
+  __IO uint8_t OTGICR;                             /**< OTG Interrupt Control Register, offset: 0x14 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t OTGSTAT;                            /**< OTG Status register, offset: 0x18 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_7[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_8[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_11[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_14[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page Register 1, offset: 0x9C */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number Register Low, offset: 0xA0 */
+       uint8_t RESERVED_16[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number Register High, offset: 0xA4 */
+       uint8_t RESERVED_17[3];
+  __IO uint8_t TOKEN;                              /**< Token register, offset: 0xA8 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t SOFTHLD;                            /**< SOF Threshold Register, offset: 0xAC */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_20[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_21[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_22[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control Register 0, offset: 0x10C */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK                        0x3Fu
+#define USB_PERID_ID_SHIFT                       0
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK                      0x3Fu
+#define USB_IDCOMP_NID_SHIFT                     0
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK                         0xFFu
+#define USB_REV_REV_SHIFT                        0
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK                  0x1u
+#define USB_ADDINFO_IEHOST_SHIFT                 0
+#define USB_ADDINFO_IRQNUM_MASK                  0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT                 3
+#define USB_ADDINFO_IRQNUM(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK               0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT              0
+#define USB_OTGISTAT_B_SESS_CHG_MASK             0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT            2
+#define USB_OTGISTAT_SESSVLDCHG_MASK             0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT            3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK         0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        5
+#define USB_OTGISTAT_ONEMSEC_MASK                0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT               6
+#define USB_OTGISTAT_IDCHG_MASK                  0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT                 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK                  0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT                 0
+#define USB_OTGICR_BSESSEN_MASK                  0x4u
+#define USB_OTGICR_BSESSEN_SHIFT                 2
+#define USB_OTGICR_SESSVLDEN_MASK                0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT               3
+#define USB_OTGICR_LINESTATEEN_MASK              0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT             5
+#define USB_OTGICR_ONEMSECEN_MASK                0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT               6
+#define USB_OTGICR_IDEN_MASK                     0x80u
+#define USB_OTGICR_IDEN_SHIFT                    7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK                0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT               0
+#define USB_OTGSTAT_BSESSEND_MASK                0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT               2
+#define USB_OTGSTAT_SESS_VLD_MASK                0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT               3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK         0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        5
+#define USB_OTGSTAT_ONEMSECEN_MASK               0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT              6
+#define USB_OTGSTAT_ID_MASK                      0x80u
+#define USB_OTGSTAT_ID_SHIFT                     7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK                    0x4u
+#define USB_OTGCTL_OTGEN_SHIFT                   2
+#define USB_OTGCTL_DMLOW_MASK                    0x10u
+#define USB_OTGCTL_DMLOW_SHIFT                   4
+#define USB_OTGCTL_DPLOW_MASK                    0x20u
+#define USB_OTGCTL_DPLOW_SHIFT                   5
+#define USB_OTGCTL_DPHIGH_MASK                   0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT                  7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK                    0x1u
+#define USB_ISTAT_USBRST_SHIFT                   0
+#define USB_ISTAT_ERROR_MASK                     0x2u
+#define USB_ISTAT_ERROR_SHIFT                    1
+#define USB_ISTAT_SOFTOK_MASK                    0x4u
+#define USB_ISTAT_SOFTOK_SHIFT                   2
+#define USB_ISTAT_TOKDNE_MASK                    0x8u
+#define USB_ISTAT_TOKDNE_SHIFT                   3
+#define USB_ISTAT_SLEEP_MASK                     0x10u
+#define USB_ISTAT_SLEEP_SHIFT                    4
+#define USB_ISTAT_RESUME_MASK                    0x20u
+#define USB_ISTAT_RESUME_SHIFT                   5
+#define USB_ISTAT_ATTACH_MASK                    0x40u
+#define USB_ISTAT_ATTACH_SHIFT                   6
+#define USB_ISTAT_STALL_MASK                     0x80u
+#define USB_ISTAT_STALL_SHIFT                    7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK                  0x1u
+#define USB_INTEN_USBRSTEN_SHIFT                 0
+#define USB_INTEN_ERROREN_MASK                   0x2u
+#define USB_INTEN_ERROREN_SHIFT                  1
+#define USB_INTEN_SOFTOKEN_MASK                  0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT                 2
+#define USB_INTEN_TOKDNEEN_MASK                  0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT                 3
+#define USB_INTEN_SLEEPEN_MASK                   0x10u
+#define USB_INTEN_SLEEPEN_SHIFT                  4
+#define USB_INTEN_RESUMEEN_MASK                  0x20u
+#define USB_INTEN_RESUMEEN_SHIFT                 5
+#define USB_INTEN_ATTACHEN_MASK                  0x40u
+#define USB_INTEN_ATTACHEN_SHIFT                 6
+#define USB_INTEN_STALLEN_MASK                   0x80u
+#define USB_INTEN_STALLEN_SHIFT                  7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK                  0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT                 0
+#define USB_ERRSTAT_CRC5EOF_MASK                 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT                1
+#define USB_ERRSTAT_CRC16_MASK                   0x4u
+#define USB_ERRSTAT_CRC16_SHIFT                  2
+#define USB_ERRSTAT_DFN8_MASK                    0x8u
+#define USB_ERRSTAT_DFN8_SHIFT                   3
+#define USB_ERRSTAT_BTOERR_MASK                  0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT                 4
+#define USB_ERRSTAT_DMAERR_MASK                  0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT                 5
+#define USB_ERRSTAT_BTSERR_MASK                  0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT                 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK                  0x1u
+#define USB_ERREN_PIDERREN_SHIFT                 0
+#define USB_ERREN_CRC5EOFEN_MASK                 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT                1
+#define USB_ERREN_CRC16EN_MASK                   0x4u
+#define USB_ERREN_CRC16EN_SHIFT                  2
+#define USB_ERREN_DFN8EN_MASK                    0x8u
+#define USB_ERREN_DFN8EN_SHIFT                   3
+#define USB_ERREN_BTOERREN_MASK                  0x10u
+#define USB_ERREN_BTOERREN_SHIFT                 4
+#define USB_ERREN_DMAERREN_MASK                  0x20u
+#define USB_ERREN_DMAERREN_SHIFT                 5
+#define USB_ERREN_BTSERREN_MASK                  0x80u
+#define USB_ERREN_BTSERREN_SHIFT                 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK                        0x4u
+#define USB_STAT_ODD_SHIFT                       2
+#define USB_STAT_TX_MASK                         0x8u
+#define USB_STAT_TX_SHIFT                        3
+#define USB_STAT_ENDP_MASK                       0xF0u
+#define USB_STAT_ENDP_SHIFT                      4
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK                  0x1u
+#define USB_CTL_USBENSOFEN_SHIFT                 0
+#define USB_CTL_ODDRST_MASK                      0x2u
+#define USB_CTL_ODDRST_SHIFT                     1
+#define USB_CTL_RESUME_MASK                      0x4u
+#define USB_CTL_RESUME_SHIFT                     2
+#define USB_CTL_HOSTMODEEN_MASK                  0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT                 3
+#define USB_CTL_RESET_MASK                       0x10u
+#define USB_CTL_RESET_SHIFT                      4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         5
+#define USB_CTL_SE0_MASK                         0x40u
+#define USB_CTL_SE0_SHIFT                        6
+#define USB_CTL_JSTATE_MASK                      0x80u
+#define USB_CTL_JSTATE_SHIFT                     7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK                       0x7Fu
+#define USB_ADDR_ADDR_SHIFT                      0
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK                       0x80u
+#define USB_ADDR_LSEN_SHIFT                      7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK                  0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT                 1
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK                     0xFFu
+#define USB_FRMNUML_FRM_SHIFT                    0
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK                     0x7u
+#define USB_FRMNUMH_FRM_SHIFT                    0
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK                0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT               0
+#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK                  0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT                 4
+#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK                     0xFFu
+#define USB_SOFTHLD_CNT_SHIFT                    0
+#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT                 0
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT                 0
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK                    0x1u
+#define USB_ENDPT_EPHSHK_SHIFT                   0
+#define USB_ENDPT_EPSTALL_MASK                   0x2u
+#define USB_ENDPT_EPSTALL_SHIFT                  1
+#define USB_ENDPT_EPTXEN_MASK                    0x4u
+#define USB_ENDPT_EPTXEN_SHIFT                   2
+#define USB_ENDPT_EPRXEN_MASK                    0x8u
+#define USB_ENDPT_EPRXEN_SHIFT                   3
+#define USB_ENDPT_EPCTLDIS_MASK                  0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT                 4
+#define USB_ENDPT_RETRYDIS_MASK                  0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT                 6
+#define USB_ENDPT_HOSTWOHUB_MASK                 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT                7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK                     0x40u
+#define USB_USBCTRL_PDE_SHIFT                    6
+#define USB_USBCTRL_SUSP_MASK                    0x80u
+#define USB_USBCTRL_SUSP_SHIFT                   7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK                    0x10u
+#define USB_OBSERVE_DMPD_SHIFT                   4
+#define USB_OBSERVE_DPPD_MASK                    0x40u
+#define USB_OBSERVE_DPPD_SHIFT                   6
+#define USB_OBSERVE_DPPU_MASK                    0x80u
+#define USB_OBSERVE_DPPU_SHIFT                   7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         0
+#define USB_USBTRC0_SYNC_DET_MASK                0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT               1
+#define USB_USBTRC0_USBRESMEN_MASK               0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT              5
+#define USB_USBTRC0_USBRESET_MASK                0x80u
+#define USB_USBTRC0_USBRESET_SHIFT               7
+
+/**
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASES                                { USB0 }
+
+/**
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/**
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Backward Compatibility
+   ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+/* No backward compatibility issues. */
+
+/**
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif  /* #if !defined(MKL25Z4_H_) */
+
+/* MKL25Z4.h, eof. */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x20000  {    ; load region size_region (32k)
+  ER_IROM1 0x00000000 0x20000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
+  ; 0x4000 - 0xC0 = 0x3F40
+  RW_IRAM1 0x1FFFF0C0 0x3F40 {
+   .ANY (+RW +ZI)
+  }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,353 @@
+;/*****************************************************************************
+; * @file:    startup_MKL25Z4.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; *           MKL25Z4
+; * @version: 1.1
+; * @date:    2012-6-21
+; *
+; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+Stack_Mem       SPACE   Stack_Size
+__initial_sp        EQU     0x20003000  ; Top of RAM
+
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp  ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler  ; NMI Handler
+                DCD     HardFault_Handler  ; Hard Fault Handler
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     SVC_Handler  ; SVCall Handler
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     PendSV_Handler  ; PendSV Handler
+                DCD     SysTick_Handler  ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DMA0_IRQHandler  ; DMA channel 0 transfer complete interrupt
+                DCD     DMA1_IRQHandler  ; DMA channel 1 transfer complete interrupt
+                DCD     DMA2_IRQHandler  ; DMA channel 2 transfer complete interrupt
+                DCD     DMA3_IRQHandler  ; DMA channel 3 transfer complete interrupt
+                DCD     Reserved20_IRQHandler  ; Reserved interrupt 20
+                DCD     FTFA_IRQHandler  ; FTFA interrupt
+                DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
+                DCD     LLW_IRQHandler  ; Low Leakage Wakeup
+                DCD     I2C0_IRQHandler  ; I2C0 interrupt
+                DCD     I2C1_IRQHandler  ; I2C0 interrupt 25
+                DCD     SPI0_IRQHandler  ; SPI0 interrupt
+                DCD     SPI1_IRQHandler  ; SPI1 interrupt
+                DCD     UART0_IRQHandler  ; UART0 status/error interrupt
+                DCD     UART1_IRQHandler  ; UART1 status/error interrupt
+                DCD     UART2_IRQHandler  ; UART2 status/error interrupt
+                DCD     ADC0_IRQHandler  ; ADC0 interrupt
+                DCD     CMP0_IRQHandler  ; CMP0 interrupt
+                DCD     TPM0_IRQHandler  ; TPM0 fault, overflow and channels interrupt
+                DCD     TPM1_IRQHandler  ; TPM1 fault, overflow and channels interrupt
+                DCD     TPM2_IRQHandler  ; TPM2 fault, overflow and channels interrupt
+                DCD     RTC_IRQHandler  ; RTC interrupt
+                DCD     RTC_Seconds_IRQHandler  ; RTC seconds interrupt
+                DCD     PIT_IRQHandler  ; PIT timer interrupt
+                DCD     Reserved39_IRQHandler  ; Reserved interrupt 39
+                DCD     USB0_IRQHandler  ; USB0 interrupt
+                DCD     DAC0_IRQHandler  ; DAC interrupt
+                DCD     TSI0_IRQHandler  ; TSI0 interrupt
+                DCD     MCG_IRQHandler  ; MCG interrupt
+                DCD     LPTimer_IRQHandler  ; LPTimer interrupt
+                DCD     Reserved45_IRQHandler  ; Reserved interrupt 45
+                DCD     PORTA_IRQHandler  ; Port A interrupt
+                DCD     PORTD_IRQHandler  ; Port D interrupt
+__Vectors_End
+
+__Vectors_Size 	EQU     __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
+;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
+;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
+;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
+;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
+;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
+;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
+;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> Program flash protection bytes (FPROT)
+;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+;     <i> Each bit protects a 1/32 region of the program flash memory.
+;     <h> FPROT0
+;       <i> Program flash protection bytes
+;       <i> 1/32 - 8/32 region
+;       <o.0>   FPROT0.0
+;       <o.1>   FPROT0.1
+;       <o.2>   FPROT0.2
+;       <o.3>   FPROT0.3
+;       <o.4>   FPROT0.4
+;       <o.5>   FPROT0.5
+;       <o.6>   FPROT0.6
+;       <o.7>   FPROT0.7
+nFPROT0         EQU     0x00
+FPROT0          EQU     nFPROT0:EOR:0xFF
+;     </h>
+;     <h> FPROT1
+;       <i> Program Flash Region Protect Register 1
+;       <i> 9/32 - 16/32 region
+;       <o.0>   FPROT1.0
+;       <o.1>   FPROT1.1
+;       <o.2>   FPROT1.2
+;       <o.3>   FPROT1.3
+;       <o.4>   FPROT1.4
+;       <o.5>   FPROT1.5
+;       <o.6>   FPROT1.6
+;       <o.7>   FPROT1.7
+nFPROT1         EQU     0x00
+FPROT1          EQU     nFPROT1:EOR:0xFF
+;     </h>
+;     <h> FPROT2
+;       <i> Program Flash Region Protect Register 2
+;       <i> 17/32 - 24/32 region
+;       <o.0>   FPROT2.0
+;       <o.1>   FPROT2.1
+;       <o.2>   FPROT2.2
+;       <o.3>   FPROT2.3
+;       <o.4>   FPROT2.4
+;       <o.5>   FPROT2.5
+;       <o.6>   FPROT2.6
+;       <o.7>   FPROT2.7
+nFPROT2         EQU     0x00
+FPROT2          EQU     nFPROT2:EOR:0xFF
+;     </h>
+;     <h> FPROT3
+;       <i> Program Flash Region Protect Register 3
+;       <i> 25/32 - 32/32 region
+;       <o.0>   FPROT3.0
+;       <o.1>   FPROT3.1
+;       <o.2>   FPROT3.2
+;       <o.3>   FPROT3.3
+;       <o.4>   FPROT3.4
+;       <o.5>   FPROT3.5
+;       <o.6>   FPROT3.6
+;       <o.7>   FPROT3.7
+nFPROT3         EQU     0x00
+FPROT3          EQU     nFPROT3:EOR:0xFF
+;     </h>
+;   </h>
+;   </h>
+;   <h> Flash nonvolatile option byte (FOPT)
+;     <i> Allows the user to customize the operation of the MCU at boot time.
+;     <o.0>  LPBOOT0
+;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
+;       <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
+;     <o.4>  LPBOOT1
+;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
+;       <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
+;     <o.2>  NMI_DIS
+;       <0=> NMI interrupts are always blocked
+;       <1=> NMI pin/interrupts reset default to enabled
+;     <o.3>  RESET_PIN_CFG
+;       <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
+;       <1=> RESET pin is dedicated
+;     <o.3>  FAST_INIT
+;       <0=> Slower initialization
+;       <1=> Fast Initialization
+FOPT            EQU     0xFF
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;         <i> This bits define the security state of the MCU.
+;     <o.2..3> FSLACC
+;       <2=> Freescale factory access denied
+;       <3=> Freescale factory access granted
+;         <i> Freescale Failure Analysis Access Code
+;         <i> This bits define the security state of the MCU.
+;     <o.4..5> MEEN
+;       <2=> Mass erase is disabled
+;       <3=> Mass erase is enabled
+;         <i> Mass Erase Enable Bits
+;         <i> Enables and disables mass erase capability of the FTFL module
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor key Security Enable
+;         <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC            EQU     0xFE
+;   </h>
+
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    |.ARM.__at_0x400|, CODE, READONLY
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     FPROT0,     FPROT1,     FPROT2,     FPROT3
+                DCB     FSEC,       FOPT,       0xFF,     0xFF
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DMA0_IRQHandler     [WEAK]
+                EXPORT  DMA1_IRQHandler     [WEAK]
+                EXPORT  DMA2_IRQHandler     [WEAK]
+                EXPORT  DMA3_IRQHandler     [WEAK]
+                EXPORT  Reserved20_IRQHandler     [WEAK]
+                EXPORT  FTFA_IRQHandler     [WEAK]
+                EXPORT  LVD_LVW_IRQHandler     [WEAK]
+                EXPORT  LLW_IRQHandler     [WEAK]
+                EXPORT  I2C0_IRQHandler     [WEAK]
+                EXPORT  I2C1_IRQHandler     [WEAK]
+                EXPORT  SPI0_IRQHandler     [WEAK]
+                EXPORT  SPI1_IRQHandler     [WEAK]
+                EXPORT  UART0_IRQHandler     [WEAK]
+                EXPORT  UART1_IRQHandler     [WEAK]
+                EXPORT  UART2_IRQHandler     [WEAK]
+                EXPORT  ADC0_IRQHandler     [WEAK]
+                EXPORT  CMP0_IRQHandler     [WEAK]
+                EXPORT  TPM0_IRQHandler     [WEAK]
+                EXPORT  TPM1_IRQHandler     [WEAK]
+                EXPORT  TPM2_IRQHandler     [WEAK]
+                EXPORT  RTC_IRQHandler     [WEAK]
+                EXPORT  RTC_Seconds_IRQHandler     [WEAK]
+                EXPORT  PIT_IRQHandler     [WEAK]
+                EXPORT  Reserved39_IRQHandler     [WEAK]
+                EXPORT  USB0_IRQHandler     [WEAK]
+                EXPORT  DAC0_IRQHandler     [WEAK]
+                EXPORT  TSI0_IRQHandler     [WEAK]
+                EXPORT  MCG_IRQHandler     [WEAK]
+                EXPORT  LPTimer_IRQHandler     [WEAK]
+                EXPORT  Reserved45_IRQHandler     [WEAK]
+                EXPORT  PORTA_IRQHandler     [WEAK]
+                EXPORT  PORTD_IRQHandler     [WEAK]
+                EXPORT  DefaultISR                      [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+Reserved39_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+Reserved45_IRQHandler
+PORTA_IRQHandler
+PORTD_IRQHandler
+DefaultISR
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/sys.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_ARM_STD/MKL25Z4.sct	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x20000  {    ; load region size_region (32k)
+  ER_IROM1 0x00000000 0x20000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
+  ; 0x4000 - 0xC0 = 0x3F40
+  RW_IRAM1 0x1FFFF0C0 0x3F40 {
+   .ANY (+RW +ZI)
+  }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_ARM_STD/startup_MKL25Z4.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,332 @@
+;/*****************************************************************************
+; * @file:    startup_MKL25Z4.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; *           MKL25Z4
+; * @version: 1.1
+; * @date:    2012-6-21
+; *
+; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp        EQU     0x20003000  ; Top of RAM
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp  ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler  ; NMI Handler
+                DCD     HardFault_Handler  ; Hard Fault Handler
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     SVC_Handler  ; SVCall Handler
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     PendSV_Handler  ; PendSV Handler
+                DCD     SysTick_Handler  ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DMA0_IRQHandler  ; DMA channel 0 transfer complete interrupt
+                DCD     DMA1_IRQHandler  ; DMA channel 1 transfer complete interrupt
+                DCD     DMA2_IRQHandler  ; DMA channel 2 transfer complete interrupt
+                DCD     DMA3_IRQHandler  ; DMA channel 3 transfer complete interrupt
+                DCD     Reserved20_IRQHandler  ; Reserved interrupt 20
+                DCD     FTFA_IRQHandler  ; FTFA interrupt
+                DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
+                DCD     LLW_IRQHandler  ; Low Leakage Wakeup
+                DCD     I2C0_IRQHandler  ; I2C0 interrupt
+                DCD     I2C1_IRQHandler  ; I2C0 interrupt 25
+                DCD     SPI0_IRQHandler  ; SPI0 interrupt
+                DCD     SPI1_IRQHandler  ; SPI1 interrupt
+                DCD     UART0_IRQHandler  ; UART0 status/error interrupt
+                DCD     UART1_IRQHandler  ; UART1 status/error interrupt
+                DCD     UART2_IRQHandler  ; UART2 status/error interrupt
+                DCD     ADC0_IRQHandler  ; ADC0 interrupt
+                DCD     CMP0_IRQHandler  ; CMP0 interrupt
+                DCD     TPM0_IRQHandler  ; TPM0 fault, overflow and channels interrupt
+                DCD     TPM1_IRQHandler  ; TPM1 fault, overflow and channels interrupt
+                DCD     TPM2_IRQHandler  ; TPM2 fault, overflow and channels interrupt
+                DCD     RTC_IRQHandler  ; RTC interrupt
+                DCD     RTC_Seconds_IRQHandler  ; RTC seconds interrupt
+                DCD     PIT_IRQHandler  ; PIT timer interrupt
+                DCD     Reserved39_IRQHandler  ; Reserved interrupt 39
+                DCD     USB0_IRQHandler  ; USB0 interrupt
+                DCD     DAC0_IRQHandler  ; DAC interrupt
+                DCD     TSI0_IRQHandler  ; TSI0 interrupt
+                DCD     MCG_IRQHandler  ; MCG interrupt
+                DCD     LPTimer_IRQHandler  ; LPTimer interrupt
+                DCD     Reserved45_IRQHandler  ; Reserved interrupt 45
+                DCD     PORTA_IRQHandler  ; Port A interrupt
+                DCD     PORTD_IRQHandler  ; Port D interrupt
+__Vectors_End
+
+__Vectors_Size 	EQU     __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
+;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
+;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
+;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
+;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
+;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
+;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
+;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> Program flash protection bytes (FPROT)
+;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+;     <i> Each bit protects a 1/32 region of the program flash memory.
+;     <h> FPROT0
+;       <i> Program flash protection bytes
+;       <i> 1/32 - 8/32 region
+;       <o.0>   FPROT0.0
+;       <o.1>   FPROT0.1
+;       <o.2>   FPROT0.2
+;       <o.3>   FPROT0.3
+;       <o.4>   FPROT0.4
+;       <o.5>   FPROT0.5
+;       <o.6>   FPROT0.6
+;       <o.7>   FPROT0.7
+nFPROT0         EQU     0x00
+FPROT0          EQU     nFPROT0:EOR:0xFF
+;     </h>
+;     <h> FPROT1
+;       <i> Program Flash Region Protect Register 1
+;       <i> 9/32 - 16/32 region
+;       <o.0>   FPROT1.0
+;       <o.1>   FPROT1.1
+;       <o.2>   FPROT1.2
+;       <o.3>   FPROT1.3
+;       <o.4>   FPROT1.4
+;       <o.5>   FPROT1.5
+;       <o.6>   FPROT1.6
+;       <o.7>   FPROT1.7
+nFPROT1         EQU     0x00
+FPROT1          EQU     nFPROT1:EOR:0xFF
+;     </h>
+;     <h> FPROT2
+;       <i> Program Flash Region Protect Register 2
+;       <i> 17/32 - 24/32 region
+;       <o.0>   FPROT2.0
+;       <o.1>   FPROT2.1
+;       <o.2>   FPROT2.2
+;       <o.3>   FPROT2.3
+;       <o.4>   FPROT2.4
+;       <o.5>   FPROT2.5
+;       <o.6>   FPROT2.6
+;       <o.7>   FPROT2.7
+nFPROT2         EQU     0x00
+FPROT2          EQU     nFPROT2:EOR:0xFF
+;     </h>
+;     <h> FPROT3
+;       <i> Program Flash Region Protect Register 3
+;       <i> 25/32 - 32/32 region
+;       <o.0>   FPROT3.0
+;       <o.1>   FPROT3.1
+;       <o.2>   FPROT3.2
+;       <o.3>   FPROT3.3
+;       <o.4>   FPROT3.4
+;       <o.5>   FPROT3.5
+;       <o.6>   FPROT3.6
+;       <o.7>   FPROT3.7
+nFPROT3         EQU     0x00
+FPROT3          EQU     nFPROT3:EOR:0xFF
+;     </h>
+;   </h>
+;   </h>
+;   <h> Flash nonvolatile option byte (FOPT)
+;     <i> Allows the user to customize the operation of the MCU at boot time.
+;     <o.0>  LPBOOT0
+;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
+;       <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
+;     <o.4>  LPBOOT1
+;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
+;       <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
+;     <o.2>  NMI_DIS
+;       <0=> NMI interrupts are always blocked
+;       <1=> NMI pin/interrupts reset default to enabled
+;     <o.3>  RESET_PIN_CFG
+;       <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
+;       <1=> RESET pin is dedicated
+;     <o.3>  FAST_INIT
+;       <0=> Slower initialization
+;       <1=> Fast Initialization
+FOPT            EQU     0xFF
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;         <i> This bits define the security state of the MCU.
+;     <o.2..3> FSLACC
+;       <2=> Freescale factory access denied
+;       <3=> Freescale factory access granted
+;         <i> Freescale Failure Analysis Access Code
+;         <i> This bits define the security state of the MCU.
+;     <o.4..5> MEEN
+;       <2=> Mass erase is disabled
+;       <3=> Mass erase is enabled
+;         <i> Mass Erase Enable Bits
+;         <i> Enables and disables mass erase capability of the FTFL module
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor key Security Enable
+;         <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC            EQU     0xFE
+;   </h>
+
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    |.ARM.__at_0x400|, CODE, READONLY
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     FPROT0,     FPROT1,     FPROT2,     FPROT3
+                DCB     FSEC,       FOPT,       0xFF,     0xFF
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DMA0_IRQHandler     [WEAK]
+                EXPORT  DMA1_IRQHandler     [WEAK]
+                EXPORT  DMA2_IRQHandler     [WEAK]
+                EXPORT  DMA3_IRQHandler     [WEAK]
+                EXPORT  Reserved20_IRQHandler     [WEAK]
+                EXPORT  FTFA_IRQHandler     [WEAK]
+                EXPORT  LVD_LVW_IRQHandler     [WEAK]
+                EXPORT  LLW_IRQHandler     [WEAK]
+                EXPORT  I2C0_IRQHandler     [WEAK]
+                EXPORT  I2C1_IRQHandler     [WEAK]
+                EXPORT  SPI0_IRQHandler     [WEAK]
+                EXPORT  SPI1_IRQHandler     [WEAK]
+                EXPORT  UART0_IRQHandler     [WEAK]
+                EXPORT  UART1_IRQHandler     [WEAK]
+                EXPORT  UART2_IRQHandler     [WEAK]
+                EXPORT  ADC0_IRQHandler     [WEAK]
+                EXPORT  CMP0_IRQHandler     [WEAK]
+                EXPORT  TPM0_IRQHandler     [WEAK]
+                EXPORT  TPM1_IRQHandler     [WEAK]
+                EXPORT  TPM2_IRQHandler     [WEAK]
+                EXPORT  RTC_IRQHandler     [WEAK]
+                EXPORT  RTC_Seconds_IRQHandler     [WEAK]
+                EXPORT  PIT_IRQHandler     [WEAK]
+                EXPORT  Reserved39_IRQHandler     [WEAK]
+                EXPORT  USB0_IRQHandler     [WEAK]
+                EXPORT  DAC0_IRQHandler     [WEAK]
+                EXPORT  TSI0_IRQHandler     [WEAK]
+                EXPORT  MCG_IRQHandler     [WEAK]
+                EXPORT  LPTimer_IRQHandler     [WEAK]
+                EXPORT  Reserved45_IRQHandler     [WEAK]
+                EXPORT  PORTA_IRQHandler     [WEAK]
+                EXPORT  PORTD_IRQHandler     [WEAK]
+                EXPORT  DefaultISR                      [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+Reserved39_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+Reserved45_IRQHandler
+PORTA_IRQHandler
+PORTD_IRQHandler
+DefaultISR
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_ARM_STD/sys.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,197 @@
+/*
+*****************************************************************************
+**
+**  File        : KL25Z128M4_flash.ld
+**
+**  Default linker command file for Flash targets
+**
+*****************************************************************************
+*/
+/* Entry Point */
+ENTRY(__thumb_startup)
+
+/* Highest address of the user mode stack */
+_estack = 0x20003000;    /* end of SRAM */
+__SP_INIT = _estack;
+
+/* Generate a link error if heap and stack don't fit into RAM */
+__heap_size = 0x400;				/* required amount of heap  */
+__stack_size = 0x400; 				/* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts	(rx) : ORIGIN = 0x00000000, LENGTH = 0xC0
+  m_cfmprotrom 	(rx) : ORIGIN = 0x00000400, LENGTH = 0x10
+  m_text 		(rx) : ORIGIN = 0x00000800, LENGTH = 128K - 0x800
+  m_data 	   (rwx) : ORIGIN = 0x1FFFF000, LENGTH = 16K		/* SRAM */
+}
+
+		
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into Flash */
+  .interrupts :
+  {
+	__vector_table = .;
+    . = ALIGN(4);
+    KEEP(*(.vectortable)) /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+  
+  .cfmprotect :
+  {
+    . = ALIGN(4);
+	KEEP(*(.cfmconfig))	/* Flash Configuration Field (FCF) */
+	. = ALIGN(4);
+  } > m_cfmprotrom
+
+  /* The program code and other data goes into Flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } > m_text
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text
+  .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+  } > m_text
+  
+  .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text  
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text  
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+	
+	___ROM_AT = .;
+  } > m_text
+
+  /* reserve MTB memory at the beginning of m_data */
+  .mtb : /* MTB buffer address as defined by the hardware */
+  {
+    . = ALIGN(8);
+    _mtb_start = .;
+    KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
+    . = ALIGN(8);
+    _mtb_end = .;
+  } > m_data  
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT(___ROM_AT)
+  {
+    . = ALIGN(4);
+    __sinit__ = .;
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } > m_data
+  
+  ___data_size = _edata - _sdata;
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    __START_BSS = .;
+	PROVIDE ( __bss_start__ = __START_BSS );
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    __END_BSS = .;
+	PROVIDE ( __bss_end__ = __END_BSS );
+  } > m_data
+
+  _romp_at = ___ROM_AT + SIZEOF(.data);
+  .romp : AT(_romp_at)
+  {
+	__S_romp = _romp_at;
+    LONG(___ROM_AT);
+    LONG(_sdata);
+    LONG(___data_size);
+    LONG(0);
+    LONG(0);
+    LONG(0);
+  } > m_data
+ 
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+	__heap_addr = .;
+    . = . + __heap_size;
+    . = . + __stack_size;
+    . = ALIGN(4);
+  } > m_data
+  
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/startup_MKL25Z4.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,147 @@
+#include <string.h>
+#include <stdlib.h>
+
+#include "cmsis.h"
+
+// Linker Script
+extern unsigned long _estack;
+extern char __S_romp[];
+
+extern char __START_BSS[];
+extern char __END_BSS[];
+
+// CRT0
+extern void __init_registers();
+extern void __copy_rom_sections_to_ram(void);
+extern void __call_static_initializers(void);
+extern void __init_user();
+
+// User/mbed Defined
+extern int main();
+extern void mbed_exit(int return_code);
+
+void _ExitProcess(int return_code) {
+    mbed_exit(return_code);
+}
+
+void __thumb_startup(void) {
+    // Setup registers
+    __init_registers();
+    
+    // Disable the Watchdog because it may reset the core before entering main().
+    SIM->COPC = 0x0;
+    
+    //  zero-fill the .bss section
+    memset(__START_BSS, 0, (__END_BSS - __START_BSS));
+    
+    if (__S_romp != 0L)
+        __copy_rom_sections_to_ram();
+    
+    //  call C++ static initializers
+    __call_static_initializers();
+    
+    // initializations before main, user specific
+    __init_user();
+    
+    exit(main());
+    
+    //  should never get here
+    while (1);
+}
+
+void Default_Handler() {
+    __asm("bkpt");
+}
+
+/* Weak definitions of handlers point to Default_Handler if not implemented */
+void NMI_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler() __attribute__ ((weak, alias("Default_Handler")));
+
+void DMA0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void DMA1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void DMA2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void DMA3_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MCM_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void FTFL_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PMC_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void LLW_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void I2C0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void I2C1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void SPI0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void SPI1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ADC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void CMP0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void FTM0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void FTM1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void FTM2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void RTC_Alarm_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void RTC_Seconds_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PIT_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void USBOTG_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void DAC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void TSI0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MCG_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void LPTimer_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PORTA_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PORTD_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+
+/* The Interrupt Vector Table */
+void (* const InterruptVector[])() __attribute__ ((section(".vectortable"))) = {
+    /* Processor exceptions */
+    (void(*)(void)) &_estack,
+    __thumb_startup,
+    NMI_Handler,
+    HardFault_Handler,
+    0,
+    0,
+    0,
+    0,
+    0,
+    0,
+    0,
+    SVC_Handler,
+    0,
+    0,
+    PendSV_Handler,
+    SysTick_Handler,
+
+    /* Interrupts */
+    DMA0_IRQHandler, /* DMA Channel 0 Transfer Complete and Error */
+    DMA1_IRQHandler, /* DMA Channel 1 Transfer Complete and Error */
+    DMA2_IRQHandler, /* DMA Channel 2 Transfer Complete and Error */
+    DMA3_IRQHandler, /* DMA Channel 3 Transfer Complete and Error */
+    MCM_IRQHandler, /* Normal Interrupt */
+    FTFL_IRQHandler, /* FTFL Interrupt */
+    PMC_IRQHandler, /* PMC Interrupt */
+    LLW_IRQHandler, /* Low Leakage Wake-up */
+    I2C0_IRQHandler, /* I2C0 interrupt */
+    I2C1_IRQHandler, /* I2C1 interrupt */
+    SPI0_IRQHandler, /* SPI0 Interrupt */
+    SPI1_IRQHandler, /* SPI1 Interrupt */
+    UART0_IRQHandler, /* UART0 Status and Error interrupt */
+    UART1_IRQHandler, /* UART1 Status and Error interrupt */
+    UART2_IRQHandler, /* UART2 Status and Error interrupt */
+    ADC0_IRQHandler, /* ADC0 interrupt */
+    CMP0_IRQHandler, /* CMP0 interrupt */
+    FTM0_IRQHandler, /* FTM0 fault, overflow and channels interrupt */
+    FTM1_IRQHandler, /* FTM1 fault, overflow and channels interrupt */
+    FTM2_IRQHandler, /* FTM2 fault, overflow and channels interrupt */
+    RTC_Alarm_IRQHandler, /* RTC Alarm interrupt */
+    RTC_Seconds_IRQHandler, /* RTC Seconds interrupt */
+    PIT_IRQHandler, /* PIT timer all channels interrupt */
+    Default_Handler, /* Reserved interrupt 39/23 */
+    USBOTG_IRQHandler, /* USB interrupt */
+    DAC0_IRQHandler, /* DAC0 interrupt */
+    TSI0_IRQHandler, /* TSI0 Interrupt */
+    MCG_IRQHandler, /* MCG Interrupt */
+    LPTimer_IRQHandler, /* LPTimer interrupt */
+    Default_Handler, /* Reserved interrupt 45/29 */
+    PORTA_IRQHandler, /* Port A interrupt */
+    PORTD_IRQHandler /* Port D interrupt */
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,153 @@
+/* Linker script for mbed LPC1768 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
+  RAM (rwx) : ORIGIN = 0x1FFFF0C0, LENGTH = 0x3F40
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text.Reset_Handler)
+        *(.text.SystemInit)
+        
+        /* Only vectors and code running at reset are safe to be in first 512
+           bytes since RAM can be mapped into this area for RAM based interrupt
+           vectors. */
+        . = 0x00000200;
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+        
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM
+    
+    .heap :
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy :
+    {
+        *(.stack)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+    
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/startup_MKL25Z4.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,226 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with 
+ *   GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ * 
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the ARM Limited nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+    .syntax unified
+    .arch armv6-m
+
+/* Memory Model
+   The HEAP starts at the end of the DATA section and grows upward.
+   
+   The STACK starts at the end of the RAM and grows downward.
+   
+   The HEAP and stack STACK are only checked at compile time:
+   (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+   
+   This is just a check for the bare minimum for the Heap+Stack area before
+   aborting compilation, it is not the run time limit:
+   Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0x80
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x80
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+    
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    NMI_Handler           /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+    /* External interrupts */
+    .long   DMA0_IRQHandler         /* DMA channel 0 transfer complete interrupt */
+    .long   DMA1_IRQHandler         /* DMA channel 1 transfer complete interrupt */
+    .long   DMA2_IRQHandler         /* DMA channel 2 transfer complete interrupt */
+    .long   DMA3_IRQHandler         /* DMA channel 3 transfer complete interrupt */
+    .long   Reserved20_IRQHandler   /* Reserved interrupt 20 */
+    .long   FTFA_IRQHandler         /* FTFA interrupt */
+    .long   LVD_LVW_IRQHandler      /* Low Voltage Detect, Low Voltage Warning */
+    .long   LLW_IRQHandler          /* Low Leakage Wakeup */
+    .long   I2C0_IRQHandler         /* I2C0 interrupt */
+    .long   I2C1_IRQHandler         /* I2C0 interrupt 25 */
+    .long   SPI0_IRQHandler         /* SPI0 interrupt */
+    .long   SPI1_IRQHandler         /* SPI1 interrupt */
+    .long   UART0_IRQHandler        /* UART0 status/error interrupt */
+    .long   UART1_IRQHandler        /* UART1 status/error interrupt */
+    .long   UART2_IRQHandler        /* UART2 status/error interrupt */
+    .long   ADC0_IRQHandler         /* ADC0 interrupt */
+    .long   CMP0_IRQHandler         /* CMP0 interrupt */
+    .long   TPM0_IRQHandler         /* TPM0 fault, overflow and channels interrupt */
+    .long   TPM1_IRQHandler         /* TPM1 fault, overflow and channels interrupt */
+    .long   TPM2_IRQHandler         /* TPM2 fault, overflow and channels interrupt */
+    .long   RTC_IRQHandler          /* RTC interrupt */
+    .long   RTC_Seconds_IRQHandler  /* RTC seconds interrupt */
+    .long   PIT_IRQHandler          /* PIT timer interrupt */
+    .long   Reserved39_IRQHandler   /* Reserved interrupt 39 */
+    .long   USB0_IRQHandler         /* USB0 interrupt */
+    .long   DAC0_IRQHandler         /* DAC interrupt */
+    .long   TSI0_IRQHandler         /* TSI0 interrupt */
+    .long   MCG_IRQHandler          /* MCG interrupt */
+    .long   LPTimer_IRQHandler      /* LPTimer interrupt */
+    .long   Reserved45_IRQHandler   /* Reserved interrupt 45 */
+    .long   PORTA_IRQHandler        /* Port A interrupt */
+    .long   PORTD_IRQHandler        /* Port D interrupt */
+    
+    .size    __isr_vector, . - __isr_vector
+
+    .section .text.Reset_Handler
+    .thumb
+    .thumb_func
+    .align 2
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in 
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble    .flash_to_ram_loop_end
+
+    movs    r4, 0
+.flash_to_ram_loop:
+    ldr    r0, [r1,r4]
+    str    r0, [r2,r4]
+    adds    r4, 4
+    cmp    r4, r3
+    blt    .flash_to_ram_loop
+.flash_to_ram_loop_end:
+
+    ldr    r0, =SystemInit
+    blx    r0
+    ldr    r0, =_start
+    bx    r0
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+    
+    .text
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_default_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+    
+    def_default_handler     NMI_Handler
+    def_default_handler     HardFault_Handler
+    def_default_handler     SVC_Handler
+    def_default_handler     PendSV_Handler
+    def_default_handler     SysTick_Handler
+    def_default_handler     DMA0_IRQHandler
+    def_default_handler     DMA1_IRQHandler
+    def_default_handler     DMA2_IRQHandler
+    def_default_handler     DMA3_IRQHandler
+    def_default_handler     Reserved20_IRQHandler
+    def_default_handler     FTFA_IRQHandler
+    def_default_handler     LVD_LVW_IRQHandler
+    def_default_handler     LLW_IRQHandler
+    def_default_handler     I2C0_IRQHandler
+    def_default_handler     I2C1_IRQHandler
+    def_default_handler     SPI0_IRQHandler
+    def_default_handler     SPI1_IRQHandler
+    def_default_handler     UART0_IRQHandler
+    def_default_handler     UART1_IRQHandler
+    def_default_handler     UART2_IRQHandler
+    def_default_handler     ADC0_IRQHandler
+    def_default_handler     CMP0_IRQHandler
+    def_default_handler     TPM0_IRQHandler
+    def_default_handler     TPM1_IRQHandler
+    def_default_handler     TPM2_IRQHandler
+    def_default_handler     RTC_IRQHandler
+    def_default_handler     RTC_Seconds_IRQHandler
+    def_default_handler     PIT_IRQHandler
+    def_default_handler     Reserved39_IRQHandler
+    def_default_handler     USB0_IRQHandler
+    def_default_handler     DAC0_IRQHandler
+    def_default_handler     TSI0_IRQHandler
+    def_default_handler     MCG_IRQHandler
+    def_default_handler     LPTimer_IRQHandler
+    def_default_handler     Reserved45_IRQHandler
+    def_default_handler     PORTA_IRQHandler
+    def_default_handler     PORTD_IRQHandler
+
+    .weak    DEF_IRQHandler
+    .set    DEF_IRQHandler, Default_Handler
+
+    .end

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/cmsis.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MKL25Z4.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/cmsis_nvic.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+#include "cmsis_nvic.h"
+
+#define NVIC_NUM_VECTORS (16 + 32)            // CORE + MCU Peripherals
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFF000)  // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0)       // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + 16];
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/cmsis_nvic.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,23 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,263 @@
+/*
+** ###################################################################
+**     Processor:           MKL25Z128VLK4
+**     Compilers:           ARM Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL25RM, Rev.1, Jun 2012
+**     Version:             rev. 1.1, 2012-06-21
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2012-06-13)
+**         Initial version.
+**     - rev. 1.1 (2012-06-21)
+**         Update according to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL25Z4
+ * @version 1.1
+ * @date 2012-06-21
+ * @brief Device specific configuration file for MKL25Z4 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MKL25Z4.h"
+
+#define DISABLE_WDOG    1
+
+#define CLOCK_SETUP     1
+/* Predefined clock setups
+   0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+         Reference clock source for MCG module is the slow internal clock source 32.768kHz
+         Core clock = 41.94MHz, BusClock = 13.98MHz
+   1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+         Reference clock source for MCG module is an external crystal 8MHz
+         Core clock = 48MHz, BusClock = 24MHz
+   2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+         Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
+         Core clock = 8MHz, BusClock = 8MHz
+*/
+
+/*----------------------------------------------------------------------------
+  Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+    #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+    #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
+    #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
+    #define DEFAULT_SYSTEM_CLOCK            41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+    #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+    #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
+    #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
+    #define DEFAULT_SYSTEM_CLOCK            48000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+    #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+    #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
+    #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
+    #define DEFAULT_SYSTEM_CLOCK            8000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+  /* Disable the WDOG module */
+  /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
+  SIM->COPC = (uint32_t)0x00u;
+#endif /* (DISABLE_WDOG) */
+#if (CLOCK_SETUP == 0)
+  /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+  SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
+  /* Switch to FEI Mode */
+  /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (uint8_t)0x06U;
+  /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+  MCG->C2 = (uint8_t)0x00U;
+  /* MCG->C4: DMX32=0,DRST_DRS=1 */
+  MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
+  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  OSC0->CR = (uint8_t)0x80U;
+  /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  MCG->C5 = (uint8_t)0x00U;
+  /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  MCG->C6 = (uint8_t)0x00U;
+  while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+  }
+  while((MCG->S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
+  }
+#elif (CLOCK_SETUP == 1)
+  /* SIM->SCGC5: PORTA=1 */
+  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
+  /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+  SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
+  /* PORTA->PCR18: ISF=0,MUX=0 */
+  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+  /* PORTA->PCR19: ISF=0,MUX=0 */
+  PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
+  /* Switch to FBE Mode */
+  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
+  OSC0->CR = (uint8_t)0x89U;
+  /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+  MCG->C2 = (uint8_t)0x24U;
+  /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (uint8_t)0x9AU;
+  /* MCG->C4: DMX32=0,DRST_DRS=0 */
+  MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+  /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
+  MCG->C5 = (uint8_t)0x01U;
+  /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  MCG->C6 = (uint8_t)0x00U;
+  while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+  }
+  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+  }
+  /* Switch to PBE Mode */
+  /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
+  MCG->C6 = (uint8_t)0x40U;
+  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+  }
+  while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
+  }
+  /* Switch to PEE Mode */
+  /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (uint8_t)0x1AU;
+  while((MCG->S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
+  }
+#elif (CLOCK_SETUP == 2)
+  /* SIM->SCGC5: PORTA=1 */
+  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
+  /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+  SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
+  /* PORTA->PCR18: ISF=0,MUX=0 */
+  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+  /* PORTA->PCR19: ISF=0,MUX=0 */
+  PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
+  /* Switch to FBE Mode */
+  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
+  OSC0->CR = (uint8_t)0x89U;
+  /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+  MCG->C2 = (uint8_t)0x24U;
+  /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (uint8_t)0x9AU;
+  /* MCG->C4: DMX32=0,DRST_DRS=0 */
+  MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+  /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+  MCG->C5 = (uint8_t)0x00U;
+  /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  MCG->C6 = (uint8_t)0x00U;
+  while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+  }
+  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+  }
+  /* Switch to BLPE Mode */
+  /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
+  MCG->C2 = (uint8_t)0x26U;
+  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+  }
+#endif /* (CLOCK_SETUP == 2) */
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+  uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
+  uint8_t Divider;
+
+  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+    /* Output of FLL or PLL is selected */
+    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+      /* FLL is selected */
+      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+        /* External reference clock is selected */
+        MCGOUTClock = CPU_XTAL_CLK_HZ;                                       /* System oscillator drives MCG clock */
+        Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+        MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
+        if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
+          MCGOUTClock /= 32u;                                                  /* If high range is enabled, additional 32 divider is active */
+        } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
+      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+        MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
+      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+      /* Select correct multiplier to calculate the MCG output clock  */
+      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+        case 0x0u:
+          MCGOUTClock *= 640u;
+          break;
+        case 0x20u:
+          MCGOUTClock *= 1280u;
+          break;
+        case 0x40u:
+          MCGOUTClock *= 1920u;
+          break;
+        case 0x60u:
+          MCGOUTClock *= 2560u;
+          break;
+        case 0x80u:
+          MCGOUTClock *= 732u;
+          break;
+        case 0xA0u:
+          MCGOUTClock *= 1464u;
+          break;
+        case 0xC0u:
+          MCGOUTClock *= 2197u;
+          break;
+        case 0xE0u:
+          MCGOUTClock *= 2929u;
+          break;
+        default:
+          break;
+      }
+    } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+      /* PLL is selected */
+      Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+      MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider);                     /* Calculate the PLL reference clock */
+      Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+      MCGOUTClock *= Divider;                       /* Calculate the MCG output clock */
+    } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+    /* Internal reference clock is selected */
+    if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+      MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
+    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+      MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));  /* Fast internal reference clock selected */
+    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+    /* External reference clock is selected */
+    MCGOUTClock = CPU_XTAL_CLK_HZ;                                           /* System oscillator drives MCG clock */
+  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+    /* Reserved value */
+    return;
+  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+  SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_Freescale/TARGET_KL25Z/system_MKL25Z4.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,84 @@
+/*
+** ###################################################################
+**     Processor:           MKL25Z128VLK4
+**     Compilers:           ARM Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    KL25RM, Rev.1, Jun 2012
+**     Version:             rev. 1.1, 2012-06-21
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2012-06-13)
+**         Initial version.
+**     - rev. 1.1 (2012-06-21)
+**         Update according to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL25Z4
+ * @version 1.1
+ * @date 2012-06-21
+ * @brief Device specific configuration file for MKL25Z4 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL25Z4_H_
+#define SYSTEM_MKL25Z4_H_                        /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* #if !defined(SYSTEM_MKL25Z4_H_) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/LPC11Uxx.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,670 @@
+
+/****************************************************************************************************//**
+ * @file     LPC11Uxx.h
+ *
+ *
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
+ *           default LPC11Uxx Device Series
+ *
+ * @version  V0.1
+ * @date     21. March 2011
+ *
+ * @note     Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
+ *
+ *           from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
+ *           created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
+ *
+ *******************************************************************************************************/
+
+// ################################################################################
+// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000
+// ################################################################################
+
+/** @addtogroup NXP
+  * @{
+  */
+
+/** @addtogroup LPC11Uxx
+  * @{
+  */
+
+#ifndef __LPC11UXX_H__
+#define __LPC11UXX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+
+#if defined ( __CC_ARM   )
+  #pragma anon_unions
+#endif
+
+ /* Interrupt Number Definition */
+
+typedef enum {
+// -------------------------  Cortex-M0 Processor Exceptions Numbers  -----------------------------
+  Reset_IRQn                        = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
+  NonMaskableInt_IRQn               = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
+  HardFault_IRQn                    = -13,  /*!<   3  Hard Fault, all classes of Fault */
+  SVCall_IRQn                       = -5,   /*!<  11  System Service Call via SVC instruction */
+  DebugMonitor_IRQn                 = -4,   /*!<  12  Debug Monitor                    */
+  PendSV_IRQn                       = -2,   /*!<  14  Pendable request for system service */
+  SysTick_IRQn                      = -1,   /*!<  15  System Tick Timer                */
+// ---------------------------  LPC11Uxx Specific Interrupt Numbers  ------------------------------
+FLEX_INT0_IRQn                = 0,        /*!< All I/O pins can be routed to below 8 interrupts. */
+  FLEX_INT1_IRQn                = 1,
+  FLEX_INT2_IRQn                = 2,
+  FLEX_INT3_IRQn                = 3,
+  FLEX_INT4_IRQn                = 4,   
+  FLEX_INT5_IRQn                = 5,        
+  FLEX_INT6_IRQn                = 6,        
+  FLEX_INT7_IRQn                = 7,        
+  GINT0_IRQn                    = 8,        /*!< Grouped Interrupt 0                              */
+  GINT1_IRQn                    = 9,        /*!< Grouped Interrupt 1                              */
+  Reserved0_IRQn                = 10,       /*!< Reserved Interrupt                               */
+  Reserved1_IRQn                = 11,       
+  Reserved2_IRQn                = 12,       
+  Reserved3_IRQn                = 13,       
+  SSP1_IRQn                     = 14,       /*!< SSP1 Interrupt                                   */
+  I2C_IRQn                      = 15,       /*!< I2C Interrupt                                    */
+  TIMER_16_0_IRQn               = 16,       /*!< 16-bit Timer0 Interrupt                          */
+  TIMER_16_1_IRQn               = 17,       /*!< 16-bit Timer1 Interrupt                          */
+  TIMER_32_0_IRQn               = 18,       /*!< 32-bit Timer0 Interrupt                          */
+  TIMER_32_1_IRQn               = 19,       /*!< 32-bit Timer1 Interrupt                          */
+  SSP0_IRQn                     = 20,       /*!< SSP0 Interrupt                                   */
+  UART_IRQn                     = 21,       /*!< UART Interrupt                                   */
+  USB_IRQn                      = 22,       /*!< USB IRQ Interrupt                                */
+  USB_FIQn                      = 23,       /*!< USB FIQ Interrupt                                */
+  ADC_IRQn                      = 24,       /*!< A/D Converter Interrupt                          */
+  WDT_IRQn                      = 25,       /*!< Watchdog timer Interrupt                         */  
+  BOD_IRQn                      = 26,       /*!< Brown Out Detect(BOD) Interrupt                  */
+  FMC_IRQn                      = 27,       /*!< Flash Memory Controller Interrupt                */
+  Reserved4_IRQn                = 28,       /*!< Reserved Interrupt                               */
+  Reserved5_IRQn                = 29,       /*!< Reserved Interrupt                               */
+  USBWakeup_IRQn                = 30,       /*!< USB wakeup Interrupt                             */
+  Reserved6_IRQn                = 31,       /*!< Reserved Interrupt                               */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
+
+#define __MPU_PRESENT             0         /*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0.h"                       /*!< Cortex-M0 processor and core peripherals */
+#include "system_LPC11Uxx.h"                /*!< LPC11Uxx System                       */
+
+/** @addtogroup Device_Peripheral_Registers
+  * @{
+  */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          I2C                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3  (I2C)
+  */
+
+typedef struct {                            /*!< (@ 0x40000000) I2C Structure          */
+  __IO uint32_t CONSET;                     /*!< (@ 0x40000000) I2C Control Set Register */
+  __I  uint32_t STAT;                       /*!< (@ 0x40000004) I2C Status Register */
+  __IO uint32_t DAT;                        /*!< (@ 0x40000008) I2C Data Register.  */
+  __IO uint32_t ADR0;                       /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
+  __IO uint32_t SCLH;                       /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
+  __IO uint32_t SCLL;                       /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
+  __IO uint32_t CONCLR;                     /*!< (@ 0x40000018) I2C Control Clear Register*/
+  __IO uint32_t MMCTRL;                     /*!< (@ 0x4000001C) Monitor mode control register*/
+  __IO uint32_t ADR1;                       /*!< (@ 0x40000020) I2C Slave Address Register 1*/
+  __IO uint32_t ADR2;                       /*!< (@ 0x40000024) I2C Slave Address Register 2*/
+  __IO uint32_t ADR3;                       /*!< (@ 0x40000028) I2C Slave Address Register 3*/
+  __I  uint32_t DATA_BUFFER;                /*!< (@ 0x4000002C) Data buffer register */
+union{
+  __IO uint32_t MASK[4];                    /*!< (@ 0x40000030) I2C Slave address mask register */
+  struct{
+  __IO uint32_t MASK0;
+  __IO uint32_t MASK1;
+  __IO uint32_t MASK2;
+  __IO uint32_t MASK3;
+  };
+  };
+} LPC_I2C_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         WWDT                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3  (WWDT)
+  */
+
+typedef struct {                            /*!< (@ 0x40004000) WWDT Structure         */
+  __IO uint32_t MOD;                        /*!< (@ 0x40004000) Watchdog mode register*/
+  __IO uint32_t TC;                         /*!< (@ 0x40004004) Watchdog timer constant register */
+  __IO uint32_t FEED;                       /*!< (@ 0x40004008) Watchdog feed sequence register */
+  __I  uint32_t TV;                         /*!< (@ 0x4000400C) Watchdog timer value register */
+  __IO uint32_t CLKSEL;                     /*!< (@ 0x40004010) Watchdog clock select register. */
+  __IO uint32_t WARNINT;                    /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
+  __IO uint32_t WINDOW;                     /*!< (@ 0x40004018) Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         USART                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3  (USART)
+  */
+
+typedef struct {                            /*!< (@ 0x40008000) USART Structure        */
+  
+  union {
+    __IO uint32_t DLL;                      /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+    __O  uint32_t THR;                      /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
+    __I  uint32_t RBR;                      /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
+  };
+  
+  union {
+    __IO uint32_t IER;                      /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
+    __IO uint32_t DLM;                      /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+  };
+  
+  union {
+    __O  uint32_t FCR;                      /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
+    __I  uint32_t IIR;                      /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+  };
+  __IO uint32_t LCR;                        /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
+  __IO uint32_t MCR;                        /*!< (@ 0x40008010) Modem Control Register. */
+  __I  uint32_t LSR;                        /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+  __I  uint32_t MSR;                        /*!< (@ 0x40008018) Modem Status Register. */
+  __IO uint32_t SCR;                        /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
+  __IO uint32_t ACR;                        /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+  __IO uint32_t ICR;                        /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
+  __IO uint32_t FDR;                        /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+  __IO uint32_t OSR;                        /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
+  __IO uint32_t TER;                        /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
+  __I  uint32_t RESERVED0[3];
+  __IO uint32_t HDEN;                       /*!< (@ 0x40008040) Half duplex enable register. */
+  __I  uint32_t RESERVED1;
+  __IO uint32_t SCICTRL;                    /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
+  __IO uint32_t RS485CTRL;                  /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+  __IO uint32_t RS485ADRMATCH;              /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+  __IO uint32_t RS485DLY;                   /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
+  __IO uint32_t SYNCCTRL; 
+} LPC_USART_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        Timer                                       -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3  
+  */
+
+typedef struct {                            /*!< (@ 0x40014000) CT32B0 Structure        */
+  __IO uint32_t IR;                         /*!< (@ 0x40014000) Interrupt Register      */
+  __IO uint32_t TCR;                        /*!< (@ 0x40014004) Timer Control Register  */
+  __IO uint32_t TC;                         /*!< (@ 0x40014008) Timer Counter 		*/
+  __IO uint32_t PR;                         /*!< (@ 0x4001400C) Prescale Register  	*/
+  __IO uint32_t PC;                         /*!< (@ 0x40014010) Prescale Counter	 */
+  __IO uint32_t MCR;                        /*!< (@ 0x40014014) Match Control Register */
+  union {
+  __IO uint32_t MR[4];                      /*!< (@ 0x40014018) Match Register */
+  struct{
+  __IO uint32_t MR0;                        /*!< (@ 0x40018018) Match Register. MR0 */
+  __IO uint32_t MR1;                        /*!< (@ 0x4001801C) Match Register. MR1 */
+  __IO uint32_t MR2;                        /*!< (@ 0x40018020) Match Register. MR2 */
+  __IO uint32_t MR3;                        /*!< (@ 0x40018024) Match Register. MR3 */
+  };
+  };
+  __IO uint32_t CCR;                        /*!< (@ 0x40014028) Capture Control Register */
+  union{
+  __I  uint32_t CR[4];                      /*!< (@ 0x4001402C) Capture Register  */
+    struct{
+  __I  uint32_t CR0;			    /*!< (@ 0x4001802C) Capture Register. CR 0 */
+  __I  uint32_t CR1;			    /*!< (@ 0x40018030) Capture Register. CR 1 */
+  __I  uint32_t CR2;			    /*!< (@ 0x40018034) Capture Register. CR 2 */
+  __I  uint32_t CR3;			    /*!< (@ 0x40018038) Capture Register. CR 3 */
+  };
+  };
+__IO uint32_t EMR;                        /*!< (@ 0x4001403C) External Match Register */
+  __I  uint32_t RESERVED0[12];
+  __IO uint32_t CTCR;                       /*!< (@ 0x40014070) Count Control Register */
+  __IO uint32_t PWMC;                       /*!< (@ 0x40014074) PWM Control Register */
+} LPC_CTxxBx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          ADC                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3  (ADC)
+  */
+
+typedef struct {                            /*!< (@ 0x4001C000) ADC Structure          */
+  __IO uint32_t CR;                         /*!< (@ 0x4001C000) A/D Control Register */
+  __IO uint32_t GDR;                        /*!< (@ 0x4001C004) A/D Global Data Register */
+  __I  uint32_t RESERVED0[1];
+  __IO uint32_t INTEN;                      /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
+  union{
+  __I  uint32_t DR[8];                      /*!< (@ 0x4001C010) A/D Channel Data Register*/
+    struct{
+  __IO uint32_t DR0;                      	/*!< (@ 0x40020010) A/D Channel Data Register 0*/
+  __IO uint32_t DR1;                      	/*!< (@ 0x40020014) A/D Channel Data Register 1*/
+  __IO uint32_t DR2;                      	/*!< (@ 0x40020018) A/D Channel Data Register 2*/
+  __IO uint32_t DR3;                      	/*!< (@ 0x4002001C) A/D Channel Data Register 3*/
+  __IO uint32_t DR4;                      	/*!< (@ 0x40020020) A/D Channel Data Register 4*/
+  __IO uint32_t DR5;                      	/*!< (@ 0x40020024) A/D Channel Data Register 5*/
+  __IO uint32_t DR6;                      	/*!< (@ 0x40020028) A/D Channel Data Register 6*/
+  __IO uint32_t DR7;                      	/*!< (@ 0x4002002C) A/D Channel Data Register 7*/
+  };
+  };
+  __I  uint32_t STAT;                       /*!< (@ 0x4001C030) A/D Status Register.  */
+} LPC_ADC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          PMU                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3  (PMU)
+  */
+
+typedef struct {                            /*!< (@ 0x40038000) PMU Structure          */
+  __IO uint32_t PCON;                       /*!< (@ 0x40038000) Power control register */
+  union{
+  __IO uint32_t GPREG[4];                   /*!< (@ 0x40038004) General purpose register 0 */
+  struct{
+  __IO uint32_t GPREG0;                   	/*!< (@ 0x40038004) General purpose register 0 */
+  __IO uint32_t GPREG1;                   	/*!< (@ 0x40038008) General purpose register 1 */
+  __IO uint32_t GPREG2;                   	/*!< (@ 0x4003800C) General purpose register 2 */
+  __IO uint32_t GPREG3;                   	/*!< (@ 0x40038010) General purpose register 3 */
+  };
+  };
+} LPC_PMU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                       FLASHCTRL                                      -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3  (FLASHCTRL)
+  */
+
+typedef struct {                            /*!< (@ 0x4003C000) FLASHCTRL Structure    */
+  __I  uint32_t RESERVED0[4];
+  __IO uint32_t FLASHCFG;                   /*!< (@ 0x4003C010) Flash memory access time configuration register */
+  __I  uint32_t RESERVED1[3];
+  __IO uint32_t FMSSTART;                   /*!< (@ 0x4003C020) Signature start address register */
+  __IO uint32_t FMSSTOP;                    /*!< (@ 0x4003C024) Signature stop-address register */
+  __I  uint32_t RESERVED2[1];
+  __I  uint32_t FMSW0;                      /*!< (@ 0x4003C02C) Word 0 [31:0]          */
+  __I  uint32_t FMSW1;                      /*!< (@ 0x4003C030) Word 1 [63:32]         */
+  __I  uint32_t FMSW2;                      /*!< (@ 0x4003C034) Word 2 [95:64]         */
+  __I  uint32_t FMSW3;                      /*!< (@ 0x4003C038) Word 3 [127:96]        */
+  __I  uint32_t RESERVED3[1001];
+  __I  uint32_t FMSTAT;                     /*!< (@ 0x4003CFE0) Signature generation status register */
+  __I  uint32_t RESERVED4[1];
+  __IO uint32_t FMSTATCLR;                  /*!< (@ 0x4003CFE8) Signature generation status clear register */
+} LPC_FLASHCTRL_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         SSP0/1                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3  (SSP0)
+  */
+
+typedef struct {                            /*!< (@ 0x40040000) SSP0 Structure         */
+  __IO uint32_t CR0;                        /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
+  __IO uint32_t CR1;                        /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
+  __IO uint32_t DR;                         /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+  __I  uint32_t SR;                         /*!< (@ 0x4004000C) Status Register        */
+  __IO uint32_t CPSR;                       /*!< (@ 0x40040010) Clock Prescale Register */
+  __IO uint32_t IMSC;                       /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
+  __I  uint32_t RIS;                        /*!< (@ 0x40040018) Raw Interrupt Status Register */
+  __I  uint32_t MIS;                        /*!< (@ 0x4004001C) Masked Interrupt Status Register */
+  __IO uint32_t ICR;                        /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
+} LPC_SSPx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                       IOCONFIG                                       -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3  (IOCONFIG)
+  */
+
+typedef struct {                            /*!< (@ 0x40044000) IOCONFIG Structure     */
+  __IO uint32_t RESET_PIO0_0;               /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
+  __IO uint32_t PIO0_1;                     /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
+  __IO uint32_t PIO0_2;                     /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
+  __IO uint32_t PIO0_3;                     /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
+  __IO uint32_t PIO0_4;                     /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
+  __IO uint32_t PIO0_5;                     /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
+  __IO uint32_t PIO0_6;                     /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
+  __IO uint32_t PIO0_7;                     /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
+  __IO uint32_t PIO0_8;                     /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
+  __IO uint32_t PIO0_9;                     /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
+  __IO uint32_t SWCLK_PIO0_10;              /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
+  __IO uint32_t TDI_PIO0_11;                /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
+  __IO uint32_t TMS_PIO0_12;                /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
+  __IO uint32_t TDO_PIO0_13;                /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
+  __IO uint32_t TRST_PIO0_14;               /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
+  __IO uint32_t SWDIO_PIO0_15;              /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
+  __IO uint32_t PIO0_16;                    /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
+  __IO uint32_t PIO0_17;                    /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
+  __IO uint32_t PIO0_18;                    /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
+  __IO uint32_t PIO0_19;                    /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
+  __IO uint32_t PIO0_20;                    /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
+  __IO uint32_t PIO0_21;                    /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
+  __IO uint32_t PIO0_22;                    /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
+  __IO uint32_t PIO0_23;                    /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
+  __IO uint32_t PIO1_0;                 /*!< Offset: 0x060 */
+  __IO uint32_t PIO1_1;         
+  __IO uint32_t PIO1_2;       
+  __IO uint32_t PIO1_3;      
+  __IO uint32_t PIO1_4;                 /*!< Offset: 0x070 */
+  __IO uint32_t PIO1_5;                     /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
+  __IO uint32_t PIO1_6;     
+  __IO uint32_t PIO1_7;       
+  __IO uint32_t PIO1_8;                 /*!< Offset: 0x080 */
+  __IO uint32_t PIO1_9;        
+  __IO uint32_t PIO1_10;        
+  __IO uint32_t PIO1_11;       
+  __IO uint32_t PIO1_12;                /*!< Offset: 0x090 */
+  __IO uint32_t PIO1_13;                    /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
+  __IO uint32_t PIO1_14;                    /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
+  __IO uint32_t PIO1_15;                    /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
+  __IO uint32_t PIO1_16;                    /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
+  __IO uint32_t PIO1_17;
+  __IO uint32_t PIO1_18;
+  __IO uint32_t PIO1_19;                    /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
+  __IO uint32_t PIO1_20;                    /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
+  __IO uint32_t PIO1_21;                    /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
+  __IO uint32_t PIO1_22;                    /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
+  __IO uint32_t PIO1_23;                    /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
+  __IO uint32_t PIO1_24;                    /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
+  __IO uint32_t PIO1_25;                    /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
+  __IO uint32_t PIO1_26;                    /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
+  __IO uint32_t PIO1_27;                    /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
+  __IO uint32_t PIO1_28;                    /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
+  __IO uint32_t PIO1_29;                    /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
+  __IO uint32_t PIO1_30;
+  __IO uint32_t PIO1_31;                    /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
+} LPC_IOCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        SYSCON                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3  (SYSCON)
+  */
+
+typedef struct {                            /*!< (@ 0x40048000) SYSCON Structure       */
+  __IO uint32_t SYSMEMREMAP;                /*!< (@ 0x40048000) System memory remap    */
+  __IO uint32_t PRESETCTRL;                 /*!< (@ 0x40048004) Peripheral reset control */
+  __IO uint32_t SYSPLLCTRL;                 /*!< (@ 0x40048008) System PLL control     */
+  __I  uint32_t SYSPLLSTAT;                 /*!< (@ 0x4004800C) System PLL status      */
+  __IO uint32_t USBPLLCTRL;                 /*!< (@ 0x40048010) USB PLL control        */
+  __I  uint32_t USBPLLSTAT;                 /*!< (@ 0x40048014) USB PLL status         */
+  __I  uint32_t RESERVED0[2];
+  __IO uint32_t SYSOSCCTRL;                 /*!< (@ 0x40048020) System oscillator control */
+  __IO uint32_t WDTOSCCTRL;                 /*!< (@ 0x40048024) Watchdog oscillator control */
+  __I  uint32_t RESERVED1[2];
+  __IO uint32_t SYSRSTSTAT;                 /*!< (@ 0x40048030) System reset status register */
+  __I  uint32_t RESERVED2[3];
+  __IO uint32_t SYSPLLCLKSEL;               /*!< (@ 0x40048040) System PLL clock source select */
+  __IO uint32_t SYSPLLCLKUEN;               /*!< (@ 0x40048044) System PLL clock source update enable */
+  __IO uint32_t USBPLLCLKSEL;               /*!< (@ 0x40048048) USB PLL clock source select */
+  __IO uint32_t USBPLLCLKUEN;               /*!< (@ 0x4004804C) USB PLL clock source update enable */
+  __I  uint32_t RESERVED3[8];
+  __IO uint32_t MAINCLKSEL;                 /*!< (@ 0x40048070) Main clock source select */
+  __IO uint32_t MAINCLKUEN;                 /*!< (@ 0x40048074) Main clock source update enable */
+  __IO uint32_t SYSAHBCLKDIV;               /*!< (@ 0x40048078) System clock divider   */
+  __I  uint32_t RESERVED4[1];
+  __IO uint32_t SYSAHBCLKCTRL;              /*!< (@ 0x40048080) System clock control   */
+  __I  uint32_t RESERVED5[4];
+  __IO uint32_t SSP0CLKDIV;                 /*!< (@ 0x40048094) SSP0 clock divider     */
+  __IO uint32_t UARTCLKDIV;                 /*!< (@ 0x40048098) UART clock divider     */
+  __IO uint32_t SSP1CLKDIV;                 /*!< (@ 0x4004809C) SSP1 clock divider     */
+  __I  uint32_t RESERVED6[8];
+  __IO uint32_t USBCLKSEL;                  /*!< (@ 0x400480C0) USB clock source select */
+  __IO uint32_t USBCLKUEN;                  /*!< (@ 0x400480C4) USB clock source update enable */
+  __IO uint32_t USBCLKDIV;                  /*!< (@ 0x400480C8) USB clock source divider */
+  __I  uint32_t RESERVED7[5];
+  __IO uint32_t CLKOUTSEL;                  /*!< (@ 0x400480E0) CLKOUT clock source select */
+  __IO uint32_t CLKOUTUEN;                  /*!< (@ 0x400480E4) CLKOUT clock source update enable */
+  __IO uint32_t CLKOUTDIV;                  /*!< (@ 0x400480E8) CLKOUT clock divider   */
+  __I  uint32_t RESERVED8[5];
+  __I  uint32_t PIOPORCAP0;                 /*!< (@ 0x40048100) POR captured PIO status 0 */
+  __I  uint32_t PIOPORCAP1;                 /*!< (@ 0x40048104) POR captured PIO status 1 */
+  __I  uint32_t RESERVED9[18];
+  __IO uint32_t BODCTRL;                    /*!< (@ 0x40048150) Brown-Out Detect       */
+  __IO uint32_t SYSTCKCAL;                  /*!< (@ 0x40048154) System tick counter calibration */
+  __I  uint32_t RESERVED10[6];
+  __IO uint32_t IRQLATENCY;                 /*!< (@ 0x40048170) IQR delay */
+  __IO uint32_t NMISRC;                     /*!< (@ 0x40048174) NMI Source Control     */
+  __IO uint32_t PINTSEL[8];                 /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
+  __IO uint32_t USBCLKCTRL;                 /*!< (@ 0x40048198) USB clock control      */
+  __I  uint32_t USBCLKST;                   /*!< (@ 0x4004819C) USB clock status       */
+  __I  uint32_t RESERVED11[25];
+  __IO uint32_t STARTERP0;                  /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
+  __I  uint32_t RESERVED12[3];
+  __IO uint32_t STARTERP1;                  /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
+  __I  uint32_t RESERVED13[6];
+  __IO uint32_t PDSLEEPCFG;                 /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
+  __IO uint32_t PDAWAKECFG;                 /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
+  __IO uint32_t PDRUNCFG;                   /*!< (@ 0x40048238) Power configuration register */
+  __I  uint32_t RESERVED14[110];
+  __I  uint32_t DEVICE_ID;                  /*!< (@ 0x400483F4) Device ID              */
+} LPC_SYSCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                     GPIO_PIN_INT                                     -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (GPIO_PIN_INT)
+  */
+
+typedef struct {                            /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
+  __IO uint32_t ISEL;                       /*!< (@ 0x4004C000) Pin Interrupt Mode register */
+  __IO uint32_t IENR;                       /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
+  __IO uint32_t SIENR;                      /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
+  __IO uint32_t CIENR;                      /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
+  __IO uint32_t IENF;                       /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
+  __IO uint32_t SIENF;                      /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+  __IO uint32_t CIENF;                      /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+  __IO uint32_t RISE;                       /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
+  __IO uint32_t FALL;                       /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
+  __IO uint32_t IST;                        /*!< (@ 0x4004C024) Pin Interrupt Status register */
+} LPC_GPIO_PIN_INT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                    GPIO_GROUP_INT0/1                                   -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (GPIO_GROUP_INT0)
+  */
+
+typedef struct {                            /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
+  __IO uint32_t CTRL;                       /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
+  __I  uint32_t RESERVED0[7];
+  __IO uint32_t PORT_POL[2];                /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
+  __I  uint32_t RESERVED1[6];
+  __IO uint32_t PORT_ENA[2];                /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
+} LPC_GPIO_GROUP_INTx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          USB                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3  (USB)
+  */
+
+typedef struct {                            /*!< (@ 0x40080000) USB Structure          */
+  __IO uint32_t DEVCMDSTAT;                 /*!< (@ 0x40080000) USB Device Command/Status register */
+  __IO uint32_t INFO;                       /*!< (@ 0x40080004) USB Info register      */
+  __IO uint32_t EPLISTSTART;                /*!< (@ 0x40080008) USB EP Command/Status List start address */
+  __IO uint32_t DATABUFSTART;               /*!< (@ 0x4008000C) USB Data buffer start address */
+  __IO uint32_t LPM;                        /*!< (@ 0x40080010) Link Power Management register */
+  __IO uint32_t EPSKIP;                     /*!< (@ 0x40080014) USB Endpoint skip      */
+  __IO uint32_t EPINUSE;                    /*!< (@ 0x40080018) USB Endpoint Buffer in use */
+  __IO uint32_t EPBUFCFG;                   /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
+  __IO uint32_t INTSTAT;                    /*!< (@ 0x40080020) USB interrupt status register */
+  __IO uint32_t INTEN;                      /*!< (@ 0x40080024) USB interrupt enable register */
+  __IO uint32_t INTSETSTAT;                 /*!< (@ 0x40080028) USB set interrupt status register */
+  __IO uint32_t INTROUTING;                 /*!< (@ 0x4008002C) USB interrupt routing register */
+  __I  uint32_t RESERVED0[1];
+  __I  uint32_t EPTOGGLE;                   /*!< (@ 0x40080034) USB Endpoint toggle register */
+} LPC_USB_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                       GPIO_PORT                                      -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (GPIO_PORT)
+  */
+
+typedef struct {                            
+  union {
+    struct {
+      __IO uint8_t B0[32];                       /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
+      __IO uint8_t B1[32];                       /*!< (@ 0x50000020) Byte pin registers port 1 */
+    };
+    __IO uint8_t B[64];                       /*!< (@ 0x50000000) Byte pin registers port 0/1 */
+  };
+  __I  uint32_t RESERVED0[1008];
+  union {
+    struct {
+      __IO uint32_t W0[32];                      /*!< (@ 0x50001000) Word pin registers port 0 */
+      __IO uint32_t W1[32];                      /*!< (@ 0x50001080) Word pin registers port 1 */
+    };
+    __IO uint32_t W[64];                       /*!< (@ 0x50001000) Word pin registers port 0/1 */
+  };
+       uint32_t RESERVED1[960];
+  __IO uint32_t DIR[2];			/* 0x2000 */
+       uint32_t RESERVED2[30];
+  __IO uint32_t MASK[2];		/* 0x2080 */
+       uint32_t RESERVED3[30];
+  __IO uint32_t PIN[2];			/* 0x2100 */
+       uint32_t RESERVED4[30];
+  __IO uint32_t MPIN[2];		/* 0x2180 */
+       uint32_t RESERVED5[30];
+  __IO uint32_t SET[2];			/* 0x2200 */
+       uint32_t RESERVED6[30];
+  __O  uint32_t CLR[2];			/* 0x2280 */
+       uint32_t RESERVED7[30];
+  __O  uint32_t NOT[2];			/* 0x2300 */
+} LPC_GPIO_Type;
+
+
+#if defined ( __CC_ARM   )
+  #pragma no_anon_unions
+#endif
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 Peripheral memory map                                -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C_BASE              (0x40000000)
+#define LPC_WWDT_BASE             (0x40004000)
+#define LPC_USART_BASE            (0x40008000)
+#define LPC_CT16B0_BASE           (0x4000C000)
+#define LPC_CT16B1_BASE           (0x40010000)
+#define LPC_CT32B0_BASE           (0x40014000)
+#define LPC_CT32B1_BASE           (0x40018000)
+#define LPC_ADC_BASE              (0x4001C000)
+#define LPC_PMU_BASE              (0x40038000)
+#define LPC_FLASHCTRL_BASE        (0x4003C000)
+#define LPC_SSP0_BASE             (0x40040000)
+#define LPC_SSP1_BASE             (0x40058000)
+#define LPC_IOCON_BASE            (0x40044000)
+#define LPC_SYSCON_BASE           (0x40048000)
+#define LPC_GPIO_PIN_INT_BASE     (0x4004C000)
+#define LPC_GPIO_GROUP_INT0_BASE  (0x4005C000)
+#define LPC_GPIO_GROUP_INT1_BASE  (0x40060000)
+#define LPC_USB_BASE              (0x40080000)
+#define LPC_GPIO_BASE             (0x50000000)
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                Peripheral declaration                                -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C                   ((LPC_I2C_Type            *) LPC_I2C_BASE)
+#define LPC_WWDT                  ((LPC_WWDT_Type           *) LPC_WWDT_BASE)
+#define LPC_USART                 ((LPC_USART_Type          *) LPC_USART_BASE)
+#define LPC_CT16B0                ((LPC_CTxxBx_Type         *) LPC_CT16B0_BASE)
+#define LPC_CT16B1                ((LPC_CTxxBx_Type         *) LPC_CT16B1_BASE)
+#define LPC_CT32B0                ((LPC_CTxxBx_Type         *) LPC_CT32B0_BASE)
+#define LPC_CT32B1                ((LPC_CTxxBx_Type         *) LPC_CT32B1_BASE)
+#define LPC_ADC                   ((LPC_ADC_Type            *) LPC_ADC_BASE)
+#define LPC_PMU                   ((LPC_PMU_Type            *) LPC_PMU_BASE)
+#define LPC_FLASHCTRL             ((LPC_FLASHCTRL_Type      *) LPC_FLASHCTRL_BASE)
+#define LPC_SSP0                  ((LPC_SSPx_Type           *) LPC_SSP0_BASE)
+#define LPC_SSP1                  ((LPC_SSPx_Type           *) LPC_SSP1_BASE)
+#define LPC_IOCON                 ((LPC_IOCON_Type          *) LPC_IOCON_BASE)
+#define LPC_SYSCON                ((LPC_SYSCON_Type         *) LPC_SYSCON_BASE)
+#define LPC_GPIO_PIN_INT          ((LPC_GPIO_PIN_INT_Type   *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0       ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1       ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_USB                   ((LPC_USB_Type            *) LPC_USB_BASE)
+#define LPC_GPIO                  ((LPC_GPIO_Type           *) LPC_GPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group (null) */
+/** @} */ /* End of group LPC11Uxx */
+
+#ifdef __cplusplus
+}
+#endif 
+
+
+#endif  // __LPC11UXX_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/LPC11U24.sct	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0x8000  {    ; load region size_region (32k)
+  ER_IROM1 0x00000000 0x8000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
+  ; 8KB - 0xC0 = 0x1F40
+  RW_IRAM1 0x100000C0 0x1F40  {
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x20004000 0x800   { ; RW data, USB RAM
+   .ANY (USBRAM)
+  }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,325 @@
+;/*****************************************************************************
+; * @file:    startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
+; *           for the NXP LPC11xx Device Series 
+; * @version: V1.0
+; * @date:    25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+Stack_Mem       SPACE   Stack_Size
+__initial_sp        EQU     0x10002000  ; Top of RAM from LPC11U
+
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+				; for LPC11Uxx (With USB)
+                DCD     FLEX_INT0_IRQHandler      ; All GPIO pin can be routed to FLEX_INTx
+                DCD     FLEX_INT1_IRQHandler          
+                DCD     FLEX_INT2_IRQHandler                       
+                DCD     FLEX_INT3_IRQHandler                         
+                DCD     FLEX_INT4_IRQHandler                        
+                DCD     FLEX_INT5_IRQHandler
+                DCD     FLEX_INT6_IRQHandler
+                DCD     FLEX_INT7_IRQHandler                       
+                DCD     GINT0_IRQHandler                         
+                DCD     GINT1_IRQHandler          ; PIO0 (0:7)              
+                DCD     Reserved_IRQHandler	      ; Reserved
+                DCD     Reserved_IRQHandler
+                DCD     Reserved_IRQHandler       
+                DCD     Reserved_IRQHandler                       
+                DCD     SSP1_IRQHandler           ; SSP1               
+                DCD     I2C_IRQHandler            ; I2C
+                DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
+                DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
+                DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
+                DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
+                DCD     SSP0_IRQHandler           ; SSP0
+                DCD     UART_IRQHandler           ; UART
+                DCD     USB_IRQHandler            ; USB IRQ
+                DCD     USB_FIQHandler            ; USB FIQ
+                DCD     ADC_IRQHandler            ; A/D Converter
+                DCD     WDT_IRQHandler            ; Watchdog timer
+                DCD     BOD_IRQHandler            ; Brown Out Detect
+                DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
+                DCD     Reserved_IRQHandler	    ; Reserved
+                DCD     Reserved_IRQHandler       ; Reserved
+                DCD     USBWakeup_IRQHandler      ; USB wake up
+                DCD     Reserved_IRQHandler       ; Reserved
+	
+	;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+                
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+	
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+	
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled 
+; for particular peripheral.
+;NMI_Handler     PROC
+;                EXPORT  NMI_Handler               [WEAK]
+;                B       .
+;                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+Reserved_IRQHandler PROC
+                EXPORT  Reserved_IRQHandler       [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+                EXPORT  NMI_Handler               [WEAK]
+                EXPORT  FLEX_INT0_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT1_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT2_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT3_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT4_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT5_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT6_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT7_IRQHandler      [WEAK]
+                EXPORT  GINT0_IRQHandler          [WEAK]
+                EXPORT  GINT1_IRQHandler          [WEAK]
+                EXPORT  SSP1_IRQHandler           [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  TIMER16_0_IRQHandler      [WEAK]
+                EXPORT  TIMER16_1_IRQHandler      [WEAK]
+                EXPORT  TIMER32_0_IRQHandler      [WEAK]
+                EXPORT  TIMER32_1_IRQHandler      [WEAK]
+                EXPORT  SSP0_IRQHandler           [WEAK]
+                EXPORT  UART_IRQHandler           [WEAK]
+
+                EXPORT  USB_IRQHandler            [WEAK]
+                EXPORT  USB_FIQHandler            [WEAK]
+                EXPORT  ADC_IRQHandler            [WEAK]
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  BOD_IRQHandler            [WEAK]
+                EXPORT  FMC_IRQHandler            [WEAK]
+                EXPORT	USBWakeup_IRQHandler      [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/sys.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/LPC11U24.sct	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,17 @@
+
+LR_IROM1 0x00000000 0x8000  {    ; load region size_region (32k)
+  ER_IROM1 0x00000000 0x8000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
+  ; 8KB - 0xC0 = 0x1F40
+  RW_IRAM1 0x100000C0 0x1F40  {
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x20004000 0x800   { ; RW data, USB RAM
+   .ANY (USBRAM)
+  }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/startup_LPC11xx.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,308 @@
+;/*****************************************************************************
+; * @file:    startup_LPC11xx.s
+; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
+; *           for the NXP LPC11xx Device Series 
+; * @version: V1.0
+; * @date:    25. Nov. 2008
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2008 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp        EQU     0x10002000  ; Top of RAM from LPC11U
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+				; for LPC11Uxx (With USB)
+                DCD     FLEX_INT0_IRQHandler      ; All GPIO pin can be routed to FLEX_INTx
+                DCD     FLEX_INT1_IRQHandler          
+                DCD     FLEX_INT2_IRQHandler                       
+                DCD     FLEX_INT3_IRQHandler                         
+                DCD     FLEX_INT4_IRQHandler                        
+                DCD     FLEX_INT5_IRQHandler
+                DCD     FLEX_INT6_IRQHandler
+                DCD     FLEX_INT7_IRQHandler                       
+                DCD     GINT0_IRQHandler                         
+                DCD     GINT1_IRQHandler          ; PIO0 (0:7)              
+                DCD     Reserved_IRQHandler	      ; Reserved
+                DCD     Reserved_IRQHandler
+                DCD     Reserved_IRQHandler       
+                DCD     Reserved_IRQHandler                       
+                DCD     SSP1_IRQHandler           ; SSP1               
+                DCD     I2C_IRQHandler            ; I2C
+                DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
+                DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
+                DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
+                DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
+                DCD     SSP0_IRQHandler           ; SSP0
+                DCD     UART_IRQHandler           ; UART
+                DCD     USB_IRQHandler            ; USB IRQ
+                DCD     USB_FIQHandler            ; USB FIQ
+                DCD     ADC_IRQHandler            ; A/D Converter
+                DCD     WDT_IRQHandler            ; Watchdog timer
+                DCD     BOD_IRQHandler            ; Brown Out Detect
+                DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
+                DCD     Reserved_IRQHandler	    ; Reserved
+                DCD     Reserved_IRQHandler       ; Reserved
+                DCD     USBWakeup_IRQHandler      ; USB wake up
+                DCD     Reserved_IRQHandler       ; Reserved
+	
+	;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
+                
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+
+        	DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+                DCD     0xFFFFFFFF                ; Datafill
+	
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+	
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+
+; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled 
+; for particular peripheral.
+;NMI_Handler     PROC
+;                EXPORT  NMI_Handler               [WEAK]
+;                B       .
+;                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+Reserved_IRQHandler PROC
+                EXPORT  Reserved_IRQHandler       [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+; for LPC11Uxx (With USB)
+                EXPORT  NMI_Handler               [WEAK]
+                EXPORT  FLEX_INT0_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT1_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT2_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT3_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT4_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT5_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT6_IRQHandler      [WEAK]
+                EXPORT  FLEX_INT7_IRQHandler      [WEAK]
+                EXPORT  GINT0_IRQHandler          [WEAK]
+                EXPORT  GINT1_IRQHandler          [WEAK]
+                EXPORT  SSP1_IRQHandler           [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  TIMER16_0_IRQHandler      [WEAK]
+                EXPORT  TIMER16_1_IRQHandler      [WEAK]
+                EXPORT  TIMER32_0_IRQHandler      [WEAK]
+                EXPORT  TIMER32_1_IRQHandler      [WEAK]
+                EXPORT  SSP0_IRQHandler           [WEAK]
+                EXPORT  UART_IRQHandler           [WEAK]
+
+                EXPORT  USB_IRQHandler            [WEAK]
+                EXPORT  USB_FIQHandler            [WEAK]
+                EXPORT  ADC_IRQHandler            [WEAK]
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  BOD_IRQHandler            [WEAK]
+                EXPORT  FMC_IRQHandler            [WEAK]
+                EXPORT	USBWakeup_IRQHandler      [WEAK]
+
+NMI_Handler
+FLEX_INT0_IRQHandler
+FLEX_INT1_IRQHandler
+FLEX_INT2_IRQHandler
+FLEX_INT3_IRQHandler
+FLEX_INT4_IRQHandler
+FLEX_INT5_IRQHandler
+FLEX_INT6_IRQHandler
+FLEX_INT7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+SSP1_IRQHandler
+I2C_IRQHandler
+TIMER16_0_IRQHandler
+TIMER16_1_IRQHandler
+TIMER32_0_IRQHandler
+TIMER32_1_IRQHandler
+SSP0_IRQHandler
+UART_IRQHandler
+USB_IRQHandler
+USB_FIQHandler
+ADC_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+FMC_IRQHandler
+USBWakeup_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/sys.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/LPC11U24.ld	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,154 @@
+/* Linker script for mbed LPC1768 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
+  RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+  USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text.Reset_Handler)
+        *(.text.SystemInit)
+        
+        /* Only vectors and code running at reset are safe to be in first 512
+           bytes since RAM can be mapped into this area for RAM based interrupt
+           vectors. */
+        . = 0x00000200;
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+        
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM
+    
+    .heap :
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy :
+    {
+        *(.stack)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+    
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,212 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with 
+ *   GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ * 
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the ARM Limited nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+    .syntax unified
+    .arch armv6-m
+
+/* Memory Model
+   The HEAP starts at the end of the DATA section and grows upward.
+   
+   The STACK starts at the end of the RAM and grows downward.
+   
+   The HEAP and stack STACK are only checked at compile time:
+   (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+   
+   This is just a check for the bare minimum for the Heap+Stack area before
+   aborting compilation, it is not the run time limit:
+   Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0x80
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x80
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+    
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    NMI_Handler           /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+/* LPC11xx interrupts */
+    .long   WAKEUP_IRQHandler         /* 16  0 Wake-up on  pin  PIO0_0             */
+    .long   WAKEUP_IRQHandler         /* 17  1 Wake-up on  pin  PIO0_1             */
+    .long   WAKEUP_IRQHandler         /* 18  2 Wake-up on  pin  PIO0_2             */
+    .long   WAKEUP_IRQHandler         /* 19  3 Wake-up on  pin  PIO0_3             */
+    .long   WAKEUP_IRQHandler         /* 20  4 Wake-up on  pin  PIO0_4             */
+    .long   WAKEUP_IRQHandler         /* 21  5 Wake-up on  pin  PIO0_5             */
+    .long   WAKEUP_IRQHandler         /* 22  6 Wake-up on  pin  PIO0_6             */
+    .long   WAKEUP_IRQHandler         /* 23  7 Wake-up on  pin  PIO0_7             */
+    .long   WAKEUP_IRQHandler         /* 24  8 Wake-up on  pin  PIO0_8             */
+    .long   WAKEUP_IRQHandler         /* 25  9 Wake-up on  pin  PIO0_9             */
+    .long   WAKEUP_IRQHandler         /* 26 10 Wake-up on  pin  PIO0_10            */
+    .long   WAKEUP_IRQHandler         /* 27 11 Wake-up on  pin  PIO0_11            */
+    .long   WAKEUP_IRQHandler         /* 28 12 Wake-up on  pin  PIO1_0             */
+    .long   Default_Handler           /* 29 13                                     */
+    .long   SSP1_IRQHandler           /* 30 14 SSP1                                */
+    .long   I2C_IRQHandler            /* 31 15 I2C0 SI (state change)              */
+    .long   TIMER16_0_IRQHandler      /* 32 16 CT16B0 16 bit timer 0               */
+    .long   TIMER16_1_IRQHandler      /* 33 17 CT16B1 16 bit timer 1               */
+    .long   TIMER32_0_IRQHandler      /* 34 18 CT32B0 32 bit timer 0               */
+    .long   TIMER32_1_IRQHandler      /* 35 19 CT32B1 32 bit timer 1               */
+    .long   SSP0_IRQHandler           /* 36 20 SSP                                 */
+    .long   UART_IRQHandler           /* 37 21 UART                                */
+    .long   Default_Handler           /* 38 22                                     */
+    .long   Default_Handler           /* 39 23                                     */
+    .long   ADC_IRQHandler            /* 40 24 ADC end of conversion               */
+    .long   WDT_IRQHandler            /* 41 25 Watchdog interrupt (WDINT)          */
+    .long   BOD_IRQHandler            /* 42 26 BOD Brown-out detect                */
+    .long   Default_Handler           /* 43 27                                     */
+    .long   PIOINT3_IRQHandler        /* 44 28 PIO_3  GPIO interrupt status of port 3 */
+    .long   PIOINT2_IRQHandler        /* 45 29 PIO_2  GPIO interrupt status of port 2 */
+    .long   PIOINT1_IRQHandler        /* 46 30 PIO_1  GPIO interrupt status of port 1 */
+    .long   PIOINT0_IRQHandler        /* 47 31 PIO_0  GPIO interrupt status of port 0 */
+    
+    .size    __isr_vector, . - __isr_vector
+
+    .section .text.Reset_Handler
+    .thumb
+    .thumb_func
+    .align 2
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in 
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble    .flash_to_ram_loop_end
+
+    movs    r4, 0
+.flash_to_ram_loop:
+    ldr    r0, [r1,r4]
+    str    r0, [r2,r4]
+    adds    r4, 4
+    cmp    r4, r3
+    blt    .flash_to_ram_loop
+.flash_to_ram_loop_end:
+
+    ldr    r0, =SystemInit
+    blx    r0
+    ldr    r0, =_start
+    bx    r0
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+    
+    .text
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_default_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+    
+    def_default_handler    NMI_Handler
+    def_default_handler    HardFault_Handler
+    def_default_handler    SVC_Handler
+    def_default_handler    PendSV_Handler
+    def_default_handler    SysTick_Handler
+    def_default_handler    Default_Handler
+    
+    def_default_handler    WAKEUP_IRQHandler
+    def_default_handler    SSP1_IRQHandler
+    def_default_handler    I2C_IRQHandler
+    def_default_handler    TIMER16_0_IRQHandler
+    def_default_handler    TIMER16_1_IRQHandler
+    def_default_handler    TIMER32_0_IRQHandler
+    def_default_handler    TIMER32_1_IRQHandler
+    def_default_handler    SSP0_IRQHandler
+    def_default_handler    UART_IRQHandler
+    def_default_handler    ADC_IRQHandler
+    def_default_handler    WDT_IRQHandler
+    def_default_handler    BOD_IRQHandler
+    def_default_handler    PIOINT3_IRQHandler
+    def_default_handler    PIOINT2_IRQHandler
+    def_default_handler    PIOINT1_IRQHandler
+    def_default_handler    PIOINT0_IRQHandler
+
+    .weak    DEF_IRQHandler
+    .set    DEF_IRQHandler, Default_Handler
+
+    .end

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/LPC11U24.ld	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,152 @@
+/* mbed - LPC11U24 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 4.1
+ */
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+  /* Define each memory region */
+  MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32k */
+  RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */
+  RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
+}
+  /* Define a symbol for the top of each memory region */
+  __top_MFlash32 = 0x0 + 0x8000;
+  __top_RamLoc8 = 0x10000000 + 0x2000;
+  __top_RamUsb2 = 0x20004000 + 0x800;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+    /* MAIN TEXT SECTION */ 
+    .text : ALIGN(4)
+    {
+        FILL(0xff)
+        KEEP(*(.isr_vector))
+        
+        /* Global Section Table */
+        . = ALIGN(4) ;
+        __section_table_start = .;
+        __data_section_table = .;
+        LONG(LOADADDR(.data));
+        LONG(    ADDR(.data)) ;
+        LONG(  SIZEOF(.data));
+        LONG(LOADADDR(.data_RAM2));
+        LONG(    ADDR(.data_RAM2)) ;
+        LONG(  SIZEOF(.data_RAM2));
+        __data_section_table_end = .;
+        __bss_section_table = .;
+        LONG(    ADDR(.bss));
+        LONG(  SIZEOF(.bss));
+        LONG(    ADDR(.bss_RAM2));
+        LONG(  SIZEOF(.bss_RAM2));
+        __bss_section_table_end = .;
+        __section_table_end = . ;
+        /* End of Global Section Table */
+        
+
+        *(.after_vectors*)
+        
+        *(.text*)
+        *(.rodata .rodata.*)
+        . = ALIGN(4);
+        
+        /* C++ constructors etc */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+        
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+        
+        KEEP(*(.fini));
+        
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+        
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+        /* End C++ */
+    } > MFlash32
+
+    /*
+     * for exception handling/unwind - some Newlib functions (in common
+     * with C++ and STDC++) use this.
+     */
+    .ARM.extab : ALIGN(4)
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > MFlash32
+    __exidx_start = .;
+    
+    .ARM.exidx : ALIGN(4)
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > MFlash32
+    __exidx_end = .;
+    
+    _etext = .;
+        
+    
+    .data_RAM2 : ALIGN(4)
+    {
+       FILL(0xff)
+        *(.data.$RAM2*)
+        *(.data.$RamUsb2*)
+       . = ALIGN(4) ;
+    } > RamUsb2 AT>MFlash32
+    
+    /* MAIN DATA SECTION */
+
+    .uninit_RESERVED : ALIGN(4)
+    {
+        KEEP(*(.bss.$RESERVED*))
+    } > RamLoc8
+
+    .data : ALIGN(4)
+    {
+        FILL(0xff)
+        _data = .;
+        *(vtable)
+        *(.data*)
+        . = ALIGN(4) ;
+        _edata = .;
+    } > RamLoc8 AT>MFlash32
+
+    
+    .bss_RAM2 : ALIGN(4)
+    {
+        *(.bss.$RAM2*)
+        *(.bss.$RamUsb2*)
+       . = ALIGN(4) ;
+    } > RamUsb2
+
+    /* MAIN BSS SECTION */
+    .bss : ALIGN(4)
+    {
+        _bss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4) ;
+        _ebss = .;
+        PROVIDE(end = .);
+    } > RamLoc8
+    
+    PROVIDE(_pvHeapStart = .);
+    PROVIDE(_vStackTop = __top_RamLoc8 - 0);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,161 @@
+extern "C" {
+
+#include "LPC11Uxx.h"
+
+#define WEAK          __attribute__ ((weak))
+#define ALIAS(f)      __attribute__ ((weak, alias (#f)))
+#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))
+
+     void ResetISR            (void);
+WEAK void NMI_Handler         (void);
+WEAK void HardFault_Handler   (void);
+WEAK void SVCall_Handler      (void);
+WEAK void PendSV_Handler      (void);
+WEAK void SysTick_Handler     (void);
+WEAK void IntDefaultHandler   (void);
+     void FLEX_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+     void FLEX_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+     void FLEX_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+     void FLEX_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+     void FLEX_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
+     void FLEX_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
+     void FLEX_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
+     void FLEX_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
+     void GINT0_IRQHandler    (void) ALIAS(IntDefaultHandler);
+     void GINT1_IRQHandler    (void) ALIAS(IntDefaultHandler);
+     void SSP1_IRQHandler     (void) ALIAS(IntDefaultHandler);
+     void I2C_IRQHandler      (void) ALIAS(IntDefaultHandler);
+     void TIMER16_0_IRQHandler(void) ALIAS(IntDefaultHandler);
+     void TIMER16_1_IRQHandler(void) ALIAS(IntDefaultHandler);
+     void TIMER32_0_IRQHandler(void) ALIAS(IntDefaultHandler);
+     void TIMER32_1_IRQHandler(void) ALIAS(IntDefaultHandler);
+     void SSP0_IRQHandler     (void) ALIAS(IntDefaultHandler);
+     void UART_IRQHandler     (void) ALIAS(IntDefaultHandler);
+     void USB_IRQHandler      (void) ALIAS(IntDefaultHandler);
+     void USB_FIQHandler      (void) ALIAS(IntDefaultHandler);
+     void ADC_IRQHandler      (void) ALIAS(IntDefaultHandler);
+     void WDT_IRQHandler      (void) ALIAS(IntDefaultHandler);
+     void BOD_IRQHandler      (void) ALIAS(IntDefaultHandler);
+     void FMC_IRQHandler      (void) ALIAS(IntDefaultHandler);
+     void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+extern void __libc_init_array(void);
+extern int main(void);
+extern void _vStackTop(void);
+
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+    &_vStackTop,
+    ResetISR,
+    NMI_Handler,
+    HardFault_Handler,
+    0,
+    0,
+    0,
+    0,
+    0,
+    0,
+    0,
+    SVCall_Handler,
+    0,
+    0,
+    PendSV_Handler,
+    SysTick_Handler,
+    FLEX_INT0_IRQHandler,
+    FLEX_INT1_IRQHandler,
+    FLEX_INT2_IRQHandler,
+    FLEX_INT3_IRQHandler,
+    FLEX_INT4_IRQHandler,
+    FLEX_INT5_IRQHandler,
+    FLEX_INT6_IRQHandler,
+    FLEX_INT7_IRQHandler,
+    GINT0_IRQHandler,
+    GINT1_IRQHandler,
+    0,
+    0,
+    0,
+    0,
+    SSP1_IRQHandler,
+    I2C_IRQHandler,
+    TIMER16_0_IRQHandler,
+    TIMER16_1_IRQHandler,
+    TIMER32_0_IRQHandler,
+    TIMER32_1_IRQHandler,
+    SSP0_IRQHandler,
+    UART_IRQHandler,
+    USB_IRQHandler,
+    USB_FIQHandler,
+    ADC_IRQHandler,
+    WDT_IRQHandler,
+    BOD_IRQHandler,
+    FMC_IRQHandler,
+    0,
+    0,
+    USBWakeup_IRQHandler,
+    0,
+};
+
+AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int *pulSrc = (unsigned int*) romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
+}
+
+AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
+}
+
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table_end;
+
+AFTER_VECTORS void ResetISR(void) {
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+    
+    // Data Init
+    SectionTableAddr = &__data_section_table;
+    while (SectionTableAddr < &__data_section_table_end) {
+        LoadAddr = *SectionTableAddr++;
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+    
+    // BSS Init
+    while (SectionTableAddr < &__bss_section_table_end) {
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+    
+    SystemInit();
+    __libc_init_array();
+    main();
+    while (1) {;}
+}
+
+AFTER_VECTORS void NMI_Handler      (void) {while(1){}}
+AFTER_VECTORS void HardFault_Handler(void) {while(1){}}
+AFTER_VECTORS void SVCall_Handler   (void) {while(1){}}
+AFTER_VECTORS void PendSV_Handler   (void) {while(1){}}
+AFTER_VECTORS void SysTick_Handler  (void) {while(1){}}
+AFTER_VECTORS void IntDefaultHandler(void) {while(1){}}
+
+#include <stdlib.h>
+
+void *operator new  (size_t size) {return malloc(size);}
+void *operator new[](size_t size) {return malloc(size);}
+
+void operator delete  (void *p) {free(p);}
+void operator delete[](void *p) {free(p);}
+
+int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {
+    return 0;
+}
+
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/LPC11U24.ld	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,207 @@
+/* Linker script for mbed LPC1768
+ *
+ * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ *  Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(__cs3_reset_cortex_m)
+SEARCH_DIR(.)
+
+/*
+ram ORIGIN: 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
+ram LENGTH: 8KB - 0xC0 = 0xF40
+*/
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00000000, LENGTH = 32K
+  
+  ram (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+  usb_ram (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_cortex_m)
+EXTERN(__cs3_interrupt_vector_cortex_m)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __cs3_region_start_rom = .;
+    *(.cs3.region-head.rom)
+    __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
+    *(.cs3.interrupt_vector)
+    /* Make sure we pulled in an interrupt vector.  */
+    ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
+    *(.rom)
+    *(.rom.b)
+
+    __cs3_reset = __cs3_reset_cortex_m;
+    *(.cs3.reset)
+    /* Make sure we pulled in some reset code.  */
+    ASSERT (. != __cs3_reset, "No reset code");
+
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table)
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    . = ALIGN(4);
+    KEEP(*(.init))
+
+    . = ALIGN(4);
+    __preinit_array_start = .;
+    KEEP (*(.preinit_array))
+    __preinit_array_end = .;
+
+    . = ALIGN(4);
+    __init_array_start = .;
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    __init_array_end = .;
+
+    . = ALIGN(0x4);
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+
+    . = ALIGN(4);
+    KEEP(*(.fini))
+
+    . = ALIGN(4);
+    __fini_array_start = .;
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    __fini_array_end = .;
+
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    . = ALIGN(4);
+    __cs3_regions = .;
+    LONG (0)
+    LONG (__cs3_region_init_ram)
+    LONG (__cs3_region_start_ram)
+    LONG (__cs3_region_init_size_ram)
+    LONG (__cs3_region_zero_size_ram)
+  }
+
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >rom
+  __exidx_end = .;
+  .text.align :
+  {
+    . = ALIGN(8);
+    _etext = .;
+  } >rom
+  __cs3_region_size_rom = LENGTH(rom);
+  __cs3_region_num = 1;
+  
+  .data :
+  {
+    __cs3_region_start_ram = .;
+    *(.cs3.region-head.ram)
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    *(.ram)
+    . = ALIGN (8);
+    _edata = .;
+  } >ram AT>rom
+  .bss :
+  {
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    *(.ram.b)
+    . = ALIGN (8);
+    _end = .;
+    __end = .;
+  } >ram AT>rom
+  
+  .heap (NOLOAD) :
+  {
+    *(.heap)
+  } >ram
+  .stack (__cs3_stack - __cs3_stack_size) (NOLOAD):
+  {
+    *(.stack)
+    _estack = .;
+    PROVIDE(estack = .);
+  } >ram
+
+  __cs3_region_init_ram = LOADADDR (.data);
+  __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
+  __cs3_region_zero_size_ram = _end - _edata;
+  __cs3_region_size_ram = LENGTH(ram);
+  __cs3_region_num = 1;
+
+  .stab 0 (NOLOAD) : { *(.stab) }
+  .stabstr 0 (NOLOAD) : { *(.stabstr) }
+  /* DWARF debug sections.
+   * Symbols in the DWARF debugging sections are relative to the beginning
+   * of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/startup_LPC11xx.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,112 @@
+    .equ    Stack_Size, 0x80
+    .section ".stack", "w"
+    .align  3
+    .globl  __cs3_stack_mem
+    .globl  __cs3_stack_size
+__cs3_stack_mem:
+    .if     Stack_Size
+    .space  Stack_Size
+    .endif
+    .size   __cs3_stack_mem,  . - __cs3_stack_mem
+    .set    __cs3_stack_size, . - __cs3_stack_mem
+
+    .equ    Heap_Size,  0x80
+    .section ".heap", "w"
+    .align  3
+    .globl  __cs3_heap_start
+    .globl  __cs3_heap_end
+__cs3_heap_start:
+    .if     Heap_Size
+    .space  Heap_Size
+    .endif
+__cs3_heap_end:
+
+    .section ".cs3.interrupt_vector"
+    .globl  __cs3_interrupt_vector_cortex_m
+    .type   __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+    .long   __cs3_stack
+    .long   __cs3_reset
+    .long   NMI_Handler
+    .long   HardFault_Handler
+    .long   0
+    .long   0
+    .long   0
+    .long   0
+    .long   0
+    .long   0
+    .long   0
+    .long   SVC_Handler
+    .long   0
+    .long   0
+    .long   PendSV_Handler
+    .long   SysTick_Handler
+
+    .long   DEF_IRQHandler
+
+    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+    .thumb
+
+    .section .cs3.reset,"x",%progbits
+    .thumb_func
+    .globl  __cs3_reset_cortex_m
+    .type   __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+    .fnstart
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0,=__cs3_start_c
+    BX      R0
+    .pool
+    .cantunwind
+    .fnend
+    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+    .section ".text"
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ     DEF_IRQHandler
+
+    .end

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CS/sys.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,79 @@
+#include "cmsis.h"
+#include <sys/types.h>
+#include <errno.h>
+
+extern "C" {
+
+struct SCS3Regions {
+    unsigned long   Dummy;
+    unsigned long*  InitRam;
+    unsigned long*  StartRam;
+    unsigned long   InitSizeRam;
+    unsigned long   ZeroSizeRam;
+};
+
+extern unsigned long __cs3_regions;
+extern unsigned long __cs3_heap_start;
+
+int  main(void);
+void __libc_init_array(void);
+void exit(int ErrorCode);
+
+static void *heap_pointer = NULL;
+
+void __cs3_start_c(void) {
+    static SCS3Regions* pCS3Regions = (SCS3Regions*)&__cs3_regions;
+    unsigned long* pulDest;
+    unsigned long* pulSrc;
+    unsigned long  ByteCount;
+    unsigned long  i;
+    
+    pulSrc = pCS3Regions->InitRam;
+    pulDest = pCS3Regions->StartRam;
+    ByteCount = pCS3Regions->InitSizeRam;
+    if (pulSrc != pulDest) {
+        for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
+            *(pulDest++) = *(pulSrc++);
+        }
+    } else {
+        pulDest = (unsigned long*)(void*)((char*)pulDest + ByteCount);
+    }
+    
+    ByteCount = pCS3Regions->ZeroSizeRam;
+    for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
+        *(pulDest++) = 0;
+    }
+    
+    heap_pointer = &__cs3_heap_start;
+     __libc_init_array();
+    exit(main());
+}
+
+int _kill(int pid, int sig) {
+    errno = EINVAL;
+    return -1;
+}
+
+void _exit(int status) {
+    exit(status);
+}
+
+int _getpid(void) {
+    return 1;
+}
+
+void *_sbrk(unsigned int incr) {
+    void *mem;
+    
+    unsigned int next = ((((unsigned int)heap_pointer + incr) + 7) & ~7);
+    if (next > __get_MSP()) {
+        mem = NULL;
+    } else {
+        mem = (void *)heap_pointer;
+    }
+    heap_pointer = (void *)next;
+    
+    return mem;
+}
+
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC11Uxx.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+
+#include "cmsis_nvic.h"
+
+/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
+ * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0), 
+ * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF 
+ * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
+ * 
+ * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
+ * above the vector table before 0x200 will actually go to RAM. So we need to provide 
+ * a solution where the compiler gets the right results based on the memory map
+ *
+ * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
+ *  - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
+ *  - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
+ * 
+ * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there  
+ *  - No flash accesses will go to ram, as there will be nothing there
+ *  - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
+ *  - RAM overhead: 0, FLASH overhead: 320 bytes
+ *
+ * Option 2 is the one to go for, as RAM is the most valuable resource
+ */
+
+#define NVIC_NUM_VECTORS (16 + 32)            // CORE + MCU Peripherals
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000)  // Vectors positioned at start of RAM
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    int i;
+    // Space for dynamic vectors, initialised to allocate in R/W
+    static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+    
+    // Copy and switch to dynamic vectors if first time called
+    if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {     
+      uint32_t *old_vectors = (uint32_t *)0;         // FLASH vectors are at 0x0
+      for(i = 0; i < NVIC_NUM_VECTORS; i++) {    
+            vectors[i] = old_vectors[i];
+        }
+        LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
+    }
+
+    // Set the vector 
+    vectors[IRQn + 16] = vector; 
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    // We can always read vectors at 0x0, as the addresses are remapped
+    uint32_t *vectors = (uint32_t*)0; 
+
+    // Return the vector
+    return vectors[IRQn + 16];
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,23 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/power_api.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,82 @@
+/****************************************************************************
+ *   $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267                   $
+ *   Project: NXP LPC11Uxx software example  
+ *
+ *   Description:
+ *     Power API Header File for NXP LPC11Uxx Device Series 
+ *
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+****************************************************************************/
+#ifndef __LPC11UXX_POWER_API_H__
+#define __LPC11UXX_POWER_API_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#define PWRROMD_PRESENT
+
+typedef	struct _PWRD {
+  void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
+  void (*set_power)(unsigned int cmd[], unsigned int resp[]);
+}  PWRD;
+
+typedef	struct _ROM {
+#ifdef USBROMD_PRESENT
+   const USB * pUSBD;
+#else
+   const unsigned p_usbd;
+#endif /* USBROMD_PRESENT */
+   const unsigned p_clib;
+   const unsigned p_cand;
+#ifdef PWRROMD_PRESENT
+   const PWRD * pPWRD;
+#else
+   const unsigned p_pwrd;
+#endif /* PWRROMD_PRESENT */
+   const unsigned p_dev1;
+   const unsigned p_dev2;
+   const unsigned p_dev3;
+   const unsigned p_dev4; 
+}  ROM;
+
+//PLL setup related definitions
+#define	CPU_FREQ_EQU  		0       //main PLL freq must be equal to the specified 
+#define	CPU_FREQ_LTE		1       //main PLL freq must be less than or equal the specified
+#define	CPU_FREQ_GTE		2       //main PLL freq must be greater than or equal the specified
+#define	CPU_FREQ_APPROX		3       //main PLL freq must be as close as possible the specified
+
+#define	PLL_CMD_SUCCESS		0       //PLL setup successfully found
+#define	PLL_INVALID_FREQ	1       //specified freq out of range (either input or output)
+#define	PLL_INVALID_MODE	2       //invalid mode (see above for valid) specified
+#define	PLL_FREQ_NOT_FOUND	3       //specified freq not found under specified conditions
+#define	PLL_NOT_LOCKED		4       //PLL not locked => no changes to the PLL setup
+
+//power setup elated definitions
+#define	PARAM_DEFAULT			0   //default power settings (voltage regulator, flash interface)
+#define	PARAM_CPU_PERFORMANCE	1   //setup for maximum CPU performance (higher current, more computation)
+#define	PARAM_EFFICIENCY		2   //balanced setting (power vs CPU performance)
+#define	PARAM_LOW_CURRENT		3   //lowest active current, lowest CPU performance
+
+#define	PARAM_CMD_SUCCESS		0   //power setting successfully found
+#define	PARAM_INVALID_FREQ		1   //specified freq out of range (=0 or > 50 MHz)
+#define	PARAM_INVALID_MODE		2   //specified mode not valid (see above for valid)
+
+#define MAX_CLOCK_KHZ_PARAM                50000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __LPC11UXX_POWER_API_H__ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/system_LPC11Uxx.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,450 @@
+/******************************************************************************
+ * @file     system_LPC11Uxx.c
+ * @purpose  CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+ *           for the NXP LPC13xx Device Series
+ * @version  V1.10
+ * @date     24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC11Uxx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+//   <h> System Oscillator Control Register (SYSOSCCTRL)
+//     <o1.0>      BYPASS: System Oscillator Bypass Enable
+//                     <i> If enabled then PLL input (sys_osc_clk) is fed
+//                     <i> directly from XTALIN and XTALOUT pins.
+//     <o1.9>      FREQRANGE: System Oscillator Frequency Range
+//                     <i> Determines frequency range for Low-power oscillator.
+//                   <0=> 1 - 20 MHz
+//                   <1=> 15 - 25 MHz
+//   </h>
+//
+//   <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+//     <o2.0..4>   DIVSEL: Select Divider for Fclkana
+//                     <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
+//                   <0-31>
+//     <o2.5..8>   FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+//                   <0=> Undefined
+//                   <1=> 0.5 MHz
+//                   <2=> 0.8 MHz
+//                   <3=> 1.1 MHz
+//                   <4=> 1.4 MHz
+//                   <5=> 1.6 MHz
+//                   <6=> 1.8 MHz
+//                   <7=> 2.0 MHz
+//                   <8=> 2.2 MHz
+//                   <9=> 2.4 MHz
+//                   <10=> 2.6 MHz
+//                   <11=> 2.7 MHz
+//                   <12=> 2.9 MHz
+//                   <13=> 3.1 MHz
+//                   <14=> 3.2 MHz
+//                   <15=> 3.4 MHz
+//   </h>
+//
+//   <h> System PLL Control Register (SYSPLLCTRL)
+//                   <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+//                   <i> F_clkin must be in the range of  10 MHz to  25 MHz
+//                   <i> F_CCO   must be in the range of 156 MHz to 320 MHz
+//     <o3.0..4>   MSEL: Feedback Divider Selection
+//                     <i> M = MSEL + 1
+//                   <0-31>
+//     <o3.5..6>   PSEL: Post Divider Selection
+//                   <0=> P = 1
+//                   <1=> P = 2
+//                   <2=> P = 4
+//                   <3=> P = 8
+//   </h>
+//
+//   <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+//     <o4.0..1>   SEL: System PLL Clock Source
+//                   <0=> IRC Oscillator
+//                   <1=> System Oscillator
+//                   <2=> Reserved
+//                   <3=> Reserved
+//   </h>
+//
+//   <h> Main Clock Source Select Register (MAINCLKSEL)
+//     <o5.0..1>   SEL: Clock Source for Main Clock
+//                   <0=> IRC Oscillator
+//                   <1=> Input Clock to System PLL
+//                   <2=> WDT Oscillator
+//                   <3=> System PLL Clock Out
+//   </h>
+//
+//   <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+//     <o6.0..7>   DIV: System AHB Clock Divider
+//                     <i> Divides main clock to provide system clock to core, memories, and peripherals.
+//                     <i> 0 = is disabled
+//                   <0-255>
+//   </h>
+//
+//   <h> USB PLL Control Register (USBPLLCTRL)
+//                   <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+//                   <i> F_clkin must be in the range of  10 MHz to  25 MHz
+//                   <i> F_CCO   must be in the range of 156 MHz to 320 MHz
+//     <o7.0..4>   MSEL: Feedback Divider Selection
+//                     <i> M = MSEL + 1
+//                   <0-31>
+//     <o7.5..6>   PSEL: Post Divider Selection
+//                   <0=> P = 1
+//                   <1=> P = 2
+//                   <2=> P = 4
+//                   <3=> P = 8
+//   </h>
+//
+//   <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
+//     <o8.0..1>   SEL: USB PLL Clock Source
+//                     <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
+//                   <0=> IRC Oscillator
+//                   <1=> System Oscillator
+//                   <2=> Reserved
+//                   <3=> Reserved
+//   </h>
+//
+//   <h> USB Clock Source Select Register (USBCLKSEL)
+//     <o9.0..1>   SEL: System PLL Clock Source
+//                   <0=> USB PLL out
+//                   <1=> Main clock
+//                   <2=> Reserved
+//                   <3=> Reserved
+//   </h>
+//
+//   <h> USB Clock Divider Register (USBCLKDIV)
+//     <o10.0..7>  DIV: USB Clock Divider
+//                     <i> Divides USB clock to 48 MHz.
+//                     <i> 0 = is disabled
+//                   <0-255>
+//   </h>
+// </e>
+*/
+#define CLOCK_SETUP           1
+#define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
+#define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
+#define SYSPLLCTRL_Val        0x00000023              // Reset: 0x000
+#define SYSPLLCLKSEL_Val      0x00000001              // Reset: 0x000
+#define MAINCLKSEL_Val        0x00000003              // Reset: 0x000
+#define SYSAHBCLKDIV_Val      0x00000001              // Reset: 0x001
+#define USBPLLCTRL_Val        0x00000023              // Reset: 0x000
+#define USBPLLCLKSEL_Val      0x00000001              // Reset: 0x000
+#define USBCLKSEL_Val         0x00000000              // Reset: 0x000
+#define USBCLKDIV_Val         0x00000001              // Reset: 0x001
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+  Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask)                     (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val),  ~0x00000003))
+   #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val),  ~0x000001FF))
+   #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
+   #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val),  ~0x000001FF))
+   #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val),  ~0x00000003))
+   #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+   #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
+   #error "USBPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((USBPLLCTRL_Val),  ~0x000001FF))
+   #error "USBPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
+   #error "USBCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
+   #error "USBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+    
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+#define __SYS_OSC_CLK     (    __XTAL)    /* Main oscillator frequency        */
+#define __IRC_OSC_CLK     (12000000UL)    /* Internal RC oscillator frequency */
+
+
+#define __FREQSEL   ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL   (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP)                         /* Clock Setup              */
+  #if  (__FREQSEL ==  0)
+    #define __WDT_OSC_CLK        ( 0)                  /* undefined */
+  #elif (__FREQSEL ==  1)
+    #define __WDT_OSC_CLK        ( 500000 / __DIVSEL)
+  #elif (__FREQSEL ==  2)
+    #define __WDT_OSC_CLK        ( 800000 / __DIVSEL)
+  #elif (__FREQSEL ==  3)
+    #define __WDT_OSC_CLK        (1100000 / __DIVSEL)
+  #elif (__FREQSEL ==  4)
+    #define __WDT_OSC_CLK        (1400000 / __DIVSEL)
+  #elif (__FREQSEL ==  5)
+    #define __WDT_OSC_CLK        (1600000 / __DIVSEL)
+  #elif (__FREQSEL ==  6)
+    #define __WDT_OSC_CLK        (1800000 / __DIVSEL)
+  #elif (__FREQSEL ==  7)
+    #define __WDT_OSC_CLK        (2000000 / __DIVSEL)
+  #elif (__FREQSEL ==  8)
+    #define __WDT_OSC_CLK        (2200000 / __DIVSEL)
+  #elif (__FREQSEL ==  9)
+    #define __WDT_OSC_CLK        (2400000 / __DIVSEL)
+  #elif (__FREQSEL == 10)
+    #define __WDT_OSC_CLK        (2600000 / __DIVSEL)
+  #elif (__FREQSEL == 11)
+    #define __WDT_OSC_CLK        (2700000 / __DIVSEL)
+  #elif (__FREQSEL == 12)
+    #define __WDT_OSC_CLK        (2900000 / __DIVSEL)
+  #elif (__FREQSEL == 13)
+    #define __WDT_OSC_CLK        (3100000 / __DIVSEL)
+  #elif (__FREQSEL == 14)
+    #define __WDT_OSC_CLK        (3200000 / __DIVSEL)
+  #else
+    #define __WDT_OSC_CLK        (3400000 / __DIVSEL)
+  #endif
+
+  /* sys_pllclkin calculation */
+  #if   ((SYSPLLCLKSEL_Val & 0x03) == 0)
+    #define __SYS_PLLCLKIN           (__IRC_OSC_CLK)
+  #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+    #define __SYS_PLLCLKIN           (__SYS_OSC_CLK)
+  #else
+    #define __SYS_PLLCLKIN           (0)
+  #endif
+
+  #define  __SYS_PLLCLKOUT         (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+  /* main clock calculation */
+  #if   ((MAINCLKSEL_Val & 0x03) == 0)
+    #define __MAIN_CLOCK             (__IRC_OSC_CLK)
+  #elif ((MAINCLKSEL_Val & 0x03) == 1)
+    #define __MAIN_CLOCK             (__SYS_PLLCLKIN)
+  #elif ((MAINCLKSEL_Val & 0x03) == 2)
+    #if (__FREQSEL ==  0)
+      #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+    #else
+      #define __MAIN_CLOCK           (__WDT_OSC_CLK)
+    #endif
+  #elif ((MAINCLKSEL_Val & 0x03) == 3)
+    #define __MAIN_CLOCK             (__SYS_PLLCLKOUT)
+  #else
+    #define __MAIN_CLOCK             (0)
+  #endif
+
+  #define __SYSTEM_CLOCK             (__MAIN_CLOCK / SYSAHBCLKDIV_Val)         
+
+#else
+  #define __SYSTEM_CLOCK             (__IRC_OSC_CLK)
+#endif  // CLOCK_SETUP 
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  uint32_t wdt_osc = 0;
+
+  /* Determine clock frequency according to clock register values             */
+  switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+    case 0:  wdt_osc =       0; break;
+    case 1:  wdt_osc =  500000; break;
+    case 2:  wdt_osc =  800000; break;
+    case 3:  wdt_osc = 1100000; break;
+    case 4:  wdt_osc = 1400000; break;
+    case 5:  wdt_osc = 1600000; break;
+    case 6:  wdt_osc = 1800000; break;
+    case 7:  wdt_osc = 2000000; break;
+    case 8:  wdt_osc = 2200000; break;
+    case 9:  wdt_osc = 2400000; break;
+    case 10: wdt_osc = 2600000; break;
+    case 11: wdt_osc = 2700000; break;
+    case 12: wdt_osc = 2900000; break;
+    case 13: wdt_osc = 3100000; break;
+    case 14: wdt_osc = 3200000; break;
+    case 15: wdt_osc = 3400000; break;
+  }
+  wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+ 
+  switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+    case 0:                             /* Internal RC oscillator             */
+      SystemCoreClock = __IRC_OSC_CLK;
+      break;
+    case 1:                             /* Input Clock to System PLL          */
+      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+          case 0:                       /* Internal RC oscillator             */
+            SystemCoreClock = __IRC_OSC_CLK;
+            break;
+          case 1:                       /* System oscillator                  */
+            SystemCoreClock = __SYS_OSC_CLK;
+            break;
+          case 2:                       /* Reserved                           */
+          case 3:                       /* Reserved                           */
+            SystemCoreClock = 0;
+            break;
+      }
+      break;
+    case 2:                             /* WDT Oscillator                     */
+      SystemCoreClock = wdt_osc;
+      break;
+    case 3:                             /* System PLL Clock Out               */
+      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+          case 0:                       /* Internal RC oscillator             */
+            if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+              SystemCoreClock = __IRC_OSC_CLK;
+            } else {
+              SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+            }
+            break;
+          case 1:                       /* System oscillator                  */
+            if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+              SystemCoreClock = __SYS_OSC_CLK;
+            } else {
+              SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+            }
+            break;
+          case 2:                       /* Reserved                           */
+          case 3:                       /* Reserved                           */
+            SystemCoreClock = 0;
+            break;
+      }
+      break;
+  }
+
+  SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;  
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void) {
+  volatile uint32_t i;
+
+#if (CLOCK_SETUP)                                 /* Clock Setup              */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+  LPC_SYSCON->PDRUNCFG     &= ~(1 << 5);          /* Power-up System Osc      */
+  LPC_SYSCON->SYSOSCCTRL    = SYSOSCCTRL_Val;
+  for (i = 0; i < 200; i++) __NOP();
+#endif
+
+  LPC_SYSCON->SYSPLLCLKSEL  = SYSPLLCLKSEL_Val;   /* Select PLL Input         */
+  LPC_SYSCON->SYSPLLCLKUEN  = 0x01;               /* Update Clock Source      */
+  LPC_SYSCON->SYSPLLCLKUEN  = 0x00;               /* Toggle Update Register   */
+  LPC_SYSCON->SYSPLLCLKUEN  = 0x01;
+  while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01));     /* Wait Until Updated       */
+#if ((MAINCLKSEL_Val & 0x03) == 3)                /* Main Clock is PLL Out    */
+  LPC_SYSCON->SYSPLLCTRL    = SYSPLLCTRL_Val;
+  LPC_SYSCON->PDRUNCFG     &= ~(1 << 7);          /* Power-up SYSPLL          */
+  while (!(LPC_SYSCON->SYSPLLSTAT & 0x01));	      /* Wait Until PLL Locked    */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+  LPC_SYSCON->WDTOSCCTRL    = WDTOSCCTRL_Val;
+  LPC_SYSCON->PDRUNCFG     &= ~(1 << 6);          /* Power-up WDT Clock       */
+  for (i = 0; i < 200; i++) __NOP();
+#endif
+
+  LPC_SYSCON->MAINCLKSEL    = MAINCLKSEL_Val;     /* Select PLL Clock Output  */
+  LPC_SYSCON->MAINCLKUEN    = 0x01;               /* Update MCLK Clock Source */
+  LPC_SYSCON->MAINCLKUEN    = 0x00;               /* Toggle Update Register   */
+  LPC_SYSCON->MAINCLKUEN    = 0x01;
+  while (!(LPC_SYSCON->MAINCLKUEN & 0x01));       /* Wait Until Updated       */
+
+  LPC_SYSCON->SYSAHBCLKDIV  = SYSAHBCLKDIV_Val;
+
+#if ((USBCLKDIV_Val & 0x1FF) != 0)                /* USB clock is used        */
+  LPC_SYSCON->PDRUNCFG     &= ~(1 << 10);         /* Power-up USB PHY         */
+
+#if ((USBCLKSEL_Val & 0x003) == 0)                /* USB clock is USB PLL out */
+  LPC_SYSCON->PDRUNCFG     &= ~(1 <<  8);         /* Power-up USB PLL         */
+  LPC_SYSCON->USBPLLCLKSEL  = USBPLLCLKSEL_Val;   /* Select PLL Input         */
+  LPC_SYSCON->USBPLLCLKUEN  = 0x01;               /* Update Clock Source      */
+  LPC_SYSCON->USBPLLCLKUEN  = 0x00;               /* Toggle Update Register   */
+  LPC_SYSCON->USBPLLCLKUEN  = 0x01;
+  while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01));     /* Wait Until Updated       */
+  LPC_SYSCON->USBPLLCTRL    = USBPLLCTRL_Val;
+  while (!(LPC_SYSCON->USBPLLSTAT   & 0x01));     /* Wait Until PLL Locked    */
+  LPC_SYSCON->USBCLKSEL     = 0x00;               /* Select USB PLL           */
+#endif
+
+  LPC_SYSCON->USBCLKSEL     = USBCLKSEL_Val;      /* Select USB Clock         */
+  LPC_SYSCON->USBCLKDIV     = USBCLKDIV_Val;      /* Set USB clock divider    */
+
+#else                                             /* USB clock is not used    */                        
+  LPC_SYSCON->PDRUNCFG     |=  (1 << 10);         /* Power-down USB PHY       */
+  LPC_SYSCON->PDRUNCFG     |=  (1 <<  8);         /* Power-down USB PLL       */
+#endif
+
+#endif
+
+  /* System clock to the IOCON needs to be enabled or
+  most of the I/O related peripherals won't work. */
+  LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/system_LPC11Uxx.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file     system_LPC11Uxx.h
+ * @brief    CMSIS Cortex-M0 Device Peripheral Access Layer Header File
+ *           for the NXP LPC11Uxx Device Series
+ * @version  V1.10
+ * @date     24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC11Uxx_H
+#define __SYSTEM_LPC11Uxx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC11Uxx_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/LPC13Uxx.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,776 @@
+
+/****************************************************************************************************//**
+ * @file     LPC13Uxx.h
+ *
+ * 
+ *
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ *           default LPC13Uxx Device Series
+ *
+ * @version  V0.1
+ * @date     18. Jan 2012
+ *
+ * @note     Generated with SFDGen V2.6 Build 4f  on Tuesday, 17.01.2012 13:39:52
+ *
+ *           from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
+ *           created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
+ *
+ *******************************************************************************************************/
+
+/** @addtogroup NXP
+  * @{
+  */
+
+/** @addtogroup LPC13Uxx
+  * @{
+  */
+
+#ifndef __LPC13UXX_H__
+#define __LPC13UXX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+
+#if defined ( __CC_ARM   )
+  #pragma anon_unions
+#endif
+
+ /* Interrupt Number Definition */
+
+typedef enum {
+// -------------------------  Cortex-M3 Processor Exceptions Numbers  -----------------------------
+  Reset_IRQn                        = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
+  NonMaskableInt_IRQn               = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
+  HardFault_IRQn                    = -13,  /*!<   3  Hard Fault, all classes of Fault */
+  MemoryManagement_IRQn             = -12,  /*!<   4  Memory Management, MPU mismatch, including Access Violation and No Match */
+  BusFault_IRQn                     = -11,  /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+  UsageFault_IRQn                   = -10,  /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+  SVCall_IRQn                       = -5,   /*!<  11  System Service Call via SVC instruction */
+  DebugMonitor_IRQn                 = -4,   /*!<  12  Debug Monitor                    */
+  PendSV_IRQn                       = -2,   /*!<  14  Pendable request for system service */
+  SysTick_IRQn                      = -1,   /*!<  15  System Tick Timer                */
+// ----------------------------  LPC13Uxx Specific Interrupt Numbers  --------------------------------
+  PIN_INT0_IRQn                     = 0,    /*!<   0  PIN_INT0                         */
+  PIN_INT1_IRQn                     = 1,    /*!<   1  PIN_INT1                         */
+  PIN_INT2_IRQn                     = 2,    /*!<   2  PIN_INT2                         */
+  PIN_INT3_IRQn                     = 3,    /*!<   3  PIN_INT3                         */
+  PIN_INT4_IRQn                     = 4,    /*!<   4  PIN_INT4                         */
+  PIN_INT5_IRQn                     = 5,    /*!<   5  PIN_INT5                         */
+  PIN_INT6_IRQn                     = 6,    /*!<   6  PIN_INT6                         */
+  PIN_INT7_IRQn                     = 7,    /*!<   7  PIN_INT7                         */
+  GINT0_IRQn                        = 8,    /*!<   8  GINT0                            */
+  GINT1_IRQn                        = 9,    /*!<   9  GINT1                            */
+  Reserved0_IRQn                    = 10,   /*!<  10  Reserved Interrupt               */
+  Reserved1_IRQn                    = 11,   /*!<  11  Reserved Interrupt               */
+  RIT_IRQn                          = 12,   /*!<  12  Repetitive Interrupt Timer       */
+  Reserved2_IRQn                    = 13,   /*!<  13  Reserved Interrupt               */
+  SSP1_IRQn                         = 14,   /*!<  14  SSP1                             */
+  I2C_IRQn                          = 15,   /*!<  15  I2C                              */
+  CT16B0_IRQn                       = 16,   /*!<  16  CT16B0                           */
+  CT16B1_IRQn                       = 17,   /*!<  17  CT16B1                           */
+  CT32B0_IRQn                       = 18,   /*!<  18  CT32B0                           */
+  CT32B1_IRQn                       = 19,   /*!<  19  CT32B1                           */
+  SSP0_IRQn                         = 20,   /*!<  20  SSP0                             */
+  USART_IRQn                        = 21,   /*!<  21  USART                            */
+  USB_IRQ_IRQn                      = 22,   /*!<  22  USB_IRQ                          */
+  USB_FIQ_IRQn                      = 23,   /*!<  23  USB_FIQ                          */
+  ADC_IRQn                          = 24,   /*!<  24  ADC                              */
+  WDT_IRQn                          = 25,   /*!<  25  WDT                              */
+  BOD_IRQn                          = 26,   /*!<  26  BOD                              */
+  FMC_IRQn                          = 27,   /*!<  27  FMC                              */
+  Reserved3_IRQn                    = 28,   /*!<  28  Reserved Interrupt               */
+  Reserved4_IRQn                    = 29,   /*!<  29  Reserved Interrupt               */
+  USBWAKEUP_IRQn                    = 30,   /*!<  30  USBWAKEUP                        */
+  Reserved5_IRQn                    = 31,   /*!<  31  Reserved Interrupt               */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
+
+#define __CM3_REV              0x0000       /*!< Cortex-M3 Core Revision               */
+#define __MPU_PRESENT             0         /*!< MPU present or not                    */
+#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include <core_cm3.h>                       /*!< Cortex-M3 processor and core peripherals */
+#include "system_LPC13Uxx.h"                /*!< LPC13Uxx System                          */
+
+/** @addtogroup Device_Peripheral_Registers
+  * @{
+  */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          I2C                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+
+typedef struct {                            /*!< (@ 0x40000000) I2C Structure          */
+  __IO uint32_t CONSET;                     /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+  __I  uint32_t STAT;                       /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
+  __IO uint32_t DAT;                        /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
+  __IO uint32_t ADR0;                       /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+  __IO uint32_t SCLH;                       /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
+  __IO uint32_t SCLL;                       /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
+  __O  uint32_t CONCLR;                     /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+  __IO uint32_t MMCTRL;                     /*!< (@ 0x4000001C) Monitor mode control register. */
+  union{
+  __IO uint32_t ADR[3];                     /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+  struct{
+  __IO uint32_t ADR1;
+  __IO uint32_t ADR2;
+  __IO uint32_t ADR3;
+  };
+  };
+  __I  uint32_t DATA_BUFFER;                /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
+  union{
+  __IO uint32_t MASK[4];                    /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
+  struct{
+  __IO uint32_t MASK0;
+  __IO uint32_t MASK1;
+  __IO uint32_t MASK2;
+  __IO uint32_t MASK3;
+  };
+  };
+} LPC_I2C_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         WWDT                                         -----
+// ------------------------------------------------------------------------------------------------
+
+
+typedef struct {                            /*!< (@ 0x40004000) WWDT Structure         */
+  __IO uint32_t MOD;                        /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+  __IO uint32_t TC;                         /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
+  __O  uint32_t FEED;                       /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
+  __I  uint32_t TV;                         /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
+  __IO uint32_t CLKSEL;                     /*!< (@ 0x40004010) Watchdog clock select register. */
+  __IO uint32_t WARNINT;                    /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
+  __IO uint32_t WINDOW;                     /*!< (@ 0x40004018) Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         USART                                        -----
+// ------------------------------------------------------------------------------------------------
+
+
+typedef struct {                            /*!< (@ 0x40008000) USART Structure        */
+  
+  union {
+    __IO uint32_t DLL;                      /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+    __O  uint32_t THR;                      /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
+    __I  uint32_t RBR;                      /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
+  };
+  
+  union {
+    __IO uint32_t IER;                      /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
+    __IO uint32_t DLM;                      /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+  };
+  
+  union {
+    __O  uint32_t FCR;                      /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
+    __I  uint32_t IIR;                      /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+  };
+  __IO uint32_t LCR;                        /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
+  __IO uint32_t MCR;                        /*!< (@ 0x40008010) Modem Control Register. */
+  __I  uint32_t LSR;                        /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+  __I  uint32_t MSR;                        /*!< (@ 0x40008018) Modem Status Register. */
+  __IO uint32_t SCR;                        /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
+  __IO uint32_t ACR;                        /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+  __IO uint32_t ICR;                        /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
+  __IO uint32_t FDR;                        /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+  __IO uint32_t OSR;                        /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
+  __IO uint32_t TER;                        /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
+  __I  uint32_t RESERVED0[3];
+  __IO uint32_t HDEN;                       /*!< (@ 0x40008040) Half duplex enable register. */
+  __I  uint32_t RESERVED1;
+  __IO uint32_t SCICTRL;                    /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
+  __IO uint32_t RS485CTRL;                  /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+  __IO uint32_t RS485ADRMATCH;              /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+  __IO uint32_t RS485DLY;                   /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
+  __IO uint32_t SYNCCTRL;                   /*!< (@ 0x40008058) Synchronous mode control register. */
+} LPC_USART_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        CT16B0                                        -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct {                            /*!< (@ 0x4000C000) LPC_CTxxBx_Type Structure       */
+  __IO uint32_t IR;                         /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+  __IO uint32_t TCR;                        /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+  __IO uint32_t TC;                         /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+  __IO uint32_t PR;                         /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+  __IO uint32_t PC;                         /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+  __IO uint32_t MCR;                        /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+  union {
+  __IO uint32_t MR[4];                      /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+  struct{
+  __IO uint32_t MR0;                        /*!< (@ 0x4000C018) Match Register. MR0 */
+  __IO uint32_t MR1;                        /*!< (@ 0x4000C01C) Match Register. MR1 */
+  __IO uint32_t MR2;                        /*!< (@ 0x4000C020) Match Register. MR2 */
+  __IO uint32_t MR3;                        /*!< (@ 0x4000C024) Match Register. MR3 */
+  };
+  };
+  __IO uint32_t CCR;                        /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+  union{
+  __I  uint32_t CR[4];                      /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
+    struct{
+  __I  uint32_t CR0;                        /*!< (@ 0x4000C02C) Capture Register. CR 0 */
+  __I  uint32_t CR1;                        /*!< (@ 0x4000C030) Capture Register. CR 1 */
+  __I  uint32_t CR2;                        /*!< (@ 0x4000C034) Capture Register. CR 2 */
+  __I  uint32_t CR3;                        /*!< (@ 0x4000C038) Capture Register. CR 3 */
+  };
+  };
+  __IO uint32_t EMR;                        /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins  */
+  __I  uint32_t RESERVED0[12];
+  __IO uint32_t CTCR;                       /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+  __IO uint32_t PWMC;                       /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
+} LPC_CTxxBx_Type;
+
+typedef struct {                            /*!< (@ 0x4000C000) CT16B0 Structure       */
+  __IO uint32_t IR;                         /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+  __IO uint32_t TCR;                        /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+  __IO uint32_t TC;                         /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+  __IO uint32_t PR;                         /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+  __IO uint32_t PC;                         /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+  __IO uint32_t MCR;                        /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+  union {
+  __IO uint32_t MR[4];                      /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+  struct{
+  __IO uint32_t MR0;                        /*!< (@ 0x4000C018) Match Register. MR0 */
+  __IO uint32_t MR1;                        /*!< (@ 0x4000C01C) Match Register. MR1 */
+  __IO uint32_t MR2;                        /*!< (@ 0x4000C020) Match Register. MR2 */
+  __IO uint32_t MR3;                        /*!< (@ 0x4000C024) Match Register. MR3 */
+  };
+  };
+  __IO uint32_t CCR;                        /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+  union{
+  __I  uint32_t CR[4];                      /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
+    struct{
+  __I  uint32_t CR0;			            /*!< (@ 0x4000C02C) Capture Register. CR 0 */
+  __I  uint32_t CR1;			            /*!< (@ 0x4000C030) Capture Register. CR 1 */
+  __I  uint32_t CR2;			            /*!< (@ 0x4000C034) Capture Register. CR 2 */
+  __I  uint32_t CR3;			            /*!< (@ 0x4000C038) Capture Register. CR 3 */
+  };
+  };
+  __IO uint32_t EMR;                        /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins  */
+  __I  uint32_t RESERVED0[12];
+  __IO uint32_t CTCR;                       /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+  __IO uint32_t PWMC;                       /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
+} LPC_CT16B0_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        CT16B1                                        -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct {                            /*!< (@ 0x40010000) CT16B1 Structure       */
+  __IO uint32_t IR;                         /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+  __IO uint32_t TCR;                        /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+  __IO uint32_t TC;                         /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+  __IO uint32_t PR;                         /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+  __IO uint32_t PC;                         /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+  __IO uint32_t MCR;                        /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+  union {
+  __IO uint32_t MR[4];                      /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+  struct{
+  __IO uint32_t MR0;                        /*!< (@ 0x40010018) Match Register. MR0 */
+  __IO uint32_t MR1;                        /*!< (@ 0x4001001C) Match Register. MR1 */
+  __IO uint32_t MR2;                        /*!< (@ 0x40010020) Match Register. MR2 */
+  __IO uint32_t MR3;                        /*!< (@ 0x40010024) Match Register. MR3 */
+  };
+  };
+  __IO uint32_t CCR;                        /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+  union{
+  __I  uint32_t CR[4];                      /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
+    struct{
+  __I  uint32_t CR0;			            /*!< (@ 0x4001002C) Capture Register. CR 0 */
+  __I  uint32_t CR1;			            /*!< (@ 0x40010030) Capture Register. CR 1 */
+  __I  uint32_t CR2;			            /*!< (@ 0x40010034) Capture Register. CR 2 */
+  __I  uint32_t CR3;			            /*!< (@ 0x40010038) Capture Register. CR 3 */
+  };
+  };
+  __IO uint32_t EMR;                        /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins  */
+  __I  uint32_t RESERVED0[12];
+  __IO uint32_t CTCR;                       /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+  __IO uint32_t PWMC;                       /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
+} LPC_CT16B1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        CT32B0                                        -----
+// ------------------------------------------------------------------------------------------------
+typedef struct {                            /*!< (@ 0x40014000) CT32B0 Structure       */
+  __IO uint32_t IR;                         /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+  __IO uint32_t TCR;                        /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+  __IO uint32_t TC;                         /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+  __IO uint32_t PR;                         /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+  __IO uint32_t PC;                         /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+  __IO uint32_t MCR;                        /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+  union {
+  __IO uint32_t MR[4];                      /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+  struct{
+  __IO uint32_t MR0;                        /*!< (@ 0x40014018) Match Register. MR0 */
+  __IO uint32_t MR1;                        /*!< (@ 0x4001401C) Match Register. MR1 */
+  __IO uint32_t MR2;                        /*!< (@ 0x40014020) Match Register. MR2 */
+  __IO uint32_t MR3;                        /*!< (@ 0x40014024) Match Register. MR3 */
+  };
+  };
+  __IO uint32_t CCR;                        /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+  union{
+  __I  uint32_t CR[4];                      /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
+    struct{
+  __I  uint32_t CR0;			            /*!< (@ 0x4001402C) Capture Register. CR 0 */
+  __I  uint32_t CR1;			            /*!< (@ 0x40014030) Capture Register. CR 1 */
+  __I  uint32_t CR2;			            /*!< (@ 0x40014034) Capture Register. CR 2 */
+  __I  uint32_t CR3;			            /*!< (@ 0x40014038) Capture Register. CR 3 */
+  };
+  };
+  __IO uint32_t EMR;                        /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
+  __I  uint32_t RESERVED0[12];
+  __IO uint32_t CTCR;                       /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+  __IO uint32_t PWMC;                       /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
+} LPC_CT32B0_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        CT32B1                                        -----
+// ------------------------------------------------------------------------------------------------
+typedef struct {                            /*!< (@ 0x40018000) CT32B1 Structure       */
+  __IO uint32_t IR;                         /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+  __IO uint32_t TCR;                        /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+  __IO uint32_t TC;                         /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+  __IO uint32_t PR;                         /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+  __IO uint32_t PC;                         /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+  __IO uint32_t MCR;                        /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+  union {
+  __IO uint32_t MR[4];                      /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+  struct{
+  __IO uint32_t MR0;                        /*!< (@ 0x40018018) Match Register. MR0 */
+  __IO uint32_t MR1;                        /*!< (@ 0x4001801C) Match Register. MR1 */
+  __IO uint32_t MR2;                        /*!< (@ 0x40018020) Match Register. MR2 */
+  __IO uint32_t MR3;                        /*!< (@ 0x40018024) Match Register. MR3 */
+  };
+  };
+  __IO uint32_t CCR;                        /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+  union{
+  __I  uint32_t CR[4];                      /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
+    struct{
+  __I  uint32_t CR0;			            /*!< (@ 0x4001802C) Capture Register. CR 0 */
+  __I  uint32_t CR1;			            /*!< (@ 0x40018030) Capture Register. CR 1 */
+  __I  uint32_t CR2;			            /*!< (@ 0x40018034) Capture Register. CR 2 */
+  __I  uint32_t CR3;			            /*!< (@ 0x40018038) Capture Register. CR 3 */
+  };
+  };
+  __IO uint32_t EMR;                        /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
+  __I  uint32_t RESERVED0[12];
+  __IO uint32_t CTCR;                       /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+  __IO uint32_t PWMC;                       /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
+} LPC_CT32B1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          ADC                                         -----
+// ------------------------------------------------------------------------------------------------
+typedef struct {                            /*!< (@ 0x4001C000) ADC Structure          */
+  __IO uint32_t CR;                         /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
+  __IO uint32_t GDR;                        /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+  __I  uint32_t RESERVED0[1];
+  __IO uint32_t INTEN;                      /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+  union{
+  __I  uint32_t DR[8];                      /*!< (@ 0x4001C010) A/D Channel Data Register*/
+    struct{
+  __I  uint32_t DR0;                      	/*!< (@ 0x4001C010) A/D Channel Data Register 0*/
+  __I  uint32_t DR1;                      	/*!< (@ 0x4001C014) A/D Channel Data Register 1*/
+  __I  uint32_t DR2;                      	/*!< (@ 0x4001C018) A/D Channel Data Register 2*/
+  __I  uint32_t DR3;                      	/*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
+  __I  uint32_t DR4;                      	/*!< (@ 0x4001C020) A/D Channel Data Register 4*/
+  __I  uint32_t DR5;                      	/*!< (@ 0x4001C024) A/D Channel Data Register 5*/
+  __I  uint32_t DR6;                      	/*!< (@ 0x4001C028) A/D Channel Data Register 6*/
+  __I  uint32_t DR7;                      	/*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
+  };
+  };
+  __I  uint32_t STAT;                       /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+} LPC_ADC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          PMU                                         -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct {                            /*!< (@ 0x40038000) PMU Structure          */
+  __IO uint32_t PCON;                       /*!< (@ 0x40038000) Power control register */
+  union{
+  __IO uint32_t GPREG[4];                   /*!< (@ 0x40038004) General purpose register 0 */
+  struct{
+  __IO uint32_t GPREG0;                   	/*!< (@ 0x40038004) General purpose register 0 */
+  __IO uint32_t GPREG1;                   	/*!< (@ 0x40038008) General purpose register 1 */
+  __IO uint32_t GPREG2;                   	/*!< (@ 0x4003800C) General purpose register 2 */
+  __IO uint32_t GPREG3;                   	/*!< (@ 0x40038010) General purpose register 3 */
+  };
+  };
+  __IO uint32_t GPREG4;                     /*!< (@ 0x40038014) General purpose register 4 */
+} LPC_PMU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                       FLASHCTRL                                      -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct {                            /*!< (@ 0x4003C000) FLASHCTRL Structure    */
+  __I  uint32_t RESERVED0[4];
+  __IO uint32_t FLASHCFG;                   /*!< (@ 0x4003C010) Flash memory access time configuration register */
+  __I  uint32_t RESERVED1[3];
+  __IO uint32_t FMSSTART;                   /*!< (@ 0x4003C020) Signature start address register */
+  __IO uint32_t FMSSTOP;                    /*!< (@ 0x4003C024) Signature stop-address register */
+  __I  uint32_t RESERVED2[1];
+  __I  uint32_t FMSW0;                      /*!< (@ 0x4003C02C) Word 0 [31:0]          */
+  __I  uint32_t FMSW1;                      /*!< (@ 0x4003C030) Word 1 [63:32]         */
+  __I  uint32_t FMSW2;                      /*!< (@ 0x4003C034) Word 2 [95:64]         */
+  __I  uint32_t FMSW3;                      /*!< (@ 0x4003C038) Word 3 [127:96]        */
+  __I  uint32_t RESERVED3[1001];
+  __I  uint32_t FMSTAT;                     /*!< (@ 0x4003CFE0) Signature generation status register */
+  __I  uint32_t RESERVED4[1];
+  __O  uint32_t FMSTATCLR;                  /*!< (@ 0x4003CFE8) Signature generation status clear register */
+} LPC_FLASHCTRL_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         SSP                                          -----
+// ------------------------------------------------------------------------------------------------
+typedef struct {                            /*!< (@ 0x40040000) SSP0 Structure         */
+  __IO uint32_t CR0;                        /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
+  __IO uint32_t CR1;                        /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
+  __IO uint32_t DR;                         /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+  __I  uint32_t SR;                         /*!< (@ 0x4004000C) Status Register        */
+  __IO uint32_t CPSR;                       /*!< (@ 0x40040010) Clock Prescale Register */
+  __IO uint32_t IMSC;                       /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
+  __I  uint32_t RIS;                        /*!< (@ 0x40040018) Raw Interrupt Status Register */
+  __I  uint32_t MIS;                        /*!< (@ 0x4004001C) Masked Interrupt Status Register */
+  __O  uint32_t ICR;                        /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
+} LPC_SSPx_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                         IOCON                                        -----
+// ------------------------------------------------------------------------------------------------
+typedef struct {                            /*!< (@ 0x40044000) IOCON Structure        */
+  __IO uint32_t RESET_PIO0_0;               /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
+  __IO uint32_t PIO0_1;                     /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
+  __IO uint32_t PIO0_2;                     /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
+  __IO uint32_t PIO0_3;                     /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
+  __IO uint32_t PIO0_4;                     /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
+  __IO uint32_t PIO0_5;                     /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
+  __IO uint32_t PIO0_6;                     /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
+  __IO uint32_t PIO0_7;                     /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
+  __IO uint32_t PIO0_8;                     /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
+  __IO uint32_t PIO0_9;                     /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
+  __IO uint32_t SWCLK_PIO0_10;              /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
+  __IO uint32_t TDI_PIO0_11;                /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
+  __IO uint32_t TMS_PIO0_12;                /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
+  __IO uint32_t TDO_PIO0_13;                /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
+  __IO uint32_t TRST_PIO0_14;               /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
+  __IO uint32_t SWDIO_PIO0_15;              /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
+  __IO uint32_t PIO0_16;                    /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
+  __IO uint32_t PIO0_17;                    /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
+  __IO uint32_t PIO0_18;                    /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
+  __IO uint32_t PIO0_19;                    /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
+  __IO uint32_t PIO0_20;                    /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
+  __IO uint32_t PIO0_21;                    /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
+  __IO uint32_t PIO0_22;                    /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
+  __IO uint32_t PIO0_23;                    /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
+  __IO uint32_t PIO1_0;                     /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
+  __IO uint32_t PIO1_1;                     /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
+  __IO uint32_t PIO1_2;                     /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
+  __IO uint32_t PIO1_3;                     /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
+  __IO uint32_t PIO1_4;                     /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
+  __IO uint32_t PIO1_5;                     /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
+  __IO uint32_t PIO1_6;                     /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
+  __IO uint32_t PIO1_7;                     /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
+  __IO uint32_t PIO1_8;                     /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
+  __IO uint32_t PIO1_9;                     /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
+  __IO uint32_t PIO1_10;                    /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
+  __IO uint32_t PIO1_11;                    /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
+  __IO uint32_t PIO1_12;                    /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
+  __IO uint32_t PIO1_13;                    /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
+  __IO uint32_t PIO1_14;                    /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
+  __IO uint32_t PIO1_15;                    /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
+  __IO uint32_t PIO1_16;                    /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
+  __IO uint32_t PIO1_17;                    /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
+  __IO uint32_t PIO1_18;                    /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
+  __IO uint32_t PIO1_19;                    /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
+  __IO uint32_t PIO1_20;                    /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
+  __IO uint32_t PIO1_21;                    /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
+  __IO uint32_t PIO1_22;                    /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
+  __IO uint32_t PIO1_23;                    /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
+  __IO uint32_t PIO1_24;                    /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
+  __IO uint32_t PIO1_25;                    /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
+  __IO uint32_t PIO1_26;                    /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
+  __IO uint32_t PIO1_27;                    /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
+  __IO uint32_t PIO1_28;                    /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
+  __IO uint32_t PIO1_29;                    /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
+  __IO uint32_t PIO1_30;                    /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
+  __IO uint32_t PIO1_31;                    /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
+} LPC_IOCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                        SYSCON                                        -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct {                            /*!< (@ 0x40048000) SYSCON Structure       */
+  __IO uint32_t SYSMEMREMAP;                /*!< (@ 0x40048000) System memory remap    */
+  __IO uint32_t PRESETCTRL;                 /*!< (@ 0x40048004) Peripheral reset control */
+  __IO uint32_t SYSPLLCTRL;                 /*!< (@ 0x40048008) System PLL control     */
+  __I  uint32_t SYSPLLSTAT;                 /*!< (@ 0x4004800C) System PLL status      */
+  __IO uint32_t USBPLLCTRL;                 /*!< (@ 0x40048010) USB PLL control        */
+  __I  uint32_t USBPLLSTAT;                 /*!< (@ 0x40048014) USB PLL status         */
+  __I  uint32_t RESERVED0[2];
+  __IO uint32_t SYSOSCCTRL;                 /*!< (@ 0x40048020) System oscillator control */
+  __IO uint32_t WDTOSCCTRL;                 /*!< (@ 0x40048024) Watchdog oscillator control */
+  __I  uint32_t RESERVED1[2];
+  __IO uint32_t SYSRSTSTAT;                 /*!< (@ 0x40048030) System reset status register */
+  __I  uint32_t RESERVED2[3];
+  __IO uint32_t SYSPLLCLKSEL;               /*!< (@ 0x40048040) System PLL clock source select */
+  __I  uint32_t RESERVED3;
+  __IO uint32_t USBPLLCLKSEL;               /*!< (@ 0x40048048) USB PLL clock source select */
+  __I  uint32_t RESERVED4[9];
+  __IO uint32_t MAINCLKSEL;                 /*!< (@ 0x40048070) Main clock source select */
+  __I  uint32_t RESERVED5;
+  __IO uint32_t SYSAHBCLKDIV;               /*!< (@ 0x40048078) System clock divider   */
+  __I  uint32_t RESERVED6;
+  __IO uint32_t SYSAHBCLKCTRL;              /*!< (@ 0x40048080) System clock control   */
+  __I  uint32_t RESERVED7[4];
+  __IO uint32_t SSP0CLKDIV;                 /*!< (@ 0x40048094) SSP0 clock divider     */
+  __IO uint32_t UARTCLKDIV;                 /*!< (@ 0x40048098) UART clock divider     */
+  __IO uint32_t SSP1CLKDIV;                 /*!< (@ 0x4004809C) SSP1 clock divider     */
+  __I  uint32_t RESERVED8[3];
+  __IO uint32_t TRACECLKDIV;                /*!< (@ 0x400480AC) ARM trace clock divider */
+  __IO uint32_t SYSTICKCLKDIV;              /*!< (@ 0x400480B0) SYSTICK clock divder   */
+  __I  uint32_t RESERVED9[3];
+  __IO uint32_t USBCLKSEL;                  /*!< (@ 0x400480C0) USB clock source select */
+  __I  uint32_t RESERVED10;
+  __IO uint32_t USBCLKDIV;                  /*!< (@ 0x400480C8) USB clock source divider */
+  __I  uint32_t RESERVED11[5];
+  __IO uint32_t CLKOUTSEL;                  /*!< (@ 0x400480E0) CLKOUT clock source select */
+  __I  uint32_t RESERVED12;
+  __IO uint32_t CLKOUTDIV;                  /*!< (@ 0x400480E8) CLKOUT clock divider   */
+  __I  uint32_t RESERVED13[5];
+  __I  uint32_t PIOPORCAP0;                 /*!< (@ 0x40048100) POR captured PIO status 0 */
+  __I  uint32_t PIOPORCAP1;                 /*!< (@ 0x40048104) POR captured PIO status 1 */
+  __I  uint32_t RESERVED14[18];
+  __IO uint32_t BODCTRL;                    /*!< (@ 0x40048150) Brown-Out Detect       */
+  __IO uint32_t SYSTCKCAL;                  /*!< (@ 0x40048154) System tick counter calibration */
+  __I  uint32_t RESERVED15[6];
+  __IO uint32_t IRQLATENCY;                 /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
+  __IO uint32_t NMISRC;                     /*!< (@ 0x40048174) NMI Source Control     */
+  __IO uint32_t PINSEL[8];                  /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
+  __IO uint32_t USBCLKCTRL;                 /*!< (@ 0x40048198) USB clock control      */
+  __I  uint32_t USBCLKST;                   /*!< (@ 0x4004819C) USB clock status       */
+  __I  uint32_t RESERVED16[25];
+  __IO uint32_t STARTERP0;                  /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
+  __I  uint32_t RESERVED17[3];
+  __IO uint32_t STARTERP1;                  /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
+  __I  uint32_t RESERVED18[6];
+  __IO uint32_t PDSLEEPCFG;                 /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
+  __IO uint32_t PDAWAKECFG;                 /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
+  __IO uint32_t PDRUNCFG;                   /*!< (@ 0x40048238) Power configuration register */
+  __I  uint32_t RESERVED19[111];
+  __I  uint32_t DEVICE_ID;                  /*!< (@ 0x400483F8) Device ID              */
+} LPC_SYSCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                     GPIO_PIN_INT                                     -----
+// ------------------------------------------------------------------------------------------------
+typedef struct {                            /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
+  __IO uint32_t ISEL;                       /*!< (@ 0x4004C000) Pin Interrupt Mode register */
+  __IO uint32_t IENR;                       /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
+  __O  uint32_t SIENR;                      /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
+  __O  uint32_t CIENR;                      /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
+  __IO uint32_t IENF;                       /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
+  __O  uint32_t SIENF;                      /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+  __O  uint32_t CIENF;                      /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+  __IO uint32_t RISE;                       /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
+  __IO uint32_t FALL;                       /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
+  __IO uint32_t IST;                        /*!< (@ 0x4004C024) Pin Interrupt Status register */
+} LPC_GPIO_PIN_INT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                    GPIO_GROUP_INT0                                   -----
+// ------------------------------------------------------------------------------------------------
+typedef struct {                            /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
+  __IO uint32_t CTRL;                       /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
+  __I  uint32_t RESERVED0[7];
+  __IO uint32_t PORT_POL[2];                /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
+  __I  uint32_t RESERVED1[6];
+  __IO uint32_t PORT_ENA[2];                /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
+} LPC_GPIO_GROUP_INT0_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                    GPIO_GROUP_INT1                                   -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct {                            /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
+  __IO uint32_t CTRL;                       /*!< (@ 0x40060000) GPIO grouped interrupt control register */
+  __I  uint32_t RESERVED0[7];
+  __IO uint32_t PORT_POL[2];                /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
+  __I  uint32_t RESERVED1[6];
+  __IO uint32_t PORT_ENA[2];                /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
+} LPC_GPIO_GROUP_INT1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                          Repetitive Interrupt Timer (RIT)                            -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct {                            /*!< (@ 0x40064000) RITIMER Structure */
+  __IO uint32_t COMPVAL;                    /*!< (@ 0x40064000) RITIMER compare register */
+  __IO uint32_t MASK;                       /*!< (@ 0x40064004) RITIMER mask register */
+  __IO uint32_t CTRL;                       /*!< (@ 0x40064008) RITIMER control register */
+  __IO uint32_t COUNTER;                    /*!< (@ 0x4006400C) RITIMER counter register */
+  __IO uint32_t COMPVAL_H;                  /*!< (@ 0x40064010) RITIMER compare upper register */
+  __IO uint32_t MASK_H;                     /*!< (@ 0x40064014) RITIMER mask upper register */
+  __I  uint32_t RESERVED0[1];
+  __IO uint32_t COUNTER_H;                  /*!< (@ 0x4006401C) RITIMER counter upper register */
+} LPC_RITIMER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                          USB                                         -----
+// ------------------------------------------------------------------------------------------------
+typedef struct {                            /*!< (@ 0x40020000) USB Structure          */
+  __IO uint32_t DEVCMDSTAT;                 /*!< (@ 0x40020000) USB Device Command/Status register */
+  __IO uint32_t INFO;                       /*!< (@ 0x40020004) USB Info register      */
+  __IO uint32_t EPLISTSTART;                /*!< (@ 0x40020008) USB EP Command/Status List start address */
+  __IO uint32_t DATABUFSTART;               /*!< (@ 0x4002000C) USB Data buffer start address */
+  __IO uint32_t LPM;                        /*!< (@ 0x40020010) Link Power Management register */
+  __IO uint32_t EPSKIP;                     /*!< (@ 0x40020014) USB Endpoint skip      */
+  __IO uint32_t EPINUSE;                    /*!< (@ 0x40020018) USB Endpoint Buffer in use */
+  __IO uint32_t EPBUFCFG;                   /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
+  __IO uint32_t INTSTAT;                    /*!< (@ 0x40020020) USB interrupt status register */
+  __IO uint32_t INTEN;                      /*!< (@ 0x40020024) USB interrupt enable register */
+  __IO uint32_t INTSETSTAT;                 /*!< (@ 0x40020028) USB set interrupt status register */
+  __IO uint32_t INTROUTING;                 /*!< (@ 0x4002002C) USB interrupt routing register */
+  __I  uint32_t RESERVED0[1];
+  __I  uint32_t EPTOGGLE;                   /*!< (@ 0x40020034) USB Endpoint toggle register */
+} LPC_USB_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                       GPIO_PORT                                      -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct {                            /*!< (@ 0x50000000) GPIO_PORT Structure    */
+  union {
+    struct {
+      __IO uint8_t B0[32];                  /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
+      __IO uint8_t B1[32];                  /*!< (@ 0x50000020) Byte pin registers port 1 */
+    };
+    __IO uint8_t B[64];                     /*!< (@ 0x50000000) Byte pin registers port 0/1 */
+  };
+  __I  uint32_t RESERVED0[1008];
+  union {
+    struct {
+      __IO uint32_t W0[32];                 /*!< (@ 0x50001000) Word pin registers port 0 */
+      __IO uint32_t W1[32];                 /*!< (@ 0x50001080) Word pin registers port 1 */
+    };
+    __IO uint32_t W[64];                    /*!< (@ 0x50001000) Word pin registers port 0/1 */
+  };
+  __I  uint32_t RESERVED1[960];
+  __IO uint32_t DIR[2];                     /*!< (@ 0x50002000) Direction registers port 0/1 */
+  __I  uint32_t RESERVED2[30];
+  __IO uint32_t MASK[2];                    /*!< (@ 0x50002080) Mask register port 0/1 */
+  __I  uint32_t RESERVED3[30];
+  __IO uint32_t PIN[2];                     /*!< (@ 0x50002100) Portpin register port 0 */
+  __I  uint32_t RESERVED4[30];
+  __IO uint32_t MPIN[2];                    /*!< (@ 0x50002180) Masked port register port 0/1 */
+  __I  uint32_t RESERVED5[30];
+  __IO uint32_t SET[2];                     /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
+  __I  uint32_t RESERVED6[30];
+  __O  uint32_t CLR[2];                     /*!< (@ 0x50002280) Clear port 0/1         */
+  __I  uint32_t RESERVED7[30];
+  __O  uint32_t NOT[2];                     /*!< (@ 0x50002300) Toggle port 0/1        */
+} LPC_GPIO_Type;
+
+
+#if defined ( __CC_ARM   )
+  #pragma no_anon_unions
+#endif
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                 Peripheral memory map                                -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C_BASE              (0x40000000)
+#define LPC_WWDT_BASE             (0x40004000)
+#define LPC_USART_BASE            (0x40008000)
+#define LPC_CT16B0_BASE           (0x4000C000)
+#define LPC_CT16B1_BASE           (0x40010000)
+#define LPC_CT32B0_BASE           (0x40014000)
+#define LPC_CT32B1_BASE           (0x40018000)
+#define LPC_ADC_BASE              (0x4001C000)
+#define LPC_PMU_BASE              (0x40038000)
+#define LPC_FLASHCTRL_BASE        (0x4003C000)
+#define LPC_SSP0_BASE             (0x40040000)
+#define LPC_IOCON_BASE            (0x40044000)
+#define LPC_SYSCON_BASE           (0x40048000)
+#define LPC_GPIO_PIN_INT_BASE     (0x4004C000)
+#define LPC_SSP1_BASE             (0x40058000)
+#define LPC_GPIO_GROUP_INT0_BASE  (0x4005C000)
+#define LPC_GPIO_GROUP_INT1_BASE  (0x40060000)
+#define LPC_RITIMER_BASE          (0x40064000)
+#define LPC_USB_BASE              (0x40080000)
+#define LPC_GPIO_BASE             (0x50000000)
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                Peripheral declaration                                -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C                   ((LPC_I2C_Type            *) LPC_I2C_BASE)
+#define LPC_WWDT                  ((LPC_WWDT_Type           *) LPC_WWDT_BASE)
+#define LPC_USART                 ((LPC_USART_Type          *) LPC_USART_BASE)
+#define LPC_CT16B0                ((LPC_CTxxBx_Type         *) LPC_CT16B0_BASE)
+#define LPC_CT16B1                ((LPC_CTxxBx_Type         *) LPC_CT16B1_BASE)
+#define LPC_CT32B0                ((LPC_CTxxBx_Type         *) LPC_CT32B0_BASE)
+#define LPC_CT32B1                ((LPC_CTxxBx_Type         *) LPC_CT32B1_BASE)
+#define LPC_ADC                   ((LPC_ADC_Type            *) LPC_ADC_BASE)
+#define LPC_PMU                   ((LPC_PMU_Type            *) LPC_PMU_BASE)
+#define LPC_FLASHCTRL             ((LPC_FLASHCTRL_Type      *) LPC_FLASHCTRL_BASE)
+#define LPC_SSP0                  ((LPC_SSPx_Type           *) LPC_SSP0_BASE)
+#define LPC_SSP1                  ((LPC_SSPx_Type           *) LPC_SSP1_BASE)
+#define LPC_IOCON                 ((LPC_IOCON_Type          *) LPC_IOCON_BASE)
+#define LPC_SYSCON                ((LPC_SYSCON_Type         *) LPC_SYSCON_BASE)
+#define LPC_GPIO_PIN_INT          ((LPC_GPIO_PIN_INT_Type   *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0       ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1       ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_RITIMER               ((LPC_RITIMER_Type        *) LPC_RITIMER_BASE)
+#define LPC_USB                   ((LPC_USB_Type            *) LPC_USB_BASE)
+#define LPC_GPIO                  ((LPC_GPIO_Type           *) LPC_GPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group (null) */
+/** @} */ /* End of group h1usf */
+
+#ifdef __cplusplus
+}
+#endif 
+
+
+#endif  // __LPC13UXX_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/LPC1347.sct	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,19 @@
+
+LR_IROM1 0x00000000 0x10000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x10000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
+  ; 8KB - 0xC0 = 0x1F40
+  RW_IRAM1 0x100000C0 0x1F40  {
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x20000000 0x800  {  ; RW data
+   .ANY (AHBSRAM0)
+  }
+  RW_IRAM3 0x20004000 0x800  {  ; RW data, USB RAM
+   .ANY (AHBSRAM1)
+  }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/startup_LPC13xx.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,231 @@
+;/*****************************************************************************
+; * @file:    startup_LPC13xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File 
+; *           for the NXP LPC13xx Device Series 
+; * @version: V1.02, modified for mbed
+; * @date:    27. July 2009, modified 3rd Aug 2009
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+Stack_Mem       SPACE   Stack_Size
+__initial_sp    EQU     0x10002000  ; Top of RAM from LPC1347
+
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+
+                DCD    PIN_INT0_Handler      ; All GPIO pin can be routed to PIN_INTx
+                DCD    PIN_INT1_Handler
+                DCD    PIN_INT2_Handler
+                DCD    PIN_INT3_Handler
+                DCD    PIN_INT4_Handler
+                DCD    PIN_INT5_Handler
+                DCD    PIN_INT6_Handler
+                DCD    PIN_INT7_Handler
+                DCD    GINT0_Handler
+                DCD    GINT1_Handler         ; PIO0 (0:7) 
+                DCD    0
+                DCD    0
+                DCD    OSTIMER_Handler
+                DCD    0
+                DCD    SSP1_Handler          ; SSP1 
+                DCD    I2C_Handler           ; I2C 
+                DCD    CT16B0_Handler        ; 16-bit Timer0 
+                DCD    CT16B1_Handler        ; 16-bit Timer1 
+                DCD    CT32B0_Handler        ; 32-bit Timer0 
+                DCD    CT32B1_Handler        ; 32-bit Timer1 
+                DCD    SSP0_Handler          ; SSP0 
+                DCD    USART_Handler         ; USART 
+                DCD    USB_Handler           ; USB IRQ 
+                DCD    USB_FIQHandler        ; USB FIQ 
+                DCD    ADC_Handler           ; A/D Converter 
+                DCD    WDT_Handler           ; Watchdog timer 
+                DCD    BOD_Handler           ; Brown Out Detect 
+                DCD    FMC_Handler           ; IP2111 Flash Memory Controller 
+                DCD    OSCFAIL_Handler       ; OSC FAIL 
+                DCD    PVTCIRCUIT_Handler    ; PVT CIRCUIT 
+                DCD    USBWakeup_Handler     ; USB wake up 
+                DCD    0
+
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  PIN_INT0_Handler          [WEAK]
+                EXPORT  PIN_INT1_Handler          [WEAK]
+                EXPORT  PIN_INT2_Handler          [WEAK]
+                EXPORT  PIN_INT3_Handler          [WEAK]
+                EXPORT  PIN_INT4_Handler          [WEAK]
+                EXPORT  PIN_INT5_Handler          [WEAK]
+                EXPORT  PIN_INT6_Handler          [WEAK]
+                EXPORT  PIN_INT7_Handler          [WEAK]
+                EXPORT  GINT0_Handler             [WEAK]
+                EXPORT  GINT1_Handler             [WEAK]
+                EXPORT  OSTIMER_Handler           [WEAK]
+                EXPORT  SSP1_Handler              [WEAK]
+                EXPORT  I2C_Handler               [WEAK]
+                EXPORT  CT16B0_Handler            [WEAK]
+                EXPORT  CT16B1_Handler            [WEAK]
+                EXPORT  CT32B0_Handler            [WEAK]
+                EXPORT  CT32B1_Handler            [WEAK]
+                EXPORT  SSP0_Handler              [WEAK]
+                EXPORT  USART_Handler             [WEAK]
+                EXPORT  USB_Handler               [WEAK]
+                EXPORT  USB_FIQHandler            [WEAK]
+                EXPORT  ADC_Handler               [WEAK]
+                EXPORT  WDT_Handler               [WEAK]
+                EXPORT  BOD_Handler               [WEAK]
+                EXPORT  FMC_Handler               [WEAK]
+                EXPORT  OSCFAIL_Handler           [WEAK]
+                EXPORT  PVTCIRCUIT_Handler        [WEAK]
+                EXPORT  USBWakeup_Handler         [WEAK]
+  
+PIN_INT0_Handler
+PIN_INT1_Handler
+PIN_INT2_Handler
+PIN_INT3_Handler
+PIN_INT4_Handler
+PIN_INT5_Handler
+PIN_INT6_Handler
+PIN_INT7_Handler
+GINT0_Handler
+GINT1_Handler
+OSTIMER_Handler
+SSP1_Handler
+I2C_Handler
+CT16B0_Handler
+CT16B1_Handler
+CT32B0_Handler
+CT32B1_Handler
+SSP0_Handler
+USART_Handler
+USB_Handler
+USB_FIQHandler
+ADC_Handler
+WDT_Handler
+BOD_Handler
+FMC_Handler
+OSCFAIL_Handler
+PVTCIRCUIT_Handler
+USBWakeup_Handler
+
+                B       .
+
+                ENDP
+                
+                ALIGN
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_MICRO/sys.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/LPC1347.sct	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,19 @@
+
+LR_IROM1 0x00000000 0x10000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x10000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
+  ; 8KB - 0xC0 = 0x1F40
+  RW_IRAM1 0x100000C0 0x1F40  {
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x20000000 0x800  {  ; RW data
+   .ANY (AHBSRAM0)
+  }
+  RW_IRAM3 0x20004000 0x800  {  ; RW data, USB RAM
+   .ANY (AHBSRAM1)
+  }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/startup_LPC13xx.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,215 @@
+;/*****************************************************************************
+; * @file:    startup_LPC13xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File 
+; *           for the NXP LPC13xx Device Series 
+; * @version: V1.02, modified for mbed
+; * @date:    27. July 2009, modified 3rd Aug 2009
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp        EQU     0x10002000  ; Top of RAM from LPC1347
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+
+                DCD    PIN_INT0_Handler      ; All GPIO pin can be routed to PIN_INTx
+                DCD    PIN_INT1_Handler
+                DCD    PIN_INT2_Handler
+                DCD    PIN_INT3_Handler
+                DCD    PIN_INT4_Handler
+                DCD    PIN_INT5_Handler
+                DCD    PIN_INT6_Handler
+                DCD    PIN_INT7_Handler
+                DCD    GINT0_Handler
+                DCD    GINT1_Handler         ; PIO0 (0:7) 
+                DCD    0
+                DCD    0
+                DCD    OSTIMER_Handler
+                DCD    0
+                DCD    SSP1_Handler          ; SSP1 
+                DCD    I2C_Handler           ; I2C 
+                DCD    CT16B0_Handler        ; 16-bit Timer0 
+                DCD    CT16B1_Handler        ; 16-bit Timer1 
+                DCD    CT32B0_Handler        ; 32-bit Timer0 
+                DCD    CT32B1_Handler        ; 32-bit Timer1 
+                DCD    SSP0_Handler          ; SSP0 
+                DCD    USART_Handler         ; USART 
+                DCD    USB_Handler           ; USB IRQ 
+                DCD    USB_FIQHandler        ; USB FIQ 
+                DCD    ADC_Handler           ; A/D Converter 
+                DCD    WDT_Handler           ; Watchdog timer 
+                DCD    BOD_Handler           ; Brown Out Detect 
+                DCD    FMC_Handler           ; IP2111 Flash Memory Controller 
+                DCD    OSCFAIL_Handler       ; OSC FAIL 
+                DCD    PVTCIRCUIT_Handler    ; PVT CIRCUIT 
+                DCD    USBWakeup_Handler     ; USB wake up 
+                DCD    0
+
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  PIN_INT0_Handler          [WEAK]
+                EXPORT  PIN_INT1_Handler          [WEAK]
+                EXPORT  PIN_INT2_Handler          [WEAK]
+                EXPORT  PIN_INT3_Handler          [WEAK]
+                EXPORT  PIN_INT4_Handler          [WEAK]
+                EXPORT  PIN_INT5_Handler          [WEAK]
+                EXPORT  PIN_INT6_Handler          [WEAK]
+                EXPORT  PIN_INT7_Handler          [WEAK]
+                EXPORT  GINT0_Handler             [WEAK]
+                EXPORT  GINT1_Handler             [WEAK]
+                EXPORT  OSTIMER_Handler           [WEAK]
+                EXPORT  SSP1_Handler              [WEAK]
+                EXPORT  I2C_Handler               [WEAK]
+                EXPORT  CT16B0_Handler            [WEAK]
+                EXPORT  CT16B1_Handler            [WEAK]
+                EXPORT  CT32B0_Handler            [WEAK]
+                EXPORT  CT32B1_Handler            [WEAK]
+                EXPORT  SSP0_Handler              [WEAK]
+                EXPORT  USART_Handler             [WEAK]
+                EXPORT  USB_Handler               [WEAK]
+                EXPORT  USB_FIQHandler            [WEAK]
+                EXPORT  ADC_Handler               [WEAK]
+                EXPORT  WDT_Handler               [WEAK]
+                EXPORT  BOD_Handler               [WEAK]
+                EXPORT  FMC_Handler               [WEAK]
+                EXPORT  OSCFAIL_Handler           [WEAK]
+                EXPORT  PVTCIRCUIT_Handler        [WEAK]
+                EXPORT  USBWakeup_Handler         [WEAK]
+  
+PIN_INT0_Handler
+PIN_INT1_Handler
+PIN_INT2_Handler
+PIN_INT3_Handler
+PIN_INT4_Handler
+PIN_INT5_Handler
+PIN_INT6_Handler
+PIN_INT7_Handler
+GINT0_Handler
+GINT1_Handler
+OSTIMER_Handler
+SSP1_Handler
+I2C_Handler
+CT16B0_Handler
+CT16B1_Handler
+CT32B0_Handler
+CT32B1_Handler
+SSP0_Handler
+USART_Handler
+USB_Handler
+USB_FIQHandler
+ADC_Handler
+WDT_Handler
+BOD_Handler
+FMC_Handler
+OSCFAIL_Handler
+PVTCIRCUIT_Handler
+USBWakeup_Handler
+
+                B       .
+
+                ENDP
+                
+                ALIGN
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_ARM_STD/sys.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_GCC_ARM/LPC1347.ld	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,149 @@
+/* Linker script for mbed LPC1347 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
+  RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+
+  RAM1(rwx) : ORIGIN = 0x20000000, LENGTH = 2K
+  USB_RAM(rwx) : ORIGIN = 0x20004000, LENGTH = 2K
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+        
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM
+    
+    .heap :
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy :
+    {
+        *(.stack)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+    
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/TOOLCHAIN_GCC_ARM/startup_LPC13xx.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,209 @@
+/* File: startup_ARMCM3.s
+ * Purpose: startup file for Cortex-M3/M4 devices. Should use with 
+ *   GNU Tools for ARM Embedded Processors
+ * Version: V1.1
+ * Date: 17 June 2011
+ * 
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ */
+    .syntax unified
+    .arch armv7-m
+
+/* Memory Model
+   The HEAP starts at the end of the DATA section and grows upward.
+   
+   The STACK starts at the end of the RAM and grows downward.
+   
+   The HEAP and stack STACK are only checked at compile time:
+   (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+   
+   This is just a check for the bare minimum for the Heap+Stack area before
+   aborting compilation, it is not the run time limit:
+   Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0xc00
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x800
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+    
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    NMI_Handler           /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    MemManage_Handler     /* MPU Fault Handler */
+    .long    BusFault_Handler      /* Bus Fault Handler */
+    .long    UsageFault_Handler    /* Usage Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    DebugMon_Handler      /* Debug Monitor Handler */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+
+    .long    PIN_INT0_Handler      /* All GPIO pin can be routed to PIN_INTx */
+    .long    PIN_INT1_Handler
+    .long    PIN_INT2_Handler
+    .long    PIN_INT3_Handler
+    .long    PIN_INT4_Handler
+    .long    PIN_INT5_Handler
+    .long    PIN_INT6_Handler
+    .long    PIN_INT7_Handler
+    .long    GINT0_Handler
+    .long    GINT1_Handler         /* PIO0 (0:7) */
+    .long    0
+    .long    0
+    .long    OSTIMER_Handler
+    .long    0
+    .long    SSP1_Handler          /* SSP1 */
+    .long    I2C_Handler           /* I2C */
+    .long    CT16B0_Handler        /* 16-bit Timer0 */
+    .long    CT16B1_Handler        /* 16-bit Timer1 */
+    .long    CT32B0_Handler        /* 32-bit Timer0 */
+    .long    CT32B1_Handler        /* 32-bit Timer1 */
+    .long    SSP0_Handler          /* SSP0 */
+    .long    USART_Handler         /* USART */
+    .long    USB_Handler           /* USB IRQ */
+    .long    USB_FIQHandler        /* USB FIQ */
+    .long    ADC_Handler           /* A/D Converter */
+    .long    WDT_Handler           /* Watchdog timer */
+    .long    BOD_Handler           /* Brown Out Detect */
+    .long    FMC_Handler           /* IP2111 Flash Memory Controller */
+    .long    OSCFAIL_Handler       /* OSC FAIL */
+    .long    PVTCIRCUIT_Handler    /* PVT CIRCUIT */
+    .long    USBWakeup_Handler     /* USB wake up */
+    .long    0
+
+    .size    __isr_vector, . - __isr_vector
+
+    .text
+    .thumb
+    .thumb_func
+    .align 2
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in 
+ *      linker script.
+ *      _etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+.flash_to_ram_loop:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .flash_to_ram_loop
+
+    ldr    r0, =SystemInit
+    blx    r0
+    ldr    r0, =_start
+    bx    r0
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+    
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_default_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+    
+    def_default_handler    NMI_Handler
+    def_default_handler    HardFault_Handler
+    def_default_handler    MemManage_Handler
+    def_default_handler    BusFault_Handler
+    def_default_handler    UsageFault_Handler
+    def_default_handler    SVC_Handler
+    def_default_handler    DebugMon_Handler
+    def_default_handler    PendSV_Handler
+    def_default_handler    SysTick_Handler
+    def_default_handler    Default_Handler
+
+    def_default_handler    PIN_INT0_Handler
+    def_default_handler    PIN_INT1_Handler
+    def_default_handler    PIN_INT2_Handler
+    def_default_handler    PIN_INT3_Handler
+    def_default_handler    PIN_INT4_Handler
+    def_default_handler    PIN_INT5_Handler
+    def_default_handler    PIN_INT6_Handler
+    def_default_handler    PIN_INT7_Handler
+    def_default_handler    GINT0_Handler
+    def_default_handler    GINT1_Handler
+    def_default_handler    OSTIMER_Handler
+    def_default_handler    SSP1_Handler
+    def_default_handler    I2C_Handler
+    def_default_handler    CT16B0_Handler
+    def_default_handler    CT16B1_Handler
+    def_default_handler    CT32B0_Handler
+    def_default_handler    CT32B1_Handler
+    def_default_handler    SSP0_Handler
+    def_default_handler    USART_Handler
+    def_default_handler    USB_Handler
+    def_default_handler    USB_FIQHandler
+    def_default_handler    ADC_Handler
+    def_default_handler    WDT_Handler
+    def_default_handler    BOD_Handler
+    def_default_handler    FMC_Handler
+    def_default_handler    OSCFAIL_Handler
+    def_default_handler    PVTCIRCUIT_Handler
+    def_default_handler    USBWakeup_Handler
+
+    .weak    DEF_IRQHandler
+    .set    DEF_IRQHandler, Default_Handler
+
+    .end
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * A generic CMSIS include header, pulling in LPC13XX specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC13Uxx.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,32 @@
+/* mbed Microcontroller Library - cmsis_nvic for LCP1768
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+#include "cmsis_nvic.h"
+
+#define NVIC_NUM_VECTORS          (16 + 32)     // CORE + MCU Peripherals
+#define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0)       // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + 16];
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/cmsis_nvic.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,23 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/system_LPC13Uxx.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,437 @@
+/******************************************************************************
+ * @file     system_LPC13Uxx.c
+ * @purpose  CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+ *           for the NXP LPC13xx Device Series
+ * @version  V1.10
+ * @date     24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC13Uxx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+//   <h> System Oscillator Control Register (SYSOSCCTRL)
+//     <o1.0>      BYPASS: System Oscillator Bypass Enable
+//                     <i> If enabled then PLL input (sys_osc_clk) is fed
+//                     <i> directly from XTALIN and XTALOUT pins.
+//     <o1.9>      FREQRANGE: System Oscillator Frequency Range
+//                     <i> Determines frequency range for Low-power oscillator.
+//                   <0=> 1 - 20 MHz
+//                   <1=> 15 - 25 MHz
+//   </h>
+//
+//   <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+//     <o2.0..4>   DIVSEL: Select Divider for Fclkana
+//                     <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
+//                   <0-31>
+//     <o2.5..8>   FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+//                   <0=> Undefined
+//                   <1=> 0.5 MHz
+//                   <2=> 0.8 MHz
+//                   <3=> 1.1 MHz
+//                   <4=> 1.4 MHz
+//                   <5=> 1.6 MHz
+//                   <6=> 1.8 MHz
+//                   <7=> 2.0 MHz
+//                   <8=> 2.2 MHz
+//                   <9=> 2.4 MHz
+//                   <10=> 2.6 MHz
+//                   <11=> 2.7 MHz
+//                   <12=> 2.9 MHz
+//                   <13=> 3.1 MHz
+//                   <14=> 3.2 MHz
+//                   <15=> 3.4 MHz
+//   </h>
+//
+//   <h> System PLL Control Register (SYSPLLCTRL)
+//                   <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+//                   <i> F_clkin must be in the range of  10 MHz to  25 MHz
+//                   <i> F_CCO   must be in the range of 156 MHz to 320 MHz
+//     <o3.0..4>   MSEL: Feedback Divider Selection
+//                     <i> M = MSEL + 1
+//                   <0-31>
+//     <o3.5..6>   PSEL: Post Divider Selection
+//                   <0=> P = 1
+//                   <1=> P = 2
+//                   <2=> P = 4
+//                   <3=> P = 8
+//   </h>
+//
+//   <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+//     <o4.0..1>   SEL: System PLL Clock Source
+//                   <0=> IRC Oscillator
+//                   <1=> System Oscillator
+//                   <2=> Reserved
+//                   <3=> Reserved
+//   </h>
+//
+//   <h> Main Clock Source Select Register (MAINCLKSEL)
+//     <o5.0..1>   SEL: Clock Source for Main Clock
+//                   <0=> IRC Oscillator
+//                   <1=> Input Clock to System PLL
+//                   <2=> WDT Oscillator
+//                   <3=> System PLL Clock Out
+//   </h>
+//
+//   <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+//     <o6.0..7>   DIV: System AHB Clock Divider
+//                     <i> Divides main clock to provide system clock to core, memories, and peripherals.
+//                     <i> 0 = is disabled
+//                   <0-255>
+//   </h>
+//
+//   <h> USB PLL Control Register (USBPLLCTRL)
+//                   <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+//                   <i> F_clkin must be in the range of  10 MHz to  25 MHz
+//                   <i> F_CCO   must be in the range of 156 MHz to 320 MHz
+//     <o7.0..4>   MSEL: Feedback Divider Selection
+//                     <i> M = MSEL + 1
+//                   <0-31>
+//     <o7.5..6>   PSEL: Post Divider Selection
+//                   <0=> P = 1
+//                   <1=> P = 2
+//                   <2=> P = 4
+//                   <3=> P = 8
+//   </h>
+//
+//   <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
+//     <o8.0..1>   SEL: USB PLL Clock Source
+//                     <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
+//                   <0=> IRC Oscillator
+//                   <1=> System Oscillator
+//                   <2=> Reserved
+//                   <3=> Reserved
+//   </h>
+//
+//   <h> USB Clock Source Select Register (USBCLKSEL)
+//     <o9.0..1>   SEL: System PLL Clock Source
+//                   <0=> USB PLL out
+//                   <1=> Main clock
+//                   <2=> Reserved
+//                   <3=> Reserved
+//   </h>
+//
+//   <h> USB Clock Divider Register (USBCLKDIV)
+//     <o10.0..7>  DIV: USB Clock Divider
+//                     <i> Divides USB clock to 48 MHz.
+//                     <i> 0 = is disabled
+//                   <0-255>
+//   </h>
+// </e>
+*/
+#define CLOCK_SETUP           1
+#define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
+#define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
+#define SYSPLLCTRL_Val        0x00000025              // Reset: 0x000
+#define SYSPLLCLKSEL_Val      0x00000001              // Reset: 0x000
+#define MAINCLKSEL_Val        0x00000003              // Reset: 0x000
+#define SYSAHBCLKDIV_Val      0x00000001              // Reset: 0x001
+#define USBPLLCTRL_Val        0x00000023              // Reset: 0x000
+#define USBPLLCLKSEL_Val      0x00000001              // Reset: 0x000
+#define USBCLKSEL_Val         0x00000000              // Reset: 0x000
+#define USBCLKDIV_Val         0x00000001              // Reset: 0x001
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+  Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask)                     (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val),  ~0x00000003))
+   #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val),  ~0x000001FF))
+   #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
+   #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val),  ~0x000001FF))
+   #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val),  ~0x00000003))
+   #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+   #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
+   #error "USBPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((USBPLLCTRL_Val),  ~0x000001FF))
+   #error "USBPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
+   #error "USBCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
+   #error "USBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+    
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+#define __SYS_OSC_CLK     (    __XTAL)    /* Main oscillator frequency        */
+#define __IRC_OSC_CLK     (12000000UL)    /* Internal RC oscillator frequency */
+
+
+#define __FREQSEL   ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL   (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP)                         /* Clock Setup              */
+  #if  (__FREQSEL ==  0)
+    #define __WDT_OSC_CLK        ( 0)                  /* undefined */
+  #elif (__FREQSEL ==  1)
+    #define __WDT_OSC_CLK        ( 500000 / __DIVSEL)
+  #elif (__FREQSEL ==  2)
+    #define __WDT_OSC_CLK        ( 800000 / __DIVSEL)
+  #elif (__FREQSEL ==  3)
+    #define __WDT_OSC_CLK        (1100000 / __DIVSEL)
+  #elif (__FREQSEL ==  4)
+    #define __WDT_OSC_CLK        (1400000 / __DIVSEL)
+  #elif (__FREQSEL ==  5)
+    #define __WDT_OSC_CLK        (1600000 / __DIVSEL)
+  #elif (__FREQSEL ==  6)
+    #define __WDT_OSC_CLK        (1800000 / __DIVSEL)
+  #elif (__FREQSEL ==  7)
+    #define __WDT_OSC_CLK        (2000000 / __DIVSEL)
+  #elif (__FREQSEL ==  8)
+    #define __WDT_OSC_CLK        (2200000 / __DIVSEL)
+  #elif (__FREQSEL ==  9)
+    #define __WDT_OSC_CLK        (2400000 / __DIVSEL)
+  #elif (__FREQSEL == 10)
+    #define __WDT_OSC_CLK        (2600000 / __DIVSEL)
+  #elif (__FREQSEL == 11)
+    #define __WDT_OSC_CLK        (2700000 / __DIVSEL)
+  #elif (__FREQSEL == 12)
+    #define __WDT_OSC_CLK        (2900000 / __DIVSEL)
+  #elif (__FREQSEL == 13)
+    #define __WDT_OSC_CLK        (3100000 / __DIVSEL)
+  #elif (__FREQSEL == 14)
+    #define __WDT_OSC_CLK        (3200000 / __DIVSEL)
+  #else
+    #define __WDT_OSC_CLK        (3400000 / __DIVSEL)
+  #endif
+
+  /* sys_pllclkin calculation */
+  #if   ((SYSPLLCLKSEL_Val & 0x03) == 0)
+    #define __SYS_PLLCLKIN           (__IRC_OSC_CLK)
+  #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+    #define __SYS_PLLCLKIN           (__SYS_OSC_CLK)
+  #else
+    #define __SYS_PLLCLKIN           (0)
+  #endif
+
+  #define  __SYS_PLLCLKOUT         (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+  /* main clock calculation */
+  #if   ((MAINCLKSEL_Val & 0x03) == 0)
+    #define __MAIN_CLOCK             (__IRC_OSC_CLK)
+  #elif ((MAINCLKSEL_Val & 0x03) == 1)
+    #define __MAIN_CLOCK             (__SYS_PLLCLKIN)
+  #elif ((MAINCLKSEL_Val & 0x03) == 2)
+    #if (__FREQSEL ==  0)
+      #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+    #else
+      #define __MAIN_CLOCK           (__WDT_OSC_CLK)
+    #endif
+  #elif ((MAINCLKSEL_Val & 0x03) == 3)
+    #define __MAIN_CLOCK             (__SYS_PLLCLKOUT)
+  #else
+    #define __MAIN_CLOCK             (0)
+  #endif
+
+  #define __SYSTEM_CLOCK             (__MAIN_CLOCK / SYSAHBCLKDIV_Val)         
+
+#else
+  #define __SYSTEM_CLOCK             (__IRC_OSC_CLK)
+#endif  // CLOCK_SETUP 
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  uint32_t wdt_osc = 0;
+
+  /* Determine clock frequency according to clock register values             */
+  switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+    case 0:  wdt_osc =       0; break;
+    case 1:  wdt_osc =  500000; break;
+    case 2:  wdt_osc =  800000; break;
+    case 3:  wdt_osc = 1100000; break;
+    case 4:  wdt_osc = 1400000; break;
+    case 5:  wdt_osc = 1600000; break;
+    case 6:  wdt_osc = 1800000; break;
+    case 7:  wdt_osc = 2000000; break;
+    case 8:  wdt_osc = 2200000; break;
+    case 9:  wdt_osc = 2400000; break;
+    case 10: wdt_osc = 2600000; break;
+    case 11: wdt_osc = 2700000; break;
+    case 12: wdt_osc = 2900000; break;
+    case 13: wdt_osc = 3100000; break;
+    case 14: wdt_osc = 3200000; break;
+    case 15: wdt_osc = 3400000; break;
+  }
+  wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+ 
+  switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+    case 0:                             /* Internal RC oscillator             */
+      SystemCoreClock = __IRC_OSC_CLK;
+      break;
+    case 1:                             /* Input Clock to System PLL          */
+      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+          case 0:                       /* Internal RC oscillator             */
+            SystemCoreClock = __IRC_OSC_CLK;
+            break;
+          case 1:                       /* System oscillator                  */
+            SystemCoreClock = __SYS_OSC_CLK;
+            break;
+          case 2:                       /* Reserved                           */
+          case 3:                       /* Reserved                           */
+            SystemCoreClock = 0;
+            break;
+      }
+      break;
+    case 2:                             /* WDT Oscillator                     */
+      SystemCoreClock = wdt_osc;
+      break;
+    case 3:                             /* System PLL Clock Out               */
+      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+          case 0:                       /* Internal RC oscillator             */
+            if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+              SystemCoreClock = __IRC_OSC_CLK;
+            } else {
+              SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+            }
+            break;
+          case 1:                       /* System oscillator                  */
+            if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
+              SystemCoreClock = __SYS_OSC_CLK;
+            } else {
+              SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+            }
+            break;
+          case 2:                       /* Reserved                           */
+          case 3:                       /* Reserved                           */
+            SystemCoreClock = 0;
+            break;
+      }
+      break;
+  }
+
+  SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;  
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void) {
+  volatile uint32_t i;
+
+#if (CLOCK_SETUP)                                 /* Clock Setup              */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+  LPC_SYSCON->PDRUNCFG     &= ~(1 << 5);          /* Power-up System Osc      */
+  LPC_SYSCON->SYSOSCCTRL    = SYSOSCCTRL_Val;
+  for (i = 0; i < 200; i++) __NOP();
+#endif
+
+  LPC_SYSCON->SYSPLLCLKSEL  = SYSPLLCLKSEL_Val;   /* Select PLL Input         */
+#if ((MAINCLKSEL_Val & 0x03) == 3)                /* Main Clock is PLL Out    */
+  LPC_SYSCON->SYSPLLCTRL    = SYSPLLCTRL_Val;
+  LPC_SYSCON->PDRUNCFG     &= ~(1 << 7);          /* Power-up SYSPLL          */
+  while (!(LPC_SYSCON->SYSPLLSTAT & 0x01));	      /* Wait Until PLL Locked    */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+  LPC_SYSCON->WDTOSCCTRL    = WDTOSCCTRL_Val;
+  LPC_SYSCON->PDRUNCFG     &= ~(1 << 6);          /* Power-up WDT Clock       */
+  for (i = 0; i < 200; i++) __NOP();
+#endif
+
+  LPC_SYSCON->MAINCLKSEL    = MAINCLKSEL_Val;     /* Select PLL Clock Output  */
+
+  LPC_SYSCON->SYSAHBCLKDIV  = SYSAHBCLKDIV_Val;
+
+#if ((USBCLKDIV_Val & 0x1FF) != 0)                /* USB clock is used        */
+  LPC_SYSCON->PDRUNCFG     &= ~(1 << 10);         /* Power-up USB PHY         */
+
+  /* Regardless USB PLL is used as USB clock or not, USB PLL needs to be configured. */
+  LPC_SYSCON->PDRUNCFG     &= ~(1 <<  8);         /* Power-up USB PLL         */
+  LPC_SYSCON->USBPLLCLKSEL  = USBPLLCLKSEL_Val;   /* Select PLL Input         */
+  LPC_SYSCON->USBPLLCTRL    = USBPLLCTRL_Val;
+  while (!(LPC_SYSCON->USBPLLSTAT   & 0x01));     /* Wait Until PLL Locked    */
+
+  LPC_SYSCON->USBCLKSEL     = USBCLKSEL_Val;      /* Select USB Clock         */
+  LPC_SYSCON->USBCLKDIV     = USBCLKDIV_Val;      /* Set USB clock divider    */
+
+#else                                             /* USB clock is not used    */                        
+  LPC_SYSCON->PDRUNCFG     |=  (1 << 10);         /* Power-down USB PHY       */
+  LPC_SYSCON->PDRUNCFG     |=  (1 <<  8);         /* Power-down USB PLL       */
+#endif
+
+#endif
+
+  /* System clock to the IOCON needs to be enabled or
+  most of the I/O related peripherals won't work. */
+  LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
+
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC13XX/system_LPC13Uxx.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file     system_LPC13Uxx.h
+ * @brief    CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ *           for the NXP LPC13Uxx Device Series
+ * @version  V1.10
+ * @date     24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC13Uxx_H
+#define __SYSTEM_LPC13Uxx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC13Uxx_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/LPC17xx.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,1035 @@
+/**************************************************************************//**
+ * @file     LPC17xx.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File for 
+ *           NXP LPC17xx Device Series
+ * @version: V1.09
+ * @date:    17. March 2010
+
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __LPC17xx_H__
+#define __LPC17xx_H__
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
+  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
+  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
+  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
+  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
+  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
+  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
+  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
+  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
+
+/******  LPC17xx Specific Interrupt Numbers *******************************************************/
+  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
+  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */
+  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */
+  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */
+  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */
+  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */
+  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */
+  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */
+  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */
+  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */
+  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */
+  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */
+  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */
+  SPI_IRQn                      = 13,       /*!< SPI Interrupt                                    */
+  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */
+  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */
+  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
+  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */
+  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */
+  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */
+  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */
+  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */
+  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */
+  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */
+  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */
+  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */
+  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */
+  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */
+  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */
+  RIT_IRQn                      = 29,       /*!< Repetitive Interrupt Timer Interrupt             */
+  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */
+  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */
+  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */
+  USBActivity_IRQn              = 33,       /* USB Activity interrupt                             */
+  CANActivity_IRQn              = 34,       /* CAN Activity interrupt                             */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT             1         /*!< MPU present or not                               */
+#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+
+
+#include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */
+#include "system_LPC17xx.h"                 /* System Header                                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t FLASHCFG;               /* Flash Accelerator Module           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t PLL0CON;                /* Clocking and Power Control         */
+  __IO uint32_t PLL0CFG;
+  __I  uint32_t PLL0STAT;
+  __O  uint32_t PLL0FEED;
+       uint32_t RESERVED1[4];
+  __IO uint32_t PLL1CON;
+  __IO uint32_t PLL1CFG;
+  __I  uint32_t PLL1STAT;
+  __O  uint32_t PLL1FEED;
+       uint32_t RESERVED2[4];
+  __IO uint32_t PCON;
+  __IO uint32_t PCONP;
+       uint32_t RESERVED3[15];
+  __IO uint32_t CCLKCFG;
+  __IO uint32_t USBCLKCFG;
+  __IO uint32_t CLKSRCSEL;
+  __IO uint32_t	CANSLEEPCLR;
+  __IO uint32_t	CANWAKEFLAGS;
+       uint32_t RESERVED4[10];
+  __IO uint32_t EXTINT;                 /* External Interrupts                */
+       uint32_t RESERVED5;
+  __IO uint32_t EXTMODE;
+  __IO uint32_t EXTPOLAR;
+       uint32_t RESERVED6[12];
+  __IO uint32_t RSID;                   /* Reset                              */
+       uint32_t RESERVED7[7];
+  __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */
+  __IO uint32_t IRCTRIM;                /* Clock Dividers                     */
+  __IO uint32_t PCLKSEL0;
+  __IO uint32_t PCLKSEL1;
+       uint32_t RESERVED8[4];
+  __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */
+  __IO uint32_t DMAREQSEL;
+  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */
+ } LPC_SC_TypeDef;
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+  __IO uint32_t PINSEL0;
+  __IO uint32_t PINSEL1;
+  __IO uint32_t PINSEL2;
+  __IO uint32_t PINSEL3;
+  __IO uint32_t PINSEL4;
+  __IO uint32_t PINSEL5;
+  __IO uint32_t PINSEL6;
+  __IO uint32_t PINSEL7;
+  __IO uint32_t PINSEL8;
+  __IO uint32_t PINSEL9;
+  __IO uint32_t PINSEL10;
+       uint32_t RESERVED0[5];
+  __IO uint32_t PINMODE0;
+  __IO uint32_t PINMODE1;
+  __IO uint32_t PINMODE2;
+  __IO uint32_t PINMODE3;
+  __IO uint32_t PINMODE4;
+  __IO uint32_t PINMODE5;
+  __IO uint32_t PINMODE6;
+  __IO uint32_t PINMODE7;
+  __IO uint32_t PINMODE8;
+  __IO uint32_t PINMODE9;
+  __IO uint32_t PINMODE_OD0;
+  __IO uint32_t PINMODE_OD1;
+  __IO uint32_t PINMODE_OD2;
+  __IO uint32_t PINMODE_OD3;
+  __IO uint32_t PINMODE_OD4;
+  __IO uint32_t I2CPADCFG;
+} LPC_PINCON_TypeDef;
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+  union {
+    __IO uint32_t FIODIR;
+    struct {
+      __IO uint16_t FIODIRL;
+      __IO uint16_t FIODIRH;
+    };
+    struct {
+      __IO uint8_t  FIODIR0;
+      __IO uint8_t  FIODIR1;
+      __IO uint8_t  FIODIR2;
+      __IO uint8_t  FIODIR3;
+    };
+  };
+  uint32_t RESERVED0[3];
+  union {
+    __IO uint32_t FIOMASK;
+    struct {
+      __IO uint16_t FIOMASKL;
+      __IO uint16_t FIOMASKH;
+    };
+    struct {
+      __IO uint8_t  FIOMASK0;
+      __IO uint8_t  FIOMASK1;
+      __IO uint8_t  FIOMASK2;
+      __IO uint8_t  FIOMASK3;
+    };
+  };
+  union {
+    __IO uint32_t FIOPIN;
+    struct {
+      __IO uint16_t FIOPINL;
+      __IO uint16_t FIOPINH;
+    };
+    struct {
+      __IO uint8_t  FIOPIN0;
+      __IO uint8_t  FIOPIN1;
+      __IO uint8_t  FIOPIN2;
+      __IO uint8_t  FIOPIN3;
+    };
+  };
+  union {
+    __IO uint32_t FIOSET;
+    struct {
+      __IO uint16_t FIOSETL;
+      __IO uint16_t FIOSETH;
+    };
+    struct {
+      __IO uint8_t  FIOSET0;
+      __IO uint8_t  FIOSET1;
+      __IO uint8_t  FIOSET2;
+      __IO uint8_t  FIOSET3;
+    };
+  };
+  union {
+    __O  uint32_t FIOCLR;
+    struct {
+      __O  uint16_t FIOCLRL;
+      __O  uint16_t FIOCLRH;
+    };
+    struct {
+      __O  uint8_t  FIOCLR0;
+      __O  uint8_t  FIOCLR1;
+      __O  uint8_t  FIOCLR2;
+      __O  uint8_t  FIOCLR3;
+    };
+  };
+} LPC_GPIO_TypeDef;
+
+typedef struct
+{
+  __I  uint32_t IntStatus;
+  __I  uint32_t IO0IntStatR;
+  __I  uint32_t IO0IntStatF;
+  __O  uint32_t IO0IntClr;
+  __IO uint32_t IO0IntEnR;
+  __IO uint32_t IO0IntEnF;
+       uint32_t RESERVED0[3];
+  __I  uint32_t IO2IntStatR;
+  __I  uint32_t IO2IntStatF;
+  __O  uint32_t IO2IntClr;
+  __IO uint32_t IO2IntEnR;
+  __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t IR;
+  __IO uint32_t TCR;
+  __IO uint32_t TC;
+  __IO uint32_t PR;
+  __IO uint32_t PC;
+  __IO uint32_t MCR;
+  __IO uint32_t MR0;
+  __IO uint32_t MR1;
+  __IO uint32_t MR2;
+  __IO uint32_t MR3;
+  __IO uint32_t CCR;
+  __I  uint32_t CR0;
+  __I  uint32_t CR1;
+       uint32_t RESERVED0[2];
+  __IO uint32_t EMR;
+       uint32_t RESERVED1[12];
+  __IO uint32_t CTCR;
+} LPC_TIM_TypeDef;
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+  __IO uint32_t IR;
+  __IO uint32_t TCR;
+  __IO uint32_t TC;
+  __IO uint32_t PR;
+  __IO uint32_t PC;
+  __IO uint32_t MCR;
+  __IO uint32_t MR0;
+  __IO uint32_t MR1;
+  __IO uint32_t MR2;
+  __IO uint32_t MR3;
+  __IO uint32_t CCR;
+  __I  uint32_t CR0;
+  __I  uint32_t CR1;
+  __I  uint32_t CR2;
+  __I  uint32_t CR3;
+       uint32_t RESERVED0;
+  __IO uint32_t MR4;
+  __IO uint32_t MR5;
+  __IO uint32_t MR6;
+  __IO uint32_t PCR;
+  __IO uint32_t LER;
+       uint32_t RESERVED1[7];
+  __IO uint32_t CTCR;
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+  union {
+  __I  uint8_t  RBR;
+  __O  uint8_t  THR;
+  __IO uint8_t  DLL;
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;
+  __IO uint32_t IER;
+  };
+  union {
+  __I  uint32_t IIR;
+  __O  uint8_t  FCR;
+  };
+  __IO uint8_t  LCR;
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;
+  __IO uint8_t  ICR;
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;
+       uint8_t  RESERVED6[39];
+  __IO uint32_t FIFOLVL;
+} LPC_UART_TypeDef;
+
+typedef struct
+{
+  union {
+  __I  uint8_t  RBR;
+  __O  uint8_t  THR;
+  __IO uint8_t  DLL;
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;
+  __IO uint32_t IER;
+  };
+  union {
+  __I  uint32_t IIR;
+  __O  uint8_t  FCR;
+  };
+  __IO uint8_t  LCR;
+       uint8_t  RESERVED1[7];
+  __I  uint8_t  LSR;
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;
+  __IO uint8_t  ICR;
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;
+       uint8_t  RESERVED6[39];
+  __IO uint32_t FIFOLVL;
+} LPC_UART0_TypeDef;
+
+typedef struct
+{
+  union {
+  __I  uint8_t  RBR;
+  __O  uint8_t  THR;
+  __IO uint8_t  DLL;
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;
+  __IO uint32_t IER;
+  };
+  union {
+  __I  uint32_t IIR;
+  __O  uint8_t  FCR;
+  };
+  __IO uint8_t  LCR;
+       uint8_t  RESERVED1[3];
+  __IO uint8_t  MCR;
+       uint8_t  RESERVED2[3];
+  __I  uint8_t  LSR;
+       uint8_t  RESERVED3[3];
+  __I  uint8_t  MSR;
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  SCR;
+       uint8_t  RESERVED5[3];
+  __IO uint32_t ACR;
+       uint32_t RESERVED6;
+  __IO uint32_t FDR;
+       uint32_t RESERVED7;
+  __IO uint8_t  TER;
+       uint8_t  RESERVED8[27];
+  __IO uint8_t  RS485CTRL;
+       uint8_t  RESERVED9[3];
+  __IO uint8_t  ADRMATCH;
+       uint8_t  RESERVED10[3];
+  __IO uint8_t  RS485DLY;
+       uint8_t  RESERVED11[3];
+  __IO uint32_t FIFOLVL;
+} LPC_UART1_TypeDef;
+
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
+typedef struct
+{
+  __IO uint32_t SPCR;
+  __I  uint32_t SPSR;
+  __IO uint32_t SPDR;
+  __IO uint32_t SPCCR;
+       uint32_t RESERVED0[3];
+  __IO uint32_t SPINT;
+} LPC_SPI_TypeDef;
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+  __IO uint32_t CR0;
+  __IO uint32_t CR1;
+  __IO uint32_t DR;
+  __I  uint32_t SR;
+  __IO uint32_t CPSR;
+  __IO uint32_t IMSC;
+  __IO uint32_t RIS;
+  __IO uint32_t MIS;
+  __IO uint32_t ICR;
+  __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+  __IO uint32_t I2CONSET;
+  __I  uint32_t I2STAT;
+  __IO uint32_t I2DAT;
+  __IO uint32_t I2ADR0;
+  __IO uint32_t I2SCLH;
+  __IO uint32_t I2SCLL;
+  __O  uint32_t I2CONCLR;
+  __IO uint32_t MMCTRL;
+  __IO uint32_t I2ADR1;
+  __IO uint32_t I2ADR2;
+  __IO uint32_t I2ADR3;
+  __I  uint32_t I2DATA_BUFFER;
+  __IO uint32_t I2MASK0;
+  __IO uint32_t I2MASK1;
+  __IO uint32_t I2MASK2;
+  __IO uint32_t I2MASK3;
+} LPC_I2C_TypeDef;
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+  __IO uint32_t I2SDAO;
+  __IO uint32_t I2SDAI;
+  __O  uint32_t I2STXFIFO;
+  __I  uint32_t I2SRXFIFO;
+  __I  uint32_t I2SSTATE;
+  __IO uint32_t I2SDMA1;
+  __IO uint32_t I2SDMA2;
+  __IO uint32_t I2SIRQ;
+  __IO uint32_t I2STXRATE;
+  __IO uint32_t I2SRXRATE;
+  __IO uint32_t I2STXBITRATE;
+  __IO uint32_t I2SRXBITRATE;
+  __IO uint32_t I2STXMODE;
+  __IO uint32_t I2SRXMODE;
+} LPC_I2S_TypeDef;
+
+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
+typedef struct
+{
+  __IO uint32_t RICOMPVAL;
+  __IO uint32_t RIMASK;
+  __IO uint8_t  RICTRL;
+       uint8_t  RESERVED0[3];
+  __IO uint32_t RICOUNTER;
+} LPC_RIT_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+  __IO uint8_t  ILR;
+       uint8_t  RESERVED0[7];
+  __IO uint8_t  CCR;
+       uint8_t  RESERVED1[3];
+  __IO uint8_t  CIIR;
+       uint8_t  RESERVED2[3];
+  __IO uint8_t  AMR;
+       uint8_t  RESERVED3[3];
+  __I  uint32_t CTIME0;
+  __I  uint32_t CTIME1;
+  __I  uint32_t CTIME2;
+  __IO uint8_t  SEC;
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  MIN;
+       uint8_t  RESERVED5[3];
+  __IO uint8_t  HOUR;
+       uint8_t  RESERVED6[3];
+  __IO uint8_t  DOM;
+       uint8_t  RESERVED7[3];
+  __IO uint8_t  DOW;
+       uint8_t  RESERVED8[3];
+  __IO uint16_t DOY;
+       uint16_t RESERVED9;
+  __IO uint8_t  MONTH;
+       uint8_t  RESERVED10[3];
+  __IO uint16_t YEAR;
+       uint16_t RESERVED11;
+  __IO uint32_t CALIBRATION;
+  __IO uint32_t GPREG0;
+  __IO uint32_t GPREG1;
+  __IO uint32_t GPREG2;
+  __IO uint32_t GPREG3;
+  __IO uint32_t GPREG4;
+  __IO uint8_t  RTC_AUXEN;
+       uint8_t  RESERVED12[3];
+  __IO uint8_t  RTC_AUX;
+       uint8_t  RESERVED13[3];
+  __IO uint8_t  ALSEC;
+       uint8_t  RESERVED14[3];
+  __IO uint8_t  ALMIN;
+       uint8_t  RESERVED15[3];
+  __IO uint8_t  ALHOUR;
+       uint8_t  RESERVED16[3];
+  __IO uint8_t  ALDOM;
+       uint8_t  RESERVED17[3];
+  __IO uint8_t  ALDOW;
+       uint8_t  RESERVED18[3];
+  __IO uint16_t ALDOY;
+       uint16_t RESERVED19;
+  __IO uint8_t  ALMON;
+       uint8_t  RESERVED20[3];
+  __IO uint16_t ALYEAR;
+       uint16_t RESERVED21;
+} LPC_RTC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+  __IO uint8_t  WDMOD;
+       uint8_t  RESERVED0[3];
+  __IO uint32_t WDTC;
+  __O  uint8_t  WDFEED;
+       uint8_t  RESERVED1[3];
+  __I  uint32_t WDTV;
+  __IO uint32_t WDCLKSEL;
+} LPC_WDT_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+  __IO uint32_t ADCR;
+  __IO uint32_t ADGDR;
+       uint32_t RESERVED0;
+  __IO uint32_t ADINTEN;
+  __I  uint32_t ADDR0;
+  __I  uint32_t ADDR1;
+  __I  uint32_t ADDR2;
+  __I  uint32_t ADDR3;
+  __I  uint32_t ADDR4;
+  __I  uint32_t ADDR5;
+  __I  uint32_t ADDR6;
+  __I  uint32_t ADDR7;
+  __I  uint32_t ADSTAT;
+  __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+  __IO uint32_t DACR;
+  __IO uint32_t DACCTRL;
+  __IO uint16_t DACCNTVAL;
+} LPC_DAC_TypeDef;
+
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+typedef struct
+{
+  __I  uint32_t MCCON;
+  __O  uint32_t MCCON_SET;
+  __O  uint32_t MCCON_CLR;
+  __I  uint32_t MCCAPCON;
+  __O  uint32_t MCCAPCON_SET;
+  __O  uint32_t MCCAPCON_CLR;
+  __IO uint32_t MCTIM0;
+  __IO uint32_t MCTIM1;
+  __IO uint32_t MCTIM2;
+  __IO uint32_t MCPER0;
+  __IO uint32_t MCPER1;
+  __IO uint32_t MCPER2;
+  __IO uint32_t MCPW0;
+  __IO uint32_t MCPW1;
+  __IO uint32_t MCPW2;
+  __IO uint32_t MCDEADTIME;
+  __IO uint32_t MCCCP;
+  __IO uint32_t MCCR0;
+  __IO uint32_t MCCR1;
+  __IO uint32_t MCCR2;
+  __I  uint32_t MCINTEN;
+  __O  uint32_t MCINTEN_SET;
+  __O  uint32_t MCINTEN_CLR;
+  __I  uint32_t MCCNTCON;
+  __O  uint32_t MCCNTCON_SET;
+  __O  uint32_t MCCNTCON_CLR;
+  __I  uint32_t MCINTFLAG;
+  __O  uint32_t MCINTFLAG_SET;
+  __O  uint32_t MCINTFLAG_CLR;
+  __O  uint32_t MCCAP_CLR;
+} LPC_MCPWM_TypeDef;
+
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+typedef struct
+{
+  __O  uint32_t QEICON;
+  __I  uint32_t QEISTAT;
+  __IO uint32_t QEICONF;
+  __I  uint32_t QEIPOS;
+  __IO uint32_t QEIMAXPOS;
+  __IO uint32_t CMPOS0;
+  __IO uint32_t CMPOS1;
+  __IO uint32_t CMPOS2;
+  __I  uint32_t INXCNT;
+  __IO uint32_t INXCMP;
+  __IO uint32_t QEILOAD;
+  __I  uint32_t QEITIME;
+  __I  uint32_t QEIVEL;
+  __I  uint32_t QEICAP;
+  __IO uint32_t VELCOMP;
+  __IO uint32_t FILTER;
+       uint32_t RESERVED0[998];
+  __O  uint32_t QEIIEC;
+  __O  uint32_t QEIIES;
+  __I  uint32_t QEIINTSTAT;
+  __I  uint32_t QEIIE;
+  __O  uint32_t QEICLR;
+  __O  uint32_t QEISET;
+} LPC_QEI_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+  __IO uint32_t mask[512];              /* ID Masks                           */
+} LPC_CANAF_RAM_TypeDef;
+
+typedef struct                          /* Acceptance Filter Registers        */
+{
+  __IO uint32_t AFMR;
+  __IO uint32_t SFF_sa;
+  __IO uint32_t SFF_GRP_sa;
+  __IO uint32_t EFF_sa;
+  __IO uint32_t EFF_GRP_sa;
+  __IO uint32_t ENDofTable;
+  __I  uint32_t LUTerrAd;
+  __I  uint32_t LUTerr;
+  __IO uint32_t FCANIE;
+  __IO uint32_t FCANIC0;
+  __IO uint32_t FCANIC1;
+} LPC_CANAF_TypeDef;
+
+typedef struct                          /* Central Registers                  */
+{
+  __I  uint32_t CANTxSR;
+  __I  uint32_t CANRxSR;
+  __I  uint32_t CANMSR;
+} LPC_CANCR_TypeDef;
+
+typedef struct                          /* Controller Registers               */
+{
+  __IO uint32_t MOD;
+  __O  uint32_t CMR;
+  __IO uint32_t GSR;
+  __I  uint32_t ICR;
+  __IO uint32_t IER;
+  __IO uint32_t BTR;
+  __IO uint32_t EWL;
+  __I  uint32_t SR;
+  __IO uint32_t RFS;
+  __IO uint32_t RID;
+  __IO uint32_t RDA;
+  __IO uint32_t RDB;
+  __IO uint32_t TFI1;
+  __IO uint32_t TID1;
+  __IO uint32_t TDA1;
+  __IO uint32_t TDB1;
+  __IO uint32_t TFI2;
+  __IO uint32_t TID2;
+  __IO uint32_t TDA2;
+  __IO uint32_t TDB2;
+  __IO uint32_t TFI3;
+  __IO uint32_t TID3;
+  __IO uint32_t TDA3;
+  __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct                          /* Common Registers                   */
+{
+  __I  uint32_t DMACIntStat;
+  __I  uint32_t DMACIntTCStat;
+  __O  uint32_t DMACIntTCClear;
+  __I  uint32_t DMACIntErrStat;
+  __O  uint32_t DMACIntErrClr;
+  __I  uint32_t DMACRawIntTCStat;
+  __I  uint32_t DMACRawIntErrStat;
+  __I  uint32_t DMACEnbldChns;
+  __IO uint32_t DMACSoftBReq;
+  __IO uint32_t DMACSoftSReq;
+  __IO uint32_t DMACSoftLBReq;
+  __IO uint32_t DMACSoftLSReq;
+  __IO uint32_t DMACConfig;
+  __IO uint32_t DMACSync;
+} LPC_GPDMA_TypeDef;
+
+typedef struct                          /* Channel Registers                  */
+{
+  __IO uint32_t DMACCSrcAddr;
+  __IO uint32_t DMACCDestAddr;
+  __IO uint32_t DMACCLLI;
+  __IO uint32_t DMACCControl;
+  __IO uint32_t DMACCConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+  __I  uint32_t HcRevision;             /* USB Host Registers                 */
+  __IO uint32_t HcControl;
+  __IO uint32_t HcCommandStatus;
+  __IO uint32_t HcInterruptStatus;
+  __IO uint32_t HcInterruptEnable;
+  __IO uint32_t HcInterruptDisable;
+  __IO uint32_t HcHCCA;
+  __I  uint32_t HcPeriodCurrentED;
+  __IO uint32_t HcControlHeadED;
+  __IO uint32_t HcControlCurrentED;
+  __IO uint32_t HcBulkHeadED;
+  __IO uint32_t HcBulkCurrentED;
+  __I  uint32_t HcDoneHead;
+  __IO uint32_t HcFmInterval;
+  __I  uint32_t HcFmRemaining;
+  __I  uint32_t HcFmNumber;
+  __IO uint32_t HcPeriodicStart;
+  __IO uint32_t HcLSTreshold;
+  __IO uint32_t HcRhDescriptorA;
+  __IO uint32_t HcRhDescriptorB;
+  __IO uint32_t HcRhStatus;
+  __IO uint32_t HcRhPortStatus1;
+  __IO uint32_t HcRhPortStatus2;
+       uint32_t RESERVED0[40];
+  __I  uint32_t Module_ID;
+
+  __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */
+  __IO uint32_t OTGIntEn;
+  __O  uint32_t OTGIntSet;
+  __O  uint32_t OTGIntClr;
+  __IO uint32_t OTGStCtrl;
+  __IO uint32_t OTGTmr;
+       uint32_t RESERVED1[58];
+
+  __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */
+  __IO uint32_t USBDevIntEn;
+  __O  uint32_t USBDevIntClr;
+  __O  uint32_t USBDevIntSet;
+
+  __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */
+  __I  uint32_t USBCmdData;
+
+  __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */
+  __O  uint32_t USBTxData;
+  __I  uint32_t USBRxPLen;
+  __O  uint32_t USBTxPLen;
+  __IO uint32_t USBCtrl;
+  __O  uint32_t USBDevIntPri;
+
+  __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */
+  __IO uint32_t USBEpIntEn;
+  __O  uint32_t USBEpIntClr;
+  __O  uint32_t USBEpIntSet;
+  __O  uint32_t USBEpIntPri;
+
+  __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/
+  __O  uint32_t USBEpInd;
+  __IO uint32_t USBMaxPSize;
+
+  __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */
+  __O  uint32_t USBDMARClr;
+  __O  uint32_t USBDMARSet;
+       uint32_t RESERVED2[9];
+  __IO uint32_t USBUDCAH;
+  __I  uint32_t USBEpDMASt;
+  __O  uint32_t USBEpDMAEn;
+  __O  uint32_t USBEpDMADis;
+  __I  uint32_t USBDMAIntSt;
+  __IO uint32_t USBDMAIntEn;
+       uint32_t RESERVED3[2];
+  __I  uint32_t USBEoTIntSt;
+  __O  uint32_t USBEoTIntClr;
+  __O  uint32_t USBEoTIntSet;
+  __I  uint32_t USBNDDRIntSt;
+  __O  uint32_t USBNDDRIntClr;
+  __O  uint32_t USBNDDRIntSet;
+  __I  uint32_t USBSysErrIntSt;
+  __O  uint32_t USBSysErrIntClr;
+  __O  uint32_t USBSysErrIntSet;
+       uint32_t RESERVED4[15];
+
+  union {
+  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
+  __O  uint32_t I2C_TX;
+  };
+  __I  uint32_t I2C_STS;
+  __IO uint32_t I2C_CTL;
+  __IO uint32_t I2C_CLKHI;
+  __O  uint32_t I2C_CLKLO;
+       uint32_t RESERVED5[824];
+
+  union {
+  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
+  __IO uint32_t OTGClkCtrl;
+  };
+  union {
+  __I  uint32_t USBClkSt;
+  __I  uint32_t OTGClkSt;
+  };
+} LPC_USB_TypeDef;
+
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+  __IO uint32_t MAC1;                   /* MAC Registers                      */
+  __IO uint32_t MAC2;
+  __IO uint32_t IPGT;
+  __IO uint32_t IPGR;
+  __IO uint32_t CLRT;
+  __IO uint32_t MAXF;
+  __IO uint32_t SUPP;
+  __IO uint32_t TEST;
+  __IO uint32_t MCFG;
+  __IO uint32_t MCMD;
+  __IO uint32_t MADR;
+  __O  uint32_t MWTD;
+  __I  uint32_t MRDD;
+  __I  uint32_t MIND;
+       uint32_t RESERVED0[2];
+  __IO uint32_t SA0;
+  __IO uint32_t SA1;
+  __IO uint32_t SA2;
+       uint32_t RESERVED1[45];
+  __IO uint32_t Command;                /* Control Registers                  */
+  __I  uint32_t Status;
+  __IO uint32_t RxDescriptor;
+  __IO uint32_t RxStatus;
+  __IO uint32_t RxDescriptorNumber;
+  __I  uint32_t RxProduceIndex;
+  __IO uint32_t RxConsumeIndex;
+  __IO uint32_t TxDescriptor;
+  __IO uint32_t TxStatus;
+  __IO uint32_t TxDescriptorNumber;
+  __IO uint32_t TxProduceIndex;
+  __I  uint32_t TxConsumeIndex;
+       uint32_t RESERVED2[10];
+  __I  uint32_t TSV0;
+  __I  uint32_t TSV1;
+  __I  uint32_t RSV;
+       uint32_t RESERVED3[3];
+  __IO uint32_t FlowControlCounter;
+  __I  uint32_t FlowControlStatus;
+       uint32_t RESERVED4[34];
+  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
+  __IO uint32_t RxFilterWoLStatus;
+  __IO uint32_t RxFilterWoLClear;
+       uint32_t RESERVED5;
+  __IO uint32_t HashFilterL;
+  __IO uint32_t HashFilterH;
+       uint32_t RESERVED6[882];
+  __I  uint32_t IntStatus;              /* Module Control Registers           */
+  __IO uint32_t IntEnable;
+  __O  uint32_t IntClear;
+  __O  uint32_t IntSet;
+       uint32_t RESERVED7;
+  __IO uint32_t PowerDown;
+       uint32_t RESERVED8;
+  __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* Base addresses                                                             */
+#define LPC_FLASH_BASE        (0x00000000UL)
+#define LPC_RAM_BASE          (0x10000000UL)
+#define LPC_GPIO_BASE         (0x2009C000UL)
+#define LPC_APB0_BASE         (0x40000000UL)
+#define LPC_APB1_BASE         (0x40080000UL)
+#define LPC_AHB_BASE          (0x50000000UL)
+#define LPC_CM3_BASE          (0xE0000000UL)
+
+/* APB0 peripherals                                                           */
+#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)
+#define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)
+#define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)
+#define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)
+#define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)
+#define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)
+#define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)
+#define LPC_SPI_BASE          (LPC_APB0_BASE + 0x20000)
+#define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)
+#define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)
+#define LPC_PINCON_BASE       (LPC_APB0_BASE + 0x2C000)
+#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)
+#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)
+#define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)
+#define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)
+#define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)
+#define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)
+#define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)
+
+/* APB1 peripherals                                                           */
+#define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)
+#define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)
+#define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)
+#define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)
+#define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)
+#define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)
+#define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)
+#define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)
+#define LPC_RIT_BASE          (LPC_APB1_BASE + 0x30000)
+#define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)
+#define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)
+#define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)
+
+/* AHB peripherals                                                            */
+#define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x00000)
+#define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x04000)
+#define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x04100)
+#define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x04120)
+#define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x04140)
+#define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x04160)
+#define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x04180)
+#define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x041A0)
+#define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x041C0)
+#define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x041E0)
+#define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)
+
+/* GPIOs                                                                      */
+#define LPC_GPIO0_BASE        (LPC_GPIO_BASE + 0x00000)
+#define LPC_GPIO1_BASE        (LPC_GPIO_BASE + 0x00020)
+#define LPC_GPIO2_BASE        (LPC_GPIO_BASE + 0x00040)
+#define LPC_GPIO3_BASE        (LPC_GPIO_BASE + 0x00060)
+#define LPC_GPIO4_BASE        (LPC_GPIO_BASE + 0x00080)
+
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+#define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )
+#define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )
+#define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )
+#define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )
+#define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )
+#define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )
+#define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )
+#define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )
+#define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )
+#define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )
+#define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )
+#define LPC_RIT               ((LPC_RIT_TypeDef       *) LPC_RIT_BASE      )
+#define LPC_UART0             ((LPC_UART0_TypeDef     *) LPC_UART0_BASE    )
+#define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )
+#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
+#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
+#define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )
+#define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )
+#define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )
+#define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )
+#define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )
+#define LPC_SPI               ((LPC_SPI_TypeDef       *) LPC_SPI_BASE      )
+#define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )
+#define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )
+#define LPC_PINCON            ((LPC_PINCON_TypeDef    *) LPC_PINCON_BASE   )
+#define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )
+#define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )
+#define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )
+#define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )
+#define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )
+#define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )
+#define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )
+#define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )
+#define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )
+#define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )
+#define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )
+#define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )
+#define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )
+#define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )
+#define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )
+#define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )
+#define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )
+#define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )
+#define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )
+#define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )
+#define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )
+
+#endif  // __LPC17xx_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/LPC1768.sct	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,22 @@
+
+LR_IROM1 0x00000000 0x80000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x80000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(49 vect * 4 bytes) =  8_byte_aligned(0xC4) = 0xC8
+  ; 32KB - 0xC8 = 0x7F38
+  RW_IRAM1 0x100000C8 0x7F38  {
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x2007C000 0x4000  {  ; RW data, USB RAM
+   .ANY (AHBSRAM0)
+  }
+  RW_IRAM3 0x20080000 0x4000  {  ; RW data, ETH RAM
+   .ANY (AHBSRAM1)
+  }
+  RW_IRAM4 0x40038000 0x0800  {  ; RW data, CAN RAM
+   .ANY (CANRAM)
+  }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,243 @@
+;/*****************************************************************************
+; * @file:    startup_LPC17xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File 
+; *           for the NXP LPC17xx Device Series 
+; * @version: V1.02, modified for mbed
+; * @date:    27. July 2009, modified 3rd Aug 2009
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+Stack_Mem       SPACE   Stack_Size
+__initial_sp        EQU     0x10008000  ; Top of RAM from LPC1768
+
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ; 16: Watchdog Timer
+                DCD     TIMER0_IRQHandler         ; 17: Timer0
+                DCD     TIMER1_IRQHandler         ; 18: Timer1
+                DCD     TIMER2_IRQHandler         ; 19: Timer2
+                DCD     TIMER3_IRQHandler         ; 20: Timer3
+                DCD     UART0_IRQHandler          ; 21: UART0
+                DCD     UART1_IRQHandler          ; 22: UART1
+                DCD     UART2_IRQHandler          ; 23: UART2
+                DCD     UART3_IRQHandler          ; 24: UART3
+                DCD     PWM1_IRQHandler           ; 25: PWM1
+                DCD     I2C0_IRQHandler           ; 26: I2C0
+                DCD     I2C1_IRQHandler           ; 27: I2C1
+                DCD     I2C2_IRQHandler           ; 28: I2C2
+                DCD     SPI_IRQHandler            ; 29: SPI
+                DCD     SSP0_IRQHandler           ; 30: SSP0
+                DCD     SSP1_IRQHandler           ; 31: SSP1
+                DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
+                DCD     RTC_IRQHandler            ; 33: Real Time Clock
+                DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
+                DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
+                DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
+                DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
+                DCD     ADC_IRQHandler            ; 38: A/D Converter
+                DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
+                DCD     USB_IRQHandler            ; 40: USB
+                DCD     CAN_IRQHandler            ; 41: CAN
+                DCD     DMA_IRQHandler            ; 42: General Purpose DMA
+                DCD     I2S_IRQHandler            ; 43: I2S
+                DCD     ENET_IRQHandler           ; 44: Ethernet
+                DCD     RIT_IRQHandler            ; 45: Repetitive Interrupt Timer
+                DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
+                DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
+                DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
+
+
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  TIMER0_IRQHandler         [WEAK]
+                EXPORT  TIMER1_IRQHandler         [WEAK]
+                EXPORT  TIMER2_IRQHandler         [WEAK]
+                EXPORT  TIMER3_IRQHandler         [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  PWM1_IRQHandler           [WEAK]
+                EXPORT  I2C0_IRQHandler           [WEAK]
+                EXPORT  I2C1_IRQHandler           [WEAK]
+                EXPORT  I2C2_IRQHandler           [WEAK]
+                EXPORT  SPI_IRQHandler            [WEAK]
+                EXPORT  SSP0_IRQHandler           [WEAK]
+                EXPORT  SSP1_IRQHandler           [WEAK]
+                EXPORT  PLL0_IRQHandler           [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  EINT0_IRQHandler          [WEAK]
+                EXPORT  EINT1_IRQHandler          [WEAK]
+                EXPORT  EINT2_IRQHandler          [WEAK]
+                EXPORT  EINT3_IRQHandler          [WEAK]
+                EXPORT  ADC_IRQHandler            [WEAK]
+                EXPORT  BOD_IRQHandler            [WEAK]
+                EXPORT  USB_IRQHandler            [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  DMA_IRQHandler            [WEAK]
+                EXPORT  I2S_IRQHandler            [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  RIT_IRQHandler            [WEAK]
+                EXPORT  MCPWM_IRQHandler          [WEAK]
+                EXPORT  QEI_IRQHandler            [WEAK]
+                EXPORT  PLL1_IRQHandler           [WEAK]
+
+WDT_IRQHandler           
+TIMER0_IRQHandler         
+TIMER1_IRQHandler         
+TIMER2_IRQHandler         
+TIMER3_IRQHandler         
+UART0_IRQHandler          
+UART1_IRQHandler          
+UART2_IRQHandler          
+UART3_IRQHandler          
+PWM1_IRQHandler           
+I2C0_IRQHandler           
+I2C1_IRQHandler           
+I2C2_IRQHandler           
+SPI_IRQHandler            
+SSP0_IRQHandler           
+SSP1_IRQHandler           
+PLL0_IRQHandler           
+RTC_IRQHandler            
+EINT0_IRQHandler          
+EINT1_IRQHandler          
+EINT2_IRQHandler          
+EINT3_IRQHandler          
+ADC_IRQHandler            
+BOD_IRQHandler            
+USB_IRQHandler            
+CAN_IRQHandler            
+DMA_IRQHandler          
+I2S_IRQHandler            
+ENET_IRQHandler       
+RIT_IRQHandler          
+MCPWM_IRQHandler             
+QEI_IRQHandler            
+PLL1_IRQHandler           
+
+                B       .
+
+                ENDP
+                
+                ALIGN
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_MICRO/sys.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/LPC1768.sct	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,22 @@
+
+LR_IROM1 0x00000000 0x80000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x80000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(49 vect * 4 bytes) =  8_byte_aligned(0xC4) = 0xC8
+  ; 32KB - 0xC8 = 0x7F38
+  RW_IRAM1 0x100000C8 0x7F38  {
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x2007C000 0x4000  {  ; RW data, ETH RAM
+   .ANY (AHBSRAM0)
+  }
+  RW_IRAM3 0x20080000 0x4000  {  ; RW data, ETH RAM
+   .ANY (AHBSRAM1)
+  }
+  RW_IRAM4 0x40038000 0x0800  {  ; RW data, CAN RAM
+   .ANY (CANRAM)
+  }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/startup_LPC17xx.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,226 @@
+;/*****************************************************************************
+; * @file:    startup_LPC17xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File 
+; *           for the NXP LPC17xx Device Series 
+; * @version: V1.02, modified for mbed
+; * @date:    27. July 2009, modified 3rd Aug 2009
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+__initial_sp        EQU     0x10008000  ; Top of RAM from LPC1768
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ; 16: Watchdog Timer
+                DCD     TIMER0_IRQHandler         ; 17: Timer0
+                DCD     TIMER1_IRQHandler         ; 18: Timer1
+                DCD     TIMER2_IRQHandler         ; 19: Timer2
+                DCD     TIMER3_IRQHandler         ; 20: Timer3
+                DCD     UART0_IRQHandler          ; 21: UART0
+                DCD     UART1_IRQHandler          ; 22: UART1
+                DCD     UART2_IRQHandler          ; 23: UART2
+                DCD     UART3_IRQHandler          ; 24: UART3
+                DCD     PWM1_IRQHandler           ; 25: PWM1
+                DCD     I2C0_IRQHandler           ; 26: I2C0
+                DCD     I2C1_IRQHandler           ; 27: I2C1
+                DCD     I2C2_IRQHandler           ; 28: I2C2
+                DCD     SPI_IRQHandler            ; 29: SPI
+                DCD     SSP0_IRQHandler           ; 30: SSP0
+                DCD     SSP1_IRQHandler           ; 31: SSP1
+                DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
+                DCD     RTC_IRQHandler            ; 33: Real Time Clock
+                DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
+                DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
+                DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
+                DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
+                DCD     ADC_IRQHandler            ; 38: A/D Converter
+                DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
+                DCD     USB_IRQHandler            ; 40: USB
+                DCD     CAN_IRQHandler            ; 41: CAN
+                DCD     DMA_IRQHandler            ; 42: General Purpose DMA
+                DCD     I2S_IRQHandler            ; 43: I2S
+                DCD     ENET_IRQHandler           ; 44: Ethernet
+                DCD     RIT_IRQHandler            ; 45: Repetitive Interrupt Timer
+                DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
+                DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
+                DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
+
+
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  TIMER0_IRQHandler         [WEAK]
+                EXPORT  TIMER1_IRQHandler         [WEAK]
+                EXPORT  TIMER2_IRQHandler         [WEAK]
+                EXPORT  TIMER3_IRQHandler         [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  PWM1_IRQHandler           [WEAK]
+                EXPORT  I2C0_IRQHandler           [WEAK]
+                EXPORT  I2C1_IRQHandler           [WEAK]
+                EXPORT  I2C2_IRQHandler           [WEAK]
+                EXPORT  SPI_IRQHandler            [WEAK]
+                EXPORT  SSP0_IRQHandler           [WEAK]
+                EXPORT  SSP1_IRQHandler           [WEAK]
+                EXPORT  PLL0_IRQHandler           [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  EINT0_IRQHandler          [WEAK]
+                EXPORT  EINT1_IRQHandler          [WEAK]
+                EXPORT  EINT2_IRQHandler          [WEAK]
+                EXPORT  EINT3_IRQHandler          [WEAK]
+                EXPORT  ADC_IRQHandler            [WEAK]
+                EXPORT  BOD_IRQHandler            [WEAK]
+                EXPORT  USB_IRQHandler            [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  DMA_IRQHandler            [WEAK]
+                EXPORT  I2S_IRQHandler            [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  RIT_IRQHandler            [WEAK]
+                EXPORT  MCPWM_IRQHandler          [WEAK]
+                EXPORT  QEI_IRQHandler            [WEAK]
+                EXPORT  PLL1_IRQHandler           [WEAK]
+
+WDT_IRQHandler           
+TIMER0_IRQHandler         
+TIMER1_IRQHandler         
+TIMER2_IRQHandler         
+TIMER3_IRQHandler         
+UART0_IRQHandler          
+UART1_IRQHandler          
+UART2_IRQHandler          
+UART3_IRQHandler          
+PWM1_IRQHandler           
+I2C0_IRQHandler           
+I2C1_IRQHandler           
+I2C2_IRQHandler           
+SPI_IRQHandler            
+SSP0_IRQHandler           
+SSP1_IRQHandler           
+PLL0_IRQHandler           
+RTC_IRQHandler            
+EINT0_IRQHandler          
+EINT1_IRQHandler          
+EINT2_IRQHandler          
+EINT3_IRQHandler          
+ADC_IRQHandler            
+BOD_IRQHandler            
+USB_IRQHandler            
+CAN_IRQHandler            
+DMA_IRQHandler          
+I2S_IRQHandler            
+ENET_IRQHandler       
+RIT_IRQHandler          
+MCPWM_IRQHandler             
+QEI_IRQHandler            
+PLL1_IRQHandler           
+
+                B       .
+
+                ENDP
+                
+                ALIGN
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_ARM_STD/sys.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/LPC1768.ld	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,149 @@
+/* Linker script for mbed LPC1768 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38
+
+  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
+  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+        
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM
+    
+    .heap :
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy :
+    {
+        *(.stack)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+    
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_ARM/startup_LPC17xx.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,219 @@
+/* File: startup_ARMCM3.s
+ * Purpose: startup file for Cortex-M3/M4 devices. Should use with 
+ *   GNU Tools for ARM Embedded Processors
+ * Version: V1.1
+ * Date: 17 June 2011
+ * 
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ */
+    .syntax unified
+    .arch armv7-m
+
+/* Memory Model
+   The HEAP starts at the end of the DATA section and grows upward.
+   
+   The STACK starts at the end of the RAM and grows downward.
+   
+   The HEAP and stack STACK are only checked at compile time:
+   (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+   
+   This is just a check for the bare minimum for the Heap+Stack area before
+   aborting compilation, it is not the run time limit:
+   Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0xc00
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x800
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+    
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    NMI_Handler           /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    MemManage_Handler     /* MPU Fault Handler */
+    .long    BusFault_Handler      /* Bus Fault Handler */
+    .long    UsageFault_Handler    /* Usage Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    DebugMon_Handler      /* Debug Monitor Handler */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+    /* External interrupts */
+    .long   WDT_IRQHandler              /* 16: Watchdog Timer               */
+    .long   TIMER0_IRQHandler           /* 17: Timer0                       */
+    .long   TIMER1_IRQHandler           /* 18: Timer1                       */
+    .long   TIMER2_IRQHandler           /* 19: Timer2                       */
+    .long   TIMER3_IRQHandler           /* 20: Timer3                       */
+    .long   UART0_IRQHandler            /* 21: UART0                        */
+    .long   UART1_IRQHandler            /* 22: UART1                        */
+    .long   UART2_IRQHandler            /* 23: UART2                        */
+    .long   UART3_IRQHandler            /* 24: UART3                        */
+    .long   PWM1_IRQHandler             /* 25: PWM1                         */
+    .long   I2C0_IRQHandler             /* 26: I2C0                         */
+    .long   I2C1_IRQHandler             /* 27: I2C1                         */
+    .long   I2C2_IRQHandler             /* 28: I2C2                         */
+    .long   SPI_IRQHandler              /* 29: SPI                          */
+    .long   SSP0_IRQHandler             /* 30: SSP0                         */
+    .long   SSP1_IRQHandler             /* 31: SSP1                         */
+    .long   PLL0_IRQHandler             /* 32: PLL0 Lock (Main PLL)         */
+    .long   RTC_IRQHandler              /* 33: Real Time Clock              */
+    .long   EINT0_IRQHandler            /* 34: External Interrupt 0         */
+    .long   EINT1_IRQHandler            /* 35: External Interrupt 1         */
+    .long   EINT2_IRQHandler            /* 36: External Interrupt 2         */
+    .long   EINT3_IRQHandler            /* 37: External Interrupt 3         */
+    .long   ADC_IRQHandler              /* 38: A/D Converter                */
+    .long   BOD_IRQHandler              /* 39: Brown-Out Detect             */
+    .long   USB_IRQHandler              /* 40: USB                          */
+    .long   CAN_IRQHandler              /* 41: CAN                          */
+    .long   DMA_IRQHandler              /* 42: General Purpose DMA          */
+    .long   I2S_IRQHandler              /* 43: I2S                          */
+    .long   ENET_IRQHandler             /* 44: Ethernet                     */
+    .long   RIT_IRQHandler              /* 45: Repetitive Interrupt Timer   */
+    .long   MCPWM_IRQHandler            /* 46: Motor Control PWM            */
+    .long   QEI_IRQHandler              /* 47: Quadrature Encoder Interface */
+    .long   PLL1_IRQHandler             /* 48: PLL1 Lock (USB PLL)          */
+    .long   USBActivity_IRQHandler      /* 49: USB Activity                 */
+    .long   CANActivity_IRQHandler      /* 50: CAN Activity                 */
+
+    .size    __isr_vector, . - __isr_vector
+
+    .text
+    .thumb
+    .thumb_func
+    .align 2
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in 
+ *      linker script.
+ *      _etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+.flash_to_ram_loop:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .flash_to_ram_loop
+
+    ldr    r0, =SystemInit
+    blx    r0
+    ldr    r0, =_start
+    bx    r0
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+    
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_default_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+    
+    def_default_handler    NMI_Handler
+    def_default_handler    HardFault_Handler
+    def_default_handler    MemManage_Handler
+    def_default_handler    BusFault_Handler
+    def_default_handler    UsageFault_Handler
+    def_default_handler    SVC_Handler
+    def_default_handler    DebugMon_Handler
+    def_default_handler    PendSV_Handler
+    def_default_handler    SysTick_Handler
+    def_default_handler    Default_Handler
+    
+    def_default_handler     WDT_IRQHandler
+    def_default_handler     TIMER0_IRQHandler
+    def_default_handler     TIMER1_IRQHandler
+    def_default_handler     TIMER2_IRQHandler
+    def_default_handler     TIMER3_IRQHandler
+    def_default_handler     UART0_IRQHandler
+    def_default_handler     UART1_IRQHandler
+    def_default_handler     UART2_IRQHandler
+    def_default_handler     UART3_IRQHandler
+    def_default_handler     PWM1_IRQHandler
+    def_default_handler     I2C0_IRQHandler
+    def_default_handler     I2C1_IRQHandler
+    def_default_handler     I2C2_IRQHandler
+    def_default_handler     SPI_IRQHandler
+    def_default_handler     SSP0_IRQHandler
+    def_default_handler     SSP1_IRQHandler
+    def_default_handler     PLL0_IRQHandler
+    def_default_handler     RTC_IRQHandler
+    def_default_handler     EINT0_IRQHandler
+    def_default_handler     EINT1_IRQHandler
+    def_default_handler     EINT2_IRQHandler
+    def_default_handler     EINT3_IRQHandler
+    def_default_handler     ADC_IRQHandler
+    def_default_handler     BOD_IRQHandler
+    def_default_handler     USB_IRQHandler
+    def_default_handler     CAN_IRQHandler
+    def_default_handler     DMA_IRQHandler
+    def_default_handler     I2S_IRQHandler
+    def_default_handler     ENET_IRQHandler
+    def_default_handler     RIT_IRQHandler
+    def_default_handler     MCPWM_IRQHandler
+    def_default_handler     QEI_IRQHandler
+    def_default_handler     PLL1_IRQHandler
+    def_default_handler     USBActivity_IRQHandler
+    def_default_handler     CANActivity_IRQHandler
+
+    .weak    DEF_IRQHandler
+    .set    DEF_IRQHandler, Default_Handler
+
+    .end
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/LPC1768.ld	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,153 @@
+/* mbed - LPC1768 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 4.1
+ */
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+  /* Define each memory region */
+  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
+  RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 /* 32k */
+  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */
+
+}
+  /* Define a symbol for the top of each memory region */
+  __top_MFlash512 = 0x0 + 0x80000;
+  __top_RamLoc32 = 0x10000000 + 0x8000;
+  __top_RamAHB32 = 0x2007c000 + 0x8000;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+    /* MAIN TEXT SECTION */ 
+    .text : ALIGN(4)
+    {
+        FILL(0xff)
+        KEEP(*(.isr_vector))
+        
+        /* Global Section Table */
+        . = ALIGN(4) ;
+        __section_table_start = .;
+        __data_section_table = .;
+        LONG(LOADADDR(.data));
+        LONG(    ADDR(.data)) ;
+        LONG(  SIZEOF(.data));
+        LONG(LOADADDR(.data_RAM2));
+        LONG(    ADDR(.data_RAM2)) ;
+        LONG(  SIZEOF(.data_RAM2));
+        __data_section_table_end = .;
+        __bss_section_table = .;
+        LONG(    ADDR(.bss));
+        LONG(  SIZEOF(.bss));
+        LONG(    ADDR(.bss_RAM2));
+        LONG(  SIZEOF(.bss_RAM2));
+        __bss_section_table_end = .;
+        __section_table_end = . ;
+        /* End of Global Section Table */
+        
+
+        *(.after_vectors*)
+        
+        *(.text*)
+        *(.rodata .rodata.*)
+        . = ALIGN(4);
+        
+        /* C++ constructors etc */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+        
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+        
+        KEEP(*(.fini));
+        
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+        
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+        /* End C++ */
+    } > MFlash512
+
+    /*
+     * for exception handling/unwind - some Newlib functions (in common
+     * with C++ and STDC++) use this.
+     */
+    .ARM.extab : ALIGN(4)
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > MFlash512
+    __exidx_start = .;
+    
+    .ARM.exidx : ALIGN(4)
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > MFlash512
+    __exidx_end = .;
+    
+    _etext = .;
+        
+    
+    .data_RAM2 : ALIGN(4)
+    {
+       FILL(0xff)
+        *(.data.$RAM2*)
+        *(.data.$RamAHB32*)
+       . = ALIGN(4) ;
+    } > RamAHB32 AT>MFlash512
+    
+    /* MAIN DATA SECTION */
+
+    .uninit_RESERVED : ALIGN(4)
+    {
+        KEEP(*(.bss.$RESERVED*))
+    } > RamLoc32
+
+    .data : ALIGN(4)
+    {
+        FILL(0xff)
+        _data = .;
+        *(vtable)
+        *(.data*)
+        . = ALIGN(4) ;
+        _edata = .;
+    } > RamLoc32 AT>MFlash512
+
+    
+    .bss_RAM2 : ALIGN(4)
+    {
+        *(.bss.$RAM2*)
+        *(.bss.$RamAHB32*)
+       . = ALIGN(4) ;
+    } > RamAHB32
+
+    /* MAIN BSS SECTION */
+    .bss : ALIGN(4)
+    {
+        _bss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4) ;
+        _ebss = .;
+        PROVIDE(end = .);
+    } > RamLoc32
+    
+    PROVIDE(_pvHeapStart = .);
+    PROVIDE(_vStackTop = __top_RamLoc32 - 0);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,177 @@
+extern "C" {
+
+#include "LPC17xx.h"
+
+#define WEAK          __attribute__ ((weak))
+#define ALIAS(f)      __attribute__ ((weak, alias (#f)))
+#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))
+
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+extern void __libc_init_array(void);
+extern int main(void);
+extern void _vStackTop(void);
+extern void (* const g_pfnVectors[])(void);
+
+     void ResetISR          (void);
+WEAK void NMI_Handler       (void);
+WEAK void HardFault_Handler (void);
+WEAK void MemManage_Handler (void);
+WEAK void BusFault_Handler  (void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVCall_Handler    (void);
+WEAK void DebugMon_Handler  (void);
+WEAK void PendSV_Handler    (void);
+WEAK void SysTick_Handler   (void);
+WEAK void IntDefaultHandler (void);
+
+void WDT_IRQHandler        (void) ALIAS(IntDefaultHandler);
+void TIMER0_IRQHandler     (void) ALIAS(IntDefaultHandler);
+void TIMER1_IRQHandler     (void) ALIAS(IntDefaultHandler);
+void TIMER2_IRQHandler     (void) ALIAS(IntDefaultHandler);
+void TIMER3_IRQHandler     (void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler      (void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler      (void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler      (void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler      (void) ALIAS(IntDefaultHandler);
+void PWM1_IRQHandler       (void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler       (void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler       (void) ALIAS(IntDefaultHandler);
+void I2C2_IRQHandler       (void) ALIAS(IntDefaultHandler);
+void SPI_IRQHandler        (void) ALIAS(IntDefaultHandler);
+void SSP0_IRQHandler       (void) ALIAS(IntDefaultHandler);
+void SSP1_IRQHandler       (void) ALIAS(IntDefaultHandler);
+void PLL0_IRQHandler       (void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler        (void) ALIAS(IntDefaultHandler);
+void EINT0_IRQHandler      (void) ALIAS(IntDefaultHandler);
+void EINT1_IRQHandler      (void) ALIAS(IntDefaultHandler);
+void EINT2_IRQHandler      (void) ALIAS(IntDefaultHandler);
+void EINT3_IRQHandler      (void) ALIAS(IntDefaultHandler);
+void ADC_IRQHandler        (void) ALIAS(IntDefaultHandler);
+void BOD_IRQHandler        (void) ALIAS(IntDefaultHandler);
+void USB_IRQHandler        (void) ALIAS(IntDefaultHandler);
+void CAN_IRQHandler        (void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler        (void) ALIAS(IntDefaultHandler);
+void I2S_IRQHandler        (void) ALIAS(IntDefaultHandler);
+void ENET_IRQHandler       (void) ALIAS(IntDefaultHandler);
+void RIT_IRQHandler        (void) ALIAS(IntDefaultHandler);
+void MCPWM_IRQHandler      (void) ALIAS(IntDefaultHandler);
+void QEI_IRQHandler        (void) ALIAS(IntDefaultHandler);
+void PLL1_IRQHandler       (void) ALIAS(IntDefaultHandler);
+void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+    &_vStackTop, ResetISR, NMI_Handler,
+    HardFault_Handler,
+    MemManage_Handler,
+    BusFault_Handler,
+    UsageFault_Handler,
+    0,
+    0,
+    0,
+    0,
+    SVCall_Handler,
+    DebugMon_Handler,
+    0,
+    PendSV_Handler,
+    SysTick_Handler,
+    WDT_IRQHandler,
+    TIMER0_IRQHandler,
+    TIMER1_IRQHandler,
+    TIMER2_IRQHandler,
+    TIMER3_IRQHandler,
+    UART0_IRQHandler,
+    UART1_IRQHandler,
+    UART2_IRQHandler,
+    UART3_IRQHandler,
+    PWM1_IRQHandler,
+    I2C0_IRQHandler,
+    I2C1_IRQHandler,
+    I2C2_IRQHandler,
+    SPI_IRQHandler,
+    SSP0_IRQHandler,
+    SSP1_IRQHandler,
+    PLL0_IRQHandler,
+    RTC_IRQHandler,
+    EINT0_IRQHandler,
+    EINT1_IRQHandler,
+    EINT2_IRQHandler,
+    EINT3_IRQHandler,
+    ADC_IRQHandler,
+    BOD_IRQHandler,
+    USB_IRQHandler,
+    CAN_IRQHandler,
+    DMA_IRQHandler,
+    I2S_IRQHandler,
+    ENET_IRQHandler,
+    RIT_IRQHandler,
+    MCPWM_IRQHandler,
+    QEI_IRQHandler,
+    PLL1_IRQHandler,
+    USBActivity_IRQHandler,
+    CANActivity_IRQHandler,
+};
+
+AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int *pulSrc = (unsigned int*) romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
+}
+
+AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
+}
+
+AFTER_VECTORS void ResetISR(void) {
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+    
+    SectionTableAddr = &__data_section_table;
+    
+    while (SectionTableAddr < &__data_section_table_end) {
+        LoadAddr = *SectionTableAddr++;
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+    while (SectionTableAddr < &__bss_section_table_end) {
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+    
+    SystemInit();
+    __libc_init_array();
+    main();
+    while (1) {;}
+}
+
+AFTER_VECTORS void NMI_Handler       (void) {}
+AFTER_VECTORS void HardFault_Handler (void) {}
+AFTER_VECTORS void MemManage_Handler (void) {}
+AFTER_VECTORS void BusFault_Handler  (void) {}
+AFTER_VECTORS void UsageFault_Handler(void) {}
+AFTER_VECTORS void SVCall_Handler    (void) {}
+AFTER_VECTORS void DebugMon_Handler  (void) {}
+AFTER_VECTORS void PendSV_Handler    (void) {}
+AFTER_VECTORS void SysTick_Handler   (void) {}
+AFTER_VECTORS void IntDefaultHandler (void) {}
+
+int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
+}
+
+#include <stdlib.h>
+
+void *operator new(size_t size)  {return malloc(size);}
+void *operator new[](size_t size){return malloc(size);}
+
+void operator delete(void *p)   {free(p);}
+void operator delete[](void *p) {free(p);}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/LPC1768.ld	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,212 @@
+/* Linker script for mbed LPC1768
+ *
+ * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ *  Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(__cs3_reset_cortex_m)
+SEARCH_DIR(.)
+
+/*
+ram ORIGIN: 8_byte_aligned(49 vect * 4 bytes) =  8_byte_aligned(0xC4) = 0xC8
+ram LENGTH: 32KB - 0xC8 = 0x7F38
+*/
+MEMORY
+{
+  rom (rx)  : ORIGIN = 0x00000000, LENGTH = 512K
+  
+  ram (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38
+  
+  ram1(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
+  ram2(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_cortex_m)
+EXTERN(__cs3_interrupt_vector_cortex_m)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __cs3_region_start_rom = .;
+    *(.cs3.region-head.rom)
+    __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
+    *(.cs3.interrupt_vector)
+    /* Make sure we pulled in an interrupt vector.  */
+    ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
+    *(.rom)
+    *(.rom.b)
+
+    __cs3_reset = __cs3_reset_cortex_m;
+    *(.cs3.reset)
+    /* Make sure we pulled in some reset code.  */
+    ASSERT (. != __cs3_reset, "No reset code");
+
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table)
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    . = ALIGN(4);
+    KEEP(*(.init))
+
+    . = ALIGN(4);
+    __preinit_array_start = .;
+    KEEP (*(.preinit_array))
+    __preinit_array_end = .;
+
+    . = ALIGN(4);
+    __init_array_start = .;
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    __init_array_end = .;
+
+    . = ALIGN(0x4);
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+
+    . = ALIGN(4);
+    KEEP(*(.fini))
+
+    . = ALIGN(4);
+    __fini_array_start = .;
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    __fini_array_end = .;
+
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    . = ALIGN(4);
+    __cs3_regions = .;
+    LONG (0)
+    LONG (__cs3_region_init_ram)
+    LONG (__cs3_region_start_ram)
+    LONG (__cs3_region_init_size_ram)
+    LONG (__cs3_region_zero_size_ram)
+  }
+
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >rom
+  __exidx_end = .;
+  .text.align :
+  {
+    . = ALIGN(8);
+    _etext = .;
+  } >rom
+  __cs3_region_size_rom = LENGTH(rom);
+  __cs3_region_num = 1;
+  
+  .data :
+  {
+    __cs3_region_start_ram = .;
+    *(.cs3.region-head.ram)
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    *(.ram)
+    . = ALIGN (8);
+    _edata = .;
+  } >ram AT>rom
+  .bss :
+  {
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    *(.ram.b)
+    . = ALIGN (8);
+    _end = .;
+    __end = .;
+  } >ram AT>rom
+  /* This used for USB RAM section */
+	.usb_ram (NOLOAD):
+	{
+		*.o (USB_RAM)
+	} > ram2
+  .heap (NOLOAD) :
+  {
+    *(.heap)
+  } >ram
+  .stack (__cs3_stack - __cs3_stack_size) (NOLOAD):
+  {
+    *(.stack)
+    _estack = .;
+    PROVIDE(estack = .);
+  } >ram
+
+  __cs3_region_init_ram = LOADADDR (.data);
+  __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
+  __cs3_region_zero_size_ram = _end - _edata;
+  __cs3_region_size_ram = LENGTH(ram);
+  __cs3_region_num = 1;
+
+  .stab 0 (NOLOAD) : { *(.stab) }
+  .stabstr 0 (NOLOAD) : { *(.stabstr) }
+  /* DWARF debug sections.
+   * Symbols in the DWARF debugging sections are relative to the beginning
+   * of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/startup_LPC17xx.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,204 @@
+    .equ    Stack_Size, 0x1024
+    .section ".stack", "w"
+    .align  3
+    .globl  __cs3_stack_mem
+    .globl  __cs3_stack_size
+__cs3_stack_mem:
+    .if     Stack_Size
+    .space  Stack_Size
+    .endif
+    .size   __cs3_stack_mem,  . - __cs3_stack_mem
+    .set    __cs3_stack_size, . - __cs3_stack_mem
+
+    .equ    Heap_Size,  0x8000
+    .section ".heap", "w"
+    .align  3
+    .globl  __cs3_heap_start
+    .globl  __cs3_heap_end
+__cs3_heap_start:
+    .if     Heap_Size
+    .space  Heap_Size
+    .endif
+__cs3_heap_end:
+
+
+    .section ".cs3.interrupt_vector"
+    .globl  __cs3_interrupt_vector_cortex_m
+    .type   __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+    .long   __cs3_stack
+    .long   __cs3_reset
+    .long   NMI_Handler
+    .long   HardFault_Handler
+    .long   MemManage_Handler
+    .long   BusFault_Handler
+    .long   UsageFault_Handler
+    .long   0
+    .long   0
+    .long   0
+    .long   0
+    .long   SVC_Handler
+    .long   DebugMon_Handler
+    .long   0
+    .long   PendSV_Handler
+    .long   SysTick_Handler
+
+    .long   WDT_IRQHandler
+    .long   TIMER0_IRQHandler
+    .long   TIMER1_IRQHandler
+    .long   TIMER2_IRQHandler
+    .long   TIMER3_IRQHandler
+    .long   UART0_IRQHandler
+    .long   UART1_IRQHandler
+    .long   UART2_IRQHandler
+    .long   UART3_IRQHandler
+    .long   PWM1_IRQHandler
+    .long   I2C0_IRQHandler
+    .long   I2C1_IRQHandler
+    .long   I2C2_IRQHandler
+    .long   SPI_IRQHandler
+    .long   SSP0_IRQHandler
+    .long   SSP1_IRQHandler
+    .long   PLL0_IRQHandler
+    .long   RTC_IRQHandler
+    .long   EINT0_IRQHandler
+    .long   EINT1_IRQHandler
+    .long   EINT2_IRQHandler
+    .long   EINT3_IRQHandler
+    .long   ADC_IRQHandler
+    .long   BOD_IRQHandler
+    .long   USB_IRQHandler
+    .long   CAN_IRQHandler
+    .long   DMA_IRQHandler
+    .long   I2S_IRQHandler
+    .long   ENET_IRQHandler
+    .long   RIT_IRQHandler
+    .long   MCPWM_IRQHandler
+    .long   QEI_IRQHandler
+    .long   PLL1_IRQHandler
+    .long	USBActivity_IRQHandler
+    .long 	CANActivity_IRQHandler
+
+    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+    .thumb
+
+    .section .cs3.reset,"x",%progbits
+    .thumb_func
+    .globl  __cs3_reset_cortex_m
+    .type   __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+    .fnstart
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0, =__cs3_start_c
+    BX      R0
+    .pool
+    .cantunwind
+    .fnend
+    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+    .section ".text"
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B       .
+    .size   MemManage_Handler, . - MemManage_Handler
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B       .
+    .size   DebugMon_Handler, . - DebugMon_Handler
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ     WDT_IRQHandler
+    IRQ     TIMER0_IRQHandler
+    IRQ     TIMER1_IRQHandler
+    IRQ     TIMER2_IRQHandler
+    IRQ     TIMER3_IRQHandler
+    IRQ     UART0_IRQHandler
+    IRQ     UART1_IRQHandler
+    IRQ     UART2_IRQHandler
+    IRQ     UART3_IRQHandler
+    IRQ     PWM1_IRQHandler
+    IRQ     I2C0_IRQHandler
+    IRQ     I2C1_IRQHandler
+    IRQ     I2C2_IRQHandler
+    IRQ     SPI_IRQHandler
+    IRQ     SSP0_IRQHandler
+    IRQ     SSP1_IRQHandler
+    IRQ     PLL0_IRQHandler
+    IRQ     RTC_IRQHandler
+    IRQ     EINT0_IRQHandler
+    IRQ     EINT1_IRQHandler
+    IRQ     EINT2_IRQHandler
+    IRQ     EINT3_IRQHandler
+    IRQ     ADC_IRQHandler
+    IRQ     BOD_IRQHandler
+    IRQ     USB_IRQHandler
+    IRQ     CAN_IRQHandler
+    IRQ     DMA_IRQHandler
+    IRQ     I2S_IRQHandler
+    IRQ     ENET_IRQHandler
+    IRQ     RIT_IRQHandler
+    IRQ     MCPWM_IRQHandler
+    IRQ     QEI_IRQHandler
+    IRQ     PLL1_IRQHandler
+    IRQ		USBActivity_IRQHandler
+    IRQ		CANActivity_IRQHandler
+    .end

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CS/sys.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,80 @@
+#include "cmsis.h"
+#include <sys/types.h>
+#include <errno.h>
+
+extern "C" {
+
+struct SCS3Regions {
+    unsigned long   Dummy;
+    unsigned long*  InitRam;
+    unsigned long*  StartRam;
+    unsigned long   InitSizeRam;
+    unsigned long   ZeroSizeRam;
+};
+
+extern unsigned long __cs3_regions;
+extern unsigned long __cs3_heap_start;
+
+int  main(void);
+void __libc_init_array(void);
+void exit(int ErrorCode);
+
+static void *heap_pointer = NULL;
+
+void __cs3_start_c(void) {
+    static SCS3Regions* pCS3Regions = (SCS3Regions*)&__cs3_regions;
+    unsigned long* pulDest;
+    unsigned long* pulSrc;
+    unsigned long  ByteCount;
+    unsigned long  i;
+    
+    pulSrc = pCS3Regions->InitRam;
+    pulDest = pCS3Regions->StartRam;
+    ByteCount = pCS3Regions->InitSizeRam;
+    if (pulSrc != pulDest) {
+        for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
+            *(pulDest++) = *(pulSrc++);
+        }
+    } else {
+        pulDest = (unsigned long*)(void*)((char*)pulDest + ByteCount);
+    }
+    
+    ByteCount = pCS3Regions->ZeroSizeRam;
+    for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
+        *(pulDest++) = 0;
+    }
+    
+    heap_pointer = &__cs3_heap_start;
+     __libc_init_array();
+    
+    exit(main());
+}
+
+int _kill(int pid, int sig) {
+    errno = EINVAL;
+    return -1;
+}
+
+void _exit(int status) {
+    exit(status);
+}
+
+int _getpid(void) {
+	return 1;
+}
+
+void *_sbrk(unsigned int incr) {
+    void *mem;
+    
+    unsigned int next = ((((unsigned int)heap_pointer + incr) + 7) & ~7);
+    if (next > __get_MSP()) {
+        mem = NULL;
+    } else {
+        mem = (void *)heap_pointer;
+    }
+    heap_pointer = (void *)next;
+    
+    return mem;
+}
+
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_IAR/LPC17xx.icf	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,40 @@
+/* [ROM] */
+define symbol __intvec_start__     = 0x00000000;
+define symbol __region_ROM_start__ = 0x00000000;
+define symbol __CRP_start__        = 0x000002FC;
+define symbol __CRP_end__          = 0x000002FF;
+define symbol __region_ROM_end__   = 0x0007FFFF;
+
+/* [RAM] Vector table dynamic copy: 8_byte_aligned(49 vect * 4 bytes) =  8_byte_aligned(0xC4) = 0xC8*/
+define symbol __NVIC_start__       = 0x10000000;
+define symbol __NVIC_end__         = 0x100000C7;
+define symbol __region_RAM_start__ = 0x100000C8;
+define symbol __region_RAM_end__   = 0x1000FFDF;
+define symbol _AHB_RAM_start__     = 0x2007C000;
+define symbol _AHB_RAM_end__       = 0x20083FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+
+define region ROM_region     = mem:[from __region_ROM_start__   to __region_ROM_end__] - mem:[from  __CRP_start__ to __CRP_end__];
+define region CRP_region     = mem:[from  __CRP_start__ to __CRP_end__];
+
+define region RAM_region     = mem:[from __region_RAM_start__   to __region_RAM_end__];
+define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__   = 0x800;
+define symbol __size_heap__     = 0x800;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { section .intvec };
+place at address mem:0x2FC { section CRPKEY };
+place in ROM_region     { readonly };
+place in RAM_region     { readwrite, block STACKHEAP };
+place in AHB_RAM_region { section USB_RAM };
+place in CRP_region     { section .crp };

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_IAR/startup_LPC17xx.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,375 @@
+;/*****************************************************************************
+; * @file:    startup_LPC17xx.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; *           for the NXP LPC17xx Device Series
+; * @version: V1.03
+; * @date:    09. February 2010
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (C) 2010 ARM Limited. All rights reserved.
+; *
+; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD     WDT_IRQHandler            ; 16: Watchdog Timer
+        DCD     TIMER0_IRQHandler         ; 17: Timer0
+        DCD     TIMER1_IRQHandler         ; 18: Timer1
+        DCD     TIMER2_IRQHandler         ; 19: Timer2
+        DCD     TIMER3_IRQHandler         ; 20: Timer3
+        DCD     UART0_IRQHandler          ; 21: UART0
+        DCD     UART1_IRQHandler          ; 22: UART1
+        DCD     UART2_IRQHandler          ; 23: UART2
+        DCD     UART3_IRQHandler          ; 24: UART3
+        DCD     PWM1_IRQHandler           ; 25: PWM1
+        DCD     I2C0_IRQHandler           ; 26: I2C0
+        DCD     I2C1_IRQHandler           ; 27: I2C1
+        DCD     I2C2_IRQHandler           ; 28: I2C2
+        DCD     SPI_IRQHandler            ; 29: SPI
+        DCD     SSP0_IRQHandler           ; 30: SSP0
+        DCD     SSP1_IRQHandler           ; 31: SSP1
+        DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
+        DCD     RTC_IRQHandler            ; 33: Real Time Clock
+        DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
+        DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
+        DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
+        DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
+        DCD     ADC_IRQHandler            ; 38: A/D Converter
+        DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
+        DCD     USB_IRQHandler            ; 40: USB
+        DCD     CAN_IRQHandler            ; 41: CAN
+        DCD     DMA_IRQHandler            ; 42: General Purpose DMA
+        DCD     I2S_IRQHandler            ; 43: I2S
+        DCD     ENET_IRQHandler           ; 44: Ethernet
+        DCD     RIT_IRQHandler            ; 45: Repetitive Interrupt Timer
+        DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
+        DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
+        DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
+        DCD			USBActivity_IRQHandler	  ; 49: USB Activity Interrupt
+        DCD			CANActivity_IRQHandler	  ; 50: CAN Activity Interrupt
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WDT_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WDT_IRQHandler
+        B WDT_IRQHandler
+
+        PUBWEAK TIMER0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER0_IRQHandler
+        B TIMER0_IRQHandler
+
+        PUBWEAK TIMER1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER1_IRQHandler
+        B TIMER1_IRQHandler
+
+        PUBWEAK TIMER2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER2_IRQHandler
+        B TIMER2_IRQHandler
+
+        PUBWEAK TIMER3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIMER3_IRQHandler
+        B TIMER3_IRQHandler
+
+        PUBWEAK UART0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART0_IRQHandler
+        B UART0_IRQHandler
+
+        PUBWEAK UART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART1_IRQHandler
+        B UART1_IRQHandler
+
+        PUBWEAK UART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART2_IRQHandler
+        B UART2_IRQHandler
+
+        PUBWEAK UART3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART3_IRQHandler
+        B UART3_IRQHandler
+
+        PUBWEAK PWM1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PWM1_IRQHandler
+        B PWM1_IRQHandler
+
+        PUBWEAK I2C0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C0_IRQHandler
+        B I2C0_IRQHandler
+
+        PUBWEAK I2C1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C1_IRQHandler
+        B I2C1_IRQHandler
+
+        PUBWEAK I2C2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2C2_IRQHandler
+        B I2C2_IRQHandler
+
+        PUBWEAK SPI_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI_IRQHandler
+        B SPI_IRQHandler
+
+        PUBWEAK SSP0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SSP0_IRQHandler
+        B SSP0_IRQHandler
+
+        PUBWEAK SSP1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SSP1_IRQHandler
+        B SSP1_IRQHandler
+
+        PUBWEAK PLL0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PLL0_IRQHandler
+        B PLL0_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK EINT0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EINT0_IRQHandler
+        B EINT0_IRQHandler
+
+        PUBWEAK EINT1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EINT1_IRQHandler
+        B EINT1_IRQHandler
+
+        PUBWEAK EINT2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EINT2_IRQHandler
+        B EINT2_IRQHandler
+
+        PUBWEAK EINT3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EINT3_IRQHandler
+        B EINT3_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC_IRQHandler
+        B ADC_IRQHandler
+
+        PUBWEAK BOD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+BOD_IRQHandler
+        B BOD_IRQHandler
+
+        PUBWEAK USB_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USB_IRQHandler
+        B USB_IRQHandler
+
+        PUBWEAK CAN_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CAN_IRQHandler
+        B CAN_IRQHandler
+
+        PUBWEAK DMA_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DMA_IRQHandler
+        B DMA_IRQHandler
+
+        PUBWEAK I2S_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+I2S_IRQHandler
+        B I2S_IRQHandler
+
+        PUBWEAK ENET_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ENET_IRQHandler
+        B ENET_IRQHandler
+
+        PUBWEAK RIT_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RIT_IRQHandler
+        B RIT_IRQHandler
+
+        PUBWEAK MCPWM_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+MCPWM_IRQHandler
+        B MCPWM_IRQHandler
+
+        PUBWEAK QEI_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+QEI_IRQHandler
+        B QEI_IRQHandler
+
+        PUBWEAK PLL1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PLL1_IRQHandler
+        B PLL1_IRQHandler
+
+        PUBWEAK USBActivity_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USBActivity_IRQHandler
+        B USBActivity_IRQHandler
+
+        PUBWEAK CANActivity_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CANActivity_IRQHandler
+        B CANActivity_IRQHandler
+
+#ifndef SRAM
+        SECTION .crp:CODE:ROOT(2)
+        DATA
+/* Code Read Protection
+CRP1    0x12345678 - Write to RAM command can not access RAM below 0x10000200.
+                   - Read Memory command: disabled.
+                   - Copy RAM to Flash command: cannot write to Sector 0.
+                   - "Go" command: disabled.
+                   - Erase sector(s) command: can erase any individual sector except 
+                   	 sector 0 only, or can erase all sectors at once.
+                   - Compare command: disabled
+CRP2    0x87654321 - Write to RAM command: disabled.
+                   - Copy RAM to Flash: disabled.
+                   - Erase command: only allows erase of all sectors.
+CRP3    0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+                     by pulling PIO0_1 LOW is disabled if a valid user code is
+                     present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+	DCD	0xFFFFFFFF
+#endif
+        END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * A generic CMSIS include header, pulling in LPC1768 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC17xx.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,32 @@
+/* mbed Microcontroller Library - cmsis_nvic for LCP1768
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+#include "cmsis_nvic.h"
+
+#define NVIC_NUM_VECTORS          (16 + 33)     // CORE + MCU Peripherals
+#define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0)       // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + 16];
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/cmsis_nvic.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,23 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,584 @@
+/**************************************************************************//**
+ * @file     system_LPC17xx.c
+ * @brief    CMSIS Cortex-M3 Device System Source File for
+ *           NXP LPC17xx Device Series
+ * @version  V1.11
+ * @date     21. June 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC17xx.h"
+
+
+/** @addtogroup LPC17xx_System
+ * @{
+ */
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+//   <h> System Controls and Status Register (SCS)
+//     <o1.4>    OSCRANGE: Main Oscillator Range Select
+//                     <0=>  1 MHz to 20 MHz
+//                     <1=> 15 MHz to 25 MHz
+//     <e1.5>       OSCEN: Main Oscillator Enable
+//     </e>
+//   </h>
+//
+//   <h> Clock Source Select Register (CLKSRCSEL)
+//     <o2.0..1>   CLKSRC: PLL Clock Source Selection
+//                     <0=> Internal RC oscillator
+//                     <1=> Main oscillator
+//                     <2=> RTC oscillator
+//   </h>
+//
+//   <e3> PLL0 Configuration (Main PLL)
+//     <h> PLL0 Configuration Register (PLL0CFG)
+//                     <i> F_cco0 = (2 * M * F_in) / N
+//                     <i> F_in must be in the range of 32 kHz to 50 MHz
+//                     <i> F_cco0 must be in the range of 275 MHz to 550 MHz
+//       <o4.0..14>  MSEL: PLL Multiplier Selection
+//                     <6-32768><#-1>
+//                     <i> M Value
+//       <o4.16..23> NSEL: PLL Divider Selection
+//                     <1-256><#-1>
+//                     <i> N Value
+//     </h>
+//   </e>
+//
+//   <e5> PLL1 Configuration (USB PLL)
+//     <h> PLL1 Configuration Register (PLL1CFG)
+//                     <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
+//                     <i> F_cco1 = F_osc * M * 2 * P
+//                     <i> F_cco1 must be in the range of 156 MHz to 320 MHz
+//       <o6.0..4>   MSEL: PLL Multiplier Selection
+//                     <1-32><#-1>
+//                     <i> M Value (for USB maximum value is 4)
+//       <o6.5..6>   PSEL: PLL Divider Selection
+//                     <0=> 1
+//                     <1=> 2
+//                     <2=> 4
+//                     <3=> 8
+//                     <i> P Value
+//     </h>
+//   </e>
+//
+//   <h> CPU Clock Configuration Register (CCLKCFG)
+//     <o7.0..7>  CCLKSEL: Divide Value for CPU Clock from PLL0
+//                     <1-256><#-1>
+//   </h>
+//
+//   <h> USB Clock Configuration Register (USBCLKCFG)
+//     <o8.0..3>   USBSEL: Divide Value for USB Clock from PLL0
+//                     <0-15>
+//                     <i> Divide is USBSEL + 1
+//   </h>
+//
+//   <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
+//     <o9.0..1>    PCLK_WDT: Peripheral Clock Selection for WDT
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.2..3>    PCLK_TIMER0: Peripheral Clock Selection for TIMER0
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.4..5>    PCLK_TIMER1: Peripheral Clock Selection for TIMER1
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.6..7>    PCLK_UART0: Peripheral Clock Selection for UART0
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.8..9>    PCLK_UART1: Peripheral Clock Selection for UART1
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.12..13>  PCLK_PWM1: Peripheral Clock Selection for PWM1
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.14..15>  PCLK_I2C0: Peripheral Clock Selection for I2C0
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.16..17>  PCLK_SPI: Peripheral Clock Selection for SPI
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.20..21>  PCLK_SSP1: Peripheral Clock Selection for SSP1
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.22..23>  PCLK_DAC: Peripheral Clock Selection for DAC
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.24..25>  PCLK_ADC: Peripheral Clock Selection for ADC
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o9.26..27>  PCLK_CAN1: Peripheral Clock Selection for CAN1
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 6
+//     <o9.28..29>  PCLK_CAN2: Peripheral Clock Selection for CAN2
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 6
+//     <o9.30..31>  PCLK_ACF: Peripheral Clock Selection for ACF
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 6
+//   </h>
+//
+//   <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
+//     <o10.0..1>   PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.2..3>   PCLK_GPIO: Peripheral Clock Selection for GPIOs
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.4..5>   PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.6..7>   PCLK_I2C1: Peripheral Clock Selection for I2C1
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//     <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
+//                     <0=> Pclk = Cclk / 4
+//                     <1=> Pclk = Cclk
+//                     <2=> Pclk = Cclk / 2
+//                     <3=> Pclk = Hclk / 8
+//   </h>
+//
+//   <h> Power Control for Peripherals Register (PCONP)
+//     <o11.1>      PCTIM0: Timer/Counter 0 power/clock enable
+//     <o11.2>      PCTIM1: Timer/Counter 1 power/clock enable
+//     <o11.3>      PCUART0: UART 0 power/clock enable
+//     <o11.4>      PCUART1: UART 1 power/clock enable
+//     <o11.6>      PCPWM1: PWM 1 power/clock enable
+//     <o11.7>      PCI2C0: I2C interface 0 power/clock enable
+//     <o11.8>      PCSPI: SPI interface power/clock enable
+//     <o11.9>      PCRTC: RTC power/clock enable
+//     <o11.10>     PCSSP1: SSP interface 1 power/clock enable
+//     <o11.12>     PCAD: A/D converter power/clock enable
+//     <o11.13>     PCCAN1: CAN controller 1 power/clock enable
+//     <o11.14>     PCCAN2: CAN controller 2 power/clock enable
+//     <o11.15>     PCGPIO: GPIOs power/clock enable
+//     <o11.16>     PCRIT: Repetitive interrupt timer power/clock enable
+//     <o11.17>     PCMC: Motor control PWM power/clock enable
+//     <o11.18>     PCQEI: Quadrature encoder interface power/clock enable
+//     <o11.19>     PCI2C1: I2C interface 1 power/clock enable
+//     <o11.21>     PCSSP0: SSP interface 0 power/clock enable
+//     <o11.22>     PCTIM2: Timer 2 power/clock enable
+//     <o11.23>     PCTIM3: Timer 3 power/clock enable
+//     <o11.24>     PCUART2: UART 2 power/clock enable
+//     <o11.25>     PCUART3: UART 3 power/clock enable
+//     <o11.26>     PCI2C2: I2C interface 2 power/clock enable
+//     <o11.27>     PCI2S: I2S interface power/clock enable
+//     <o11.29>     PCGPDMA: GP DMA function power/clock enable
+//     <o11.30>     PCENET: Ethernet block power/clock enable
+//     <o11.31>     PCUSB: USB interface power/clock enable
+//   </h>
+//
+//   <h> Clock Output Configuration Register (CLKOUTCFG)
+//     <o12.0..3>   CLKOUTSEL: Selects clock source for CLKOUT
+//                     <0=> CPU clock
+//                     <1=> Main oscillator
+//                     <2=> Internal RC oscillator
+//                     <3=> USB clock
+//                     <4=> RTC oscillator
+//     <o12.4..7>   CLKOUTDIV: Selects clock divider for CLKOUT
+//                     <1-16><#-1>
+//     <o12.8>      CLKOUT_EN: CLKOUT enable control
+//   </h>
+//
+// </e>
+*/
+
+
+
+/** @addtogroup LPC17xx_System_Defines  LPC17xx System Defines
+  @{
+ */
+
+#define CLOCK_SETUP           1
+#define SCS_Val               0x00000020
+#define CLKSRCSEL_Val         0x00000001
+#define PLL0_SETUP            1
+
+#ifdef MCB1700
+#    define PLL0CFG_Val           0x00050063
+#    define PLL1_SETUP            1
+#    define PLL1CFG_Val           0x00000023
+#    define CCLKCFG_Val           0x00000003
+#    define USBCLKCFG_Val         0x00000000
+#else
+#    define PLL0CFG_Val           0x0000000B
+#    define PLL1_SETUP            0
+#    define PLL1CFG_Val           0x00000000
+#    define CCLKCFG_Val           0x00000002
+#    define USBCLKCFG_Val         0x00000005
+#endif
+
+#define PCLKSEL0_Val          0x00000000
+#define PCLKSEL1_Val          0x00000000
+#define PCONP_Val             0x042887DE
+#define CLKOUTCFG_Val         0x00000000
+
+
+/*--------------------- Flash Accelerator Configuration ----------------------
+//
+// <e> Flash Accelerator Configuration
+//   <o1.12..15> FLASHTIM: Flash Access Time
+//               <0=> 1 CPU clock (for CPU clock up to 20 MHz)
+//               <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
+//               <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
+//               <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
+//               <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
+//               <5=> 6 CPU clocks (for any CPU clock)
+// </e>
+*/
+#define FLASH_SETUP           1
+#define FLASHCFG_Val          0x0000303A
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+  Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask)                     (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SCS_Val),       ~0x00000030))
+   #error "SCS: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
+   #error "CLKSRCSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((PLL0CFG_Val),   ~0x00FF7FFF))
+   #error "PLL0CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
+   #error "PLL1CFG: Invalid values of reserved bits!"
+#endif
+
+#if (PLL0_SETUP)            /* if PLL0 is used */
+  #if (CCLKCFG_Val < 2)     /* CCLKSEL must be greater then 1 */
+    #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
+  #endif
+#endif
+
+#if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
+   #error "CCLKCFG: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
+   #error "USBCLKCFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL0_Val),   0x000C0C00))
+   #error "PCLKSEL0: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL1_Val),   0x03000300))
+   #error "PCLKSEL1: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCONP_Val),      0x10100821))
+   #error "PCONP: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
+   #error "CLKOUTCFG: Invalid values of reserved bits!"
+#endif
+
+/* Flash Accelerator Configuration -------------------------------------------*/
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
+   #error "FLASHCFG: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL        (12000000UL)        /* Oscillator frequency               */
+#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
+#define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */
+#define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
+
+
+/* F_cco0 = (2 * M * F_in) / N  */
+#define __M               (((PLL0CFG_Val      ) & 0x7FFF) + 1)
+#define __N               (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
+#define __FCCO(__F_IN)    ((2ULL * __M * __F_IN) / __N)
+#define __CCLK_DIV        (((CCLKCFG_Val      ) & 0x00FF) + 1)
+
+/* Determine core clock frequency according to settings */
+ #if (PLL0_SETUP)
+    #if   ((CLKSRCSEL_Val & 0x03) == 1)
+        #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
+    #elif ((CLKSRCSEL_Val & 0x03) == 2)
+        #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
+    #else
+        #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
+    #endif
+ #else
+    #if   ((CLKSRCSEL_Val & 0x03) == 1)
+        #define __CORE_CLK (OSC_CLK         / __CCLK_DIV)
+    #elif ((CLKSRCSEL_Val & 0x03) == 2)
+        #define __CORE_CLK (RTC_CLK         / __CCLK_DIV)
+    #else
+        #define __CORE_CLK (IRC_OSC         / __CCLK_DIV)
+    #endif
+ #endif
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup LPC17xx_System_Public_Variables  LPC17xx System Public Variables
+  @{
+ */
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup LPC17xx_System_Public_Functions  LPC17xx System Public Functions
+  @{
+ */
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  /* Determine clock frequency according to clock register values             */
+  if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
+    switch (LPC_SC->CLKSRCSEL & 0x03) {
+      case 0:                                /* Int. RC oscillator => PLL0    */
+      case 3:                                /* Reserved, default to Int. RC  */
+        SystemCoreClock = (IRC_OSC *
+                          ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
+                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)       /
+                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+        break;
+      case 1:                                /* Main oscillator => PLL0       */
+        SystemCoreClock = (OSC_CLK *
+                          ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
+                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)       /
+                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+        break;
+      case 2:                                /* RTC oscillator => PLL0        */
+        SystemCoreClock = (RTC_CLK *
+                          ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
+                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)       /
+                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+        break;
+    }
+  } else {
+    switch (LPC_SC->CLKSRCSEL & 0x03) {
+      case 0:                                /* Int. RC oscillator => PLL0    */
+      case 3:                                /* Reserved, default to Int. RC  */
+        SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+        break;
+      case 1:                                /* Main oscillator => PLL0       */
+        SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+        break;
+      case 2:                                /* RTC oscillator => PLL0        */
+        SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+        break;
+    }
+  }
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+#if (CLOCK_SETUP)                       /* Clock Setup                        */
+  LPC_SC->SCS       = SCS_Val;
+  if (LPC_SC->SCS & (1 << 5)) {             /* If Main Oscillator is enabled  */
+    while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */
+  }
+
+  LPC_SC->CCLKCFG   = CCLKCFG_Val;      /* Setup Clock Divider                */
+  /* Periphral clock must be selected before PLL0 enabling and connecting
+   * - according errata.lpc1768-16.March.2010 -
+   */
+  LPC_SC->PCLKSEL0  = PCLKSEL0_Val;     /* Peripheral Clock Selection         */
+  LPC_SC->PCLKSEL1  = PCLKSEL1_Val;
+
+#if (PLL0_SETUP)
+  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for PLL0       */
+
+  LPC_SC->PLL0CFG   = PLL0CFG_Val;      /* configure PLL0                     */
+  LPC_SC->PLL0FEED  = 0xAA;
+  LPC_SC->PLL0FEED  = 0x55;
+
+  LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
+  LPC_SC->PLL0FEED  = 0xAA;
+  LPC_SC->PLL0FEED  = 0x55;
+  while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0                    */
+
+  LPC_SC->PLL0CON   = 0x03;             /* PLL0 Enable & Connect              */
+  LPC_SC->PLL0FEED  = 0xAA;
+  LPC_SC->PLL0FEED  = 0x55;
+  while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
+#endif
+
+#if (PLL1_SETUP)
+  LPC_SC->PLL1CFG   = PLL1CFG_Val;
+  LPC_SC->PLL1FEED  = 0xAA;
+  LPC_SC->PLL1FEED  = 0x55;
+
+  LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
+  LPC_SC->PLL1FEED  = 0xAA;
+  LPC_SC->PLL1FEED  = 0x55;
+  while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */
+
+  LPC_SC->PLL1CON   = 0x03;             /* PLL1 Enable & Connect              */
+  LPC_SC->PLL1FEED  = 0xAA;
+  LPC_SC->PLL1FEED  = 0x55;
+  while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
+#else
+  LPC_SC->USBCLKCFG = USBCLKCFG_Val;    /* Setup USB Clock Divider            */
+#endif
+
+  LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */
+
+  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
+#endif
+
+#if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
+  LPC_SC->FLASHCFG  = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
+#endif
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,60 @@
+/******************************************************************************
+ * @file:    system_LPC17xx.h
+ * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ *           for the NXP LPC17xx Device Series 
+ * @version: V1.02
+ * @date:    27. July 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC17xx_H
+#define __SYSTEM_LPC17xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC17xx_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/LPC23xx.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,864 @@
+/* mbed Microcontroller Library - LPC23xx CMSIS-like structs
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ * 
+ * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
+ */
+
+#ifndef __LPC23xx_H
+#define __LPC23xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/******  LPC23xx Specific Interrupt Numbers *******************************************************/
+  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
+
+  TIMER0_IRQn                   = 4,        /*!< Timer0 Interrupt                                 */
+  TIMER1_IRQn                   = 5,        /*!< Timer1 Interrupt                                 */
+  UART0_IRQn                    = 6,        /*!< UART0 Interrupt                                  */
+  UART1_IRQn                    = 7,        /*!< UART1 Interrupt                                  */
+  PWM1_IRQn                     = 8,        /*!< PWM1 Interrupt                                   */
+  I2C0_IRQn                     = 9,        /*!< I2C0 Interrupt                                   */
+  SPI_IRQn                      = 10,       /*!< SPI Interrupt                                    */
+  SSP0_IRQn                     = 10,       /*!< SSP0 Interrupt                                   */
+  SSP1_IRQn                     = 11,       /*!< SSP1 Interrupt                                   */
+  PLL0_IRQn                     = 12,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
+  RTC_IRQn                      = 13,       /*!< Real Time Clock Interrupt                        */
+  EINT0_IRQn                    = 14,       /*!< External Interrupt 0 Interrupt                   */
+  EINT1_IRQn                    = 15,       /*!< External Interrupt 1 Interrupt                   */
+  EINT2_IRQn                    = 16,       /*!< External Interrupt 2 Interrupt                   */
+  EINT3_IRQn                    = 17,       /*!< External Interrupt 3 Interrupt                   */
+  ADC_IRQn                      = 18,       /*!< A/D Converter Interrupt                          */
+  I2C1_IRQn                     = 19,       /*!< I2C1 Interrupt                                   */
+  BOD_IRQn                      = 20,       /*!< Brown-Out Detect Interrupt                       */
+  ENET_IRQn                     = 21,       /*!< Ethernet Interrupt                               */
+  USB_IRQn                      = 22,       /*!< USB Interrupt                                    */
+  CAN_IRQn                      = 23,       /*!< CAN Interrupt                                    */
+  MIC_IRQn                      = 24,       /*!< Multimedia Interface Controler                   */
+  DMA_IRQn                      = 25,       /*!< General Purpose DMA Interrupt                    */
+  TIMER2_IRQn                   = 26,       /*!< Timer2 Interrupt                                 */
+  TIMER3_IRQn                   = 27,       /*!< Timer3 Interrupt                                 */
+  UART2_IRQn                    = 28,       /*!< UART2 Interrupt                                  */
+  UART3_IRQn                    = 29,       /*!< UART3 Interrupt                                  */
+  I2C2_IRQn                     = 30,       /*!< I2C2 Interrupt                                   */
+  I2S_IRQn                      = 31,       /*!< I2S Interrupt                                    */
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the ARM7 Processor and Core Peripherals */
+#define __MPU_PRESENT             0         /*!< MPU present or not                               */
+#define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+
+
+#include <core_arm7.h>
+#include "system_LPC23xx.h"                 /* System Header                                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+#if defined ( __CC_ARM   )
+  #pragma anon_unions
+#endif
+
+/*------------- Vector Interupt Controler (VIC) ------------------------------*/
+typedef struct
+{
+  __I  uint32_t IRQStatus;
+  __I  uint32_t FIQStatus;
+  __I  uint32_t RawIntr;
+  __IO uint32_t IntSelect;
+  __IO uint32_t IntEnable;
+  __O  uint32_t IntEnClr;
+  __IO uint32_t SoftInt;
+  __O  uint32_t SoftIntClr;
+  __IO uint32_t Protection;
+  __IO uint32_t SWPriorityMask;
+  __IO uint32_t RESERVED0[54];
+  __IO uint32_t VectAddr[32];
+  __IO uint32_t RESERVED1[32];
+  __IO uint32_t VectPriority[32];
+  __IO uint32_t RESERVED2[800];
+  __IO uint32_t Address;
+} LPC_VIC_TypeDef;
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t MAMCR;
+  __IO uint32_t MAMTIM;
+       uint32_t RESERVED0[14];
+  __IO uint32_t MEMMAP;
+       uint32_t RESERVED1[15];
+  __IO uint32_t PLL0CON;                /* Clocking and Power Control         */
+  __IO uint32_t PLL0CFG;
+  __I  uint32_t PLL0STAT;
+  __O  uint32_t PLL0FEED;
+       uint32_t RESERVED2[12];
+  __IO uint32_t PCON;
+  __IO uint32_t PCONP;
+       uint32_t RESERVED3[15];
+  __IO uint32_t CCLKCFG;
+  __IO uint32_t USBCLKCFG;
+  __IO uint32_t CLKSRCSEL;
+       uint32_t RESERVED4[12];
+  __IO uint32_t EXTINT;                 /* External Interrupts                */
+  __IO uint32_t INTWAKE;
+  __IO uint32_t EXTMODE;
+  __IO uint32_t EXTPOLAR;
+       uint32_t RESERVED6[12];
+  __IO uint32_t RSID;                   /* Reset                              */
+  __IO uint32_t CSPR;
+  __IO uint32_t AHBCFG1;
+  __IO uint32_t AHBCFG2;
+       uint32_t RESERVED7[4];
+  __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */
+  __IO uint32_t IRCTRIM;                /* Clock Dividers                     */
+  __IO uint32_t PCLKSEL0;
+  __IO uint32_t PCLKSEL1;
+       uint32_t RESERVED8[4];
+  __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */
+       uint32_t RESERVED9;
+//  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */
+ } LPC_SC_TypeDef;
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+  __IO uint32_t PINSEL0;
+  __IO uint32_t PINSEL1;
+  __IO uint32_t PINSEL2;
+  __IO uint32_t PINSEL3;
+  __IO uint32_t PINSEL4;
+  __IO uint32_t PINSEL5;
+  __IO uint32_t PINSEL6;
+  __IO uint32_t PINSEL7;
+  __IO uint32_t PINSEL8;
+  __IO uint32_t PINSEL9;
+  __IO uint32_t PINSEL10;
+       uint32_t RESERVED0[5];
+  __IO uint32_t PINMODE0;
+  __IO uint32_t PINMODE1;
+  __IO uint32_t PINMODE2;
+  __IO uint32_t PINMODE3;
+  __IO uint32_t PINMODE4;
+  __IO uint32_t PINMODE5;
+  __IO uint32_t PINMODE6;
+  __IO uint32_t PINMODE7;
+  __IO uint32_t PINMODE8;
+  __IO uint32_t PINMODE9;
+  __IO uint32_t PINMODE_OD0;
+  __IO uint32_t PINMODE_OD1;
+  __IO uint32_t PINMODE_OD2;
+  __IO uint32_t PINMODE_OD3;
+  __IO uint32_t PINMODE_OD4;
+} LPC_PINCON_TypeDef;
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+  __IO uint32_t FIODIR;
+       uint32_t RESERVED0[3];
+  __IO uint32_t FIOMASK;
+  __IO uint32_t FIOPIN;
+  __IO uint32_t FIOSET;
+  __O  uint32_t FIOCLR;
+} LPC_GPIO_TypeDef;
+
+typedef struct
+{
+  __I  uint32_t IntStatus;
+  __I  uint32_t IO0IntStatR;
+  __I  uint32_t IO0IntStatF;
+  __O  uint32_t IO0IntClr;
+  __IO uint32_t IO0IntEnR;
+  __IO uint32_t IO0IntEnF;
+       uint32_t RESERVED0[3];
+  __I  uint32_t IO2IntStatR;
+  __I  uint32_t IO2IntStatF;
+  __O  uint32_t IO2IntClr;
+  __IO uint32_t IO2IntEnR;
+  __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t IR;
+  __IO uint32_t TCR;
+  __IO uint32_t TC;
+  __IO uint32_t PR;
+  __IO uint32_t PC;
+  __IO uint32_t MCR;
+  __IO uint32_t MR0;
+  __IO uint32_t MR1;
+  __IO uint32_t MR2;
+  __IO uint32_t MR3;
+  __IO uint32_t CCR;
+  __I  uint32_t CR0;
+  __I  uint32_t CR1;
+       uint32_t RESERVED0[2];
+  __IO uint32_t EMR;
+       uint32_t RESERVED1[12];
+  __IO uint32_t CTCR;
+} LPC_TIM_TypeDef;
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+  __IO uint32_t IR;
+  __IO uint32_t TCR;
+  __IO uint32_t TC;
+  __IO uint32_t PR;
+  __IO uint32_t PC;
+  __IO uint32_t MCR;
+  __IO uint32_t MR0;
+  __IO uint32_t MR1;
+  __IO uint32_t MR2;
+  __IO uint32_t MR3;
+  __IO uint32_t CCR;
+  __I  uint32_t CR0;
+  __I  uint32_t CR1;
+  __I  uint32_t CR2;
+  __I  uint32_t CR3;
+       uint32_t RESERVED0;
+  __IO uint32_t MR4;
+  __IO uint32_t MR5;
+  __IO uint32_t MR6;
+  __IO uint32_t PCR;
+  __IO uint32_t LER;
+       uint32_t RESERVED1[7];
+  __IO uint32_t CTCR;
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+  union {
+  __I  uint8_t  RBR;
+  __O  uint8_t  THR;
+  __IO uint8_t  DLL;
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;
+  __IO uint32_t IER;
+  };
+  union {
+  __I  uint32_t IIR;
+  __O  uint8_t  FCR;
+  };
+  __IO uint8_t  LCR;
+       uint8_t  RESERVED1[7];
+  __IO uint8_t  LSR;
+       uint8_t  RESERVED2[7];
+  __IO uint8_t  SCR;
+       uint8_t  RESERVED3[3];
+  __IO uint32_t ACR;
+  __IO uint8_t  ICR;
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  FDR;
+       uint8_t  RESERVED5[7];
+  __IO uint8_t  TER;
+       uint8_t  RESERVED6[27];
+  __IO uint8_t  RS485CTRL;
+       uint8_t  RESERVED7[3];
+  __IO uint8_t  ADRMATCH;
+} LPC_UART_TypeDef;
+
+typedef struct
+{
+  union {
+  __I  uint8_t  RBR;
+  __O  uint8_t  THR;
+  __IO uint8_t  DLL;
+       uint32_t RESERVED0;
+  };
+  union {
+  __IO uint8_t  DLM;
+  __IO uint32_t IER;
+  };
+  union {
+  __I  uint32_t IIR;
+  __O  uint8_t  FCR;
+  };
+  __IO uint8_t  LCR;
+       uint8_t  RESERVED1[3];
+  __IO uint8_t  MCR;
+       uint8_t  RESERVED2[3];
+  __IO uint8_t  LSR;
+       uint8_t  RESERVED3[3];
+  __IO uint8_t  MSR;
+       uint8_t  RESERVED4[3];
+  __IO uint8_t  SCR;
+       uint8_t  RESERVED5[3];
+  __IO uint32_t ACR;
+       uint32_t RESERVED6;
+  __IO uint32_t FDR;
+       uint32_t RESERVED7;
+  __IO uint8_t  TER;
+       uint8_t  RESERVED8[27];
+  __IO uint8_t  RS485CTRL;
+       uint8_t  RESERVED9[3];
+  __IO uint8_t  ADRMATCH;
+       uint8_t  RESERVED10[3];
+  __IO uint8_t  RS485DLY;
+} LPC_UART1_TypeDef;
+
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
+typedef struct
+{
+  __IO uint32_t SPCR;
+  __I  uint32_t SPSR;
+  __IO uint32_t SPDR;
+  __IO uint32_t SPCCR;
+       uint32_t RESERVED0[3];
+  __IO uint32_t SPINT;
+} LPC_SPI_TypeDef;
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+  __IO uint32_t CR0;
+  __IO uint32_t CR1;
+  __IO uint32_t DR;
+  __I  uint32_t SR;
+  __IO uint32_t CPSR;
+  __IO uint32_t IMSC;
+  __IO uint32_t RIS;
+  __IO uint32_t MIS;
+  __IO uint32_t ICR;
+  __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+  __IO uint32_t I2CONSET;
+  __I  uint32_t I2STAT;
+  __IO uint32_t I2DAT;
+  __IO uint32_t I2ADR0;
+  __IO uint32_t I2SCLH;
+  __IO uint32_t I2SCLL;
+  __O  uint32_t I2CONCLR;
+  __IO uint32_t MMCTRL;
+  __IO uint32_t I2ADR1;
+  __IO uint32_t I2ADR2;
+  __IO uint32_t I2ADR3;
+  __I  uint32_t I2DATA_BUFFER;
+  __IO uint32_t I2MASK0;
+  __IO uint32_t I2MASK1;
+  __IO uint32_t I2MASK2;
+  __IO uint32_t I2MASK3;
+} LPC_I2C_TypeDef;
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+  __IO uint32_t I2SDAO;
+  __I  uint32_t I2SDAI;
+  __O  uint32_t I2STXFIFO;
+  __I  uint32_t I2SRXFIFO;
+  __I  uint32_t I2SSTATE;
+  __IO uint32_t I2SDMA1;
+  __IO uint32_t I2SDMA2;
+  __IO uint32_t I2SIRQ;
+  __IO uint32_t I2STXRATE;
+  __IO uint32_t I2SRXRATE;
+  __IO uint32_t I2STXBITRATE;
+  __IO uint32_t I2SRXBITRATE;
+  __IO uint32_t I2STXMODE;
+  __IO uint32_t I2SRXMODE;
+} LPC_I2S_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+  __IO uint8_t  ILR;
+       uint8_t  RESERVED0[3];
+  __IO uint8_t  CTC;
+       uint8_t  RESERVED1[3];
+  __IO uint8_t  CCR;
+       uint8_t  RESERVED2[3];
+  __IO uint8_t  CIIR;
+       uint8_t  RESERVED3[3];
+  __IO uint8_t  AMR;
+       uint8_t  RESERVED4[3];
+  __I  uint32_t CTIME0;
+  __I  uint32_t CTIME1;
+  __I  uint32_t CTIME2;
+  __IO uint8_t  SEC;
+       uint8_t  RESERVED5[3];
+  __IO uint8_t  MIN;
+       uint8_t  RESERVED6[3];
+  __IO uint8_t  HOUR;
+       uint8_t  RESERVED7[3];
+  __IO uint8_t  DOM;
+       uint8_t  RESERVED8[3];
+  __IO uint8_t  DOW;
+       uint8_t  RESERVED9[3];
+  __IO uint16_t DOY;
+       uint16_t RESERVED10;
+  __IO uint8_t  MONTH;
+       uint8_t  RESERVED11[3];
+  __IO uint16_t YEAR;
+       uint16_t RESERVED12;
+  __IO uint32_t CALIBRATION;
+  __IO uint32_t GPREG0;
+  __IO uint32_t GPREG1;
+  __IO uint32_t GPREG2;
+  __IO uint32_t GPREG3;
+  __IO uint32_t GPREG4;
+  __IO uint8_t  WAKEUPDIS;
+       uint8_t  RESERVED13[3];
+  __IO uint8_t  PWRCTRL;
+       uint8_t  RESERVED14[3];
+  __IO uint8_t  ALSEC;
+       uint8_t  RESERVED15[3];
+  __IO uint8_t  ALMIN;
+       uint8_t  RESERVED16[3];
+  __IO uint8_t  ALHOUR;
+       uint8_t  RESERVED17[3];
+  __IO uint8_t  ALDOM;
+       uint8_t  RESERVED18[3];
+  __IO uint8_t  ALDOW;
+       uint8_t  RESERVED19[3];
+  __IO uint16_t ALDOY;
+       uint16_t RESERVED20;
+  __IO uint8_t  ALMON;
+       uint8_t  RESERVED21[3];
+  __IO uint16_t ALYEAR;
+       uint16_t RESERVED22;
+} LPC_RTC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+  __IO uint8_t  WDMOD;
+       uint8_t  RESERVED0[3];
+  __IO uint32_t WDTC;
+  __O  uint8_t  WDFEED;
+       uint8_t  RESERVED1[3];
+  __I  uint32_t WDTV;
+  __IO uint32_t WDCLKSEL;
+} LPC_WDT_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+  __IO uint32_t ADCR;
+  __IO uint32_t ADGDR;
+       uint32_t RESERVED0;
+  __IO uint32_t ADINTEN;
+  __I  uint32_t ADDR0;
+  __I  uint32_t ADDR1;
+  __I  uint32_t ADDR2;
+  __I  uint32_t ADDR3;
+  __I  uint32_t ADDR4;
+  __I  uint32_t ADDR5;
+  __I  uint32_t ADDR6;
+  __I  uint32_t ADDR7;
+  __I  uint32_t ADSTAT;
+  __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+  __IO uint32_t DACR;
+  __IO uint32_t DACCTRL;
+  __IO uint16_t DACCNTVAL;
+} LPC_DAC_TypeDef;
+
+/*------------- Multimedia Card Interface (MCI) ------------------------------*/
+typedef struct
+{
+  __IO uint32_t MCIPower;               /* Power control                      */
+  __IO uint32_t MCIClock;               /* Clock control                      */
+  __IO uint32_t MCIArgument;
+  __IO uint32_t MMCCommand;
+  __I  uint32_t MCIRespCmd;
+  __I  uint32_t MCIResponse0;
+  __I  uint32_t MCIResponse1;
+  __I  uint32_t MCIResponse2;
+  __I  uint32_t MCIResponse3;
+  __IO uint32_t MCIDataTimer;
+  __IO uint32_t MCIDataLength;
+  __IO uint32_t MCIDataCtrl;
+  __I  uint32_t MCIDataCnt;
+} LPC_MCI_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+  __IO uint32_t mask[512];              /* ID Masks                           */
+} LPC_CANAF_RAM_TypeDef;
+
+typedef struct                          /* Acceptance Filter Registers        */
+{
+  __IO uint32_t AFMR;
+  __IO uint32_t SFF_sa;
+  __IO uint32_t SFF_GRP_sa;
+  __IO uint32_t EFF_sa;
+  __IO uint32_t EFF_GRP_sa;
+  __IO uint32_t ENDofTable;
+  __I  uint32_t LUTerrAd;
+  __I  uint32_t LUTerr;
+} LPC_CANAF_TypeDef;
+
+typedef struct                          /* Central Registers                  */
+{
+  __I  uint32_t CANTxSR;
+  __I  uint32_t CANRxSR;
+  __I  uint32_t CANMSR;
+} LPC_CANCR_TypeDef;
+
+typedef struct                          /* Controller Registers               */
+{
+  __IO uint32_t MOD;
+  __O  uint32_t CMR;
+  __IO uint32_t GSR;
+  __I  uint32_t ICR;
+  __IO uint32_t IER;
+  __IO uint32_t BTR;
+  __IO uint32_t EWL;
+  __I  uint32_t SR;
+  __IO uint32_t RFS;
+  __IO uint32_t RID;
+  __IO uint32_t RDA;
+  __IO uint32_t RDB;
+  __IO uint32_t TFI1;
+  __IO uint32_t TID1;
+  __IO uint32_t TDA1;
+  __IO uint32_t TDB1;
+  __IO uint32_t TFI2;
+  __IO uint32_t TID2;
+  __IO uint32_t TDA2;
+  __IO uint32_t TDB2;
+  __IO uint32_t TFI3;
+  __IO uint32_t TID3;
+  __IO uint32_t TDA3;
+  __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct                          /* Common Registers                   */
+{
+  __I  uint32_t DMACIntStat;
+  __I  uint32_t DMACIntTCStat;
+  __O  uint32_t DMACIntTCClear;
+  __I  uint32_t DMACIntErrStat;
+  __O  uint32_t DMACIntErrClr;
+  __I  uint32_t DMACRawIntTCStat;
+  __I  uint32_t DMACRawIntErrStat;
+  __I  uint32_t DMACEnbldChns;
+  __IO uint32_t DMACSoftBReq;
+  __IO uint32_t DMACSoftSReq;
+  __IO uint32_t DMACSoftLBReq;
+  __IO uint32_t DMACSoftLSReq;
+  __IO uint32_t DMACConfig;
+  __IO uint32_t DMACSync;
+} LPC_GPDMA_TypeDef;
+
+typedef struct                          /* Channel Registers                  */
+{
+  __IO uint32_t DMACCSrcAddr;
+  __IO uint32_t DMACCDestAddr;
+  __IO uint32_t DMACCLLI;
+  __IO uint32_t DMACCControl;
+  __IO uint32_t DMACCConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+  __I  uint32_t HcRevision;             /* USB Host Registers                 */
+  __IO uint32_t HcControl;
+  __IO uint32_t HcCommandStatus;
+  __IO uint32_t HcInterruptStatus;
+  __IO uint32_t HcInterruptEnable;
+  __IO uint32_t HcInterruptDisable;
+  __IO uint32_t HcHCCA;
+  __I  uint32_t HcPeriodCurrentED;
+  __IO uint32_t HcControlHeadED;
+  __IO uint32_t HcControlCurrentED;
+  __IO uint32_t HcBulkHeadED;
+  __IO uint32_t HcBulkCurrentED;
+  __I  uint32_t HcDoneHead;
+  __IO uint32_t HcFmInterval;
+  __I  uint32_t HcFmRemaining;
+  __I  uint32_t HcFmNumber;
+  __IO uint32_t HcPeriodicStart;
+  __IO uint32_t HcLSTreshold;
+  __IO uint32_t HcRhDescriptorA;
+  __IO uint32_t HcRhDescriptorB;
+  __IO uint32_t HcRhStatus;
+  __IO uint32_t HcRhPortStatus1;
+  __IO uint32_t HcRhPortStatus2;
+       uint32_t RESERVED0[40];
+  __I  uint32_t Module_ID;
+
+  __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */
+  __IO uint32_t OTGIntEn;
+  __O  uint32_t OTGIntSet;
+  __O  uint32_t OTGIntClr;
+  __IO uint32_t OTGStCtrl;
+  __IO uint32_t OTGTmr;
+       uint32_t RESERVED1[58];
+
+  __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */
+  __IO uint32_t USBDevIntEn;
+  __O  uint32_t USBDevIntClr;
+  __O  uint32_t USBDevIntSet;
+
+  __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */
+  __I  uint32_t USBCmdData;
+
+  __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */
+  __O  uint32_t USBTxData;
+  __I  uint32_t USBRxPLen;
+  __O  uint32_t USBTxPLen;
+  __IO uint32_t USBCtrl;
+  __O  uint32_t USBDevIntPri;
+
+  __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */
+  __IO uint32_t USBEpIntEn;
+  __O  uint32_t USBEpIntClr;
+  __O  uint32_t USBEpIntSet;
+  __O  uint32_t USBEpIntPri;
+
+  __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/
+  __O  uint32_t USBEpInd;
+  __IO uint32_t USBMaxPSize;
+
+  __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */
+  __O  uint32_t USBDMARClr;
+  __O  uint32_t USBDMARSet;
+       uint32_t RESERVED2[9];
+  __IO uint32_t USBUDCAH;
+  __I  uint32_t USBEpDMASt;
+  __O  uint32_t USBEpDMAEn;
+  __O  uint32_t USBEpDMADis;
+  __I  uint32_t USBDMAIntSt;
+  __IO uint32_t USBDMAIntEn;
+       uint32_t RESERVED3[2];
+  __I  uint32_t USBEoTIntSt;
+  __O  uint32_t USBEoTIntClr;
+  __O  uint32_t USBEoTIntSet;
+  __I  uint32_t USBNDDRIntSt;
+  __O  uint32_t USBNDDRIntClr;
+  __O  uint32_t USBNDDRIntSet;
+  __I  uint32_t USBSysErrIntSt;
+  __O  uint32_t USBSysErrIntClr;
+  __O  uint32_t USBSysErrIntSet;
+       uint32_t RESERVED4[15];
+
+  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
+  __O  uint32_t I2C_WO;
+  __I  uint32_t I2C_STS;
+  __IO uint32_t I2C_CTL;
+  __IO uint32_t I2C_CLKHI;
+  __O  uint32_t I2C_CLKLO;
+       uint32_t RESERVED5[823];
+
+  union {
+  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
+  __IO uint32_t OTGClkCtrl;
+  };
+  union {
+  __I  uint32_t USBClkSt;
+  __I  uint32_t OTGClkSt;
+  };
+} LPC_USB_TypeDef;
+
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+  __IO uint32_t MAC1;                   /* MAC Registers                      */
+  __IO uint32_t MAC2;
+  __IO uint32_t IPGT;
+  __IO uint32_t IPGR;
+  __IO uint32_t CLRT;
+  __IO uint32_t MAXF;
+  __IO uint32_t SUPP;
+  __IO uint32_t TEST;
+  __IO uint32_t MCFG;
+  __IO uint32_t MCMD;
+  __IO uint32_t MADR;
+  __O  uint32_t MWTD;
+  __I  uint32_t MRDD;
+  __I  uint32_t MIND;
+       uint32_t RESERVED0[2];
+  __IO uint32_t SA0;
+  __IO uint32_t SA1;
+  __IO uint32_t SA2;
+       uint32_t RESERVED1[45];
+  __IO uint32_t Command;                /* Control Registers                  */
+  __I  uint32_t Status;
+  __IO uint32_t RxDescriptor;
+  __IO uint32_t RxStatus;
+  __IO uint32_t RxDescriptorNumber;
+  __I  uint32_t RxProduceIndex;
+  __IO uint32_t RxConsumeIndex;
+  __IO uint32_t TxDescriptor;
+  __IO uint32_t TxStatus;
+  __IO uint32_t TxDescriptorNumber;
+  __IO uint32_t TxProduceIndex;
+  __I  uint32_t TxConsumeIndex;
+       uint32_t RESERVED2[10];
+  __I  uint32_t TSV0;
+  __I  uint32_t TSV1;
+  __I  uint32_t RSV;
+       uint32_t RESERVED3[3];
+  __IO uint32_t FlowControlCounter;
+  __I  uint32_t FlowControlStatus;
+       uint32_t RESERVED4[34];
+  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
+  __IO uint32_t RxFilterWoLStatus;
+  __IO uint32_t RxFilterWoLClear;
+       uint32_t RESERVED5;
+  __IO uint32_t HashFilterL;
+  __IO uint32_t HashFilterH;
+       uint32_t RESERVED6[882];
+  __I  uint32_t IntStatus;              /* Module Control Registers           */
+  __IO uint32_t IntEnable;
+  __O  uint32_t IntClear;
+  __O  uint32_t IntSet;
+       uint32_t RESERVED7;
+  __IO uint32_t PowerDown;
+       uint32_t RESERVED8;
+  __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+#if defined ( __CC_ARM   )
+  #pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* Base addresses                                                             */
+
+/* AHB Peripheral # 0 */
+
+/*
+#define FLASH_BASE            (0x00000000UL)
+#define RAM_BASE              (0x10000000UL)
+#define GPIO_BASE             (0x2009C000UL)
+#define APB0_BASE             (0x40000000UL)
+#define APB1_BASE             (0x40080000UL)
+#define AHB_BASE              (0x50000000UL)
+#define CM3_BASE              (0xE0000000UL)
+*/
+
+// TODO - #define VIC_BASE_ADDR	0xFFFFF000
+
+#define LPC_WDT_BASE              (0xE0000000)
+#define LPC_TIM0_BASE             (0xE0004000)
+#define LPC_TIM1_BASE             (0xE0008000)
+#define LPC_UART0_BASE            (0xE000C000)
+#define LPC_UART1_BASE            (0xE0010000)
+#define LPC_PWM1_BASE             (0xE0018000)
+#define LPC_I2C0_BASE             (0xE001C000)
+#define LPC_SPI_BASE              (0xE0020000)
+#define LPC_RTC_BASE              (0xE0024000)
+#define LPC_GPIOINT_BASE          (0xE0028080)
+#define LPC_PINCON_BASE           (0xE002C000)
+#define LPC_SSP1_BASE             (0xE0030000)
+#define LPC_ADC_BASE              (0xE0034000)
+#define LPC_CANAF_RAM_BASE        (0xE0038000)
+#define LPC_CANAF_BASE            (0xE003C000)
+#define LPC_CANCR_BASE            (0xE0040000)
+#define LPC_CAN1_BASE             (0xE0044000)
+#define LPC_CAN2_BASE             (0xE0048000)
+#define LPC_I2C1_BASE             (0xE005C000)
+#define LPC_SSP0_BASE             (0xE0068000)
+#define LPC_DAC_BASE              (0xE006C000)
+#define LPC_TIM2_BASE             (0xE0070000)
+#define LPC_TIM3_BASE             (0xE0074000)
+#define LPC_UART2_BASE            (0xE0078000)
+#define LPC_UART3_BASE            (0xE007C000)
+#define LPC_I2C2_BASE             (0xE0080000)
+#define LPC_I2S_BASE              (0xE0088000)
+#define LPC_MCI_BASE              (0xE008C000)
+#define LPC_SC_BASE               (0xE01FC000)
+#define LPC_EMAC_BASE             (0xFFE00000)
+#define LPC_GPDMA_BASE            (0xFFE04000)
+#define LPC_GPDMACH0_BASE         (0xFFE04100)
+#define LPC_GPDMACH1_BASE         (0xFFE04120)
+#define LPC_USB_BASE              (0xFFE0C000)
+#define LPC_VIC_BASE              (0xFFFFF000)
+
+/* GPIOs                                                                      */
+#define LPC_GPIO0_BASE            (0x3FFFC000)
+#define LPC_GPIO1_BASE            (0x3FFFC020)
+#define LPC_GPIO2_BASE            (0x3FFFC040)
+#define LPC_GPIO3_BASE            (0x3FFFC060)
+#define LPC_GPIO4_BASE            (0x3FFFC080)
+
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+#define LPC_SC                    ((       LPC_SC_TypeDef *)        LPC_SC_BASE)
+#define LPC_GPIO0                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO0_BASE)
+#define LPC_GPIO1                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO1_BASE)
+#define LPC_GPIO2                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO2_BASE)
+#define LPC_GPIO3                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO3_BASE)
+#define LPC_GPIO4                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO4_BASE)
+#define LPC_WDT                   ((      LPC_WDT_TypeDef *)       LPC_WDT_BASE)
+#define LPC_TIM0                  ((      LPC_TIM_TypeDef *)      LPC_TIM0_BASE)
+#define LPC_TIM1                  ((      LPC_TIM_TypeDef *)      LPC_TIM1_BASE)
+#define LPC_TIM2                  ((      LPC_TIM_TypeDef *)      LPC_TIM2_BASE)
+#define LPC_TIM3                  ((      LPC_TIM_TypeDef *)      LPC_TIM3_BASE)
+#define LPC_UART0                 ((     LPC_UART_TypeDef *)     LPC_UART0_BASE)
+#define LPC_UART1                 ((    LPC_UART1_TypeDef *)     LPC_UART1_BASE)
+#define LPC_UART2                 ((     LPC_UART_TypeDef *)     LPC_UART2_BASE)
+#define LPC_UART3                 ((     LPC_UART_TypeDef *)     LPC_UART3_BASE)
+#define LPC_PWM1                  ((      LPC_PWM_TypeDef *)      LPC_PWM1_BASE)
+#define LPC_I2C0                  ((      LPC_I2C_TypeDef *)      LPC_I2C0_BASE)
+#define LPC_I2C1                  ((      LPC_I2C_TypeDef *)      LPC_I2C1_BASE)
+#define LPC_I2C2                  ((      LPC_I2C_TypeDef *)      LPC_I2C2_BASE)
+#define LPC_I2S                   ((      LPC_I2S_TypeDef *)       LPC_I2S_BASE)
+#define LPC_SPI                   ((      LPC_SPI_TypeDef *)       LPC_SPI_BASE)
+#define LPC_RTC                   ((      LPC_RTC_TypeDef *)       LPC_RTC_BASE)
+#define LPC_GPIOINT               ((  LPC_GPIOINT_TypeDef *)   LPC_GPIOINT_BASE)
+#define LPC_PINCON                ((   LPC_PINCON_TypeDef *)    LPC_PINCON_BASE)
+#define LPC_SSP0                  ((      LPC_SSP_TypeDef *)      LPC_SSP0_BASE)
+#define LPC_SSP1                  ((      LPC_SSP_TypeDef *)      LPC_SSP1_BASE)
+#define LPC_ADC                   ((      LPC_ADC_TypeDef *)       LPC_ADC_BASE)
+#define LPC_DAC                   ((      LPC_DAC_TypeDef *)       LPC_DAC_BASE)
+#define LPC_CANAF_RAM             ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF                 ((    LPC_CANAF_TypeDef *)     LPC_CANAF_BASE)
+#define LPC_CANCR                 ((    LPC_CANCR_TypeDef *)     LPC_CANCR_BASE)
+#define LPC_CAN1                  ((      LPC_CAN_TypeDef *)      LPC_CAN1_BASE)
+#define LPC_CAN2                  ((      LPC_CAN_TypeDef *)      LPC_CAN2_BASE)
+#define LPC_MCI                   ((      LPC_MCI_TypeDef *)       LPC_MCI_BASE)
+#define LPC_EMAC                  ((     LPC_EMAC_TypeDef *)      LPC_EMAC_BASE)
+#define LPC_GPDMA                 ((    LPC_GPDMA_TypeDef *)     LPC_GPDMA_BASE)
+#define LPC_GPDMACH0              ((  LPC_GPDMACH_TypeDef *)  LPC_GPDMACH0_BASE)
+#define LPC_GPDMACH1              ((  LPC_GPDMACH_TypeDef *)  LPC_GPDMACH1_BASE)
+#define LPC_USB                   ((      LPC_USB_TypeDef *)       LPC_USB_BASE)
+#define LPC_VIC                   ((      LPC_VIC_TypeDef *)       LPC_VIC_BASE)
+
+#ifdef __cplusplus
+ }
+#endif 
+
+#endif  // __LPC23xx_H
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/LPC2368.sct	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,24 @@
+
+LR_IROM1 0x00000000 0x80000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x80000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x40000120 0x7EE0  {  ; RW data, inc space for realmonitor
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x7FD00000 0x2000  {  ; RW data, USB RAM
+   .ANY (AHBSRAM0)
+  }
+  RW_IRAM3 0x7FE00000 0x4000  {  ; RW data, ETH RAM
+   .ANY (AHBSRAM1)
+  }
+  RW_IRAM4 0xE0038000 0x0800  {  ; RW data, CAN RAM
+   .ANY (CANRAM)
+  }
+  RW_IRAM5 0xE0084000 0x0800  {  ; RW data, RTC RAM
+   .ANY (RTCRAM)
+  }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/sys.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/vector_functions.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,248 @@
+;/* mbed Microcontroller Library - InterruptIn
+; * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
+; */
+ 
+#line 1 "vector_functions.s"
+;
+;
+;
+
+#line 1 "vector_defns.h"
+
+
+
+ 
+
+
+
+ 
+
+#line 21 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 47 "vector_defns.h"
+
+
+#line 58 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 6 "vector_functions.s"
+
+
+        AREA    VECFUNCS, CODE, READONLY
+        ARM
+        PRESERVE8
+
+
+
+
+
+        EXPORT __mbed_fiq [WEAK]
+        EXPORT __mbed_undef [WEAK]
+        EXPORT __mbed_prefetch_abort [WEAK]
+        EXPORT __mbed_data_abort [WEAK]
+        EXPORT __mbed_irq [WEAK]
+        EXPORT __mbed_swi [WEAK]
+        EXPORT __mbed_dcc_irq [WEAK]
+        EXPORT __mbed_reset [WEAK]
+        IMPORT __mbed_init_realmonitor
+
+;
+;
+__mbed_fiq
+        B       __mbed_fiq
+
+;
+;
+__mbed_undef
+        LDR     PC, =0x7fffffa0
+
+;
+;
+__mbed_prefetch_abort
+        LDR     PC, =0x7fffffb0
+
+;
+;
+__mbed_data_abort
+        LDR     PC, =0x7fffffc0
+
+;
+;
+;
+;
+;
+;
+;
+;
+;
+__mbed_irq
+        ;
+        MSR     CPSR_c, #0x1F:OR:0x80:OR:0x40
+                
+        ;
+        STMDB   sp!, {r0-r3,r12,lr}    
+
+        ;
+        MOV	r0, #0xFFFFFF00
+        LDR	r0, [r0]	
+
+        ;
+        MOV     lr, pc       
+        BX      r0           
+			    				
+        ;
+        MOV	r0, #0xFFFFFF00
+        STR	r0, [r0]			;
+				
+        ;
+        LDMFD   sp!,{r0-r3,r12,lr}
+
+        ;
+        MSR     CPSR_c, #0x12:OR:0x80:OR:0x40
+
+        ;
+        SUBS    pc, lr, #4 
+
+;
+;
+;
+;
+__mbed_swi
+        ;
+        ;
+        STMFD   sp!, {a4, r4, ip, lr}
+
+        ;
+        LDR     r4, =0x40000040
+
+        ;
+        ;
+        LDR     a4, =0x00940000
+        LDR	PC, =0x7ffff820				
+
+;
+;
+;
+;
+__mbed_dcc_irq
+
+        ;
+			
+        ;
+        LDMFD    sp!,{r0-r3,r12,lr}
+
+        ;
+        MSR     CPSR_c, #0x12:OR:0x80:OR:0x40
+
+        ;
+				
+        ;
+        SUB     lr, lr, #4              ;
+        STMFD   sp!, {ip,lr}            ;
+			
+        ;
+        LDR     LR, =0xfffff000
+        STR     LR, [LR, #0xf00]
+			
+        ;
+        ;
+        ;
+        ;
+        LDR     PC, =0x7fffffe0			 
+
+;
+; __mbed_reset is called after reset
+; we setup the stacks and realmonitor, then call Reset_Handler like on M3
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                MOV     LR, PC       
+                BX      R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+__mbed_reset
+
+        ;
+
+        LDR     R0, =(0x40000000 + 0x8000)
+
+        ;
+        MSR     CPSR_c, #0x1B:OR:0x80:OR:0x40
+        MOV     SP, R0
+        SUB     R0, R0, #0x00000040
+
+        ;
+        MSR     CPSR_c, #0x17:OR:0x80:OR:0x40
+        MOV     SP, R0
+        SUB     R0, R0, #0x00000040
+
+        ;
+        MSR     CPSR_c, #0x11:OR:0x80:OR:0x40
+        MOV     SP, R0
+        SUB     R0, R0, #0x00000000
+
+        ;
+        MSR     CPSR_c, #0x12:OR:0x80:OR:0x40
+        MOV     SP, R0
+        SUB     R0, R0, #0x00000040
+
+        ;
+        MSR     CPSR_c, #0x13:OR:0x80:OR:0x40
+        MOV     SP, R0
+        SUB     R0, R0, #0x00000040
+
+        ;
+        MSR     CPSR_c, #0x10
+        MOV     SP, R0
+
+        ;
+        LDR     R0, =__mbed_init_realmonitor
+        MOV     LR, PC       
+        BX      R0           
+        
+        ;
+        LDR     R0, =Reset_Handler
+        BX      R0
+
+        
+        END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_MICRO/vector_table.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,99 @@
+;/* mbed Microcontroller Library - InterruptIn
+; * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
+; */
+ 
+#line 1 "vector_table.s"
+;
+
+
+ 
+
+#line 1 "vector_defns.h"
+
+
+
+ 
+
+
+
+ 
+
+#line 21 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 47 "vector_defns.h"
+
+
+#line 58 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 7 "vector_table.s"
+        
+;
+
+
+        AREA    RESET, CODE, READONLY
+        ARM
+;        ENTRY
+        PRESERVE8
+
+
+
+
+
+;        EXPORT __main
+        IMPORT __mbed_reset
+        IMPORT __mbed_undef
+        IMPORT __mbed_swi
+        IMPORT __mbed_prefetch_abort
+        IMPORT __mbed_data_abort
+        IMPORT __mbed_irq
+        IMPORT __mbed_fiq
+
+;
+
+ 
+;__main
+        LDR     PC, =__mbed_reset
+        LDR     PC, =__mbed_undef
+        LDR     PC, =__mbed_swi
+        LDR     PC, =__mbed_prefetch_abort
+        LDR     PC, =__mbed_data_abort
+        NOP     ;
+        LDR     PC, =__mbed_irq
+        LDR     PC, =__mbed_fiq
+        
+
+        END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/LPC2368.sct	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,24 @@
+
+LR_IROM1 0x00000000 0x80000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x80000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x40000120 0x7EE0  {  ; RW data, inc space for realmonitor
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x7FD00000 0x2000  {  ; RW data, USB RAM
+   .ANY (AHBSRAM0)
+  }
+  RW_IRAM3 0x7FE00000 0x4000  {  ; RW data, ETH RAM
+   .ANY (AHBSRAM1)
+  }
+  RW_IRAM4 0xE0038000 0x0800  {  ; RW data, CAN RAM
+   .ANY (CANRAM)
+  }
+  RW_IRAM5 0xE0084000 0x0800  {  ; RW data, RTC RAM
+   .ANY (RTCRAM)
+  }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/sys.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/vector_functions.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,248 @@
+;/* mbed Microcontroller Library - InterruptIn
+; * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
+; */
+ 
+#line 1 "vector_functions.s"
+;
+;
+;
+
+#line 1 "vector_defns.h"
+
+
+
+ 
+
+
+
+ 
+
+#line 21 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 47 "vector_defns.h"
+
+
+#line 58 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 6 "vector_functions.s"
+
+
+        AREA    VECFUNCS, CODE, READONLY
+        ARM
+        PRESERVE8
+
+
+
+
+
+        EXPORT __mbed_fiq [WEAK]
+        EXPORT __mbed_undef [WEAK]
+        EXPORT __mbed_prefetch_abort [WEAK]
+        EXPORT __mbed_data_abort [WEAK]
+        EXPORT __mbed_irq [WEAK]
+        EXPORT __mbed_swi [WEAK]
+        EXPORT __mbed_dcc_irq [WEAK]
+        EXPORT __mbed_reset [WEAK]
+        IMPORT __mbed_init_realmonitor
+
+;
+;
+__mbed_fiq
+        B       __mbed_fiq
+
+;
+;
+__mbed_undef
+        LDR     PC, =0x7fffffa0
+
+;
+;
+__mbed_prefetch_abort
+        LDR     PC, =0x7fffffb0
+
+;
+;
+__mbed_data_abort
+        LDR     PC, =0x7fffffc0
+
+;
+;
+;
+;
+;
+;
+;
+;
+;
+__mbed_irq
+        ;
+        MSR     CPSR_c, #0x1F:OR:0x80:OR:0x40
+                
+        ;
+        STMDB   sp!, {r0-r3,r12,lr}    
+
+        ;
+        MOV	r0, #0xFFFFFF00
+        LDR	r0, [r0]	
+
+        ;
+        MOV     lr, pc       
+        BX      r0           
+			    				
+        ;
+        MOV	r0, #0xFFFFFF00
+        STR	r0, [r0]			;
+				
+        ;
+        LDMFD   sp!,{r0-r3,r12,lr}
+
+        ;
+        MSR     CPSR_c, #0x12:OR:0x80:OR:0x40
+
+        ;
+        SUBS    pc, lr, #4 
+
+;
+;
+;
+;
+__mbed_swi
+        ;
+        ;
+        STMFD   sp!, {a4, r4, ip, lr}
+
+        ;
+        LDR     r4, =0x40000040
+
+        ;
+        ;
+        LDR     a4, =0x00940000
+        LDR	PC, =0x7ffff820				
+
+;
+;
+;
+;
+__mbed_dcc_irq
+
+        ;
+			
+        ;
+        LDMFD    sp!,{r0-r3,r12,lr}
+
+        ;
+        MSR     CPSR_c, #0x12:OR:0x80:OR:0x40
+
+        ;
+				
+        ;
+        SUB     lr, lr, #4              ;
+        STMFD   sp!, {ip,lr}            ;
+			
+        ;
+        LDR     LR, =0xfffff000
+        STR     LR, [LR, #0xf00]
+			
+        ;
+        ;
+        ;
+        ;
+        LDR     PC, =0x7fffffe0			 
+
+;
+; __mbed_reset is called after reset
+; we setup the stacks and realmonitor, then call Reset_Handler like on M3
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                MOV     LR, PC       
+                BX      R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+__mbed_reset
+
+        ;
+
+        LDR     R0, =(0x40000000 + 0x8000)
+
+        ;
+        MSR     CPSR_c, #0x1B:OR:0x80:OR:0x40
+        MOV     SP, R0
+        SUB     R0, R0, #0x00000040
+
+        ;
+        MSR     CPSR_c, #0x17:OR:0x80:OR:0x40
+        MOV     SP, R0
+        SUB     R0, R0, #0x00000040
+
+        ;
+        MSR     CPSR_c, #0x11:OR:0x80:OR:0x40
+        MOV     SP, R0
+        SUB     R0, R0, #0x00000000
+
+        ;
+        MSR     CPSR_c, #0x12:OR:0x80:OR:0x40
+        MOV     SP, R0
+        SUB     R0, R0, #0x00000040
+
+        ;
+        MSR     CPSR_c, #0x13:OR:0x80:OR:0x40
+        MOV     SP, R0
+        SUB     R0, R0, #0x00000040
+
+        ;
+        MSR     CPSR_c, #0x10
+        MOV     SP, R0
+
+        ;
+        LDR     R0, =__mbed_init_realmonitor
+        MOV     LR, PC       
+        BX      R0           
+        
+        ;
+        LDR     R0, =Reset_Handler
+        BX      R0
+
+        
+        END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_ARM_STD/vector_table.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,99 @@
+;/* mbed Microcontroller Library - InterruptIn
+; * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
+; */
+ 
+#line 1 "vector_table.s"
+;
+
+
+ 
+
+#line 1 "vector_defns.h"
+
+
+
+ 
+
+
+
+ 
+
+#line 21 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 47 "vector_defns.h"
+
+
+#line 58 "vector_defns.h"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#line 7 "vector_table.s"
+        
+;
+
+
+        AREA    RESET, CODE, READONLY
+        ARM
+;        ENTRY
+        PRESERVE8
+
+
+
+
+
+;        EXPORT __main
+        IMPORT __mbed_reset
+        IMPORT __mbed_undef
+        IMPORT __mbed_swi
+        IMPORT __mbed_prefetch_abort
+        IMPORT __mbed_data_abort
+        IMPORT __mbed_irq
+        IMPORT __mbed_fiq
+
+;
+
+ 
+;__main
+        LDR     PC, =__mbed_reset
+        LDR     PC, =__mbed_undef
+        LDR     PC, =__mbed_swi
+        LDR     PC, =__mbed_prefetch_abort
+        LDR     PC, =__mbed_data_abort
+        NOP     ;
+        LDR     PC, =__mbed_irq
+        LDR     PC, =__mbed_fiq
+        
+
+        END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/LPC2368.ld	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,206 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(vectors)
+
+/* Memory Definitions: */
+MEMORY
+{
+    Flash  (rx)  : ORIGIN = 0x00000000, LENGTH = 512k
+    Ram    (rwx) : ORIGIN = 0x40000000, LENGTH = 32k
+    UsbRam (rw)  : ORIGIN = 0x7FD00000, LENGTH = 8k
+    EthRam (rw)  : ORIGIN = 0x7FE00000, LENGTH = 16k
+    CanRam (rw)  : ORIGIN = 0xE0038000, LENGTH = 2k
+    BatRam (rw)  : ORIGIN = 0xE0084000, LENGTH = 2k
+}
+
+/* Stack sizes: */
+UND_Stack_Size = 16;
+SVC_Stack_Size = 512;
+ABT_Stack_Size = 16;
+FIQ_Stack_Size = 16;
+IRQ_Stack_Size = 256;
+Stack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;
+
+/* Stack tops for each mode: */
+__und_stack_top__ = __stacks_top__;
+__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;
+__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;
+__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;
+__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;
+
+/* C-accessible symbols for memory address ranges: */
+__FLASH_segment_start__ = ORIGIN( Flash );
+__FLASH_segment_end__   = ORIGIN( Flash ) + LENGTH( Flash );
+__SRAM_segment_start__  = ORIGIN( Ram );
+__SRAM_segment_end__    = ORIGIN( Ram ) + LENGTH( Ram );
+
+/* Stacks (full descending) at top of RAM, grows downward:
+ *
+ * __stack_min__ is used by the malloc implementation to ensure heap never collides
+ * with stack (assuming stack never grows beyond Stack_Size_Total in length) */
+__stacks_top__ = __SRAM_segment_end__;
+__stacks_min__ = __SRAM_segment_end__ - Stack_Size_Total;
+
+SECTIONS
+{
+    /* first section is .text which is used for code */
+    __text_start__ = . ;
+    .text : {
+        __privileged_code_start__ = . ;
+        KEEP( *( .vectors ) )
+        *( .privileged_code )
+    
+        __privileged_code_end__ = .;
+
+        *( .text .text.* .gnu.linkonce.t.* )
+        *( .plt )
+        *( .gnu.warning )
+        *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )
+        
+        *( .rodata .rodata.* .gnu.linkonce.r.* )
+        
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.gcc_except_table)
+        *(.eh_frame_hdr)
+        *(.eh_frame)
+        
+        . = ALIGN( 4 ) ;
+        KEEP( *( .init ) )
+        . = ALIGN( 4 ) ;
+        __preinit_array_start = . ;
+        KEEP( *( .preinit_array ) )
+        __preinit_array_end = . ;
+        . = ALIGN( 4 ) ;
+        __init_array_start = . ;
+        KEEP( *( SORT( .init_array.* ) ) )
+        KEEP( *( .init_array ) )
+        __init_array_end = . ;
+        
+        . = ALIGN( 4 ) ;
+        KEEP( *crtbegin.o( .ctors ) )
+        KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )
+        KEEP( *( SORT( .ctors.* ) ) )
+        KEEP( *crtend.o( .ctors ) )
+        
+        . = ALIGN( 4 ) ;
+        KEEP( *( .fini ) )
+        . = ALIGN( 4 ) ;
+        __fini_array_start = . ;
+        KEEP( *( .fini_array ) )
+        KEEP( *( SORT( .fini_array.* ) ) )
+        __fini_array_end = . ;
+        
+        KEEP( *crtbegin.o( .dtors ) )
+        KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )
+        KEEP( *( SORT( .dtors.* ) ) )
+        KEEP( *crtend.o( .dtors ) )
+    
+    } >Flash
+    
+    __exidx_start = . ;
+    .ARM.exidx : {
+        *( .ARM.exidx* .gnu.linkonce.armexidx.* )
+    } >Flash
+    __exidx_end = . ;
+    
+    .text.align : { . = ALIGN( 8 ) ; } >Flash /* Alignment schenanigans */
+    __text_end__ = . ;
+    
+    /* .bss section -- used for uninitialized data */
+    /* Located at the start of RAM */
+    .bss (NOLOAD) : {
+        __bss_start__ = . ;
+        *crt0.o( .ram_vectors )
+        
+        __user_bss_start__ = . ;
+        *( .user_bss )
+        __user_bss_end__ = . ;
+        
+        *( .shbss )
+        *( .bss .bss.* .gnu.linkonce.b.* )
+        *( COMMON )
+        *( .ram.b )
+        . = ALIGN( 8 ) ;
+        
+        __bss_end__ = . ;
+    } >Ram AT>Flash
+
+    /* .data section -- used for initialized data */
+    .data : {
+        __data_start__ = . ;
+        KEEP( *( .jcr ) )
+        *( .got.plt ) *( .got )
+        *( .shdata )
+        *( .data .data.* .gnu.linkonce.d.* )
+        *( .ram )
+        . = ALIGN( 8 ) ;
+        __data_end__ = . ;
+    } >Ram AT>Flash
+
+    __data_init_start__ = LOADADDR( .data ) ;
+
+    /* Heap starts here and grows up in memory */
+    . = ALIGN( 8 ) ;
+    __heap_start__ = . ;
+
+    .stab    0 (NOLOAD) : { *(.stab) }
+    .stabstr 0 (NOLOAD) : { *(.stabstr) }
+    /* DWARF debug sections. */
+    /* Symbols in the DWARF debugging sections are relative to the  */
+    /* beginning of the section so we begin them at 0.              */
+    /* DWARF 1 */
+    .debug           0 : { *(.debug) }
+    .line            0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo   0 : { *(.debug_srcinfo) }
+    .debug_sfnames   0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges   0 : { *(.debug_aranges) }
+    .debug_pubnames  0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info      0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev    0 : { *(.debug_abbrev) }
+    .debug_line      0 : { *(.debug_line) }
+    .debug_frame     0 : { *(.debug_frame) }
+    .debug_str       0 : { *(.debug_str) }
+    .debug_loc       0 : { *(.debug_loc) }
+    .debug_macinfo   0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+    /* DWARF 3 */
+    .debug_pubtypes  0 : { *(.debug_pubtypes) }
+    .debug_ranges    0 : { *(.debug_ranges) }
+    
+    .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }
+    .ARM.attributes     0 : {
+        KEEP( *( .ARM.attributes ) )
+        KEEP( *( .gnu.attributes ) )
+    }
+    /DISCARD/             : { *( .note.GNU-stack ) }
+    
+    /* C data can be defined as being in special purpose RAMs using
+     * __attribute__ ((section ("ethram"))) for example. */
+    .usbram (NOLOAD):
+    {
+        *( .usbram )
+        *( .usbram.* )
+    } > UsbRam
+    .ethram (NOLOAD):
+    {
+        *( .ethram )
+        *( .ethram.* )
+    } > EthRam
+    .canram (NOLOAD):
+    {
+        *( .canram )
+        *( .canram.* )
+    } > CanRam
+    .batram (NOLOAD):
+    {
+        *( .batram )
+        *( .batram.* )
+    } > BatRam
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/vector_functions.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,180 @@
+# 1 "vector_functions.s"
+# 1 "<built-in>"
+# 1 "<command line>"
+# 1 "vector_functions.s"
+;
+;
+;
+
+# 1 "vector_defns.h" 1
+# 6 "vector_functions.s" 2
+
+
+
+
+
+
+        .section VECFUNCS, "ax"
+        .arm
+
+
+        .weak __mbed_fiq
+        .weak __mbed_undef
+        .weak __mbed_prefetch_abort
+        .weak __mbed_data_abort
+        .weak __mbed_irq
+        .weak __mbed_swi
+        .weak __mbed_dcc_irq
+        .weak __mbed_reset
+        .global __mbed_init_realmonitor
+        .global __mbed_init
+
+;
+;
+__mbed_fiq:
+        B __mbed_fiq
+
+;
+;
+__mbed_undef:
+        LDR PC, =0x7fffffa0
+
+;
+;
+__mbed_prefetch_abort:
+        LDR PC, =0x7fffffb0
+
+;
+;
+__mbed_data_abort:
+        LDR PC, =0x7fffffc0
+
+;
+;
+;
+;
+;
+;
+;
+;
+;
+__mbed_irq:
+        ;
+        MSR CPSR_c, #0x1F|0x80|0x40
+
+        ;
+        STMDB sp!, {r0-r3,r12,lr}
+
+        ;
+        MOV r0, #0xFFFFFF00
+        LDR r0, [r0]
+
+        ;
+        MOV lr, pc
+        BX r0
+
+        ;
+        MOV r0, #0xFFFFFF00
+        STR r0, [r0] ;
+
+        ;
+        LDMFD sp!,{r0-r3,r12,lr}
+
+        ;
+        MSR CPSR_c, #0x12|0x80|0x40
+
+        ;
+        SUBS pc, lr, #4
+
+;
+;
+;
+;
+__mbed_swi:
+        ;
+        ;
+        STMFD sp!, {a4, r4, ip, lr}
+
+        ;
+        LDR r4, =0x40000040
+
+        ;
+        ;
+        LDR a4, =0x00940000
+        LDR PC, =0x7ffff820
+
+;
+;
+;
+;
+__mbed_dcc_irq:
+
+        ;
+
+        ;
+        LDMFD sp!,{r0-r3,r12,lr}
+
+        ;
+        MSR CPSR_c, #0x12|0x80|0x40
+
+        ;
+
+        ;
+        SUB lr, lr, #4 ;
+        STMFD sp!, {ip,lr} ;
+
+        ;
+        LDR LR, =0xfffff000
+        STR LR, [LR, #0xf00]
+
+        ;
+        ;
+        ;
+        ;
+        LDR PC, =0x7fffffe0
+
+;
+;
+__mbed_reset:
+
+        ;
+
+        LDR R0, =(0x40000000 + 0x8000)
+
+        ;
+        MSR CPSR_c, #0x1B|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000040
+
+        ;
+        MSR CPSR_c, #0x17|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000040
+
+        ;
+        MSR CPSR_c, #0x11|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000000
+
+        ;
+        MSR CPSR_c, #0x12|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000040
+
+        ;
+        MSR CPSR_c, #0x13|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000040
+
+        ;
+        MSR CPSR_c, #0x10
+        MOV SP, R0
+
+        ;
+        LDR R0, =__mbed_init_realmonitor
+        MOV LR, PC
+        BX R0
+
+        ;
+        LDR R0, =__mbed_init
+        BX R0

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_ARM/vector_table.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,45 @@
+# 1 "vector_table.s"
+# 1 "<built-in>"
+# 1 "<command line>"
+# 1 "vector_table.s"
+;
+
+
+
+
+# 1 "vector_defns.h" 1
+# 7 "vector_table.s" 2
+
+;
+
+
+
+
+
+
+
+        .section VECTOR_TABLE, "ax"
+        .arm
+
+
+        .global __main
+        .global __mbed_reset
+        .global __mbed_undef
+        .global __mbed_swi
+        .global __mbed_prefetch_abort
+        .global __mbed_data_abort
+        .global __mbed_irq
+        .global __mbed_fiq
+
+;
+
+
+__main:
+        LDR PC, =__mbed_reset
+        LDR PC, =__mbed_undef
+        LDR PC, =__mbed_swi
+        LDR PC, =__mbed_prefetch_abort
+        LDR PC, =__mbed_data_abort
+        NOP ;
+        LDR PC, =__mbed_irq
+        LDR PC, =__mbed_fiq

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/LPC2368.ld	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,208 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(vectors)
+
+GROUP(-lsupc++ -lm -lc -lgcc)
+
+/* Memory Definitions: */
+MEMORY
+{
+    Flash  (rx)  : ORIGIN = 0x00000000, LENGTH = 512k
+    Ram    (rwx) : ORIGIN = 0x40000000, LENGTH = 32k
+    UsbRam (rw)  : ORIGIN = 0x7FD00000, LENGTH = 8k
+    EthRam (rw)  : ORIGIN = 0x7FE00000, LENGTH = 16k
+    CanRam (rw)  : ORIGIN = 0xE0038000, LENGTH = 2k
+    BatRam (rw)  : ORIGIN = 0xE0084000, LENGTH = 2k
+}
+
+/* Stack sizes: */
+UND_Stack_Size = 16;
+SVC_Stack_Size = 512;
+ABT_Stack_Size = 16;
+FIQ_Stack_Size = 16;
+IRQ_Stack_Size = 256;
+Stack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;
+
+/* Stack tops for each mode: */
+__und_stack_top__ = __stacks_top__;
+__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;
+__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;
+__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;
+__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;
+
+/* C-accessible symbols for memory address ranges: */
+__FLASH_segment_start__ = ORIGIN( Flash );
+__FLASH_segment_end__   = ORIGIN( Flash ) + LENGTH( Flash );
+__SRAM_segment_start__  = ORIGIN( Ram );
+__SRAM_segment_end__    = ORIGIN( Ram ) + LENGTH( Ram );
+
+/* Stacks (full descending) at top of RAM, grows downward:
+ *
+ * __stack_min__ is used by the malloc implementation to ensure heap never collides
+ * with stack (assuming stack never grows beyond Stack_Size_Total in length) */
+__stacks_top__ = __SRAM_segment_end__;
+__stacks_min__ = __SRAM_segment_end__ - Stack_Size_Total;
+
+SECTIONS
+{
+    /* first section is .text which is used for code */
+    __text_start__ = . ;
+    .text : {
+        __privileged_code_start__ = . ;
+        KEEP( *( .vectors ) )
+        *( .privileged_code )
+    
+        __privileged_code_end__ = .;
+
+        *( .text .text.* .gnu.linkonce.t.* )
+        *( .plt )
+        *( .gnu.warning )
+        *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )
+        
+        *( .rodata .rodata.* .gnu.linkonce.r.* )
+        
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.gcc_except_table)
+        *(.eh_frame_hdr)
+        *(.eh_frame)
+        
+        . = ALIGN( 4 ) ;
+        KEEP( *( .init ) )
+        . = ALIGN( 4 ) ;
+        __preinit_array_start = . ;
+        KEEP( *( .preinit_array ) )
+        __preinit_array_end = . ;
+        . = ALIGN( 4 ) ;
+        __init_array_start = . ;
+        KEEP( *( SORT( .init_array.* ) ) )
+        KEEP( *( .init_array ) )
+        __init_array_end = . ;
+        
+        . = ALIGN( 4 ) ;
+        KEEP( *crtbegin.o( .ctors ) )
+        KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )
+        KEEP( *( SORT( .ctors.* ) ) )
+        KEEP( *crtend.o( .ctors ) )
+        
+        . = ALIGN( 4 ) ;
+        KEEP( *( .fini ) )
+        . = ALIGN( 4 ) ;
+        __fini_array_start = . ;
+        KEEP( *( .fini_array ) )
+        KEEP( *( SORT( .fini_array.* ) ) )
+        __fini_array_end = . ;
+        
+        KEEP( *crtbegin.o( .dtors ) )
+        KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )
+        KEEP( *( SORT( .dtors.* ) ) )
+        KEEP( *crtend.o( .dtors ) )
+    
+    } >Flash
+    
+    __exidx_start = . ;
+    .ARM.exidx : {
+        *( .ARM.exidx* .gnu.linkonce.armexidx.* )
+    } >Flash
+    __exidx_end = . ;
+    
+    .text.align : { . = ALIGN( 8 ) ; } >Flash /* Alignment schenanigans */
+    __text_end__ = . ;
+    
+    /* .bss section -- used for uninitialized data */
+    /* Located at the start of RAM */
+    .bss (NOLOAD) : {
+        __bss_start__ = . ;
+        *crt0.o( .ram_vectors )
+        
+        __user_bss_start__ = . ;
+        *( .user_bss )
+        __user_bss_end__ = . ;
+        
+        *( .shbss )
+        *( .bss .bss.* .gnu.linkonce.b.* )
+        *( COMMON )
+        *( .ram.b )
+        . = ALIGN( 8 ) ;
+        
+        __bss_end__ = . ;
+    } >Ram AT>Flash
+
+    /* .data section -- used for initialized data */
+    .data : {
+        __data_start__ = . ;
+        KEEP( *( .jcr ) )
+        *( .got.plt ) *( .got )
+        *( .shdata )
+        *( .data .data.* .gnu.linkonce.d.* )
+        *( .ram )
+        . = ALIGN( 8 ) ;
+        __data_end__ = . ;
+    } >Ram AT>Flash
+
+    __data_init_start__ = LOADADDR( .data ) ;
+
+    /* Heap starts here and grows up in memory */
+    . = ALIGN( 8 ) ;
+    __heap_start__ = . ;
+
+    .stab    0 (NOLOAD) : { *(.stab) }
+    .stabstr 0 (NOLOAD) : { *(.stabstr) }
+    /* DWARF debug sections. */
+    /* Symbols in the DWARF debugging sections are relative to the  */
+    /* beginning of the section so we begin them at 0.              */
+    /* DWARF 1 */
+    .debug           0 : { *(.debug) }
+    .line            0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo   0 : { *(.debug_srcinfo) }
+    .debug_sfnames   0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges   0 : { *(.debug_aranges) }
+    .debug_pubnames  0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info      0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev    0 : { *(.debug_abbrev) }
+    .debug_line      0 : { *(.debug_line) }
+    .debug_frame     0 : { *(.debug_frame) }
+    .debug_str       0 : { *(.debug_str) }
+    .debug_loc       0 : { *(.debug_loc) }
+    .debug_macinfo   0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+    /* DWARF 3 */
+    .debug_pubtypes  0 : { *(.debug_pubtypes) }
+    .debug_ranges    0 : { *(.debug_ranges) }
+    
+    .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }
+    .ARM.attributes     0 : {
+        KEEP( *( .ARM.attributes ) )
+        KEEP( *( .gnu.attributes ) )
+    }
+    /DISCARD/             : { *( .note.GNU-stack ) }
+    
+    /* C data can be defined as being in special purpose RAMs using
+     * __attribute__ ((section ("ethram"))) for example. */
+    .usbram (NOLOAD):
+    {
+        *( .usbram )
+        *( .usbram.* )
+    } > UsbRam
+    .ethram (NOLOAD):
+    {
+        *( .ethram )
+        *( .ethram.* )
+    } > EthRam
+    .canram (NOLOAD):
+    {
+        *( .canram )
+        *( .canram.* )
+    } > CanRam
+    .batram (NOLOAD):
+    {
+        *( .batram )
+        *( .batram.* )
+    } > BatRam
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/vector_functions.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,180 @@
+# 1 "vector_functions.s"
+# 1 "<built-in>"
+# 1 "<command line>"
+# 1 "vector_functions.s"
+;
+;
+;
+
+# 1 "vector_defns.h" 1
+# 6 "vector_functions.s" 2
+
+
+
+
+
+
+        .section VECFUNCS, "ax"
+        .arm
+
+
+        .weak __mbed_fiq
+        .weak __mbed_undef
+        .weak __mbed_prefetch_abort
+        .weak __mbed_data_abort
+        .weak __mbed_irq
+        .weak __mbed_swi
+        .weak __mbed_dcc_irq
+        .weak __mbed_reset
+        .global __mbed_init_realmonitor
+        .global __mbed_init
+
+;
+;
+__mbed_fiq:
+        B __mbed_fiq
+
+;
+;
+__mbed_undef:
+        LDR PC, =0x7fffffa0
+
+;
+;
+__mbed_prefetch_abort:
+        LDR PC, =0x7fffffb0
+
+;
+;
+__mbed_data_abort:
+        LDR PC, =0x7fffffc0
+
+;
+;
+;
+;
+;
+;
+;
+;
+;
+__mbed_irq:
+        ;
+        MSR CPSR_c, #0x1F|0x80|0x40
+
+        ;
+        STMDB sp!, {r0-r3,r12,lr}
+
+        ;
+        MOV r0, #0xFFFFFF00
+        LDR r0, [r0]
+
+        ;
+        MOV lr, pc
+        BX r0
+
+        ;
+        MOV r0, #0xFFFFFF00
+        STR r0, [r0] ;
+
+        ;
+        LDMFD sp!,{r0-r3,r12,lr}
+
+        ;
+        MSR CPSR_c, #0x12|0x80|0x40
+
+        ;
+        SUBS pc, lr, #4
+
+;
+;
+;
+;
+__mbed_swi:
+        ;
+        ;
+        STMFD sp!, {a4, r4, ip, lr}
+
+        ;
+        LDR r4, =0x40000040
+
+        ;
+        ;
+        LDR a4, =0x00940000
+        LDR PC, =0x7ffff820
+
+;
+;
+;
+;
+__mbed_dcc_irq:
+
+        ;
+
+        ;
+        LDMFD sp!,{r0-r3,r12,lr}
+
+        ;
+        MSR CPSR_c, #0x12|0x80|0x40
+
+        ;
+
+        ;
+        SUB lr, lr, #4 ;
+        STMFD sp!, {ip,lr} ;
+
+        ;
+        LDR LR, =0xfffff000
+        STR LR, [LR, #0xf00]
+
+        ;
+        ;
+        ;
+        ;
+        LDR PC, =0x7fffffe0
+
+;
+;
+__mbed_reset:
+
+        ;
+
+        LDR R0, =(0x40000000 + 0x8000)
+
+        ;
+        MSR CPSR_c, #0x1B|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000040
+
+        ;
+        MSR CPSR_c, #0x17|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000040
+
+        ;
+        MSR CPSR_c, #0x11|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000000
+
+        ;
+        MSR CPSR_c, #0x12|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000040
+
+        ;
+        MSR CPSR_c, #0x13|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000040
+
+        ;
+        MSR CPSR_c, #0x10
+        MOV SP, R0
+
+        ;
+        LDR R0, =__mbed_init_realmonitor
+        MOV LR, PC
+        BX R0
+
+        ;
+        LDR R0, =__mbed_init
+        BX R0

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CR/vector_table.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,45 @@
+# 1 "vector_table.s"
+# 1 "<built-in>"
+# 1 "<command line>"
+# 1 "vector_table.s"
+;
+
+
+
+
+# 1 "vector_defns.h" 1
+# 7 "vector_table.s" 2
+
+;
+
+
+
+
+
+
+
+        .section VECTOR_TABLE, "ax"
+        .arm
+
+
+        .global __main
+        .global __mbed_reset
+        .global __mbed_undef
+        .global __mbed_swi
+        .global __mbed_prefetch_abort
+        .global __mbed_data_abort
+        .global __mbed_irq
+        .global __mbed_fiq
+
+;
+
+
+__main:
+        LDR PC, =__mbed_reset
+        LDR PC, =__mbed_undef
+        LDR PC, =__mbed_swi
+        LDR PC, =__mbed_prefetch_abort
+        LDR PC, =__mbed_data_abort
+        NOP ;
+        LDR PC, =__mbed_irq
+        LDR PC, =__mbed_fiq

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/LPC2368.ld	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,207 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(vectors)
+GROUP(-lsupc++ -lm -lc -lcs3unhosted -lcs3 -lgcc)
+
+/* Memory Definitions: */
+MEMORY
+{
+    Flash  (rx)  : ORIGIN = 0x00000000, LENGTH = 512k
+    Ram    (rwx) : ORIGIN = 0x40000000, LENGTH = 32k
+    UsbRam (rw)  : ORIGIN = 0x7FD00000, LENGTH = 8k
+    EthRam (rw)  : ORIGIN = 0x7FE00000, LENGTH = 16k
+    CanRam (rw)  : ORIGIN = 0xE0038000, LENGTH = 2k
+    BatRam (rw)  : ORIGIN = 0xE0084000, LENGTH = 2k
+}
+
+/* Stack sizes: */
+UND_Stack_Size = 16;
+SVC_Stack_Size = 512;
+ABT_Stack_Size = 16;
+FIQ_Stack_Size = 16;
+IRQ_Stack_Size = 256;
+Stack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;
+
+/* Stack tops for each mode: */
+__und_stack_top__ = __stacks_top__;
+__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;
+__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;
+__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;
+__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;
+
+/* C-accessible symbols for memory address ranges: */
+__FLASH_segment_start__ = ORIGIN( Flash );
+__FLASH_segment_end__   = ORIGIN( Flash ) + LENGTH( Flash );
+__SRAM_segment_start__  = ORIGIN( Ram );
+__SRAM_segment_end__    = ORIGIN( Ram ) + LENGTH( Ram );
+
+/* Stacks (full descending) at top of RAM, grows downward:
+ *
+ * __stack_min__ is used by the malloc implementation to ensure heap never collides
+ * with stack (assuming stack never grows beyond Stack_Size_Total in length) */
+__stacks_top__ = __SRAM_segment_end__;
+__stacks_min__ = __SRAM_segment_end__ - Stack_Size_Total;
+
+SECTIONS
+{
+    /* first section is .text which is used for code */
+    __text_start__ = . ;
+    .text : {
+        __privileged_code_start__ = . ;
+        KEEP( *( .vectors ) )
+        *( .privileged_code )
+    
+        __privileged_code_end__ = .;
+
+        *( .text .text.* .gnu.linkonce.t.* )
+        *( .plt )
+        *( .gnu.warning )
+        *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )
+        
+        *( .rodata .rodata.* .gnu.linkonce.r.* )
+        
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.gcc_except_table)
+        *(.eh_frame_hdr)
+        *(.eh_frame)
+        
+        . = ALIGN( 4 ) ;
+        KEEP( *( .init ) )
+        . = ALIGN( 4 ) ;
+        __preinit_array_start = . ;
+        KEEP( *( .preinit_array ) )
+        __preinit_array_end = . ;
+        . = ALIGN( 4 ) ;
+        __init_array_start = . ;
+        KEEP( *( SORT( .init_array.* ) ) )
+        KEEP( *( .init_array ) )
+        __init_array_end = . ;
+        
+        . = ALIGN( 4 ) ;
+        KEEP( *crtbegin.o( .ctors ) )
+        KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )
+        KEEP( *( SORT( .ctors.* ) ) )
+        KEEP( *crtend.o( .ctors ) )
+        
+        . = ALIGN( 4 ) ;
+        KEEP( *( .fini ) )
+        . = ALIGN( 4 ) ;
+        __fini_array_start = . ;
+        KEEP( *( .fini_array ) )
+        KEEP( *( SORT( .fini_array.* ) ) )
+        __fini_array_end = . ;
+        
+        KEEP( *crtbegin.o( .dtors ) )
+        KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )
+        KEEP( *( SORT( .dtors.* ) ) )
+        KEEP( *crtend.o( .dtors ) )
+    
+    } >Flash
+    
+    __exidx_start = . ;
+    .ARM.exidx : {
+        *( .ARM.exidx* .gnu.linkonce.armexidx.* )
+    } >Flash
+    __exidx_end = . ;
+    
+    .text.align : { . = ALIGN( 8 ) ; } >Flash /* Alignment schenanigans */
+    __text_end__ = . ;
+    
+    /* .bss section -- used for uninitialized data */
+    /* Located at the start of RAM */
+    .bss (NOLOAD) : {
+        __bss_start__ = . ;
+        *crt0.o( .ram_vectors )
+        
+        __user_bss_start__ = . ;
+        *( .user_bss )
+        __user_bss_end__ = . ;
+        
+        *( .shbss )
+        *( .bss .bss.* .gnu.linkonce.b.* )
+        *( COMMON )
+        *( .ram.b )
+        . = ALIGN( 8 ) ;
+        
+        __bss_end__ = . ;
+    } >Ram AT>Flash
+
+    /* .data section -- used for initialized data */
+    .data : {
+        __data_start__ = . ;
+        KEEP( *( .jcr ) )
+        *( .got.plt ) *( .got )
+        *( .shdata )
+        *( .data .data.* .gnu.linkonce.d.* )
+        *( .ram )
+        . = ALIGN( 8 ) ;
+        __data_end__ = . ;
+    } >Ram AT>Flash
+
+    __data_init_start__ = LOADADDR( .data ) ;
+
+    /* Heap starts here and grows up in memory */
+    . = ALIGN( 8 ) ;
+    __heap_start__ = . ;
+
+    .stab    0 (NOLOAD) : { *(.stab) }
+    .stabstr 0 (NOLOAD) : { *(.stabstr) }
+    /* DWARF debug sections. */
+    /* Symbols in the DWARF debugging sections are relative to the  */
+    /* beginning of the section so we begin them at 0.              */
+    /* DWARF 1 */
+    .debug           0 : { *(.debug) }
+    .line            0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo   0 : { *(.debug_srcinfo) }
+    .debug_sfnames   0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges   0 : { *(.debug_aranges) }
+    .debug_pubnames  0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info      0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev    0 : { *(.debug_abbrev) }
+    .debug_line      0 : { *(.debug_line) }
+    .debug_frame     0 : { *(.debug_frame) }
+    .debug_str       0 : { *(.debug_str) }
+    .debug_loc       0 : { *(.debug_loc) }
+    .debug_macinfo   0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+    /* DWARF 3 */
+    .debug_pubtypes  0 : { *(.debug_pubtypes) }
+    .debug_ranges    0 : { *(.debug_ranges) }
+    
+    .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }
+    .ARM.attributes     0 : {
+        KEEP( *( .ARM.attributes ) )
+        KEEP( *( .gnu.attributes ) )
+    }
+    /DISCARD/             : { *( .note.GNU-stack ) }
+    
+    /* C data can be defined as being in special purpose RAMs using
+     * __attribute__ ((section ("ethram"))) for example. */
+    .usbram (NOLOAD):
+    {
+        *( .usbram )
+        *( .usbram.* )
+    } > UsbRam
+    .ethram (NOLOAD):
+    {
+        *( .ethram )
+        *( .ethram.* )
+    } > EthRam
+    .canram (NOLOAD):
+    {
+        *( .canram )
+        *( .canram.* )
+    } > CanRam
+    .batram (NOLOAD):
+    {
+        *( .batram )
+        *( .batram.* )
+    } > BatRam
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/vector_functions.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,180 @@
+# 1 "vector_functions.s"
+# 1 "<built-in>"
+# 1 "<command line>"
+# 1 "vector_functions.s"
+;
+;
+;
+
+# 1 "vector_defns.h" 1
+# 6 "vector_functions.s" 2
+
+
+
+
+
+
+        .section VECFUNCS, "ax"
+        .arm
+
+
+        .weak __mbed_fiq
+        .weak __mbed_undef
+        .weak __mbed_prefetch_abort
+        .weak __mbed_data_abort
+        .weak __mbed_irq
+        .weak __mbed_swi
+        .weak __mbed_dcc_irq
+        .weak __mbed_reset
+        .global __mbed_init_realmonitor
+        .global __mbed_init
+
+;
+;
+__mbed_fiq:
+        B __mbed_fiq
+
+;
+;
+__mbed_undef:
+        LDR PC, =0x7fffffa0
+
+;
+;
+__mbed_prefetch_abort:
+        LDR PC, =0x7fffffb0
+
+;
+;
+__mbed_data_abort:
+        LDR PC, =0x7fffffc0
+
+;
+;
+;
+;
+;
+;
+;
+;
+;
+__mbed_irq:
+        ;
+        MSR CPSR_c, #0x1F|0x80|0x40
+
+        ;
+        STMDB sp!, {r0-r3,r12,lr}
+
+        ;
+        MOV r0, #0xFFFFFF00
+        LDR r0, [r0]
+
+        ;
+        MOV lr, pc
+        BX r0
+
+        ;
+        MOV r0, #0xFFFFFF00
+        STR r0, [r0] ;
+
+        ;
+        LDMFD sp!,{r0-r3,r12,lr}
+
+        ;
+        MSR CPSR_c, #0x12|0x80|0x40
+
+        ;
+        SUBS pc, lr, #4
+
+;
+;
+;
+;
+__mbed_swi:
+        ;
+        ;
+        STMFD sp!, {a4, r4, ip, lr}
+
+        ;
+        LDR r4, =0x40000040
+
+        ;
+        ;
+        LDR a4, =0x00940000
+        LDR PC, =0x7ffff820
+
+;
+;
+;
+;
+__mbed_dcc_irq:
+
+        ;
+
+        ;
+        LDMFD sp!,{r0-r3,r12,lr}
+
+        ;
+        MSR CPSR_c, #0x12|0x80|0x40
+
+        ;
+
+        ;
+        SUB lr, lr, #4 ;
+        STMFD sp!, {ip,lr} ;
+
+        ;
+        LDR LR, =0xfffff000
+        STR LR, [LR, #0xf00]
+
+        ;
+        ;
+        ;
+        ;
+        LDR PC, =0x7fffffe0
+
+;
+;
+__mbed_reset:
+
+        ;
+
+        LDR R0, =(0x40000000 + 0x8000)
+
+        ;
+        MSR CPSR_c, #0x1B|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000040
+
+        ;
+        MSR CPSR_c, #0x17|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000040
+
+        ;
+        MSR CPSR_c, #0x11|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000000
+
+        ;
+        MSR CPSR_c, #0x12|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000040
+
+        ;
+        MSR CPSR_c, #0x13|0x80|0x40
+        MOV SP, R0
+        SUB R0, R0, #0x00000040
+
+        ;
+        MSR CPSR_c, #0x10
+        MOV SP, R0
+
+        ;
+        LDR R0, =__mbed_init_realmonitor
+        MOV LR, PC
+        BX R0
+
+        ;
+        LDR R0, =__mbed_init
+        BX R0

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/TOOLCHAIN_GCC_CS/vector_table.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,45 @@
+# 1 "vector_table.s"
+# 1 "<built-in>"
+# 1 "<command line>"
+# 1 "vector_table.s"
+;
+
+
+
+
+# 1 "vector_defns.h" 1
+# 7 "vector_table.s" 2
+
+;
+
+
+
+
+
+
+
+        .section VECTOR_TABLE, "ax"
+        .arm
+
+
+        .global __main
+        .global __mbed_reset
+        .global __mbed_undef
+        .global __mbed_swi
+        .global __mbed_prefetch_abort
+        .global __mbed_data_abort
+        .global __mbed_irq
+        .global __mbed_fiq
+
+;
+
+
+__main:
+        LDR PC, =__mbed_reset
+        LDR PC, =__mbed_undef
+        LDR PC, =__mbed_swi
+        LDR PC, =__mbed_prefetch_abort
+        LDR PC, =__mbed_data_abort
+        NOP ;
+        LDR PC, =__mbed_irq
+        LDR PC, =__mbed_fiq

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * A generic CMSIS include header, pulling in LPC2368 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC23xx.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,16 @@
+/* mbed Microcontroller Library - cmsis_nvic for LPC2368
+ * Copyright (c) 2009 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+
+#include "cmsis_nvic.h"
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    LPC_VIC->VectAddr[(int)IRQn] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    return LPC_VIC->VectAddr[(int)IRQn];
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/cmsis_nvic.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,23 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library
+ * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
+ *
+ * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
+ * based on core_cm3.h, V1.20
+ */
+
+#include <stdint.h>
+
+
+/* define compiler specific symbols */
+#if defined   ( __CC_ARM   )
+  #define __ASM            __asm           /*!< asm keyword for armcc           */
+  #define __INLINE         __inline        /*!< inline keyword for armcc        */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm            /*!< asm keyword for iarcc           */
+  #define __INLINE        inline           /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
+
+#elif defined (  __GNUC__  )
+  #define __ASM             __asm          /*!< asm keyword for gcc            */
+  #define __INLINE          inline         /*!< inline keyword for gcc         */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm           /*!< asm keyword for TASKING Compiler          */
+  #define __INLINE         inline          /*!< inline keyword for TASKING Compiler       */
+
+#endif
+
+#if defined ( __CC_ARM   )
+/**
+ * @brief  Return the Main Stack Pointer (return current ARM7 stack)
+ *
+ * @param  none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+    return __current_sp();
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,265 @@
+/* mbed Microcontroller Library
+ * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
+ *
+ * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
+ * based on core_cm3.h, V1.20
+ */
+
+#ifndef __ARM7_CORE_H__
+#define __ARM7_CORE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
+
+/**
+ *  Lint configuration \n
+ *  ----------------------- \n
+ *
+ *  The following Lint messages will be suppressed and not shown: \n
+ *  \n
+ *    --- Error 10: --- \n
+ *    register uint32_t __regBasePri         __asm("basepri"); \n
+ *    Error 10: Expecting ';' \n
+ *     \n
+ *    --- Error 530: --- \n
+ *    return(__regBasePri); \n
+ *    Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
+ *     \n
+ *    --- Error 550: --- \n
+ *      __regBasePri = (basePri & 0x1ff); \n
+ *    } \n
+ *    Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
+ *     \n
+ *    --- Error 754: --- \n
+ *    uint32_t RESERVED0[24]; \n
+ *    Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
+ *     \n
+ *    --- Error 750: --- \n
+ *    #define __CM3_CORE_H__ \n
+ *    Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
+ *     \n
+ *    --- Error 528: --- \n
+ *    static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
+ *    Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
+ *     \n
+ *    --- Error 751: --- \n
+ *    } InterruptType_Type; \n
+ *    Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
+ * \n
+ * \n
+ *    Note:  To re-enable a Message, insert a space before 'lint' * \n
+ *
+ */
+
+/*lint -save */
+/*lint -e10  */
+/*lint -e530 */
+/*lint -e550 */
+/*lint -e754 */
+/*lint -e750 */
+/*lint -e528 */
+/*lint -e751 */
+
+#include <stdint.h>                           /* Include standard types */
+
+#if defined ( __CC_ARM   )
+/**
+ * @brief  Return the Main Stack Pointer (current ARM7 stack)
+ *
+ * @param  none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+#endif
+
+
+#if defined (__ICCARM__)
+  #include <intrinsics.h>                     /* IAR Intrinsics   */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
+#endif
+
+typedef struct
+{
+  uint32_t IRQStatus;
+  uint32_t FIQStatus;
+  uint32_t RawIntr;
+  uint32_t IntSelect;
+  uint32_t IntEnable;
+  uint32_t IntEnClr;
+  uint32_t SoftInt;
+  uint32_t SoftIntClr;
+  uint32_t Protection;
+  uint32_t SWPriorityMask;
+  uint32_t RESERVED0[54];
+  uint32_t VectAddr[32];
+  uint32_t RESERVED1[32];
+  uint32_t VectPriority[32];
+  uint32_t RESERVED2[800];
+  uint32_t Address;
+} NVIC_TypeDef;
+
+#define NVIC_BASE              (0xFFFFF000)
+#define NVIC                   ((      NVIC_TypeDef *)       NVIC_BASE)
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#ifdef __cplusplus
+#define     __I     volatile                  /*!< defines 'read only' permissions      */
+#else
+#define     __I     volatile const            /*!< defines 'read only' permissions      */
+#endif
+#define     __O     volatile                  /*!< defines 'write only' permissions     */
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
+
+
+
+
+
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler           */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler       */
+
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#define __enable_fault_irq                __enable_fiq
+#define __disable_fault_irq               __disable_fiq
+
+#define __NOP                             __nop
+//#define __WFI                             __wfi
+//#define __WFE                             __wfe
+//#define __SEV                             __sev
+//#define __ISB()                           __isb(0)
+//#define __DSB()                           __dsb(0)
+//#define __DMB()                           __dmb(0)
+//#define __REV                             __rev
+//#define __RBIT                            __rbit
+#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
+#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
+#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
+#define __STREXB(value, ptr)              __strex(value, ptr)
+#define __STREXH(value, ptr)              __strex(value, ptr)
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+#define __disable_irq()         unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
+                                LPC_VIC->IntEnClr = 0xffffffff
+
+#define __enable_irq()          LPC_VIC->IntEnable = tmp_IntEnable
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+
+#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
+#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
+#define __NOP                                     __no_operation()          /*!< no operation intrinsic in IAR Compiler */ 
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+
+static __INLINE void __enable_irq() {
+    unsigned long temp;
+    __asm__ __volatile__("mrs %0, cpsr\n"
+                         "bic %0, %0, #0x80\n"
+                         "msr cpsr_c, %0"
+                         : "=r" (temp)
+                         :
+                         : "memory");
+}
+
+static __INLINE void __disable_irq() {
+    unsigned long old,temp;
+    __asm__ __volatile__("mrs %0, cpsr\n"
+                         "orr %1, %0, #0xc0\n"
+                         "msr cpsr_c, %1"
+                         : "=r" (old), "=r" (temp)
+                         :
+                         : "memory");
+    // return (old & 0x80) == 0;
+}
+
+static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+/**
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ *
+ * @param  IRQn_Type IRQn specifies the interrupt number
+ * @return none 
+ *
+ * Enable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->IntEnable = 1 << (uint32_t)IRQn;
+}
+
+
+/**
+ * @brief  Disable the interrupt line for external interrupt specified
+ * 
+ * @param  IRQn_Type IRQn is the positive number of the external interrupt
+ * @return none
+ * 
+ * Disable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->IntEnClr = 1 << (uint32_t)IRQn;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARM7_CORE_H__ */
+
+/*lint -restore */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,144 @@
+/* mbed Microcontroller Library
+ * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
+ *
+ * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
+ */
+
+#include <stdint.h>
+#include "LPC23xx.h"
+
+#define CLOCK_SETUP           1
+#define SCS_Val               0x00000020
+#define CLKSRCSEL_Val         0x00000001
+
+#define PLL0_SETUP            1
+#define PLL0CFG_Val           0x00000013
+#define CCLKCFG_Val           0x00000007
+#define USBCLKCFG_Val         0x00000009
+#define PCLKSEL0_Val          0x00000000
+#define PCLKSEL1_Val          0x00000000
+#define PCONP_Val             0x042887DE
+#define CLKOUTCFG_Val         0x00000000
+#define MAMCR_Val             0x00000001  // there is a bug in the MAM so it should never be fully enabled (only disabled or partially enabled)
+#define MAMTIM_Val            0x00000004
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+    
+#define XTAL        (12000000UL)        /* Oscillator frequency               */
+#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
+#define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */
+#define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
+
+/* F_cco0 = (2 * M * F_in) / N  */
+#define __M               (((PLL0CFG_Val      ) & 0x7FFF) + 1)
+#define __N               (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
+#define __FCCO(__F_IN)    ((2 * __M * __F_IN) / __N) 
+#define __CCLK_DIV        (((CCLKCFG_Val      ) & 0x00FF) + 1)
+
+/* Determine core clock frequency according to settings */
+ #if (PLL0_SETUP)
+    #if   ((CLKSRCSEL_Val & 0x03) == 1)
+        #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
+    #elif ((CLKSRCSEL_Val & 0x03) == 2)
+        #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
+    #else 
+        #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
+    #endif
+ #endif
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  /* Determine clock frequency according to clock register values             */
+  if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
+    switch (LPC_SC->CLKSRCSEL & 0x03) {
+      case 0:                                /* Int. RC oscillator => PLL0    */
+      case 3:                                /* Reserved, default to Int. RC  */
+        SystemCoreClock = (IRC_OSC * 
+                          (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   /
+                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+        break;
+      case 1:                                /* Main oscillator => PLL0       */
+        SystemCoreClock = (OSC_CLK * 
+                          (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   /
+                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+        break;
+      case 2:                                /* RTC oscillator => PLL0        */
+        SystemCoreClock = (RTC_CLK * 
+                          (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   /
+                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+        break;
+    }
+  } else {
+    switch (LPC_SC->CLKSRCSEL & 0x03) {
+      case 0:                                /* Int. RC oscillator => PLL0    */
+      case 3:                                /* Reserved, default to Int. RC  */
+        SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+        break;
+      case 1:                                /* Main oscillator => PLL0       */
+        SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+        break;
+      case 2:                                /* RTC oscillator => PLL0        */
+        SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+        break;
+    }
+  }
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemFrequency variable.
+ */
+void SystemInit (void)
+{
+#if (CLOCK_SETUP)                       /* Clock Setup                        */
+  LPC_SC->SCS       = SCS_Val;
+  if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
+    while ((LPC_SC->SCS & (1 << 6)) == 0);  /* Wait for Oscillator to be ready    */
+  }
+
+  LPC_SC->CCLKCFG   = CCLKCFG_Val;          /* Setup Clock Divider                */
+
+#if (PLL0_SETUP)
+  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;        /* Select Clock Source for PLL0       */
+  LPC_SC->PLL0CFG   = PLL0CFG_Val;
+  LPC_SC->PLL0CON   = 0x01;                 /* PLL0 Enable                        */
+  LPC_SC->PLL0FEED  = 0xAA;
+  LPC_SC->PLL0FEED  = 0x55;
+  while (!(LPC_SC->PLL0STAT & (1 << 26)));  /* Wait for PLOCK0                    */
+
+  LPC_SC->PLL0CON   = 0x03;                 /* PLL0 Enable & Connect              */
+  LPC_SC->PLL0FEED  = 0xAA;
+  LPC_SC->PLL0FEED  = 0x55;
+#endif
+
+  LPC_SC->USBCLKCFG = USBCLKCFG_Val;        /* Setup USB Clock Divider            */
+#endif
+
+  LPC_SC->PCLKSEL0  = PCLKSEL0_Val;         /* Peripheral Clock Selection         */
+  LPC_SC->PCLKSEL1  = PCLKSEL1_Val;
+
+  LPC_SC->PCONP     = PCONP_Val;            /* Power Control for Peripherals      */
+    
+  // Setup MAM
+  LPC_SC->MAMTIM      = MAMTIM_Val;
+  LPC_SC->MAMCR       = MAMCR_Val;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library
+ * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
+ *
+ * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
+ * based on cmsis system_LPC17xx.h 
+ */
+
+#ifndef __SYSTEM_LPC23xx_H
+#define __SYSTEM_LPC23xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+
+#ifdef __cplusplus
+}
+#endif 
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_defns.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library - Vectors 
+ * Copyright (c) 2006-2009 ARM Limited. All rights reserved. 
+ */
+
+#ifndef MBED_VECTOR_DEFNS_H
+#define MBED_VECTOR_DEFNS_H
+ 
+// Assember Macros 
+#ifdef __ARMCC_VERSION
+#define EXPORT(x) EXPORT x
+#define WEAK_EXPORT(x) EXPORT x [WEAK]
+#define IMPORT(x) IMPORT x
+#define LABEL(x) x
+#else        
+#define EXPORT(x) .global x
+#define WEAK_EXPORT(x) .weak x
+#define IMPORT(x) .global x
+#define LABEL(x) x:        
+#endif
+
+// RealMonitor
+// Requires RAM (0x40000040-0x4000011F) to be allocated by the linker
+
+// RealMonitor entry points
+#define rm_init_entry 0x7fffff91
+#define rm_undef_handler 0x7fffffa0
+#define rm_prefetchabort_handler 0x7fffffb0
+#define rm_dataabort_handler 0x7fffffc0
+#define rm_irqhandler2 0x7fffffe0
+//#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64
+#define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40
+
+// Unofficial RealMonitor entry points and variables
+#define RM_MSG_SWI 0x00940000 
+#define StateP 0x40000040 
+
+// VIC register addresses
+#define VIC_Base 0xfffff000
+#define VICAddress_Offset 0xf00
+#define VICVectAddr2_Offset 0x108
+#define VICVectAddr3_Offset 0x10c
+#define VICIntEnClr_Offset 0x014
+#define VICIntEnClr    (*(volatile unsigned long *)(VIC_Base + 0x014))
+#define VICVectAddr2   (*(volatile unsigned long *)(VIC_Base + 0x108))
+#define VICVectAddr3   (*(volatile unsigned long *)(VIC_Base + 0x10C))
+
+// ARM Mode bits and Interrupt flags in PSRs
+#define Mode_USR 0x10
+#define Mode_FIQ 0x11
+#define Mode_IRQ 0x12
+#define Mode_SVC 0x13
+#define Mode_ABT 0x17
+#define Mode_UND 0x1B
+#define Mode_SYS 0x1F
+#define I_Bit 0x80    // when I bit is set, IRQ is disabled
+#define F_Bit 0x40    // when F bit is set, FIQ is disabled
+
+// MCU RAM
+#define LPC2368_RAM_ADDRESS 0x40000000	// RAM Base
+#define LPC2368_RAM_SIZE 0x8000		// 32KB 
+
+// ISR Stack Allocation
+#define UND_stack_size  0x00000040
+#define SVC_stack_size  0x00000040
+#define ABT_stack_size  0x00000040
+#define FIQ_stack_size  0x00000000
+#define IRQ_stack_size  0x00000040
+
+#define ISR_stack_size  (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size)
+
+// Full Descending Stack, so top-most stack points to just above the top of RAM
+#define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE)
+#define USR_STACK_TOP	  (LPC2368_STACK_TOP - ISR_stack_size)
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/vector_realmonitor.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,22 @@
+/* mbed Microcontroller Library - RealMonitor
+ * Copyright (c) 2006-2009 ARM Limited. All rights reserved. 
+ */
+#include "vector_defns.h"
+
+extern void __mbed_dcc_irq(void);
+
+/* Function: __mbed_init_realmonitor
+ * Setup the RealMonitor DCC Interrupt Handlers
+ */
+void __mbed_init_realmonitor(void) __attribute__((weak));
+void __mbed_init_realmonitor() {
+    // Disable all interrupts
+    VICIntEnClr = 0xffffffff;
+  
+    // Set DCC interrupt vector addresses
+    VICVectAddr2 = (unsigned)&__mbed_dcc_irq;
+    VICVectAddr3 = (unsigned)&__mbed_dcc_irq;  
+
+    // Initialise RealMonitor
+    ((void (*)(void))rm_init_entry)();
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,687 @@
+/****************************************************************************
+ *   $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694                     $
+ *   Project: NXP LPC8xx software example
+ *
+ *   Description:
+ *     CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
+ *     NXP LPC800 Device Series
+ *
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors'
+ * relevant copyright in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+****************************************************************************/
+#ifndef __LPC8xx_H__
+#define __LPC8xx_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup LPC8xx_Definitions LPC8xx Definitions
+  This file defines all structures and symbols for LPC8xx:
+    - Registers and bitfields
+    - peripheral base address
+    - PIO definitions
+  @{
+*/
+
+
+/******************************************************************************/
+/*                Processor and Core Peripherals                              */
+/******************************************************************************/
+/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
+  Configuration of the Cortex-M0+ Processor and Core Peripherals
+  @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
+  Reset_IRQn                    = -15,    /*!< 1 Reset Vector, invoked on Power up and warm reset*/
+  NonMaskableInt_IRQn           = -14,    /*!< 2 Non Maskable Interrupt                           */
+  HardFault_IRQn                = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                   */
+  SVCall_IRQn                   = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                     */
+  PendSV_IRQn                   = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                     */
+  SysTick_IRQn                  = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                 */
+
+/******  LPC8xx Specific Interrupt Numbers ********************************************************/
+  SPI0_IRQn                     = 0,        /*!< SPI0                                             */
+  SPI1_IRQn                     = 1,        /*!< SPI1                                             */
+  Reserved0_IRQn                = 2,        /*!< Reserved Interrupt                               */
+  UART0_IRQn                    = 3,        /*!< USART0                                            */
+  UART1_IRQn                    = 4,        /*!< USART1                                            */
+  UART2_IRQn                    = 5,        /*!< USART2                                            */
+  Reserved1_IRQn                = 6,        /*!< Reserved Interrupt                               */
+  Reserved2_IRQn                = 7,        /*!< Reserved Interrupt                               */
+  I2C_IRQn                      = 8,        /*!< I2C                                              */
+  SCT_IRQn                      = 9,        /*!< SCT                                              */
+  MRT_IRQn                      = 10,       /*!< MRT                                              */
+  CMP_IRQn                      = 11,       /*!< CMP                                              */
+  WDT_IRQn                      = 12,      /*!< WDT                                              */
+  BOD_IRQn                      = 13,       /*!< BOD                                              */
+  Reserved3_IRQn                = 14,       /*!< Reserved Interrupt                               */
+  WKT_IRQn                      = 15,       /*!< WKT Interrupt                                    */
+  Reserved4_IRQn                = 16,       /*!< Reserved Interrupt                               */
+  Reserved5_IRQn                = 17,       /*!< Reserved Interrupt                               */
+  Reserved6_IRQn                = 18,       /*!< Reserved Interrupt                               */
+  Reserved7_IRQn                = 19,       /*!< Reserved Interrupt                               */
+  Reserved8_IRQn                = 20,       /*!< Reserved Interrupt                               */
+  Reserved9_IRQn                = 21,       /*!< Reserved Interrupt                               */
+  Reserved10_IRQn               = 22,       /*!< Reserved Interrupt                               */
+  Reserved11_IRQn               = 23,       /*!< Reserved Interrupt                               */
+  PININT0_IRQn               	  = 24,       /*!< External Interrupt 0                             */
+  PININT1_IRQn                  = 25,       /*!< External Interrupt 1                             */
+  PININT2_IRQn                  = 26,       /*!< External Interrupt 2                             */
+  PININT3_IRQn                  = 27,       /*!< External Interrupt 3                             */
+  PININT4_IRQn                  = 28,       /*!< External Interrupt 4                             */
+  PININT5_IRQn                  = 29,       /*!< External Interrupt 5                             */
+  PININT6_IRQn                  = 30,       /*!< External Interrupt 6                             */
+  PININT7_IRQn                  = 31,       /*!< External Interrupt 7                             */
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
+#define __MPU_PRESENT             0         /*!< MPU present or not                               */
+#define __VTOR_PRESENT            1         /**< Defines if an VTOR is present or not */
+#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+
+/*@}*/ /* end of group LPC8xx_CMSIS */
+
+
+#include "core_cm0plus.h"                  /* Cortex-M0+ processor and core peripherals          */
+#include "system_LPC8xx.h"                 /* System Header                                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral Registers structures             */
+/******************************************************************************/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+/** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t SYSMEMREMAP;            /*!< Offset: 0x000 System memory remap (R/W) */
+  __IO uint32_t PRESETCTRL;             /*!< Offset: 0x004 Peripheral reset control (R/W) */
+  __IO uint32_t SYSPLLCTRL;             /*!< Offset: 0x008 System PLL control (R/W) */
+  __IO uint32_t SYSPLLSTAT;             /*!< Offset: 0x00C System PLL status (R/W ) */
+       uint32_t RESERVED0[4];
+
+  __IO uint32_t SYSOSCCTRL;             /*!< Offset: 0x020 System oscillator control (R/W) */
+  __IO uint32_t WDTOSCCTRL;             /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
+       uint32_t RESERVED1[2];
+  __IO uint32_t SYSRSTSTAT;             /*!< Offset: 0x030 System reset status Register (R/W ) */
+       uint32_t RESERVED2[3];
+  __IO uint32_t SYSPLLCLKSEL;           /*!< Offset: 0x040 System PLL clock source select (R/W) */
+  __IO uint32_t SYSPLLCLKUEN;           /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
+       uint32_t RESERVED3[10];
+
+  __IO uint32_t MAINCLKSEL;             /*!< Offset: 0x070 Main clock source select (R/W) */
+  __IO uint32_t MAINCLKUEN;             /*!< Offset: 0x074 Main clock source update enable (R/W) */
+  __IO uint32_t SYSAHBCLKDIV;           /*!< Offset: 0x078 System AHB clock divider (R/W) */
+       uint32_t RESERVED4[1];
+
+  __IO uint32_t SYSAHBCLKCTRL;          /*!< Offset: 0x080 System AHB clock control (R/W) */
+       uint32_t RESERVED5[4];
+  __IO uint32_t UARTCLKDIV;             /*!< Offset: 0x094 UART clock divider (R/W) */
+       uint32_t RESERVED6[18];
+
+  __IO uint32_t CLKOUTSEL;              /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
+  __IO uint32_t CLKOUTUEN;              /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
+  __IO uint32_t CLKOUTDIV;              /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
+       uint32_t RESERVED7;
+  __IO uint32_t UARTFRGDIV;             /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
+  __IO uint32_t UARTFRGMULT;             /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
+       uint32_t RESERVED8[1];
+  __IO uint32_t EXTTRACECMD;            /*!< (@ 0x400480FC) External trace buffer command register  */
+  __IO uint32_t PIOPORCAP0;             /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
+       uint32_t RESERVED9[12];
+  __IO uint32_t IOCONCLKDIV[7];       /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
+  __IO uint32_t BODCTRL;                /*!< Offset: 0x150 BOD control (R/W) */
+  __IO uint32_t SYSTCKCAL;              /*!< Offset: 0x154 System tick counter calibration (R/W) */
+       uint32_t RESERVED10[6];
+  __IO uint32_t IRQLATENCY;             /*!< (@ 0x40048170) IRQ delay */
+  __IO uint32_t NMISRC;                 /*!< (@ 0x40048174) NMI Source Control     */
+  __IO uint32_t PINTSEL[8];             /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
+       uint32_t RESERVED11[27];
+  __IO uint32_t STARTERP0;              /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
+       uint32_t RESERVED12[3];
+  __IO uint32_t STARTERP1;              /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
+       uint32_t RESERVED13[6];
+  __IO uint32_t PDSLEEPCFG;             /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
+  __IO uint32_t PDAWAKECFG;             /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
+  __IO uint32_t PDRUNCFG;               /*!< Offset: 0x238 Power-down configuration Register (R/W) */
+       uint32_t RESERVED14[110];
+  __I  uint32_t DEVICE_ID;              /*!< Offset: 0x3F4 Device ID (R/ ) */
+} LPC_SYSCON_TypeDef;
+/*@}*/ /* end of group LPC8xx_SYSCON */
+
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3  (IOCONFIG)
+  */
+
+typedef struct {                            /*!< (@ 0x40044000) IOCONFIG Structure     */
+  __IO uint32_t PIO0_17;                    /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
+  __IO uint32_t PIO0_13;                    /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
+  __IO uint32_t PIO0_12;                    /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
+  __IO uint32_t PIO0_5;                     /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
+  __IO uint32_t PIO0_4;                     /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
+  __IO uint32_t PIO0_3;                     /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
+  __IO uint32_t PIO0_2;                     /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
+  __IO uint32_t PIO0_11;                    /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
+  __IO uint32_t PIO0_10;                    /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
+  __IO uint32_t PIO0_16;                    /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
+  __IO uint32_t PIO0_15;                    /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
+  __IO uint32_t PIO0_1;                     /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
+  __IO uint32_t Reserved;                   /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
+  __IO uint32_t PIO0_9;                     /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
+  __IO uint32_t PIO0_8;                     /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
+  __IO uint32_t PIO0_7;                     /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
+  __IO uint32_t PIO0_6;                     /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
+  __IO uint32_t PIO0_0;                     /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
+  __IO uint32_t PIO0_14;                    /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
+} LPC_IOCON_TypeDef;
+/*@}*/ /* end of group LPC8xx_IOCON */
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3  (FLASHCTRL)
+  */
+typedef struct {                            /*!< (@ 0x40040000) FLASHCTRL Structure    */
+  __I  uint32_t  RESERVED0[4];
+  __IO uint32_t  FLASHCFG;                          /*!< (@ 0x40040010) Flash configuration register                           */
+  __I  uint32_t  RESERVED1[3];
+  __IO uint32_t  FMSSTART;                          /*!< (@ 0x40040020) Signature start address register                       */
+  __IO uint32_t  FMSSTOP;                           /*!< (@ 0x40040024) Signature stop-address register                        */
+  __I  uint32_t  RESERVED2;
+  __I  uint32_t  FMSW0;
+} LPC_FLASHCTRL_TypeDef;
+/*@}*/ /* end of group LPC8xx_FLASHCTRL */
+
+
+/*------------- Power Management Unit (PMU) --------------------------*/
+/** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t PCON;                   /*!< Offset: 0x000 Power control Register (R/W) */
+  __IO uint32_t GPREG0;                 /*!< Offset: 0x004 General purpose Register 0 (R/W) */
+  __IO uint32_t GPREG1;                 /*!< Offset: 0x008 General purpose Register 1 (R/W) */
+  __IO uint32_t GPREG2;                 /*!< Offset: 0x00C General purpose Register 2 (R/W) */
+  __IO uint32_t GPREG3;                 /*!< Offset: 0x010 General purpose Register 3 (R/W) */
+  __IO uint32_t DPDCTRL;                /*!< Offset: 0x014 Deep power-down control register (R/W) */
+} LPC_PMU_TypeDef;
+/*@}*/ /* end of group LPC8xx_PMU */
+
+
+/*------------- Switch Matrix Port --------------------------*/
+/** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
+  @{
+*/
+typedef struct
+{
+  union {
+    __IO uint32_t PINASSIGN[9];
+    struct {
+      __IO uint32_t PINASSIGN0;
+      __IO uint32_t PINASSIGN1;
+      __IO uint32_t PINASSIGN2;
+      __IO uint32_t PINASSIGN3;
+      __IO uint32_t PINASSIGN4;
+      __IO uint32_t PINASSIGN5;
+      __IO uint32_t PINASSIGN6;
+      __IO uint32_t PINASSIGN7;
+      __IO uint32_t PINASSIGN8;
+    };
+  };
+  __I  uint32_t  RESERVED0[103];
+  __IO uint32_t  PINENABLE0;
+} LPC_SWM_TypeDef;
+/*@}*/ /* end of group LPC8xx_SWM */
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                       GPIO_PORT                                      -----
+// ------------------------------------------------------------------------------------------------
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (GPIO_PORT)
+  */
+
+typedef struct {
+  __IO uint8_t B0[18];                   /*!< (@ 0xA0000000) Byte pin registers port 0 */
+  __I  uint16_t RESERVED0[2039];
+  __IO uint32_t W0[18];                  /*!< (@ 0xA0001000) Word pin registers port 0 */
+       uint32_t RESERVED1[1006];
+  __IO uint32_t DIR0;                          /* 0x2000 */
+       uint32_t RESERVED2[31];
+  __IO uint32_t MASK0;                                  /* 0x2080 */
+       uint32_t RESERVED3[31];
+  __IO uint32_t PIN0;                          /* 0x2100 */
+       uint32_t RESERVED4[31];
+  __IO uint32_t MPIN0;                                   /* 0x2180 */
+       uint32_t RESERVED5[31];
+  __IO uint32_t SET0;                         /* 0x2200 */
+       uint32_t RESERVED6[31];
+  __O  uint32_t CLR0;                         /* 0x2280 */
+       uint32_t RESERVED7[31];
+  __O  uint32_t NOT0;                                    /* 0x2300 */
+
+} LPC_GPIO_PORT_TypeDef;
+
+
+// ------------------------------------------------------------------------------------------------
+// -----                                     PIN_INT                                     -----
+// ------------------------------------------------------------------------------------------------
+
+/**
+  * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (PIN_INT)
+  */
+
+typedef struct {                            /*!< (@ 0xA0004000) PIN_INT Structure */
+  __IO uint32_t ISEL;                       /*!< (@ 0xA0004000) Pin Interrupt Mode register */
+  __IO uint32_t IENR;                       /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
+  __IO uint32_t SIENR;                      /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
+  __IO uint32_t CIENR;                      /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
+  __IO uint32_t IENF;                       /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
+  __IO uint32_t SIENF;                      /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+  __IO uint32_t CIENF;                      /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+  __IO uint32_t RISE;                       /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
+  __IO uint32_t FALL;                       /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
+  __IO uint32_t IST;                        /*!< (@ 0xA0004024) Pin Interrupt Status register */
+  __IO uint32_t PMCTRL;                     /*!< (@ 0xA0004028) GPIO pattern match interrupt control register          */
+  __IO uint32_t PMSRC;                      /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
+  __IO uint32_t PMCFG;                      /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
+} LPC_PIN_INT_TypeDef;
+
+
+/*------------- CRC Engine (CRC) -----------------------------------------*/
+/** @addtogroup LPC8xx_CRC
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t MODE;
+  __IO uint32_t SEED;
+  union {
+  __I  uint32_t SUM;
+  __O  uint32_t WR_DATA_DWORD;
+  __O  uint16_t WR_DATA_WORD;
+       uint16_t RESERVED_WORD;
+  __O  uint8_t WR_DATA_BYTE;
+       uint8_t RESERVED_BYTE[3];
+  };
+} LPC_CRC_TypeDef;
+/*@}*/ /* end of group LPC8xx_CRC */
+
+/*------------- Comparator (CMP) --------------------------------------------------*/
+/** @addtogroup LPC8xx_CMP LPC8xx Comparator
+  @{
+*/
+typedef struct {                            /*!< (@ 0x40024000) CMP Structure          */
+  __IO uint32_t  CTRL;                      /*!< (@ 0x40024000) Comparator control register */
+  __IO uint32_t  LAD;                       /*!< (@ 0x40024004) Voltage ladder register */
+} LPC_CMP_TypeDef;
+/*@}*/ /* end of group LPC8xx_CMP */
+
+
+/*------------- Wakeup Timer (WKT) --------------------------------------------------*/
+/** @addtogroup LPC8xx_WKT
+  @{
+*/
+typedef struct {                            /*!< (@ 0x40028000) WKT Structure          */
+  __IO uint32_t  CTRL;                      /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
+       uint32_t  Reserved[2];
+  __IO uint32_t  COUNT;                     /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
+} LPC_WKT_TypeDef;
+/*@}*/ /* end of group LPC8xx_WKT */
+
+
+/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
+typedef struct {
+__IO uint32_t INTVAL;
+__IO uint32_t TIMER;
+__IO uint32_t CTRL;
+__IO uint32_t STAT;
+} MRT_Channel_cfg_Type;
+
+typedef struct {
+  MRT_Channel_cfg_Type Channel[4];
+   uint32_t Reserved0[1];
+  __IO uint32_t IDLE_CH;
+  __IO uint32_t IRQ_FLAG;
+} LPC_MRT_TypeDef;
+
+
+/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
+/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
+  @{
+*/
+/**
+  * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9  (USART)
+  */
+typedef struct
+{
+  __IO uint32_t  CFG;								/* 0x00 */
+  __IO uint32_t  CTRL;
+  __IO uint32_t  STAT;
+  __IO uint32_t  INTENSET;
+  __O  uint32_t  INTENCLR;					/* 0x10 */
+  __I  uint32_t  RXDATA;
+  __I  uint32_t  RXDATA_STAT;
+  __IO uint32_t  TXDATA;
+  __IO uint32_t  BRG;								/* 0x20 */
+  __IO uint32_t  INTSTAT;
+} LPC_USART_TypeDef;
+
+/*@}*/ /* end of group LPC8xx_USART */
+
+
+/*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
+/** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t  CFG;			    /* 0x00 */
+  __IO uint32_t  DLY;
+  __IO uint32_t  STAT;
+  __IO uint32_t  INTENSET;
+  __O  uint32_t  INTENCLR;		/* 0x10 */
+  __I  uint32_t  RXDAT;
+  __IO uint32_t  TXDATCTL;
+  __IO uint32_t  TXDAT;
+  __IO uint32_t  TXCTRL;		  /* 0x20 */
+  __IO uint32_t  DIV;
+  __I  uint32_t  INTSTAT;
+} LPC_SPI_TypeDef;
+/*@}*/ /* end of group LPC8xx_SPI */
+
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+/** @addtogroup LPC8xx_I2C I2C-Bus Interface
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t  CFG;			  /* 0x00 */
+  __IO uint32_t  STAT;
+  __IO uint32_t  INTENSET;
+  __O  uint32_t  INTENCLR;
+  __IO uint32_t  TIMEOUT;		/* 0x10 */
+  __IO uint32_t  DIV;
+  __IO uint32_t  INTSTAT;
+       uint32_t  Reserved0[1];
+  __IO uint32_t  MSTCTL;			  /* 0x20 */
+  __IO uint32_t  MSTTIME;
+  __IO uint32_t  MSTDAT;
+       uint32_t  Reserved1[5];
+  __IO uint32_t  SLVCTL;			  /* 0x40 */
+  __IO uint32_t  SLVDAT;
+  __IO uint32_t  SLVADR0;
+  __IO uint32_t  SLVADR1;
+  __IO uint32_t  SLVADR2;			  /* 0x50 */
+  __IO uint32_t  SLVADR3;
+  __IO uint32_t  SLVQUAL0;
+       uint32_t  Reserved2[9];
+  __I  uint32_t  MONRXDAT;			/* 0x80 */
+} LPC_I2C_TypeDef;
+
+/*@}*/ /* end of group LPC8xx_I2C */
+
+/**
+  * @brief State Configurable Timer (SCT) (SCT)
+  */
+
+/**
+  * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7  (SCT)
+  */
+
+#define CONFIG_SCT_nEV   (6)             /* Number of events */
+#define CONFIG_SCT_nRG   (5)             /* Number of match/compare registers */
+#define CONFIG_SCT_nOU   (4)             /* Number of outputs */
+
+typedef struct
+{
+    __IO  uint32_t CONFIG;              /* 0x000 Configuration Register */
+    union {
+        __IO uint32_t CTRL_U;           /* 0x004 Control Register */
+        struct {
+            __IO uint16_t CTRL_L;       /* 0x004 low control register */
+            __IO uint16_t CTRL_H;       /* 0x006 high control register */
+        };
+    };
+    __IO uint16_t LIMIT_L;              /* 0x008 limit register for counter L */
+    __IO uint16_t LIMIT_H;              /* 0x00A limit register for counter H */
+    __IO uint16_t HALT_L;               /* 0x00C halt register for counter L */
+    __IO uint16_t HALT_H;               /* 0x00E halt register for counter H */
+    __IO uint16_t STOP_L;               /* 0x010 stop register for counter L */
+    __IO uint16_t STOP_H;               /* 0x012 stop register for counter H */
+    __IO uint16_t START_L;              /* 0x014 start register for counter L */
+    __IO uint16_t START_H;              /* 0x016 start register for counter H */
+         uint32_t RESERVED1[10];        /* 0x018-0x03C reserved */
+    union {
+        __IO uint32_t COUNT_U;          /* 0x040 counter register */
+        struct {
+            __IO uint16_t COUNT_L;      /* 0x040 counter register for counter L */
+            __IO uint16_t COUNT_H;      /* 0x042 counter register for counter H */
+        };
+    };
+    __IO uint16_t STATE_L;              /* 0x044 state register for counter L */
+    __IO uint16_t STATE_H;              /* 0x046 state register for counter H */
+    __I  uint32_t INPUT;                /* 0x048 input register */
+    __IO uint16_t REGMODE_L;            /* 0x04C match - capture registers mode register L */
+    __IO uint16_t REGMODE_H;            /* 0x04E match - capture registers mode register H */
+    __IO uint32_t OUTPUT;               /* 0x050 output register */
+    __IO uint32_t OUTPUTDIRCTRL;        /* 0x054 Output counter direction Control Register */
+    __IO uint32_t RES;                  /* 0x058 conflict resolution register */
+         uint32_t RESERVED2[37];        /* 0x05C-0x0EC reserved */
+    __IO uint32_t EVEN;                 /* 0x0F0 event enable register */
+    __IO uint32_t EVFLAG;               /* 0x0F4 event flag register */
+    __IO uint32_t CONEN;                /* 0x0F8 conflict enable register */
+    __IO uint32_t CONFLAG;              /* 0x0FC conflict flag register */
+
+    union {
+        __IO union {                    /* 0x100-... Match / Capture value */
+            uint32_t U;                 /*       SCTMATCH[i].U  Unified 32-bit register */
+            struct {
+                uint16_t L;             /*       SCTMATCH[i].L  Access to L value */
+                uint16_t H;             /*       SCTMATCH[i].H  Access to H value */
+            };
+        } MATCH[CONFIG_SCT_nRG];
+        __I union {
+            uint32_t U;                 /*       SCTCAP[i].U  Unified 32-bit register */
+            struct {
+                uint16_t L;             /*       SCTCAP[i].L  Access to H value */
+                uint16_t H;             /*       SCTCAP[i].H  Access to H value */
+            };
+        } CAP[CONFIG_SCT_nRG];
+    };
+
+
+         uint32_t RESERVED3[32-CONFIG_SCT_nRG];      /* ...-0x17C reserved */
+
+    union {
+        __IO uint16_t MATCH_L[CONFIG_SCT_nRG];       /* 0x180-... Match Value L counter */
+        __I  uint16_t CAP_L[CONFIG_SCT_nRG];         /* 0x180-... Capture Value L counter */
+    };
+         uint16_t RESERVED4[32-CONFIG_SCT_nRG];      /* ...-0x1BE reserved */
+    union {
+        __IO uint16_t MATCH_H[CONFIG_SCT_nRG];       /* 0x1C0-... Match Value H counter */
+        __I  uint16_t CAP_H[CONFIG_SCT_nRG];         /* 0x1C0-... Capture Value H counter */
+    };
+
+         uint16_t RESERVED5[32-CONFIG_SCT_nRG];      /* ...-0x1FE reserved */
+
+
+    union {
+        __IO union {                    /* 0x200-... Match Reload / Capture Control value */
+            uint32_t U;                 /*       SCTMATCHREL[i].U  Unified 32-bit register */
+            struct {
+                uint16_t L;             /*       SCTMATCHREL[i].L  Access to L value */
+                uint16_t H;             /*       SCTMATCHREL[i].H  Access to H value */
+            };
+        } MATCHREL[CONFIG_SCT_nRG];
+        __IO union {
+            uint32_t U;                 /*       SCTCAPCTRL[i].U  Unified 32-bit register */
+            struct {
+                uint16_t L;             /*       SCTCAPCTRL[i].L  Access to H value */
+                uint16_t H;             /*       SCTCAPCTRL[i].H  Access to H value */
+            };
+        } CAPCTRL[CONFIG_SCT_nRG];
+    };
+
+         uint32_t RESERVED6[32-CONFIG_SCT_nRG];      /* ...-0x27C reserved */
+
+    union {
+        __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG];    /* 0x280-... Match Reload value L counter */
+        __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG];     /* 0x280-... Capture Control value L counter */
+    };
+         uint16_t RESERVED7[32-CONFIG_SCT_nRG];      /* ...-0x2BE reserved */
+    union {
+        __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG];    /* 0x2C0-... Match Reload value H counter */
+        __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG];     /* 0x2C0-... Capture Control value H counter */
+    };
+         uint16_t RESERVED8[32-CONFIG_SCT_nRG];      /* ...-0x2FE reserved */
+
+    __IO struct {                       /* 0x300-0x3FC  SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
+        uint32_t STATE;                 /* Event State Register */
+        uint32_t CTRL;                  /* Event Control Register */
+    } EVENT[CONFIG_SCT_nEV];
+
+         uint32_t RESERVED9[128-2*CONFIG_SCT_nEV];   /* ...-0x4FC reserved */
+
+    __IO struct {                       /* 0x500-0x57C  SCTOUT[i].SET / SCTOUT[i].CLR */
+        uint32_t SET;                   /* Output n Set Register */
+        uint32_t CLR;                   /* Output n Clear Register */
+    } OUT[CONFIG_SCT_nOU];
+
+         uint32_t RESERVED10[191-2*CONFIG_SCT_nOU];  /* ...-0x7F8 reserved */
+
+    __I  uint32_t MODULECONTENT;        /* 0x7FC Module Content */
+
+} LPC_SCT_TypeDef;
+/*@}*/ /* end of group LPC8xx_SCT */
+
+
+/*------------- Watchdog Timer (WWDT) -----------------------------------------*/
+/** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t MOD;                    /*!< Offset: 0x000 Watchdog mode register (R/W) */
+  __IO uint32_t TC;                     /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
+  __O  uint32_t FEED;                   /*!< Offset: 0x008 Watchdog feed sequence register (W) */
+  __I  uint32_t TV;                     /*!< Offset: 0x00C Watchdog timer value register (R) */
+       uint32_t RESERVED;               /*!< Offset: 0x010 RESERVED                          */
+  __IO uint32_t WARNINT;                /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
+  __IO uint32_t WINDOW;                 /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
+} LPC_WWDT_TypeDef;
+/*@}*/ /* end of group LPC8xx_WDT */
+
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* Base addresses                                                             */
+#define LPC_FLASH_BASE        (0x00000000UL)
+#define LPC_RAM_BASE          (0x10000000UL)
+#define LPC_ROM_BASE          (0x1FFF0000UL)
+#define LPC_APB0_BASE         (0x40000000UL)
+#define LPC_AHB_BASE          (0x50000000UL)
+
+/* APB0 peripherals */
+#define LPC_WWDT_BASE         (LPC_APB0_BASE + 0x00000)
+#define LPC_MRT_BASE          (LPC_APB0_BASE + 0x04000)
+#define LPC_WKT_BASE          (LPC_APB0_BASE + 0x08000)
+#define LPC_SWM_BASE          (LPC_APB0_BASE + 0x0C000)
+#define LPC_PMU_BASE          (LPC_APB0_BASE + 0x20000)
+#define LPC_CMP_BASE          (LPC_APB0_BASE + 0x24000)
+
+#define LPC_FLASHCTRL_BASE    (LPC_APB0_BASE + 0x40000)
+#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x44000)
+#define LPC_SYSCON_BASE       (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C_BASE          (LPC_APB0_BASE + 0x50000)
+#define LPC_SPI0_BASE         (LPC_APB0_BASE + 0x58000)
+#define LPC_SPI1_BASE         (LPC_APB0_BASE + 0x5C000)
+#define LPC_USART0_BASE       (LPC_APB0_BASE + 0x64000)
+#define LPC_USART1_BASE       (LPC_APB0_BASE + 0x68000)
+#define LPC_USART2_BASE       (LPC_APB0_BASE + 0x6C000)
+
+/* AHB peripherals                                                            */
+#define LPC_CRC_BASE         (LPC_AHB_BASE + 0x00000)
+#define LPC_SCT_BASE         (LPC_AHB_BASE + 0x04000)
+
+#define LPC_GPIO_PORT_BASE    (0xA0000000)
+#define LPC_PIN_INT_BASE     (LPC_GPIO_PORT_BASE  + 0x4000)
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+#define LPC_WWDT              ((LPC_WWDT_TypeDef   *) LPC_WWDT_BASE  )
+#define LPC_MRT               ((LPC_MRT_TypeDef    *) LPC_MRT_BASE   )
+
+
+#define LPC_WKT               ((LPC_WKT_TypeDef    *) LPC_WKT_BASE   )
+#define LPC_SWM               ((LPC_SWM_TypeDef    *) LPC_SWM_BASE   )
+#define LPC_PMU               ((LPC_PMU_TypeDef    *) LPC_PMU_BASE   )
+#define LPC_CMP               ((LPC_CMP_TypeDef    *) LPC_CMP_BASE   )
+
+#define LPC_FLASHCTRL         ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
+#define LPC_IOCON             ((LPC_IOCON_TypeDef  *) LPC_IOCON_BASE )
+#define LPC_SYSCON            ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
+#define LPC_I2C               ((LPC_I2C_TypeDef    *) LPC_I2C_BASE   )
+#define LPC_SPI0              ((LPC_SPI_TypeDef    *) LPC_SPI0_BASE  )
+#define LPC_SPI1              ((LPC_SPI_TypeDef    *) LPC_SPI1_BASE  )
+#define LPC_USART0            ((LPC_USART_TypeDef   *) LPC_USART0_BASE )
+#define LPC_USART1            ((LPC_USART_TypeDef   *) LPC_USART1_BASE )
+#define LPC_USART2            ((LPC_USART_TypeDef   *) LPC_USART2_BASE )
+
+#define LPC_CRC               ((LPC_CRC_TypeDef    *) LPC_CRC_BASE   )
+#define LPC_SCT               ((LPC_SCT_TypeDef    *) LPC_SCT_BASE   )
+
+#define LPC_GPIO_PORT         ((LPC_GPIO_PORT_TypeDef  *) LPC_GPIO_PORT_BASE  )
+#define LPC_PIN_INT          ((LPC_PIN_INT_TypeDef   *) LPC_PIN_INT_BASE  )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __LPC8xx_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/LPC812.sct	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x4000  {    ; load region size_region (32k)
+  ER_IROM1 0x00000000 0x4000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
+  ; 8KB - 0xC0 = 0xF40
+  RW_IRAM1 0x100000C0 0xF40  {
+   .ANY (+RW +ZI)
+  }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,211 @@
+;/*****************************************************************************
+; * @file:    startup_LPC8xx.s
+; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
+; *           for the NXP LPC8xx Device Series
+; * @version: V1.0
+; * @date:    16. Aug. 2012
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+Stack_Mem       SPACE   Stack_Size
+__initial_sp            EQU     0x10001000
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     SPI0_IRQHandler             ; SPI0 controller
+                DCD     SPI1_IRQHandler             ; SPI1 controller
+                DCD     0                           ; Reserved
+                DCD     UART0_IRQHandler            ; UART0
+                DCD     UART1_IRQHandler            ; UART1
+                DCD     UART2_IRQHandler            ; UART2
+                DCD     0                           ; Reserved
+                DCD     0                           ; Reserved
+                DCD     I2C_IRQHandler              ; I2C controller
+                DCD     SCT_IRQHandler              ; Smart Counter Timer
+                DCD     MRT_IRQHandler              ; Multi-Rate Timer
+                DCD     CMP_IRQHandler              ; Comparator
+                DCD     WDT_IRQHandler              ; PIO1 (0:11)
+                DCD     BOD_IRQHandler              ; Brown Out Detect
+                DCD     0                           ; Reserved
+                DCD     WKT_IRQHandler              ; Wakeup timer
+                DCD     0                           ; Reserved
+                DCD     0                           ; Reserved
+                DCD     0                           ; Reserved
+                DCD     0                           ; Reserved
+                DCD     0                           ; Reserved
+                DCD     0                           ; Reserved
+                DCD     0                           ; Reserved
+                DCD     0                           ; Reserved
+                DCD     PININT0_IRQHandler          ; PIO INT0
+                DCD     PININT1_IRQHandler         ; PIO INT1
+                DCD     PININT2_IRQHandler         ; PIO INT2
+                DCD     PININT3_IRQHandler         ; PIO INT3
+                DCD     PININT4_IRQHandler         ; PIO INT4
+                DCD     PININT5_IRQHandler         ; PIO INT5
+                DCD     PININT6_IRQHandler         ; PIO INT6
+                DCD     PININT7_IRQHandler         ; PIO INT7
+
+
+                IF      :LNOT::DEF:NO_CRP
+                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key         DCD     0xFFFFFFFF
+                ENDIF
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler     PROC
+;                EXPORT  NMI_Handler               [WEAK]
+;                B       .
+;                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  NMI_Handler               [WEAK]
+                EXPORT  SPI0_IRQHandler           [WEAK]
+                EXPORT  SPI1_IRQHandler           [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  SCT_IRQHandler            [WEAK]
+                EXPORT  MRT_IRQHandler            [WEAK]
+                EXPORT  CMP_IRQHandler            [WEAK]
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  BOD_IRQHandler            [WEAK]
+
+                EXPORT  WKT_IRQHandler            [WEAK]
+
+                EXPORT  PININT0_IRQHandler      [WEAK]
+                EXPORT  PININT1_IRQHandler      [WEAK]
+                EXPORT  PININT2_IRQHandler      [WEAK]
+                EXPORT  PININT3_IRQHandler      [WEAK]
+                EXPORT  PININT4_IRQHandler      [WEAK]
+                EXPORT  PININT5_IRQHandler      [WEAK]
+                EXPORT  PININT6_IRQHandler      [WEAK]
+                EXPORT  PININT7_IRQHandler      [WEAK]
+
+NMI_Handler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C_IRQHandler
+SCT_IRQHandler
+MRT_IRQHandler
+CMP_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+WKT_IRQHandler
+PININT0_IRQHandler
+PININT1_IRQHandler
+PININT2_IRQHandler
+PININT3_IRQHandler
+PININT4_IRQHandler
+PININT5_IRQHandler
+PININT6_IRQHandler
+PININT7_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TOOLCHAIN_ARM_MICRO/sys.cpp	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * A generic CMSIS include header, pulling in LPC8xx specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC8xx.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+#include "cmsis_nvic.h"
+
+#define NVIC_NUM_VECTORS (16 + 32)            // CORE + MCU Peripherals
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000)  // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0)       // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + 16];
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC81X/cmsis_nvic.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,23 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,367 @@
+/******************************************************************************
+ * @file:    system_LPC8xx.c
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
+ *           for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date:    16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#include <stdint.h>
+#include "LPC8xx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+//   <h> System Oscillator Control Register (SYSOSCCTRL)
+//     <o1.0>      BYPASS: System Oscillator Bypass Enable
+//                     <i> If enabled then PLL input (sys_osc_clk) is fed
+//                     <i> directly from XTALIN and XTALOUT pins.
+//     <o1.9>      FREQRANGE: System Oscillator Frequency Range
+//                     <i> Determines frequency range for Low-power oscillator.
+//                   <0=> 1 - 20 MHz
+//                   <1=> 15 - 25 MHz
+//   </h>
+//
+//   <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
+//     <o2.0..4>   DIVSEL: Select Divider for Fclkana
+//                     <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
+//                   <0-31>
+//     <o2.5..8>   FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+//                   <0=> Undefined
+//                   <1=> 0.5 MHz
+//                   <2=> 0.8 MHz
+//                   <3=> 1.1 MHz
+//                   <4=> 1.4 MHz
+//                   <5=> 1.6 MHz
+//                   <6=> 1.8 MHz
+//                   <7=> 2.0 MHz
+//                   <8=> 2.2 MHz
+//                   <9=> 2.4 MHz
+//                   <10=> 2.6 MHz
+//                   <11=> 2.7 MHz
+//                   <12=> 2.9 MHz
+//                   <13=> 3.1 MHz
+//                   <14=> 3.2 MHz
+//                   <15=> 3.4 MHz
+//   </h>
+//
+//   <h> System PLL Control Register (SYSPLLCTRL)
+//                   <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
+//                   <i> F_clkin must be in the range of  10 MHz to  25 MHz
+//                   <i> F_CCO   must be in the range of 156 MHz to 320 MHz
+//     <o3.0..4>   MSEL: Feedback Divider Selection
+//                     <i> M = MSEL + 1
+//                   <0-31>
+//     <o3.5..6>   PSEL: Post Divider Selection
+//                   <0=> P = 1
+//                   <1=> P = 2
+//                   <2=> P = 4
+//                   <3=> P = 8
+//   </h>
+//
+//   <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
+//     <o4.0..1>   SEL: System PLL Clock Source
+//                   <0=> IRC Oscillator
+//                   <1=> System Oscillator
+//                   <2=> Reserved
+//                   <3=> CLKIN pin
+//   </h>
+//
+//   <h> Main Clock Source Select Register (MAINCLKSEL)
+//     <o5.0..1>   SEL: Clock Source for Main Clock
+//                   <0=> IRC Oscillator
+//                   <1=> Input Clock to System PLL
+//                   <2=> WDT Oscillator
+//                   <3=> System PLL Clock Out
+//   </h>
+//
+//   <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
+//     <o6.0..7>   DIV: System AHB Clock Divider
+//                     <i> Divides main clock to provide system clock to core, memories, and peripherals.
+//                     <i> 0 = is disabled
+//                   <0-255>
+//   </h>
+// </e>
+*/
+#define CLOCK_SETUP           1
+#define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
+#define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
+#define SYSPLLCTRL_Val        0x00000041              // Reset: 0x000
+#define SYSPLLCLKSEL_Val      0x00000000              // Reset: 0x000
+#define MAINCLKSEL_Val        0x00000000              // Reset: 0x000
+#define SYSAHBCLKDIV_Val      0x00000001              // Reset: 0x001
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+  Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask)                     (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val),  ~0x00000003))
+   #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val),  ~0x000001FF))
+   #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
+   #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val),  ~0x000001FF))
+   #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val),  ~0x00000003))
+   #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+   #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+#define __SYS_OSC_CLK     (    __XTAL)    /* Main oscillator frequency        */
+#define __IRC_OSC_CLK     (12000000UL)    /* Internal RC oscillator frequency */
+#define __CLKIN_CLK       (12000000UL)    /* CLKIN pin frequency              */
+
+
+#define __FREQSEL   ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL   (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP)                         /* Clock Setup              */
+  #if  (__FREQSEL ==  0)
+    #define __WDT_OSC_CLK        ( 0)                  /* undefined */
+  #elif (__FREQSEL ==  1)
+    #define __WDT_OSC_CLK        ( 500000 / __DIVSEL)
+  #elif (__FREQSEL ==  2)
+    #define __WDT_OSC_CLK        ( 800000 / __DIVSEL)
+  #elif (__FREQSEL ==  3)
+    #define __WDT_OSC_CLK        (1100000 / __DIVSEL)
+  #elif (__FREQSEL ==  4)
+    #define __WDT_OSC_CLK        (1400000 / __DIVSEL)
+  #elif (__FREQSEL ==  5)
+    #define __WDT_OSC_CLK        (1600000 / __DIVSEL)
+  #elif (__FREQSEL ==  6)
+    #define __WDT_OSC_CLK        (1800000 / __DIVSEL)
+  #elif (__FREQSEL ==  7)
+    #define __WDT_OSC_CLK        (2000000 / __DIVSEL)
+  #elif (__FREQSEL ==  8)
+    #define __WDT_OSC_CLK        (2200000 / __DIVSEL)
+  #elif (__FREQSEL ==  9)
+    #define __WDT_OSC_CLK        (2400000 / __DIVSEL)
+  #elif (__FREQSEL == 10)
+    #define __WDT_OSC_CLK        (2600000 / __DIVSEL)
+  #elif (__FREQSEL == 11)
+    #define __WDT_OSC_CLK        (2700000 / __DIVSEL)
+  #elif (__FREQSEL == 12)
+    #define __WDT_OSC_CLK        (2900000 / __DIVSEL)
+  #elif (__FREQSEL == 13)
+    #define __WDT_OSC_CLK        (3100000 / __DIVSEL)
+  #elif (__FREQSEL == 14)
+    #define __WDT_OSC_CLK        (3200000 / __DIVSEL)
+  #else
+    #define __WDT_OSC_CLK        (3400000 / __DIVSEL)
+  #endif
+
+  /* sys_pllclkin calculation */
+  #if   ((SYSPLLCLKSEL_Val & 0x03) == 0)
+    #define __SYS_PLLCLKIN           (__IRC_OSC_CLK)
+  #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+    #define __SYS_PLLCLKIN           (__SYS_OSC_CLK)
+  #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
+    #define __SYS_PLLCLKIN           (__CLKIN_CLK)
+  #else
+    #define __SYS_PLLCLKIN           (0)
+  #endif
+
+  #define  __SYS_PLLCLKOUT         (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+  /* main clock calculation */
+  #if   ((MAINCLKSEL_Val & 0x03) == 0)
+    #define __MAIN_CLOCK             (__IRC_OSC_CLK)
+  #elif ((MAINCLKSEL_Val & 0x03) == 1)
+    #define __MAIN_CLOCK             (__SYS_PLLCLKIN)
+  #elif ((MAINCLKSEL_Val & 0x03) == 2)
+    #if (__FREQSEL ==  0)
+      #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+    #else
+      #define __MAIN_CLOCK           (__WDT_OSC_CLK)
+    #endif
+  #elif ((MAINCLKSEL_Val & 0x03) == 3)
+    #define __MAIN_CLOCK             (__SYS_PLLCLKOUT)
+  #else
+    #define __MAIN_CLOCK             (0)
+  #endif
+
+  #define __SYSTEM_CLOCK             (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+  #define __SYSTEM_CLOCK             (__IRC_OSC_CLK)
+#endif  // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+  uint32_t wdt_osc = 0;
+
+  /* Determine clock frequency according to clock register values             */
+  switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+    case 0:  wdt_osc =       0; break;
+    case 1:  wdt_osc =  500000; break;
+    case 2:  wdt_osc =  800000; break;
+    case 3:  wdt_osc = 1100000; break;
+    case 4:  wdt_osc = 1400000; break;
+    case 5:  wdt_osc = 1600000; break;
+    case 6:  wdt_osc = 1800000; break;
+    case 7:  wdt_osc = 2000000; break;
+    case 8:  wdt_osc = 2200000; break;
+    case 9:  wdt_osc = 2400000; break;
+    case 10: wdt_osc = 2600000; break;
+    case 11: wdt_osc = 2700000; break;
+    case 12: wdt_osc = 2900000; break;
+    case 13: wdt_osc = 3100000; break;
+    case 14: wdt_osc = 3200000; break;
+    case 15: wdt_osc = 3400000; break;
+  }
+  wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+  switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+    case 0:                             /* Internal RC oscillator             */
+      SystemCoreClock = __IRC_OSC_CLK;
+      break;
+    case 1:                             /* Input Clock to System PLL          */
+      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+          case 0:                       /* Internal RC oscillator             */
+            SystemCoreClock = __IRC_OSC_CLK;
+            break;
+          case 1:                       /* System oscillator                  */
+            SystemCoreClock = __SYS_OSC_CLK;
+            break;
+          case 2:                       /* Reserved                           */
+            SystemCoreClock = 0;
+            break;
+          case 3:                       /* CLKIN pin                          */
+            SystemCoreClock = __CLKIN_CLK;
+            break;
+      }
+      break;
+    case 2:                             /* WDT Oscillator                     */
+      SystemCoreClock = wdt_osc;
+      break;
+    case 3:                             /* System PLL Clock Out               */
+      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+          case 0:                       /* Internal RC oscillator             */
+            SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+            break;
+          case 1:                       /* System oscillator                  */
+            SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+            break;
+          case 2:                       /* Reserved                           */
+            SystemCoreClock = 0;
+            break;
+          case 3:                       /* CLKIN pin                          */
+            SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+            break;
+      }
+      break;
+  }
+
+  SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void) {
+  volatile uint32_t i;
+
+  /* System clock to the IOCON & the SWM need to be enabled or
+  most of the I/O related peripherals won't work. */
+  LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
+
+#if (CLOCK_SETUP)                                 /* Clock Setup              */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+  LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
+  LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
+  LPC_SWM->PINENABLE0 &= ~(0x3 << 4);
+  LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 5);        /* Power-up System Osc      */
+  LPC_SYSCON->SYSOSCCTRL    = SYSOSCCTRL_Val;
+  for (i = 0; i < 200; i++) __NOP();
+#endif
+#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
+  LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
+  LPC_SWM->PINENABLE0 &= ~(0x1 << 7);
+  for (i = 0; i < 200; i++) __NOP();
+#endif
+
+  LPC_SYSCON->SYSPLLCLKSEL  = SYSPLLCLKSEL_Val;   /* Select PLL Input         */
+  LPC_SYSCON->SYSPLLCLKUEN  = 0x01;               /* Update Clock Source      */
+  while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01));     /* Wait Until Updated       */
+#if ((MAINCLKSEL_Val & 0x03) == 3)                /* Main Clock is PLL Out    */
+  LPC_SYSCON->SYSPLLCTRL    = SYSPLLCTRL_Val;
+  LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 7);        /* Power-up SYSPLL          */
+  while (!(LPC_SYSCON->SYSPLLSTAT & 0x01));	      /* Wait Until PLL Locked    */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+  LPC_SYSCON->WDTOSCCTRL    = WDTOSCCTRL_Val;
+  LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 6);        /* Power-up WDT Clock       */
+  for (i = 0; i < 200; i++) __NOP();
+#endif
+
+  LPC_SYSCON->MAINCLKSEL    = MAINCLKSEL_Val;     /* Select PLL Clock Output  */
+  LPC_SYSCON->MAINCLKUEN    = 0x01;               /* Update MCLK Clock Source */
+  while (!(LPC_SYSCON->MAINCLKUEN & 0x01));       /* Wait Until Updated       */
+
+  LPC_SYSCON->SYSAHBCLKDIV  = SYSAHBCLKDIV_Val;
+#endif
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,62 @@
+/******************************************************************************
+ * @file:    system_LPC8xx.h
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File
+ *           for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date:    16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC8xx_H
+#define __SYSTEM_LPC8xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC8xx_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/core_cm0.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/core_cm0plus.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x20)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/core_cm3.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/core_cm4.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/core_cm4_simd.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/core_cmFunc.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/core_cmInstr.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/PeripheralNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    UART_0 = (int)UART0_BASE,
+    UART_1 = (int)UART1_BASE,
+    UART_2 = (int)UART2_BASE
+} UARTName;
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART_0
+
+typedef enum {
+    I2C_0 = (int)I2C0_BASE,
+    I2C_1 = (int)I2C1_BASE,
+} I2CName;
+
+#define TPM_SHIFT   8
+typedef enum {
+    PWM_1  = (0 << TPM_SHIFT) | (0),  // TPM0 CH0
+    PWM_2  = (0 << TPM_SHIFT) | (1),  // TPM0 CH1
+    PWM_3  = (0 << TPM_SHIFT) | (2),  // TPM0 CH2
+    PWM_4  = (0 << TPM_SHIFT) | (3),  // TPM0 CH3
+    PWM_5  = (0 << TPM_SHIFT) | (4),  // TPM0 CH4
+    PWM_6  = (0 << TPM_SHIFT) | (5),  // TPM0 CH5
+
+    PWM_7  = (1 << TPM_SHIFT) | (0),  // TPM1 CH0
+    PWM_8  = (1 << TPM_SHIFT) | (1),  // TPM1 CH1
+
+    PWM_9  = (2 << TPM_SHIFT) | (0),  // TPM2 CH0
+    PWM_10 = (2 << TPM_SHIFT) | (1)   // TPM2 CH1
+} PWMName;
+
+typedef enum {
+    ADC0_SE0  =  0,
+    ADC0_SE3  =  3,
+    ADC0_SE4b =  4,
+    ADC0_SE5b =  5,
+    ADC0_SE6b =  6,
+    ADC0_SE7b =  7,
+    ADC0_SE8  =  8,
+    ADC0_SE9  =  9,
+    ADC0_SE11 = 11,
+    ADC0_SE12 = 12,
+    ADC0_SE13 = 13,
+    ADC0_SE14 = 14,
+    ADC0_SE15 = 15,
+    ADC0_SE23 = 23
+} ADCName;
+
+typedef enum {
+    DAC_0 = 0
+} DACName;
+
+
+typedef enum {
+    SPI_0 = (int)SPI0_BASE,
+    SPI_1 = (int)SPI1_BASE,
+} SPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/PinNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,247 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  12
+
+typedef enum {
+    PTA0 = 0x0,
+    PTA1 = 0x4,
+    PTA2 = 0x8,
+    PTA3 = 0xc,
+    PTA4 = 0x10,
+    PTA5 = 0x14,
+    PTA6 = 0x18,
+    PTA7 = 0x1c,
+    PTA8 = 0x20,
+    PTA9 = 0x24,
+    PTA10 = 0x28,
+    PTA11 = 0x2c,
+    PTA12 = 0x30,
+    PTA13 = 0x34,
+    PTA14 = 0x38,
+    PTA15 = 0x3c,
+    PTA16 = 0x40,
+    PTA17 = 0x44,
+    PTA18 = 0x48,
+    PTA19 = 0x4c,
+    PTA20 = 0x50,
+    PTA21 = 0x54,
+    PTA22 = 0x58,
+    PTA23 = 0x5c,
+    PTA24 = 0x60,
+    PTA25 = 0x64,
+    PTA26 = 0x68,
+    PTA27 = 0x6c,
+    PTA28 = 0x70,
+    PTA29 = 0x74,
+    PTA30 = 0x78,
+    PTA31 = 0x7c,
+    PTB0 = 0x1000,
+    PTB1 = 0x1004,
+    PTB2 = 0x1008,
+    PTB3 = 0x100c,
+    PTB4 = 0x1010,
+    PTB5 = 0x1014,
+    PTB6 = 0x1018,
+    PTB7 = 0x101c,
+    PTB8 = 0x1020,
+    PTB9 = 0x1024,
+    PTB10 = 0x1028,
+    PTB11 = 0x102c,
+    PTB12 = 0x1030,
+    PTB13 = 0x1034,
+    PTB14 = 0x1038,
+    PTB15 = 0x103c,
+    PTB16 = 0x1040,
+    PTB17 = 0x1044,
+    PTB18 = 0x1048,
+    PTB19 = 0x104c,
+    PTB20 = 0x1050,
+    PTB21 = 0x1054,
+    PTB22 = 0x1058,
+    PTB23 = 0x105c,
+    PTB24 = 0x1060,
+    PTB25 = 0x1064,
+    PTB26 = 0x1068,
+    PTB27 = 0x106c,
+    PTB28 = 0x1070,
+    PTB29 = 0x1074,
+    PTB30 = 0x1078,
+    PTB31 = 0x107c,
+    PTC0 = 0x2000,
+    PTC1 = 0x2004,
+    PTC2 = 0x2008,
+    PTC3 = 0x200c,
+    PTC4 = 0x2010,
+    PTC5 = 0x2014,
+    PTC6 = 0x2018,
+    PTC7 = 0x201c,
+    PTC8 = 0x2020,
+    PTC9 = 0x2024,
+    PTC10 = 0x2028,
+    PTC11 = 0x202c,
+    PTC12 = 0x2030,
+    PTC13 = 0x2034,
+    PTC14 = 0x2038,
+    PTC15 = 0x203c,
+    PTC16 = 0x2040,
+    PTC17 = 0x2044,
+    PTC18 = 0x2048,
+    PTC19 = 0x204c,
+    PTC20 = 0x2050,
+    PTC21 = 0x2054,
+    PTC22 = 0x2058,
+    PTC23 = 0x205c,
+    PTC24 = 0x2060,
+    PTC25 = 0x2064,
+    PTC26 = 0x2068,
+    PTC27 = 0x206c,
+    PTC28 = 0x2070,
+    PTC29 = 0x2074,
+    PTC30 = 0x2078,
+    PTC31 = 0x207c,
+    PTD0 = 0x3000,
+    PTD1 = 0x3004,
+    PTD2 = 0x3008,
+    PTD3 = 0x300c,
+    PTD4 = 0x3010,
+    PTD5 = 0x3014,
+    PTD6 = 0x3018,
+    PTD7 = 0x301c,
+    PTD8 = 0x3020,
+    PTD9 = 0x3024,
+    PTD10 = 0x3028,
+    PTD11 = 0x302c,
+    PTD12 = 0x3030,
+    PTD13 = 0x3034,
+    PTD14 = 0x3038,
+    PTD15 = 0x303c,
+    PTD16 = 0x3040,
+    PTD17 = 0x3044,
+    PTD18 = 0x3048,
+    PTD19 = 0x304c,
+    PTD20 = 0x3050,
+    PTD21 = 0x3054,
+    PTD22 = 0x3058,
+    PTD23 = 0x305c,
+    PTD24 = 0x3060,
+    PTD25 = 0x3064,
+    PTD26 = 0x3068,
+    PTD27 = 0x306c,
+    PTD28 = 0x3070,
+    PTD29 = 0x3074,
+    PTD30 = 0x3078,
+    PTD31 = 0x307c,
+    PTE0 = 0x4000,
+    PTE1 = 0x4004,
+    PTE2 = 0x4008,
+    PTE3 = 0x400c,
+    PTE4 = 0x4010,
+    PTE5 = 0x4014,
+    PTE6 = 0x4018,
+    PTE7 = 0x401c,
+    PTE8 = 0x4020,
+    PTE9 = 0x4024,
+    PTE10 = 0x4028,
+    PTE11 = 0x402c,
+    PTE12 = 0x4030,
+    PTE13 = 0x4034,
+    PTE14 = 0x4038,
+    PTE15 = 0x403c,
+    PTE16 = 0x4040,
+    PTE17 = 0x4044,
+    PTE18 = 0x4048,
+    PTE19 = 0x404c,
+    PTE20 = 0x4050,
+    PTE21 = 0x4054,
+    PTE22 = 0x4058,
+    PTE23 = 0x405c,
+    PTE24 = 0x4060,
+    PTE25 = 0x4064,
+    PTE26 = 0x4068,
+    PTE27 = 0x406c,
+    PTE28 = 0x4070,
+    PTE29 = 0x4074,
+    PTE30 = 0x4078,
+    PTE31 = 0x407c,
+
+    LED_RED = PTB18,
+    LED_GREEN = PTB19,
+    LED_BLUE = PTD1,
+
+    // mbed original LED naming
+    LED1 = LED_BLUE,
+    LED2 = LED_GREEN,
+    LED3 = LED_RED,
+    LED4 = LED_RED,
+
+    // USB Pins
+    USBTX = PTA2,
+    USBRX = PTA1,
+
+    // Arduino Headers
+    D0 = PTA1,
+    D1 = PTA2,
+    D2 = PTD4,
+    D3 = PTA12,
+    D4 = PTA4,
+    D5 = PTA5,
+    D6 = PTC8,
+    D7 = PTC9,
+    D8 = PTA13,
+    D9 = PTD5,
+    D10 = PTD0,
+    D11 = PTD2,
+    D12 = PTD3,
+    D13 = PTD1,
+    D14 = PTE0,
+    D15 = PTE1,
+
+    A0 = PTB0,
+    A1 = PTB1,
+    A2 = PTB2,
+    A3 = PTB3,
+    A4 = PTC2,
+    A5 = PTC1,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+/* PullDown not available for KL25 */
+typedef enum {
+    PullNone = 0,
+    PullUp = 2,
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/PortNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,34 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PortA = 0,
+    PortB = 1,
+    PortC = 2,
+    PortD = 3,
+    PortE = 4
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/analogin_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,87 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogin_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_ADC[] = {
+    {PTE20, ADC0_SE0,  0},
+    {PTE22, ADC0_SE3,  0},
+    {PTE29, ADC0_SE4b, 0},
+    {PTE30, ADC0_SE23, 0},
+    {PTB0,  ADC0_SE8,  0},
+    {PTB1,  ADC0_SE9,  0},
+    {PTB2,  ADC0_SE12, 0},
+    {PTB3,  ADC0_SE13, 0},
+    {PTC0,  ADC0_SE14, 0},
+    {PTC1,  ADC0_SE15, 0},
+    {PTC2,  ADC0_SE11, 0},
+    {PTD1,  ADC0_SE5b, 0},
+    {PTD5,  ADC0_SE6b, 0},
+    {PTD6,  ADC0_SE7b, 0},
+    {NC,    NC,        0}
+};
+
+void analogin_init(analogin_t *obj, PinName pin) {
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    if (obj->adc == (uint32_t)NC) {
+        error("ADC pin mapping failed");
+    }
+
+    SIM->SCGC6 |= SIM_SCGC6_ADC0_MASK;
+
+    uint32_t port = (uint32_t)pin >> PORT_SHIFT;
+    SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port);
+
+    ADC0->SC1[1] = ADC_SC1_ADCH(obj->adc);
+
+    ADC0->CFG1 = ADC_CFG1_ADLPC_MASK    // Low-Power Configuration
+               | ADC_CFG1_ADIV(3)       // Clock Divide Select: (Input Clock)/8
+               | ADC_CFG1_ADLSMP_MASK   // Long Sample Time
+               | ADC_CFG1_MODE(3)       // (16)bits Resolution
+               | ADC_CFG1_ADICLK(1);    // Input Clock: (Bus Clock)/2
+
+    ADC0->CFG2 = ADC_CFG2_MUXSEL_MASK   // ADxxb channels are selected
+               | ADC_CFG2_ADACKEN_MASK  // Asynchronous Clock Output Enable
+               | ADC_CFG2_ADHSC_MASK    // High-Speed Configuration
+               | ADC_CFG2_ADLSTS(0);    // Long Sample Time Select
+
+    ADC0->SC2 = ADC_SC2_REFSEL(0);      // Default Voltage Reference
+
+    ADC0->SC3 = ADC_SC3_AVGE_MASK       // Hardware Average Enable
+              | ADC_SC3_AVGS(0);        // 4 Samples Averaged
+
+    pinmap_pinout(pin, PinMap_ADC);
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+    // start conversion
+    ADC0->SC1[0] = ADC_SC1_ADCH(obj->adc);
+
+    // Wait Conversion Complete
+    while ((ADC0->SC1[0] & ADC_SC1_COCO_MASK) != ADC_SC1_COCO_MASK);
+
+    // Return value
+    return (uint16_t)ADC0->R[0];
+}
+
+float analogin_read(analogin_t *obj) {
+    uint16_t value = analogin_read_u16(obj);
+    return (float)value * (1.0f / (float)0xFFFF);
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/analogout_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogout_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#define RANGE_12BIT     0xFFF
+
+static const PinMap PinMap_DAC[] = {
+    {PTE30, DAC_0, 0},
+    {NC   , NC   , 0}
+};
+
+void analogout_init(dac_t *obj, PinName pin) {
+    obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
+    if (obj->dac == (uint32_t)NC) {
+        error("DAC pin mapping failed");
+    }
+
+    SIM->SCGC6 |= SIM_SCGC6_DAC0_MASK;
+
+    uint32_t port = (uint32_t)pin >> PORT_SHIFT;
+    SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port);
+
+    DAC0->DAT[obj->dac].DATH = 0;
+    DAC0->DAT[obj->dac].DATL = 0;
+
+    DAC0->C1 = DAC_C1_DACBFMD_MASK;     // One-Time Scan Mode
+
+    DAC0->C0 = DAC_C0_DACEN_MASK        // Enable
+             | DAC_C0_DACSWTRG_MASK;    // Software Trigger
+
+    pinmap_pinout(pin, PinMap_DAC);
+
+    analogout_write_u16(obj, 0);
+}
+
+void analogout_free(dac_t *obj) {}
+
+static inline void dac_write(dac_t *obj, int value) {
+    DAC0->DAT[obj->dac].DATL = (uint8_t)( value       & 0xFF);
+    DAC0->DAT[obj->dac].DATH = (uint8_t)((value >> 8) & 0xFF);
+}
+
+static inline int dac_read(dac_t *obj) {
+    return ((DAC0->DAT[obj->dac].DATH << 8) | DAC0->DAT[obj->dac].DATL);
+}
+
+void analogout_write(dac_t *obj, float value) {
+    if (value < 0.0) {
+        dac_write(obj, 0);
+    } else if (value > 1.0) {
+        dac_write(obj, RANGE_12BIT);
+    } else {
+        dac_write(obj, value * (float)RANGE_12BIT);
+    }
+}
+
+void analogout_write_u16(dac_t *obj, uint16_t value) {
+    dac_write(obj, value >> 4); // 12-bit
+}
+
+float analogout_read(dac_t *obj) {
+    uint32_t value = dac_read(obj);
+    return (float)value * (1.0f / (float)RANGE_12BIT);
+}
+
+uint16_t analogout_read_u16(dac_t *obj) {
+    uint32_t value = dac_read(obj); // 12-bit
+    return (value << 4) | ((value >> 8) & 0x003F);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/device.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        1
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         1
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         1
+
+#define DEVICE_CAN              0
+
+#define DEVICE_RTC              1
+
+#define DEVICE_ETHERNET         0
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_SEMIHOST         1
+#define DEVICE_LOCALFILESYSTEM  0
+#define DEVICE_ID_LENGTH       24
+
+#define DEVICE_SLEEP            0
+
+#define DEVICE_DEBUG_AWARENESS  0
+
+#define DEVICE_STDIO_MESSAGES   1
+
+#define DEVICE_ERROR_RED        1
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/gpio_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+
+uint32_t gpio_set(PinName pin) {
+    pin_function(pin, 1);
+    return 1 << ((pin & 0x7F) >> 2);
+}
+
+void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
+    if(pin == NC) return;
+
+    obj->pin = pin;
+    obj->mask = gpio_set(pin);
+
+    unsigned int port = (unsigned int)pin >> PORT_SHIFT;
+
+    FGPIO_Type *reg = (FGPIO_Type *)(FPTA_BASE + port * 0x40);
+    obj->reg_set = &reg->PSOR;
+    obj->reg_clr = &reg->PCOR;
+    obj->reg_in  = &reg->PDIR;
+    obj->reg_dir = &reg->PDDR;
+
+    gpio_dir(obj, direction);
+    switch (direction) {
+        case PIN_OUTPUT: pin_mode(pin, PullNone); break;
+        case PIN_INPUT : pin_mode(pin, PullUp); break;
+    }
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+    pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+    switch (direction) {
+        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/gpio_irq_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,145 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "cmsis.h"
+
+#include "gpio_irq_api.h"
+#include "error.h"
+
+#define CHANNEL_NUM    64
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+
+#define IRQ_DISABLED        (0)
+#define IRQ_RAISING_EDGE    PORT_PCR_IRQC(9)
+#define IRQ_FALLING_EDGE    PORT_PCR_IRQC(10)
+#define IRQ_EITHER_EDGE     PORT_PCR_IRQC(11)
+
+static void handle_interrupt_in(PORT_Type *port, int ch_base) {
+    uint32_t mask = 0, i;
+
+    for (i = 0; i < 32; i++) {
+        uint32_t pmask = (1 << i);
+        if (port->ISFR & pmask) {
+            mask |= pmask;
+            uint32_t id = channel_ids[ch_base + i];
+            if (id == 0) continue;
+
+            FGPIO_Type *gpio;
+            gpio_irq_event event = IRQ_NONE;
+            switch (port->PCR[i] & PORT_PCR_IRQC_MASK) {
+                case IRQ_RAISING_EDGE:
+                    event = IRQ_RISE;
+                    break;
+
+                case IRQ_FALLING_EDGE:
+                    event = IRQ_FALL;
+                    break;
+
+                case IRQ_EITHER_EDGE:
+                    gpio = (port == PORTA) ? (FPTA) : (FPTD);
+                    event = (gpio->PDIR & pmask) ? (IRQ_RISE) : (IRQ_FALL);
+                    break;
+            }
+            if (event != IRQ_NONE)
+                irq_handler(id, event);
+        }
+    }
+    port->ISFR = mask;
+}
+
+void gpio_irqA(void) {handle_interrupt_in(PORTA, 0);}
+void gpio_irqD(void) {handle_interrupt_in(PORTD, 32);}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+    if (pin == NC) return -1;
+
+    irq_handler = handler;
+
+    obj->port = pin >> PORT_SHIFT;
+    obj->pin = (pin & 0x7F) >> 2;
+
+    uint32_t ch_base, vector;
+    IRQn_Type irq_n;
+    switch (obj->port) {
+            case PortA:
+                ch_base = 0;  irq_n = PORTA_IRQn; vector = (uint32_t)gpio_irqA;
+                break;
+
+            case PortD:
+                ch_base = 32; irq_n = PORTD_IRQn; vector = (uint32_t)gpio_irqD;
+                break;
+
+            default:
+                error("gpio_irq only supported on port A and D\n");
+                break;
+    }
+    NVIC_SetVector(irq_n, vector);
+    NVIC_EnableIRQ(irq_n);
+
+    obj->ch = ch_base + obj->pin;
+    channel_ids[obj->ch] = id;
+
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+    channel_ids[obj->ch] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+    PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port);
+
+    uint32_t irq_settings = IRQ_DISABLED;
+
+    switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) {
+        case IRQ_DISABLED:
+            if (enable) {
+                irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE);
+            }
+            break;
+
+        case IRQ_RAISING_EDGE:
+            if (enable) {
+                irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE);
+            } else {
+                if (event == IRQ_FALL)
+                    irq_settings = IRQ_RAISING_EDGE;
+            }
+            break;
+
+        case IRQ_FALLING_EDGE:
+            if (enable) {
+                irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE);
+            } else {
+                if (event == IRQ_RISE)
+                    irq_settings = IRQ_FALLING_EDGE;
+            }
+            break;
+
+        case IRQ_EITHER_EDGE:
+            if (enable) {
+                irq_settings = IRQ_EITHER_EDGE;
+            } else {
+                irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE);
+            }
+            break;
+    }
+
+    // Interrupt configuration and clear interrupt
+    port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/gpio_object.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName  pin;
+    uint32_t mask;
+
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_set;
+    __IO uint32_t *reg_clr;
+    __I  uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+    if (value)
+        *obj->reg_set = obj->mask;
+    else
+        *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/i2c_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,409 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "i2c_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_I2C_SDA[] = {
+    {PTE25, I2C_0, 5},
+    {PTC9,  I2C_0, 2},
+    {PTE0,  I2C_1, 6},
+    {PTB1,  I2C_0, 2},
+    {PTB3,  I2C_0, 2},
+    {NC  ,  NC   , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+    {PTE24, I2C_0, 5},
+    {PTC8,  I2C_0, 2},
+    {PTE1,  I2C_1, 6},
+    {PTB0,  I2C_0, 2},
+    {PTB2,  I2C_0, 2},
+    {NC  ,  NC,    0}
+};
+
+static const uint16_t ICR[0x40] = {
+      20,   22,   24,   26,   28,
+      30,   34,   40,   28,   32,
+      36,   40,   44,   48,   56,
+      68,   48,   56,   64,   72,
+      80,   88,  104,  128,   80,
+      96,  112,  128,  144,  160,
+      192,  240,  160,  192,  224,
+      256,  288,  320,  384,  480,
+      320,  384,  448,  512,  576,
+      640,  768,  960,  640,  768,
+      896, 1024, 1152, 1280, 1536,
+      1920, 1280, 1536, 1792, 2048,
+      2304, 2560, 3072, 3840
+};
+
+static uint8_t first_read;
+
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+    // determine the I2C to use
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+    obj->i2c = (I2C_Type*)pinmap_merge(i2c_sda, i2c_scl);
+    if ((int)obj->i2c == NC) {
+        error("I2C pin mapping failed");
+    }
+
+    // enable power
+    switch ((int)obj->i2c) {
+        case I2C_0: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 6; break;
+        case I2C_1: SIM->SCGC5 |= 1 << 11; SIM->SCGC4 |= 1 << 7; break;
+    }
+
+    // set default frequency at 100k
+    i2c_frequency(obj, 100000);
+
+    // enable I2C interface
+    obj->i2c->C1 |= 0x80;
+
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+    
+    first_read = 1;
+}
+
+int i2c_start(i2c_t *obj) {
+    // if we are in the middle of a transaction
+    // activate the repeat_start flag
+    if (obj->i2c->S & I2C_S_BUSY_MASK) {
+        obj->i2c->C1 |= 0x04;
+    } else {
+        obj->i2c->C1 |= I2C_C1_MST_MASK;
+        obj->i2c->C1 |= I2C_C1_TX_MASK;
+    }
+    first_read = 1;
+    return 0;
+}
+
+int i2c_stop(i2c_t *obj) {
+    volatile uint32_t n = 0;
+    obj->i2c->C1 &= ~I2C_C1_MST_MASK;
+    obj->i2c->C1 &= ~I2C_C1_TX_MASK;
+
+    // It seems that there are timing problems
+    // when there is no waiting time after a STOP.
+    // This wait is also included on the samples
+    // code provided with the freedom board
+    for (n = 0; n < 100; n++) __NOP();
+    first_read = 1;
+    return 0;
+}
+
+static int timeout_status_poll(i2c_t *obj, uint32_t mask) {
+    uint32_t i, timeout = 1000;
+    
+    for (i = 0; i < timeout; i++) {
+        if (obj->i2c->S & mask)
+            return 0;
+    }
+    
+    return 1;
+}
+
+// this function waits the end of a tx transfer and return the status of the transaction:
+//    0: OK ack received
+//    1: OK ack not received
+//    2: failure
+static int i2c_wait_end_tx_transfer(i2c_t *obj) {
+    
+    // wait for the interrupt flag
+    if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) {
+        return 2;
+    }
+    
+    obj->i2c->S |= I2C_S_IICIF_MASK;
+    
+    // wait transfer complete
+    if (timeout_status_poll(obj, I2C_S_TCF_MASK)) {
+        return 2;
+    }
+
+    // check if we received the ACK or not
+    return obj->i2c->S & I2C_S_RXAK_MASK ? 1 : 0;
+}
+
+// this function waits the end of a rx transfer and return the status of the transaction:
+//    0: OK
+//    1: failure
+static int i2c_wait_end_rx_transfer(i2c_t *obj) {
+    // wait for the end of the rx transfer
+    if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) {
+        return 1;
+    }
+    
+    obj->i2c->S |= I2C_S_IICIF_MASK;
+    
+    return 0;
+}
+
+static void i2c_send_nack(i2c_t *obj) {
+    obj->i2c->C1 |= I2C_C1_TXAK_MASK; // NACK
+}
+
+static void i2c_send_ack(i2c_t *obj) {
+    obj->i2c->C1 &= ~I2C_C1_TXAK_MASK; // ACK
+}
+
+static int i2c_do_write(i2c_t *obj, int value) {
+    // write the data
+    obj->i2c->D = value;
+
+    // init and wait the end of the transfer
+    return i2c_wait_end_tx_transfer(obj);
+}
+
+static int i2c_do_read(i2c_t *obj, char * data, int last) {
+    if (last)
+        i2c_send_nack(obj);
+    else
+        i2c_send_ack(obj);
+
+    *data = (obj->i2c->D & 0xFF);
+
+    // start rx transfer and wait the end of the transfer
+    return i2c_wait_end_rx_transfer(obj);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+    uint8_t icr = 0;
+    uint8_t mult = 0;
+    uint32_t error = 0;
+    uint32_t p_error = 0xffffffff;
+    uint32_t ref = 0;
+    uint8_t i, j;
+    // bus clk
+    uint32_t PCLK = 24000000u;
+    uint32_t pulse = PCLK / (hz * 2);
+
+    // we look for the values that minimize the error
+
+    // test all the MULT values
+    for (i = 1; i < 5; i*=2) {
+        for (j = 0; j < 0x40; j++) {
+            ref = PCLK / (i*ICR[j]);
+            if (ref > hz)
+                continue;
+            error = hz - ref;
+            if (error < p_error) {
+                icr = j;
+                mult = i/2;
+                p_error = error;
+            }
+        }
+    }
+    pulse = icr | (mult << 6);
+
+    // I2C Rate
+    obj->i2c->F = pulse;
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+    uint8_t count;
+    char dummy_read, *ptr;
+
+    if (i2c_start(obj)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+
+    if (i2c_do_write(obj, (address | 0x01))) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    // set rx mode
+    obj->i2c->C1 &= ~I2C_C1_TX_MASK;
+
+    // Read in bytes
+    for (count = 0; count < (length); count++) {
+        ptr = (count == 0) ? &dummy_read : &data[count - 1];
+        uint8_t stop_ = (count == (length - 1)) ? 1 : 0;
+        if (i2c_do_read(obj, ptr, stop_)) {
+            i2c_stop(obj);
+            return count;
+        }
+    }
+
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+
+    // last read
+    data[count-1] = obj->i2c->D;
+
+    return length;
+}
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+    int i;
+
+    if (i2c_start(obj)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+
+    if (i2c_do_write(obj, (address & 0xFE))) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    for (i = 0; i < length; i++) {
+        if(i2c_do_write(obj, data[i])) {
+            i2c_stop(obj);
+            return i;
+        }
+    }
+
+    if (stop) {
+        i2c_stop(obj);
+    }
+
+    return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+    i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+    char data;
+    
+    // set rx mode
+    obj->i2c->C1 &= ~I2C_C1_TX_MASK;
+    
+    if(first_read) {
+        // first dummy read
+        i2c_do_read(obj, &data, 0);
+        first_read = 0;
+    }
+    
+    if (last) {
+        // set tx mode
+        obj->i2c->C1 |= I2C_C1_TX_MASK;
+        return obj->i2c->D;
+    }
+        
+    i2c_do_read(obj, &data, last);
+    
+    return data;
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+    first_read = 1;
+    
+    // set tx mode
+    obj->i2c->C1 |= I2C_C1_TX_MASK;
+    
+    return !i2c_do_write(obj, (data & 0xFF));
+}
+
+
+#if DEVICE_I2CSLAVE
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+    if (enable_slave) {
+        // set slave mode
+        obj->i2c->C1 &= ~I2C_C1_MST_MASK;
+        obj->i2c->C1 |= I2C_C1_IICIE_MASK;
+    } else {
+        // set master mode
+        obj->i2c->C1 |= I2C_C1_MST_MASK;
+    }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+    switch(obj->i2c->S) {
+        // read addressed
+        case 0xE6: return 1;
+        
+        // write addressed
+        case 0xE2: return 3;
+        
+        default: return 0;
+    }
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+    uint8_t dummy_read, count;
+    uint8_t * ptr;
+    
+    // set rx mode
+    obj->i2c->C1 &= ~I2C_C1_TX_MASK;
+    
+    // first dummy read
+    dummy_read = obj->i2c->D;
+    if(i2c_wait_end_rx_transfer(obj)) {
+        return 0;
+    }
+    
+    // read address
+    dummy_read = obj->i2c->D;
+    if(i2c_wait_end_rx_transfer(obj)) {
+        return 0;
+    }
+    
+    // read (length - 1) bytes
+    for (count = 0; count < (length - 1); count++) {
+        data[count] = obj->i2c->D;
+        if(i2c_wait_end_rx_transfer(obj)) {
+            return count;
+        }
+    }
+
+    // read last byte
+    ptr = (length == 0) ? &dummy_read : (uint8_t *)&data[count];
+    *ptr = obj->i2c->D;
+    
+    return (length) ? (count + 1) : 0;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+    uint32_t i, count = 0;
+    
+    // set tx mode
+    obj->i2c->C1 |= I2C_C1_TX_MASK;
+    
+    for (i = 0; i < length; i++) {
+        if(i2c_do_write(obj, data[count++]) == 2) {
+            return i;
+        }
+    }
+    
+    // set rx mode
+    obj->i2c->C1 &= ~I2C_C1_TX_MASK;
+    
+    // dummy rx transfer needed
+    // otherwise the master cannot generate a stop bit
+    obj->i2c->D;
+    if(i2c_wait_end_rx_transfer(obj) == 2) {
+        return count;
+    }
+    
+    return count;
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+    obj->i2c->A1 = address & 0xfe;
+}
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/objects.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    uint32_t port;
+    uint32_t pin;
+    uint32_t ch;
+};
+
+struct port_s {
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_out;
+    __I  uint32_t *reg_in;
+    PortName port;
+    uint32_t mask;
+};
+
+struct pwmout_s {
+    __IO uint32_t *MOD;
+    __IO uint32_t *CNT;
+    __IO uint32_t *CnV;
+};
+
+struct serial_s {
+    UARTLP_Type *uart;
+    int index;
+};
+
+struct analogin_s {
+    ADCName adc;
+};
+
+struct dac_s {
+    DACName dac;
+};
+
+struct i2c_s {
+    I2C_Type *i2c;
+};
+
+struct spi_s {
+    SPI_Type *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/pinmap.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "error.h"
+
+void pin_function(PinName pin, int function) {
+    if (pin == (uint32_t)NC) return;
+
+    uint32_t port_n = (uint32_t)pin >> PORT_SHIFT;
+    uint32_t pin_n  = (uint32_t)(pin & 0x7C) >> 2;
+
+    SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port_n);
+    __IO uint32_t* pin_pcr = &(((PORT_Type *)(PORTA_BASE + 0x1000 * port_n)))->PCR[pin_n];
+
+    // pin mux bits: [10:8] -> 11100000000 = (0x700)
+    *pin_pcr = (*pin_pcr & ~0x700) | (function << 8);
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+    if (pin == (uint32_t)NC) { return; }
+
+    __IO uint32_t* pin_pcr = (__IO uint32_t*)(PORTA_BASE + pin);
+
+    // pin pullup bits: [1:0] -> 11 = (0x3)
+    *pin_pcr = (*pin_pcr & ~0x3) | mode;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/port_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,68 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+
+PinName port_pin(PortName port, int pin_n) {
+    return (PinName)((port << PORT_SHIFT) | (pin_n << 2));
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+    obj->port = port;
+    obj->mask = mask;
+
+    FGPIO_Type *reg = (FGPIO_Type *)(FPTA_BASE + port * 0x40);
+
+    obj->reg_out = &reg->PDOR;
+    obj->reg_in  = &reg->PDIR;
+    obj->reg_dir = &reg->PDDR;
+
+    uint32_t i;
+    // The function is set per pin: reuse gpio logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            gpio_set(port_pin(obj->port, i));
+        }
+    }
+
+    port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+    uint32_t i;
+    // The mode is set per pin: reuse pinmap logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+    switch (dir) {
+        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
+    }
+}
+
+void port_write(port_t *obj, int value) {
+    *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj) {
+    return (*obj->reg_in & obj->mask);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/pwmout_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,121 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pwmout_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_PWM[] = {
+    // LEDs
+    {LED_RED  , PWM_9 , 3}, // PTB18, TPM2 CH0
+    {LED_GREEN, PWM_10, 3}, // PTB19, TPM2 CH1
+    {LED_BLUE , PWM_2 , 4}, // PTD1 , TPM0 CH1
+
+    // Arduino digital pinout
+    {D0,  PWM_9 , 3}, // PTA1 , TPM2 CH0
+    {D1,  PWM_10, 3}, // PTA2 , TPM2 CH1
+    {D2,  PWM_5 , 4}, // PTD4 , TPM0 CH4
+    {D3,  PWM_7 , 3}, // PTA12, TPM1 CH0
+    {D4,  PWM_2 , 3}, // PTA4 , TPM0 CH1
+    {D5,  PWM_3 , 3}, // PTA5 , TPM0 CH2
+    {D6,  PWM_5 , 3}, // PTC8 , TPM0 CH4
+    {D7,  PWM_6 , 3}, // PTC9 , TPM0 CH5
+    {D8,  PWM_8 , 3}, // PTA13, TPM1 CH1
+    {D9,  PWM_6 , 4}, // PTD5 , TPM0 CH5
+    {D10, PWM_1 , 4}, // PTD0 , TPM0 CH0
+    {D11, PWM_3 , 4}, // PTD2 , TPM0 CH2
+    {D12, PWM_4 , 4}, // PTD3 , TPM0 CH3
+    {D13, PWM_2 , 4}, // PTD1 , TPM0 CH1
+    {NC , NC    , 0}
+};
+
+#define PWM_CLOCK_MHZ       (0.75) // (48)MHz / 64 = (0.75)MHz
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+    // determine the channel
+    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+    if (pwm == (uint32_t)NC)
+        error("PwmOut pin mapping failed");
+
+    unsigned int port = (unsigned int)pin >> PORT_SHIFT;
+    unsigned int tpm_n = (pwm >> TPM_SHIFT);
+    unsigned int ch_n = (pwm & 0xFF);
+
+    SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port);
+    SIM->SCGC6 |= 1 << (SIM_SCGC6_TPM0_SHIFT + tpm_n);
+    SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); // Clock source: MCGFLLCLK or MCGPLLCLK
+
+    TPM_Type *tpm = (TPM_Type *)(TPM0_BASE + 0x1000 * tpm_n);
+    tpm->SC = TPM_SC_CMOD(1) | TPM_SC_PS(6); // (48)MHz / 64 = (0.75)MHz
+    tpm->CONTROLS[ch_n].CnSC = (TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK); /* No Interrupts; High True pulses on Edge Aligned PWM */
+
+    obj->CnV = &tpm->CONTROLS[ch_n].CnV;
+    obj->MOD = &tpm->MOD;
+    obj->CNT = &tpm->CNT;
+
+    // default to 20ms: standard for servos, and fine for e.g. brightness control
+    pwmout_period_ms(obj, 20);
+    pwmout_write    (obj, 0);
+
+    // Wire pinout
+    pinmap_pinout(pin, PinMap_PWM);
+}
+
+void pwmout_free(pwmout_t* obj) {}
+
+void pwmout_write(pwmout_t* obj, float value) {
+    if (value < 0.0) {
+        value = 0.0;
+    } else if (value > 1.0) {
+        value = 1.0;
+    }
+
+    *obj->CnV = (uint32_t)((float)(*obj->MOD) * value);
+    *obj->CNT = 0;
+}
+
+float pwmout_read(pwmout_t* obj) {
+    float v = (float)(*obj->CnV) / (float)(*obj->MOD);
+    return (v > 1.0) ? (1.0) : (v);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+    pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+    pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+    float dc = pwmout_read(obj);
+    *obj->MOD = PWM_CLOCK_MHZ * us;
+    pwmout_write(obj, dc);
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+    *obj->CnV = PWM_CLOCK_MHZ * us;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/rtc_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "rtc_api.h"
+
+static void init(void) {
+    // enable PORTC clock
+    SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
+
+    // enable RTC clock
+    SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
+
+    /*
+    * configure PTC1 with alternate function 1: RTC_CLKIN
+    * As the kl25z board does not have a 32kHz osc,
+    * we use an external clock generated by the
+    * interface chip
+    */
+    PORTC->PCR[1] &= ~PORT_PCR_MUX_MASK;
+    PORTC->PCR[1] = PORT_PCR_MUX(1);
+
+    // select RTC_CLKIN as RTC clock source
+    SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
+    SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(2);
+}
+
+void rtc_init(void) {
+    init();
+
+    //Configure the TSR. default value: 1
+    RTC->TSR = 1;
+
+    // enable counter
+    RTC->SR |= RTC_SR_TCE_MASK;
+}
+
+void rtc_free(void) {
+    // [TODO]
+}
+
+/*
+ * Little check routine to see if the RTC has been enabled
+ * 0 = Disabled, 1 = Enabled
+ */
+int rtc_isenabled(void) {
+    // even if the RTC module is enabled,
+    // as we use RTC_CLKIN and an external clock,
+    // we need to reconfigure the pins. That is why we
+    // call init() if the rtc is enabled
+
+    // if RTC not enabled return 0
+    SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
+    SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
+    if ((RTC->SR & RTC_SR_TCE_MASK) == 0)
+        return 0;
+
+    init();
+    return 1;
+}
+
+time_t rtc_read(void) {
+    return RTC->TSR;
+}
+
+void rtc_write(time_t t) {
+    // disable counter
+    RTC->SR &= ~RTC_SR_TCE_MASK;
+
+    // we do not write 0 into TSR
+    // to avoid invalid time
+    if (t == 0)
+        t = 1;
+
+    // write seconds
+    RTC->TSR = t;
+
+    // re-enable counter
+    RTC->SR |= RTC_SR_TCE_MASK;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/serial_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,305 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "serial_api.h"
+
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+
+#include <string.h>
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+static const PinMap PinMap_UART_TX[] = {
+    {PTC4, UART_1, 3},
+    {PTA2, UART_0, 2},
+    {PTD5, UART_2, 3},
+    {PTD3, UART_2, 3},
+    {NC  , NC    , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+    {PTC3, UART_1, 3},
+    {PTA1, UART_0, 2},
+    {PTD4, UART_2, 3},
+    {PTD2, UART_2, 3},
+    {NC  , NC    , 0}
+};
+
+#define UART_NUM    3
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+    // determine the UART to use
+    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+    UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    if ((int)uart == NC) {
+        error("Serial pinout mapping failed");
+    }
+
+    obj->uart = (UARTLP_Type *)uart;
+    // enable clk
+    switch (uart) {
+        case UART_0: SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK | (1<<SIM_SOPT2_UART0SRC_SHIFT);
+                     SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; break;
+        case UART_1: SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK; SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; break;
+        case UART_2: SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK; SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; break;
+    }
+    // Disable UART before changing registers
+    obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+    
+    switch (uart) {
+        case UART_0: obj->index = 0; break;
+        case UART_1: obj->index = 1; break;
+        case UART_2: obj->index = 2; break;
+    }
+
+    // set default baud rate and format
+    serial_baud  (obj, 9600);
+    serial_format(obj, 8, ParityNone, 1);
+
+    // pinout the chosen uart
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+
+    // set rx/tx pins in PullUp mode
+    pin_mode(tx, PullUp);
+    pin_mode(rx, PullUp);
+
+    obj->uart->C2 |= (UART_C2_RE_MASK | UART_C2_TE_MASK);
+
+    if (uart == STDIO_UART) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj) {
+    serial_irq_ids[obj->index] = 0;
+}
+
+// serial_baud
+//
+// set the baud rate, taking in to account the current SystemFrequency
+//
+// The LPC2300 and LPC1700 have a divider and a fractional divider to control the
+// baud rate. The formula is:
+//
+// Baudrate = (1 / PCLK) * 16 * DL * (1 + DivAddVal / MulVal)
+//   where:
+//     1 < MulVal <= 15
+//     0 <= DivAddVal < 14
+//     DivAddVal < MulVal
+//
+void serial_baud(serial_t *obj, int baudrate) {
+    
+    // save C2 state
+    uint8_t c2_state = (obj->uart->C2 & (UART_C2_RE_MASK | UART_C2_TE_MASK));
+    
+    // Disable UART before changing registers
+    obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+    
+    // [TODO] not hardcode this value
+    uint32_t PCLK = (obj->uart == UART0) ? 48000000u : 24000000u;
+
+    // First we check to see if the basic divide with no DivAddVal/MulVal
+    // ratio gives us an integer result. If it does, we set DivAddVal = 0,
+    // MulVal = 1. Otherwise, we search the valid ratio value range to find
+    // the closest match. This could be more elegant, using search methods
+    // and/or lookup tables, but the brute force method is not that much
+    // slower, and is more maintainable.
+    uint16_t DL = PCLK / (16 * baudrate);
+
+    // set BDH and BDL
+    obj->uart->BDH = (obj->uart->BDH & ~(0x1f)) | ((DL >> 8) & 0x1f);
+    obj->uart->BDL = (obj->uart->BDL & ~(0xff)) | ((DL >> 0) & 0xff);
+    
+    // restore C2 state
+    obj->uart->C2 |= c2_state;
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+    uint8_t m10 = 0;
+    
+    // save C2 state
+    uint8_t c2_state = (obj->uart->C2 & (UART_C2_RE_MASK | UART_C2_TE_MASK));
+    
+    // Disable UART before changing registers
+    obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
+    
+    // 8 data bits = 0 ... 9 data bits = 1
+    if ((data_bits < 8) || (data_bits > 9)) {
+        error("Invalid number of bits (%d) in serial format, should be 8..9\r\n", data_bits);
+    }
+    data_bits -= 8;
+
+    uint8_t parity_enable, parity_select;
+    switch (parity) {
+        case ParityNone: parity_enable = 0; parity_select = 0; break;
+        case ParityOdd : parity_enable = 1; parity_select = 1; data_bits++; break;
+        case ParityEven: parity_enable = 1; parity_select = 0; data_bits++; break;
+        default:
+            error("Invalid serial parity setting\r\n");
+            return;
+    }
+
+    // 1 stop bits = 0, 2 stop bits = 1
+    if ((stop_bits != 1) && (stop_bits != 2)) {
+        error("Invalid stop bits specified\r\n");
+    }
+    stop_bits -= 1;
+    
+    // 9 data bits + parity
+    if (data_bits == 2) {
+        // only uart0 supports 10 bit communication
+        if (obj->index != 0) {
+            error("Invalid number of bits (9) to be used with parity\r\n");
+        }
+        data_bits = 0;
+        m10 = 1;
+    }
+
+    // data bits, parity and parity mode
+    obj->uart->C1 = ((data_bits << 4)
+                  |  (parity_enable << 1)
+                  |  (parity_select << 0));
+    
+    // enable 10bit mode if needed
+    if (obj->index == 0) {
+        obj->uart->C4 &= ~UARTLP_C4_M10_MASK;
+        obj->uart->C4 |= (m10 << UARTLP_C4_M10_SHIFT);
+    }
+    
+    // stop bits
+    obj->uart->BDH &= ~UART_BDH_SBNS_MASK;
+    obj->uart->BDH |= (stop_bits << UART_BDH_SBNS_SHIFT);
+    
+    // restore C2 state
+    obj->uart->C2 |= c2_state;
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint8_t status, uint32_t index) {
+    if (serial_irq_ids[index] != 0) {
+        if (status & UART_S1_TDRE_MASK)
+            irq_handler(serial_irq_ids[index], TxIrq);
+
+        if (status & UART_S1_RDRF_MASK)
+            irq_handler(serial_irq_ids[index], RxIrq);
+    }
+}
+
+void uart0_irq() {
+    uart_irq(UART0->S1, 0);
+    if (UART0->S1 & UART_S1_OR_MASK)
+        UART0->S1 |= UART_S1_OR_MASK;
+}
+void uart1_irq() {uart_irq(UART1->S1, 1);}
+void uart2_irq() {uart_irq(UART2->S1, 2);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;
+    switch ((int)obj->uart) {
+        case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
+        case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
+        case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
+    }
+
+    if (enable) {
+        switch (irq) {
+            case RxIrq: obj->uart->C2 |= (UART_C2_RIE_MASK); break;
+            case TxIrq: obj->uart->C2 |= (UART_C2_TIE_MASK); break;
+        }
+        NVIC_SetVector(irq_n, vector);
+        NVIC_EnableIRQ(irq_n);
+
+    } else { // disable
+        int all_disabled = 0;
+        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+        switch (irq) {
+            case RxIrq: obj->uart->C2 &= ~(UART_C2_RIE_MASK); break;
+            case TxIrq: obj->uart->C2 &= ~(UART_C2_TIE_MASK); break;
+        }
+        switch (other_irq) {
+            case RxIrq: all_disabled = (obj->uart->C2 & (UART_C2_RIE_MASK)) == 0; break;
+            case TxIrq: all_disabled = (obj->uart->C2 & (UART_C2_TIE_MASK)) == 0; break;
+        }
+        if (all_disabled)
+            NVIC_DisableIRQ(irq_n);
+    }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+    while (!serial_readable(obj));
+    return obj->uart->D;
+}
+
+void serial_putc(serial_t *obj, int c) {
+    while (!serial_writable(obj));
+    obj->uart->D = c;
+}
+
+int serial_readable(serial_t *obj) {
+    // check overrun
+    if (obj->uart->S1 &  UART_S1_OR_MASK) {
+        obj->uart->S1 |= UART_S1_OR_MASK;
+    }
+    return (obj->uart->S1 & UART_S1_RDRF_MASK);
+}
+
+int serial_writable(serial_t *obj) {
+    // check overrun
+    if (obj->uart->S1 &  UART_S1_OR_MASK) {
+        obj->uart->S1 |= UART_S1_OR_MASK;
+    }
+    return (obj->uart->S1 & UART_S1_TDRE_MASK);
+}
+
+void serial_clear(serial_t *obj) {
+}
+
+void serial_pinout_tx(PinName tx) {
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+    obj->uart->C2 |= UART_C2_SBK_MASK; 
+}
+
+void serial_break_clear(serial_t *obj) {
+    obj->uart->C2 &= ~UART_C2_SBK_MASK;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/spi_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,200 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "spi_api.h"
+
+#include <math.h>
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_SPI_SCLK[] = {
+    {PTA15, SPI_0, 2},
+    {PTB11, SPI_1, 2},
+    {PTC5,  SPI_0, 2},
+    {PTD1,  SPI_0, 2},
+    {PTD5,  SPI_1, 2},
+    {PTE2,  SPI_1, 2},
+    {NC  ,  NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+    {PTA16, SPI_0, 2},
+    {PTA17, SPI_0, 5},
+    {PTB16, SPI_1, 2},
+    {PTB17, SPI_1, 5},
+    {PTC6,  SPI_0, 2},
+    {PTC7,  SPI_0, 5},
+    {PTD2,  SPI_0, 2},
+    {PTD3,  SPI_0, 5},
+    {PTD6,  SPI_1, 2},
+    {PTD7,  SPI_1, 5},
+    {PTE1,  SPI_1, 2},
+    {PTE3,  SPI_1, 5},
+    {NC  ,  NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+    {PTA16, SPI_0, 5},
+    {PTA17, SPI_0, 2},
+    {PTB16, SPI_1, 5},
+    {PTB17, SPI_1, 2},
+    {PTC6,  SPI_0, 5},
+    {PTC7,  SPI_0, 2},
+    {PTD2,  SPI_0, 5},
+    {PTD3,  SPI_0, 2},
+    {PTD6,  SPI_1, 5},
+    {PTD7,  SPI_1, 2},
+    {PTE1,  SPI_1, 5},
+    {PTE3,  SPI_1, 2},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+    {PTA14, SPI_0, 2},
+    {PTB10, SPI_1, 2},
+    {PTC4,  SPI_0, 2},
+    {PTD0,  SPI_0, 2},
+    {PTD4,  SPI_1, 2},
+    {PTE4,  SPI_1, 2},
+    {NC  ,  NC   , 0}
+};
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    // determine the SPI to use
+    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+
+    obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
+    if ((int)obj->spi == NC) {
+        error("SPI pinout mapping failed");
+    }
+
+    // enable power and clocking
+    switch ((int)obj->spi) {
+        case SPI_0: SIM->SCGC5 |= 1 << 11; SIM->SCGC4 |= 1 << 22; break;
+        case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
+    }
+
+    // set default format and frequency
+    if (ssel == NC) {
+        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
+    } else {
+        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
+    }
+    spi_frequency(obj, 1000000);
+
+    // enable SPI
+    obj->spi->C1 |= SPI_C1_SPE_MASK;
+
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+}
+
+void spi_free(spi_t *obj) {
+    // [TODO]
+}
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+    if (bits != 8) {
+        error("Only 8bits SPI supported");
+    }
+
+    if ((mode < 0) || (mode > 3)) {
+        error("SPI mode unsupported");
+    }
+
+    uint8_t polarity = (mode & 0x2) ? 1 : 0;
+    uint8_t phase = (mode & 0x1) ? 1 : 0;
+    uint8_t c1_data = ((!slave) << 4) | (polarity << 3) | (phase << 2);
+
+    // clear MSTR, CPOL and CPHA bits
+    obj->spi->C1 &= ~(0x7 << 2);
+
+    // write new value
+    obj->spi->C1 |= c1_data;
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+    uint32_t error = 0;
+    uint32_t p_error = 0xffffffff;
+    uint32_t ref = 0;
+    uint8_t  spr = 0;
+    uint8_t  ref_spr = 0;
+    uint8_t  ref_prescaler = 0;
+
+    // bus clk
+    uint32_t PCLK = 48000000u;
+    uint8_t prescaler = 1;
+    uint8_t divisor = 2;
+
+    for (prescaler = 1; prescaler <= 8; prescaler++) {
+        divisor = 2;
+        for (spr = 0; spr <= 8; spr++, divisor *= 2) {
+            ref = PCLK / (prescaler*divisor);
+            if (ref > hz)
+                continue;
+            error = hz - ref;
+            if (error < p_error) {
+                ref_spr = spr;
+                ref_prescaler = prescaler - 1;
+                p_error = error;
+            }
+        }
+    }
+
+    // set SPPR and SPR
+    obj->spi->BR = ((ref_prescaler & 0x7) << 4) | (ref_spr & 0xf);
+}
+
+static inline int spi_writeable(spi_t * obj) {
+    return (obj->spi->S & SPI_S_SPTEF_MASK) ? 1 : 0;
+}
+
+static inline int spi_readable(spi_t * obj) {
+    return (obj->spi->S & SPI_S_SPRF_MASK) ? 1 : 0;
+}
+
+int spi_master_write(spi_t *obj, int value) {
+    // wait tx buffer empty
+    while(!spi_writeable(obj));
+    obj->spi->D = (value & 0xff);
+
+    // wait rx buffer full
+    while (!spi_readable(obj));
+    return obj->spi->D & 0xff;
+}
+
+int spi_slave_receive(spi_t *obj) {
+    return spi_readable(obj);
+}
+
+int spi_slave_read(spi_t *obj) {
+    return obj->spi->D;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+    while (!spi_writeable(obj));
+    obj->spi->D = value;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KL25Z/us_ticker.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,146 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+static void pit_init(void);
+static void lptmr_init(void);
+
+static int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+    if (us_ticker_inited) return;
+    us_ticker_inited = 1;
+    
+    pit_init();
+    lptmr_init();
+}
+
+/******************************************************************************
+ * Timer for us timing.
+ ******************************************************************************/
+static void pit_init(void) {
+    SIM->SCGC6 |= SIM_SCGC6_PIT_MASK;   // Clock PIT
+    PIT->MCR = 0;                       // Enable PIT
+    
+    // Channel 1
+    PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF;
+    PIT->CHANNEL[1].TCTRL = PIT_TCTRL_CHN_MASK;    // Chain to timer 0, disable Interrupts
+    PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_TEN_MASK;   // Start timer 1
+    
+    // Use channel 0 as a prescaler for channel 1
+    PIT->CHANNEL[0].LDVAL = 23;
+    PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK;    // Start timer 0, disable interrupts
+}
+
+uint32_t us_ticker_read() {
+    if (!us_ticker_inited)
+        us_ticker_init();
+    
+    // The PIT is a countdown timer
+    return ~(PIT->CHANNEL[1].CVAL);
+}
+
+/******************************************************************************
+ * Timer Event
+ * 
+ * It schedules interrupts at given (32bit)us interval of time.
+ * It is implemented used the 16bit Low Power Timer that remains powered in all
+ * power modes.
+ ******************************************************************************/
+static void lptmr_isr(void);
+
+static void lptmr_init(void) {
+    /* Clock the timer */
+    SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
+    
+    /* Reset */
+    LPTMR0->CSR = 0;
+    
+    /* Set interrupt handler */
+    NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr);
+    NVIC_EnableIRQ(LPTimer_IRQn);
+    
+    /* Clock at (1)MHz -> (1)tick/us */
+    LPTMR0->PSR = LPTMR_PSR_PCS(3);       // OSCERCLK -> 8MHz
+    LPTMR0->PSR |= LPTMR_PSR_PRESCALE(2); // divide by 8
+}
+
+void us_ticker_disable_interrupt(void) {
+    LPTMR0->CSR &= ~LPTMR_CSR_TIE_MASK;
+}
+
+void us_ticker_clear_interrupt(void) {
+    // we already clear interrupt in lptmr_isr
+}
+
+static uint32_t us_ticker_int_counter = 0;
+static uint16_t us_ticker_int_remainder = 0;
+
+static void lptmr_set(unsigned short count) {
+    /* Reset */
+    LPTMR0->CSR = 0;
+    
+    /* Set the compare register */
+    LPTMR0->CMR = count;
+    
+    /* Enable interrupt */
+    LPTMR0->CSR |= LPTMR_CSR_TIE_MASK;
+    
+    /* Start the timer */
+    LPTMR0->CSR |= LPTMR_CSR_TEN_MASK;
+}
+
+static void lptmr_isr(void) {
+    // write 1 to TCF to clear the LPT timer compare flag
+    LPTMR0->CSR |= LPTMR_CSR_TCF_MASK;
+    
+    if (us_ticker_int_counter > 0) {
+        lptmr_set(0xFFFF);
+        us_ticker_int_counter--;
+    
+    } else {
+        if (us_ticker_int_remainder > 0) {
+            lptmr_set(us_ticker_int_remainder);
+            us_ticker_int_remainder = 0;
+        
+        } else {
+            // This function is going to disable the interrupts if there are
+            // no other events in the queue
+            us_ticker_irq_handler();
+        }
+    }
+}
+
+void us_ticker_set_interrupt(unsigned int timestamp) {
+    int delta = (int)(timestamp - us_ticker_read());
+    if (delta <= 0) {
+        // This event was in the past:
+        us_ticker_irq_handler();
+        return;
+    }
+    
+    us_ticker_int_counter   = (uint32_t)(delta >> 16);
+    us_ticker_int_remainder = (uint16_t)(0xFFFF & delta);
+    if (us_ticker_int_counter > 0) {
+        lptmr_set(0xFFFF);
+        us_ticker_int_counter--;
+    } else {
+        lptmr_set(us_ticker_int_remainder);
+        us_ticker_int_remainder = 0;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/PeripheralNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    UART_0 = (int)LPC_USART_BASE
+} UARTName;
+
+typedef enum {
+    I2C_0 = (int)LPC_I2C_BASE
+} I2CName;
+
+typedef enum {
+    ADC0_0 = 0,
+    ADC0_1,
+    ADC0_2,
+    ADC0_3,
+    ADC0_4,
+    ADC0_5,
+    ADC0_6,
+    ADC0_7
+} ADCName;
+
+typedef enum {
+    SPI_0 = (int)LPC_SSP0_BASE,
+    SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+    PWM_1 = 0,
+    PWM_2,
+    PWM_3,
+    PWM_4,
+    PWM_5,
+    PWM_6,
+    PWM_7,
+    PWM_8,
+    PWM_9,
+    PWM_10,
+    PWM_11
+} PWMName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/PinNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,165 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  5
+
+typedef enum {
+    // LPC11U Pin Names
+    P0_0 = 0,
+    P0_1 = 1,
+    P0_2 = 2,
+    P0_3 = 3,
+    P0_4 = 4,
+    P0_5 = 5,
+    P0_6 = 6,
+    P0_7 = 7,
+    P0_8 = 8,
+    P0_9 = 9,
+    P0_10 = 10,
+    P0_11 = 11,
+    P0_12 = 12,
+    P0_13 = 13,
+    P0_14 = 14,
+    P0_15 = 15,
+    P0_16 = 16,
+    P0_17 = 17,
+    P0_18 = 18,
+    P0_19 = 19,
+    P0_20 = 20,
+    P0_21 = 21,
+    P0_22 = 22,
+    P0_23 = 23,
+    P0_24 = 24,
+    P0_25 = 25,
+    P0_26 = 26,
+    P0_27 = 27,
+
+    P1_0 = 32,
+    P1_1 = 33,
+    P1_2 = 34,
+    P1_3 = 35,
+    P1_4 = 36,
+    P1_5 = 37,
+    P1_6 = 38,
+    P1_7 = 39,
+    P1_8 = 40,
+    P1_9 = 41,
+    P1_10 = 42,
+    P1_11 = 43,
+    P1_12 = 44,
+    P1_13 = 45,
+    P1_14 = 46,
+    P1_15 = 47,
+    P1_16 = 48,
+    P1_17 = 49,
+    P1_18 = 50,
+    P1_19 = 51,
+    P1_20 = 52,
+    P1_21 = 53,
+    P1_22 = 54,
+    P1_23 = 55,
+    P1_24 = 56,
+    P1_25 = 57,
+    P1_26 = 58,
+    P1_27 = 59,
+    P1_28 = 60,
+    P1_29 = 61,
+
+    P1_31 = 63,
+
+    // mbed DIP Pin Names
+    p5  = P0_9,
+    p6  = P0_8,
+    p7  = P1_29,
+    p8  = P0_2,
+    p9  = P1_27,
+    p10 = P1_26,
+    p11 = P1_22,
+    p12 = P1_21,
+    p13 = P1_20,
+    p14 = P1_23,
+    p15 = P0_11,
+    p16 = P0_12,
+    p17 = P0_13,
+    p18 = P0_14,
+    p19 = P0_16,
+    p20 = P0_22,
+    p21 = P0_7,
+    p22 = P0_17,
+    p23 = P1_17,
+    p24 = P1_18,
+    p25 = P1_24,
+    p26 = P1_25,
+    p27 = P0_4,
+    p28 = P0_5,
+    p29 = P1_5,
+    p30 = P1_2,
+
+    p33 = P0_3,
+    p34 = P1_15,
+    p35 = P0_20,
+    p36 = P0_21,
+
+    // Other mbed Pin Names
+    LED1 = P1_8,
+    LED2 = P1_9,
+    LED3 = P1_10,
+    LED4 = P1_11,
+
+    USBTX = P0_19,
+    USBRX = P0_18,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+    CHANNEL0 = FLEX_INT0_IRQn,
+    CHANNEL1 = FLEX_INT1_IRQn,
+    CHANNEL2 = FLEX_INT2_IRQn,
+    CHANNEL3 = FLEX_INT3_IRQn,
+    CHANNEL4 = FLEX_INT4_IRQn,
+    CHANNEL5 = FLEX_INT5_IRQn,
+    CHANNEL6 = FLEX_INT6_IRQn,
+    CHANNEL7 = FLEX_INT7_IRQn
+} Channel;
+
+typedef enum {
+    PullUp = 2,
+    PullDown = 1,
+    PullNone = 0,
+    Repeater = 3,
+    OpenDrain = 4
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/PortNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0,
+    Port1 = 1
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/analogin_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,126 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogin_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#define ANALOGIN_MEDIAN_FILTER      1
+
+#define ADC_10BIT_RANGE             0x3FF
+#define ADC_12BIT_RANGE             0xFFF
+
+static inline int div_round_up(int x, int y) {
+  return (x + (y - 1)) / y;
+}
+
+static const PinMap PinMap_ADC[] = {
+    {P0_11, ADC0_0, 0x02},
+    {P0_12, ADC0_1, 0x02},
+    {P0_13, ADC0_2, 0x02},
+    {P0_14, ADC0_3, 0x02},
+    {P0_15, ADC0_4, 0x02},
+    {P0_16, ADC0_5, 0x01},
+    {P0_22, ADC0_6, 0x01},
+    {P0_23, ADC0_7, 0x01},
+    {NC   , NC    , 0   }
+};
+
+#define LPC_IOCON0_BASE (LPC_IOCON_BASE)
+#define LPC_IOCON1_BASE (LPC_IOCON_BASE + 0x60)
+
+#define ADC_RANGE    ADC_10BIT_RANGE
+
+void analogin_init(analogin_t *obj, PinName pin) {
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    if (obj->adc == (uint32_t)NC) {
+        error("ADC pin mapping failed");
+    }
+    
+    // Power up ADC
+    LPC_SYSCON->PDRUNCFG &= ~ (1 << 4);
+    LPC_SYSCON->SYSAHBCLKCTRL |= ((uint32_t)1 << 13);
+
+    uint32_t pin_number = (uint32_t)pin;
+    __IO uint32_t *reg = (pin_number < 32) ? (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) : (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
+
+    // set pin to ADC mode
+    *reg &= ~(1 << 7); // set ADMODE = 0 (analog mode)
+
+    uint32_t PCLK = SystemCoreClock;
+    uint32_t MAX_ADC_CLK = 4500000;
+    uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
+
+    LPC_ADC->CR = (0 << 0)      // no channels selected
+                | (clkdiv << 8) // max of 4.5MHz
+                | (0 << 16)     // BURST = 0, software controlled
+                | ( 0 << 17 );  // CLKS = 0, not applicable
+    
+    pinmap_pinout(pin, PinMap_ADC);
+}
+
+static inline uint32_t adc_read(analogin_t *obj) {
+    // Select the appropriate channel and start conversion
+    LPC_ADC->CR &= ~0xFF;
+    LPC_ADC->CR |= 1 << (int)obj->adc;
+    LPC_ADC->CR |= 1 << 24;
+    
+    // Repeatedly get the sample data until DONE bit
+    unsigned int data;
+    do {
+        data = LPC_ADC->GDR;
+    } while ((data & ((unsigned int)1 << 31)) == 0);
+    
+    // Stop conversion
+    LPC_ADC->CR &= ~(1 << 24);
+    
+    return (data >> 6) & ADC_RANGE; // 10 bit
+}
+
+static inline void order(uint32_t *a, uint32_t *b) {
+    if (*a > *b) {
+        uint32_t t = *a;
+        *a = *b;
+        *b = t;
+    }
+}
+
+static inline uint32_t adc_read_u32(analogin_t *obj) {
+    uint32_t value;
+#if ANALOGIN_MEDIAN_FILTER
+    uint32_t v1 = adc_read(obj);
+    uint32_t v2 = adc_read(obj);
+    uint32_t v3 = adc_read(obj);
+    order(&v1, &v2);
+    order(&v2, &v3);
+    order(&v1, &v2);
+    value = v2;
+#else
+    value = adc_read(obj);
+#endif
+    return value;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+    
+    return (value << 6) | ((value >> 4) & 0x003F); // 10 bit
+}
+
+float analogin_read(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+    return (float)value * (1.0f / (float)ADC_RANGE);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/device.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        0
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         1
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         1
+
+#define DEVICE_CAN              0
+
+#define DEVICE_RTC              0
+
+#define DEVICE_ETHERNET         0
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_SEMIHOST         1
+#define DEVICE_LOCALFILESYSTEM  1
+#define DEVICE_ID_LENGTH       32
+#define DEVICE_MAC_OFFSET      20
+
+#define DEVICE_SLEEP            1
+
+#define DEVICE_DEBUG_AWARENESS  0
+
+#define DEVICE_STDIO_MESSAGES   1
+
+#define DEVICE_ERROR_PATTERN    1
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+
+uint32_t gpio_set(PinName pin) {
+    int f = ((pin == P0_11) ||
+             (pin == P0_12) ||
+             (pin == P0_13) ||
+             (pin == P0_14)) ? (1) : (0);
+    
+    pin_function(pin, f);
+    
+    return (1 << ((int)pin & 0x1F));
+}
+
+void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
+    if(pin == NC) return;
+
+    obj->pin = pin;
+    obj->mask = gpio_set(pin);
+    
+    unsigned int port = (unsigned int)pin >> PORT_SHIFT;
+    
+    obj->reg_set = &LPC_GPIO->SET[port];
+    obj->reg_clr = &LPC_GPIO->CLR[port];
+    obj->reg_in  = &LPC_GPIO->PIN[port];
+    obj->reg_dir = &LPC_GPIO->DIR[port];
+    
+    gpio_dir(obj, direction);
+    switch (direction) {
+        case PIN_OUTPUT: pin_mode(pin, PullNone); break;
+        case PIN_INPUT : pin_mode(pin, PullDown); break;
+    }
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+    pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+    switch (direction) {
+        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_irq_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,133 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "error.h"
+
+#define CHANNEL_NUM    8
+#define LPC_GPIO_X LPC_GPIO_PIN_INT
+#define PININT_IRQ 0
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+
+static inline void handle_interrupt_in(uint32_t channel) {
+    uint32_t ch_bit = (1 << channel);
+    // Return immediately if:
+    //   * The interrupt was already served
+    //   * There is no user handler
+    //   * It is a level interrupt, not an edge interrupt
+    if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
+         (channel_ids[channel] == 0      ) ||
+         (LPC_GPIO_X->ISEL & ch_bit      ) ) return;
+
+    if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
+        irq_handler(channel_ids[channel], IRQ_RISE);
+        LPC_GPIO_X->RISE = ch_bit;
+    }
+    if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
+        irq_handler(channel_ids[channel], IRQ_FALL);
+    }
+    LPC_GPIO_X->IST = ch_bit;
+}
+
+void gpio_irq0(void) {handle_interrupt_in(0);}
+void gpio_irq1(void) {handle_interrupt_in(1);}
+void gpio_irq2(void) {handle_interrupt_in(2);}
+void gpio_irq3(void) {handle_interrupt_in(3);}
+void gpio_irq4(void) {handle_interrupt_in(4);}
+void gpio_irq5(void) {handle_interrupt_in(5);}
+void gpio_irq6(void) {handle_interrupt_in(6);}
+void gpio_irq7(void) {handle_interrupt_in(7);}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+    if (pin == NC) return -1;
+    
+    irq_handler = handler;
+    
+    int found_free_channel = 0;
+    int i = 0;
+    for (i=0; i<CHANNEL_NUM; i++) {
+        if (channel_ids[i] == 0) {
+            channel_ids[i] = id;
+            obj->ch = i;
+            found_free_channel = 1;
+            break;
+        }
+    }
+    if (!found_free_channel) return -1;
+    
+    /* Enable AHB clock to the GPIO domain. */
+    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
+    
+    /* Enable AHB clock to the FlexInt, GroupedInt domain. */
+    LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
+    
+    /* To select a pin for any of the eight pin interrupts, write the pin number
+     * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
+     * @see: mbed_capi/PinNames.h
+     */
+    LPC_SYSCON->PINTSEL[obj->ch] = (pin >> 5) ? (pin - 8) : (pin);
+    
+    // Interrupt Wake-Up Enable
+    LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
+    
+    void (*channels_irq)(void) = NULL;
+    switch (obj->ch) {
+        case 0: channels_irq = &gpio_irq0; break;
+        case 1: channels_irq = &gpio_irq1; break;
+        case 2: channels_irq = &gpio_irq2; break;
+        case 3: channels_irq = &gpio_irq3; break;
+        case 4: channels_irq = &gpio_irq4; break;
+        case 5: channels_irq = &gpio_irq5; break;
+        case 6: channels_irq = &gpio_irq6; break;
+        case 7: channels_irq = &gpio_irq7; break;
+    }
+    NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
+    NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+    
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+    channel_ids[obj->ch] = 0;
+    LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+    unsigned int ch_bit = (1 << obj->ch);
+    
+    // Clear interrupt
+    if (!(LPC_GPIO_X->ISEL & ch_bit))
+        LPC_GPIO_X->IST = ch_bit;
+    
+    // Edge trigger
+    LPC_GPIO_X->ISEL &= ~ch_bit;
+    if (event == IRQ_RISE) {
+        if (enable) {
+            LPC_GPIO_X->IENR |= ch_bit;
+        } else {
+            LPC_GPIO_X->IENR &= ~ch_bit;
+        }
+    } else {
+        if (enable) {
+            LPC_GPIO_X->IENF |= ch_bit;
+        } else {
+            LPC_GPIO_X->IENF &= ~ch_bit;
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/gpio_object.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName  pin;
+    uint32_t mask;
+
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_set;
+    __IO uint32_t *reg_clr;
+    __I  uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+    if (value)
+        *obj->reg_set = obj->mask;
+    else
+        *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,387 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_I2C_SDA[] = {
+    {P0_5, I2C_0, 1},
+    {NC  , NC   , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+    {P0_4, I2C_0, 1},
+    {NC  , NC,    0}
+};
+
+#define I2C_CONSET(x)       (x->i2c->CONSET)
+#define I2C_CONCLR(x)       (x->i2c->CONCLR)
+#define I2C_STAT(x)         (x->i2c->STAT)
+#define I2C_DAT(x)          (x->i2c->DAT)
+#define I2C_SCLL(x, val)    (x->i2c->SCLL = val)
+#define I2C_SCLH(x, val)    (x->i2c->SCLH = val)
+
+static const uint32_t I2C_addr_offset[2][4] = {
+    {0x0C, 0x20, 0x24, 0x28},
+    {0x30, 0x34, 0x38, 0x3C}
+};
+
+static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+    I2C_CONCLR(obj) = (start << 5)
+                    | (stop << 4)
+                    | (interrupt << 3)
+                    | (acknowledge << 2);
+}
+
+static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+    I2C_CONSET(obj) = (start << 5)
+                    | (stop << 4)
+                    | (interrupt << 3)
+                    | (acknowledge << 2);
+}
+
+// Clear the Serial Interrupt (SI)
+static inline void i2c_clear_SI(i2c_t *obj) {
+    i2c_conclr(obj, 0, 0, 1, 0);
+}
+
+static inline int i2c_status(i2c_t *obj) {
+    return I2C_STAT(obj);
+}
+
+// Wait until the Serial Interrupt (SI) is set
+static int i2c_wait_SI(i2c_t *obj) {
+    int timeout = 0;
+    while (!(I2C_CONSET(obj) & (1 << 3))) {
+        timeout++;
+        if (timeout > 100000) return -1;
+    }
+    return 0;
+}
+
+static inline void i2c_interface_enable(i2c_t *obj) {
+    I2C_CONSET(obj) = 0x40;
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+    LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5);
+    LPC_SYSCON->PRESETCTRL |= 1 << 1;
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+    // determine the SPI to use
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+    obj->i2c = (LPC_I2C_Type *)pinmap_merge(i2c_sda, i2c_scl);
+    
+    if ((int)obj->i2c == NC) {
+        error("I2C pin mapping failed");
+    }
+    
+    // enable power
+    i2c_power_enable(obj);
+    
+    // set default frequency at 100k
+    i2c_frequency(obj, 100000);
+    i2c_conclr(obj, 1, 1, 1, 1);
+    i2c_interface_enable(obj);
+    
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+}
+
+inline int i2c_start(i2c_t *obj) {
+    int status = 0;
+    // 8.1 Before master mode can be entered, I2CON must be initialised to:
+    //  - I2EN STA STO SI AA - -
+    //  -  1    0   0   0  x - -
+    // if AA = 0, it can't enter slave mode
+    i2c_conclr(obj, 1, 1, 1, 1);
+    
+    // The master mode may now be entered by setting the STA bit
+    // this will generate a start condition when the bus becomes free
+    i2c_conset(obj, 1, 0, 0, 1);
+    
+    i2c_wait_SI(obj);
+    status = i2c_status(obj);
+    
+    // Clear start bit now transmitted, and interrupt bit
+    i2c_conclr(obj, 1, 0, 0, 0);
+    return status;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+    int timeout = 0;
+
+    // write the stop bit
+    i2c_conset(obj, 0, 1, 0, 0);
+    i2c_clear_SI(obj);
+    
+    // wait for STO bit to reset
+    while(I2C_CONSET(obj) & (1 << 4)) {
+        timeout ++;
+        if (timeout > 100000) return 1;
+    }
+
+    return 0;
+}
+
+
+static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
+    // write the data
+    I2C_DAT(obj) = value;
+    
+    // clear SI to init a send
+    i2c_clear_SI(obj);
+    
+    // wait and return status
+    i2c_wait_SI(obj);
+    return i2c_status(obj);
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+    // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
+    if (last) {
+        i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
+    } else {
+        i2c_conset(obj, 0, 0, 0, 1); // send a ACK
+    }
+    
+    // accept byte
+    i2c_clear_SI(obj);
+    
+    // wait for it to arrive
+    i2c_wait_SI(obj);
+    
+    // return the data
+    return (I2C_DAT(obj) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+    // No peripheral clock divider on the M0
+    uint32_t PCLK = SystemCoreClock;
+    
+    uint32_t pulse = PCLK / (hz * 2);
+    
+    // I2C Rate
+    I2C_SCLL(obj, pulse);
+    I2C_SCLH(obj, pulse);
+}
+
+// The I2C does a read or a write as a whole operation
+// There are two types of error conditions it can encounter
+//  1) it can not obtain the bus
+//  2) it gets error responses at part of the transmission
+//
+// We tackle them as follows:
+//  1) we retry until we get the bus. we could have a "timeout" if we can not get it
+//      which basically turns it in to a 2)
+//  2) on error, we use the standard error mechanisms to report/debug
+//
+// Therefore an I2C transaction should always complete. If it doesn't it is usually
+// because something is setup wrong (e.g. wiring), and we don't need to programatically
+// check for that
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+    int count, status;
+    
+    status = i2c_start(obj);
+    
+    if ((status != 0x10) && (status != 0x08)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+    
+    status = i2c_do_write(obj, (address | 0x01), 1);
+    if (status != 0x40) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    // Read in all except last byte
+    for (count = 0; count < (length - 1); count++) {
+        int value = i2c_do_read(obj, 0);
+        status = i2c_status(obj);
+        if (status != 0x50) {
+            i2c_stop(obj);
+            return count;
+        }
+        data[count] = (char) value;
+    }
+
+    // read in last byte
+    int value = i2c_do_read(obj, 1);
+    status = i2c_status(obj);
+    if (status != 0x58) {
+        i2c_stop(obj);
+        return length - 1;
+    }
+    
+    data[count] = (char) value;
+    
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+    
+    return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+    int i, status;
+    
+    status = i2c_start(obj);
+    
+    if ((status != 0x10) && (status != 0x08)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+    
+    status = i2c_do_write(obj, (address & 0xFE), 1);
+    if (status != 0x18) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    
+    for (i=0; i<length; i++) {
+        status = i2c_do_write(obj, data[i], 0);
+        if(status != 0x28) {
+            i2c_stop(obj);
+            return i;
+        }
+    }
+    
+    // clearing the serial interrupt here might cause an unintended rewrite of the last byte
+    // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
+    // i2c_clear_SI(obj);
+    
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+    
+    return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+    i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+    return (i2c_do_read(obj, last) & 0xFF);
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+    int ack;
+    int status = i2c_do_write(obj, (data & 0xFF), 0);
+    
+    switch(status) {
+        case 0x18: case 0x28:       // Master transmit ACKs
+            ack = 1;
+            break;
+        case 0x40:                  // Master receive address transmitted ACK
+            ack = 1;
+            break;
+        case 0xB8:                  // Slave transmit ACK
+            ack = 1;
+            break;
+        default:
+            ack = 0;
+            break;
+    }
+
+    return ack;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+    if (enable_slave != 0) {
+        i2c_conclr(obj, 1, 1, 1, 0);
+        i2c_conset(obj, 0, 0, 0, 1);
+    } else {
+        i2c_conclr(obj, 1, 1, 1, 1);
+    }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+    int status;
+    int retval;
+    
+    status = i2c_status(obj);
+    switch(status) {
+        case 0x60: retval = 3; break;
+        case 0x70: retval = 2; break;
+        case 0xA8: retval = 1; break;
+        default  : retval = 0; break;
+    }
+    
+    return(retval);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+    int count = 0;
+    int status;
+    
+    do {
+        i2c_clear_SI(obj);
+        i2c_wait_SI(obj);
+        status = i2c_status(obj);
+        if((status == 0x80) || (status == 0x90)) {
+            data[count] = I2C_DAT(obj) & 0xFF;
+        }
+        count++;
+    } while (((status == 0x80) || (status == 0x90) ||
+            (status == 0x060) || (status == 0x70)) && (count < length));
+    
+    if(status != 0xA0) {
+        i2c_stop(obj);
+    }
+    
+    i2c_clear_SI(obj);
+    
+    return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+    int count = 0;
+    int status;
+    
+    if(length <= 0) {
+        return(0);
+    }
+    
+    do {
+        status = i2c_do_write(obj, data[count], 0);
+        count++;
+    } while ((count < length) && (status == 0xB8));
+    
+    if((status != 0xC0) && (status != 0xC8)) {
+        i2c_stop(obj);
+    }
+    
+    i2c_clear_SI(obj);
+    
+    return(count);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+    uint32_t addr;
+    
+    if ((idx >= 0) && (idx <= 3)) {
+        addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
+        *((uint32_t *) addr) = address & 0xFF;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/objects.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    uint32_t ch;
+};
+
+struct port_s {
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_mpin;
+    PortName port;
+    uint32_t mask;
+};
+
+struct pwmout_s {
+    PWMName pwm;
+};
+
+struct serial_s {
+    LPC_USART_Type *uart;
+    int index;
+};
+
+struct analogin_s {
+    ADCName adc;
+};
+
+struct i2c_s {
+    LPC_I2C_Type *i2c;
+};
+
+struct spi_s {
+    LPC_SSPx_Type *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/pinmap.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "error.h"
+
+#define LPC_IOCON0_BASE (LPC_IOCON_BASE)
+#define LPC_IOCON1_BASE (LPC_IOCON_BASE + 0x60)
+
+void pin_function(PinName pin, int function) {
+    if (pin == (uint32_t)NC) return;
+    
+    uint32_t pin_number = (uint32_t)pin;
+    
+    __IO uint32_t *reg = (pin_number < 32) ?
+            (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
+            (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
+    
+    // pin function bits: [2:0] -> 111 = (0x7)
+    *reg = (*reg & ~0x7) | (function & 0x7);
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+    if (pin == (uint32_t)NC) { return; }
+    
+    uint32_t pin_number = (uint32_t)pin;
+    uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2;
+    
+    __IO uint32_t *reg = (pin_number < 32) ?
+            (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
+            (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
+    uint32_t tmp = *reg;
+    
+    // pin mode bits: [4:3] -> 11000 = (0x3 << 3)
+    tmp &= ~(0x3 << 3);
+    tmp |= (mode & 0x3) << 3;
+    
+    // drain
+    tmp &= ~(0x1 << 10);
+    tmp |= drain << 10;
+    
+    *reg = tmp;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/port_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+
+PinName port_pin(PortName port, int pin_n) {
+    return (PinName)((port << PORT_SHIFT) | pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+    obj->port = port;
+    obj->mask = mask;
+    
+    LPC_GPIO->MASK[port] = ~mask;
+    
+    obj->reg_mpin = &LPC_GPIO->MPIN[port];
+    obj->reg_dir = &LPC_GPIO->DIR[port];
+    
+    uint32_t i;
+    // The function is set per pin: reuse gpio logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            gpio_set(port_pin(obj->port, i));
+        }
+    }
+    
+    port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+    uint32_t i;
+    // The mode is set per pin: reuse pinmap logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+    switch (dir) {
+        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
+    }
+}
+
+void port_write(port_t *obj, int value) {
+    *obj->reg_mpin = value;
+}
+
+int port_read(port_t *obj) {
+    return (*obj->reg_mpin);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/pwmout_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,183 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#define TCR_CNT_EN       0x00000001
+#define TCR_RESET        0x00000002
+
+/* To have a PWM where we can change both the period and the duty cycle,
+ * we need an entire timer. With the following conventions:
+ *   * MR3 is used for the PWM period
+ *   * MR0, MR1, MR2 are used for the duty cycle
+ */
+static const PinMap PinMap_PWM[] = {
+    /* CT16B0 */
+    {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2},    /* MR0 */
+    {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2},   /* MR1 */
+    {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2},   /* MR2 */
+
+    /* CT16B1 */
+    {P0_21, PWM_4, 1},                      /* MR0 */
+    {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1},   /* MR1 */
+
+    /* CT32B0 */
+    {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1},   /* MR0 */
+    {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1},   /* MR1 */
+    {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1},   /* MR2 */
+
+    /* CT32B1 */
+    {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1},  /* MR0 */
+    {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1},  /* MR1 */
+    {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1},  /* MR2 */
+
+    {NC, NC, 0}
+};
+
+typedef struct {
+    uint8_t timer;
+    uint8_t mr;
+} timer_mr;
+
+static timer_mr pwm_timer_map[11] = {
+    {0, 0}, {0, 1}, {0, 2},
+    {1, 0}, {1, 1},
+    {2, 0}, {2, 1}, {2, 2},
+    {3, 0}, {3, 1}, {3, 2},
+};
+
+static LPC_CTxxBx_Type *Timers[4] = {
+    LPC_CT16B0, LPC_CT16B1,
+    LPC_CT32B0, LPC_CT32B1
+};
+
+static unsigned int pwm_clock_mhz;
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+    // determine the channel
+    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+    if (pwm == (uint32_t)NC)
+        error("PwmOut pin mapping failed");
+    
+    obj->pwm = pwm;
+    
+    // Timer registers
+    timer_mr tid = pwm_timer_map[pwm];
+    LPC_CTxxBx_Type *timer = Timers[tid.timer];
+    
+    // Disable timer
+    timer->TCR = 0;
+    
+    // Power the correspondent timer
+    LPC_SYSCON->SYSAHBCLKCTRL |= 1 << (tid.timer + 7);
+    
+    /* Enable PWM function */
+    timer->PWMC = (1 << 3)|(1 << 2)|(1 << 1)|(1 << 0);
+    
+    /* Reset Functionality on MR3 controlling the PWM period */
+    timer->MCR = 1 << 10;
+    
+    pwm_clock_mhz = SystemCoreClock / 1000000;
+    
+    // default to 20ms: standard for servos, and fine for e.g. brightness control
+    pwmout_period_ms(obj, 20);
+    pwmout_write    (obj, 0);
+    
+    // Wire pinout
+    pinmap_pinout(pin, PinMap_PWM);
+}
+
+void pwmout_free(pwmout_t* obj) {
+    // [TODO]
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+    if (value < 0.0f) {
+        value = 0.0;
+    } else if (value > 1.0f) {
+        value = 1.0;
+    }
+    
+    timer_mr tid = pwm_timer_map[obj->pwm];
+    LPC_CTxxBx_Type *timer = Timers[tid.timer];
+    uint32_t t_off = timer->MR3 - (uint32_t)((float)(timer->MR3) * value);
+    
+    timer->TCR = TCR_RESET;
+    timer->MR[tid.mr] = t_off;
+    timer->TCR = TCR_CNT_EN;
+}
+
+float pwmout_read(pwmout_t* obj) {
+    timer_mr tid = pwm_timer_map[obj->pwm];
+    LPC_CTxxBx_Type *timer = Timers[tid.timer];
+    
+    float v = (float)(timer->MR3 - timer->MR[tid.mr]) / (float)(timer->MR3);
+    return (v > 1.0f) ? (1.0f) : (v);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+    pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+    pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+    int i = 0;
+    uint32_t period_ticks = pwm_clock_mhz * us;
+    
+    timer_mr tid = pwm_timer_map[obj->pwm];
+    LPC_CTxxBx_Type *timer = Timers[tid.timer];
+    uint32_t old_period_ticks = timer->MR3;
+    
+    timer->TCR = TCR_RESET;
+    timer->MR3 = period_ticks;
+    
+    // Scale the pulse width to preserve the duty ratio
+    if (old_period_ticks > 0) {
+        for (i=0; i<3; i++) {
+            uint32_t t_off = period_ticks - (uint32_t)(((uint64_t)timer->MR[i] * (uint64_t)period_ticks) / (uint64_t)old_period_ticks);
+            timer->MR[i] = t_off;
+        }
+    }
+    timer->TCR = TCR_CNT_EN;
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+    uint32_t t_on = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000);
+    timer_mr tid = pwm_timer_map[obj->pwm];
+    LPC_CTxxBx_Type *timer = Timers[tid.timer];
+    
+    timer->TCR = TCR_RESET;
+    if (t_on > timer->MR3) {
+        pwmout_period_us(obj, us);
+    }
+    uint32_t t_off = timer->MR3 - t_on;
+    timer->MR[tid.mr] = t_off;
+    timer->TCR = TCR_CNT_EN;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/serial_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,282 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include <string.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+#define UART_NUM    1
+
+static const PinMap PinMap_UART_TX[] = {
+    {P0_19, UART_0, 1},
+    {P1_13, UART_0, 3},
+    {P1_27, UART_0, 2},
+    { NC  , NC    , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+    {P0_18, UART_0, 1},
+    {P1_14, UART_0, 3},
+    {P1_26, UART_0, 2},
+    {NC   , NC    , 0}
+};
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+    int is_stdio_uart = 0;
+    
+    // determine the UART to use
+    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+    UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    if ((int)uart == NC) {
+        error("Serial pinout mapping failed");
+    }
+    
+    obj->uart = (LPC_USART_Type *)uart;
+    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
+    
+    // [TODO] Consider more elegant approach
+    // disconnect USBTX/RX mapping mux, for case when switching ports
+    pin_function(USBTX, 0);
+    pin_function(USBRX, 0);
+    
+    // enable fifos and default rx trigger level
+    obj->uart->FCR = 1 << 0  // FIFO Enable - 0 = Disables, 1 = Enabled
+                   | 0 << 1  // Rx Fifo Reset
+                   | 0 << 2  // Tx Fifo Reset
+                   | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
+    
+    // disable irqs
+    obj->uart->IER = 0 << 0  // Rx Data available irq enable
+                   | 0 << 1  // Tx Fifo empty irq enable
+                   | 0 << 2; // Rx Line Status irq enable
+    
+    // set default baud rate and format
+    serial_baud  (obj, 9600);
+    serial_format(obj, 8, ParityNone, 1);
+    
+    // pinout the chosen uart
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+    
+    // set rx/tx pins in PullUp mode
+    pin_mode(tx, PullUp);
+    pin_mode(rx, PullUp);
+    
+    switch (uart) {
+        case UART_0: obj->index = 0; break;
+    }
+    
+    is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+    
+    if (is_stdio_uart) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj) {
+    serial_irq_ids[obj->index] = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+    LPC_SYSCON->UARTCLKDIV = 0x1;
+    uint32_t PCLK = SystemCoreClock;
+    // First we check to see if the basic divide with no DivAddVal/MulVal
+    // ratio gives us an integer result. If it does, we set DivAddVal = 0,
+    // MulVal = 1. Otherwise, we search the valid ratio value range to find
+    // the closest match. This could be more elegant, using search methods
+    // and/or lookup tables, but the brute force method is not that much
+    // slower, and is more maintainable.
+    uint16_t DL = PCLK / (16 * baudrate);
+    
+    uint8_t DivAddVal = 0;
+    uint8_t MulVal = 1;
+    int hit = 0;
+    uint16_t dlv;
+    uint8_t mv, dav;
+    if ((PCLK % (16 * baudrate)) != 0) {     // Checking for zero remainder
+        float err_best = (float) baudrate;
+        uint16_t dlmax = DL;
+        for ( dlv = (dlmax/2); (dlv <= dlmax) && !hit; dlv++) {
+            for ( mv = 1; mv <= 15; mv++) {
+                for ( dav = 1; dav < mv; dav++) {
+                    float ratio = 1.0f + ((float) dav / (float) mv);
+                    float calcbaud = (float)PCLK / (16.0f * (float) dlv * ratio);
+                    float err = fabs(((float) baudrate - calcbaud) / (float) baudrate);
+                    if (err < err_best) {
+                        DL = dlv;
+                        DivAddVal = dav;
+                        MulVal = mv;
+                        err_best = err;
+                        if (err < 0.001f) {
+                            hit = 1;
+                        }
+                    }
+                }
+            }
+        }
+    }
+    
+    // set LCR[DLAB] to enable writing to divider registers
+    obj->uart->LCR |= (1 << 7);
+    
+    // set divider values
+    obj->uart->DLM = (DL >> 8) & 0xFF;
+    obj->uart->DLL = (DL >> 0) & 0xFF;
+    obj->uart->FDR = (uint32_t) DivAddVal << 0
+                   | (uint32_t) MulVal    << 4;
+    
+    // clear LCR[DLAB]
+    obj->uart->LCR &= ~(1 << 7);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+    // 0: 1 stop bits, 1: 2 stop bits
+    if (stop_bits != 1 && stop_bits != 2) {
+        error("Invalid stop bits specified");
+    }
+    stop_bits -= 1;
+    
+    // 0: 5 data bits ... 3: 8 data bits
+    if (data_bits < 5 || data_bits > 8) {
+        error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
+    }
+    data_bits -= 5;
+
+    int parity_enable, parity_select;
+    switch (parity) {
+        case ParityNone: parity_enable = 0; parity_select = 0; break;
+        case ParityOdd : parity_enable = 1; parity_select = 0; break;
+        case ParityEven: parity_enable = 1; parity_select = 1; break;
+        case ParityForced1: parity_enable = 1; parity_select = 2; break;
+        case ParityForced0: parity_enable = 1; parity_select = 3; break;
+        default:
+            error("Invalid serial parity setting");
+            return;
+    }
+    
+    obj->uart->LCR = data_bits            << 0
+                   | stop_bits            << 2
+                   | parity_enable        << 3
+                   | parity_select        << 4;
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t iir, uint32_t index) {
+    // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
+    SerialIrq irq_type;
+    switch (iir) {
+        case 1: irq_type = TxIrq; break;
+        case 2: irq_type = RxIrq; break;
+        default: return;
+    }
+    
+    if (serial_irq_ids[index] != 0)
+        irq_handler(serial_irq_ids[index], irq_type);
+}
+
+void uart0_irq() {uart_irq((LPC_USART->IIR >> 1) & 0x7, 0);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;
+    switch ((int)obj->uart) {
+        case UART_0: irq_n=UART_IRQn ; vector = (uint32_t)&uart0_irq; break;
+    }
+    
+    if (enable) {
+        obj->uart->IER |= 1 << irq;
+        NVIC_SetVector(irq_n, vector);
+        NVIC_EnableIRQ(irq_n);
+    } else { // disable
+        int all_disabled = 0;
+        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+
+        obj->uart->IER &= ~(1 << irq);
+        all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
+        
+        if (all_disabled)
+            NVIC_DisableIRQ(irq_n);
+    }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+    while (!serial_readable(obj));
+    return obj->uart->RBR;
+}
+
+void serial_putc(serial_t *obj, int c) {
+    while (!serial_writable(obj));
+    obj->uart->THR = c;
+    
+    uint32_t lsr = obj->uart->LSR;
+    lsr = lsr;
+    uint32_t thr = obj->uart->THR;
+    thr = thr;
+}
+
+int serial_readable(serial_t *obj) {
+    return obj->uart->LSR & 0x01;
+}
+
+int serial_writable(serial_t *obj) {
+    return obj->uart->LSR & 0x20;
+}
+
+void serial_clear(serial_t *obj) {
+    obj->uart->FCR = 1 << 1  // rx FIFO reset
+                   | 1 << 2  // tx FIFO reset
+                   | 0 << 6; // interrupt depth
+}
+
+void serial_pinout_tx(PinName tx) {
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+    obj->uart->LCR |= (1 << 6);
+}
+
+void serial_break_clear(serial_t *obj) {
+    obj->uart->LCR &= ~(1 << 6);
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/sleep.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+
+void sleep(void) {
+    // ensure debug is disconnected
+    mbed_interface_disconnect();
+    
+    // PCON[PD] set to sleep
+    LPC_PMU->PCON = 0x0;
+    
+    // SRC[SLEEPDEEP] set to 0 = sleep
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    
+    // wait for interrupt
+    __WFI();
+}
+
+/*
+* The mbed lpc1768 does not support the deepsleep mode
+* as a debugger is connected to it (the mbed interface).
+*
+* As mentionned in an application note from NXP:
+*
+*       http://www.po-star.com/public/uploads/20120319123122_141.pdf
+*
+*       {{{
+*       The user should be aware of certain limitations during debugging.
+*       The most important is that, due to limitations of the Cortex-M3
+*       integration, the LPC17xx cannot wake up in the usual manner from
+*       Deep Sleep and Power-down modes. It is recommended not to use these
+*       modes during debug. Once an application is downloaded via JTAG/SWD
+*       interface, the USB to SWD/JTAG debug adapter (Keil ULINK2 for example)
+*       should be removed from the target board, and thereafter, power cycle
+*       the LPC17xx to allow wake-up from deep sleep and power-down modes
+*       }}}
+*
+*       As the interface firmware does not reset the target when a
+*       mbed_interface_disconnect() semihosting call is made, the
+*       core cannot wake-up from deepsleep.
+*
+*       We treat a deepsleep() as a normal sleep().
+*/
+
+void deepsleep(void) {
+    // ensure debug is disconnected
+    mbed_interface_disconnect();
+    
+    // PCON[PD] set to deepsleep
+    LPC_PMU->PCON = 0x1;
+    
+    // SRC[SLEEPDEEP] set to 1 = deep sleep
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+    
+    // Power up everything after powerdown
+    LPC_SYSCON->PDAWAKECFG &= 0xFFFFF800;
+    
+    // wait for interrupt
+    __WFI();
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/spi_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,218 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_SPI_SCLK[] = {
+    {P0_6 , SPI_0, 0x02},
+    {P0_10, SPI_0, 0x02},
+    {P1_29, SPI_0, 0x01},
+    {P1_15, SPI_1, 0x03},
+    {P1_20, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+    {P0_9 , SPI_0, 0x01},
+    {P0_21, SPI_1, 0x02},
+    {P1_22, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+    {P0_8 , SPI_0, 0x01},
+    {P0_22, SPI_1, 0x03},
+    {P1_21, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+    {P0_2 , SPI_0, 0x01},
+    {P1_19, SPI_1, 0x02},
+    {P1_23, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    // determine the SPI to use
+    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+    
+    obj->spi = (LPC_SSPx_Type*)pinmap_merge(spi_data, spi_cntl);
+    
+    if ((int)obj->spi == NC) {
+        error("SPI pinout mapping failed");
+    }
+    
+    // enable power and clocking
+    switch ((int)obj->spi) {
+        case SPI_0:
+            LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
+            LPC_SYSCON->SSP0CLKDIV = 0x01;
+            LPC_SYSCON->PRESETCTRL |= 1 << 0;
+            break;
+        case SPI_1:
+            LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
+            LPC_SYSCON->SSP1CLKDIV = 0x01;
+            LPC_SYSCON->PRESETCTRL |= 1 << 2;
+            break;
+    }
+    
+    // set default format and frequency
+    if (ssel == NC) {
+        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
+    } else {
+        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
+    }
+    spi_frequency(obj, 1000000);
+    
+    // enable the ssp channel
+    ssp_enable(obj);
+    
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+    ssp_disable(obj);
+    
+    if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
+        error("SPI format error");
+    }
+    
+    int polarity = (mode & 0x2) ? 1 : 0;
+    int phase = (mode & 0x1) ? 1 : 0;
+    
+    // set it up
+    int DSS = bits - 1;            // DSS (data select size)
+    int SPO = (polarity) ? 1 : 0;  // SPO - clock out polarity
+    int SPH = (phase) ? 1 : 0;     // SPH - clock out phase
+    
+    int FRF = 0;                   // FRF (frame format) = SPI
+    uint32_t tmp = obj->spi->CR0;
+    tmp &= ~(0xFFFF);
+    tmp |= DSS << 0
+        | FRF << 4
+        | SPO << 6
+        | SPH << 7;
+    obj->spi->CR0 = tmp;
+    
+    tmp = obj->spi->CR1;
+    tmp &= ~(0xD);
+    tmp |= 0 << 0                   // LBM - loop back mode - off
+        | ((slave) ? 1 : 0) << 2   // MS - master slave mode, 1 = slave
+        | 0 << 3;                  // SOD - slave output disable - na
+    obj->spi->CR1 = tmp;
+    
+    ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+    ssp_disable(obj);
+    
+    uint32_t PCLK = SystemCoreClock;
+    
+    int prescaler;
+    
+    for (prescaler = 2; prescaler <= 254; prescaler += 2) {
+        int prescale_hz = PCLK / prescaler;
+        
+        // calculate the divider
+        int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
+        
+        // check we can support the divider
+        if (divider < 256) {
+            // prescaler
+            obj->spi->CPSR = prescaler;
+            
+            // divider
+            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 |= (divider - 1) << 8;
+            ssp_enable(obj);
+            return;
+        }
+    }
+    error("Couldn't setup requested SPI frequency");
+}
+
+static inline int ssp_disable(spi_t *obj) {
+    return obj->spi->CR1 &= ~(1 << 1);
+}
+
+static inline int ssp_enable(spi_t *obj) {
+    return obj->spi->CR1 |= (1 << 1);
+}
+
+static inline int ssp_readable(spi_t *obj) {
+    return obj->spi->SR & (1 << 2);
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+    return obj->spi->SR & (1 << 1);
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+    while (!ssp_writeable(obj));
+    obj->spi->DR = value;
+}
+
+static inline int ssp_read(spi_t *obj) {
+    while (!ssp_readable(obj));
+    return obj->spi->DR;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+    return (obj->spi->SR & (1 << 4)) ? (1) : (0);
+}
+
+int spi_master_write(spi_t *obj, int value) {
+    ssp_write(obj, value);
+    return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+    return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+};
+
+int spi_slave_read(spi_t *obj) {
+    return obj->spi->DR;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+    while (ssp_writeable(obj) == 0) ;
+    obj->spi->DR = value;
+}
+
+int spi_busy(spi_t *obj) {
+    return ssp_busy(obj);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/us_ticker.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+#define US_TICKER_TIMER          ((LPC_CTxxBx_Type *)LPC_CT32B1_BASE)
+#define US_TICKER_TIMER_IRQn     TIMER_32_1_IRQn
+
+int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+    if (us_ticker_inited) return;
+    us_ticker_inited = 1;
+    
+    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10); // Clock TIMER_1
+    uint32_t PCLK = SystemCoreClock;
+    
+    US_TICKER_TIMER->TCR = 0x2;  // reset
+    
+    uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks)
+    US_TICKER_TIMER->PR = prescale - 1;
+    US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0
+    
+    NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+uint32_t us_ticker_read() {
+    if (!us_ticker_inited)
+        us_ticker_init();
+    
+    return US_TICKER_TIMER->TC;
+}
+
+void us_ticker_set_interrupt(unsigned int timestamp) {
+    // set match value
+    US_TICKER_TIMER->MR0 = timestamp;
+    // enable match interrupt
+    US_TICKER_TIMER->MCR |= 1;
+}
+
+void us_ticker_disable_interrupt(void) {
+    US_TICKER_TIMER->MCR &= ~1;
+}
+
+void us_ticker_clear_interrupt(void) {
+    US_TICKER_TIMER->IR = 1;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/PeripheralNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    UART_0 = (int)LPC_USART_BASE
+} UARTName;
+
+typedef enum {
+    I2C_0 = (int)LPC_I2C_BASE
+} I2CName;
+
+typedef enum {
+    ADC0_0 = 0,
+    ADC0_1,
+    ADC0_2,
+    ADC0_3,
+    ADC0_4,
+    ADC0_5,
+    ADC0_6,
+    ADC0_7
+} ADCName;
+
+typedef enum {
+    SPI_0 = (int)LPC_SSP0_BASE,
+    SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+    PWM_1 = 0,
+    PWM_2,
+    PWM_3,
+    PWM_4,
+    PWM_5,
+    PWM_6,
+    PWM_7,
+    PWM_8,
+    PWM_9,
+    PWM_10,
+    PWM_11
+} PWMName;
+
+#define STDIO_UART_TX     UART_TX
+#define STDIO_UART_RX     UART_RX
+#define STDIO_UART        UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/PinNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,150 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  5
+
+typedef enum {
+    // LPC1347 Pin Names
+    P0_0 = 0,
+    P0_1 = 1,
+    P0_2 = 2,
+    P0_3 = 3,
+    P0_4 = 4,
+    P0_5 = 5,
+    P0_6 = 6,
+    P0_7 = 7,
+    P0_8 = 8,
+    P0_9 = 9,
+    P0_10 = 10,
+    P0_11 = 11,
+    P0_12 = 12,
+    P0_13 = 13,
+    P0_14 = 14,
+    P0_15 = 15,
+    P0_16 = 16,
+    P0_17 = 17,
+    P0_18 = 18,
+    P0_19 = 19,
+    P0_20 = 20,
+    P0_21 = 21,
+    P0_22 = 22,
+    P0_23 = 23,
+
+    P1_13 = 45,
+    P1_14 = 46,
+    P1_15 = 47,
+    P1_16 = 48,
+
+    P1_19 = 51,
+    P1_20 = 52,
+    P1_21 = 53,
+    P1_22 = 54,
+    P1_23 = 55,
+    P1_24 = 56,
+    P1_25 = 57,
+    P1_26 = 58,
+    P1_27 = 59,
+    P1_28 = 60,
+    P1_29 = 61,
+
+    P1_31 = 63,
+
+    // DIP Pin Names
+    p1  = P0_0,
+    p2  = P0_11,
+    p3  = P0_12,
+    p4  = P0_13,
+    p5  = P0_14,
+    p6  = P1_31,
+    p8  = P0_16,
+    p9  = P0_22,
+    p10 = P0_23,
+    p13 = P1_29,
+    p14 = P1_21,
+    p15 = P0_8,
+    p16 = P0_9,
+    p17 = P1_24,
+    p18 = P0_4,
+    p19 = P1_13,
+    p20 = P1_14,
+    p21 = P1_22,
+    p22 = P0_17,
+    p23 = P0_5,
+    p24 = P0_21,
+    p25 = P0_19,
+    p26 = P0_18,
+    p27 = P1_15,
+    p28 = P1_16,
+    p29 = P1_25,
+    p30 = P1_19,
+    p33 = P0_20,
+    p34 = P0_2,
+    p35 = P1_26,
+    p36 = P1_27,
+    p37 = P1_20,
+    p38 = P1_23,
+    p39 = P0_7,
+    p40 = P1_28,
+
+    UART_TX = P0_19,
+    UART_RX = P0_18,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF,
+
+    LED1 = p21,
+    LED2 = p21,
+    LED3 = p21,
+    LED4 = p21
+} PinName;
+
+typedef enum {
+    CHANNEL0 = PIN_INT0_IRQn,
+    CHANNEL1 = PIN_INT1_IRQn,
+    CHANNEL2 = PIN_INT2_IRQn,
+    CHANNEL3 = PIN_INT3_IRQn,
+    CHANNEL4 = PIN_INT4_IRQn,
+    CHANNEL5 = PIN_INT5_IRQn,
+    CHANNEL6 = PIN_INT6_IRQn,
+    CHANNEL7 = PIN_INT7_IRQn
+} Channel;
+
+typedef enum {
+    PullUp = 2,
+    PullDown = 1,
+    PullNone = 0,
+    Repeater = 3,
+    OpenDrain = 4
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/PortNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0,
+    Port1 = 1
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/analogin_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,126 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogin_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#define ANALOGIN_MEDIAN_FILTER      1
+
+#define ADC_10BIT_RANGE             0x3FF
+#define ADC_12BIT_RANGE             0xFFF
+
+static inline int div_round_up(int x, int y) {
+  return (x + (y - 1)) / y;
+}
+
+static const PinMap PinMap_ADC[] = {
+    {P0_11, ADC0_0, 0x02},
+    {P0_12, ADC0_1, 0x02},
+    {P0_13, ADC0_2, 0x02},
+    {P0_14, ADC0_3, 0x02},
+    {P0_15, ADC0_4, 0x02},
+    {P0_16, ADC0_5, 0x01},
+    {P0_22, ADC0_6, 0x01},
+    {P0_23, ADC0_7, 0x01},
+    {NC   , NC    , 0   }
+};
+
+#define LPC_IOCON0_BASE (LPC_IOCON_BASE)
+#define LPC_IOCON1_BASE (LPC_IOCON_BASE + 0x60)
+
+#define ADC_RANGE    ADC_10BIT_RANGE
+
+void analogin_init(analogin_t *obj, PinName pin) {
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    if (obj->adc == (uint32_t)NC) {
+        error("ADC pin mapping failed");
+    }
+    
+    // Power up ADC
+    LPC_SYSCON->PDRUNCFG &= ~ (1 << 4);
+    LPC_SYSCON->SYSAHBCLKCTRL |= ((uint32_t)1 << 13);
+
+    uint32_t pin_number = (uint32_t)pin;
+    __IO uint32_t *reg = (pin_number < 32) ? (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) : (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
+
+    // set pin to ADC mode
+    *reg &= ~(1 << 7); // set ADMODE = 0 (analog mode)
+
+    uint32_t PCLK = SystemCoreClock;
+    uint32_t MAX_ADC_CLK = 4500000;
+    uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
+
+    LPC_ADC->CR = (0 << 0)      // no channels selected
+                | (clkdiv << 8) // max of 4.5MHz
+                | (0 << 16)     // BURST = 0, software controlled
+                | ( 0 << 17 );  // CLKS = 0, not applicable
+    
+    pinmap_pinout(pin, PinMap_ADC);
+}
+
+static inline uint32_t adc_read(analogin_t *obj) {
+    // Select the appropriate channel and start conversion
+    LPC_ADC->CR &= ~0xFF;
+    LPC_ADC->CR |= 1 << (int)obj->adc;
+    LPC_ADC->CR |= 1 << 24;
+    
+    // Repeatedly get the sample data until DONE bit
+    unsigned int data;
+    do {
+        data = LPC_ADC->GDR;
+    } while ((data & ((unsigned int)1 << 31)) == 0);
+    
+    // Stop conversion
+    LPC_ADC->CR &= ~(1 << 24);
+    
+    return (data >> 6) & ADC_RANGE; // 10 bit
+}
+
+static inline void order(uint32_t *a, uint32_t *b) {
+    if (*a > *b) {
+        uint32_t t = *a;
+        *a = *b;
+        *b = t;
+    }
+}
+
+static inline uint32_t adc_read_u32(analogin_t *obj) {
+    uint32_t value;
+#if ANALOGIN_MEDIAN_FILTER
+    uint32_t v1 = adc_read(obj);
+    uint32_t v2 = adc_read(obj);
+    uint32_t v3 = adc_read(obj);
+    order(&v1, &v2);
+    order(&v2, &v3);
+    order(&v1, &v2);
+    value = v2;
+#else
+    value = adc_read(obj);
+#endif
+    return value;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+    
+    return (value << 6) | ((value >> 4) & 0x003F); // 10 bit
+}
+
+float analogin_read(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+    return (float)value * (1.0f / (float)ADC_RANGE);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/device.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        0
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         1
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         1
+
+#define DEVICE_CAN              0
+
+#define DEVICE_RTC              0
+
+#define DEVICE_ETHERNET         0
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_SEMIHOST         0
+#define DEVICE_LOCALFILESYSTEM  0
+#define DEVICE_ID_LENGTH       32
+#define DEVICE_MAC_OFFSET      20
+
+#define DEVICE_SLEEP            1
+
+#define DEVICE_DEBUG_AWARENESS  0
+
+#define DEVICE_STDIO_MESSAGES   1
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+
+uint32_t gpio_set(PinName pin) {
+    int f = ((pin == P0_11) ||
+             (pin == P0_12) ||
+             (pin == P0_13) ||
+             (pin == P0_14)) ? (1) : (0);
+    
+    pin_function(pin, f);
+    
+    return (1 << ((int)pin & 0x1F));
+}
+
+void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
+    if(pin == NC) return;
+
+    obj->pin = pin;
+    obj->mask = gpio_set(pin);
+    
+    unsigned int port = (unsigned int)pin >> PORT_SHIFT;
+    
+    obj->reg_set = &LPC_GPIO->SET[port];
+    obj->reg_clr = &LPC_GPIO->CLR[port];
+    obj->reg_in  = &LPC_GPIO->PIN[port];
+    obj->reg_dir = &LPC_GPIO->DIR[port];
+    
+    gpio_dir(obj, direction);
+    switch (direction) {
+        case PIN_OUTPUT: pin_mode(pin, PullNone); break;
+        case PIN_INPUT : pin_mode(pin, PullDown); break;
+    }
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+    pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+    switch (direction) {
+        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_irq_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,133 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "error.h"
+
+#define CHANNEL_NUM    8
+#define LPC_GPIO_X LPC_GPIO_PIN_INT
+#define PININT_IRQ 0
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+
+static inline void handle_interrupt_in(uint32_t channel) {
+    uint32_t ch_bit = (1 << channel);
+    // Return immediately if:
+    //   * The interrupt was already served
+    //   * There is no user handler
+    //   * It is a level interrupt, not an edge interrupt
+    if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
+         (channel_ids[channel] == 0      ) ||
+         (LPC_GPIO_X->ISEL & ch_bit      ) ) return;
+
+    if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
+        irq_handler(channel_ids[channel], IRQ_RISE);
+        LPC_GPIO_X->RISE = ch_bit;
+    }
+    if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
+        irq_handler(channel_ids[channel], IRQ_FALL);
+    }
+    LPC_GPIO_X->IST = ch_bit;
+}
+
+void gpio_irq0(void) {handle_interrupt_in(0);}
+void gpio_irq1(void) {handle_interrupt_in(1);}
+void gpio_irq2(void) {handle_interrupt_in(2);}
+void gpio_irq3(void) {handle_interrupt_in(3);}
+void gpio_irq4(void) {handle_interrupt_in(4);}
+void gpio_irq5(void) {handle_interrupt_in(5);}
+void gpio_irq6(void) {handle_interrupt_in(6);}
+void gpio_irq7(void) {handle_interrupt_in(7);}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+    if (pin == NC) return -1;
+
+    irq_handler = handler;
+    
+    int found_free_channel = 0;
+    int i = 0;
+    for (i=0; i<CHANNEL_NUM; i++) {
+        if (channel_ids[i] == 0) {
+            channel_ids[i] = id;
+            obj->ch = i;
+            found_free_channel = 1;
+            break;
+        }
+    }
+    if (!found_free_channel) return -1;
+    
+    /* Enable AHB clock to the GPIO domain. */
+    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
+    
+    /* Enable AHB clock to the FlexInt, GroupedInt domain. */
+    LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
+    
+    /* To select a pin for any of the eight pin interrupts, write the pin number
+     * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
+     * @see: mbed_capi/PinNames.h
+     */
+    LPC_SYSCON->PINSEL[obj->ch] = (pin >> 5) ? (pin - 8) : (pin);
+    
+    // Interrupt Wake-Up Enable
+    LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
+
+    void (*channels_irq)(void) = NULL;
+    switch (obj->ch) {
+        case 0: channels_irq = &gpio_irq0; break;
+        case 1: channels_irq = &gpio_irq1; break;
+        case 2: channels_irq = &gpio_irq2; break;
+        case 3: channels_irq = &gpio_irq3; break;
+        case 4: channels_irq = &gpio_irq4; break;
+        case 5: channels_irq = &gpio_irq5; break;
+        case 6: channels_irq = &gpio_irq6; break;
+        case 7: channels_irq = &gpio_irq7; break;
+    }
+    NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
+    NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+    
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+    channel_ids[obj->ch] = 0;
+    LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+    unsigned int ch_bit = (1 << obj->ch);
+    
+    // Clear interrupt
+    if (!(LPC_GPIO_X->ISEL & ch_bit))
+        LPC_GPIO_X->IST = ch_bit;
+    
+    // Edge trigger
+    LPC_GPIO_X->ISEL &= ~ch_bit;
+    if (event == IRQ_RISE) {
+        if (enable) {
+            LPC_GPIO_X->IENR |= ch_bit;
+        } else {
+            LPC_GPIO_X->IENR &= ~ch_bit;
+        }
+    } else {
+        if (enable) {
+            LPC_GPIO_X->IENF |= ch_bit;
+        } else {
+            LPC_GPIO_X->IENF &= ~ch_bit;
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_object.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName  pin;
+    uint32_t mask;
+
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_set;
+    __IO uint32_t *reg_clr;
+    __I  uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+    if (value)
+        *obj->reg_set = obj->mask;
+    else
+        *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/i2c_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,387 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_I2C_SDA[] = {
+    {P0_5, I2C_0, 1},
+    {NC  , NC   , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+    {P0_4, I2C_0, 1},
+    {NC  , NC,    0}
+};
+
+#define I2C_CONSET(x)       (x->i2c->CONSET)
+#define I2C_CONCLR(x)       (x->i2c->CONCLR)
+#define I2C_STAT(x)         (x->i2c->STAT)
+#define I2C_DAT(x)          (x->i2c->DAT)
+#define I2C_SCLL(x, val)    (x->i2c->SCLL = val)
+#define I2C_SCLH(x, val)    (x->i2c->SCLH = val)
+
+static const uint32_t I2C_addr_offset[2][4] = {
+    {0x0C, 0x20, 0x24, 0x28},
+    {0x30, 0x34, 0x38, 0x3C}
+};
+
+static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+    I2C_CONCLR(obj) = (start << 5)
+                    | (stop << 4)
+                    | (interrupt << 3)
+                    | (acknowledge << 2);
+}
+
+static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+    I2C_CONSET(obj) = (start << 5)
+                    | (stop << 4)
+                    | (interrupt << 3)
+                    | (acknowledge << 2);
+}
+
+// Clear the Serial Interrupt (SI)
+static inline void i2c_clear_SI(i2c_t *obj) {
+    i2c_conclr(obj, 0, 0, 1, 0);
+}
+
+static inline int i2c_status(i2c_t *obj) {
+    return I2C_STAT(obj);
+}
+
+// Wait until the Serial Interrupt (SI) is set
+static int i2c_wait_SI(i2c_t *obj) {
+    int timeout = 0;
+    while (!(I2C_CONSET(obj) & (1 << 3))) {
+        timeout++;
+        if (timeout > 100000) return -1;
+    }
+    return 0;
+}
+
+static inline void i2c_interface_enable(i2c_t *obj) {
+    I2C_CONSET(obj) = 0x40;
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+    LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5);
+    LPC_SYSCON->PRESETCTRL |= 1 << 1;
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+    // determine the SPI to use
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+    obj->i2c = (LPC_I2C_Type *)pinmap_merge(i2c_sda, i2c_scl);
+    
+    if ((int)obj->i2c == NC) {
+        error("I2C pin mapping failed");
+    }
+    
+    // enable power
+    i2c_power_enable(obj);
+    
+    // set default frequency at 100k
+    i2c_frequency(obj, 100000);
+    i2c_conclr(obj, 1, 1, 1, 1);
+    i2c_interface_enable(obj);
+    
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+}
+
+inline int i2c_start(i2c_t *obj) {
+    int status = 0;
+    // 8.1 Before master mode can be entered, I2CON must be initialised to:
+    //  - I2EN STA STO SI AA - -
+    //  -  1    0   0   0  x - -
+    // if AA = 0, it can't enter slave mode
+    i2c_conclr(obj, 1, 1, 1, 1);
+    
+    // The master mode may now be entered by setting the STA bit
+    // this will generate a start condition when the bus becomes free
+    i2c_conset(obj, 1, 0, 0, 1);
+    
+    i2c_wait_SI(obj);
+    status = i2c_status(obj);
+    
+    // Clear start bit now transmitted, and interrupt bit
+    i2c_conclr(obj, 1, 0, 0, 0);
+    return status;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+    int timeout = 0;
+
+    // write the stop bit
+    i2c_conset(obj, 0, 1, 0, 0);
+    i2c_clear_SI(obj);
+    
+    // wait for STO bit to reset
+    while(I2C_CONSET(obj) & (1 << 4)) {
+        timeout ++;
+        if (timeout > 100000) return 1;
+    }
+
+    return 0;
+}
+
+
+static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
+    // write the data
+    I2C_DAT(obj) = value;
+    
+    // clear SI to init a send
+    i2c_clear_SI(obj);
+    
+    // wait and return status
+    i2c_wait_SI(obj);
+    return i2c_status(obj);
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+    // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
+    if (last) {
+        i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
+    } else {
+        i2c_conset(obj, 0, 0, 0, 1); // send a ACK
+    }
+    
+    // accept byte
+    i2c_clear_SI(obj);
+    
+    // wait for it to arrive
+    i2c_wait_SI(obj);
+    
+    // return the data
+    return (I2C_DAT(obj) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+    // No peripheral clock divider on the M0
+    uint32_t PCLK = SystemCoreClock;
+    
+    uint32_t pulse = PCLK / (hz * 2);
+    
+    // I2C Rate
+    I2C_SCLL(obj, pulse);
+    I2C_SCLH(obj, pulse);
+}
+
+// The I2C does a read or a write as a whole operation
+// There are two types of error conditions it can encounter
+//  1) it can not obtain the bus
+//  2) it gets error responses at part of the transmission
+//
+// We tackle them as follows:
+//  1) we retry until we get the bus. we could have a "timeout" if we can not get it
+//      which basically turns it in to a 2)
+//  2) on error, we use the standard error mechanisms to report/debug
+//
+// Therefore an I2C transaction should always complete. If it doesn't it is usually
+// because something is setup wrong (e.g. wiring), and we don't need to programatically
+// check for that
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+    int count, status;
+    
+    status = i2c_start(obj);
+    
+    if ((status != 0x10) && (status != 0x08)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+    
+    status = i2c_do_write(obj, (address | 0x01), 1);
+    if (status != 0x40) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    // Read in all except last byte
+    for (count = 0; count < (length - 1); count++) {
+        int value = i2c_do_read(obj, 0);
+        status = i2c_status(obj);
+        if (status != 0x50) {
+            i2c_stop(obj);
+            return count;
+        }
+        data[count] = (char) value;
+    }
+
+    // read in last byte
+    int value = i2c_do_read(obj, 1);
+    status = i2c_status(obj);
+    if (status != 0x58) {
+        i2c_stop(obj);
+        return length - 1;
+    }
+    
+    data[count] = (char) value;
+    
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+    
+    return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+    int i, status;
+    
+    status = i2c_start(obj);
+    
+    if ((status != 0x10) && (status != 0x08)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+    
+    status = i2c_do_write(obj, (address & 0xFE), 1);
+    if (status != 0x18) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    
+    for (i=0; i<length; i++) {
+        status = i2c_do_write(obj, data[i], 0);
+        if(status != 0x28) {
+            i2c_stop(obj);
+            return i;
+        }
+    }
+    
+    // clearing the serial interrupt here might cause an unintended rewrite of the last byte
+    // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
+    // i2c_clear_SI(obj);
+    
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+    
+    return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+    i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+    return (i2c_do_read(obj, last) & 0xFF);
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+    int ack;
+    int status = i2c_do_write(obj, (data & 0xFF), 0);
+    
+    switch(status) {
+        case 0x18: case 0x28:       // Master transmit ACKs
+            ack = 1;
+            break;
+        case 0x40:                  // Master receive address transmitted ACK
+            ack = 1;
+            break;
+        case 0xB8:                  // Slave transmit ACK
+            ack = 1;
+            break;
+        default:
+            ack = 0;
+            break;
+    }
+
+    return ack;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+    if (enable_slave != 0) {
+        i2c_conclr(obj, 1, 1, 1, 0);
+        i2c_conset(obj, 0, 0, 0, 1);
+    } else {
+        i2c_conclr(obj, 1, 1, 1, 1);
+    }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+    int status;
+    int retval;
+    
+    status = i2c_status(obj);
+    switch(status) {
+        case 0x60: retval = 3; break;
+        case 0x70: retval = 2; break;
+        case 0xA8: retval = 1; break;
+        default  : retval = 0; break;
+    }
+    
+    return(retval);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+    int count = 0;
+    int status;
+    
+    do {
+        i2c_clear_SI(obj);
+        i2c_wait_SI(obj);
+        status = i2c_status(obj);
+        if((status == 0x80) || (status == 0x90)) {
+            data[count] = I2C_DAT(obj) & 0xFF;
+        }
+        count++;
+    } while (((status == 0x80) || (status == 0x90) ||
+            (status == 0x060) || (status == 0x70)) && (count < length));
+    
+    if(status != 0xA0) {
+        i2c_stop(obj);
+    }
+    
+    i2c_clear_SI(obj);
+    
+    return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+    int count = 0;
+    int status;
+    
+    if(length <= 0) {
+        return(0);
+    }
+    
+    do {
+        status = i2c_do_write(obj, data[count], 0);
+        count++;
+    } while ((count < length) && (status == 0xB8));
+    
+    if((status != 0xC0) && (status != 0xC8)) {
+        i2c_stop(obj);
+    }
+    
+    i2c_clear_SI(obj);
+    
+    return(count);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+    uint32_t addr;
+    
+    if ((idx >= 0) && (idx <= 3)) {
+        addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
+        *((uint32_t *) addr) = address & 0xFF;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/objects.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,70 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    uint32_t ch;
+};
+
+struct port_s {
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_mpin;
+    PortName port;
+    uint32_t mask;
+};
+
+
+struct pwmout_s {
+    PWMName pwm;
+};
+
+
+struct serial_s {
+    LPC_USART_Type *uart;
+    int index;
+};
+
+struct analogin_s {
+    ADCName adc;
+};
+
+
+struct i2c_s {
+    LPC_I2C_Type *i2c;
+};
+
+
+struct spi_s {
+    LPC_SSPx_Type *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/pinmap.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "error.h"
+
+#define LPC_IOCON0_BASE (LPC_IOCON_BASE)
+#define LPC_IOCON1_BASE (LPC_IOCON_BASE + 0x60)
+
+void pin_function(PinName pin, int function) {
+    if (pin == (uint32_t)NC) return;
+    
+    uint32_t pin_number = (uint32_t)pin;
+    
+    __IO uint32_t *reg = (pin_number < 32) ?
+            (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
+            (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
+    
+    // pin function bits: [2:0] -> 111 = (0x7)
+    *reg = (*reg & ~0x7) | (function & 0x7);
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+    if (pin == (uint32_t)NC) { return; }
+    
+    uint32_t pin_number = (uint32_t)pin;
+    uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2;
+    
+    __IO uint32_t *reg = (pin_number < 32) ?
+            (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
+            (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
+    uint32_t tmp = *reg;
+    
+    // pin mode bits: [4:3] -> 11000 = (0x3 << 3)
+    tmp &= ~(0x3 << 3);
+    tmp |= (mode & 0x3) << 3;
+    
+    // drain
+    tmp &= ~(0x1 << 10);
+    tmp |= drain << 10;
+    
+    *reg = tmp;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/port_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+
+PinName port_pin(PortName port, int pin_n) {
+    return (PinName)((port << PORT_SHIFT) | pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+    obj->port = port;
+    obj->mask = mask;
+    
+    LPC_GPIO->MASK[port] = ~mask;
+    
+    obj->reg_mpin = &LPC_GPIO->MPIN[port];
+    obj->reg_dir = &LPC_GPIO->DIR[port];
+    
+    uint32_t i;
+    // The function is set per pin: reuse gpio logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            gpio_set(port_pin(obj->port, i));
+        }
+    }
+    
+    port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+    uint32_t i;
+    // The mode is set per pin: reuse pinmap logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+    switch (dir) {
+        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
+    }
+}
+
+void port_write(port_t *obj, int value) {
+    *obj->reg_mpin = value;
+}
+
+int port_read(port_t *obj) {
+    return (*obj->reg_mpin);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/pwmout_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,185 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#define TCR_CNT_EN       0x00000001
+#define TCR_RESET        0x00000002
+
+/* To have a PWM where we can change both the period and the duty cycle,
+ * we need an entire timer. With the following conventions:
+ *   * MR3 is used for the PWM period
+ *   * MR0, MR1, MR2 are used for the duty cycle
+ */
+static const PinMap PinMap_PWM[] = {
+    /* CT16B0 */
+    {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2},    /* MR0 */
+    {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2},   /* MR1 */
+    {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2},   /* MR2 */
+
+    /* CT16B1 */
+    {P0_21, PWM_4, 1},                      /* MR0 */
+    {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1},   /* MR1 */
+
+    /* CT32B0 */
+    {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1},   /* MR0 */
+    {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1},   /* MR1 */
+    {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1},   /* MR2 */
+
+    /* CT32B1 */
+    {P0_13, PWM_9 , 3}, //{P1_0, PWM_9 , 1},  /* MR0 */
+    {P0_14, PWM_10, 3}, //{P1_1, PWM_10, 1},  /* MR1 */
+    {P0_15, PWM_11, 3}, //{P1_2, PWM_11, 1},  /* MR2 */
+
+    {NC, NC, 0}
+};
+
+typedef struct {
+    uint8_t timer;
+    uint8_t mr;
+} timer_mr;
+
+static timer_mr pwm_timer_map[11] = {
+    {0, 0}, {0, 1}, {0, 2},
+    {1, 0}, {1, 1},
+    {2, 0}, {2, 1}, {2, 2},
+    {3, 0}, {3, 1}, {3, 2},
+};
+
+static LPC_CTxxBx_Type *Timers[4] = {
+    LPC_CT16B0, LPC_CT16B1,
+    LPC_CT32B0, LPC_CT32B1
+};
+
+static unsigned int pwm_clock_mhz;
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+    // determine the channel
+    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+    if (pwm == (uint32_t)NC)
+        error("PwmOut pin mapping failed");
+    
+    obj->pwm = pwm;
+    
+    // Timer registers
+    timer_mr tid = pwm_timer_map[pwm];
+    LPC_CTxxBx_Type *timer = Timers[tid.timer];
+    
+    // Disable timer
+    timer->TCR = 0;
+    
+    // Power the correspondent timer
+    LPC_SYSCON->SYSAHBCLKCTRL |= 1 << (tid.timer + 7);
+    
+    /* Enable PWM function */
+    timer->PWMC = (1 << 3)|(1 << 2)|(1 << 1)|(1 << 0);
+    
+    /* Reset Functionality on MR3 controlling the PWM period */
+    timer->MCR = 1 << 10;
+    
+    pwm_clock_mhz = SystemCoreClock / 1000000;
+    
+    // default to 20ms: standard for servos, and fine for e.g. brightness control
+    pwmout_period_ms(obj, 20);
+    pwmout_write    (obj, 0);
+    
+    // Wire pinout
+    pinmap_pinout(pin, PinMap_PWM);
+}
+
+void pwmout_free(pwmout_t* obj) {
+    // [TODO]
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+    if (value < 0.0f) {
+        value = 0.0;
+    } else if (value > 1.0f) {
+        value = 1.0;
+    }
+    
+    timer_mr tid = pwm_timer_map[obj->pwm];
+    LPC_CTxxBx_Type *timer = Timers[tid.timer];
+    uint32_t t_off = timer->MR3 - (uint32_t)((float)(timer->MR3) * value);
+    
+    timer->TCR = TCR_RESET;
+    timer->MR[tid.mr] = t_off;
+    timer->TCR = TCR_CNT_EN;
+}
+
+float pwmout_read(pwmout_t* obj) {
+    timer_mr tid = pwm_timer_map[obj->pwm];
+    LPC_CTxxBx_Type *timer = Timers[tid.timer];
+    
+    float v = (float)(timer->MR3 - timer->MR[tid.mr]) / (float)(timer->MR3);
+    return (v > 1.0f) ? (1.0f) : (v);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+    pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+    pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+    int i = 0;
+    uint32_t period_ticks = pwm_clock_mhz * us;
+    
+    timer_mr tid = pwm_timer_map[obj->pwm];
+    LPC_CTxxBx_Type *timer = Timers[tid.timer];
+    uint32_t old_period_ticks = timer->MR3;
+    
+    timer->TCR = TCR_RESET;
+    timer->MR3 = period_ticks;
+    
+    // Scale the pulse width to preserve the duty ratio
+    if (old_period_ticks > 0) {
+        for (i=0; i<3; i++) {
+            uint32_t t_off = period_ticks - (uint32_t)(((uint64_t)timer->MR[i] * (uint64_t)period_ticks) / (uint64_t)old_period_ticks);
+            timer->MR[i] = t_off;
+        }
+    }
+    timer->TCR = TCR_CNT_EN;
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+    uint32_t t_on = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000);
+    timer_mr tid = pwm_timer_map[obj->pwm];
+    LPC_CTxxBx_Type *timer = Timers[tid.timer];
+    
+    timer->TCR = TCR_RESET;
+    if (t_on > timer->MR3) {
+        pwmout_period_us(obj, us);
+    }
+    uint32_t t_off = timer->MR3 - t_on;
+    timer->MR[tid.mr] = t_off;
+    timer->TCR = TCR_CNT_EN;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/serial_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,282 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include <string.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+#define UART_NUM    1
+
+static const PinMap PinMap_UART_TX[] = {
+    {P0_19, UART_0, 1},
+    {P1_13, UART_0, 3},
+    {P1_27, UART_0, 2},
+    { NC  , NC    , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+    {P0_18, UART_0, 1},
+    {P1_14, UART_0, 3},
+    {P1_26, UART_0, 2},
+    {NC   , NC    , 0}
+};
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+    int is_stdio_uart = 0;
+    
+    // determine the UART to use
+    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+    UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    if ((int)uart == NC) {
+        error("Serial pinout mapping failed");
+    }
+    
+    obj->uart = (LPC_USART_Type *)uart;
+    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
+    
+    // [TODO] Consider more elegant approach
+    // disconnect USBTX/RX mapping mux, for case when switching ports
+    //pin_function(USBTX, 0);
+    //pin_function(USBRX, 0);
+    
+    // enable fifos and default rx trigger level
+    obj->uart->FCR = 1 << 0  // FIFO Enable - 0 = Disables, 1 = Enabled
+                   | 0 << 1  // Rx Fifo Reset
+                   | 0 << 2  // Tx Fifo Reset
+                   | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
+    
+    // disable irqs
+    obj->uart->IER = 0 << 0  // Rx Data available irq enable
+                   | 0 << 1  // Tx Fifo empty irq enable
+                   | 0 << 2; // Rx Line Status irq enable
+    
+    // set default baud rate and format
+    serial_baud  (obj, 9600);
+    serial_format(obj, 8, ParityNone, 1);
+    
+    // pinout the chosen uart
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+    
+    // set rx/tx pins in PullUp mode
+    pin_mode(tx, PullUp);
+    pin_mode(rx, PullUp);
+    
+    switch (uart) {
+        case UART_0: obj->index = 0; break;
+    }
+    
+    is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+    
+    if (is_stdio_uart) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj) {
+    serial_irq_ids[obj->index] = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+    LPC_SYSCON->UARTCLKDIV = 0x1;
+    uint32_t PCLK = SystemCoreClock;
+    // First we check to see if the basic divide with no DivAddVal/MulVal
+    // ratio gives us an integer result. If it does, we set DivAddVal = 0,
+    // MulVal = 1. Otherwise, we search the valid ratio value range to find
+    // the closest match. This could be more elegant, using search methods
+    // and/or lookup tables, but the brute force method is not that much
+    // slower, and is more maintainable.
+    uint16_t DL = PCLK / (16 * baudrate);
+    
+    uint8_t DivAddVal = 0;
+    uint8_t MulVal = 1;
+    int hit = 0;
+    uint16_t dlv;
+    uint8_t mv, dav;
+    if ((PCLK % (16 * baudrate)) != 0) {     // Checking for zero remainder
+        float err_best = (float) baudrate;
+        uint16_t dlmax = DL;
+        for ( dlv = (dlmax/2); (dlv <= dlmax) && !hit; dlv++) {
+            for ( mv = 1; mv <= 15; mv++) {
+                for ( dav = 1; dav < mv; dav++) {
+                    float ratio = 1.0f + ((float) dav / (float) mv);
+                    float calcbaud = (float)PCLK / (16.0f * (float) dlv * ratio);
+                    float err = fabs(((float) baudrate - calcbaud) / (float) baudrate);
+                    if (err < err_best) {
+                        DL = dlv;
+                        DivAddVal = dav;
+                        MulVal = mv;
+                        err_best = err;
+                        if (err < 0.001f) {
+                            hit = 1;
+                        }
+                    }
+                }
+            }
+        }
+    }
+    
+    // set LCR[DLAB] to enable writing to divider registers
+    obj->uart->LCR |= (1 << 7);
+    
+    // set divider values
+    obj->uart->DLM = (DL >> 8) & 0xFF;
+    obj->uart->DLL = (DL >> 0) & 0xFF;
+    obj->uart->FDR = (uint32_t) DivAddVal << 0
+                   | (uint32_t) MulVal    << 4;
+    
+    // clear LCR[DLAB]
+    obj->uart->LCR &= ~(1 << 7);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+    // 0: 1 stop bits, 1: 2 stop bits
+    if (stop_bits != 1 && stop_bits != 2) {
+        error("Invalid stop bits specified");
+    }
+    stop_bits -= 1;
+    
+    // 0: 5 data bits ... 3: 8 data bits
+    if (data_bits < 5 || data_bits > 8) {
+        error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
+    }
+    data_bits -= 5;
+
+    int parity_enable, parity_select;
+    switch (parity) {
+        case ParityNone: parity_enable = 0; parity_select = 0; break;
+        case ParityOdd : parity_enable = 1; parity_select = 0; break;
+        case ParityEven: parity_enable = 1; parity_select = 1; break;
+        case ParityForced1: parity_enable = 1; parity_select = 2; break;
+        case ParityForced0: parity_enable = 1; parity_select = 3; break;
+        default:
+            error("Invalid serial parity setting");
+            return;
+    }
+    
+    obj->uart->LCR = data_bits            << 0
+                   | stop_bits            << 2
+                   | parity_enable        << 3
+                   | parity_select        << 4;
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t iir, uint32_t index) {
+    // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
+    SerialIrq irq_type;
+    switch (iir) {
+        case 1: irq_type = TxIrq; break;
+        case 2: irq_type = RxIrq; break;
+        default: return;
+    }
+    
+    if (serial_irq_ids[index] != 0)
+        irq_handler(serial_irq_ids[index], irq_type);
+}
+
+void uart0_irq() {uart_irq((LPC_USART->IIR >> 1) & 0x7, 0);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;
+    switch ((int)obj->uart) {
+        case UART_0: irq_n=USART_IRQn ; vector = (uint32_t)&uart0_irq; break;
+    }
+    
+    if (enable) {
+        obj->uart->IER |= 1 << irq;
+        NVIC_SetVector(irq_n, vector);
+        NVIC_EnableIRQ(irq_n);
+    } else { // disable
+        int all_disabled = 0;
+        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+
+        obj->uart->IER &= ~(1 << irq);
+        all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
+        
+        if (all_disabled)
+            NVIC_DisableIRQ(irq_n);
+    }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+    while (!serial_readable(obj));
+    return obj->uart->RBR;
+}
+
+void serial_putc(serial_t *obj, int c) {
+    while (!serial_writable(obj));
+    obj->uart->THR = c;
+    
+    uint32_t lsr = obj->uart->LSR;
+    lsr = lsr;
+    uint32_t thr = obj->uart->THR;
+    thr = thr;
+}
+
+int serial_readable(serial_t *obj) {
+    return obj->uart->LSR & 0x01;
+}
+
+int serial_writable(serial_t *obj) {
+    return obj->uart->LSR & 0x20;
+}
+
+void serial_clear(serial_t *obj) {
+    obj->uart->FCR = 1 << 1  // rx FIFO reset
+                   | 1 << 2  // tx FIFO reset
+                   | 0 << 6; // interrupt depth
+}
+
+void serial_pinout_tx(PinName tx) {
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+    obj->uart->LCR |= (1 << 6);
+}
+
+void serial_break_clear(serial_t *obj) {
+    obj->uart->LCR &= ~(1 << 6);
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/sleep.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+
+void sleep(void) {
+    // ensure debug is disconnected
+    mbed_interface_disconnect();
+    
+    // PCON[PD] set to sleep
+    LPC_PMU->PCON = 0x0;
+    
+    // SRC[SLEEPDEEP] set to 0 = sleep
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    
+    // wait for interrupt
+    __WFI();
+}
+
+/*
+* The mbed lpc1768 does not support the deepsleep mode
+* as a debugger is connected to it (the mbed interface).
+*
+* As mentionned in an application note from NXP:
+*
+*       http://www.po-star.com/public/uploads/20120319123122_141.pdf
+*
+*       {{{
+*       The user should be aware of certain limitations during debugging.
+*       The most important is that, due to limitations of the Cortex-M3
+*       integration, the LPC17xx cannot wake up in the usual manner from
+*       Deep Sleep and Power-down modes. It is recommended not to use these
+*       modes during debug. Once an application is downloaded via JTAG/SWD
+*       interface, the USB to SWD/JTAG debug adapter (Keil ULINK2 for example)
+*       should be removed from the target board, and thereafter, power cycle
+*       the LPC17xx to allow wake-up from deep sleep and power-down modes
+*       }}}
+*
+*       As the interface firmware does not reset the target when a
+*       mbed_interface_disconnect() semihosting call is made, the
+*       core cannot wake-up from deepsleep.
+*
+*       We treat a deepsleep() as a normal sleep().
+*/
+
+void deepsleep(void) {
+    // ensure debug is disconnected
+    mbed_interface_disconnect();
+    
+    // PCON[PD] set to deepsleep
+    LPC_PMU->PCON = 0x1;
+    
+    // SRC[SLEEPDEEP] set to 1 = deep sleep
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+    
+    // Power up everything after powerdown
+    LPC_SYSCON->PDAWAKECFG &= 0xFFFFF800;
+    
+    // wait for interrupt
+    __WFI();
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/spi_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,218 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_SPI_SCLK[] = {
+    {P0_6 , SPI_0, 0x02},
+    {P0_10, SPI_0, 0x02},
+    {P1_29, SPI_0, 0x01},
+    {P1_15, SPI_1, 0x03},
+    {P1_20, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+    {P0_9 , SPI_0, 0x01},
+    {P0_21, SPI_1, 0x02},
+    {P1_22, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+    {P0_8 , SPI_0, 0x01},
+    {P0_22, SPI_1, 0x03},
+    {P1_21, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+    {P0_2 , SPI_0, 0x01},
+    {P1_19, SPI_1, 0x02},
+    {P1_23, SPI_1, 0x02},
+    {NC   , NC   , 0}
+};
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    // determine the SPI to use
+    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+    
+    obj->spi = (LPC_SSPx_Type*)pinmap_merge(spi_data, spi_cntl);
+    
+    if ((int)obj->spi == NC) {
+        error("SPI pinout mapping failed");
+    }
+    
+    // enable power and clocking
+    switch ((int)obj->spi) {
+        case SPI_0:
+            LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
+            LPC_SYSCON->SSP0CLKDIV = 0x01;
+            LPC_SYSCON->PRESETCTRL |= 1 << 0;
+            break;
+        case SPI_1:
+            LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
+            LPC_SYSCON->SSP1CLKDIV = 0x01;
+            LPC_SYSCON->PRESETCTRL |= 1 << 2;
+            break;
+    }
+    
+    // set default format and frequency
+    if (ssel == NC) {
+        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
+    } else {
+        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
+    }
+    spi_frequency(obj, 1000000);
+    
+    // enable the ssp channel
+    ssp_enable(obj);
+    
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+    ssp_disable(obj);
+    
+    if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
+        error("SPI format error");
+    }
+    
+    int polarity = (mode & 0x2) ? 1 : 0;
+    int phase = (mode & 0x1) ? 1 : 0;
+    
+    // set it up
+    int DSS = bits - 1;            // DSS (data select size)
+    int SPO = (polarity) ? 1 : 0;  // SPO - clock out polarity
+    int SPH = (phase) ? 1 : 0;     // SPH - clock out phase
+    
+    int FRF = 0;                   // FRF (frame format) = SPI
+    uint32_t tmp = obj->spi->CR0;
+    tmp &= ~(0xFFFF);
+    tmp |= DSS << 0
+        | FRF << 4
+        | SPO << 6
+        | SPH << 7;
+    obj->spi->CR0 = tmp;
+    
+    tmp = obj->spi->CR1;
+    tmp &= ~(0xD);
+    tmp |= 0 << 0                   // LBM - loop back mode - off
+        | ((slave) ? 1 : 0) << 2   // MS - master slave mode, 1 = slave
+        | 0 << 3;                  // SOD - slave output disable - na
+    obj->spi->CR1 = tmp;
+    
+    ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+    ssp_disable(obj);
+    
+    uint32_t PCLK = SystemCoreClock;
+    
+    int prescaler;
+    
+    for (prescaler = 2; prescaler <= 254; prescaler += 2) {
+        int prescale_hz = PCLK / prescaler;
+        
+        // calculate the divider
+        int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
+        
+        // check we can support the divider
+        if (divider < 256) {
+            // prescaler
+            obj->spi->CPSR = prescaler;
+            
+            // divider
+            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 |= (divider - 1) << 8;
+            ssp_enable(obj);
+            return;
+        }
+    }
+    error("Couldn't setup requested SPI frequency");
+}
+
+static inline int ssp_disable(spi_t *obj) {
+    return obj->spi->CR1 &= ~(1 << 1);
+}
+
+static inline int ssp_enable(spi_t *obj) {
+    return obj->spi->CR1 |= (1 << 1);
+}
+
+static inline int ssp_readable(spi_t *obj) {
+    return obj->spi->SR & (1 << 2);
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+    return obj->spi->SR & (1 << 1);
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+    while (!ssp_writeable(obj));
+    obj->spi->DR = value;
+}
+
+static inline int ssp_read(spi_t *obj) {
+    while (!ssp_readable(obj));
+    return obj->spi->DR;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+    return (obj->spi->SR & (1 << 4)) ? (1) : (0);
+}
+
+int spi_master_write(spi_t *obj, int value) {
+    ssp_write(obj, value);
+    return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+    return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+};
+
+int spi_slave_read(spi_t *obj) {
+    return obj->spi->DR;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+    while (ssp_writeable(obj) == 0) ;
+    obj->spi->DR = value;
+}
+
+int spi_busy(spi_t *obj) {
+    return ssp_busy(obj);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC13XX/us_ticker.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+#define US_TICKER_TIMER          ((LPC_CT32B1_Type *)LPC_CT32B1_BASE)
+#define US_TICKER_TIMER_IRQn     CT32B1_IRQn
+
+int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+    if (us_ticker_inited) return;
+    us_ticker_inited = 1;
+    
+    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10); // Clock TIMER_1
+    uint32_t PCLK = SystemCoreClock;
+    
+    US_TICKER_TIMER->TCR = 0x2;  // reset
+    
+    uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks)
+    US_TICKER_TIMER->PR = prescale - 1;
+    US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0
+    
+    NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+uint32_t us_ticker_read() {
+    if (!us_ticker_inited)
+        us_ticker_init();
+    
+    return US_TICKER_TIMER->TC;
+}
+
+void us_ticker_set_interrupt(unsigned int timestamp) {
+    // set match value
+    US_TICKER_TIMER->MR0 = timestamp;
+    // enable match interrupt
+    US_TICKER_TIMER->MCR |= 1;
+}
+
+void us_ticker_disable_interrupt(void) {
+    US_TICKER_TIMER->MCR &= ~1;
+}
+
+void us_ticker_clear_interrupt(void) {
+    US_TICKER_TIMER->IR = 1;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/PeripheralNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    UART_0 = (int)LPC_UART0_BASE,
+    UART_1 = (int)LPC_UART1_BASE,
+    UART_2 = (int)LPC_UART2_BASE,
+    UART_3 = (int)LPC_UART3_BASE
+} UARTName;
+
+typedef enum {
+    ADC0_0 = 0,
+    ADC0_1,
+    ADC0_2,
+    ADC0_3,
+    ADC0_4,
+    ADC0_5,
+    ADC0_6,
+    ADC0_7
+} ADCName;
+
+typedef enum {
+    DAC_0 = 0
+} DACName;
+
+typedef enum {
+    SPI_0 = (int)LPC_SSP0_BASE,
+    SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+    I2C_0 = (int)LPC_I2C0_BASE,
+    I2C_1 = (int)LPC_I2C1_BASE,
+    I2C_2 = (int)LPC_I2C2_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1 = 1,
+    PWM_2,
+    PWM_3,
+    PWM_4,
+    PWM_5,
+    PWM_6
+} PWMName;
+
+typedef enum {
+     CAN_1 = (int)LPC_CAN1_BASE,
+     CAN_2 = (int)LPC_CAN2_BASE
+} CANName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/PinNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,109 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  5
+
+typedef enum {
+    // LPC Pin Names
+    P0_0 = LPC_GPIO0_BASE,
+          P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
+    P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
+    P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
+    P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
+    P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
+
+    // mbed DIP Pin Names
+    p5 = P0_9,
+    p6 = P0_8,
+    p7 = P0_7,
+    p8 = P0_6,
+    p9 = P0_0,
+    p10 = P0_1,
+    p11 = P0_18,
+    p12 = P0_17,
+    p13 = P0_15,
+    p14 = P0_16,
+    p15 = P0_23,
+    p16 = P0_24,
+    p17 = P0_25,
+    p18 = P0_26,
+    p19 = P1_30,
+    p20 = P1_31,
+    p21 = P2_5,
+    p22 = P2_4,
+    p23 = P2_3,
+    p24 = P2_2,
+    p25 = P2_1,
+    p26 = P2_0,
+    p27 = P0_11,
+    p28 = P0_10,
+    p29 = P0_5,
+    p30 = P0_4,
+
+    // Other mbed Pin Names
+#ifdef MCB1700
+    LED1 = P1_28,
+    LED2 = P1_29,
+    LED3 = P1_31,
+    LED4 = P2_2,
+#else
+    LED1 = P1_18,
+    LED2 = P1_20,
+    LED3 = P1_21,
+    LED4 = P1_23,
+#endif
+    USBTX = P0_2,
+    USBRX = P0_3,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullUp = 0,
+    PullDown = 3,
+    PullNone = 2,
+    OpenDrain = 4
+} PinMode;
+
+// version of PINCON_TypeDef using register arrays
+typedef struct {
+  __IO uint32_t PINSEL[11];
+       uint32_t RESERVED0[5];
+  __IO uint32_t PINMODE[10];
+  __IO uint32_t PINMODE_OD[5];
+} PINCONARRAY_TypeDef;
+
+#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/PortNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,34 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0,
+    Port1 = 1,
+    Port2 = 2,
+    Port3 = 3,
+    Port4 = 4
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/analogin_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogin_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#define ANALOGIN_MEDIAN_FILTER      1
+
+#define ADC_10BIT_RANGE             0x3FF
+#define ADC_12BIT_RANGE             0xFFF
+
+static inline int div_round_up(int x, int y) {
+  return (x + (y - 1)) / y;
+}
+
+static const PinMap PinMap_ADC[] = {
+    {P0_23, ADC0_0, 1},
+    {P0_24, ADC0_1, 1},
+    {P0_25, ADC0_2, 1},
+    {P0_26, ADC0_3, 1},
+    {P1_30, ADC0_4, 3},
+    {P1_31, ADC0_5, 3},
+    {P0_2,  ADC0_7, 2},
+    {P0_3,  ADC0_6, 2},
+    {NC,    NC,     0}
+};
+
+#define ADC_RANGE    ADC_12BIT_RANGE
+
+void analogin_init(analogin_t *obj, PinName pin) {
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    if (obj->adc == (uint32_t)NC) {
+        error("ADC pin mapping failed");
+    }
+    
+    // ensure power is turned on
+    LPC_SC->PCONP |= (1 << 12);
+    
+    // set PCLK of ADC to /1
+    LPC_SC->PCLKSEL0 &= ~(0x3 << 24);
+    LPC_SC->PCLKSEL0 |= (0x1 << 24);
+    uint32_t PCLK = SystemCoreClock;
+    
+    // calculate minimum clock divider
+    //  clkdiv = divider - 1
+    uint32_t MAX_ADC_CLK = 13000000;
+    uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
+    
+    // Set the generic software-controlled ADC settings
+    LPC_ADC->ADCR = (0 << 0)      // SEL: 0 = no channels selected
+                  | (clkdiv << 8) // CLKDIV: PCLK max ~= 25MHz, /25 to give safe 1MHz at fastest
+                  | (0 << 16)     // BURST: 0 = software control
+                  | (0 << 17)     // CLKS: not applicable
+                  | (1 << 21)     // PDN: 1 = operational
+                  | (0 << 24)     // START: 0 = no start
+                  | (0 << 27);    // EDGE: not applicable
+    
+    pinmap_pinout(pin, PinMap_ADC);
+}
+
+static inline uint32_t adc_read(analogin_t *obj) {
+    // Select the appropriate channel and start conversion
+    LPC_ADC->ADCR &= ~0xFF;
+    LPC_ADC->ADCR |= 1 << (int)obj->adc;
+    LPC_ADC->ADCR |= 1 << 24;
+    
+    // Repeatedly get the sample data until DONE bit
+    unsigned int data;
+    do {
+        data = LPC_ADC->ADGDR;
+    } while ((data & ((unsigned int)1 << 31)) == 0);
+    
+    // Stop conversion
+    LPC_ADC->ADCR &= ~(1 << 24);
+    
+    return (data >> 4) & ADC_RANGE; // 12 bit
+}
+
+static inline void order(uint32_t *a, uint32_t *b) {
+    if (*a > *b) {
+        uint32_t t = *a;
+        *a = *b;
+        *b = t;
+    }
+}
+
+static inline uint32_t adc_read_u32(analogin_t *obj) {
+    uint32_t value;
+#if ANALOGIN_MEDIAN_FILTER
+    uint32_t v1 = adc_read(obj);
+    uint32_t v2 = adc_read(obj);
+    uint32_t v3 = adc_read(obj);
+    order(&v1, &v2);
+    order(&v2, &v3);
+    order(&v1, &v2);
+    value = v2;
+#else
+    value = adc_read(obj);
+#endif
+    return value;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+    
+    return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
+}
+
+float analogin_read(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+    return (float)value * (1.0f / (float)ADC_RANGE);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/analogout_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogout_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_DAC[] = {
+    {P0_26, DAC_0, 2},
+    {NC   , NC   , 0}
+};
+
+void analogout_init(dac_t *obj, PinName pin) {
+    obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
+    if (obj->dac == (uint32_t)NC) {
+        error("DAC pin mapping failed");
+    }
+    
+    // power is on by default, set DAC clk divider is /4
+    LPC_SC->PCLKSEL0 &= ~(0x3 << 22);
+    
+    // map out (must be done before accessing registers)
+    pinmap_pinout(pin, PinMap_DAC);
+    
+    analogout_write_u16(obj, 0);
+}
+
+void analogout_free(dac_t *obj) {}
+
+static inline void dac_write(int value) {
+    value &= 0x3FF; // 10-bit
+    
+    // Set the DAC output
+    LPC_DAC->DACR = (0 << 16)       // bias = 0
+                  | (value << 6);
+}
+
+static inline int dac_read() {
+    return (LPC_DAC->DACR >> 6) & 0x3FF;
+}
+
+void analogout_write(dac_t *obj, float value) {
+    if (value < 0.0f) {
+        dac_write(0);
+    } else if (value > 1.0f) {
+        dac_write(0x3FF);
+    } else {
+        dac_write(value * (float)0x3FF);
+    }
+}
+
+void analogout_write_u16(dac_t *obj, uint16_t value) {
+    dac_write(value >> 6); // 10-bit
+}
+
+float analogout_read(dac_t *obj) {
+    uint32_t value = dac_read();
+    return (float)value * (1.0f / (float)0x3FF);
+}
+
+uint16_t analogout_read_u16(dac_t *obj) {
+    uint32_t value = dac_read(); // 10-bit
+    return (value << 6) | ((value >> 4) & 0x003F);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/can_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,300 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "can_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#include <math.h>
+#include <string.h>
+
+/* Acceptance filter mode in AFMR register */
+#define ACCF_OFF                0x01
+#define ACCF_BYPASS             0x02
+#define ACCF_ON                 0x00
+#define ACCF_FULLCAN            0x04
+
+/* There are several bit timing calculators on the internet.
+http://www.port.de/engl/canprod/sv_req_form.html
+http://www.kvaser.com/can/index.htm
+*/
+
+static const PinMap PinMap_CAN_RD[] = {
+    {P0_0 , CAN_1, 1},
+    {P0_4 , CAN_2, 2},
+    {P0_21, CAN_1, 3},
+    {P2_7 , CAN_2, 1},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_CAN_TD[] = {
+    {P0_1 , CAN_1, 1},
+    {P0_5 , CAN_2, 2},
+    {P0_22, CAN_1, 3},
+    {P2_8 , CAN_2, 1},
+    {NC   , NC   , 0}
+};
+
+// Type definition to hold a CAN message
+struct CANMsg {
+    unsigned int  reserved1 : 16;
+    unsigned int  dlc       :  4; // Bits 16..19: DLC - Data Length Counter
+    unsigned int  reserved0 : 10;
+    unsigned int  rtr       :  1; // Bit 30: Set if this is a RTR message
+    unsigned int  type      :  1; // Bit 31: Set if this is a 29-bit ID message
+    unsigned int  id;             // CAN Message ID (11-bit or 29-bit)
+    unsigned char data[8];        // CAN Message Data Bytes 0-7
+};
+typedef struct CANMsg CANMsg;
+
+static uint32_t can_disable(can_t *obj) {
+    uint32_t sm = obj->dev->MOD;
+    obj->dev->MOD |= 1;
+    return sm;
+}
+
+static inline void can_enable(can_t *obj) {
+    if (obj->dev->MOD & 1) {
+        obj->dev->MOD &= ~(1);
+    }
+}
+
+static int can_pclk(can_t *obj) {
+    int value = 0;
+    switch ((int)obj->dev) {
+        case CAN_1: value = (LPC_SC->PCLKSEL0 & (0x3 << 26)) >> 26; break;
+        case CAN_2: value = (LPC_SC->PCLKSEL0 & (0x3 << 28)) >> 28; break;
+    }
+
+    switch (value) {
+        case 1: return 1;
+        case 2: return 2;
+        case 3: return 6;
+        default: return 4;
+    }
+}
+
+// This table has the sampling points as close to 75% as possible. The first
+// value is TSEG1, the second TSEG2.
+static const int timing_pts[23][2] = {
+    {0x0, 0x0},      // 2,  50%
+    {0x1, 0x0},      // 3,  67%
+    {0x2, 0x0},      // 4,  75%
+    {0x3, 0x0},      // 5,  80%
+    {0x3, 0x1},      // 6,  67%
+    {0x4, 0x1},      // 7,  71%
+    {0x5, 0x1},      // 8,  75%
+    {0x6, 0x1},      // 9,  78%
+    {0x6, 0x2},      // 10, 70%
+    {0x7, 0x2},      // 11, 73%
+    {0x8, 0x2},      // 12, 75%
+    {0x9, 0x2},      // 13, 77%
+    {0x9, 0x3},      // 14, 71%
+    {0xA, 0x3},      // 15, 73%
+    {0xB, 0x3},      // 16, 75%
+    {0xC, 0x3},      // 17, 76%
+    {0xD, 0x3},      // 18, 78%
+    {0xD, 0x4},      // 19, 74%
+    {0xE, 0x4},      // 20, 75%
+    {0xF, 0x4},      // 21, 76%
+    {0xF, 0x5},      // 22, 73%
+    {0xF, 0x6},      // 23, 70%
+    {0xF, 0x7},      // 24, 67%
+};
+
+static unsigned int can_speed(unsigned int sclk, unsigned int pclk, unsigned int cclk, unsigned char psjw) {
+    uint32_t    btr;
+    uint16_t    brp = 0;
+    uint32_t    calcbit;
+    uint32_t    bitwidth;
+    int         hit = 0;
+    int         bits;
+    
+    bitwidth = sclk / (pclk * cclk);
+    
+    brp = bitwidth / 0x18;
+    while ((!hit) && (brp < bitwidth / 4)) {
+        brp++;
+        for (bits = 22; bits > 0; bits--) {
+            calcbit = (bits + 3) * (brp + 1);
+            if (calcbit == bitwidth) {
+                hit = 1;
+                break;
+            }
+        }
+    }
+    
+    if (hit) {
+        btr = ((timing_pts[bits][1] << 20) & 0x00700000)
+            | ((timing_pts[bits][0] << 16) & 0x000F0000)
+            | ((psjw                << 14) & 0x0000C000)
+            | ((brp                 <<  0) & 0x000003FF);
+    } else {
+        btr = 0xFFFFFFFF;
+    }
+    
+    return btr;
+
+}
+
+void can_init(can_t *obj, PinName rd, PinName td) {
+    CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
+    CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+    obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
+    if ((int)obj->dev == NC) {
+        error("CAN pin mapping failed");
+    }
+
+    switch ((int)obj->dev) {
+        case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
+        case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
+    }
+
+    pinmap_pinout(rd, PinMap_CAN_RD);
+    pinmap_pinout(td, PinMap_CAN_TD);
+
+    can_reset(obj);
+    obj->dev->IER = 0;             // Disable Interrupts
+    can_frequency(obj, 100000);
+
+    LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
+}
+
+void can_free(can_t *obj) {
+    switch ((int)obj->dev) {
+        case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
+        case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
+    }
+}
+
+int can_frequency(can_t *obj, int f) {
+    int pclk = can_pclk(obj);
+    
+    int btr = can_speed(SystemCoreClock, pclk, (unsigned int)f, 1);
+
+    if (btr > 0) {
+        uint32_t modmask = can_disable(obj);
+        obj->dev->BTR = btr;
+        obj->dev->MOD = modmask;
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc) {
+    unsigned int CANStatus;
+    CANMsg m;
+
+    can_enable(obj);
+
+    m.id   = msg.id ;
+    m.dlc  = msg.len & 0xF;
+    m.rtr  = msg.type;
+    m.type = msg.format;
+    memcpy(m.data, msg.data, msg.len);
+    const unsigned int *buf = (const unsigned int *)&m;
+
+    CANStatus = obj->dev->SR;
+    if (CANStatus & 0x00000004) {
+        obj->dev->TFI1 = buf[0] & 0xC00F0000;
+        obj->dev->TID1 = buf[1];
+        obj->dev->TDA1 = buf[2];
+        obj->dev->TDB1 = buf[3];
+        if(cc) {
+            obj->dev->CMR = 0x30;
+        } else {
+            obj->dev->CMR = 0x21;
+        }
+        return 1;
+
+    } else if (CANStatus & 0x00000400) {
+        obj->dev->TFI2 = buf[0] & 0xC00F0000;
+        obj->dev->TID2 = buf[1];
+        obj->dev->TDA2 = buf[2];
+        obj->dev->TDB2 = buf[3];
+        if (cc) {
+            obj->dev->CMR = 0x50;
+        } else {
+            obj->dev->CMR = 0x41;
+        }
+        return 1;
+
+    } else if (CANStatus & 0x00040000) {
+        obj->dev->TFI3 = buf[0] & 0xC00F0000;
+        obj->dev->TID3 = buf[1];
+        obj->dev->TDA3 = buf[2];
+        obj->dev->TDB3 = buf[3];
+        if (cc) {
+            obj->dev->CMR = 0x90;
+        } else {
+            obj->dev->CMR = 0x81;
+        }
+        return 1;
+    }
+
+    return 0;
+}
+
+int can_read(can_t *obj, CAN_Message *msg) {
+    CANMsg x;
+    unsigned int *i = (unsigned int *)&x;
+
+    can_enable(obj);
+
+    if (obj->dev->GSR & 0x1) {
+        *i++ = obj->dev->RFS;  // Frame
+        *i++ = obj->dev->RID;  // ID
+        *i++ = obj->dev->RDA;  // Data A
+        *i++ = obj->dev->RDB;  // Data B
+        obj->dev->CMR = 0x04;  // release receive buffer
+
+        msg->id     = x.id;
+        msg->len    = x.dlc;
+        msg->format = (x.type)? CANExtended : CANStandard;
+        msg->type   = (x.rtr)?  CANRemote:    CANData;
+        memcpy(msg->data,x.data,x.dlc);
+        return 1;
+    }
+
+    return 0;
+}
+
+void can_reset(can_t *obj) {
+    can_disable(obj);
+    obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
+}
+
+unsigned char can_rderror(can_t *obj) {
+    return (obj->dev->GSR >> 16) & 0xFF;
+}
+
+unsigned char can_tderror(can_t *obj) {
+    return (obj->dev->GSR >> 24) & 0xFF;
+}
+
+void can_monitor(can_t *obj, int silent) {
+    uint32_t mod_mask = can_disable(obj);
+    if (silent) {
+        obj->dev->MOD |= (1 << 1);
+    } else {
+        obj->dev->MOD &= ~(1 << 1);
+    }
+    if (!(mod_mask & 1)) {
+        can_enable(obj);
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/device.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        1
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         1
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         1
+
+#define DEVICE_CAN              1
+
+#define DEVICE_RTC              1
+
+#define DEVICE_ETHERNET         1
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_SEMIHOST         1
+#define DEVICE_LOCALFILESYSTEM  1
+#define DEVICE_ID_LENGTH       32
+#define DEVICE_MAC_OFFSET      20
+
+#define DEVICE_SLEEP            1
+
+#define DEVICE_DEBUG_AWARENESS  1
+
+#define DEVICE_STDIO_MESSAGES   1
+
+#define DEVICE_ERROR_PATTERN    1
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/ethernet_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,948 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "ethernet_api.h"
+
+#include <string.h>
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "toolchain.h"
+#include "error.h"
+
+#define NEW_LOGIC       0
+#define NEW_ETH_BUFFER  0
+
+#if NEW_ETH_BUFFER
+
+#define NUM_RX_FRAG         4           // Number of Rx Fragments (== packets)
+#define NUM_TX_FRAG         3           // Number of Tx Fragments (== packets)
+
+#define ETH_MAX_FLEN        1536         // Maximum Ethernet Frame Size
+#define ETH_FRAG_SIZE       ETH_MAX_FLEN // Packet Fragment size (same as packet length)
+
+#else
+
+// Memfree calculation:
+// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
+//                (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
+#define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */
+#define NUM_TX_FRAG         3           /* Num.of TX Fragments 3*1536= 4.6kB */
+//#define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
+
+//#define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
+#define ETH_FRAG_SIZE       0x300       /* Packet Fragment size 1536/2 Bytes   */
+#define ETH_MAX_FLEN        0x300       /* Max. Ethernet Frame Size          */
+
+const int ethernet_MTU_SIZE  = 0x300;
+
+#endif
+
+#define ETHERNET_ADDR_SIZE 6
+
+PACKED struct RX_DESC_TypeDef {                        /* RX Descriptor struct              */
+   unsigned int Packet;
+   unsigned int Ctrl;
+};
+typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
+
+PACKED struct RX_STAT_TypeDef {                        /* RX Status struct                  */
+   unsigned int Info;
+   unsigned int HashCRC;
+};
+typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
+
+PACKED struct TX_DESC_TypeDef {                        /* TX Descriptor struct              */
+   unsigned int Packet;
+   unsigned int Ctrl;
+};
+typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
+
+PACKED struct TX_STAT_TypeDef {                        /* TX Status struct                  */
+   unsigned int Info;
+};
+typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
+
+/* MAC Configuration Register 1 */
+#define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
+#define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
+#define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
+#define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
+#define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
+#define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
+#define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
+#define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
+#define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
+#define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
+#define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
+
+/* MAC Configuration Register 2 */
+#define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
+#define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
+#define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
+#define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
+#define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
+#define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
+#define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
+#define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
+#define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
+#define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
+#define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
+#define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
+#define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
+
+/* Back-to-Back Inter-Packet-Gap Register */
+#define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
+#define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
+
+/* Non Back-to-Back Inter-Packet-Gap Register */
+#define IPGR_DEF            0x00000012  /* Recommended value                 */
+
+/* Collision Window/Retry Register */
+#define CLRT_DEF            0x0000370F  /* Default value                     */
+
+/* PHY Support Register */
+#define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
+//#define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */
+#define SUPP_RES_RMII       0x00000000  /* Reset Reduced MII Logic           */
+
+/* Test Register */
+#define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
+#define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
+#define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
+
+/* MII Management Configuration Register */
+#define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
+#define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
+#define MCFG_CLK_SEL        0x0000003C  /* Clock Select Mask                 */
+#define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
+
+/* MII Management Command Register */
+#define MCMD_READ           0x00000001  /* MII Read                          */
+#define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
+
+#define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
+#define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
+
+/* MII Management Address Register */
+#define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
+#define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
+
+/* MII Management Indicators Register */
+#define MIND_BUSY           0x00000001  /* MII is Busy                       */
+#define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
+#define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
+#define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
+
+/* Command Register */
+#define CR_RX_EN            0x00000001  /* Enable Receive                    */
+#define CR_TX_EN            0x00000002  /* Enable Transmit                   */
+#define CR_REG_RES          0x00000008  /* Reset Host Registers              */
+#define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
+#define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
+#define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
+#define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
+#define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
+#define CR_RMII             0x00000200  /* Reduced MII Interface             */
+#define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
+
+/* Status Register */
+#define SR_RX_EN            0x00000001  /* Enable Receive                    */
+#define SR_TX_EN            0x00000002  /* Enable Transmit                   */
+
+/* Transmit Status Vector 0 Register */
+#define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
+#define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
+#define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
+#define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
+#define TSV0_MCAST          0x00000010  /* Multicast Destination             */
+#define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
+#define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
+#define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
+#define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
+#define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
+#define TSV0_GIANT          0x00000400  /* Giant Frame                       */
+#define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
+#define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
+#define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
+#define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
+#define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
+#define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
+
+/* Transmit Status Vector 1 Register */
+#define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
+#define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
+
+/* Receive Status Vector Register */
+#define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
+#define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
+#define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
+#define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
+#define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
+#define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
+#define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
+#define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
+#define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
+#define RSV_MCAST           0x01000000  /* Multicast Frame                   */
+#define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
+#define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
+#define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
+#define RSV_PAUSE           0x10000000  /* Pause Frame                       */
+#define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
+#define RSV_VLAN            0x40000000  /* VLAN Frame                        */
+
+/* Flow Control Counter Register */
+#define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
+#define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
+
+/* Flow Control Status Register */
+#define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
+
+/* Receive Filter Control Register */
+#define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
+#define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
+#define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
+#define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
+#define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
+#define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
+#define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
+#define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
+
+/* Receive Filter WoL Status/Clear Registers */
+#define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
+#define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
+#define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
+#define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
+#define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
+#define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
+#define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
+#define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
+
+/* Interrupt Status/Enable/Clear/Set Registers */
+#define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
+#define INT_RX_ERR          0x00000002  /* Receive Error                     */
+#define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
+#define INT_RX_DONE         0x00000008  /* Receive Done                      */
+#define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
+#define INT_TX_ERR          0x00000020  /* Transmit Error                    */
+#define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
+#define INT_TX_DONE         0x00000080  /* Transmit Done                     */
+#define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
+#define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
+
+/* Power Down Register */
+#define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
+
+/* RX Descriptor Control Word */
+#define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
+#define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
+
+/* RX Status Hash CRC Word */
+#define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
+#define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
+
+/* RX Status Information Word */
+#define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
+#define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
+#define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
+#define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
+#define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
+#define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
+#define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
+#define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
+#define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
+#define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
+#define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
+#define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
+#define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
+#define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
+#define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
+
+//#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
+                            RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+
+
+/* TX Descriptor Control Word */
+#define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
+#define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
+#define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
+#define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
+#define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
+#define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
+#define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
+
+/* TX Status Information Word */
+#define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
+#define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
+#define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
+#define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
+#define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
+#define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
+#define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
+#define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
+
+/* ENET Device Revision ID */
+#define OLD_EMAC_MODULE_ID  0x39022000  /* Rev. ID for first rev '-'         */
+
+/* DP83848C PHY Registers */
+#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
+#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
+#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
+#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
+#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
+#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
+#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
+#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
+
+/* PHY Extended Registers */
+#define PHY_REG_STS         0x10        /* Status Register                   */
+#define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */
+#define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */
+#define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */
+#define PHY_REG_RECR        0x15        /* Receive Error Counter             */
+#define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */
+#define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */
+#define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */
+#define PHY_REG_PHYCR       0x19        /* PHY Control Register              */
+#define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */
+#define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */
+#define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */
+
+#define PHY_REG_SCSR        0x1F        /* PHY Special Control/Status Register */
+
+#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
+#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
+#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
+#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
+#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */
+
+#define DP83848C_DEF_ADR    0x0100      /* Default PHY device address        */
+#define DP83848C_ID         0x20005C90  /* PHY Identifier - DP83848C         */
+
+#define LAN8720_ID          0x0007C0F0  /* PHY Identifier - LAN8720          */
+
+#define PHY_STS_LINK        0x0001      /* PHY Status Link Mask              */
+#define PHY_STS_SPEED       0x0002      /* PHY Status Speed Mask             */
+#define PHY_STS_DUPLEX      0x0004      /* PHY Status Duplex Mask            */
+
+#define PHY_BMCR_RESET      0x8000      /* PHY Reset                         */
+
+#define PHY_BMSR_LINK       0x0004      /* PHY BMSR Link valid               */
+
+#define PHY_SCSR_100MBIT    0x0008      /* Speed: 1=100 MBit, 0=10Mbit       */
+#define PHY_SCSR_DUPLEX     0x0010      /* PHY Duplex Mask                   */
+
+
+static int phy_read(unsigned int PhyReg);
+static int phy_write(unsigned int PhyReg, unsigned short Data);
+
+static void txdscr_init(void);
+static void rxdscr_init(void);
+
+#if defined (__ICCARM__)
+#   define AHBSRAM1
+#elif defined(TOOLCHAIN_GCC_CR)
+#   define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
+#else
+#   define AHBSRAM1     __attribute__((section("AHBSRAM1"),aligned))
+#endif
+
+AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
+AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
+AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
+AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
+
+
+#if NEW_LOGIC
+static int rx_consume_offset = -1;
+static int tx_produce_offset = -1;
+#else
+static int send_doff =  0;
+static int send_idx  = -1;
+static int send_size =  0;
+
+static int receive_soff =  0;
+static int receive_idx  = -1;
+#endif
+
+static uint32_t phy_id = 0;
+
+static inline int rinc(int idx, int mod) {
+  ++idx;
+  idx %= mod;
+  return idx;
+}
+
+//extern unsigned int SystemFrequency;
+static inline unsigned int clockselect() {
+  if(SystemCoreClock < 10000000) {
+    return 1;
+  } else if(SystemCoreClock <  15000000) {
+    return 2;
+  } else if(SystemCoreClock <  20000000) {
+    return 3;
+  } else if(SystemCoreClock <  25000000) {
+    return 4;
+  } else if(SystemCoreClock <  35000000) {
+    return 5;
+  } else if(SystemCoreClock <  50000000) {
+    return 6;
+  } else if(SystemCoreClock <  70000000) {
+    return 7;
+  } else if(SystemCoreClock <  80000000) {
+    return 8;
+  } else if(SystemCoreClock <  90000000) {
+    return 9;
+  } else if(SystemCoreClock < 100000000) {
+    return 10;
+  } else if(SystemCoreClock < 120000000) {
+    return 11;
+  } else if(SystemCoreClock < 130000000) {
+    return 12;
+  } else if(SystemCoreClock < 140000000) {
+    return 13;
+  } else if(SystemCoreClock < 150000000) {
+    return 15;
+  } else if(SystemCoreClock < 160000000) {
+    return 16;
+  } else {
+    return 0;
+  }
+}
+
+#ifndef min
+#define min(x, y) (((x)<(y))?(x):(y))
+#endif
+
+/*----------------------------------------------------------------------------
+  Ethernet Device initialize
+ *----------------------------------------------------------------------------*/
+int ethernet_init() {
+  int regv, tout;
+  char mac[ETHERNET_ADDR_SIZE];
+  unsigned int clock = clockselect();
+  
+  LPC_SC->PCONP |= 0x40000000;                       /* Power Up the EMAC controller. */
+  
+  LPC_PINCON->PINSEL2 = 0x50150105;                  /* Enable P1 Ethernet Pins. */
+  LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
+
+   /* Reset all EMAC internal modules. */
+  LPC_EMAC->MAC1    = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
+                      MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
+  LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
+
+  for(tout = 100; tout; tout--) __NOP();             /* A short delay after reset. */
+
+  LPC_EMAC->MAC1 = MAC1_PASS_ALL;                    /* Initialize MAC control registers. */
+  LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+  LPC_EMAC->MAXF = ETH_MAX_FLEN;
+  LPC_EMAC->CLRT = CLRT_DEF;
+  LPC_EMAC->IPGR = IPGR_DEF;
+
+  LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;    /* Enable Reduced MII interface. */
+
+  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;    /* Set clock */
+  LPC_EMAC->MCFG |= MCFG_RES_MII;                    /* and reset */
+
+  for(tout = 100; tout; tout--) __NOP();             /* A short delay */
+
+  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
+  LPC_EMAC->MCMD = 0;
+
+  LPC_EMAC->SUPP = SUPP_RES_RMII;                    /* Reset Reduced MII Logic. */
+
+  for (tout = 100; tout; tout--) __NOP();            /* A short delay */
+
+  LPC_EMAC->SUPP = 0;
+
+  phy_write(PHY_REG_BMCR, PHY_BMCR_RESET);           /* perform PHY reset */
+  for(tout = 0x20000; ; tout--) {                    /* Wait for hardware reset to end. */
+    regv = phy_read(PHY_REG_BMCR);
+    if(regv < 0 || tout == 0) {
+       return -1;                                    /* Error */
+    }
+    if(!(regv & PHY_BMCR_RESET)) {
+       break;                                        /* Reset complete. */
+    }
+  }
+
+  phy_id =  (phy_read(PHY_REG_IDR1) << 16);
+  phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
+
+  if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
+      error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
+  }
+
+  ethernet_set_link(-1, 0);
+
+  /* Set the Ethernet MAC Address registers */
+  ethernet_address(mac);
+  LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
+  LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
+  LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
+
+  txdscr_init();                                      /* initialize DMA TX Descriptor */
+  rxdscr_init();                                      /* initialize DMA RX Descriptor */
+
+  LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
+                                                      /* Receive Broadcast, Perfect Match Packets */
+
+  LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;    /* Enable EMAC interrupts. */
+  LPC_EMAC->IntClear  = 0xFFFF;                       /* Reset all interrupts */
+
+
+  LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);        /* Enable receive and transmit mode of MAC Ethernet core */
+  LPC_EMAC->MAC1     |= MAC1_REC_EN;
+
+#if NEW_LOGIC
+  rx_consume_offset = -1;
+  tx_produce_offset = -1;
+#else
+  send_doff =  0;
+  send_idx  = -1;
+  send_size =  0;
+
+  receive_soff =  0;
+  receive_idx  = -1;
+#endif
+
+  return 0;
+}
+
+/*----------------------------------------------------------------------------
+  Ethernet Device Uninitialize
+ *----------------------------------------------------------------------------*/
+void ethernet_free() {
+    LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
+    LPC_EMAC->IntClear   =  0xFFFF;
+    
+    LPC_SC->PCONP   &= ~0x40000000;       /* Power down the EMAC controller. */
+    
+    LPC_PINCON->PINSEL2 &= ~0x50150105;   /* Disable P1 ethernet pins. */
+    LPC_PINCON->PINSEL3  = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000000;
+}
+
+// if(TxProduceIndex == TxConsumeIndex) buffer array is empty
+// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
+// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
+// TxConsumeIndex - The buffer that will/is beign sent by hardware
+
+int ethernet_write(const char *data, int slen) {
+
+#if NEW_LOGIC
+
+   if(tx_produce_offset < 0) { // mark as active if not already
+     tx_produce_offset = 0;
+   }
+
+   int index = LPC_EMAC->TxProduceIndex;
+
+   int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
+   int requested = slen;
+   int ncopy = min(remaining, requested);
+
+   void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
+   void *psrc = (void *)(data);
+
+   if(ncopy > 0 ){
+     if(data != NULL) {
+       memcpy(pdst, psrc, ncopy);
+     } else {
+       memset(pdst, 0, ncopy);
+     }
+   }
+
+   tx_produce_offset += ncopy;
+
+   return ncopy;
+
+#else
+    void       *pdst, *psrc;
+    const int   dlen = ETH_FRAG_SIZE;
+    int         copy = 0;
+    int         soff = 0;
+
+    if(send_idx == -1) {
+        send_idx = LPC_EMAC->TxProduceIndex;
+    }
+
+    if(slen + send_doff > ethernet_MTU_SIZE) {
+       return -1;
+    }
+
+    do {
+        copy = min(slen - soff, dlen - send_doff);
+        pdst = (void *)(txdesc[send_idx].Packet + send_doff);
+        psrc = (void *)(data + soff);
+        if(send_doff + copy > ETH_FRAG_SIZE) {
+            txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
+            send_idx = rinc(send_idx, NUM_TX_FRAG);
+            send_doff = 0;
+        }
+
+        if(data != NULL) {
+            memcpy(pdst, psrc, copy);
+        } else {
+            memset(pdst, 0, copy);
+        }
+
+        soff += copy;
+        send_doff += copy;
+        send_size += copy;
+    } while(soff != slen);
+
+    return soff;
+#endif
+}
+
+int ethernet_send() {
+
+#if NEW_LOGIC
+  if(tx_produce_offset < 0) { // no buffer active
+    return -1;
+  }
+
+  // ensure there is a link
+  if(!ethernet_link()) {
+    return -2;
+  }
+
+  // we have been writing in to a buffer, so finalise it
+  int size = tx_produce_offset;
+  int index = LPC_EMAC->TxProduceIndex;
+  txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
+
+  // Increment ProduceIndex to allow it to be sent
+  // We can only do this if the next slot is free
+  int next = rinc(index, NUM_TX_FRAG);
+  while(next == LPC_EMAC->TxConsumeIndex) {
+    for(int i=0; i<1000; i++) { __NOP(); }
+  }
+
+  LPC_EMAC->TxProduceIndex = next;
+  tx_produce_offset = -1;
+  return size;
+
+#else
+    int s = send_size;
+    txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
+    send_idx  = rinc(send_idx, NUM_TX_FRAG);
+    LPC_EMAC->TxProduceIndex = send_idx;
+    send_doff =  0;
+    send_idx  = -1;
+    send_size =  0;
+    return s;
+#endif
+}
+
+// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
+// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
+//
+// if(RxConsumeIndex == RxProduceIndex) buffer array is empty
+// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
+
+// Recevies an arrived ethernet packet.
+// Receiving an ethernet packet will drop the last received ethernet packet
+// and make a new ethernet packet ready to read.
+// Returns size of packet, else 0 if nothing to receive
+
+// We read from RxConsumeIndex from position rx_consume_offset
+// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
+// rx_consume_offset = -1 // no frame
+// rx_consume_offset = 0  // start of frame
+// Assumption: A fragment should alway be a whole frame
+
+int ethernet_receive() {
+#if NEW_LOGIC
+
+  // if we are currently reading a valid RxConsume buffer, increment to the next one
+  if(rx_consume_offset >= 0) {
+    LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
+  }
+
+  // if the buffer is empty, mark it as no valid buffer
+  if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
+    rx_consume_offset = -1;
+    return 0;
+  }
+
+  uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
+  rx_consume_offset = 0;
+
+  // check if it is not marked as last or for errors
+  if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
+    return -1;
+  }
+
+  int size = (info & RINFO_SIZE) + 1;
+  return size - 4; // don't include checksum bytes
+
+#else
+    if(receive_idx == -1) {
+      receive_idx = LPC_EMAC->RxConsumeIndex;
+    } else {
+        while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && (receive_idx != LPC_EMAC->RxProduceIndex)) {
+            receive_idx  = rinc(receive_idx, NUM_RX_FRAG);
+        }
+        unsigned int info =   rxstat[receive_idx].Info;
+        int slen =  (info & RINFO_SIZE) + 1;
+
+        if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
+            /* Invalid frame, ignore it and free buffer. */
+            receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+        }
+        receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+        receive_soff = 0;
+
+        LPC_EMAC->RxConsumeIndex = receive_idx;
+    }
+
+    if(receive_idx == LPC_EMAC->RxProduceIndex) {
+        receive_idx = -1;
+        return 0;
+    }
+
+    return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
+#endif
+}
+
+// Read from an recevied ethernet packet.
+// After receive returnd a number bigger than 0 it is
+// possible to read bytes from this packet.
+// Read will write up to size bytes into data.
+// It is possible to use read multible times.
+// Each time read will start reading after the last read byte before.
+
+int ethernet_read(char *data, int dlen) {
+#if NEW_LOGIC
+  // Check we have a valid buffer to read
+  if(rx_consume_offset < 0) {
+    return 0;
+  }
+
+  // Assume 1 fragment block
+  uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
+  int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
+
+  int remaining = size - rx_consume_offset;
+  int requested = dlen;
+  int ncopy = min(remaining, requested);
+
+  void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
+  void *pdst = (void *)(data);
+
+  if(data != NULL && ncopy > 0) {
+    memcpy(pdst, psrc, ncopy);
+  }
+
+  rx_consume_offset += ncopy;
+
+  return ncopy;
+#else
+    int          slen;
+    int          copy   = 0;
+    unsigned int more;
+    unsigned int info;
+    void        *pdst, *psrc;
+    int          doff = 0;
+
+    if(receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
+        return 0;
+    }
+
+    do {
+        info =   rxstat[receive_idx].Info;
+        more = !(info & RINFO_LAST_FLAG);
+        slen =  (info & RINFO_SIZE) + 1;
+
+        if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
+            /* Invalid frame, ignore it and free buffer. */
+            receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+        } else {
+
+            copy = min(slen - receive_soff, dlen - doff);
+            psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
+            pdst = (void *)(data + doff);
+
+            if(data != NULL) {
+                /* check if Buffer available */
+                memcpy(pdst, psrc, copy);
+            }
+
+            receive_soff += copy;
+            doff += copy;
+
+            if((more && (receive_soff == slen))) {
+                receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+                receive_soff = 0;
+            }
+        }
+    } while(more && !(doff == dlen) && !receive_soff);
+
+    return doff;
+#endif
+}
+
+int ethernet_link(void) {
+
+    if (phy_id == DP83848C_ID) {
+      return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
+    }
+    else { // LAN8720_ID
+      return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
+    }
+}
+
+static int phy_write(unsigned int PhyReg, unsigned short Data) {
+    unsigned int timeOut;
+
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MWTD = Data;
+
+    for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) {     /* Wait until operation completed */
+        if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+            return 0;
+        }
+    }
+
+    return -1;
+}
+
+
+static int phy_read(unsigned int PhyReg) {
+    unsigned int timeOut;
+
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MCMD = MCMD_READ;
+
+    for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) {     /* Wait until operation completed */
+        if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+            LPC_EMAC->MCMD = 0;
+            return LPC_EMAC->MRDD;                           /* Return a 16-bit value. */
+        }
+    }
+
+    return -1;
+}
+
+
+static void txdscr_init() {
+    int i;
+
+    for(i = 0; i < NUM_TX_FRAG; i++) {
+        txdesc[i].Packet = (uint32_t)&txbuf[i];
+        txdesc[i].Ctrl   = 0;
+        txstat[i].Info   = 0;
+    }
+
+    LPC_EMAC->TxDescriptor       = (uint32_t)txdesc;         /* Set EMAC Transmit Descriptor Registers. */
+    LPC_EMAC->TxStatus           = (uint32_t)txstat;
+    LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
+
+    LPC_EMAC->TxProduceIndex  = 0;                           /* Tx Descriptors Point to 0 */
+}
+
+
+static void rxdscr_init() {
+    int i;
+
+    for(i = 0; i < NUM_RX_FRAG; i++) {
+        rxdesc[i].Packet  = (uint32_t)&rxbuf[i];
+        rxdesc[i].Ctrl    = RCTRL_INT | (ETH_FRAG_SIZE-1);
+        rxstat[i].Info    = 0;
+        rxstat[i].HashCRC = 0;
+    }
+
+    LPC_EMAC->RxDescriptor       = (uint32_t)rxdesc;        /* Set EMAC Receive Descriptor Registers. */
+    LPC_EMAC->RxStatus           = (uint32_t)rxstat;
+    LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
+
+    LPC_EMAC->RxConsumeIndex  = 0;                          /* Rx Descriptors Point to 0 */
+}
+
+void ethernet_address(char *mac) {
+    mbed_mac_address(mac);
+}
+
+void ethernet_set_link(int speed, int duplex) {
+    unsigned short phy_data;
+    int tout;
+
+    if((speed < 0) || (speed > 1)) {
+
+        phy_data = PHY_AUTO_NEG;
+
+    } else {
+
+        phy_data = (((unsigned short) speed << 13) |
+                    ((unsigned short) duplex << 8));
+    }
+
+    phy_write(PHY_REG_BMCR, phy_data);
+
+    for(tout = 100; tout; tout--) { __NOP(); }     /* A short delay */
+
+    switch(phy_id) {
+    case DP83848C_ID:
+
+        phy_data = phy_read(PHY_REG_STS);
+
+        if(phy_data & PHY_STS_DUPLEX) {
+            LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
+            LPC_EMAC->Command |= CR_FULL_DUP;
+            LPC_EMAC->IPGT = IPGT_FULL_DUP;
+        } else {
+        LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
+            LPC_EMAC->Command &= ~CR_FULL_DUP;
+            LPC_EMAC->IPGT = IPGT_HALF_DUP;
+        }
+
+        if(phy_data & PHY_STS_SPEED) {
+            LPC_EMAC->SUPP &= ~SUPP_SPEED;
+        } else {
+            LPC_EMAC->SUPP |= SUPP_SPEED;
+        }
+
+
+        break;
+    case LAN8720_ID:
+
+        phy_data = phy_read(PHY_REG_SCSR);
+
+        if (phy_data & PHY_SCSR_DUPLEX) {
+            LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
+            LPC_EMAC->Command |= CR_FULL_DUP;
+            LPC_EMAC->IPGT = IPGT_FULL_DUP;
+        } else {
+            LPC_EMAC->Command &= ~CR_FULL_DUP;
+            LPC_EMAC->IPGT = IPGT_HALF_DUP;
+        }
+
+        if(phy_data & PHY_SCSR_100MBIT) {
+            LPC_EMAC->SUPP |= SUPP_SPEED;
+        } else {
+            LPC_EMAC->SUPP &= ~SUPP_SPEED;
+        }
+
+
+        break;
+    }
+
+
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+
+uint32_t gpio_set(PinName pin) {
+    pin_function(pin, 0);
+    return (1 << ((int)pin & 0x1F));
+}
+
+void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
+    if(pin == NC) return;
+    
+    obj->pin = pin;
+    obj->mask = gpio_set(pin);
+    
+    LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *) ((int)pin & ~0x1F);
+    obj->reg_set = &port_reg->FIOSET;
+    obj->reg_clr = &port_reg->FIOCLR;
+    obj->reg_in  = &port_reg->FIOPIN;
+    obj->reg_dir = &port_reg->FIODIR;
+    
+    gpio_dir(obj, direction);
+    switch (direction) {
+        case PIN_OUTPUT: pin_mode(pin, PullNone); break;
+        case PIN_INPUT : pin_mode(pin, PullDown); break;
+    }
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+    pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+    switch (direction) {
+        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_irq_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,144 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+
+#include "gpio_irq_api.h"
+#include "error.h"
+#include "cmsis.h"
+
+#define CHANNEL_NUM     48
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+
+static void handle_interrupt_in(void) {
+    // Read in all current interrupt registers. We do this once as the
+    // GPIO interrupt registers are on the APB bus, and this is slow.
+    uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
+    uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
+    uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
+    uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
+    uint32_t mask0 = 0;
+    uint32_t mask2 = 0;
+    int i;
+
+    // P0.0-0.31
+    for (i = 0; i < 32; i++) {
+        uint32_t pmask = (1 << i);
+        if (rise0 & pmask) {
+            mask0 |= pmask;
+            if (channel_ids[i] != 0)
+                irq_handler(channel_ids[i], IRQ_RISE);
+        }
+        if (fall0 & pmask) {
+            mask0 |= pmask;
+            if (channel_ids[i] != 0)
+                irq_handler(channel_ids[i], IRQ_FALL);
+        }
+    }
+    
+    // P2.0-2.15
+    for (i = 0; i < 16; i++) {
+        uint32_t pmask = (1 << i);
+        int channel_index = i + 32;
+        if (rise2 & pmask) {
+            mask2 |= pmask;
+            if (channel_ids[channel_index] != 0)
+                irq_handler(channel_ids[channel_index], IRQ_RISE);
+        }
+        if (fall2 & pmask) {
+            mask2 |= pmask;
+            if (channel_ids[channel_index] != 0)
+                irq_handler(channel_ids[channel_index], IRQ_FALL);
+        }
+    }
+
+    // Clear the interrupts we just handled
+    LPC_GPIOINT->IO0IntClr = mask0;
+    LPC_GPIOINT->IO2IntClr = mask2;
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+    if (pin == NC) return -1;
+    
+    irq_handler = handler;
+    
+    obj->port = (int)pin & ~0x1F;
+    obj->pin = (int)pin & 0x1F;
+    
+    // Interrupts available only on GPIO0 and GPIO2
+    if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
+        error("pins on this port cannot generate interrupts\n");
+    }
+    
+    // put us in the interrupt table
+    int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
+    channel_ids[index] = id;
+    obj->ch = index;
+    
+    NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
+    NVIC_EnableIRQ(EINT3_IRQn);
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+    channel_ids[obj->ch] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+    // ensure nothing is pending
+    switch (obj->port) {
+         case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
+         case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
+    }
+
+    // enable the pin interrupt
+    if (event == IRQ_RISE) {
+        switch (obj->port) {
+            case LPC_GPIO0_BASE:
+                if (enable) {
+                    LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
+                } else {
+                    LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
+                }
+                break;
+            case LPC_GPIO2_BASE:
+                if (enable) {
+                    LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
+                } else {
+                    LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
+                }
+                break;
+        }
+    } else {
+        switch (obj->port) {
+            case LPC_GPIO0_BASE:
+                if (enable) {
+                    LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
+                } else {
+                    LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
+                }
+                break;
+            case LPC_GPIO2_BASE:
+                if (enable) {
+                    LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
+                } else {
+                    LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
+                }
+                break;
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_object.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName  pin;
+    uint32_t mask;
+
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_set;
+    __IO uint32_t *reg_clr;
+    __I  uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+    if (value)
+        *obj->reg_set = obj->mask;
+    else
+        *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/i2c_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,397 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_I2C_SDA[] = {
+    {P0_0 , I2C_1, 3},
+    {P0_10, I2C_2, 2},
+    {P0_19, I2C_1, 3},
+    {P0_27, I2C_0, 1},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+    {P0_1 , I2C_1, 3},
+    {P0_11, I2C_2, 2},
+    {P0_20, I2C_1, 3},
+    {P0_28, I2C_0, 1},
+    {NC   , NC,    0}
+};
+
+#define I2C_CONSET(x)       (x->i2c->I2CONSET)
+#define I2C_CONCLR(x)       (x->i2c->I2CONCLR)
+#define I2C_STAT(x)         (x->i2c->I2STAT)
+#define I2C_DAT(x)          (x->i2c->I2DAT)
+#define I2C_SCLL(x, val)    (x->i2c->I2SCLL = val)
+#define I2C_SCLH(x, val)    (x->i2c->I2SCLH = val)
+
+static const uint32_t I2C_addr_offset[2][4] = {
+    {0x0C, 0x20, 0x24, 0x28},
+    {0x30, 0x34, 0x38, 0x3C}
+};
+
+static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+    I2C_CONCLR(obj) = (start << 5)
+                    | (stop << 4)
+                    | (interrupt << 3)
+                    | (acknowledge << 2);
+}
+
+static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+    I2C_CONSET(obj) = (start << 5)
+                    | (stop << 4)
+                    | (interrupt << 3)
+                    | (acknowledge << 2);
+}
+
+// Clear the Serial Interrupt (SI)
+static inline void i2c_clear_SI(i2c_t *obj) {
+    i2c_conclr(obj, 0, 0, 1, 0);
+}
+
+static inline int i2c_status(i2c_t *obj) {
+    return I2C_STAT(obj);
+}
+
+// Wait until the Serial Interrupt (SI) is set
+static int i2c_wait_SI(i2c_t *obj) {
+    int timeout = 0;
+    while (!(I2C_CONSET(obj) & (1 << 3))) {
+        timeout++;
+        if (timeout > 100000) return -1;
+    }
+    return 0;
+}
+
+static inline void i2c_interface_enable(i2c_t *obj) {
+    I2C_CONSET(obj) = 0x40;
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+    switch ((int)obj->i2c) {
+        case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
+        case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
+        case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
+    }
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+    // determine the SPI to use
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+    obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
+    
+    if ((int)obj->i2c == NC) {
+        error("I2C pin mapping failed");
+    }
+    
+    // enable power
+    i2c_power_enable(obj);
+    
+    // set default frequency at 100k
+    i2c_frequency(obj, 100000);
+    i2c_conclr(obj, 1, 1, 1, 1);
+    i2c_interface_enable(obj);
+    
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+}
+
+inline int i2c_start(i2c_t *obj) {
+    int status = 0;
+    // 8.1 Before master mode can be entered, I2CON must be initialised to:
+    //  - I2EN STA STO SI AA - -
+    //  -  1    0   0   0  x - -
+    // if AA = 0, it can't enter slave mode
+    i2c_conclr(obj, 1, 1, 1, 1);
+    
+    // The master mode may now be entered by setting the STA bit
+    // this will generate a start condition when the bus becomes free
+    i2c_conset(obj, 1, 0, 0, 1);
+    
+    i2c_wait_SI(obj);
+    status = i2c_status(obj);
+    
+    // Clear start bit now transmitted, and interrupt bit
+    i2c_conclr(obj, 1, 0, 0, 0);
+    return status;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+    int timeout = 0;
+
+    // write the stop bit
+    i2c_conset(obj, 0, 1, 0, 0);
+    i2c_clear_SI(obj);
+    
+    // wait for STO bit to reset
+    while(I2C_CONSET(obj) & (1 << 4)) {
+        timeout ++;
+        if (timeout > 100000) return 1;
+    }
+
+    return 0;
+}
+
+static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
+    // write the data
+    I2C_DAT(obj) = value;
+    
+    // clear SI to init a send
+    i2c_clear_SI(obj);
+    
+    // wait and return status
+    i2c_wait_SI(obj);
+    return i2c_status(obj);
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+    // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
+    if(last) {
+        i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
+    } else {
+        i2c_conset(obj, 0, 0, 0, 1); // send a ACK
+    }
+    
+    // accept byte
+    i2c_clear_SI(obj);
+    
+    // wait for it to arrive
+    i2c_wait_SI(obj);
+    
+    // return the data
+    return (I2C_DAT(obj) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+    // [TODO] set pclk to /4
+    uint32_t PCLK = SystemCoreClock / 4;
+    
+    uint32_t pulse = PCLK / (hz * 2);
+    
+    // I2C Rate
+    I2C_SCLL(obj, pulse);
+    I2C_SCLH(obj, pulse);
+}
+
+// The I2C does a read or a write as a whole operation
+// There are two types of error conditions it can encounter
+//  1) it can not obtain the bus
+//  2) it gets error responses at part of the transmission
+//
+// We tackle them as follows:
+//  1) we retry until we get the bus. we could have a "timeout" if we can not get it
+//      which basically turns it in to a 2)
+//  2) on error, we use the standard error mechanisms to report/debug
+//
+// Therefore an I2C transaction should always complete. If it doesn't it is usually
+// because something is setup wrong (e.g. wiring), and we don't need to programatically
+// check for that
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+    int count, status;
+    
+    status = i2c_start(obj);
+    
+    if ((status != 0x10) && (status != 0x08)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+    
+    status = i2c_do_write(obj, (address | 0x01), 1);
+    if (status != 0x40) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    
+    // Read in all except last byte
+    for (count = 0; count < (length - 1); count++) {
+        int value = i2c_do_read(obj, 0);
+        status = i2c_status(obj);
+        if (status != 0x50) {
+            i2c_stop(obj);
+            return count;
+        }
+        data[count] = (char) value;
+    }
+    
+    // read in last byte
+    int value = i2c_do_read(obj, 1);
+    status = i2c_status(obj);
+    if (status != 0x58) {
+        i2c_stop(obj);
+        return length - 1;
+    }
+    
+    data[count] = (char) value;
+    
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+    
+    return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+    int i, status;
+    
+    status = i2c_start(obj);
+    
+    if ((status != 0x10) && (status != 0x08)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+    
+    status = i2c_do_write(obj, (address & 0xFE), 1);
+    if (status != 0x18) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    
+    for (i=0; i<length; i++) {
+        status = i2c_do_write(obj, data[i], 0);
+        if(status != 0x28) {
+            i2c_stop(obj);
+            return i;
+        }
+    }
+    
+    // clearing the serial interrupt here might cause an unintended rewrite of the last byte
+    // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
+    // i2c_clear_SI(obj);
+    
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+    
+    return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+    i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+    return (i2c_do_read(obj, last) & 0xFF);
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+    int ack;
+    int status = i2c_do_write(obj, (data & 0xFF), 0);
+    
+    switch(status) {
+        case 0x18: case 0x28:       // Master transmit ACKs
+            ack = 1;
+            break;
+        case 0x40:                  // Master receive address transmitted ACK
+            ack = 1;
+            break;
+        case 0xB8:                  // Slave transmit ACK
+            ack = 1;
+            break;
+        default:
+            ack = 0;
+            break;
+    }
+    
+    return ack;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+    if (enable_slave != 0) {
+        i2c_conclr(obj, 1, 1, 1, 0);
+        i2c_conset(obj, 0, 0, 0, 1);
+    } else {
+        i2c_conclr(obj, 1, 1, 1, 1);
+    }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+    int status;
+    int retval;
+    
+    status = i2c_status(obj);
+    switch(status) {
+        case 0x60: retval = 3; break;
+        case 0x70: retval = 2; break;
+        case 0xA8: retval = 1; break;
+        default  : retval = 0; break;
+    }
+    
+    return(retval);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+    int count = 0;
+    int status;
+    
+    do {
+        i2c_clear_SI(obj);
+        i2c_wait_SI(obj);
+        status = i2c_status(obj);
+        if((status == 0x80) || (status == 0x90)) {
+            data[count] = I2C_DAT(obj) & 0xFF;
+        }
+        count++;
+    } while (((status == 0x80) || (status == 0x90) ||
+            (status == 0x060) || (status == 0x70)) && (count < length));
+    
+    if(status != 0xA0) {
+        i2c_stop(obj);
+    }
+    
+    i2c_clear_SI(obj);
+    
+    return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+    int count = 0;
+    int status;
+    
+    if(length <= 0) {
+        return(0);
+    }
+    
+    do {
+        status = i2c_do_write(obj, data[count], 0);
+        count++;
+    } while ((count < length) && (status == 0xB8));
+    
+    if ((status != 0xC0) && (status != 0xC8)) {
+        i2c_stop(obj);
+    }
+    
+    i2c_clear_SI(obj);
+    
+    return(count);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+    uint32_t addr;
+    
+    if ((idx >= 0) && (idx <= 3)) {
+        addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
+        *((uint32_t *) addr) = address & 0xFF;
+        addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
+        *((uint32_t *) addr) = mask & 0xFE;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/objects.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    uint32_t port;
+    uint32_t pin;
+    uint32_t ch;
+};
+
+struct port_s {
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_out;
+    __I  uint32_t *reg_in;
+    PortName port;
+    uint32_t mask;
+};
+
+struct pwmout_s {
+    __IO uint32_t *MR;
+    PWMName pwm;
+};
+
+struct serial_s {
+    LPC_UART_TypeDef *uart;
+    int index;
+};
+
+struct analogin_s {
+    ADCName adc;
+};
+
+struct dac_s {
+    DACName dac;
+};
+
+struct can_s {
+    LPC_CAN_TypeDef *dev;
+};
+
+struct i2c_s {
+    LPC_I2C_TypeDef *i2c;
+};
+
+struct spi_s {
+    LPC_SSP_TypeDef *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/pinmap.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "error.h"
+
+void pin_function(PinName pin, int function) {
+    if (pin == (uint32_t)NC) return;
+    
+    uint32_t pin_number = (uint32_t)pin - (uint32_t)P0_0;
+    int index = pin_number >> 4;
+    int offset = (pin_number & 0xF) << 1;
+    
+    PINCONARRAY->PINSEL[index] &= ~(0x3 << offset);
+    PINCONARRAY->PINSEL[index] |= function << offset;
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+    if (pin == (uint32_t)NC) { return; }
+    
+    uint32_t pin_number = (uint32_t)pin - (uint32_t)P0_0;
+    int index = pin_number >> 5;
+    int offset = pin_number & 0x1F;
+    uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2;
+    
+    PINCONARRAY->PINMODE_OD[index] &= ~(drain << offset);
+    PINCONARRAY->PINMODE_OD[index] |= drain << offset;
+    
+    if (!drain) {
+        index = pin_number >> 4;
+        offset = (pin_number & 0xF) << 1;
+        
+        PINCONARRAY->PINMODE[index] &= ~(0x3 << offset);
+        PINCONARRAY->PINMODE[index] |= (uint32_t)mode << offset;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/port_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+
+PinName port_pin(PortName port, int pin_n) {
+    return (PinName)(LPC_GPIO0_BASE + ((port << PORT_SHIFT) | pin_n));
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+    obj->port = port;
+    obj->mask = mask;
+    
+    LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *)(LPC_GPIO0_BASE + ((int)port * 0x20));
+    
+    // Do not use masking, because it prevents the use of the unmasked pins
+    // port_reg->FIOMASK = ~mask;
+    
+    obj->reg_out = &port_reg->FIOPIN;
+    obj->reg_in  = &port_reg->FIOPIN;
+    obj->reg_dir  = &port_reg->FIODIR;
+    
+    uint32_t i;
+    // The function is set per pin: reuse gpio logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            gpio_set(port_pin(obj->port, i));
+        }
+    }
+
+    port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+    uint32_t i;
+    // The mode is set per pin: reuse pinmap logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+    switch (dir) {
+        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
+    }
+}
+
+void port_write(port_t *obj, int value) {
+    *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj) {
+    return (*obj->reg_in & obj->mask);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/pwmout_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,172 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#define TCR_CNT_EN       0x00000001
+#define TCR_RESET        0x00000002
+
+//  PORT ID, PWM ID, Pin function
+static const PinMap PinMap_PWM[] = {
+    {P1_18, PWM_1, 2},
+    {P1_20, PWM_2, 2},
+    {P1_21, PWM_3, 2},
+    {P1_23, PWM_4, 2},
+    {P1_24, PWM_5, 2},
+    {P1_26, PWM_6, 2},
+    {P2_0 , PWM_1, 1},
+    {P2_1 , PWM_2, 1},
+    {P2_2 , PWM_3, 1},
+    {P2_3 , PWM_4, 1},
+    {P2_4 , PWM_5, 1},
+    {P2_5 , PWM_6, 1},
+    {P3_25, PWM_2, 3},
+    {P3_26, PWM_3, 3},
+    {NC, NC, 0}
+};
+
+__IO uint32_t *PWM_MATCH[] = {
+    &(LPC_PWM1->MR0),
+    &(LPC_PWM1->MR1),
+    &(LPC_PWM1->MR2),
+    &(LPC_PWM1->MR3),
+    &(LPC_PWM1->MR4),
+    &(LPC_PWM1->MR5),
+    &(LPC_PWM1->MR6)
+};
+
+#define TCR_PWM_EN       0x00000008
+
+static unsigned int pwm_clock_mhz;
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+    // determine the channel
+    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+    if (pwm == (uint32_t)NC)
+        error("PwmOut pin mapping failed");
+    
+    obj->pwm = pwm;
+    obj->MR = PWM_MATCH[pwm];
+    
+    // ensure the power is on
+    LPC_SC->PCONP |= 1 << 6;
+    
+    // ensure clock to /4
+    LPC_SC->PCLKSEL0 &= ~(0x3 << 12);     // pclk = /4
+    LPC_PWM1->PR = 0;                     // no pre-scale
+    
+    // ensure single PWM mode
+    LPC_PWM1->MCR = 1 << 1; // reset TC on match 0
+    
+    // enable the specific PWM output
+    LPC_PWM1->PCR |= 1 << (8 + pwm);
+    
+    pwm_clock_mhz = SystemCoreClock / 4000000;
+    
+    // default to 20ms: standard for servos, and fine for e.g. brightness control
+    pwmout_period_ms(obj, 20);
+    pwmout_write    (obj, 0);
+    
+    // Wire pinout
+    pinmap_pinout(pin, PinMap_PWM);
+}
+
+void pwmout_free(pwmout_t* obj) {
+    // [TODO]
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+    if (value < 0.0f) {
+        value = 0.0;
+    } else if (value > 1.0f) {
+        value = 1.0;
+    }
+    
+    // set channel match to percentage
+    uint32_t v = (uint32_t)((float)(LPC_PWM1->MR0) * value);
+    
+    // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
+    if (v == LPC_PWM1->MR0) {
+        v++;
+    }
+    
+    *obj->MR = v;
+    
+    // accept on next period start
+    LPC_PWM1->LER |= 1 << obj->pwm;
+}
+
+float pwmout_read(pwmout_t* obj) {
+    float v = (float)(*obj->MR) / (float)(LPC_PWM1->MR0);
+    return (v > 1.0f) ? (1.0f) : (v);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+    pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+    pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+    // calculate number of ticks
+    uint32_t ticks = pwm_clock_mhz * us;
+
+    // set reset
+    LPC_PWM1->TCR = TCR_RESET;
+
+    // set the global match register
+    LPC_PWM1->MR0 = ticks;
+
+    // Scale the pulse width to preserve the duty ratio
+    if (LPC_PWM1->MR0 > 0) {
+        *obj->MR = (*obj->MR * ticks) / LPC_PWM1->MR0;
+    }
+
+    // set the channel latch to update value at next period start
+    LPC_PWM1->LER |= 1 << 0;
+
+    // enable counter and pwm, clear reset
+    LPC_PWM1->TCR = TCR_CNT_EN | TCR_PWM_EN;
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+    // calculate number of ticks
+    uint32_t v = pwm_clock_mhz * us;
+    
+    // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
+    if (v == LPC_PWM1->MR0) {
+        v++;
+    }
+    
+    // set the match register value
+    *obj->MR = v;
+    
+    // set the channel latch to update value at next period start
+    LPC_PWM1->LER |= 1 << obj->pwm;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/rtc_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "rtc_api.h"
+
+// ensure rtc is running (unchanged if already running)
+
+/* Setup the RTC based on a time structure, ensuring RTC is enabled
+ *
+ * Can be clocked by a 32.768KHz oscillator or prescale divider based on the APB clock
+ * - We want to use the 32khz clock, allowing for sleep mode
+ *
+ * Most registers are not changed by a Reset
+ * - We must initialize these registers between power-on and setting the RTC into operation
+
+ * Clock Control Register
+ *  RTC_CCR[0] : Enable - 0 = Disabled, 1 = Enabled
+ *  RTC_CCR[1] : Reset - 0 = Normal, 1 = Reset
+ *  RTC_CCR[4] : Clock Source - 0 = Prescaler, 1 = 32k Xtal
+ *
+ * The RTC may already be running, so we should set it up
+ * without impacting if it is the case
+ */
+void rtc_init(void) {
+    LPC_SC->PCONP |= 0x200; // Ensure power is on
+    LPC_RTC->CCR = 0x00;
+    
+    LPC_RTC->CCR |= 1 << 0; // Ensure the RTC is enabled
+}
+
+void rtc_free(void) {
+    // [TODO]
+}
+
+/*
+ * Little check routine to see if the RTC has been enabled
+ *
+ * Clock Control Register
+ *  RTC_CCR[0] : 0 = Disabled, 1 = Enabled
+ *
+ */
+int rtc_isenabled(void) {
+    return(((LPC_RTC->CCR) & 0x01) != 0);
+}
+
+/*
+ * RTC Registers
+ *  RTC_SEC        Seconds 0-59
+ *  RTC_MIN        Minutes 0-59
+ *  RTC_HOUR    Hour 0-23
+ *  RTC_DOM        Day of Month 1-28..31
+ *  RTC_DOW        Day of Week 0-6
+ *  RTC_DOY        Day of Year 1-365
+ *  RTC_MONTH    Month 1-12
+ *  RTC_YEAR    Year 0-4095
+ *
+ * struct tm
+ *  tm_sec        seconds after the minute 0-61
+ *  tm_min        minutes after the hour 0-59
+ *  tm_hour        hours since midnight 0-23
+ *  tm_mday        day of the month 1-31
+ *  tm_mon        months since January 0-11
+ *  tm_year        years since 1900
+ *  tm_wday        days since Sunday 0-6
+ *  tm_yday        days since January 1 0-365
+ *  tm_isdst    Daylight Saving Time flag
+ */
+time_t rtc_read(void) {
+    // Setup a tm structure based on the RTC
+    struct tm timeinfo;
+    timeinfo.tm_sec = LPC_RTC->SEC;
+    timeinfo.tm_min = LPC_RTC->MIN;
+    timeinfo.tm_hour = LPC_RTC->HOUR;
+    timeinfo.tm_mday = LPC_RTC->DOM;
+    timeinfo.tm_mon = LPC_RTC->MONTH - 1;
+    timeinfo.tm_year = LPC_RTC->YEAR - 1900;
+    
+    // Convert to timestamp
+    time_t t = mktime(&timeinfo);
+    
+    return t;
+}
+
+void rtc_write(time_t t) {
+    // Convert the time in to a tm
+    struct tm *timeinfo = localtime(&t);
+    
+    // Pause clock, and clear counter register (clears us count)
+    LPC_RTC->CCR |= 2;
+    
+    // Set the RTC
+    LPC_RTC->SEC = timeinfo->tm_sec;
+    LPC_RTC->MIN = timeinfo->tm_min;
+    LPC_RTC->HOUR = timeinfo->tm_hour;
+    LPC_RTC->DOM = timeinfo->tm_mday;
+    LPC_RTC->MONTH = timeinfo->tm_mon + 1;
+    LPC_RTC->YEAR = timeinfo->tm_year + 1900;
+    
+    // Restart clock
+    LPC_RTC->CCR &= ~((uint32_t)2);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/serial_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,318 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include <string.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+#define UART_NUM    4
+
+static const PinMap PinMap_UART_TX[] = {
+    {P0_0,  UART_3, 2},
+    {P0_2,  UART_0, 1},
+    {P0_10, UART_2, 1},
+    {P0_15, UART_1, 1},
+    {P0_25, UART_3, 3},
+    {P2_0 , UART_1, 2},
+    {P2_8 , UART_2, 2},
+    {P4_28, UART_3, 3},
+    {NC   , NC    , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+    {P0_1 , UART_3, 2},
+    {P0_3 , UART_0, 1},
+    {P0_11, UART_2, 1},
+    {P0_16, UART_1, 1},
+    {P0_26, UART_3, 3},
+    {P2_1 , UART_1, 2},
+    {P2_9 , UART_2, 2},
+    {P4_29, UART_3, 3},
+    {NC   , NC    , 0}
+};
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+    int is_stdio_uart = 0;
+    
+    // determine the UART to use
+    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+    UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    if ((int)uart == NC) {
+        error("Serial pinout mapping failed");
+    }
+    
+    obj->uart = (LPC_UART_TypeDef *)uart;
+    // enable power
+    switch (uart) {
+        case UART_0: LPC_SC->PCONP |= 1 <<  3; break;
+        case UART_1: LPC_SC->PCONP |= 1 <<  4; break;
+        case UART_2: LPC_SC->PCONP |= 1 << 24; break;
+        case UART_3: LPC_SC->PCONP |= 1 << 25; break;
+    }
+    
+    // enable fifos and default rx trigger level
+    obj->uart->FCR = 1 << 0  // FIFO Enable - 0 = Disables, 1 = Enabled
+                   | 0 << 1  // Rx Fifo Reset
+                   | 0 << 2  // Tx Fifo Reset
+                   | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
+
+    // disable irqs
+    obj->uart->IER = 0 << 0  // Rx Data available irq enable
+                   | 0 << 1  // Tx Fifo empty irq enable
+                   | 0 << 2; // Rx Line Status irq enable
+    
+    // set default baud rate and format
+    serial_baud  (obj, 9600);
+    serial_format(obj, 8, ParityNone, 1);
+    
+    // pinout the chosen uart
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+    
+    // set rx/tx pins in PullUp mode
+    pin_mode(tx, PullUp);
+    pin_mode(rx, PullUp);
+    
+    switch (uart) {
+        case UART_0: obj->index = 0; break;
+        case UART_1: obj->index = 1; break;
+        case UART_2: obj->index = 2; break;
+        case UART_3: obj->index = 3; break;
+    }
+    
+    is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+    
+    if (is_stdio_uart) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj) {
+    serial_irq_ids[obj->index] = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+    // The LPC2300 and LPC1700 have a divider and a fractional divider to control the
+    // baud rate. The formula is:
+    //
+    // Baudrate = (1 / PCLK) * 16 * DL * (1 + DivAddVal / MulVal)
+    //   where:
+    //     1 < MulVal <= 15
+    //     0 <= DivAddVal < 14
+    //     DivAddVal < MulVal
+    //
+    // set pclk to /1
+    switch ((int)obj->uart) {
+        case UART_0: LPC_SC->PCLKSEL0 &= ~(0x3 <<  6); LPC_SC->PCLKSEL0 |= (0x1 <<  6); break;
+        case UART_1: LPC_SC->PCLKSEL0 &= ~(0x3 <<  8); LPC_SC->PCLKSEL0 |= (0x1 <<  8); break;
+        case UART_2: LPC_SC->PCLKSEL1 &= ~(0x3 << 16); LPC_SC->PCLKSEL1 |= (0x1 << 16); break;
+        case UART_3: LPC_SC->PCLKSEL1 &= ~(0x3 << 18); LPC_SC->PCLKSEL1 |= (0x1 << 18); break;
+        default: error("serial_baud"); break;
+    }
+    
+    uint32_t PCLK = SystemCoreClock;
+    
+    // First we check to see if the basic divide with no DivAddVal/MulVal
+    // ratio gives us an integer result. If it does, we set DivAddVal = 0,
+    // MulVal = 1. Otherwise, we search the valid ratio value range to find
+    // the closest match. This could be more elegant, using search methods
+    // and/or lookup tables, but the brute force method is not that much
+    // slower, and is more maintainable.
+    uint16_t DL = PCLK / (16 * baudrate);
+
+    uint8_t DivAddVal = 0;
+    uint8_t MulVal = 1;
+    int hit = 0;
+    uint16_t dlv;
+    uint8_t mv, dav;
+    if ((PCLK % (16 * baudrate)) != 0) {     // Checking for zero remainder
+        float err_best = (float) baudrate;
+        uint16_t dlmax = DL;
+        for ( dlv = (dlmax/2); (dlv <= dlmax) && !hit; dlv++) {
+            for ( mv = 1; mv <= 15; mv++) {
+                for ( dav = 1; dav < mv; dav++) {
+                    float ratio = 1.0f + ((float) dav / (float) mv);
+                    float calcbaud = (float)PCLK / (16.0f * (float) dlv * ratio);
+                    float err = fabs(((float) baudrate - calcbaud) / (float) baudrate);
+                    if (err < err_best) {
+                        DL = dlv;
+                        DivAddVal = dav;
+                        MulVal = mv;
+                        err_best = err;
+                        if (err < 0.001f) {
+                            hit = 1;
+                        }
+                    }
+                }
+            }
+        }
+    }
+    
+    // set LCR[DLAB] to enable writing to divider registers
+    obj->uart->LCR |= (1 << 7);
+    
+    // set divider values
+    obj->uart->DLM = (DL >> 8) & 0xFF;
+    obj->uart->DLL = (DL >> 0) & 0xFF;
+    obj->uart->FDR = (uint32_t) DivAddVal << 0
+                   | (uint32_t) MulVal    << 4;
+    
+    // clear LCR[DLAB]
+    obj->uart->LCR &= ~(1 << 7);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+    // 0: 1 stop bits, 1: 2 stop bits
+    if (stop_bits != 1 && stop_bits != 2) {
+        error("Invalid stop bits specified");
+    }
+    stop_bits -= 1;
+    
+    // 0: 5 data bits ... 3: 8 data bits
+    if (data_bits < 5 || data_bits > 8) {
+        error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
+    }
+    data_bits -= 5;
+
+    int parity_enable, parity_select;
+    switch (parity) {
+        case ParityNone: parity_enable = 0; parity_select = 0; break;
+        case ParityOdd : parity_enable = 1; parity_select = 0; break;
+        case ParityEven: parity_enable = 1; parity_select = 1; break;
+        case ParityForced1: parity_enable = 1; parity_select = 2; break;
+        case ParityForced0: parity_enable = 1; parity_select = 3; break;
+        default:
+            error("Invalid serial parity setting");
+            return;
+    }
+    
+    obj->uart->LCR = data_bits            << 0
+                   | stop_bits            << 2
+                   | parity_enable        << 3
+                   | parity_select        << 4;
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t iir, uint32_t index) {
+    // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
+    SerialIrq irq_type;
+    switch (iir) {
+        case 1: irq_type = TxIrq; break;
+        case 2: irq_type = RxIrq; break;
+        default: return;
+    }
+    
+    if (serial_irq_ids[index] != 0)
+        irq_handler(serial_irq_ids[index], irq_type);
+}
+
+void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0);}
+void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);}
+void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2);}
+void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;
+    switch ((int)obj->uart) {
+        case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
+        case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
+        case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
+        case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
+    }
+    
+    if (enable) {
+        obj->uart->IER |= 1 << irq;
+        NVIC_SetVector(irq_n, vector);
+        NVIC_EnableIRQ(irq_n);
+    } else { // disable
+        int all_disabled = 0;
+        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+        obj->uart->IER &= ~(1 << irq);
+        all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
+        if (all_disabled)
+            NVIC_DisableIRQ(irq_n);
+    }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+    while (!serial_readable(obj));
+    return obj->uart->RBR;
+}
+
+void serial_putc(serial_t *obj, int c) {
+    while (!serial_writable(obj));
+    obj->uart->THR = c;
+    
+    uint32_t lsr = obj->uart->LSR;
+    lsr = lsr;
+    uint32_t thr = obj->uart->THR;
+    thr = thr;
+}
+
+int serial_readable(serial_t *obj) {
+    return obj->uart->LSR & 0x01;
+}
+
+int serial_writable(serial_t *obj) {
+    return obj->uart->LSR & 0x20;
+}
+
+void serial_clear(serial_t *obj) {
+    obj->uart->FCR = 1 << 1  // rx FIFO reset
+                   | 1 << 2  // tx FIFO reset
+                   | 0 << 6; // interrupt depth
+}
+
+void serial_pinout_tx(PinName tx) {
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+    obj->uart->LCR |= (1 << 6);
+}
+
+void serial_break_clear(serial_t *obj) {
+    obj->uart->LCR &= ~(1 << 6);
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/sleep.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+
+void sleep(void) {
+    // ensure debug is disconnected
+    mbed_interface_disconnect();
+    
+    // PCON[PD] set to sleep
+    LPC_SC->PCON = 0x0;
+    
+    // SRC[SLEEPDEEP] set to 0 = sleep
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    
+    // wait for interrupt
+    __WFI();
+}
+
+/*
+* The mbed lpc1768 does not support the deepsleep mode
+* as a debugger is connected to it (the mbed interface).
+*
+* As mentionned in an application note from NXP:
+*
+*       http://www.po-star.com/public/uploads/20120319123122_141.pdf
+*
+*       {{{
+*       The user should be aware of certain limitations during debugging.
+*       The most important is that, due to limitations of the Cortex-M3
+*       integration, the LPC17xx cannot wake up in the usual manner from
+*       Deep Sleep and Power-down modes. It is recommended not to use these
+*       modes during debug. Once an application is downloaded via JTAG/SWD
+*       interface, the USB to SWD/JTAG debug adapter (Keil ULINK2 for example)
+*       should be removed from the target board, and thereafter, power cycle
+*       the LPC17xx to allow wake-up from deep sleep and power-down modes
+*       }}}
+*
+*       As the interface firmware does not reset the target when a
+*       mbed_interface_disconnect() semihosting call is made, the
+*       core cannot wake-up from deepsleep.
+*
+*       We treat a deepsleep() as a normal sleep().
+*/
+
+void deepsleep(void) {
+    // ensure debug is disconnected
+    mbed_interface_disconnect();
+    
+    // PCON[PD] set to deepsleep
+    sleep();
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/spi_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,222 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_SPI_SCLK[] = {
+    {P0_7 , SPI_1, 2},
+    {P0_15, SPI_0, 2},
+    {P1_20, SPI_0, 3},
+    {P1_31, SPI_1, 2},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+    {P0_9 , SPI_1, 2},
+    {P0_13, SPI_1, 2},
+    {P0_18, SPI_0, 2},
+    {P1_24, SPI_0, 3},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+    {P0_8 , SPI_1, 2},
+    {P0_12, SPI_1, 2},
+    {P0_17, SPI_0, 2},
+    {P1_23, SPI_0, 3},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+    {P0_6 , SPI_1, 2},
+    {P0_11, SPI_1, 2},
+    {P0_16, SPI_0, 2},
+    {P1_21, SPI_0, 3},
+    {NC   , NC   , 0}
+};
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    // determine the SPI to use
+    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+    obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
+    if ((int)obj->spi == NC) {
+        error("SPI pinout mapping failed");
+    }
+    
+    // enable power and clocking
+    switch ((int)obj->spi) {
+        case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
+        case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
+    }
+    
+    // set default format and frequency
+    if (ssel == NC) {
+        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
+    } else {
+        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
+    }
+    spi_frequency(obj, 1000000);
+    
+    // enable the ssp channel
+    ssp_enable(obj);
+
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+    ssp_disable(obj);
+    if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
+        error("SPI format error");
+    }
+    
+    int polarity = (mode & 0x2) ? 1 : 0;
+    int phase = (mode & 0x1) ? 1 : 0;
+    
+    // set it up
+    int DSS = bits - 1;            // DSS (data select size)
+    int SPO = (polarity) ? 1 : 0;  // SPO - clock out polarity
+    int SPH = (phase) ? 1 : 0;     // SPH - clock out phase
+    
+    int FRF = 0;                   // FRF (frame format) = SPI
+    uint32_t tmp = obj->spi->CR0;
+    tmp &= ~(0xFFFF);
+    tmp |= DSS << 0
+        | FRF << 4
+        | SPO << 6
+        | SPH << 7;
+    obj->spi->CR0 = tmp;
+    
+    tmp = obj->spi->CR1;
+    tmp &= ~(0xD);
+    tmp |= 0 << 0                   // LBM - loop back mode - off
+        | ((slave) ? 1 : 0) << 2   // MS - master slave mode, 1 = slave
+        | 0 << 3;                  // SOD - slave output disable - na
+    obj->spi->CR1 = tmp;
+    
+    ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+    ssp_disable(obj);
+    
+    // setup the spi clock diveder to /1
+    switch ((int)obj->spi) {
+        case SPI_0:
+            LPC_SC->PCLKSEL1 &= ~(3 << 10);
+            LPC_SC->PCLKSEL1 |=  (1 << 10);
+            break;
+        case SPI_1:
+            LPC_SC->PCLKSEL0 &= ~(3 << 20);
+            LPC_SC->PCLKSEL0 |=  (1 << 20);
+            break;
+    }
+    
+    uint32_t PCLK = SystemCoreClock;
+    
+    int prescaler;
+    
+    for (prescaler = 2; prescaler <= 254; prescaler += 2) {
+        int prescale_hz = PCLK / prescaler;
+        
+        // calculate the divider
+        int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
+        
+        // check we can support the divider
+        if (divider < 256) {
+            // prescaler
+            obj->spi->CPSR = prescaler;
+            
+            // divider
+            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 |= (divider - 1) << 8;
+            ssp_enable(obj);
+            return;
+        }
+    }
+    error("Couldn't setup requested SPI frequency");
+}
+
+static inline int ssp_disable(spi_t *obj) {
+    return obj->spi->CR1 &= ~(1 << 1);
+}
+
+static inline int ssp_enable(spi_t *obj) {
+    return obj->spi->CR1 |= (1 << 1);
+}
+
+static inline int ssp_readable(spi_t *obj) {
+    return obj->spi->SR & (1 << 2);
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+    return obj->spi->SR & (1 << 1);
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+    while (!ssp_writeable(obj));
+    obj->spi->DR = value;
+}
+
+static inline int ssp_read(spi_t *obj) {
+    while (!ssp_readable(obj));
+    return obj->spi->DR;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+    return (obj->spi->SR & (1 << 4)) ? (1) : (0);
+}
+
+int spi_master_write(spi_t *obj, int value) {
+    ssp_write(obj, value);
+    return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+    return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+};
+
+int spi_slave_read(spi_t *obj) {
+    return obj->spi->DR;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+    while (ssp_writeable(obj) == 0) ;
+    obj->spi->DR = value;
+}
+
+int spi_busy(spi_t *obj) {
+    return ssp_busy(obj);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC176X/us_ticker.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+#define US_TICKER_TIMER      ((LPC_TIM_TypeDef *)LPC_TIM3_BASE)
+#define US_TICKER_TIMER_IRQn TIMER3_IRQn
+
+int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+    if (us_ticker_inited) return;
+    us_ticker_inited = 1;
+    
+    LPC_SC->PCONP |= 1 << 23; // Clock TIMER_3
+    
+    US_TICKER_TIMER->CTCR = 0x0; // timer mode
+    uint32_t PCLK = SystemCoreClock / 4;
+    
+    US_TICKER_TIMER->TCR = 0x2;  // reset
+    
+    uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks)
+    US_TICKER_TIMER->PR = prescale - 1;
+    US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0
+    
+    NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+uint32_t us_ticker_read() {
+    if (!us_ticker_inited)
+        us_ticker_init();
+    
+    return US_TICKER_TIMER->TC;
+}
+
+void us_ticker_set_interrupt(unsigned int timestamp) {
+    // set match value
+    US_TICKER_TIMER->MR0 = timestamp;
+    // enable match interrupt
+    US_TICKER_TIMER->MCR |= 1;
+}
+
+void us_ticker_disable_interrupt(void) {
+    US_TICKER_TIMER->MCR &= ~1;
+}
+
+void us_ticker_clear_interrupt(void) {
+    US_TICKER_TIMER->IR = 1;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/PeripheralNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    UART_0 = (int)LPC_UART0_BASE,
+    UART_1 = (int)LPC_UART1_BASE,
+    UART_2 = (int)LPC_UART2_BASE,
+    UART_3 = (int)LPC_UART3_BASE
+} UARTName;
+
+typedef enum {
+    ADC0_0 = 0,
+    ADC0_1,
+    ADC0_2,
+    ADC0_3,
+    ADC0_4,
+    ADC0_5,
+    ADC0_6,
+    ADC0_7
+} ADCName;
+
+typedef enum {
+    DAC_0 = 0
+} DACName;
+
+typedef enum {
+    SPI_0 = (int)LPC_SSP0_BASE,
+    SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+    I2C_0 = (int)LPC_I2C0_BASE,
+    I2C_1 = (int)LPC_I2C1_BASE,
+    I2C_2 = (int)LPC_I2C2_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1 = 1,
+    PWM_2,
+    PWM_3,
+    PWM_4,
+    PWM_5,
+    PWM_6
+} PWMName;
+
+typedef enum {
+     CAN_1 = (int)LPC_CAN1_BASE,
+     CAN_2 = (int)LPC_CAN2_BASE
+} CANName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/PinNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  5
+
+typedef enum {
+    // LPC Pin Names
+    P0_0 = LPC_GPIO0_BASE,
+          P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
+    P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
+    P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
+    P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
+    P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
+
+    // mbed DIP Pin Names
+    p5 = P0_9,
+    p6 = P0_8,
+    p7 = P0_7,
+    p8 = P0_6,
+    p9 = P0_0,
+    p10 = P0_1,
+    p11 = P0_18,
+    p12 = P0_17,
+    p13 = P0_15,
+    p14 = P0_16,
+    p15 = P0_23,
+    p16 = P0_24,
+    p17 = P0_25,
+    p18 = P0_26,
+    p19 = P1_30,
+    p20 = P1_31,
+    p21 = P2_5,
+    p22 = P2_4,
+    p23 = P2_3,
+    p24 = P2_2,
+    p25 = P2_1,
+    p26 = P2_0,
+    p27 = P0_11,
+    p28 = P0_10,
+    p29 = P0_5,
+    p30 = P0_4,
+
+    // Other mbed Pin Names
+    LED1 = P1_18,
+    LED2 = P1_20,
+    LED3 = P1_21,
+    LED4 = P1_23,
+
+    USBTX = P0_2,
+    USBRX = P0_3,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullUp = 0,
+    PullDown = 3,
+    PullNone = 2,
+    OpenDrain = 4
+} PinMode;
+
+// version of PINCON_TypeDef using register arrays
+typedef struct {
+  __IO uint32_t PINSEL[11];
+       uint32_t RESERVED0[5];
+  __IO uint32_t PINMODE[10];
+} PINCONARRAY_TypeDef;
+
+#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/PortNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,34 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0,
+    Port1 = 1,
+    Port2 = 2,
+    Port3 = 3,
+    Port4 = 4
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/analogin_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,125 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogin_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#define ANALOGIN_MEDIAN_FILTER      1
+
+#define ADC_10BIT_RANGE             0x3FF
+#define ADC_12BIT_RANGE             0xFFF
+
+static inline int div_round_up(int x, int y) {
+  return (x + (y - 1)) / y;
+}
+
+static const PinMap PinMap_ADC[] = {
+    {P0_23, ADC0_0, 1},
+    {P0_24, ADC0_1, 1},
+    {P0_25, ADC0_2, 1},
+    {P0_26, ADC0_3, 1},
+    {P1_30, ADC0_4, 3},
+    {P1_31, ADC0_5, 3},
+    {NC,    NC,     0}
+};
+
+#define ADC_RANGE    ADC_10BIT_RANGE
+
+
+void analogin_init(analogin_t *obj, PinName pin) {
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    if (obj->adc == (uint32_t)NC) {
+        error("ADC pin mapping failed");
+    }
+    
+    // ensure power is turned on
+    LPC_SC->PCONP |= (1 << 12);
+    
+    // set PCLK of ADC to /1
+    LPC_SC->PCLKSEL0 &= ~(0x3 << 24);
+    LPC_SC->PCLKSEL0 |= (0x1 << 24);
+    uint32_t PCLK = SystemCoreClock;
+    
+    // calculate minimum clock divider
+    //  clkdiv = divider - 1
+    uint32_t MAX_ADC_CLK = 13000000;
+    uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
+    
+    // Set the generic software-controlled ADC settings
+    LPC_ADC->ADCR = (0 << 0)      // SEL: 0 = no channels selected
+                  | (clkdiv << 8) // CLKDIV: PCLK max ~= 25MHz, /25 to give safe 1MHz at fastest
+                  | (0 << 16)     // BURST: 0 = software control
+                  | (0 << 17)     // CLKS: not applicable
+                  | (1 << 21)     // PDN: 1 = operational
+                  | (0 << 24)     // START: 0 = no start
+                  | (0 << 27);    // EDGE: not applicable
+    
+    pinmap_pinout(pin, PinMap_ADC);
+}
+
+static inline uint32_t adc_read(analogin_t *obj) {
+    // Select the appropriate channel and start conversion
+    LPC_ADC->ADCR &= ~0xFF;
+    LPC_ADC->ADCR |= 1 << (int)obj->adc;
+    LPC_ADC->ADCR |= 1 << 24;
+    
+    // Repeatedly get the sample data until DONE bit
+    unsigned int data;
+    do {
+        data = LPC_ADC->ADGDR;
+    } while ((data & ((unsigned int)1 << 31)) == 0);
+    
+    // Stop conversion
+    LPC_ADC->ADCR &= ~(1 << 24);
+    
+    return (data >> 6) & ADC_RANGE; // 10 bit
+}
+
+static inline void order(uint32_t *a, uint32_t *b) {
+    if (*a > *b) {
+        uint32_t t = *a;
+        *a = *b;
+        *b = t;
+    }
+}
+
+static inline uint32_t adc_read_u32(analogin_t *obj) {
+    uint32_t value;
+#if ANALOGIN_MEDIAN_FILTER
+    uint32_t v1 = adc_read(obj);
+    uint32_t v2 = adc_read(obj);
+    uint32_t v3 = adc_read(obj);
+    order(&v1, &v2);
+    order(&v2, &v3);
+    order(&v1, &v2);
+    value = v2;
+#else
+    value = adc_read(obj);
+#endif
+    return value;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+    
+    return (value << 6) | ((value >> 4) & 0x003F); // 10 bit
+}
+
+float analogin_read(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+    return (float)value * (1.0f / (float)ADC_RANGE);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/analogout_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_DAC[] = {
+    {P0_26, DAC_0, 2},
+    {NC   , NC   , 0}
+};
+
+void analogout_init(dac_t *obj, PinName pin) {
+    obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
+    if (obj->dac == (uint32_t)NC) {
+        error("DAC pin mapping failed");
+    }
+    
+    // power is on by default, set DAC clk divider is /4
+    LPC_SC->PCLKSEL0 &= ~(0x3 << 22);
+    
+    // map out (must be done before accessing registers)
+    pinmap_pinout(pin, PinMap_DAC);
+    
+    analogout_write_u16(obj, 0);
+}
+
+void analogout_free(dac_t *obj) {}
+
+static inline void dac_write(int value) {
+    value &= 0x3FF; // 10-bit
+    
+    // Set the DAC output
+    LPC_DAC->DACR = (0 << 16)       // bias = 0
+                  | (value << 6);
+}
+
+static inline int dac_read() {
+    return (LPC_DAC->DACR >> 6) & 0x3FF;
+}
+
+void analogout_write(dac_t *obj, float value) {
+    if (value < 0.0f) {
+        dac_write(0);
+    } else if (value > 1.0f) {
+        dac_write(0x3FF);
+    } else {
+        dac_write(value * (float)0x3FF);
+    }
+}
+
+void analogout_write_u16(dac_t *obj, uint16_t value) {
+    dac_write(value >> 6); // 10-bit
+}
+
+float analogout_read(dac_t *obj) {
+    uint32_t value = dac_read();
+    return (float)value * (1.0f / (float)0x3FF);
+}
+
+uint16_t analogout_read_u16(dac_t *obj) {
+    uint32_t value = dac_read(); // 10-bit
+    return (value << 6) | ((value >> 4) & 0x003F);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/can_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,297 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "can_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#include <math.h>
+#include <string.h>
+
+/* Acceptance filter mode in AFMR register */
+#define ACCF_OFF                0x01
+#define ACCF_BYPASS             0x02
+#define ACCF_ON                 0x00
+#define ACCF_FULLCAN            0x04
+
+/* There are several bit timing calculators on the internet.
+http://www.port.de/engl/canprod/sv_req_form.html
+http://www.kvaser.com/can/index.htm
+*/
+
+static const PinMap PinMap_CAN_RD[] = {
+    {P0_0 , CAN_1, 1},
+    {P0_4 , CAN_2, 2},
+    {P0_21, CAN_1, 3},
+    {P2_7 , CAN_2, 1},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_CAN_TD[] = {
+    {P0_1 , CAN_1, 1},
+    {P0_5 , CAN_2, 2},
+    {P0_22, CAN_1, 3},
+    {P2_8 , CAN_2, 1},
+    {NC   , NC   , 0}
+};
+
+// Type definition to hold a CAN message
+struct CANMsg {
+    unsigned int  reserved1 : 16;
+    unsigned int  dlc       :  4; // Bits 16..19: DLC - Data Length Counter
+    unsigned int  reserved0 : 10;
+    unsigned int  rtr       :  1; // Bit 30: Set if this is a RTR message
+    unsigned int  type      :  1; // Bit 31: Set if this is a 29-bit ID message
+    unsigned int  id;             // CAN Message ID (11-bit or 29-bit)
+    unsigned char data[8];        // CAN Message Data Bytes 0-7
+};
+typedef struct CANMsg CANMsg;
+
+static uint32_t can_disable(can_t *obj) {
+    uint32_t sm = obj->dev->MOD;
+    obj->dev->MOD |= 1;
+    return sm;
+}
+
+static inline void can_enable(can_t *obj) {
+    if (obj->dev->MOD & 1) {
+        obj->dev->MOD &= ~(1);
+    }
+}
+
+static int can_pclk(can_t *obj) {
+    int value = 0;
+    switch ((int)obj->dev) {
+        case CAN_1: value = (LPC_SC->PCLKSEL0 & (0x3 << 26)) >> 26; break;
+        case CAN_2: value = (LPC_SC->PCLKSEL0 & (0x3 << 28)) >> 28; break;
+    }
+    
+    switch (value) {
+        case 1: return 1;
+        case 2: return 2;
+        case 3: return 6;
+        default: return 4;
+    }
+}
+
+// This table has the sampling points as close to 75% as possible. The first
+// value is TSEG1, the second TSEG2.
+static const int timing_pts[23][2] = {
+    {0x0, 0x0},      // 2,  50%
+    {0x1, 0x0},      // 3,  67%
+    {0x2, 0x0},      // 4,  75%
+    {0x3, 0x0},      // 5,  80%
+    {0x3, 0x1},      // 6,  67%
+    {0x4, 0x1},      // 7,  71%
+    {0x5, 0x1},      // 8,  75%
+    {0x6, 0x1},      // 9,  78%
+    {0x6, 0x2},      // 10, 70%
+    {0x7, 0x2},      // 11, 73%
+    {0x8, 0x2},      // 12, 75%
+    {0x9, 0x2},      // 13, 77%
+    {0x9, 0x3},      // 14, 71%
+    {0xA, 0x3},      // 15, 73%
+    {0xB, 0x3},      // 16, 75%
+    {0xC, 0x3},      // 17, 76%
+    {0xD, 0x3},      // 18, 78%
+    {0xD, 0x4},      // 19, 74%
+    {0xE, 0x4},      // 20, 75%
+    {0xF, 0x4},      // 21, 76%
+    {0xF, 0x5},      // 22, 73%
+    {0xF, 0x6},      // 23, 70%
+    {0xF, 0x7},      // 24, 67%
+};
+
+static unsigned int can_speed(unsigned int sclk, unsigned int pclk, unsigned int cclk, unsigned char psjw) {
+    uint32_t    btr;
+    uint16_t    brp = 0;
+    uint32_t    calcbit;
+    uint32_t    bitwidth;
+    int         hit = 0;
+    int         bits;
+    
+    bitwidth = sclk / (pclk * cclk);
+    
+    brp = bitwidth / 0x18;
+    while ((!hit) && (brp < bitwidth / 4)) {
+        brp++;
+        for (bits = 22; bits > 0; bits--) {
+            calcbit = (bits + 3) * (brp + 1);
+            if (calcbit == bitwidth) {
+                hit = 1;
+                break;
+            }
+        }
+    }
+    
+    if (hit) {
+        btr = ((timing_pts[bits][1] << 20) & 0x00700000)
+            | ((timing_pts[bits][0] << 16) & 0x000F0000)
+            | ((psjw                << 14) & 0x0000C000)
+            | ((brp                 <<  0) & 0x000003FF);
+    } else {
+        btr = 0xFFFFFFFF;
+    }
+    
+    return btr;
+}
+
+void can_init(can_t *obj, PinName rd, PinName td) {
+    CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
+    CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+    obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
+    if ((int)obj->dev == NC) {
+        error("CAN pin mapping failed");
+    }
+    
+    switch ((int)obj->dev) {
+        case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
+        case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
+    }
+    
+    pinmap_pinout(rd, PinMap_CAN_RD);
+    pinmap_pinout(td, PinMap_CAN_TD);
+    
+    can_reset(obj);
+    obj->dev->IER = 0;             // Disable Interrupts
+    can_frequency(obj, 100000);
+    
+    LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
+}
+
+void can_free(can_t *obj) {
+    switch ((int)obj->dev) {
+        case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
+        case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
+    }
+}
+
+int can_frequency(can_t *obj, int f) {
+    int pclk = can_pclk(obj);
+    int btr = can_speed(SystemCoreClock, pclk, (unsigned int)f, 1);
+    
+    if (btr > 0) {
+        uint32_t modmask = can_disable(obj);
+        obj->dev->BTR = btr;
+        obj->dev->MOD = modmask;
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc) {
+    unsigned int CANStatus;
+    CANMsg m;
+    
+    can_enable(obj);
+    
+    m.id   = msg.id ;
+    m.dlc  = msg.len & 0xF;
+    m.rtr  = msg.type;
+    m.type = msg.format;
+    memcpy(m.data, msg.data, msg.len);
+    const unsigned int *buf = (const unsigned int *)&m;
+    
+    CANStatus = obj->dev->SR;
+    if (CANStatus & 0x00000004) {
+        obj->dev->TFI1 = buf[0] & 0xC00F0000;
+        obj->dev->TID1 = buf[1];
+        obj->dev->TDA1 = buf[2];
+        obj->dev->TDB1 = buf[3];
+        if (cc) {
+            obj->dev->CMR = 0x30;
+        } else {
+            obj->dev->CMR = 0x21;
+        }
+        return 1;
+    
+    } else if (CANStatus & 0x00000400) {
+        obj->dev->TFI2 = buf[0] & 0xC00F0000;
+        obj->dev->TID2 = buf[1];
+        obj->dev->TDA2 = buf[2];
+        obj->dev->TDB2 = buf[3];
+        if (cc) {
+            obj->dev->CMR = 0x50;
+        } else {
+            obj->dev->CMR = 0x41;
+        }
+        return 1;
+    
+    } else if (CANStatus & 0x00040000) {
+        obj->dev->TFI3 = buf[0] & 0xC00F0000;
+        obj->dev->TID3 = buf[1];
+        obj->dev->TDA3 = buf[2];
+        obj->dev->TDB3 = buf[3];
+        if (cc) {
+            obj->dev->CMR = 0x90;
+        } else {
+            obj->dev->CMR = 0x81;
+        }
+        return 1;
+    }
+    
+    return 0;
+}
+
+int can_read(can_t *obj, CAN_Message *msg) {
+    CANMsg x;
+    unsigned int *i = (unsigned int *)&x;
+    
+    can_enable(obj);
+    
+    if (obj->dev->GSR & 0x1) {
+        *i++ = obj->dev->RFS;  // Frame
+        *i++ = obj->dev->RID;  // ID
+        *i++ = obj->dev->RDA;  // Data A
+        *i++ = obj->dev->RDB;  // Data B
+        obj->dev->CMR = 0x04;  // release receive buffer
+        
+        msg->id     = x.id;
+        msg->len    = x.dlc;
+        msg->format = (x.type)? CANExtended : CANStandard;
+        msg->type   = (x.rtr)?  CANRemote:    CANData;
+        memcpy(msg->data,x.data,x.dlc);
+        return 1;
+    }
+    
+    return 0;
+}
+
+void can_reset(can_t *obj) {
+    can_disable(obj);
+    obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
+}
+
+unsigned char can_rderror(can_t *obj) {
+    return (obj->dev->GSR >> 16) & 0xFF;
+}
+
+unsigned char can_tderror(can_t *obj) {
+    return (obj->dev->GSR >> 24) & 0xFF;
+}
+
+void can_monitor(can_t *obj, int silent) {
+    uint32_t mod_mask = can_disable(obj);
+    if (silent) {
+        obj->dev->MOD |= (1 << 1);
+    } else {
+        obj->dev->MOD &= ~(1 << 1);
+    }
+    if (!(mod_mask & 1)) {
+        can_enable(obj);
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/device.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        1
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         1
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         1
+
+#define DEVICE_CAN              1
+
+#define DEVICE_RTC              1
+
+#define DEVICE_ETHERNET         1
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_SEMIHOST         1
+#define DEVICE_LOCALFILESYSTEM  1
+#define DEVICE_ID_LENGTH       32
+#define DEVICE_MAC_OFFSET      20
+
+#define DEVICE_SLEEP            0
+
+#define DEVICE_DEBUG_AWARENESS  0
+
+#define DEVICE_STDIO_MESSAGES   1
+
+#define DEVICE_ERROR_PATTERN    1
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/ethernet_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,935 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+
+#include "ethernet_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "toolchain.h"
+#include "error.h"
+
+#define NEW_LOGIC       0
+#define NEW_ETH_BUFFER  0
+
+#if NEW_ETH_BUFFER
+
+#define NUM_RX_FRAG         4           // Number of Rx Fragments (== packets)
+#define NUM_TX_FRAG         3           // Number of Tx Fragments (== packets)
+
+#define ETH_MAX_FLEN        1536         // Maximum Ethernet Frame Size
+#define ETH_FRAG_SIZE       ETH_MAX_FLEN // Packet Fragment size (same as packet length)
+
+#else
+
+// Memfree calculation:
+// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
+//                (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
+#define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */
+#define NUM_TX_FRAG         3           /* Num.of TX Fragments 3*1536= 4.6kB */
+//#define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
+
+//#define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
+#define ETH_FRAG_SIZE       0x300       /* Packet Fragment size 1536/2 Bytes   */
+#define ETH_MAX_FLEN        0x300       /* Max. Ethernet Frame Size          */
+
+const int ethernet_MTU_SIZE  = 0x300;
+
+#endif
+
+#define ETHERNET_ADDR_SIZE 6
+
+PACKED struct RX_DESC_TypeDef {                        /* RX Descriptor struct              */
+   unsigned int Packet;
+   unsigned int Ctrl;
+};
+typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
+
+PACKED struct RX_STAT_TypeDef {                        /* RX Status struct                  */
+   unsigned int Info;
+   unsigned int HashCRC;
+};
+typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
+
+PACKED struct TX_DESC_TypeDef {                        /* TX Descriptor struct              */
+   unsigned int Packet;
+   unsigned int Ctrl;
+};
+typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
+
+PACKED struct TX_STAT_TypeDef {                        /* TX Status struct                  */
+   unsigned int Info;
+};
+typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
+
+/* MAC Configuration Register 1 */
+#define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
+#define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
+#define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
+#define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
+#define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
+#define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
+#define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
+#define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
+#define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
+#define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
+#define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
+
+/* MAC Configuration Register 2 */
+#define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
+#define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
+#define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
+#define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
+#define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
+#define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
+#define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
+#define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
+#define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
+#define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
+#define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
+#define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
+#define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
+
+/* Back-to-Back Inter-Packet-Gap Register */
+#define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
+#define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
+
+/* Non Back-to-Back Inter-Packet-Gap Register */
+#define IPGR_DEF            0x00000012  /* Recommended value                 */
+
+/* Collision Window/Retry Register */
+#define CLRT_DEF            0x0000370F  /* Default value                     */
+
+/* PHY Support Register */
+#define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
+//#define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */
+#define SUPP_RES_RMII       0x00000000  /* Reset Reduced MII Logic           */
+
+/* Test Register */
+#define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
+#define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
+#define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
+
+/* MII Management Configuration Register */
+#define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
+#define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
+#define MCFG_CLK_SEL        0x0000003C  /* Clock Select Mask                 */
+#define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
+
+/* MII Management Command Register */
+#define MCMD_READ           0x00000001  /* MII Read                          */
+#define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
+
+#define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
+#define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
+
+/* MII Management Address Register */
+#define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
+#define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
+
+/* MII Management Indicators Register */
+#define MIND_BUSY           0x00000001  /* MII is Busy                       */
+#define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
+#define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
+#define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
+
+/* Command Register */
+#define CR_RX_EN            0x00000001  /* Enable Receive                    */
+#define CR_TX_EN            0x00000002  /* Enable Transmit                   */
+#define CR_REG_RES          0x00000008  /* Reset Host Registers              */
+#define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
+#define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
+#define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
+#define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
+#define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
+#define CR_RMII             0x00000200  /* Reduced MII Interface             */
+#define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
+
+/* Status Register */
+#define SR_RX_EN            0x00000001  /* Enable Receive                    */
+#define SR_TX_EN            0x00000002  /* Enable Transmit                   */
+
+/* Transmit Status Vector 0 Register */
+#define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
+#define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
+#define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
+#define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
+#define TSV0_MCAST          0x00000010  /* Multicast Destination             */
+#define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
+#define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
+#define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
+#define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
+#define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
+#define TSV0_GIANT          0x00000400  /* Giant Frame                       */
+#define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
+#define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
+#define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
+#define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
+#define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
+#define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
+
+/* Transmit Status Vector 1 Register */
+#define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
+#define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
+
+/* Receive Status Vector Register */
+#define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
+#define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
+#define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
+#define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
+#define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
+#define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
+#define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
+#define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
+#define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
+#define RSV_MCAST           0x01000000  /* Multicast Frame                   */
+#define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
+#define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
+#define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
+#define RSV_PAUSE           0x10000000  /* Pause Frame                       */
+#define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
+#define RSV_VLAN            0x40000000  /* VLAN Frame                        */
+
+/* Flow Control Counter Register */
+#define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
+#define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
+
+/* Flow Control Status Register */
+#define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
+
+/* Receive Filter Control Register */
+#define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
+#define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
+#define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
+#define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
+#define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
+#define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
+#define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
+#define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
+
+/* Receive Filter WoL Status/Clear Registers */
+#define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
+#define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
+#define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
+#define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
+#define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
+#define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
+#define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
+#define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
+
+/* Interrupt Status/Enable/Clear/Set Registers */
+#define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
+#define INT_RX_ERR          0x00000002  /* Receive Error                     */
+#define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
+#define INT_RX_DONE         0x00000008  /* Receive Done                      */
+#define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
+#define INT_TX_ERR          0x00000020  /* Transmit Error                    */
+#define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
+#define INT_TX_DONE         0x00000080  /* Transmit Done                     */
+#define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
+#define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
+
+/* Power Down Register */
+#define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
+
+/* RX Descriptor Control Word */
+#define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
+#define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
+
+/* RX Status Hash CRC Word */
+#define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
+#define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
+
+/* RX Status Information Word */
+#define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
+#define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
+#define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
+#define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
+#define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
+#define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
+#define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
+#define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
+#define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
+#define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
+#define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
+#define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
+#define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
+#define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
+#define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
+
+//#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
+                            RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+
+
+/* TX Descriptor Control Word */
+#define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
+#define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
+#define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
+#define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
+#define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
+#define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
+#define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
+
+/* TX Status Information Word */
+#define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
+#define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
+#define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
+#define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
+#define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
+#define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
+#define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
+#define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
+
+/* ENET Device Revision ID */
+#define OLD_EMAC_MODULE_ID  0x39022000  /* Rev. ID for first rev '-'         */
+
+/* DP83848C PHY Registers */
+#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
+#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
+#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
+#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
+#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
+#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
+#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
+#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
+
+/* PHY Extended Registers */
+#define PHY_REG_STS         0x10        /* Status Register                   */
+#define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */
+#define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */
+#define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */
+#define PHY_REG_RECR        0x15        /* Receive Error Counter             */
+#define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */
+#define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */
+#define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */
+#define PHY_REG_PHYCR       0x19        /* PHY Control Register              */
+#define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */
+#define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */
+#define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */
+
+#define PHY_REG_SCSR        0x1F        /* PHY Special Control/Status Register */
+
+#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
+#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
+#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
+#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
+#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */
+
+#define DP83848C_DEF_ADR    0x0100      /* Default PHY device address        */
+#define DP83848C_ID         0x20005C90  /* PHY Identifier - DP83848C         */
+
+#define LAN8720_ID          0x0007C0F0  /* PHY Identifier - LAN8720          */
+
+#define PHY_STS_LINK        0x0001      /* PHY Status Link Mask              */
+#define PHY_STS_SPEED       0x0002      /* PHY Status Speed Mask             */
+#define PHY_STS_DUPLEX      0x0004      /* PHY Status Duplex Mask            */
+
+#define PHY_BMCR_RESET      0x8000      /* PHY Reset                         */
+
+#define PHY_BMSR_LINK       0x0004      /* PHY BMSR Link valid               */
+
+#define PHY_SCSR_100MBIT    0x0008      /* Speed: 1=100 MBit, 0=10Mbit       */
+#define PHY_SCSR_DUPLEX     0x0010      /* PHY Duplex Mask                   */
+
+
+static int phy_read(unsigned int PhyReg);
+static int phy_write(unsigned int PhyReg, unsigned short Data);
+
+static void txdscr_init(void);
+static void rxdscr_init(void);
+
+#if defined (__ICCARM__)
+#   define AHBSRAM1
+#elif defined(TOOLCHAIN_GCC_CR)
+#   define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
+#else
+#   define AHBSRAM1     __attribute__((section("AHBSRAM1"),aligned))
+#endif
+
+AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
+AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
+AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
+AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
+AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
+
+
+#if NEW_LOGIC
+static int rx_consume_offset = -1;
+static int tx_produce_offset = -1;
+#else
+static int send_doff =  0;
+static int send_idx  = -1;
+static int send_size =  0;
+
+static int receive_soff =  0;
+static int receive_idx  = -1;
+#endif
+
+static uint32_t phy_id = 0;
+
+static inline int rinc(int idx, int mod) {
+  ++idx;
+  idx %= mod;
+  return idx;
+}
+
+//extern unsigned int SystemFrequency;
+static inline unsigned int clockselect() {
+  if(SystemCoreClock < 10000000) {
+    return 1;
+  } else if(SystemCoreClock <  15000000) {
+    return 2;
+  } else if(SystemCoreClock <  20000000) {
+    return 3;
+  } else if(SystemCoreClock <  25000000) {
+    return 4;
+  } else if(SystemCoreClock <  35000000) {
+    return 5;
+  } else if(SystemCoreClock <  50000000) {
+    return 6;
+  } else if(SystemCoreClock <  70000000) {
+    return 7;
+  } else if(SystemCoreClock <  80000000) {
+    return 8;
+  } else if(SystemCoreClock <  90000000) {
+    return 9;
+  } else if(SystemCoreClock < 100000000) {
+    return 10;
+  } else if(SystemCoreClock < 120000000) {
+    return 11;
+  } else if(SystemCoreClock < 130000000) {
+    return 12;
+  } else if(SystemCoreClock < 140000000) {
+    return 13;
+  } else if(SystemCoreClock < 150000000) {
+    return 15;
+  } else if(SystemCoreClock < 160000000) {
+    return 16;
+  } else {
+    return 0;
+  }
+}
+
+#ifndef min
+#define min(x, y) (((x)<(y))?(x):(y))
+#endif
+
+/*----------------------------------------------------------------------------
+  Ethernet Device initialize
+ *----------------------------------------------------------------------------*/
+int ethernet_init() {
+  int regv, tout;
+  char mac[ETHERNET_ADDR_SIZE];
+  unsigned int clock = clockselect();
+  
+  LPC_SC->PCONP |= 0x40000000;                       /* Power Up the EMAC controller. */
+  
+  LPC_PINCON->PINSEL2 = 0x50150105;                  /* Enable P1 Ethernet Pins. */
+  LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
+  
+   /* Reset all EMAC internal modules. */
+  LPC_EMAC->MAC1    = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
+                      MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
+  LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
+
+  for(tout = 100; tout; tout--) __NOP();             /* A short delay after reset. */
+
+  LPC_EMAC->MAC1 = MAC1_PASS_ALL;                    /* Initialize MAC control registers. */
+  LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+  LPC_EMAC->MAXF = ETH_MAX_FLEN;
+  LPC_EMAC->CLRT = CLRT_DEF;
+  LPC_EMAC->IPGR = IPGR_DEF;
+
+  LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;    /* Enable Reduced MII interface. */
+
+  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;    /* Set clock */
+  LPC_EMAC->MCFG |= MCFG_RES_MII;                    /* and reset */
+
+  for(tout = 100; tout; tout--) __NOP();             /* A short delay */
+
+  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
+  LPC_EMAC->MCMD = 0;
+
+  LPC_EMAC->SUPP = SUPP_RES_RMII;                    /* Reset Reduced MII Logic. */
+
+  for (tout = 100; tout; tout--) __NOP();            /* A short delay */
+
+  LPC_EMAC->SUPP = 0;
+
+  phy_write(PHY_REG_BMCR, PHY_BMCR_RESET);           /* perform PHY reset */
+  for(tout = 0x20000; ; tout--) {                    /* Wait for hardware reset to end. */
+    regv = phy_read(PHY_REG_BMCR);
+    if(regv < 0 || tout == 0) {
+       return -1;                                    /* Error */
+    }
+    if(!(regv & PHY_BMCR_RESET)) {
+       break;                                        /* Reset complete. */
+    }
+  }
+
+  phy_id =  (phy_read(PHY_REG_IDR1) << 16);
+  phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
+
+  if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
+      error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
+  }
+
+  ethernet_set_link(-1, 0);
+
+  /* Set the Ethernet MAC Address registers */
+  ethernet_address(mac);
+  LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
+  LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
+  LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
+
+  txdscr_init();                                      /* initialize DMA TX Descriptor */
+  rxdscr_init();                                      /* initialize DMA RX Descriptor */
+
+  LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
+                                                      /* Receive Broadcast, Perfect Match Packets */
+
+  LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;    /* Enable EMAC interrupts. */
+  LPC_EMAC->IntClear  = 0xFFFF;                       /* Reset all interrupts */
+
+
+  LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);        /* Enable receive and transmit mode of MAC Ethernet core */
+  LPC_EMAC->MAC1     |= MAC1_REC_EN;
+
+#if NEW_LOGIC
+  rx_consume_offset = -1;
+  tx_produce_offset = -1;
+#else
+  send_doff =  0;
+  send_idx  = -1;
+  send_size =  0;
+
+  receive_soff =  0;
+  receive_idx  = -1;
+#endif
+
+  return 0;
+}
+
+/*----------------------------------------------------------------------------
+  Ethernet Device Uninitialize
+ *----------------------------------------------------------------------------*/
+void ethernet_free() {
+  LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
+  LPC_EMAC->IntClear   =  0xFFFF;
+  
+  LPC_SC->PCONP   &= ~0x40000000;       /* Power down the EMAC controller. */
+  
+  LPC_PINCON->PINSEL2 &= ~0x50150105;   /* Disable P1 ethernet pins. */
+  LPC_PINCON->PINSEL3  = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000000;
+}
+
+// if(TxProduceIndex == TxConsumeIndex) buffer array is empty
+// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
+// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
+// TxConsumeIndex - The buffer that will/is beign sent by hardware
+
+int ethernet_write(const char *data, int slen) {
+
+#if NEW_LOGIC
+
+   if(tx_produce_offset < 0) { // mark as active if not already
+     tx_produce_offset = 0;
+   }
+
+   int index = LPC_EMAC->TxProduceIndex;
+
+   int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
+   int requested = slen;
+   int ncopy = min(remaining, requested);
+
+   void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
+   void *psrc = (void *)(data);
+
+   if(ncopy > 0 ){
+     if(data != NULL) {
+       memcpy(pdst, psrc, ncopy);
+     } else {
+       memset(pdst, 0, ncopy);
+     }
+   }
+
+   tx_produce_offset += ncopy;
+
+   return ncopy;
+
+#else
+    void       *pdst, *psrc;
+    const int   dlen = ETH_FRAG_SIZE;
+    int         copy = 0;
+    int         soff = 0;
+
+    if(send_idx == -1) {
+        send_idx = LPC_EMAC->TxProduceIndex;
+    }
+
+    if(slen + send_doff > ethernet_MTU_SIZE) {
+       return -1;
+    }
+
+    do {
+        copy = min(slen - soff, dlen - send_doff);
+        pdst = (void *)(txdesc[send_idx].Packet + send_doff);
+        psrc = (void *)(data + soff);
+        if(send_doff + copy > ETH_FRAG_SIZE) {
+            txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
+            send_idx = rinc(send_idx, NUM_TX_FRAG);
+            send_doff = 0;
+        }
+
+        if(data != NULL) {
+            memcpy(pdst, psrc, copy);
+        } else {
+            memset(pdst, 0, copy);
+        }
+
+        soff += copy;
+        send_doff += copy;
+        send_size += copy;
+    } while(soff != slen);
+
+    return soff;
+#endif
+}
+
+int ethernet_send() {
+
+#if NEW_LOGIC
+  if(tx_produce_offset < 0) { // no buffer active
+    return -1;
+  }
+
+  // ensure there is a link
+  if(!ethernet_link()) {
+    return -2;
+  }
+
+  // we have been writing in to a buffer, so finalise it
+  int size = tx_produce_offset;
+  int index = LPC_EMAC->TxProduceIndex;
+  txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
+
+  // Increment ProduceIndex to allow it to be sent
+  // We can only do this if the next slot is free
+  int next = rinc(index, NUM_TX_FRAG);
+  while(next == LPC_EMAC->TxConsumeIndex) {
+    for(int i=0; i<1000; i++) { __NOP(); }
+  }
+
+  LPC_EMAC->TxProduceIndex = next;
+  tx_produce_offset = -1;
+  return size;
+
+#else
+    int s = send_size;
+    txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
+    send_idx  = rinc(send_idx, NUM_TX_FRAG);
+    LPC_EMAC->TxProduceIndex = send_idx;
+    send_doff =  0;
+    send_idx  = -1;
+    send_size =  0;
+    return s;
+#endif
+}
+
+// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
+// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
+//
+// if(RxConsumeIndex == RxProduceIndex) buffer array is empty
+// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
+
+// Recevies an arrived ethernet packet.
+// Receiving an ethernet packet will drop the last received ethernet packet
+// and make a new ethernet packet ready to read.
+// Returns size of packet, else 0 if nothing to receive
+
+// We read from RxConsumeIndex from position rx_consume_offset
+// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
+// rx_consume_offset = -1 // no frame
+// rx_consume_offset = 0  // start of frame
+// Assumption: A fragment should alway be a whole frame
+
+int ethernet_receive() {
+#if NEW_LOGIC
+
+  // if we are currently reading a valid RxConsume buffer, increment to the next one
+  if(rx_consume_offset >= 0) {
+    LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
+  }
+
+  // if the buffer is empty, mark it as no valid buffer
+  if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
+    rx_consume_offset = -1;
+    return 0;
+  }
+
+  uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
+  rx_consume_offset = 0;
+
+  // check if it is not marked as last or for errors
+  if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
+    return -1;
+  }
+
+  int size = (info & RINFO_SIZE) + 1;
+  return size - 4; // don't include checksum bytes
+
+#else
+    if(receive_idx == -1) {
+      receive_idx = LPC_EMAC->RxConsumeIndex;
+    } else {
+        while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && (receive_idx != LPC_EMAC->RxProduceIndex)) {
+            receive_idx  = rinc(receive_idx, NUM_RX_FRAG);
+        }
+        unsigned int info =   rxstat[receive_idx].Info;
+        int slen =  (info & RINFO_SIZE) + 1;
+
+        if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
+            /* Invalid frame, ignore it and free buffer. */
+            receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+        }
+        receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+        receive_soff = 0;
+        
+        LPC_EMAC->RxConsumeIndex = receive_idx;
+    }
+    
+    if(receive_idx == LPC_EMAC->RxProduceIndex) {
+        receive_idx = -1;
+        return 0;
+    }
+    
+    return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
+#endif
+}
+
+// Read from an recevied ethernet packet.
+// After receive returnd a number bigger than 0 it is
+// possible to read bytes from this packet.
+// Read will write up to size bytes into data.
+// It is possible to use read multible times.
+// Each time read will start reading after the last read byte before.
+
+int ethernet_read(char *data, int dlen) {
+#if NEW_LOGIC
+  // Check we have a valid buffer to read
+  if(rx_consume_offset < 0) {
+    return 0;
+  }
+
+  // Assume 1 fragment block
+  uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
+  int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
+
+  int remaining = size - rx_consume_offset;
+  int requested = dlen;
+  int ncopy = min(remaining, requested);
+
+  void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
+  void *pdst = (void *)(data);
+
+  if(data != NULL && ncopy > 0) {
+    memcpy(pdst, psrc, ncopy);
+  }
+
+  rx_consume_offset += ncopy;
+
+  return ncopy;
+#else
+    int          slen;
+    int          copy   = 0;
+    unsigned int more;
+    unsigned int info;
+    void        *pdst, *psrc;
+    int          doff = 0;
+    
+    if(receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
+        return 0;
+    }
+    
+    do {
+        info =   rxstat[receive_idx].Info;
+        more = !(info & RINFO_LAST_FLAG);
+        slen =  (info & RINFO_SIZE) + 1;
+        
+        if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
+            /* Invalid frame, ignore it and free buffer. */
+            receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+        } else {
+            
+            copy = min(slen - receive_soff, dlen - doff);
+            psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
+            pdst = (void *)(data + doff);
+            
+            if(data != NULL) {
+                /* check if Buffer available */
+                memcpy(pdst, psrc, copy);
+            }
+            
+            receive_soff += copy;
+            doff += copy;
+            
+            if((more && (receive_soff == slen))) {
+                receive_idx = rinc(receive_idx, NUM_RX_FRAG);
+                receive_soff = 0;
+            }
+        }
+    } while(more && !(doff == dlen) && !receive_soff);
+    
+    return doff;
+#endif
+}
+
+int ethernet_link(void) {
+    if (phy_id == DP83848C_ID) {
+      return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
+    }
+    else { // LAN8720_ID
+      return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
+    }
+}
+
+static int phy_write(unsigned int PhyReg, unsigned short Data) {
+    unsigned int timeOut;
+    
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MWTD = Data;
+    
+    for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) {     /* Wait until operation completed */
+        if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+            return 0;
+        }
+    }
+    
+    return -1;
+}
+
+static int phy_read(unsigned int PhyReg) {
+    unsigned int timeOut;
+    
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MCMD = MCMD_READ;
+    
+    for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) {     /* Wait until operation completed */
+        if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+            LPC_EMAC->MCMD = 0;
+            return LPC_EMAC->MRDD;                           /* Return a 16-bit value. */
+        }
+    }
+    
+    return -1;
+}
+
+
+static void txdscr_init() {
+    int i;
+    
+    for(i = 0; i < NUM_TX_FRAG; i++) {
+        txdesc[i].Packet = (uint32_t)&txbuf[i];
+        txdesc[i].Ctrl   = 0;
+        txstat[i].Info   = 0;
+    }
+    
+    LPC_EMAC->TxDescriptor       = (uint32_t)txdesc;         /* Set EMAC Transmit Descriptor Registers. */
+    LPC_EMAC->TxStatus           = (uint32_t)txstat;
+    LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
+    
+    LPC_EMAC->TxProduceIndex  = 0;                           /* Tx Descriptors Point to 0 */
+}
+
+static void rxdscr_init() {
+    int i;
+    
+    for(i = 0; i < NUM_RX_FRAG; i++) {
+        rxdesc[i].Packet  = (uint32_t)&rxbuf[i];
+        rxdesc[i].Ctrl    = RCTRL_INT | (ETH_FRAG_SIZE-1);
+        rxstat[i].Info    = 0;
+        rxstat[i].HashCRC = 0;
+    }
+    
+    LPC_EMAC->RxDescriptor       = (uint32_t)rxdesc;        /* Set EMAC Receive Descriptor Registers. */
+    LPC_EMAC->RxStatus           = (uint32_t)rxstat;
+    LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
+    
+    LPC_EMAC->RxConsumeIndex  = 0;                          /* Rx Descriptors Point to 0 */
+}
+
+void ethernet_address(char *mac) {
+    mbed_mac_address(mac);
+}
+
+void ethernet_set_link(int speed, int duplex) {
+    unsigned short phy_data;
+    int tout;
+    
+    if((speed < 0) || (speed > 1)) {
+        phy_data = PHY_AUTO_NEG;
+    } else {
+        phy_data = (((unsigned short) speed << 13) |
+                    ((unsigned short) duplex << 8));
+    }
+    
+    phy_write(PHY_REG_BMCR, phy_data);
+    
+    for(tout = 100; tout; tout--) { __NOP(); }     /* A short delay */
+    
+    switch(phy_id) {
+        case DP83848C_ID:
+            phy_data = phy_read(PHY_REG_STS);
+            
+            if(phy_data & PHY_STS_DUPLEX) {
+                LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
+                LPC_EMAC->Command |= CR_FULL_DUP;
+                LPC_EMAC->IPGT = IPGT_FULL_DUP;
+            } else {
+            LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
+                LPC_EMAC->Command &= ~CR_FULL_DUP;
+                LPC_EMAC->IPGT = IPGT_HALF_DUP;
+            }
+            
+            if(phy_data & PHY_STS_SPEED) {
+                LPC_EMAC->SUPP &= ~SUPP_SPEED;
+            } else {
+                LPC_EMAC->SUPP |= SUPP_SPEED;
+            }
+            break;
+        
+        case LAN8720_ID:
+            phy_data = phy_read(PHY_REG_SCSR);
+            
+            if (phy_data & PHY_SCSR_DUPLEX) {
+                LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
+                LPC_EMAC->Command |= CR_FULL_DUP;
+                LPC_EMAC->IPGT = IPGT_FULL_DUP;
+            } else {
+                LPC_EMAC->Command &= ~CR_FULL_DUP;
+                LPC_EMAC->IPGT = IPGT_HALF_DUP;
+            }
+            
+            if(phy_data & PHY_SCSR_100MBIT) {
+                LPC_EMAC->SUPP |= SUPP_SPEED;
+            } else {
+                LPC_EMAC->SUPP &= ~SUPP_SPEED;
+            }
+            break;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+
+uint32_t gpio_set(PinName pin) {
+    LPC_SC->SCS |= 1; // High speed GPIO is enabled on ports 0 and 1
+    
+    pin_function(pin, 0);
+    
+    return (1 << ((int)pin & 0x1F));
+}
+
+void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
+    if (pin == NC) return;
+    
+    obj->pin = pin;
+    obj->mask = gpio_set(pin);
+    
+    LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *) ((int)pin & ~0x1F);
+    
+    obj->reg_set = &port_reg->FIOSET;
+    obj->reg_clr = &port_reg->FIOCLR;
+    obj->reg_in  = &port_reg->FIOPIN;
+    obj->reg_dir = &port_reg->FIODIR;
+    
+    gpio_dir(obj, direction);
+    switch (direction) {
+        case PIN_OUTPUT: pin_mode(pin, PullNone); break;
+        case PIN_INPUT : pin_mode(pin, PullDown); break;
+    }
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+    pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+    switch (direction) {
+        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_irq_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,145 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_irq_api.h"
+#include "error.h"
+#include <stddef.h>
+#include "cmsis.h"
+
+#define CHANNEL_NUM     48
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+
+static void handle_interrupt_in(void) {
+    // Read in all current interrupt registers. We do this once as the
+    // GPIO interrupt registers are on the APB bus, and this is slow.
+    uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
+    uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
+    uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
+    uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
+    uint32_t mask0 = 0;
+    uint32_t mask2 = 0;
+    int i;
+    
+    // P0.0-0.31
+    for (i = 0; i < 32; i++) {
+        uint32_t pmask = (1 << i);
+        if (rise0 & pmask) {
+            mask0 |= pmask;
+            if (channel_ids[i] != 0)
+                irq_handler(channel_ids[i], IRQ_RISE);
+        }
+        if (fall0 & pmask) {
+            mask0 |= pmask;
+            if (channel_ids[i] != 0)
+                irq_handler(channel_ids[i], IRQ_FALL);
+        }
+    }
+    
+    // P2.0-2.15
+    for (i = 0; i < 16; i++) {
+        uint32_t pmask = (1 << i);
+        int channel_index = i + 32;
+        if (rise2 & pmask) {
+            mask2 |= pmask;
+            if (channel_ids[channel_index] != 0)
+                irq_handler(channel_ids[channel_index], IRQ_RISE);
+        }
+        if (fall2 & pmask) {
+            mask2 |= pmask;
+            if (channel_ids[channel_index] != 0)
+                irq_handler(channel_ids[channel_index], IRQ_FALL);
+        }
+    }
+    
+    // Clear the interrupts we just handled
+    LPC_GPIOINT->IO0IntClr = mask0;
+    LPC_GPIOINT->IO2IntClr = mask2;
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+    if (pin == NC) return -1;
+    
+    irq_handler = handler;
+    
+    obj->port = (int)pin & ~0x1F;
+    obj->pin = (int)pin & 0x1F;
+    
+    // Interrupts available only on GPIO0 and GPIO2
+    if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
+        error("pins on this port cannot generate interrupts\n");
+    }
+    
+    // put us in the interrupt table
+    int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
+    channel_ids[index] = id;
+    obj->ch = index;
+    
+    NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
+    NVIC_EnableIRQ(EINT3_IRQn);
+    
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+    channel_ids[obj->ch] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+    // ensure nothing is pending
+    switch (obj->port) {
+         case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
+         case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
+    }
+    
+    // enable the pin interrupt
+    if (event == IRQ_RISE) {
+        switch (obj->port) {
+            case LPC_GPIO0_BASE:
+                if (enable) {
+                    LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
+                } else {
+                    LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
+                }
+                break;
+            case LPC_GPIO2_BASE:
+                if (enable) {
+                    LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
+                } else {
+                    LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
+                }
+                break;
+        }
+    } else {
+        switch (obj->port) {
+            case LPC_GPIO0_BASE:
+                if (enable) {
+                    LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
+                } else {
+                    LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
+                }
+                break;
+            
+            case LPC_GPIO2_BASE:
+                if (enable) {
+                    LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
+                } else {
+                    LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
+                }
+                break;
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_object.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName  pin;
+    uint32_t mask;
+
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_set;
+    __IO uint32_t *reg_clr;
+    __I  uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+    if (value)
+        *obj->reg_set = obj->mask;
+    else
+        *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/i2c_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,397 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_I2C_SDA[] = {
+    {P0_0 , I2C_1, 3},
+    {P0_10, I2C_2, 2},
+    {P0_19, I2C_1, 3},
+    {P0_27, I2C_0, 1},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+    {P0_1 , I2C_1, 3},
+    {P0_11, I2C_2, 2},
+    {P0_20, I2C_1, 3},
+    {P0_28, I2C_0, 1},
+    {NC   , NC,    0}
+};
+
+#define I2C_CONSET(x)       (x->i2c->I2CONSET)
+#define I2C_CONCLR(x)       (x->i2c->I2CONCLR)
+#define I2C_STAT(x)         (x->i2c->I2STAT)
+#define I2C_DAT(x)          (x->i2c->I2DAT)
+#define I2C_SCLL(x, val)    (x->i2c->I2SCLL = val)
+#define I2C_SCLH(x, val)    (x->i2c->I2SCLH = val)
+
+static const uint32_t I2C_addr_offset[2][4] = {
+    {0x0C, 0x20, 0x24, 0x28},
+    {0x30, 0x34, 0x38, 0x3C}
+};
+
+static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+    I2C_CONCLR(obj) = (start << 5)
+                    | (stop << 4)
+                    | (interrupt << 3)
+                    | (acknowledge << 2);
+}
+
+static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
+    I2C_CONSET(obj) = (start << 5)
+                    | (stop << 4)
+                    | (interrupt << 3)
+                    | (acknowledge << 2);
+}
+
+// Clear the Serial Interrupt (SI)
+static inline void i2c_clear_SI(i2c_t *obj) {
+    i2c_conclr(obj, 0, 0, 1, 0);
+}
+
+static inline int i2c_status(i2c_t *obj) {
+    return I2C_STAT(obj);
+}
+
+// Wait until the Serial Interrupt (SI) is set
+static int i2c_wait_SI(i2c_t *obj) {
+    int timeout = 0;
+    while (!(I2C_CONSET(obj) & (1 << 3))) {
+        timeout++;
+        if (timeout > 100000) return -1;
+    }
+    return 0;
+}
+
+static inline void i2c_interface_enable(i2c_t *obj) {
+    I2C_CONSET(obj) = 0x40;
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+    switch ((int)obj->i2c) {
+        case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
+        case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
+        case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
+    }
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+    // determine the SPI to use
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+    obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
+    
+    if ((int)obj->i2c == NC) {
+        error("I2C pin mapping failed");
+    }
+    
+    // enable power
+    i2c_power_enable(obj);
+    
+    // set default frequency at 100k
+    i2c_frequency(obj, 100000);
+    i2c_conclr(obj, 1, 1, 1, 1);
+    i2c_interface_enable(obj);
+    
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+}
+
+inline int i2c_start(i2c_t *obj) {
+    int status = 0;
+    // 8.1 Before master mode can be entered, I2CON must be initialised to:
+    //  - I2EN STA STO SI AA - -
+    //  -  1    0   0   0  x - -
+    // if AA = 0, it can't enter slave mode
+    i2c_conclr(obj, 1, 1, 1, 1);
+    
+    // The master mode may now be entered by setting the STA bit
+    // this will generate a start condition when the bus becomes free
+    i2c_conset(obj, 1, 0, 0, 1);
+    
+    i2c_wait_SI(obj);
+    status = i2c_status(obj);
+    
+    // Clear start bit now transmitted, and interrupt bit
+    i2c_conclr(obj, 1, 0, 0, 0);
+    return status;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+    int timeout = 0;
+
+    // write the stop bit
+    i2c_conset(obj, 0, 1, 0, 0);
+    i2c_clear_SI(obj);
+    
+    // wait for STO bit to reset
+    while (I2C_CONSET(obj) & (1 << 4)) {
+        timeout ++;
+        if (timeout > 100000) return 1;
+    }
+
+    return 0;
+}
+
+static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
+    // write the data
+    I2C_DAT(obj) = value;
+    
+    // clear SI to init a send
+    i2c_clear_SI(obj);
+    
+    // wait and return status
+    i2c_wait_SI(obj);
+    return i2c_status(obj);
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+    // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
+    if (last) {
+        i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
+    } else {
+        i2c_conset(obj, 0, 0, 0, 1); // send a ACK
+    }
+    
+    // accept byte
+    i2c_clear_SI(obj);
+    
+    // wait for it to arrive
+    i2c_wait_SI(obj);
+    
+    // return the data
+    return (I2C_DAT(obj) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+    // [TODO] set pclk to /4
+    uint32_t PCLK = SystemCoreClock / 4;
+    
+    uint32_t pulse = PCLK / (hz * 2);
+    
+    // I2C Rate
+    I2C_SCLL(obj, pulse);
+    I2C_SCLH(obj, pulse);
+}
+
+// The I2C does a read or a write as a whole operation
+// There are two types of error conditions it can encounter
+//  1) it can not obtain the bus
+//  2) it gets error responses at part of the transmission
+//
+// We tackle them as follows:
+//  1) we retry until we get the bus. we could have a "timeout" if we can not get it
+//      which basically turns it in to a 2)
+//  2) on error, we use the standard error mechanisms to report/debug
+//
+// Therefore an I2C transaction should always complete. If it doesn't it is usually
+// because something is setup wrong (e.g. wiring), and we don't need to programatically
+// check for that
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+    int count, status;
+    
+    status = i2c_start(obj);
+    
+    if ((status != 0x10) && (status != 0x08)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+    
+    status = i2c_do_write(obj, (address | 0x01), 1);
+    if (status != 0x40) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    
+    // Read in all except last byte
+    for (count = 0; count < (length - 1); count++) {
+        int value = i2c_do_read(obj, 0);
+        status = i2c_status(obj);
+        if (status != 0x50) {
+            i2c_stop(obj);
+            return count;
+        }
+        data[count] = (char) value;
+    }
+    
+    // read in last byte
+    int value = i2c_do_read(obj, 1);
+    status = i2c_status(obj);
+    if (status != 0x58) {
+        i2c_stop(obj);
+        return length - 1;
+    }
+    
+    data[count] = (char) value;
+    
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+    
+    return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+    int i, status;
+    
+    status = i2c_start(obj);
+    
+    if ((status != 0x10) && (status != 0x08)) {
+        i2c_stop(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+    
+    status = i2c_do_write(obj, (address & 0xFE), 1);
+    if (status != 0x18) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    
+    for (i=0; i<length; i++) {
+        status = i2c_do_write(obj, data[i], 0);
+        if (status != 0x28) {
+            i2c_stop(obj);
+            return i;
+        }
+    }
+    
+    // clearing the serial interrupt here might cause an unintended rewrite of the last byte
+    // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
+    // i2c_clear_SI(obj);
+    
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    }
+    
+    return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+    i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+    return (i2c_do_read(obj, last) & 0xFF);
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+    int ack;
+    int status = i2c_do_write(obj, (data & 0xFF), 0);
+    
+    switch(status) {
+        case 0x18: case 0x28:       // Master transmit ACKs
+            ack = 1;
+            break;
+        
+        case 0x40:                  // Master receive address transmitted ACK
+            ack = 1;
+            break;
+        
+        case 0xB8:                  // Slave transmit ACK
+            ack = 1;
+            break;
+        
+        default:
+            ack = 0;
+            break;
+    }
+    
+    return ack;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+    if (enable_slave != 0) {
+        i2c_conclr(obj, 1, 1, 1, 0);
+        i2c_conset(obj, 0, 0, 0, 1);
+    } else {
+        i2c_conclr(obj, 1, 1, 1, 1);
+    }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+    int status;
+    int retval;
+    
+    status = i2c_status(obj);
+    switch(status) {
+        case 0x60: retval = 3; break;
+        case 0x70: retval = 2; break;
+        case 0xA8: retval = 1; break;
+        default  : retval = 0; break;
+    }
+    
+    return(retval);
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+    int count = 0;
+    int status;
+    
+    do {
+        i2c_clear_SI(obj);
+        i2c_wait_SI(obj);
+        status = i2c_status(obj);
+        if((status == 0x80) || (status == 0x90)) {
+            data[count] = I2C_DAT(obj) & 0xFF;
+        }
+        count++;
+    } while (((status == 0x80) || (status == 0x90) ||
+            (status == 0x060) || (status == 0x70)) && (count < length));
+    
+    if(status != 0xA0) {
+        i2c_stop(obj);
+    }
+    
+    i2c_clear_SI(obj);
+    
+    return count;
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+    int count = 0;
+    int status;
+    
+    if(length <= 0) {
+        return(0);
+    }
+    
+    do {
+        status = i2c_do_write(obj, data[count], 0);
+        count++;
+    } while ((count < length) && (status == 0xB8));
+    
+    if((status != 0xC0) && (status != 0xC8)) {
+        i2c_stop(obj);
+    }
+    
+    i2c_clear_SI(obj);
+    
+    return(count);
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+    uint32_t addr;
+    
+    if ((idx >= 0) && (idx <= 3)) {
+        addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
+        *((uint32_t *) addr) = address & 0xFF;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/objects.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    uint32_t port;
+    uint32_t pin;
+    uint32_t ch;
+};
+
+struct port_s {
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_out;
+    __I  uint32_t *reg_in;
+    PortName port;
+    uint32_t mask;
+};
+
+struct pwmout_s {
+    __IO uint32_t *MR;
+    PWMName pwm;
+};
+
+struct serial_s {
+    LPC_UART_TypeDef *uart;
+    int index;
+};
+
+struct analogin_s {
+    ADCName adc;
+};
+
+struct dac_s {
+    DACName dac;
+};
+
+struct can_s {
+    LPC_CAN_TypeDef *dev;
+};
+
+struct i2c_s {
+    LPC_I2C_TypeDef *i2c;
+};
+
+struct spi_s {
+    LPC_SSP_TypeDef *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/pinmap.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "error.h"
+
+void pin_function(PinName pin, int function) {
+    if (pin == (uint32_t)NC) return;
+    
+    uint32_t pin_number = (uint32_t)pin - (uint32_t)P0_0;
+    int index = pin_number >> 4;
+    int offset = (pin_number & 0xF) << 1;
+    
+    PINCONARRAY->PINSEL[index] &= ~(0x3 << offset);
+    PINCONARRAY->PINSEL[index] |= function << offset;
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+    if (pin == (uint32_t)NC) { return; }
+    
+    uint32_t pin_number = (uint32_t)pin - (uint32_t)P0_0;
+    int index = pin_number >> 5;
+    int offset = pin_number & 0x1F;
+    uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2;
+    
+    if (mode == OpenDrain) error("OpenDrain not supported on LPC2368");
+    
+    if (!drain) {
+        index = pin_number >> 4;
+        offset = (pin_number & 0xF) << 1;
+        
+        PINCONARRAY->PINMODE[index] &= ~(0x3 << offset);
+        PINCONARRAY->PINMODE[index] |= (uint32_t)mode << offset;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/port_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+
+PinName port_pin(PortName port, int pin_n) {
+    return (PinName)(LPC_GPIO0_BASE + ((port << PORT_SHIFT) | pin_n));
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+    obj->port = port;
+    obj->mask = mask;
+    
+    LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *)(LPC_GPIO0_BASE + ((int)port * 0x20));
+    
+    // Do not use masking, because it prevents the use of the unmasked pins
+    // port_reg->FIOMASK = ~mask;
+    
+    obj->reg_out = &port_reg->FIOPIN;
+    obj->reg_in  = &port_reg->FIOPIN;
+    obj->reg_dir  = &port_reg->FIODIR;
+    
+    uint32_t i;
+    // The function is set per pin: reuse gpio logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            gpio_set(port_pin(obj->port, i));
+        }
+    }
+    
+    port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+    uint32_t i;
+    // The mode is set per pin: reuse pinmap logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+    switch (dir) {
+        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
+    }
+}
+
+void port_write(port_t *obj, int value) {
+    *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj) {
+    return (*obj->reg_in & obj->mask);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/pwmout_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,172 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+#define TCR_CNT_EN       0x00000001
+#define TCR_RESET        0x00000002
+
+//  PORT ID, PWM ID, Pin function
+static const PinMap PinMap_PWM[] = {
+    {P1_18, PWM_1, 2},
+    {P1_20, PWM_2, 2},
+    {P1_21, PWM_3, 2},
+    {P1_23, PWM_4, 2},
+    {P1_24, PWM_5, 2},
+    {P1_26, PWM_6, 2},
+    {P2_0 , PWM_1, 1},
+    {P2_1 , PWM_2, 1},
+    {P2_2 , PWM_3, 1},
+    {P2_3 , PWM_4, 1},
+    {P2_4 , PWM_5, 1},
+    {P2_5 , PWM_6, 1},
+    {P3_25, PWM_2, 3},
+    {P3_26, PWM_3, 3},
+    {NC, NC, 0}
+};
+
+__IO uint32_t *PWM_MATCH[] = {
+    &(LPC_PWM1->MR0),
+    &(LPC_PWM1->MR1),
+    &(LPC_PWM1->MR2),
+    &(LPC_PWM1->MR3),
+    &(LPC_PWM1->MR4),
+    &(LPC_PWM1->MR5),
+    &(LPC_PWM1->MR6)
+};
+
+#define TCR_PWM_EN       0x00000008
+
+static unsigned int pwm_clock_mhz;
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+    // determine the channel
+    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+    if (pwm == (uint32_t)NC)
+        error("PwmOut pin mapping failed");
+    
+    obj->pwm = pwm;
+    obj->MR = PWM_MATCH[pwm];
+    
+    // ensure the power is on
+    LPC_SC->PCONP |= 1 << 6;
+    
+    // ensure clock to /4
+    LPC_SC->PCLKSEL0 &= ~(0x3 << 12);     // pclk = /4
+    LPC_PWM1->PR = 0;                     // no pre-scale
+    
+    // ensure single PWM mode
+    LPC_PWM1->MCR = 1 << 1; // reset TC on match 0
+    
+    // enable the specific PWM output
+    LPC_PWM1->PCR |= 1 << (8 + pwm);
+    
+    pwm_clock_mhz = SystemCoreClock / 4000000;
+    
+    // default to 20ms: standard for servos, and fine for e.g. brightness control
+    pwmout_period_ms(obj, 20);
+    pwmout_write    (obj, 0);
+    
+    // Wire pinout
+    pinmap_pinout(pin, PinMap_PWM);
+}
+
+void pwmout_free(pwmout_t* obj) {
+    // [TODO]
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+    if (value < 0.0f) {
+        value = 0.0;
+    } else if (value > 1.0f) {
+        value = 1.0;
+    }
+    
+    // set channel match to percentage
+    uint32_t v = (uint32_t)((float)(LPC_PWM1->MR0) * value);
+    
+    // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
+    if (v == LPC_PWM1->MR0) {
+        v++;
+    }
+    
+    *obj->MR = v;
+    
+    // accept on next period start
+    LPC_PWM1->LER |= 1 << obj->pwm;
+}
+
+float pwmout_read(pwmout_t* obj) {
+    float v = (float)(*obj->MR) / (float)(LPC_PWM1->MR0);
+    return (v > 1.0f) ? (1.0f) : (v);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+    pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+    pwmout_period_us(obj, ms * 1000);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+    // calculate number of ticks
+    uint32_t ticks = pwm_clock_mhz * us;
+    
+    // set reset
+    LPC_PWM1->TCR = TCR_RESET;
+    
+    // set the global match register
+    LPC_PWM1->MR0 = ticks;
+    
+    // Scale the pulse width to preserve the duty ratio
+    if (LPC_PWM1->MR0 > 0) {
+        *obj->MR = (*obj->MR * ticks) / LPC_PWM1->MR0;
+    }
+    
+    // set the channel latch to update value at next period start
+    LPC_PWM1->LER |= 1 << 0;
+    
+    // enable counter and pwm, clear reset
+    LPC_PWM1->TCR = TCR_CNT_EN | TCR_PWM_EN;
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+    // calculate number of ticks
+    uint32_t v = pwm_clock_mhz * us;
+    
+    // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
+    if (v == LPC_PWM1->MR0) {
+        v++;
+    }
+    
+    // set the match register value
+    *obj->MR = v;
+    
+    // set the channel latch to update value at next period start
+    LPC_PWM1->LER |= 1 << obj->pwm;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/rtc_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,117 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "rtc_api.h"
+
+// ensure rtc is running (unchanged if already running)
+
+/* Setup the RTC based on a time structure, ensuring RTC is enabled
+ *
+ * Can be clocked by a 32.768KHz oscillator or prescale divider based on the APB clock
+ * - We want to use the 32khz clock, allowing for sleep mode
+ *
+ * Most registers are not changed by a Reset
+ * - We must initialize these registers between power-on and setting the RTC into operation
+
+ * Clock Control Register
+ *  RTC_CCR[0] : Enable - 0 = Disabled, 1 = Enabled
+ *  RTC_CCR[1] : Reset - 0 = Normal, 1 = Reset
+ *  RTC_CCR[4] : Clock Source - 0 = Prescaler, 1 = 32k Xtal
+ *
+ * The RTC may already be running, so we should set it up
+ * without impacting if it is the case
+ */
+void rtc_init(void) {
+    LPC_SC->PCONP |= 0x200; // Ensure power is on
+    LPC_RTC->CCR = 0x00;
+    
+    // clock source on 2368 is special test mode on 1768!
+    LPC_RTC->CCR |= 1 << 4;  // Ensure clock source is 32KHz Xtal
+    
+    LPC_RTC->CCR |= 1 << 0; // Ensure the RTC is enabled
+}
+
+void rtc_free(void) {
+    // [TODO]
+}
+
+/*
+ * Little check routine to see if the RTC has been enabled
+ *
+ * Clock Control Register
+ *  RTC_CCR[0] : 0 = Disabled, 1 = Enabled
+ *
+ */
+
+int rtc_isenabled(void) {
+    return(((LPC_RTC->CCR) & 0x01) != 0);
+}
+
+/*
+ * RTC Registers
+ *  RTC_SEC        Seconds 0-59
+ *  RTC_MIN        Minutes 0-59
+ *  RTC_HOUR    Hour 0-23
+ *  RTC_DOM        Day of Month 1-28..31
+ *  RTC_DOW        Day of Week 0-6
+ *  RTC_DOY        Day of Year 1-365
+ *  RTC_MONTH    Month 1-12
+ *  RTC_YEAR    Year 0-4095
+ *
+ * struct tm
+ *  tm_sec        seconds after the minute 0-61
+ *  tm_min        minutes after the hour 0-59
+ *  tm_hour        hours since midnight 0-23
+ *  tm_mday        day of the month 1-31
+ *  tm_mon        months since January 0-11
+ *  tm_year        years since 1900
+ *  tm_wday        days since Sunday 0-6
+ *  tm_yday        days since January 1 0-365
+ *  tm_isdst    Daylight Saving Time flag
+ */
+time_t rtc_read(void) {
+    // Setup a tm structure based on the RTC
+    struct tm timeinfo;
+    timeinfo.tm_sec = LPC_RTC->SEC;
+    timeinfo.tm_min = LPC_RTC->MIN;
+    timeinfo.tm_hour = LPC_RTC->HOUR;
+    timeinfo.tm_mday = LPC_RTC->DOM;
+    timeinfo.tm_mon = LPC_RTC->MONTH - 1;
+    timeinfo.tm_year = LPC_RTC->YEAR - 1900;
+    
+    // Convert to timestamp
+    time_t t = mktime(&timeinfo);
+    
+    return t;
+}
+
+void rtc_write(time_t t) {
+    // Convert the time in to a tm
+    struct tm *timeinfo = localtime(&t);
+    
+    // Pause clock, and clear counter register (clears us count)
+    LPC_RTC->CCR |= 2;
+    
+    // Set the RTC
+    LPC_RTC->SEC = timeinfo->tm_sec;
+    LPC_RTC->MIN = timeinfo->tm_min;
+    LPC_RTC->HOUR = timeinfo->tm_hour;
+    LPC_RTC->DOM = timeinfo->tm_mday;
+    LPC_RTC->MONTH = timeinfo->tm_mon + 1;
+    LPC_RTC->YEAR = timeinfo->tm_year + 1900;
+    
+    // Restart clock
+    LPC_RTC->CCR &= ~((uint32_t)2);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/serial_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,318 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include <string.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+#define UART_NUM    4
+
+static const PinMap PinMap_UART_TX[] = {
+    {P0_0,  UART_3, 2},
+    {P0_2,  UART_0, 1},
+    {P0_10, UART_2, 1},
+    {P0_15, UART_1, 1},
+    {P0_25, UART_3, 3},
+    {P2_0 , UART_1, 2},
+    {P2_8 , UART_2, 2},
+    {P4_28, UART_3, 3},
+    {NC   , NC    , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+    {P0_1 , UART_3, 2},
+    {P0_3 , UART_0, 1},
+    {P0_11, UART_2, 1},
+    {P0_16, UART_1, 1},
+    {P0_26, UART_3, 3},
+    {P2_1 , UART_1, 2},
+    {P2_9 , UART_2, 2},
+    {P4_29, UART_3, 3},
+    {NC   , NC    , 0}
+};
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+    int is_stdio_uart = 0;
+    
+    // determine the UART to use
+    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+    UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    if ((int)uart == NC) {
+        error("Serial pinout mapping failed");
+    }
+    
+    obj->uart = (LPC_UART_TypeDef *)uart;
+    // enable power
+    switch (uart) {
+        case UART_0: LPC_SC->PCONP |= 1 <<  3; break;
+        case UART_1: LPC_SC->PCONP |= 1 <<  4; break;
+        case UART_2: LPC_SC->PCONP |= 1 << 24; break;
+        case UART_3: LPC_SC->PCONP |= 1 << 25; break;
+    }
+    
+    // enable fifos and default rx trigger level
+    obj->uart->FCR = 1 << 0  // FIFO Enable - 0 = Disables, 1 = Enabled
+                   | 0 << 1  // Rx Fifo Reset
+                   | 0 << 2  // Tx Fifo Reset
+                   | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
+
+    // disable irqs
+    obj->uart->IER = 0 << 0  // Rx Data available irq enable
+                   | 0 << 1  // Tx Fifo empty irq enable
+                   | 0 << 2; // Rx Line Status irq enable
+    
+    // set default baud rate and format
+    serial_baud  (obj, 9600);
+    serial_format(obj, 8, ParityNone, 1);
+    
+    // pinout the chosen uart
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+    
+    // set rx/tx pins in PullUp mode
+    pin_mode(tx, PullUp);
+    pin_mode(rx, PullUp);
+    
+    switch (uart) {
+        case UART_0: obj->index = 0; break;
+        case UART_1: obj->index = 1; break;
+        case UART_2: obj->index = 2; break;
+        case UART_3: obj->index = 3; break;
+    }
+    
+    is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+    
+    if (is_stdio_uart) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj) {
+    serial_irq_ids[obj->index] = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+    // The LPC2300 and LPC1700 have a divider and a fractional divider to control the
+    // baud rate. The formula is:
+    //
+    // Baudrate = (1 / PCLK) * 16 * DL * (1 + DivAddVal / MulVal)
+    //   where:
+    //     1 < MulVal <= 15
+    //     0 <= DivAddVal < 14
+    //     DivAddVal < MulVal
+    //
+    // set pclk to /1
+    switch ((int)obj->uart) {
+        case UART_0: LPC_SC->PCLKSEL0 &= ~(0x3 <<  6); LPC_SC->PCLKSEL0 |= (0x1 <<  6); break;
+        case UART_1: LPC_SC->PCLKSEL0 &= ~(0x3 <<  8); LPC_SC->PCLKSEL0 |= (0x1 <<  8); break;
+        case UART_2: LPC_SC->PCLKSEL1 &= ~(0x3 << 16); LPC_SC->PCLKSEL1 |= (0x1 << 16); break;
+        case UART_3: LPC_SC->PCLKSEL1 &= ~(0x3 << 18); LPC_SC->PCLKSEL1 |= (0x1 << 18); break;
+        default: error("serial_baud"); break;
+    }
+    
+    uint32_t PCLK = SystemCoreClock;
+    
+    // First we check to see if the basic divide with no DivAddVal/MulVal
+    // ratio gives us an integer result. If it does, we set DivAddVal = 0,
+    // MulVal = 1. Otherwise, we search the valid ratio value range to find
+    // the closest match. This could be more elegant, using search methods
+    // and/or lookup tables, but the brute force method is not that much
+    // slower, and is more maintainable.
+    uint16_t DL = PCLK / (16 * baudrate);
+
+    uint8_t DivAddVal = 0;
+    uint8_t MulVal = 1;
+    int hit = 0;
+    uint16_t dlv;
+    uint8_t mv, dav;
+    if ((PCLK % (16 * baudrate)) != 0) {     // Checking for zero remainder
+        float err_best = (float) baudrate;
+        uint16_t dlmax = DL;
+        for ( dlv = (dlmax/2); (dlv <= dlmax) && !hit; dlv++) {
+            for ( mv = 1; mv <= 15; mv++) {
+                for ( dav = 1; dav < mv; dav++) {
+                    float ratio = 1.0f + ((float) dav / (float) mv);
+                    float calcbaud = (float)PCLK / (16.0f * (float) dlv * ratio);
+                    float err = fabs(((float) baudrate - calcbaud) / (float) baudrate);
+                    if (err < err_best) {
+                        DL = dlv;
+                        DivAddVal = dav;
+                        MulVal = mv;
+                        err_best = err;
+                        if (err < 0.001f) {
+                            hit = 1;
+                        }
+                    }
+                }
+            }
+        }
+    }
+    
+    // set LCR[DLAB] to enable writing to divider registers
+    obj->uart->LCR |= (1 << 7);
+    
+    // set divider values
+    obj->uart->DLM = (DL >> 8) & 0xFF;
+    obj->uart->DLL = (DL >> 0) & 0xFF;
+    obj->uart->FDR = (uint32_t) DivAddVal << 0
+                   | (uint32_t) MulVal    << 4;
+    
+    // clear LCR[DLAB]
+    obj->uart->LCR &= ~(1 << 7);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+    // 0: 1 stop bits, 1: 2 stop bits
+    if (stop_bits != 1 && stop_bits != 2) {
+        error("Invalid stop bits specified");
+    }
+    stop_bits -= 1;
+    
+    // 0: 5 data bits ... 3: 8 data bits
+    if (data_bits < 5 || data_bits > 8) {
+        error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
+    }
+    data_bits -= 5;
+
+    int parity_enable, parity_select;
+    switch (parity) {
+        case ParityNone: parity_enable = 0; parity_select = 0; break;
+        case ParityOdd : parity_enable = 1; parity_select = 0; break;
+        case ParityEven: parity_enable = 1; parity_select = 1; break;
+        case ParityForced1: parity_enable = 1; parity_select = 2; break;
+        case ParityForced0: parity_enable = 1; parity_select = 3; break;
+        default:
+            error("Invalid serial parity setting");
+            return;
+    }
+    
+    obj->uart->LCR = data_bits            << 0
+                   | stop_bits            << 2
+                   | parity_enable        << 3
+                   | parity_select        << 4;
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t iir, uint32_t index) {
+    // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
+    SerialIrq irq_type;
+    switch (iir) {
+        case 1: irq_type = TxIrq; break;
+        case 2: irq_type = RxIrq; break;
+        default: return;
+    }
+    
+    if (serial_irq_ids[index] != 0)
+        irq_handler(serial_irq_ids[index], irq_type);
+}
+
+void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0);}
+void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);}
+void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2);}
+void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;
+    switch ((int)obj->uart) {
+        case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
+        case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
+        case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
+        case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
+    }
+    
+    if (enable) {
+        obj->uart->IER |= 1 << irq;
+        NVIC_SetVector(irq_n, vector);
+        NVIC_EnableIRQ(irq_n);
+    } else { // disable
+        int all_disabled = 0;
+        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+        obj->uart->IER &= ~(1 << irq);
+        all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
+        if (all_disabled)
+            NVIC_DisableIRQ(irq_n);
+    }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+    while (!serial_readable(obj));
+    return obj->uart->RBR;
+}
+
+void serial_putc(serial_t *obj, int c) {
+    while (!serial_writable(obj));
+    obj->uart->THR = c;
+    
+    uint32_t lsr = obj->uart->LSR;
+    lsr = lsr;
+    uint32_t thr = obj->uart->THR;
+    thr = thr;
+}
+
+int serial_readable(serial_t *obj) {
+    return obj->uart->LSR & 0x01;
+}
+
+int serial_writable(serial_t *obj) {
+    return obj->uart->LSR & 0x20;
+}
+
+void serial_clear(serial_t *obj) {
+    obj->uart->FCR = 1 << 1  // rx FIFO reset
+                   | 1 << 2  // tx FIFO reset
+                   | 0 << 6; // interrupt depth
+}
+
+void serial_pinout_tx(PinName tx) {
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+    obj->uart->LCR |= (1 << 6);
+}
+
+void serial_break_clear(serial_t *obj) {
+    obj->uart->LCR &= ~(1 << 6);
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/spi_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,224 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const PinMap PinMap_SPI_SCLK[] = {
+    {P0_7 , SPI_1, 2},
+    {P0_15, SPI_0, 2},
+    {P1_20, SPI_0, 3},
+    {P1_31, SPI_1, 2},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+    {P0_9 , SPI_1, 2},
+    {P0_13, SPI_1, 2},
+    {P0_18, SPI_0, 2},
+    {P1_24, SPI_0, 3},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+    {P0_8 , SPI_1, 2},
+    {P0_12, SPI_1, 2},
+    {P0_17, SPI_0, 2},
+    {P1_23, SPI_0, 3},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+    {P0_6 , SPI_1, 2},
+    {P0_11, SPI_1, 2},
+    {P0_16, SPI_0, 2},
+    {P1_21, SPI_0, 3},
+    {NC   , NC   , 0}
+};
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    // determine the SPI to use
+    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+    obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
+    
+    if ((int)obj->spi == NC) {
+        error("SPI pinout mapping failed");
+    }
+    
+    // enable power and clocking
+    switch ((int)obj->spi) {
+        case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
+        case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
+    }
+    
+    // set default format and frequency
+    if (ssel == NC) {
+        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
+    } else {
+        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
+    }
+    spi_frequency(obj, 1000000);
+    
+    // enable the ssp channel
+    ssp_enable(obj);
+    
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+    ssp_disable(obj);
+    
+    if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
+        error("SPI format error");
+    }
+    
+    int polarity = (mode & 0x2) ? 1 : 0;
+    int phase = (mode & 0x1) ? 1 : 0;
+    
+    // set it up
+    int DSS = bits - 1;            // DSS (data select size)
+    int SPO = (polarity) ? 1 : 0;  // SPO - clock out polarity
+    int SPH = (phase) ? 1 : 0;     // SPH - clock out phase
+    
+    int FRF = 0;                   // FRF (frame format) = SPI
+    uint32_t tmp = obj->spi->CR0;
+    tmp &= ~(0xFFFF);
+    tmp |= DSS << 0
+        | FRF << 4
+        | SPO << 6
+        | SPH << 7;
+    obj->spi->CR0 = tmp;
+    
+    tmp = obj->spi->CR1;
+    tmp &= ~(0xD);
+    tmp |= 0 << 0                   // LBM - loop back mode - off
+        | ((slave) ? 1 : 0) << 2   // MS - master slave mode, 1 = slave
+        | 0 << 3;                  // SOD - slave output disable - na
+    obj->spi->CR1 = tmp;
+    
+    ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+    ssp_disable(obj);
+    
+    // setup the spi clock diveder to /1
+    switch ((int)obj->spi) {
+        case SPI_0:
+            LPC_SC->PCLKSEL1 &= ~(3 << 10);
+            LPC_SC->PCLKSEL1 |=  (1 << 10);
+            break;
+        case SPI_1:
+            LPC_SC->PCLKSEL0 &= ~(3 << 20);
+            LPC_SC->PCLKSEL0 |=  (1 << 20);
+            break;
+    }
+    
+    uint32_t PCLK = SystemCoreClock;
+    
+    int prescaler;
+    
+    for (prescaler = 2; prescaler <= 254; prescaler += 2) {
+        int prescale_hz = PCLK / prescaler;
+        
+        // calculate the divider
+        int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
+        
+        // check we can support the divider
+        if (divider < 256) {
+            // prescaler
+            obj->spi->CPSR = prescaler;
+            
+            // divider
+            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 |= (divider - 1) << 8;
+            ssp_enable(obj);
+            return;
+        }
+    }
+    error("Couldn't setup requested SPI frequency");
+}
+
+static inline int ssp_disable(spi_t *obj) {
+    return obj->spi->CR1 &= ~(1 << 1);
+}
+
+static inline int ssp_enable(spi_t *obj) {
+    return obj->spi->CR1 |= (1 << 1);
+}
+
+static inline int ssp_readable(spi_t *obj) {
+    return obj->spi->SR & (1 << 2);
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+    return obj->spi->SR & (1 << 1);
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+    while (!ssp_writeable(obj));
+    obj->spi->DR = value;
+}
+
+static inline int ssp_read(spi_t *obj) {
+    while (!ssp_readable(obj));
+    return obj->spi->DR;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+    return (obj->spi->SR & (1 << 4)) ? (1) : (0);
+}
+
+int spi_master_write(spi_t *obj, int value) {
+    ssp_write(obj, value);
+    return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+    return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+};
+
+int spi_slave_read(spi_t *obj) {
+    return obj->spi->DR;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+    while (ssp_writeable(obj) == 0) ;
+    obj->spi->DR = value;
+}
+
+int spi_busy(spi_t *obj) {
+    return ssp_busy(obj);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC23XX/us_ticker.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+#define US_TICKER_TIMER      ((LPC_TIM_TypeDef *)LPC_TIM3_BASE)
+#define US_TICKER_TIMER_IRQn TIMER3_IRQn
+
+int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+    if (us_ticker_inited) return;
+    us_ticker_inited = 1;
+    
+    LPC_SC->PCONP |= 1 << 23; // Clock TIMER_3
+    
+    US_TICKER_TIMER->CTCR = 0x0; // timer mode
+    uint32_t PCLK = SystemCoreClock / 4;
+    
+    US_TICKER_TIMER->TCR = 0x2;  // reset
+    
+    uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks)
+    US_TICKER_TIMER->PR = prescale - 1;
+    US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0
+    
+    NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+uint32_t us_ticker_read() {
+    if (!us_ticker_inited)
+        us_ticker_init();
+    
+    return US_TICKER_TIMER->TC;
+}
+
+void us_ticker_set_interrupt(unsigned int timestamp) {
+    // set match value
+    US_TICKER_TIMER->MR0 = timestamp;
+    // enable match interrupt
+    US_TICKER_TIMER->MCR |= 1;
+}
+
+void us_ticker_disable_interrupt(void) {
+    US_TICKER_TIMER->MCR &= ~1;
+}
+
+void us_ticker_clear_interrupt(void) {
+    US_TICKER_TIMER->IR = 1;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/PeripheralNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/PinNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+    P0_0 = 0,
+    P0_1 = 1,
+    P0_2 = 2,
+    P0_3 = 3,
+    P0_4 = 4,
+    P0_5 = 5,
+    P0_6 = 6,
+    P0_7 = 7,
+    P0_8 = 8,
+    P0_9 = 9,
+    P0_10 = 10,
+    P0_11 = 11,
+    P0_12 = 12,
+    P0_13 = 13,
+    P0_14 = 14,
+    P0_15 = 15,
+    P0_16 = 16,
+    P0_17 = 17,
+    
+    D0 = P0_0,
+    D1 = P0_4,
+    D2 = P0_6,
+    D3 = P0_8,
+    D4 = P0_9,
+    
+    D7 = P0_7,
+    D8 = P0_17,
+    D9 = P0_16,
+    D10 = P0_13,
+    D11 = P0_14,
+    D12 = P0_15,
+    D13 = P0_12,
+    
+    A4 = P0_10,
+    A5 = P0_11,
+    
+    // LPC800-MAX board
+    LED_RED = P0_7,
+    LED_GREEN = P0_17,
+    LED_BLUE = P0_16,
+    
+    // mbed original LED naming
+    LED1 = LED_BLUE,
+    LED2 = LED_GREEN,
+    LED3 = LED_RED,
+    LED4 = LED_RED,
+    
+    // Serial to USB pins
+    USBTX = P0_6,
+    USBRX = P0_1,
+    
+    // Not connected
+    NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+    PullUp = 2,
+    PullDown = 1,
+    PullNone = 0,
+    Repeater = 3,
+    OpenDrain = 4
+} PinMode;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+
+typedef struct {
+    unsigned char n;
+    unsigned char offset;
+} SWM_Map;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/PortNames.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0,
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/device.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           0
+#define DEVICE_PORTOUT          0
+#define DEVICE_PORTINOUT        0
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         0
+#define DEVICE_ANALOGOUT        0
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         0
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         0
+
+#define DEVICE_CAN              0
+
+#define DEVICE_RTC              0
+
+#define DEVICE_ETHERNET         0
+
+#define DEVICE_PWMOUT           0
+
+#define DEVICE_SEMIHOST         0
+#define DEVICE_LOCALFILESYSTEM  0
+
+#define DEVICE_SLEEP            0
+
+#define DEVICE_DEBUG_AWARENESS  0
+
+#define DEVICE_STDIO_MESSAGES   1
+
+#define DEVICE_ERROR_RED        1
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,69 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+
+static int  gpio_enabled = 0;
+static void gpio_enable(void) {
+    gpio_enabled = 1;
+    
+    /* Enable AHB clock to the GPIO domain. */
+    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
+    
+    /* Peripheral reset control to GPIO and GPIO INT, a "1" bring it out of reset. */
+    LPC_SYSCON->PRESETCTRL &= ~(0x1<<10);
+    LPC_SYSCON->PRESETCTRL |=  (0x1<<10);
+}
+
+uint32_t gpio_set(PinName pin) {
+    int f = 0;
+    
+    if (!gpio_enabled)
+         gpio_enable();
+    
+    pin_function(pin, f);
+    
+    return (1 << ((int)pin & 0x1F));
+}
+
+void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
+    if(pin == NC) return;
+    
+    obj->pin = pin;
+    obj->mask = gpio_set(pin);
+    
+    obj->reg_set = &LPC_GPIO_PORT->SET0;
+    obj->reg_clr = &LPC_GPIO_PORT->CLR0;
+    obj->reg_in  = &LPC_GPIO_PORT->PIN0;
+    obj->reg_dir = &LPC_GPIO_PORT->DIR0;
+    
+    gpio_dir(obj, direction);
+    switch (direction) {
+        case PIN_OUTPUT: pin_mode(pin, PullNone); break;
+        case PIN_INPUT : pin_mode(pin, PullDown); break;
+    }
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+    pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+    switch (direction) {
+        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "error.h"
+
+#define CHANNEL_NUM    8
+#define LPC_GPIO_X LPC_PIN_INT
+#define PININT_IRQ PININT0_IRQn
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+
+static inline void handle_interrupt_in(uint32_t channel) {
+    uint32_t ch_bit = (1 << channel);
+    // Return immediately if:
+    //   * The interrupt was already served
+    //   * There is no user handler
+    //   * It is a level interrupt, not an edge interrupt
+    if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
+         (channel_ids[channel] == 0      ) ||
+         (LPC_GPIO_X->ISEL & ch_bit      ) ) return;
+
+    if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
+        irq_handler(channel_ids[channel], IRQ_RISE);
+        LPC_GPIO_X->RISE = ch_bit;
+    }
+    if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
+        irq_handler(channel_ids[channel], IRQ_FALL);
+    }
+    LPC_GPIO_X->IST = ch_bit;
+}
+
+void gpio_irq0(void) {handle_interrupt_in(0);}
+void gpio_irq1(void) {handle_interrupt_in(1);}
+void gpio_irq2(void) {handle_interrupt_in(2);}
+void gpio_irq3(void) {handle_interrupt_in(3);}
+void gpio_irq4(void) {handle_interrupt_in(4);}
+void gpio_irq5(void) {handle_interrupt_in(5);}
+void gpio_irq6(void) {handle_interrupt_in(6);}
+void gpio_irq7(void) {handle_interrupt_in(7);}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+    if (pin == NC) return -1;
+    
+    irq_handler = handler;
+    
+    int found_free_channel = 0;
+    int i = 0;
+    for (i=0; i<CHANNEL_NUM; i++) {
+        if (channel_ids[i] == 0) {
+            channel_ids[i] = id;
+            obj->ch = i;
+            found_free_channel = 1;
+            break;
+        }
+    }
+    if (!found_free_channel) return -1;
+
+    /* Enable AHB clock to the GPIO domain. */
+    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
+    
+    LPC_SYSCON->PINTSEL[obj->ch] = pin;
+    
+    // Interrupt Wake-Up Enable
+    LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
+    
+    void (*channels_irq)(void) = NULL;
+    switch (obj->ch) {
+        case 0: channels_irq = &gpio_irq0; break;
+        case 1: channels_irq = &gpio_irq1; break;
+        case 2: channels_irq = &gpio_irq2; break;
+        case 3: channels_irq = &gpio_irq3; break;
+        case 4: channels_irq = &gpio_irq4; break;
+        case 5: channels_irq = &gpio_irq5; break;
+        case 6: channels_irq = &gpio_irq6; break;
+        case 7: channels_irq = &gpio_irq7; break;
+    }
+    NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
+    NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+    
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+    channel_ids[obj->ch] = 0;
+    LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+    unsigned int ch_bit = (1 << obj->ch);
+    
+    // Clear interrupt
+    if (!(LPC_GPIO_X->ISEL & ch_bit))
+        LPC_GPIO_X->IST = ch_bit;
+    
+    // Edge trigger
+    LPC_GPIO_X->ISEL &= ~ch_bit;
+    if (event == IRQ_RISE) {
+        if (enable) {
+            LPC_GPIO_X->IENR |= ch_bit;
+        } else {
+            LPC_GPIO_X->IENR &= ~ch_bit;
+        }
+    } else {
+        if (enable) {
+            LPC_GPIO_X->IENF |= ch_bit;
+        } else {
+            LPC_GPIO_X->IENF &= ~ch_bit;
+        }
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_object.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName  pin;
+    uint32_t mask;
+
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_set;
+    __IO uint32_t *reg_clr;
+    __I  uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+    if (value)
+        *obj->reg_set = obj->mask;
+    else
+        *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,242 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const SWM_Map SWM_I2C_SDA[] = {
+    {7, 24},
+};
+
+static const SWM_Map SWM_I2C_SCL[] = {
+    {8, 0},
+};
+
+static uint8_t repeated_start = 0;
+
+#define I2C_DAT(x)          (x->i2c->MSTDAT)
+#define I2C_STAT(x)         ((x->i2c->STAT >> 1) & (0x07))
+
+static inline int i2c_status(i2c_t *obj) {
+    return I2C_STAT(obj);
+}
+
+// Wait until the Serial Interrupt (SI) is set
+static int i2c_wait_SI(i2c_t *obj) {
+    int timeout = 0;
+    while (!(obj->i2c->STAT & (1 << 0))) {
+        timeout++;
+        if (timeout > 100000) return -1;
+    }
+    return 0;
+}
+
+static inline void i2c_interface_enable(i2c_t *obj) {
+    obj->i2c->CFG |= (1 << 0);
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<5);	
+    LPC_SYSCON->PRESETCTRL &= ~(0x1<<6);
+    LPC_SYSCON->PRESETCTRL |= (0x1<<6);
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+    obj->i2c = (LPC_I2C_TypeDef *)LPC_I2C;
+    
+    const SWM_Map *swm;
+    uint32_t regVal;
+    
+    swm = &SWM_I2C_SDA[0];
+    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+    LPC_SWM->PINASSIGN[swm->n] = regVal |  (sda   << swm->offset);
+    
+    swm = &SWM_I2C_SCL[0];
+    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+    LPC_SWM->PINASSIGN[swm->n] = regVal |  (scl   << swm->offset);
+    
+    // enable power
+    i2c_power_enable(obj);
+    // set default frequency at 100k
+    i2c_frequency(obj, 100000);
+    i2c_interface_enable(obj);
+}
+
+inline int i2c_start(i2c_t *obj) {
+    int status = 0;
+    if (repeated_start) {
+        obj->i2c->MSTCTL = (1 << 1) | (1 << 0);
+        repeated_start = 0;
+    } else {
+        obj->i2c->MSTCTL = (1 << 1);
+    }
+    return status;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+    int timeout = 0;
+
+    obj->i2c->MSTCTL = (1 << 2) | (1 << 0);
+    while ((obj->i2c->STAT & ((1 << 0) | (7 << 1))) != ((1 << 0) | (0 << 1))) {
+        timeout ++;
+        if (timeout > 100000) return 1;
+    }
+
+    return 0;
+}
+
+
+static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
+    // write the data
+    I2C_DAT(obj) = value;
+    
+    if (!addr)
+        obj->i2c->MSTCTL = (1 << 0);
+    
+    // wait and return status
+    i2c_wait_SI(obj);
+    return i2c_status(obj);
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+    // wait for it to arrive
+    i2c_wait_SI(obj);
+    if (!last)
+        obj->i2c->MSTCTL = (1 << 0);
+    
+    // return the data
+    return (I2C_DAT(obj) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+    // No peripheral clock divider on the M0
+    uint32_t PCLK = SystemCoreClock;
+    
+    uint32_t clkdiv = PCLK / (hz * 4) - 1;
+    
+    obj->i2c->DIV = clkdiv;
+    obj->i2c->MSTTIME = 0;
+}
+
+// The I2C does a read or a write as a whole operation
+// There are two types of error conditions it can encounter
+//  1) it can not obtain the bus
+//  2) it gets error responses at part of the transmission
+//
+// We tackle them as follows:
+//  1) we retry until we get the bus. we could have a "timeout" if we can not get it
+//      which basically turns it in to a 2)
+//  2) on error, we use the standard error mechanisms to report/debug
+//
+// Therefore an I2C transaction should always complete. If it doesn't it is usually
+// because something is setup wrong (e.g. wiring), and we don't need to programatically
+// check for that
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+    int count, status;
+    
+    i2c_start(obj);
+    
+    status = i2c_do_write(obj, (address | 0x01), 1);
+    if (status != 0x01) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    
+    // Read in all except last byte
+    for (count = 0; count < (length - 1); count++) {
+        int value = i2c_do_read(obj, 0);
+        status = i2c_status(obj);
+        if (status != 0x00) {
+            i2c_stop(obj);
+            return count;
+        }
+        data[count] = (char) value;
+    }
+    
+    // read in last byte
+    int value = i2c_do_read(obj, 1);
+    status = i2c_status(obj);
+    if (status != 0x01) {
+        i2c_stop(obj);
+        return length - 1;
+    }
+    
+    data[count] = (char) value;
+    
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    } else {
+        repeated_start = 1;
+    }
+    
+    return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+    int i, status;
+    
+    i2c_start(obj);
+    
+    status = i2c_do_write(obj, (address & 0xFE), 1);
+    if (status != 0x02) {
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    
+    for (i=0; i<length; i++) {
+        status = i2c_do_write(obj, data[i], 0);
+        if (status != 0x02) {
+            i2c_stop(obj);
+            return i;
+        }
+    }
+    
+    // If not repeated start, send stop.
+    if (stop) {
+        i2c_stop(obj);
+    } else {
+        repeated_start = 1;
+    }
+    
+    return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+    i2c_stop(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+    return (i2c_do_read(obj, last) & 0xFF);
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+    int ack;
+    int status = i2c_do_write(obj, (data & 0xFF), 0);
+    
+    switch(status) {
+        case 2:
+            ack = 1;
+            break;
+        default:
+            ack = 0;
+            break;
+    }
+
+    return ack;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/objects.h	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    uint32_t ch;
+};
+
+struct serial_s {
+    LPC_USART_TypeDef *uart;
+    unsigned char index;
+};
+
+struct i2c_s {
+    LPC_I2C_TypeDef *i2c;
+};
+
+struct spi_s {
+    LPC_SPI_TypeDef *spi;
+    unsigned char spi_n;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/pinmap.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,50 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "error.h"
+
+__IO uint32_t* IOCON_REGISTERS[18] = {
+        &LPC_IOCON->PIO0_0 , &LPC_IOCON->PIO0_1 , &LPC_IOCON->PIO0_2 ,
+        &LPC_IOCON->PIO0_3 , &LPC_IOCON->PIO0_4 , &LPC_IOCON->PIO0_5 ,
+        &LPC_IOCON->PIO0_6 , &LPC_IOCON->PIO0_7 , &LPC_IOCON->PIO0_8 ,
+        &LPC_IOCON->PIO0_9 , &LPC_IOCON->PIO0_10, &LPC_IOCON->PIO0_11,
+        &LPC_IOCON->PIO0_12, &LPC_IOCON->PIO0_13, &LPC_IOCON->PIO0_14,
+        &LPC_IOCON->PIO0_15, &LPC_IOCON->PIO0_16, &LPC_IOCON->PIO0_17,
+};
+
+void pin_function(PinName pin, int function) {
+    
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+    if (pin == (uint32_t)NC) { return; }
+    
+    if ((pin == 10) || (pin == 11)) {
+        // True open-drain pins can be configured for different I2C-bus speeds
+        return;
+    }
+    
+    __IO uint32_t *reg = IOCON_REGISTERS[pin];
+    
+    if (mode == OpenDrain) {
+        *reg |= (1 << 10);
+    } else {
+        uint32_t tmp = *reg;
+        tmp &= ~(0x3 << 3);
+        tmp |= (mode & 0x3) << 3;
+        *reg = tmp;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,280 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include <string.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+#define UART_NUM    3
+
+static const SWM_Map SWM_UART_TX[] = {
+    {0, 0},
+    {1, 8},
+    {2, 16},
+};
+
+static const SWM_Map SWM_UART_RX[] = {
+    {0, 8},
+    {1, 16},
+    {2, 24},
+};
+
+// bit flags for used UARTs
+static unsigned char uart_used = 0;
+static int get_available_uart(void) {
+    int i;
+    for (i=0; i<3; i++) {
+        if ((uart_used & (1 << i)) == 0)
+            return i;
+    }
+    return -1;
+}
+
+#define UART_EN       (0x01<<0)
+
+#define CTS_DELTA     (0x01<<5)
+#define RXBRK         (0x01<<10)
+#define DELTA_RXBRK   (0x01<<11)
+
+#define RXRDY         (0x01<<0)
+#define TXRDY         (0x01<<2)
+
+#define TXBRKEN       (0x01<<1)
+
+static uint32_t UARTSysClk;
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+    int is_stdio_uart = 0;
+    
+    int uart_n = get_available_uart();
+    if (uart_n == -1) {
+        error("No available UART");
+    }
+    obj->index = uart_n;
+    obj->uart = (LPC_USART_TypeDef *)(LPC_USART0_BASE + (0x4000 * uart_n));
+    uart_used |= (1 << uart_n);
+    
+    const SWM_Map *swm;
+    uint32_t regVal;
+    
+    swm = &SWM_UART_TX[uart_n];
+    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+    LPC_SWM->PINASSIGN[swm->n] = regVal |  (tx   << swm->offset);
+    
+    swm = &SWM_UART_RX[uart_n];
+    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+    LPC_SWM->PINASSIGN[swm->n] = regVal |  (rx   << swm->offset);
+    
+    /* uart clock divided by 1 */
+    LPC_SYSCON->UARTCLKDIV = 1;
+    
+    /* disable uart interrupts */
+    NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
+    
+    /* Enable UART clock */
+    LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (14 + uart_n));
+    
+    /* Peripheral reset control to UART, a "1" bring it out of reset. */
+    LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n));
+    LPC_SYSCON->PRESETCTRL |=  (0x1 << (3 + uart_n));
+    
+    UARTSysClk = SystemCoreClock / LPC_SYSCON->UARTCLKDIV;
+    
+    // set default baud rate and format
+    serial_baud  (obj, 9600);
+    serial_format(obj, 8, ParityNone, 1);
+    
+    /* Clear all status bits. */
+    obj->uart->STAT = CTS_DELTA | DELTA_RXBRK;
+    
+    /* enable uart interrupts */
+    NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
+    
+    /* Enable UART interrupt */
+    // obj->uart->INTENSET = RXRDY | TXRDY | DELTA_RXBRK;
+    
+    /* Enable UART */
+    obj->uart->CFG |= UART_EN;
+    
+    is_stdio_uart = ((tx == USBTX) && (rx == USBRX));
+    
+    if (is_stdio_uart) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj) {
+    uart_used &= ~(1 << obj->index);
+    serial_irq_ids[obj->index] = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+    /* Integer divider:
+         BRG = UARTSysClk/(Baudrate * 16) - 1
+       
+       Frational divider:
+         FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1)
+       
+       where
+         FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1)
+       
+       (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB
+           register is 0xFF.
+       (2) In ADD register value, depending on the value of UartSysClk,
+           baudrate, BRG register value, and SUB register value, be careful
+           about the order of multiplier and divider and make sure any
+           multiplier doesn't exceed 32-bit boundary and any divider doesn't get
+           down below one(integer 0).
+       (3) ADD should be always less than SUB.
+    */
+    obj->uart->BRG = UARTSysClk / 16 / baudrate - 1;
+    
+    LPC_SYSCON->UARTFRGDIV = 0xFF;
+    LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) /
+                                (baudrate * (obj->uart->BRG + 1))
+                              ) - (LPC_SYSCON->UARTFRGDIV + 1);
+
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+    // 0: 1 stop bits, 1: 2 stop bits
+    if (stop_bits != 1 && stop_bits != 2) {
+        error("Invalid stop bits specified");
+    }
+    stop_bits -= 1;
+    
+    // 0: 7 data bits ... 2: 9 data bits
+    if (data_bits < 7 || data_bits > 9) {
+        error("Invalid number of bits (%d) in serial format, should be 7..9", data_bits);
+    }
+    data_bits -= 7;
+    
+    int paritysel;
+    switch (parity) {
+        case ParityNone: paritysel = 0; break;
+        case ParityEven: paritysel = 2; break;
+        case ParityOdd : paritysel = 3; break;
+        default:
+            error("Invalid serial parity setting");
+            return;
+    }
+    
+    obj->uart->CFG = (data_bits << 2)
+                   | (paritysel << 4)
+                   | (stop_bits << 6);
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t iir, uint32_t index) {
+    // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
+    SerialIrq irq_type;
+    switch (iir) {
+        case 1: irq_type = TxIrq; break;
+        case 2: irq_type = RxIrq; break;
+        default: return;
+    }
+    
+    if (serial_irq_ids[index] != 0)
+        irq_handler(serial_irq_ids[index], irq_type);
+}
+
+void uart0_irq() {uart_irq((LPC_USART0->STAT & (1 << 2)) ? 2 : 1, 0);}
+void uart1_irq() {uart_irq((LPC_USART1->STAT & (1 << 2)) ? 2 : 1, 1);}
+void uart2_irq() {uart_irq((LPC_USART2->STAT & (1 << 2)) ? 2 : 1, 2);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;
+    switch ((int)obj->uart) {
+        case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
+        case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
+        case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
+    }
+    
+    if (enable) {
+        obj->uart->INTENSET = (1 << ((irq == RxIrq) ? 0 : 2));
+        NVIC_SetVector(irq_n, vector);
+        NVIC_EnableIRQ(irq_n);
+    } else { // disable
+        int all_disabled = 0;
+        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+        obj->uart->INTENSET &= ~(1 << ((irq == RxIrq) ? 0 : 2));
+        all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0;
+        if (all_disabled)
+            NVIC_DisableIRQ(irq_n);
+    }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+    while (!serial_readable(obj));
+    return obj->uart->RXDATA;
+}
+
+void serial_putc(serial_t *obj, int c) {
+    while (!serial_writable(obj));
+    obj->uart->TXDATA = c;
+}
+
+int serial_readable(serial_t *obj) {
+    return obj->uart->STAT & RXRDY;
+}
+
+int serial_writable(serial_t *obj) {
+    return obj->uart->STAT & TXRDY;
+}
+
+void serial_clear(serial_t *obj) {
+    // [TODO]
+}
+
+void serial_pinout_tx(PinName tx) {
+    
+}
+
+void serial_break_set(serial_t *obj) {
+    obj->uart->CTRL |= TXBRKEN;
+}
+
+void serial_break_clear(serial_t *obj) {
+    obj->uart->CTRL &= ~TXBRKEN;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,210 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <math.h>
+
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const SWM_Map SWM_SPI_SSEL[] = {
+    {4, 16},
+    {5, 16},
+};
+
+static const SWM_Map SWM_SPI_SCLK[] = {
+    {3, 24},
+    {4, 24},
+};
+
+static const SWM_Map SWM_SPI_MOSI[] = {
+    {4, 0},
+    {5, 0},
+};
+
+static const SWM_Map SWM_SPI_MISO[] = {
+    {4, 8},
+    {5, 16},
+};
+
+// bit flags for used SPIs
+static unsigned char spi_used = 0;
+static int get_available_spi(void) {
+    int i;
+    for (i=0; i<2; i++) {
+        if ((spi_used & (1 << i)) == 0)
+            return i;
+    }
+    return -1;
+}
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    int spi_n = get_available_spi();
+    if (spi_n == -1) {
+        error("No available SPI");
+    }
+    obj->spi_n = spi_n;
+    spi_used |= (1 << spi_n);
+    
+    obj->spi = (spi_n) ? (LPC_SPI_TypeDef *)(LPC_SPI1_BASE) : (LPC_SPI_TypeDef *)(LPC_SPI0_BASE);
+    
+    const SWM_Map *swm;
+    uint32_t regVal;
+    
+    swm = &SWM_SPI_SCLK[obj->spi_n];
+    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+    LPC_SWM->PINASSIGN[swm->n] = regVal |  (sclk   << swm->offset);
+    
+    swm = &SWM_SPI_MOSI[obj->spi_n];
+    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+    LPC_SWM->PINASSIGN[swm->n] = regVal |  (mosi   << swm->offset);
+    
+    swm = &SWM_SPI_MISO[obj->spi_n];
+    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+    LPC_SWM->PINASSIGN[swm->n] = regVal |  (miso   << swm->offset);
+    
+    swm = &SWM_SPI_SSEL[obj->spi_n];
+    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+    LPC_SWM->PINASSIGN[swm->n] = regVal |  (ssel   << swm->offset);
+    
+    // clear interrupts
+    obj->spi->INTENCLR = 0x3f;
+    
+    // enable power and clocking
+    switch (obj->spi_n) {
+        case 0:
+            LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11);
+            LPC_SYSCON->PRESETCTRL &= ~(0x1<<0);
+            LPC_SYSCON->PRESETCTRL |= (0x1<<0);
+            break;
+        case 1:
+            LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
+            LPC_SYSCON->PRESETCTRL &= ~(0x1<<1);
+            LPC_SYSCON->PRESETCTRL |= (0x1<<1);
+            break;
+    }
+    
+    // set default format and frequency
+    if (ssel == NC) {
+        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
+    } else {
+        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
+    }
+    spi_frequency(obj, 1000000);
+    
+    // enable the ssp channel
+    ssp_enable(obj);
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+    ssp_disable(obj);
+    
+    if (!(bits >= 1 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
+        error("SPI format error");
+    }
+    
+    
+    int polarity = (mode & 0x2) ? 1 : 0;
+    int phase = (mode & 0x1) ? 1 : 0;
+    
+    // set it up
+    int DSS = bits - 1;            // DSS (data select size)
+    int SPO = (polarity) ? 1 : 0;  // SPO - clock out polarity
+    int SPH = (phase) ? 1 : 0;     // SPH - clock out phase
+    
+    uint32_t tmp = obj->spi->CFG;
+    tmp &= ~((1 << 2) | (1 << 4) | (1 << 5));
+    tmp |= (SPH << 4) | (SPO << 5) | ((slave ? 0 : 1) << 2);
+    obj->spi->CFG = tmp;
+    
+    // select frame length
+    tmp = obj->spi->TXDATCTL;
+    tmp &= ~(0xf << 24);
+    tmp |= (DSS << 24);
+    obj->spi->TXDATCTL = tmp;
+    
+    ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+    ssp_disable(obj);
+    
+    uint32_t PCLK = SystemCoreClock;
+    
+    obj->spi->DIV = PCLK/hz - 1;
+    obj->spi->DLY = 0;
+    ssp_enable(obj);
+}
+
+static inline int ssp_disable(spi_t *obj) {
+    return obj->spi->CFG &= ~(1 << 0);
+}
+
+static inline int ssp_enable(spi_t *obj) {
+    return obj->spi->CFG |= (1 << 0);
+}
+
+static inline int ssp_readable(spi_t *obj) {
+    return obj->spi->STAT & (1 << 0);
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+    return obj->spi->STAT & (1 << 1);
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+    while (!ssp_writeable(obj));
+    // end of transfer
+    obj->spi->TXDATCTL |= (1 << 20);
+    obj->spi->TXDAT = value;
+}
+
+static inline int ssp_read(spi_t *obj) {
+    while (!ssp_readable(obj));
+    return obj->spi->RXDAT;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+    // TODO
+    return 0;
+}
+
+int spi_master_write(spi_t *obj, int value) {
+    ssp_write(obj, value);
+    return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+    return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+};
+
+int spi_slave_read(spi_t *obj) {
+    return obj->spi->RXDAT;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+    while (ssp_writeable(obj) == 0) ;
+    obj->spi->TXDAT = value;
+}
+
+int spi_busy(spi_t *obj) {
+    return ssp_busy(obj);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/us_ticker.c	Mon Aug 05 14:12:34 2013 +0300
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+#define US_TICKER_TIMER_IRQn     SCT_IRQn
+
+int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+    if (us_ticker_inited) return;
+    us_ticker_inited = 1;
+    
+    // Enable the SCT clock
+    LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
+    
+    // Clear peripheral reset the SCT:
+    LPC_SYSCON->PRESETCTRL |= (1 << 8);
+    
+    // Unified counter (32 bits)
+    LPC_SCT->CONFIG |= 1;
+    
+    // halt and clear the counter
+    LPC_SCT->CTRL_L |= (1 << 2) | (1 << 3);
+    
+    // System Clock (12)MHz -> us_ticker (1)MHz
+    LPC_SCT->CTRL_L |= ((SystemCoreClock/1000000 - 1) << 5);
+    
+    // unhalt the counter:
+    //    - clearing bit 2 of the CTRL register
+    LPC_SCT->CTRL_L &= ~(1 << 2);
+    
+    NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+uint32_t us_ticker_read() {
+    if (!us_ticker_inited)
+        us_ticker_init();
+    
+    return LPC_SCT->COUNT_U;
+}
+
+void us_ticker_set_interrupt(unsigned int timestamp) {
+    // halt the counter: 
+    //    - setting bit 2 of the CTRL register
+    LPC_SCT->CTRL_L |= (1 << 2);
+    
+    // set timestamp in compare register
+    LPC_SCT->MATCH[0].U = timestamp;
+    
+    // unhalt the counter:
+    //    - clearing bit 2 of the CTRL register
+    LPC_SCT->CTRL_L &= ~(1 << 2);
+    
+    // if events are not enabled, enable them
+    if (!(LPC_SCT->EVEN & 0x01)) {
+        
+        // comb mode = match only
+        LPC_SCT->EVENT[0].CTRL = (1 << 12);
+        
+        // ref manual:
+        //   In simple applications that do not 
+        //   use states, write 0x01 to this 
+        //   register to enable an event
+        LPC_SCT->EVENT[0].STATE |= 0x1;
+        
+        // enable events
+        LPC_SCT->EVEN |= 0x1;
+    }
+}
+
+void us_ticker_disable_interrupt(void) {
+    LPC_SCT->EVEN &= ~1;
+}
+
+void us_ticker_clear_interrupt(void) {
+    LPC_SCT->EVFLAG = 1;
+}

--- a/vendor/Freescale/KL25Z/cmsis/ARM/MKL25Z4.sct	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,14 +0,0 @@
-
-LR_IROM1 0x00000000 0x20000  {    ; load region size_region (32k)
-  ER_IROM1 0x00000000 0x20000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
-  ; 0x4000 - 0xC0 = 0x3F40
-  RW_IRAM1 0x1FFFF0C0 0x3F40 {
-   .ANY (+RW +ZI)
-  }
-}
-

--- a/vendor/Freescale/KL25Z/cmsis/ARM/startup_MKL25Z4.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,332 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_MKL25Z4.s
-; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
-; *           MKL25Z4
-; * @version: 1.1
-; * @date:    2012-6-21
-; *
-; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-;*
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; *****************************************************************************/
-
-
-__initial_sp        EQU     0x20003000  ; Top of RAM
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp  ; Top of Stack
-                DCD     Reset_Handler  ; Reset Handler
-                DCD     NMI_Handler  ; NMI Handler
-                DCD     HardFault_Handler  ; Hard Fault Handler
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     SVC_Handler  ; SVCall Handler
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     PendSV_Handler  ; PendSV Handler
-                DCD     SysTick_Handler  ; SysTick Handler
-
-                ; External Interrupts
-                DCD     DMA0_IRQHandler  ; DMA channel 0 transfer complete interrupt
-                DCD     DMA1_IRQHandler  ; DMA channel 1 transfer complete interrupt
-                DCD     DMA2_IRQHandler  ; DMA channel 2 transfer complete interrupt
-                DCD     DMA3_IRQHandler  ; DMA channel 3 transfer complete interrupt
-                DCD     Reserved20_IRQHandler  ; Reserved interrupt 20
-                DCD     FTFA_IRQHandler  ; FTFA interrupt
-                DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
-                DCD     LLW_IRQHandler  ; Low Leakage Wakeup
-                DCD     I2C0_IRQHandler  ; I2C0 interrupt
-                DCD     I2C1_IRQHandler  ; I2C0 interrupt 25
-                DCD     SPI0_IRQHandler  ; SPI0 interrupt
-                DCD     SPI1_IRQHandler  ; SPI1 interrupt
-                DCD     UART0_IRQHandler  ; UART0 status/error interrupt
-                DCD     UART1_IRQHandler  ; UART1 status/error interrupt
-                DCD     UART2_IRQHandler  ; UART2 status/error interrupt
-                DCD     ADC0_IRQHandler  ; ADC0 interrupt
-                DCD     CMP0_IRQHandler  ; CMP0 interrupt
-                DCD     TPM0_IRQHandler  ; TPM0 fault, overflow and channels interrupt
-                DCD     TPM1_IRQHandler  ; TPM1 fault, overflow and channels interrupt
-                DCD     TPM2_IRQHandler  ; TPM2 fault, overflow and channels interrupt
-                DCD     RTC_IRQHandler  ; RTC interrupt
-                DCD     RTC_Seconds_IRQHandler  ; RTC seconds interrupt
-                DCD     PIT_IRQHandler  ; PIT timer interrupt
-                DCD     Reserved39_IRQHandler  ; Reserved interrupt 39
-                DCD     USB0_IRQHandler  ; USB0 interrupt
-                DCD     DAC0_IRQHandler  ; DAC interrupt
-                DCD     TSI0_IRQHandler  ; TSI0 interrupt
-                DCD     MCG_IRQHandler  ; MCG interrupt
-                DCD     LPTimer_IRQHandler  ; LPTimer interrupt
-                DCD     Reserved45_IRQHandler  ; Reserved interrupt 45
-                DCD     PORTA_IRQHandler  ; Port A interrupt
-                DCD     PORTD_IRQHandler  ; Port D interrupt
-__Vectors_End
-
-__Vectors_Size 	EQU     __Vectors_End - __Vectors
-
-; <h> Flash Configuration
-;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
-;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
-;   <h> Backdoor Comparison Key
-;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
-;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
-;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
-;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
-;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
-;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
-;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
-;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
-BackDoorK0      EQU     0xFF
-BackDoorK1      EQU     0xFF
-BackDoorK2      EQU     0xFF
-BackDoorK3      EQU     0xFF
-BackDoorK4      EQU     0xFF
-BackDoorK5      EQU     0xFF
-BackDoorK6      EQU     0xFF
-BackDoorK7      EQU     0xFF
-;   </h>
-;   <h> Program flash protection bytes (FPROT)
-;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
-;     <i> Each bit protects a 1/32 region of the program flash memory.
-;     <h> FPROT0
-;       <i> Program flash protection bytes
-;       <i> 1/32 - 8/32 region
-;       <o.0>   FPROT0.0
-;       <o.1>   FPROT0.1
-;       <o.2>   FPROT0.2
-;       <o.3>   FPROT0.3
-;       <o.4>   FPROT0.4
-;       <o.5>   FPROT0.5
-;       <o.6>   FPROT0.6
-;       <o.7>   FPROT0.7
-nFPROT0         EQU     0x00
-FPROT0          EQU     nFPROT0:EOR:0xFF
-;     </h>
-;     <h> FPROT1
-;       <i> Program Flash Region Protect Register 1
-;       <i> 9/32 - 16/32 region
-;       <o.0>   FPROT1.0
-;       <o.1>   FPROT1.1
-;       <o.2>   FPROT1.2
-;       <o.3>   FPROT1.3
-;       <o.4>   FPROT1.4
-;       <o.5>   FPROT1.5
-;       <o.6>   FPROT1.6
-;       <o.7>   FPROT1.7
-nFPROT1         EQU     0x00
-FPROT1          EQU     nFPROT1:EOR:0xFF
-;     </h>
-;     <h> FPROT2
-;       <i> Program Flash Region Protect Register 2
-;       <i> 17/32 - 24/32 region
-;       <o.0>   FPROT2.0
-;       <o.1>   FPROT2.1
-;       <o.2>   FPROT2.2
-;       <o.3>   FPROT2.3
-;       <o.4>   FPROT2.4
-;       <o.5>   FPROT2.5
-;       <o.6>   FPROT2.6
-;       <o.7>   FPROT2.7
-nFPROT2         EQU     0x00
-FPROT2          EQU     nFPROT2:EOR:0xFF
-;     </h>
-;     <h> FPROT3
-;       <i> Program Flash Region Protect Register 3
-;       <i> 25/32 - 32/32 region
-;       <o.0>   FPROT3.0
-;       <o.1>   FPROT3.1
-;       <o.2>   FPROT3.2
-;       <o.3>   FPROT3.3
-;       <o.4>   FPROT3.4
-;       <o.5>   FPROT3.5
-;       <o.6>   FPROT3.6
-;       <o.7>   FPROT3.7
-nFPROT3         EQU     0x00
-FPROT3          EQU     nFPROT3:EOR:0xFF
-;     </h>
-;   </h>
-;   </h>
-;   <h> Flash nonvolatile option byte (FOPT)
-;     <i> Allows the user to customize the operation of the MCU at boot time.
-;     <o.0>  LPBOOT0
-;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
-;       <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
-;     <o.4>  LPBOOT1
-;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
-;       <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
-;     <o.2>  NMI_DIS
-;       <0=> NMI interrupts are always blocked
-;       <1=> NMI pin/interrupts reset default to enabled
-;     <o.3>  RESET_PIN_CFG
-;       <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
-;       <1=> RESET pin is dedicated
-;     <o.3>  FAST_INIT
-;       <0=> Slower initialization
-;       <1=> Fast Initialization
-FOPT            EQU     0xFF
-;   </h>
-;   <h> Flash security byte (FSEC)
-;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
-;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
-;     <o.0..1> SEC
-;       <2=> MCU security status is unsecure
-;       <3=> MCU security status is secure
-;         <i> Flash Security
-;         <i> This bits define the security state of the MCU.
-;     <o.2..3> FSLACC
-;       <2=> Freescale factory access denied
-;       <3=> Freescale factory access granted
-;         <i> Freescale Failure Analysis Access Code
-;         <i> This bits define the security state of the MCU.
-;     <o.4..5> MEEN
-;       <2=> Mass erase is disabled
-;       <3=> Mass erase is enabled
-;         <i> Mass Erase Enable Bits
-;         <i> Enables and disables mass erase capability of the FTFL module
-;     <o.6..7> KEYEN
-;       <2=> Backdoor key access enabled
-;       <3=> Backdoor key access disabled
-;         <i> Backdoor key Security Enable
-;         <i> These bits enable and disable backdoor key access to the FTFL module.
-FSEC            EQU     0xFE
-;   </h>
-
-                IF      :LNOT::DEF:RAM_TARGET
-                AREA    |.ARM.__at_0x400|, CODE, READONLY
-                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
-                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
-                DCB     FPROT0,     FPROT1,     FPROT2,     FPROT3
-                DCB     FSEC,       FOPT,       0xFF,     0xFF
-                ENDIF
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-                EXPORT  DMA0_IRQHandler     [WEAK]
-                EXPORT  DMA1_IRQHandler     [WEAK]
-                EXPORT  DMA2_IRQHandler     [WEAK]
-                EXPORT  DMA3_IRQHandler     [WEAK]
-                EXPORT  Reserved20_IRQHandler     [WEAK]
-                EXPORT  FTFA_IRQHandler     [WEAK]
-                EXPORT  LVD_LVW_IRQHandler     [WEAK]
-                EXPORT  LLW_IRQHandler     [WEAK]
-                EXPORT  I2C0_IRQHandler     [WEAK]
-                EXPORT  I2C1_IRQHandler     [WEAK]
-                EXPORT  SPI0_IRQHandler     [WEAK]
-                EXPORT  SPI1_IRQHandler     [WEAK]
-                EXPORT  UART0_IRQHandler     [WEAK]
-                EXPORT  UART1_IRQHandler     [WEAK]
-                EXPORT  UART2_IRQHandler     [WEAK]
-                EXPORT  ADC0_IRQHandler     [WEAK]
-                EXPORT  CMP0_IRQHandler     [WEAK]
-                EXPORT  TPM0_IRQHandler     [WEAK]
-                EXPORT  TPM1_IRQHandler     [WEAK]
-                EXPORT  TPM2_IRQHandler     [WEAK]
-                EXPORT  RTC_IRQHandler     [WEAK]
-                EXPORT  RTC_Seconds_IRQHandler     [WEAK]
-                EXPORT  PIT_IRQHandler     [WEAK]
-                EXPORT  Reserved39_IRQHandler     [WEAK]
-                EXPORT  USB0_IRQHandler     [WEAK]
-                EXPORT  DAC0_IRQHandler     [WEAK]
-                EXPORT  TSI0_IRQHandler     [WEAK]
-                EXPORT  MCG_IRQHandler     [WEAK]
-                EXPORT  LPTimer_IRQHandler     [WEAK]
-                EXPORT  Reserved45_IRQHandler     [WEAK]
-                EXPORT  PORTA_IRQHandler     [WEAK]
-                EXPORT  PORTD_IRQHandler     [WEAK]
-                EXPORT  DefaultISR                      [WEAK]
-
-DMA0_IRQHandler
-DMA1_IRQHandler
-DMA2_IRQHandler
-DMA3_IRQHandler
-Reserved20_IRQHandler
-FTFA_IRQHandler
-LVD_LVW_IRQHandler
-LLW_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-SPI0_IRQHandler
-SPI1_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-ADC0_IRQHandler
-CMP0_IRQHandler
-TPM0_IRQHandler
-TPM1_IRQHandler
-TPM2_IRQHandler
-RTC_IRQHandler
-RTC_Seconds_IRQHandler
-PIT_IRQHandler
-Reserved39_IRQHandler
-USB0_IRQHandler
-DAC0_IRQHandler
-TSI0_IRQHandler
-MCG_IRQHandler
-LPTimer_IRQHandler
-Reserved45_IRQHandler
-PORTA_IRQHandler
-PORTD_IRQHandler
-DefaultISR
-
-                B       .
-
-                ENDP
-
-
-                ALIGN
-                END

--- a/vendor/Freescale/KL25Z/cmsis/ARM/sys.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * Setup a fixed single stack/heap memory model, 
- *  between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/vendor/Freescale/KL25Z/cmsis/MKL25Z4.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,4155 +0,0 @@
-/*
-** ###################################################################
-**     Processor:           MKL25Z128VLK4
-**     Compilers:           ARM Compiler
-**                          Freescale C/C++ for Embedded ARM
-**                          GNU C Compiler
-**                          IAR ANSI C/C++ Compiler for ARM
-**
-**     Reference manual:    KL25RM, Rev.1, Jun 2012
-**     Version:             rev. 1.1, 2012-06-21
-**
-**     Abstract:
-**         CMSIS Peripheral Access Layer for MKL25Z4
-**
-**     Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-**
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
-**
-**     Revisions:
-**     - rev. 1.0 (2012-06-13)
-**         Initial version.
-**     - rev. 1.1 (2012-06-21)
-**         Update according to reference manual rev. 1.
-**
-** ###################################################################
-*/
-
-/**
- * @file MKL25Z4.h
- * @version 1.1
- * @date 2012-06-21
- * @brief CMSIS Peripheral Access Layer for MKL25Z4
- *
- * CMSIS Peripheral Access Layer for MKL25Z4
- */
-
-#if !defined(MKL25Z4_H_)
-#define MKL25Z4_H_                               /**< Symbol preventing repeated inclusion */
-
-/** Memory map major version (memory maps with equal major version number are
- * compatible) */
-#define MCU_MEM_MAP_VERSION 0x0100u
-/** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0001u
-
-
-/* ----------------------------------------------------------------------------
-   -- Interrupt vector numbers
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
- * @{
- */
-
-/** Interrupt Number Definitions */
-typedef enum IRQn {
-  /* Core interrupts */
-  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
-  HardFault_IRQn               = -13,              /**< Cortex-M0 SV Hard Fault Interrupt */
-  SVCall_IRQn                  = -5,               /**< Cortex-M0 SV Call Interrupt */
-  PendSV_IRQn                  = -2,               /**< Cortex-M0 Pend SV Interrupt */
-  SysTick_IRQn                 = -1,               /**< Cortex-M0 System Tick Interrupt */
-
-  /* Device specific interrupts */
-  DMA0_IRQn                    = 0,                /**< DMA channel 0 transfer complete interrupt */
-  DMA1_IRQn                    = 1,                /**< DMA channel 1 transfer complete interrupt */
-  DMA2_IRQn                    = 2,                /**< DMA channel 2 transfer complete interrupt */
-  DMA3_IRQn                    = 3,                /**< DMA channel 3 transfer complete interrupt */
-  Reserved20_IRQn              = 4,                /**< Reserved interrupt 20 */
-  FTFA_IRQn                    = 5,                /**< FTFA interrupt */
-  LVD_LVW_IRQn                 = 6,                /**< Low Voltage Detect, Low Voltage Warning */
-  LLW_IRQn                     = 7,                /**< Low Leakage Wakeup */
-  I2C0_IRQn                    = 8,                /**< I2C0 interrupt */
-  I2C1_IRQn                    = 9,                /**< I2C0 interrupt 25 */
-  SPI0_IRQn                    = 10,               /**< SPI0 interrupt */
-  SPI1_IRQn                    = 11,               /**< SPI1 interrupt */
-  UART0_IRQn                   = 12,               /**< UART0 status/error interrupt */
-  UART1_IRQn                   = 13,               /**< UART1 status/error interrupt */
-  UART2_IRQn                   = 14,               /**< UART2 status/error interrupt */
-  ADC0_IRQn                    = 15,               /**< ADC0 interrupt */
-  CMP0_IRQn                    = 16,               /**< CMP0 interrupt */
-  TPM0_IRQn                    = 17,               /**< TPM0 fault, overflow and channels interrupt */
-  TPM1_IRQn                    = 18,               /**< TPM1 fault, overflow and channels interrupt */
-  TPM2_IRQn                    = 19,               /**< TPM2 fault, overflow and channels interrupt */
-  RTC_IRQn                     = 20,               /**< RTC interrupt */
-  RTC_Seconds_IRQn             = 21,               /**< RTC seconds interrupt */
-  PIT_IRQn                     = 22,               /**< PIT timer interrupt */
-  Reserved39_IRQn              = 23,               /**< Reserved interrupt 39 */
-  USB0_IRQn                    = 24,               /**< USB0 interrupt */
-  DAC0_IRQn                    = 25,               /**< DAC interrupt */
-  TSI0_IRQn                    = 26,               /**< TSI0 interrupt */
-  MCG_IRQn                     = 27,               /**< MCG interrupt */
-  LPTimer_IRQn                 = 28,               /**< LPTimer interrupt */
-  Reserved45_IRQn              = 29,               /**< Reserved interrupt 45 */
-  PORTA_IRQn                   = 30,               /**< Port A interrupt */
-  PORTD_IRQn                   = 31                /**< Port D interrupt */
-} IRQn_Type;
-
-/**
- * @}
- */ /* end of group Interrupt_vector_numbers */
-
-
-/* ----------------------------------------------------------------------------
-   -- Cortex M0 Core Configuration
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
- * @{
- */
-
-#define __CM0PLUS_REV                  0x0000    /**< Core revision r0p0 */
-#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
-#define __VTOR_PRESENT                 1         /**< Defines if an MPU is present or not */
-#define __NVIC_PRIO_BITS               2         /**< Number of priority bits implemented in the NVIC */
-#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
-
-#include "core_cm0plus.h"              /* Core Peripheral Access Layer */
-#include "system_MKL25Z4.h"            /* Device specific configuration file */
-
-/**
- * @}
- */ /* end of group Cortex_Core_Configuration */
-
-
-/* ----------------------------------------------------------------------------
-   -- Device Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
- * @{
- */
-
-
-/*
-** Start of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
-  #pragma push
-  #pragma anon_unions
-#elif defined(__CWCC__)
-  #pragma push
-  #pragma cpp_extensions on
-#elif defined(__GNUC__)
-  /* anonymous unions are enabled by default */
-#elif defined(__IAR_SYSTEMS_ICC__)
-  #pragma language=extended
-#else
-  #error Not supported compiler type
-#endif
-
-/* ----------------------------------------------------------------------------
-   -- ADC Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
- * @{
- */
-
-/** ADC - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
-  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
-  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
-  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
-  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
-  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
-  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
-  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
-  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
-  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
-  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
-  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
-  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
-  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
-  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
-  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
-  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
-  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
-       uint8_t RESERVED_0[4];
-  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
-  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
-  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
-  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
-  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
-  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
-  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
-} ADC_Type;
-
-/* ----------------------------------------------------------------------------
-   -- ADC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ADC_Register_Masks ADC Register Masks
- * @{
- */
-
-/* SC1 Bit Fields */
-#define ADC_SC1_ADCH_MASK                        0x1Fu
-#define ADC_SC1_ADCH_SHIFT                       0
-#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
-#define ADC_SC1_DIFF_MASK                        0x20u
-#define ADC_SC1_DIFF_SHIFT                       5
-#define ADC_SC1_AIEN_MASK                        0x40u
-#define ADC_SC1_AIEN_SHIFT                       6
-#define ADC_SC1_COCO_MASK                        0x80u
-#define ADC_SC1_COCO_SHIFT                       7
-/* CFG1 Bit Fields */
-#define ADC_CFG1_ADICLK_MASK                     0x3u
-#define ADC_CFG1_ADICLK_SHIFT                    0
-#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
-#define ADC_CFG1_MODE_MASK                       0xCu
-#define ADC_CFG1_MODE_SHIFT                      2
-#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
-#define ADC_CFG1_ADLSMP_MASK                     0x10u
-#define ADC_CFG1_ADLSMP_SHIFT                    4
-#define ADC_CFG1_ADIV_MASK                       0x60u
-#define ADC_CFG1_ADIV_SHIFT                      5
-#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
-#define ADC_CFG1_ADLPC_MASK                      0x80u
-#define ADC_CFG1_ADLPC_SHIFT                     7
-/* CFG2 Bit Fields */
-#define ADC_CFG2_ADLSTS_MASK                     0x3u
-#define ADC_CFG2_ADLSTS_SHIFT                    0
-#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
-#define ADC_CFG2_ADHSC_MASK                      0x4u
-#define ADC_CFG2_ADHSC_SHIFT                     2
-#define ADC_CFG2_ADACKEN_MASK                    0x8u
-#define ADC_CFG2_ADACKEN_SHIFT                   3
-#define ADC_CFG2_MUXSEL_MASK                     0x10u
-#define ADC_CFG2_MUXSEL_SHIFT                    4
-/* R Bit Fields */
-#define ADC_R_D_MASK                             0xFFFFu
-#define ADC_R_D_SHIFT                            0
-#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
-/* CV1 Bit Fields */
-#define ADC_CV1_CV_MASK                          0xFFFFu
-#define ADC_CV1_CV_SHIFT                         0
-#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
-/* CV2 Bit Fields */
-#define ADC_CV2_CV_MASK                          0xFFFFu
-#define ADC_CV2_CV_SHIFT                         0
-#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
-/* SC2 Bit Fields */
-#define ADC_SC2_REFSEL_MASK                      0x3u
-#define ADC_SC2_REFSEL_SHIFT                     0
-#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
-#define ADC_SC2_DMAEN_MASK                       0x4u
-#define ADC_SC2_DMAEN_SHIFT                      2
-#define ADC_SC2_ACREN_MASK                       0x8u
-#define ADC_SC2_ACREN_SHIFT                      3
-#define ADC_SC2_ACFGT_MASK                       0x10u
-#define ADC_SC2_ACFGT_SHIFT                      4
-#define ADC_SC2_ACFE_MASK                        0x20u
-#define ADC_SC2_ACFE_SHIFT                       5
-#define ADC_SC2_ADTRG_MASK                       0x40u
-#define ADC_SC2_ADTRG_SHIFT                      6
-#define ADC_SC2_ADACT_MASK                       0x80u
-#define ADC_SC2_ADACT_SHIFT                      7
-/* SC3 Bit Fields */
-#define ADC_SC3_AVGS_MASK                        0x3u
-#define ADC_SC3_AVGS_SHIFT                       0
-#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
-#define ADC_SC3_AVGE_MASK                        0x4u
-#define ADC_SC3_AVGE_SHIFT                       2
-#define ADC_SC3_ADCO_MASK                        0x8u
-#define ADC_SC3_ADCO_SHIFT                       3
-#define ADC_SC3_CALF_MASK                        0x40u
-#define ADC_SC3_CALF_SHIFT                       6
-#define ADC_SC3_CAL_MASK                         0x80u
-#define ADC_SC3_CAL_SHIFT                        7
-/* OFS Bit Fields */
-#define ADC_OFS_OFS_MASK                         0xFFFFu
-#define ADC_OFS_OFS_SHIFT                        0
-#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
-/* PG Bit Fields */
-#define ADC_PG_PG_MASK                           0xFFFFu
-#define ADC_PG_PG_SHIFT                          0
-#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
-/* MG Bit Fields */
-#define ADC_MG_MG_MASK                           0xFFFFu
-#define ADC_MG_MG_SHIFT                          0
-#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
-/* CLPD Bit Fields */
-#define ADC_CLPD_CLPD_MASK                       0x3Fu
-#define ADC_CLPD_CLPD_SHIFT                      0
-#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
-/* CLPS Bit Fields */
-#define ADC_CLPS_CLPS_MASK                       0x3Fu
-#define ADC_CLPS_CLPS_SHIFT                      0
-#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
-/* CLP4 Bit Fields */
-#define ADC_CLP4_CLP4_MASK                       0x3FFu
-#define ADC_CLP4_CLP4_SHIFT                      0
-#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
-/* CLP3 Bit Fields */
-#define ADC_CLP3_CLP3_MASK                       0x1FFu
-#define ADC_CLP3_CLP3_SHIFT                      0
-#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
-/* CLP2 Bit Fields */
-#define ADC_CLP2_CLP2_MASK                       0xFFu
-#define ADC_CLP2_CLP2_SHIFT                      0
-#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
-/* CLP1 Bit Fields */
-#define ADC_CLP1_CLP1_MASK                       0x7Fu
-#define ADC_CLP1_CLP1_SHIFT                      0
-#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
-/* CLP0 Bit Fields */
-#define ADC_CLP0_CLP0_MASK                       0x3Fu
-#define ADC_CLP0_CLP0_SHIFT                      0
-#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
-/* CLMD Bit Fields */
-#define ADC_CLMD_CLMD_MASK                       0x3Fu
-#define ADC_CLMD_CLMD_SHIFT                      0
-#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
-/* CLMS Bit Fields */
-#define ADC_CLMS_CLMS_MASK                       0x3Fu
-#define ADC_CLMS_CLMS_SHIFT                      0
-#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
-/* CLM4 Bit Fields */
-#define ADC_CLM4_CLM4_MASK                       0x3FFu
-#define ADC_CLM4_CLM4_SHIFT                      0
-#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
-/* CLM3 Bit Fields */
-#define ADC_CLM3_CLM3_MASK                       0x1FFu
-#define ADC_CLM3_CLM3_SHIFT                      0
-#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
-/* CLM2 Bit Fields */
-#define ADC_CLM2_CLM2_MASK                       0xFFu
-#define ADC_CLM2_CLM2_SHIFT                      0
-#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
-/* CLM1 Bit Fields */
-#define ADC_CLM1_CLM1_MASK                       0x7Fu
-#define ADC_CLM1_CLM1_SHIFT                      0
-#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
-/* CLM0 Bit Fields */
-#define ADC_CLM0_CLM0_MASK                       0x3Fu
-#define ADC_CLM0_CLM0_SHIFT                      0
-#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
-
-/**
- * @}
- */ /* end of group ADC_Register_Masks */
-
-
-/* ADC - Peripheral instance base addresses */
-/** Peripheral ADC0 base address */
-#define ADC0_BASE                                (0x4003B000u)
-/** Peripheral ADC0 base pointer */
-#define ADC0                                     ((ADC_Type *)ADC0_BASE)
-/** Array initializer of ADC peripheral base pointers */
-#define ADC_BASES                                { ADC0 }
-
-/**
- * @}
- */ /* end of group ADC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- CMP Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
- * @{
- */
-
-/** CMP - Register Layout Typedef */
-typedef struct {
-  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
-  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
-  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
-  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
-  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
-  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
-} CMP_Type;
-
-/* ----------------------------------------------------------------------------
-   -- CMP Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMP_Register_Masks CMP Register Masks
- * @{
- */
-
-/* CR0 Bit Fields */
-#define CMP_CR0_HYSTCTR_MASK                     0x3u
-#define CMP_CR0_HYSTCTR_SHIFT                    0
-#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
-#define CMP_CR0_FILTER_CNT_MASK                  0x70u
-#define CMP_CR0_FILTER_CNT_SHIFT                 4
-#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
-/* CR1 Bit Fields */
-#define CMP_CR1_EN_MASK                          0x1u
-#define CMP_CR1_EN_SHIFT                         0
-#define CMP_CR1_OPE_MASK                         0x2u
-#define CMP_CR1_OPE_SHIFT                        1
-#define CMP_CR1_COS_MASK                         0x4u
-#define CMP_CR1_COS_SHIFT                        2
-#define CMP_CR1_INV_MASK                         0x8u
-#define CMP_CR1_INV_SHIFT                        3
-#define CMP_CR1_PMODE_MASK                       0x10u
-#define CMP_CR1_PMODE_SHIFT                      4
-#define CMP_CR1_TRIGM_MASK                       0x20u
-#define CMP_CR1_TRIGM_SHIFT                      5
-#define CMP_CR1_WE_MASK                          0x40u
-#define CMP_CR1_WE_SHIFT                         6
-#define CMP_CR1_SE_MASK                          0x80u
-#define CMP_CR1_SE_SHIFT                         7
-/* FPR Bit Fields */
-#define CMP_FPR_FILT_PER_MASK                    0xFFu
-#define CMP_FPR_FILT_PER_SHIFT                   0
-#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
-/* SCR Bit Fields */
-#define CMP_SCR_COUT_MASK                        0x1u
-#define CMP_SCR_COUT_SHIFT                       0
-#define CMP_SCR_CFF_MASK                         0x2u
-#define CMP_SCR_CFF_SHIFT                        1
-#define CMP_SCR_CFR_MASK                         0x4u
-#define CMP_SCR_CFR_SHIFT                        2
-#define CMP_SCR_IEF_MASK                         0x8u
-#define CMP_SCR_IEF_SHIFT                        3
-#define CMP_SCR_IER_MASK                         0x10u
-#define CMP_SCR_IER_SHIFT                        4
-#define CMP_SCR_DMAEN_MASK                       0x40u
-#define CMP_SCR_DMAEN_SHIFT                      6
-/* DACCR Bit Fields */
-#define CMP_DACCR_VOSEL_MASK                     0x3Fu
-#define CMP_DACCR_VOSEL_SHIFT                    0
-#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
-#define CMP_DACCR_VRSEL_MASK                     0x40u
-#define CMP_DACCR_VRSEL_SHIFT                    6
-#define CMP_DACCR_DACEN_MASK                     0x80u
-#define CMP_DACCR_DACEN_SHIFT                    7
-/* MUXCR Bit Fields */
-#define CMP_MUXCR_MSEL_MASK                      0x7u
-#define CMP_MUXCR_MSEL_SHIFT                     0
-#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
-#define CMP_MUXCR_PSEL_MASK                      0x38u
-#define CMP_MUXCR_PSEL_SHIFT                     3
-#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
-#define CMP_MUXCR_PSTM_MASK                      0x40u
-#define CMP_MUXCR_PSTM_SHIFT                     6
-
-/**
- * @}
- */ /* end of group CMP_Register_Masks */
-
-
-/* CMP - Peripheral instance base addresses */
-/** Peripheral CMP0 base address */
-#define CMP0_BASE                                (0x40073000u)
-/** Peripheral CMP0 base pointer */
-#define CMP0                                     ((CMP_Type *)CMP0_BASE)
-/** Array initializer of CMP peripheral base pointers */
-#define CMP_BASES                                { CMP0 }
-
-/**
- * @}
- */ /* end of group CMP_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- DAC Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
- * @{
- */
-
-/** DAC - Register Layout Typedef */
-typedef struct {
-  struct {                                         /* offset: 0x0, array step: 0x2 */
-    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
-    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
-  } DAT[2];
-       uint8_t RESERVED_0[28];
-  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
-  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
-  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
-  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
-} DAC_Type;
-
-/* ----------------------------------------------------------------------------
-   -- DAC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DAC_Register_Masks DAC Register Masks
- * @{
- */
-
-/* DATL Bit Fields */
-#define DAC_DATL_DATA0_MASK                      0xFFu
-#define DAC_DATL_DATA0_SHIFT                     0
-#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
-/* DATH Bit Fields */
-#define DAC_DATH_DATA1_MASK                      0xFu
-#define DAC_DATH_DATA1_SHIFT                     0
-#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
-/* SR Bit Fields */
-#define DAC_SR_DACBFRPBF_MASK                    0x1u
-#define DAC_SR_DACBFRPBF_SHIFT                   0
-#define DAC_SR_DACBFRPTF_MASK                    0x2u
-#define DAC_SR_DACBFRPTF_SHIFT                   1
-/* C0 Bit Fields */
-#define DAC_C0_DACBBIEN_MASK                     0x1u
-#define DAC_C0_DACBBIEN_SHIFT                    0
-#define DAC_C0_DACBTIEN_MASK                     0x2u
-#define DAC_C0_DACBTIEN_SHIFT                    1
-#define DAC_C0_LPEN_MASK                         0x8u
-#define DAC_C0_LPEN_SHIFT                        3
-#define DAC_C0_DACSWTRG_MASK                     0x10u
-#define DAC_C0_DACSWTRG_SHIFT                    4
-#define DAC_C0_DACTRGSEL_MASK                    0x20u
-#define DAC_C0_DACTRGSEL_SHIFT                   5
-#define DAC_C0_DACRFS_MASK                       0x40u
-#define DAC_C0_DACRFS_SHIFT                      6
-#define DAC_C0_DACEN_MASK                        0x80u
-#define DAC_C0_DACEN_SHIFT                       7
-/* C1 Bit Fields */
-#define DAC_C1_DACBFEN_MASK                      0x1u
-#define DAC_C1_DACBFEN_SHIFT                     0
-#define DAC_C1_DACBFMD_MASK                      0x4u
-#define DAC_C1_DACBFMD_SHIFT                     2
-#define DAC_C1_DMAEN_MASK                        0x80u
-#define DAC_C1_DMAEN_SHIFT                       7
-/* C2 Bit Fields */
-#define DAC_C2_DACBFUP_MASK                      0x1u
-#define DAC_C2_DACBFUP_SHIFT                     0
-#define DAC_C2_DACBFRP_MASK                      0x10u
-#define DAC_C2_DACBFRP_SHIFT                     4
-
-/**
- * @}
- */ /* end of group DAC_Register_Masks */
-
-
-/* DAC - Peripheral instance base addresses */
-/** Peripheral DAC0 base address */
-#define DAC0_BASE                                (0x4003F000u)
-/** Peripheral DAC0 base pointer */
-#define DAC0                                     ((DAC_Type *)DAC0_BASE)
-/** Array initializer of DAC peripheral base pointers */
-#define DAC_BASES                                { DAC0 }
-
-/**
- * @}
- */ /* end of group DAC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- DMA Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
- * @{
- */
-
-/** DMA - Register Layout Typedef */
-typedef struct {
-  union {                                          /* offset: 0x0 */
-    __IO uint8_t REQC_ARR[4];                        /**< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 */
-  };
-       uint8_t RESERVED_0[252];
-  struct {                                         /* offset: 0x100, array step: 0x10 */
-    __IO uint32_t SAR;                               /**< Source Address Register, array offset: 0x100, array step: 0x10 */
-    __IO uint32_t DAR;                               /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
-    union {                                          /* offset: 0x108, array step: 0x10 */
-      __IO uint32_t DSR_BCR;                           /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
-      struct {                                         /* offset: 0x108, array step: 0x10 */
-             uint8_t RESERVED_0[3];
-        __IO uint8_t DSR;                                /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
-      } DMA_DSR_ACCESS8BIT;
-    };
-    __IO uint32_t DCR;                               /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
-  } DMA[4];
-} DMA_Type;
-
-/* ----------------------------------------------------------------------------
-   -- DMA Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMA_Register_Masks DMA Register Masks
- * @{
- */
-
-/* REQC_ARR Bit Fields */
-#define DMA_REQC_ARR_DMAC_MASK                   0xFu
-#define DMA_REQC_ARR_DMAC_SHIFT                  0
-#define DMA_REQC_ARR_DMAC(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK)
-#define DMA_REQC_ARR_CFSM_MASK                   0x80u
-#define DMA_REQC_ARR_CFSM_SHIFT                  7
-/* SAR Bit Fields */
-#define DMA_SAR_SAR_MASK                         0xFFFFFFFFu
-#define DMA_SAR_SAR_SHIFT                        0
-#define DMA_SAR_SAR(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
-/* DAR Bit Fields */
-#define DMA_DAR_DAR_MASK                         0xFFFFFFFFu
-#define DMA_DAR_DAR_SHIFT                        0
-#define DMA_DAR_DAR(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
-/* DSR_BCR Bit Fields */
-#define DMA_DSR_BCR_BCR_MASK                     0xFFFFFFu
-#define DMA_DSR_BCR_BCR_SHIFT                    0
-#define DMA_DSR_BCR_BCR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
-#define DMA_DSR_BCR_DONE_MASK                    0x1000000u
-#define DMA_DSR_BCR_DONE_SHIFT                   24
-#define DMA_DSR_BCR_BSY_MASK                     0x2000000u
-#define DMA_DSR_BCR_BSY_SHIFT                    25
-#define DMA_DSR_BCR_REQ_MASK                     0x4000000u
-#define DMA_DSR_BCR_REQ_SHIFT                    26
-#define DMA_DSR_BCR_BED_MASK                     0x10000000u
-#define DMA_DSR_BCR_BED_SHIFT                    28
-#define DMA_DSR_BCR_BES_MASK                     0x20000000u
-#define DMA_DSR_BCR_BES_SHIFT                    29
-#define DMA_DSR_BCR_CE_MASK                      0x40000000u
-#define DMA_DSR_BCR_CE_SHIFT                     30
-/* DCR Bit Fields */
-#define DMA_DCR_LCH2_MASK                        0x3u
-#define DMA_DCR_LCH2_SHIFT                       0
-#define DMA_DCR_LCH2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
-#define DMA_DCR_LCH1_MASK                        0xCu
-#define DMA_DCR_LCH1_SHIFT                       2
-#define DMA_DCR_LCH1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
-#define DMA_DCR_LINKCC_MASK                      0x30u
-#define DMA_DCR_LINKCC_SHIFT                     4
-#define DMA_DCR_LINKCC(x)                        (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
-#define DMA_DCR_D_REQ_MASK                       0x80u
-#define DMA_DCR_D_REQ_SHIFT                      7
-#define DMA_DCR_DMOD_MASK                        0xF00u
-#define DMA_DCR_DMOD_SHIFT                       8
-#define DMA_DCR_DMOD(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
-#define DMA_DCR_SMOD_MASK                        0xF000u
-#define DMA_DCR_SMOD_SHIFT                       12
-#define DMA_DCR_SMOD(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
-#define DMA_DCR_START_MASK                       0x10000u
-#define DMA_DCR_START_SHIFT                      16
-#define DMA_DCR_DSIZE_MASK                       0x60000u
-#define DMA_DCR_DSIZE_SHIFT                      17
-#define DMA_DCR_DSIZE(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
-#define DMA_DCR_DINC_MASK                        0x80000u
-#define DMA_DCR_DINC_SHIFT                       19
-#define DMA_DCR_SSIZE_MASK                       0x300000u
-#define DMA_DCR_SSIZE_SHIFT                      20
-#define DMA_DCR_SSIZE(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
-#define DMA_DCR_SINC_MASK                        0x400000u
-#define DMA_DCR_SINC_SHIFT                       22
-#define DMA_DCR_EADREQ_MASK                      0x800000u
-#define DMA_DCR_EADREQ_SHIFT                     23
-#define DMA_DCR_AA_MASK                          0x10000000u
-#define DMA_DCR_AA_SHIFT                         28
-#define DMA_DCR_CS_MASK                          0x20000000u
-#define DMA_DCR_CS_SHIFT                         29
-#define DMA_DCR_ERQ_MASK                         0x40000000u
-#define DMA_DCR_ERQ_SHIFT                        30
-#define DMA_DCR_EINT_MASK                        0x80000000u
-#define DMA_DCR_EINT_SHIFT                       31
-
-/**
- * @}
- */ /* end of group DMA_Register_Masks */
-
-
-/* DMA - Peripheral instance base addresses */
-/** Peripheral DMA base address */
-#define DMA_BASE                                 (0x40008000u)
-/** Peripheral DMA base pointer */
-#define DMA0                                     ((DMA_Type *)DMA_BASE)
-/** Array initializer of DMA peripheral base pointers */
-#define DMA_BASES                                { DMA0 }
-
-/**
- * @}
- */ /* end of group DMA_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- DMAMUX Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
- * @{
- */
-
-/** DMAMUX - Register Layout Typedef */
-typedef struct {
-  __IO uint8_t CHCFG[4];                           /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
-} DMAMUX_Type;
-
-/* ----------------------------------------------------------------------------
-   -- DMAMUX Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
- * @{
- */
-
-/* CHCFG Bit Fields */
-#define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
-#define DMAMUX_CHCFG_SOURCE_SHIFT                0
-#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
-#define DMAMUX_CHCFG_TRIG_MASK                   0x40u
-#define DMAMUX_CHCFG_TRIG_SHIFT                  6
-#define DMAMUX_CHCFG_ENBL_MASK                   0x80u
-#define DMAMUX_CHCFG_ENBL_SHIFT                  7
-
-/**
- * @}
- */ /* end of group DMAMUX_Register_Masks */
-
-
-/* DMAMUX - Peripheral instance base addresses */
-/** Peripheral DMAMUX0 base address */
-#define DMAMUX0_BASE                             (0x40021000u)
-/** Peripheral DMAMUX0 base pointer */
-#define DMAMUX0                                  ((DMAMUX_Type *)DMAMUX0_BASE)
-/** Array initializer of DMAMUX peripheral base pointers */
-#define DMAMUX_BASES                             { DMAMUX0 }
-
-/**
- * @}
- */ /* end of group DMAMUX_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- FGPIO Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
- * @{
- */
-
-/** FGPIO - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
-  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
-  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
-  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
-  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
-  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
-} FGPIO_Type;
-
-/* ----------------------------------------------------------------------------
-   -- FGPIO Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
- * @{
- */
-
-/* PDOR Bit Fields */
-#define FGPIO_PDOR_PDO_MASK                      0xFFFFFFFFu
-#define FGPIO_PDOR_PDO_SHIFT                     0
-#define FGPIO_PDOR_PDO(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define FGPIO_PSOR_PTSO_MASK                     0xFFFFFFFFu
-#define FGPIO_PSOR_PTSO_SHIFT                    0
-#define FGPIO_PSOR_PTSO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define FGPIO_PCOR_PTCO_MASK                     0xFFFFFFFFu
-#define FGPIO_PCOR_PTCO_SHIFT                    0
-#define FGPIO_PCOR_PTCO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define FGPIO_PTOR_PTTO_MASK                     0xFFFFFFFFu
-#define FGPIO_PTOR_PTTO_SHIFT                    0
-#define FGPIO_PTOR_PTTO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define FGPIO_PDIR_PDI_MASK                      0xFFFFFFFFu
-#define FGPIO_PDIR_PDI_SHIFT                     0
-#define FGPIO_PDIR_PDI(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define FGPIO_PDDR_PDD_MASK                      0xFFFFFFFFu
-#define FGPIO_PDDR_PDD_SHIFT                     0
-#define FGPIO_PDDR_PDD(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
-
-/**
- * @}
- */ /* end of group FGPIO_Register_Masks */
-
-
-/* FGPIO - Peripheral instance base addresses */
-/** Peripheral FPTA base address */
-#define FPTA_BASE                                (0xF80FF000u)
-/** Peripheral FPTA base pointer */
-#define FPTA                                     ((FGPIO_Type *)FPTA_BASE)
-/** Peripheral FPTB base address */
-#define FPTB_BASE                                (0xF80FF040u)
-/** Peripheral FPTB base pointer */
-#define FPTB                                     ((FGPIO_Type *)FPTB_BASE)
-/** Peripheral FPTC base address */
-#define FPTC_BASE                                (0xF80FF080u)
-/** Peripheral FPTC base pointer */
-#define FPTC                                     ((FGPIO_Type *)FPTC_BASE)
-/** Peripheral FPTD base address */
-#define FPTD_BASE                                (0xF80FF0C0u)
-/** Peripheral FPTD base pointer */
-#define FPTD                                     ((FGPIO_Type *)FPTD_BASE)
-/** Peripheral FPTE base address */
-#define FPTE_BASE                                (0xF80FF100u)
-/** Peripheral FPTE base pointer */
-#define FPTE                                     ((FGPIO_Type *)FPTE_BASE)
-/** Array initializer of FGPIO peripheral base pointers */
-#define FGPIO_BASES                              { FPTA, FPTB, FPTC, FPTD, FPTE }
-
-/**
- * @}
- */ /* end of group FGPIO_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- FTFA Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
- * @{
- */
-
-/** FTFA - Register Layout Typedef */
-typedef struct {
-  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
-  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
-  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
-  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
-  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
-  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
-  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
-  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
-  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
-  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
-  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
-  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
-  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
-  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
-  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
-  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
-  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
-  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
-  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
-  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
-} FTFA_Type;
-
-/* ----------------------------------------------------------------------------
-   -- FTFA Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTFA_Register_Masks FTFA Register Masks
- * @{
- */
-
-/* FSTAT Bit Fields */
-#define FTFA_FSTAT_MGSTAT0_MASK                  0x1u
-#define FTFA_FSTAT_MGSTAT0_SHIFT                 0
-#define FTFA_FSTAT_FPVIOL_MASK                   0x10u
-#define FTFA_FSTAT_FPVIOL_SHIFT                  4
-#define FTFA_FSTAT_ACCERR_MASK                   0x20u
-#define FTFA_FSTAT_ACCERR_SHIFT                  5
-#define FTFA_FSTAT_RDCOLERR_MASK                 0x40u
-#define FTFA_FSTAT_RDCOLERR_SHIFT                6
-#define FTFA_FSTAT_CCIF_MASK                     0x80u
-#define FTFA_FSTAT_CCIF_SHIFT                    7
-/* FCNFG Bit Fields */
-#define FTFA_FCNFG_ERSSUSP_MASK                  0x10u
-#define FTFA_FCNFG_ERSSUSP_SHIFT                 4
-#define FTFA_FCNFG_ERSAREQ_MASK                  0x20u
-#define FTFA_FCNFG_ERSAREQ_SHIFT                 5
-#define FTFA_FCNFG_RDCOLLIE_MASK                 0x40u
-#define FTFA_FCNFG_RDCOLLIE_SHIFT                6
-#define FTFA_FCNFG_CCIE_MASK                     0x80u
-#define FTFA_FCNFG_CCIE_SHIFT                    7
-/* FSEC Bit Fields */
-#define FTFA_FSEC_SEC_MASK                       0x3u
-#define FTFA_FSEC_SEC_SHIFT                      0
-#define FTFA_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
-#define FTFA_FSEC_FSLACC_MASK                    0xCu
-#define FTFA_FSEC_FSLACC_SHIFT                   2
-#define FTFA_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
-#define FTFA_FSEC_MEEN_MASK                      0x30u
-#define FTFA_FSEC_MEEN_SHIFT                     4
-#define FTFA_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
-#define FTFA_FSEC_KEYEN_MASK                     0xC0u
-#define FTFA_FSEC_KEYEN_SHIFT                    6
-#define FTFA_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define FTFA_FOPT_OPT_MASK                       0xFFu
-#define FTFA_FOPT_OPT_SHIFT                      0
-#define FTFA_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
-/* FCCOB3 Bit Fields */
-#define FTFA_FCCOB3_CCOBn_MASK                   0xFFu
-#define FTFA_FCCOB3_CCOBn_SHIFT                  0
-#define FTFA_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
-/* FCCOB2 Bit Fields */
-#define FTFA_FCCOB2_CCOBn_MASK                   0xFFu
-#define FTFA_FCCOB2_CCOBn_SHIFT                  0
-#define FTFA_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
-/* FCCOB1 Bit Fields */
-#define FTFA_FCCOB1_CCOBn_MASK                   0xFFu
-#define FTFA_FCCOB1_CCOBn_SHIFT                  0
-#define FTFA_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
-/* FCCOB0 Bit Fields */
-#define FTFA_FCCOB0_CCOBn_MASK                   0xFFu
-#define FTFA_FCCOB0_CCOBn_SHIFT                  0
-#define FTFA_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
-/* FCCOB7 Bit Fields */
-#define FTFA_FCCOB7_CCOBn_MASK                   0xFFu
-#define FTFA_FCCOB7_CCOBn_SHIFT                  0
-#define FTFA_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
-/* FCCOB6 Bit Fields */
-#define FTFA_FCCOB6_CCOBn_MASK                   0xFFu
-#define FTFA_FCCOB6_CCOBn_SHIFT                  0
-#define FTFA_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
-/* FCCOB5 Bit Fields */
-#define FTFA_FCCOB5_CCOBn_MASK                   0xFFu
-#define FTFA_FCCOB5_CCOBn_SHIFT                  0
-#define FTFA_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
-/* FCCOB4 Bit Fields */
-#define FTFA_FCCOB4_CCOBn_MASK                   0xFFu
-#define FTFA_FCCOB4_CCOBn_SHIFT                  0
-#define FTFA_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
-/* FCCOBB Bit Fields */
-#define FTFA_FCCOBB_CCOBn_MASK                   0xFFu
-#define FTFA_FCCOBB_CCOBn_SHIFT                  0
-#define FTFA_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
-/* FCCOBA Bit Fields */
-#define FTFA_FCCOBA_CCOBn_MASK                   0xFFu
-#define FTFA_FCCOBA_CCOBn_SHIFT                  0
-#define FTFA_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
-/* FCCOB9 Bit Fields */
-#define FTFA_FCCOB9_CCOBn_MASK                   0xFFu
-#define FTFA_FCCOB9_CCOBn_SHIFT                  0
-#define FTFA_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
-/* FCCOB8 Bit Fields */
-#define FTFA_FCCOB8_CCOBn_MASK                   0xFFu
-#define FTFA_FCCOB8_CCOBn_SHIFT                  0
-#define FTFA_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
-/* FPROT3 Bit Fields */
-#define FTFA_FPROT3_PROT_MASK                    0xFFu
-#define FTFA_FPROT3_PROT_SHIFT                   0
-#define FTFA_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define FTFA_FPROT2_PROT_MASK                    0xFFu
-#define FTFA_FPROT2_PROT_SHIFT                   0
-#define FTFA_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define FTFA_FPROT1_PROT_MASK                    0xFFu
-#define FTFA_FPROT1_PROT_SHIFT                   0
-#define FTFA_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define FTFA_FPROT0_PROT_MASK                    0xFFu
-#define FTFA_FPROT0_PROT_SHIFT                   0
-#define FTFA_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
-
-/**
- * @}
- */ /* end of group FTFA_Register_Masks */
-
-
-/* FTFA - Peripheral instance base addresses */
-/** Peripheral FTFA base address */
-#define FTFA_BASE                                (0x40020000u)
-/** Peripheral FTFA base pointer */
-#define FTFA                                     ((FTFA_Type *)FTFA_BASE)
-/** Array initializer of FTFA peripheral base pointers */
-#define FTFA_BASES                               { FTFA }
-
-/**
- * @}
- */ /* end of group FTFA_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- GPIO Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
- * @{
- */
-
-/** GPIO - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
-  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
-  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
-  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
-  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
-  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
-} GPIO_Type;
-
-/* ----------------------------------------------------------------------------
-   -- GPIO Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup GPIO_Register_Masks GPIO Register Masks
- * @{
- */
-
-/* PDOR Bit Fields */
-#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
-#define GPIO_PDOR_PDO_SHIFT                      0
-#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
-#define GPIO_PSOR_PTSO_SHIFT                     0
-#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
-#define GPIO_PCOR_PTCO_SHIFT                     0
-#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
-#define GPIO_PTOR_PTTO_SHIFT                     0
-#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
-#define GPIO_PDIR_PDI_SHIFT                      0
-#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
-#define GPIO_PDDR_PDD_SHIFT                      0
-#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
-
-/**
- * @}
- */ /* end of group GPIO_Register_Masks */
-
-
-/* GPIO - Peripheral instance base addresses */
-/** Peripheral PTA base address */
-#define PTA_BASE                                 (0x400FF000u)
-/** Peripheral PTA base pointer */
-#define PTA                                      ((GPIO_Type *)PTA_BASE)
-/** Peripheral PTB base address */
-#define PTB_BASE                                 (0x400FF040u)
-/** Peripheral PTB base pointer */
-#define PTB                                      ((GPIO_Type *)PTB_BASE)
-/** Peripheral PTC base address */
-#define PTC_BASE                                 (0x400FF080u)
-/** Peripheral PTC base pointer */
-#define PTC                                      ((GPIO_Type *)PTC_BASE)
-/** Peripheral PTD base address */
-#define PTD_BASE                                 (0x400FF0C0u)
-/** Peripheral PTD base pointer */
-#define PTD                                      ((GPIO_Type *)PTD_BASE)
-/** Peripheral PTE base address */
-#define PTE_BASE                                 (0x400FF100u)
-/** Peripheral PTE base pointer */
-#define PTE                                      ((GPIO_Type *)PTE_BASE)
-/** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASES                               { PTA, PTB, PTC, PTD, PTE }
-
-/**
- * @}
- */ /* end of group GPIO_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- I2C Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
- * @{
- */
-
-/** I2C - Register Layout Typedef */
-typedef struct {
-  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
-  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
-  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
-  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
-  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
-  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
-  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
-  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
-  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
-  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
-  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
-  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
-} I2C_Type;
-
-/* ----------------------------------------------------------------------------
-   -- I2C Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2C_Register_Masks I2C Register Masks
- * @{
- */
-
-/* A1 Bit Fields */
-#define I2C_A1_AD_MASK                           0xFEu
-#define I2C_A1_AD_SHIFT                          1
-#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
-/* F Bit Fields */
-#define I2C_F_ICR_MASK                           0x3Fu
-#define I2C_F_ICR_SHIFT                          0
-#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
-#define I2C_F_MULT_MASK                          0xC0u
-#define I2C_F_MULT_SHIFT                         6
-#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
-/* C1 Bit Fields */
-#define I2C_C1_DMAEN_MASK                        0x1u
-#define I2C_C1_DMAEN_SHIFT                       0
-#define I2C_C1_WUEN_MASK                         0x2u
-#define I2C_C1_WUEN_SHIFT                        1
-#define I2C_C1_RSTA_MASK                         0x4u
-#define I2C_C1_RSTA_SHIFT                        2
-#define I2C_C1_TXAK_MASK                         0x8u
-#define I2C_C1_TXAK_SHIFT                        3
-#define I2C_C1_TX_MASK                           0x10u
-#define I2C_C1_TX_SHIFT                          4
-#define I2C_C1_MST_MASK                          0x20u
-#define I2C_C1_MST_SHIFT                         5
-#define I2C_C1_IICIE_MASK                        0x40u
-#define I2C_C1_IICIE_SHIFT                       6
-#define I2C_C1_IICEN_MASK                        0x80u
-#define I2C_C1_IICEN_SHIFT                       7
-/* S Bit Fields */
-#define I2C_S_RXAK_MASK                          0x1u
-#define I2C_S_RXAK_SHIFT                         0
-#define I2C_S_IICIF_MASK                         0x2u
-#define I2C_S_IICIF_SHIFT                        1
-#define I2C_S_SRW_MASK                           0x4u
-#define I2C_S_SRW_SHIFT                          2
-#define I2C_S_RAM_MASK                           0x8u
-#define I2C_S_RAM_SHIFT                          3
-#define I2C_S_ARBL_MASK                          0x10u
-#define I2C_S_ARBL_SHIFT                         4
-#define I2C_S_BUSY_MASK                          0x20u
-#define I2C_S_BUSY_SHIFT                         5
-#define I2C_S_IAAS_MASK                          0x40u
-#define I2C_S_IAAS_SHIFT                         6
-#define I2C_S_TCF_MASK                           0x80u
-#define I2C_S_TCF_SHIFT                          7
-/* D Bit Fields */
-#define I2C_D_DATA_MASK                          0xFFu
-#define I2C_D_DATA_SHIFT                         0
-#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
-/* C2 Bit Fields */
-#define I2C_C2_AD_MASK                           0x7u
-#define I2C_C2_AD_SHIFT                          0
-#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
-#define I2C_C2_RMEN_MASK                         0x8u
-#define I2C_C2_RMEN_SHIFT                        3
-#define I2C_C2_SBRC_MASK                         0x10u
-#define I2C_C2_SBRC_SHIFT                        4
-#define I2C_C2_HDRS_MASK                         0x20u
-#define I2C_C2_HDRS_SHIFT                        5
-#define I2C_C2_ADEXT_MASK                        0x40u
-#define I2C_C2_ADEXT_SHIFT                       6
-#define I2C_C2_GCAEN_MASK                        0x80u
-#define I2C_C2_GCAEN_SHIFT                       7
-/* FLT Bit Fields */
-#define I2C_FLT_FLT_MASK                         0x1Fu
-#define I2C_FLT_FLT_SHIFT                        0
-#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
-#define I2C_FLT_STOPIE_MASK                      0x20u
-#define I2C_FLT_STOPIE_SHIFT                     5
-#define I2C_FLT_STOPF_MASK                       0x40u
-#define I2C_FLT_STOPF_SHIFT                      6
-#define I2C_FLT_SHEN_MASK                        0x80u
-#define I2C_FLT_SHEN_SHIFT                       7
-/* RA Bit Fields */
-#define I2C_RA_RAD_MASK                          0xFEu
-#define I2C_RA_RAD_SHIFT                         1
-#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
-/* SMB Bit Fields */
-#define I2C_SMB_SHTF2IE_MASK                     0x1u
-#define I2C_SMB_SHTF2IE_SHIFT                    0
-#define I2C_SMB_SHTF2_MASK                       0x2u
-#define I2C_SMB_SHTF2_SHIFT                      1
-#define I2C_SMB_SHTF1_MASK                       0x4u
-#define I2C_SMB_SHTF1_SHIFT                      2
-#define I2C_SMB_SLTF_MASK                        0x8u
-#define I2C_SMB_SLTF_SHIFT                       3
-#define I2C_SMB_TCKSEL_MASK                      0x10u
-#define I2C_SMB_TCKSEL_SHIFT                     4
-#define I2C_SMB_SIICAEN_MASK                     0x20u
-#define I2C_SMB_SIICAEN_SHIFT                    5
-#define I2C_SMB_ALERTEN_MASK                     0x40u
-#define I2C_SMB_ALERTEN_SHIFT                    6
-#define I2C_SMB_FACK_MASK                        0x80u
-#define I2C_SMB_FACK_SHIFT                       7
-/* A2 Bit Fields */
-#define I2C_A2_SAD_MASK                          0xFEu
-#define I2C_A2_SAD_SHIFT                         1
-#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
-/* SLTH Bit Fields */
-#define I2C_SLTH_SSLT_MASK                       0xFFu
-#define I2C_SLTH_SSLT_SHIFT                      0
-#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
-/* SLTL Bit Fields */
-#define I2C_SLTL_SSLT_MASK                       0xFFu
-#define I2C_SLTL_SSLT_SHIFT                      0
-#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
-
-/**
- * @}
- */ /* end of group I2C_Register_Masks */
-
-
-/* I2C - Peripheral instance base addresses */
-/** Peripheral I2C0 base address */
-#define I2C0_BASE                                (0x40066000u)
-/** Peripheral I2C0 base pointer */
-#define I2C0                                     ((I2C_Type *)I2C0_BASE)
-/** Peripheral I2C1 base address */
-#define I2C1_BASE                                (0x40067000u)
-/** Peripheral I2C1 base pointer */
-#define I2C1                                     ((I2C_Type *)I2C1_BASE)
-/** Array initializer of I2C peripheral base pointers */
-#define I2C_BASES                                { I2C0, I2C1 }
-
-/**
- * @}
- */ /* end of group I2C_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- LLWU Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
- * @{
- */
-
-/** LLWU - Register Layout Typedef */
-typedef struct {
-  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
-  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
-  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
-  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
-  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
-  __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
-  __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
-  __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
-  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
-  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
-} LLWU_Type;
-
-/* ----------------------------------------------------------------------------
-   -- LLWU Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LLWU_Register_Masks LLWU Register Masks
- * @{
- */
-
-/* PE1 Bit Fields */
-#define LLWU_PE1_WUPE0_MASK                      0x3u
-#define LLWU_PE1_WUPE0_SHIFT                     0
-#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
-#define LLWU_PE1_WUPE1_MASK                      0xCu
-#define LLWU_PE1_WUPE1_SHIFT                     2
-#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
-#define LLWU_PE1_WUPE2_MASK                      0x30u
-#define LLWU_PE1_WUPE2_SHIFT                     4
-#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
-#define LLWU_PE1_WUPE3_MASK                      0xC0u
-#define LLWU_PE1_WUPE3_SHIFT                     6
-#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
-/* PE2 Bit Fields */
-#define LLWU_PE2_WUPE4_MASK                      0x3u
-#define LLWU_PE2_WUPE4_SHIFT                     0
-#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
-#define LLWU_PE2_WUPE5_MASK                      0xCu
-#define LLWU_PE2_WUPE5_SHIFT                     2
-#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
-#define LLWU_PE2_WUPE6_MASK                      0x30u
-#define LLWU_PE2_WUPE6_SHIFT                     4
-#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
-#define LLWU_PE2_WUPE7_MASK                      0xC0u
-#define LLWU_PE2_WUPE7_SHIFT                     6
-#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
-/* PE3 Bit Fields */
-#define LLWU_PE3_WUPE8_MASK                      0x3u
-#define LLWU_PE3_WUPE8_SHIFT                     0
-#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
-#define LLWU_PE3_WUPE9_MASK                      0xCu
-#define LLWU_PE3_WUPE9_SHIFT                     2
-#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
-#define LLWU_PE3_WUPE10_MASK                     0x30u
-#define LLWU_PE3_WUPE10_SHIFT                    4
-#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
-#define LLWU_PE3_WUPE11_MASK                     0xC0u
-#define LLWU_PE3_WUPE11_SHIFT                    6
-#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
-/* PE4 Bit Fields */
-#define LLWU_PE4_WUPE12_MASK                     0x3u
-#define LLWU_PE4_WUPE12_SHIFT                    0
-#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
-#define LLWU_PE4_WUPE13_MASK                     0xCu
-#define LLWU_PE4_WUPE13_SHIFT                    2
-#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
-#define LLWU_PE4_WUPE14_MASK                     0x30u
-#define LLWU_PE4_WUPE14_SHIFT                    4
-#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
-#define LLWU_PE4_WUPE15_MASK                     0xC0u
-#define LLWU_PE4_WUPE15_SHIFT                    6
-#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
-/* ME Bit Fields */
-#define LLWU_ME_WUME0_MASK                       0x1u
-#define LLWU_ME_WUME0_SHIFT                      0
-#define LLWU_ME_WUME1_MASK                       0x2u
-#define LLWU_ME_WUME1_SHIFT                      1
-#define LLWU_ME_WUME2_MASK                       0x4u
-#define LLWU_ME_WUME2_SHIFT                      2
-#define LLWU_ME_WUME3_MASK                       0x8u
-#define LLWU_ME_WUME3_SHIFT                      3
-#define LLWU_ME_WUME4_MASK                       0x10u
-#define LLWU_ME_WUME4_SHIFT                      4
-#define LLWU_ME_WUME5_MASK                       0x20u
-#define LLWU_ME_WUME5_SHIFT                      5
-#define LLWU_ME_WUME6_MASK                       0x40u
-#define LLWU_ME_WUME6_SHIFT                      6
-#define LLWU_ME_WUME7_MASK                       0x80u
-#define LLWU_ME_WUME7_SHIFT                      7
-/* F1 Bit Fields */
-#define LLWU_F1_WUF0_MASK                        0x1u
-#define LLWU_F1_WUF0_SHIFT                       0
-#define LLWU_F1_WUF1_MASK                        0x2u
-#define LLWU_F1_WUF1_SHIFT                       1
-#define LLWU_F1_WUF2_MASK                        0x4u
-#define LLWU_F1_WUF2_SHIFT                       2
-#define LLWU_F1_WUF3_MASK                        0x8u
-#define LLWU_F1_WUF3_SHIFT                       3
-#define LLWU_F1_WUF4_MASK                        0x10u
-#define LLWU_F1_WUF4_SHIFT                       4
-#define LLWU_F1_WUF5_MASK                        0x20u
-#define LLWU_F1_WUF5_SHIFT                       5
-#define LLWU_F1_WUF6_MASK                        0x40u
-#define LLWU_F1_WUF6_SHIFT                       6
-#define LLWU_F1_WUF7_MASK                        0x80u
-#define LLWU_F1_WUF7_SHIFT                       7
-/* F2 Bit Fields */
-#define LLWU_F2_WUF8_MASK                        0x1u
-#define LLWU_F2_WUF8_SHIFT                       0
-#define LLWU_F2_WUF9_MASK                        0x2u
-#define LLWU_F2_WUF9_SHIFT                       1
-#define LLWU_F2_WUF10_MASK                       0x4u
-#define LLWU_F2_WUF10_SHIFT                      2
-#define LLWU_F2_WUF11_MASK                       0x8u
-#define LLWU_F2_WUF11_SHIFT                      3
-#define LLWU_F2_WUF12_MASK                       0x10u
-#define LLWU_F2_WUF12_SHIFT                      4
-#define LLWU_F2_WUF13_MASK                       0x20u
-#define LLWU_F2_WUF13_SHIFT                      5
-#define LLWU_F2_WUF14_MASK                       0x40u
-#define LLWU_F2_WUF14_SHIFT                      6
-#define LLWU_F2_WUF15_MASK                       0x80u
-#define LLWU_F2_WUF15_SHIFT                      7
-/* F3 Bit Fields */
-#define LLWU_F3_MWUF0_MASK                       0x1u
-#define LLWU_F3_MWUF0_SHIFT                      0
-#define LLWU_F3_MWUF1_MASK                       0x2u
-#define LLWU_F3_MWUF1_SHIFT                      1
-#define LLWU_F3_MWUF2_MASK                       0x4u
-#define LLWU_F3_MWUF2_SHIFT                      2
-#define LLWU_F3_MWUF3_MASK                       0x8u
-#define LLWU_F3_MWUF3_SHIFT                      3
-#define LLWU_F3_MWUF4_MASK                       0x10u
-#define LLWU_F3_MWUF4_SHIFT                      4
-#define LLWU_F3_MWUF5_MASK                       0x20u
-#define LLWU_F3_MWUF5_SHIFT                      5
-#define LLWU_F3_MWUF6_MASK                       0x40u
-#define LLWU_F3_MWUF6_SHIFT                      6
-#define LLWU_F3_MWUF7_MASK                       0x80u
-#define LLWU_F3_MWUF7_SHIFT                      7
-/* FILT1 Bit Fields */
-#define LLWU_FILT1_FILTSEL_MASK                  0xFu
-#define LLWU_FILT1_FILTSEL_SHIFT                 0
-#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
-#define LLWU_FILT1_FILTE_MASK                    0x60u
-#define LLWU_FILT1_FILTE_SHIFT                   5
-#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
-#define LLWU_FILT1_FILTF_MASK                    0x80u
-#define LLWU_FILT1_FILTF_SHIFT                   7
-/* FILT2 Bit Fields */
-#define LLWU_FILT2_FILTSEL_MASK                  0xFu
-#define LLWU_FILT2_FILTSEL_SHIFT                 0
-#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
-#define LLWU_FILT2_FILTE_MASK                    0x60u
-#define LLWU_FILT2_FILTE_SHIFT                   5
-#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
-#define LLWU_FILT2_FILTF_MASK                    0x80u
-#define LLWU_FILT2_FILTF_SHIFT                   7
-
-/**
- * @}
- */ /* end of group LLWU_Register_Masks */
-
-
-/* LLWU - Peripheral instance base addresses */
-/** Peripheral LLWU base address */
-#define LLWU_BASE                                (0x4007C000u)
-/** Peripheral LLWU base pointer */
-#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
-/** Array initializer of LLWU peripheral base pointers */
-#define LLWU_BASES                               { LLWU }
-
-/**
- * @}
- */ /* end of group LLWU_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- LPTMR Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
- * @{
- */
-
-/** LPTMR - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
-  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
-  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
-  __I  uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
-} LPTMR_Type;
-
-/* ----------------------------------------------------------------------------
-   -- LPTMR Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
- * @{
- */
-
-/* CSR Bit Fields */
-#define LPTMR_CSR_TEN_MASK                       0x1u
-#define LPTMR_CSR_TEN_SHIFT                      0
-#define LPTMR_CSR_TMS_MASK                       0x2u
-#define LPTMR_CSR_TMS_SHIFT                      1
-#define LPTMR_CSR_TFC_MASK                       0x4u
-#define LPTMR_CSR_TFC_SHIFT                      2
-#define LPTMR_CSR_TPP_MASK                       0x8u
-#define LPTMR_CSR_TPP_SHIFT                      3
-#define LPTMR_CSR_TPS_MASK                       0x30u
-#define LPTMR_CSR_TPS_SHIFT                      4
-#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
-#define LPTMR_CSR_TIE_MASK                       0x40u
-#define LPTMR_CSR_TIE_SHIFT                      6
-#define LPTMR_CSR_TCF_MASK                       0x80u
-#define LPTMR_CSR_TCF_SHIFT                      7
-/* PSR Bit Fields */
-#define LPTMR_PSR_PCS_MASK                       0x3u
-#define LPTMR_PSR_PCS_SHIFT                      0
-#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
-#define LPTMR_PSR_PBYP_MASK                      0x4u
-#define LPTMR_PSR_PBYP_SHIFT                     2
-#define LPTMR_PSR_PRESCALE_MASK                  0x78u
-#define LPTMR_PSR_PRESCALE_SHIFT                 3
-#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
-/* CMR Bit Fields */
-#define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
-#define LPTMR_CMR_COMPARE_SHIFT                  0
-#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
-/* CNR Bit Fields */
-#define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
-#define LPTMR_CNR_COUNTER_SHIFT                  0
-#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
-
-/**
- * @}
- */ /* end of group LPTMR_Register_Masks */
-
-
-/* LPTMR - Peripheral instance base addresses */
-/** Peripheral LPTMR0 base address */
-#define LPTMR0_BASE                              (0x40040000u)
-/** Peripheral LPTMR0 base pointer */
-#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
-/** Array initializer of LPTMR peripheral base pointers */
-#define LPTMR_BASES                              { LPTMR0 }
-
-/**
- * @}
- */ /* end of group LPTMR_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- MCG Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
- * @{
- */
-
-/** MCG - Register Layout Typedef */
-typedef struct {
-  __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
-  __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
-  __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
-  __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
-  __IO uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
-  __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
-  __I  uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
-       uint8_t RESERVED_0[1];
-  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
-       uint8_t RESERVED_1[1];
-  __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
-  __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
-  __I  uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
-  __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
-  __I  uint8_t C9;                                 /**< MCG Control 9 Register, offset: 0xE */
-  __I  uint8_t C10;                                /**< MCG Control 10 Register, offset: 0xF */
-} MCG_Type;
-
-/* ----------------------------------------------------------------------------
-   -- MCG Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCG_Register_Masks MCG Register Masks
- * @{
- */
-
-/* C1 Bit Fields */
-#define MCG_C1_IREFSTEN_MASK                     0x1u
-#define MCG_C1_IREFSTEN_SHIFT                    0
-#define MCG_C1_IRCLKEN_MASK                      0x2u
-#define MCG_C1_IRCLKEN_SHIFT                     1
-#define MCG_C1_IREFS_MASK                        0x4u
-#define MCG_C1_IREFS_SHIFT                       2
-#define MCG_C1_FRDIV_MASK                        0x38u
-#define MCG_C1_FRDIV_SHIFT                       3
-#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
-#define MCG_C1_CLKS_MASK                         0xC0u
-#define MCG_C1_CLKS_SHIFT                        6
-#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
-/* C2 Bit Fields */
-#define MCG_C2_IRCS_MASK                         0x1u
-#define MCG_C2_IRCS_SHIFT                        0
-#define MCG_C2_LP_MASK                           0x2u
-#define MCG_C2_LP_SHIFT                          1
-#define MCG_C2_EREFS0_MASK                       0x4u
-#define MCG_C2_EREFS0_SHIFT                      2
-#define MCG_C2_HGO0_MASK                         0x8u
-#define MCG_C2_HGO0_SHIFT                        3
-#define MCG_C2_RANGE0_MASK                       0x30u
-#define MCG_C2_RANGE0_SHIFT                      4
-#define MCG_C2_RANGE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
-#define MCG_C2_LOCRE0_MASK                       0x80u
-#define MCG_C2_LOCRE0_SHIFT                      7
-/* C3 Bit Fields */
-#define MCG_C3_SCTRIM_MASK                       0xFFu
-#define MCG_C3_SCTRIM_SHIFT                      0
-#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
-/* C4 Bit Fields */
-#define MCG_C4_SCFTRIM_MASK                      0x1u
-#define MCG_C4_SCFTRIM_SHIFT                     0
-#define MCG_C4_FCTRIM_MASK                       0x1Eu
-#define MCG_C4_FCTRIM_SHIFT                      1
-#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
-#define MCG_C4_DRST_DRS_MASK                     0x60u
-#define MCG_C4_DRST_DRS_SHIFT                    5
-#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
-#define MCG_C4_DMX32_MASK                        0x80u
-#define MCG_C4_DMX32_SHIFT                       7
-/* C5 Bit Fields */
-#define MCG_C5_PRDIV0_MASK                       0x1Fu
-#define MCG_C5_PRDIV0_SHIFT                      0
-#define MCG_C5_PRDIV0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
-#define MCG_C5_PLLSTEN0_MASK                     0x20u
-#define MCG_C5_PLLSTEN0_SHIFT                    5
-#define MCG_C5_PLLCLKEN0_MASK                    0x40u
-#define MCG_C5_PLLCLKEN0_SHIFT                   6
-/* C6 Bit Fields */
-#define MCG_C6_VDIV0_MASK                        0x1Fu
-#define MCG_C6_VDIV0_SHIFT                       0
-#define MCG_C6_VDIV0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
-#define MCG_C6_CME0_MASK                         0x20u
-#define MCG_C6_CME0_SHIFT                        5
-#define MCG_C6_PLLS_MASK                         0x40u
-#define MCG_C6_PLLS_SHIFT                        6
-#define MCG_C6_LOLIE0_MASK                       0x80u
-#define MCG_C6_LOLIE0_SHIFT                      7
-/* S Bit Fields */
-#define MCG_S_IRCST_MASK                         0x1u
-#define MCG_S_IRCST_SHIFT                        0
-#define MCG_S_OSCINIT0_MASK                      0x2u
-#define MCG_S_OSCINIT0_SHIFT                     1
-#define MCG_S_CLKST_MASK                         0xCu
-#define MCG_S_CLKST_SHIFT                        2
-#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
-#define MCG_S_IREFST_MASK                        0x10u
-#define MCG_S_IREFST_SHIFT                       4
-#define MCG_S_PLLST_MASK                         0x20u
-#define MCG_S_PLLST_SHIFT                        5
-#define MCG_S_LOCK0_MASK                         0x40u
-#define MCG_S_LOCK0_SHIFT                        6
-#define MCG_S_LOLS_MASK                          0x80u
-#define MCG_S_LOLS_SHIFT                         7
-/* SC Bit Fields */
-#define MCG_SC_LOCS0_MASK                        0x1u
-#define MCG_SC_LOCS0_SHIFT                       0
-#define MCG_SC_FCRDIV_MASK                       0xEu
-#define MCG_SC_FCRDIV_SHIFT                      1
-#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
-#define MCG_SC_FLTPRSRV_MASK                     0x10u
-#define MCG_SC_FLTPRSRV_SHIFT                    4
-#define MCG_SC_ATMF_MASK                         0x20u
-#define MCG_SC_ATMF_SHIFT                        5
-#define MCG_SC_ATMS_MASK                         0x40u
-#define MCG_SC_ATMS_SHIFT                        6
-#define MCG_SC_ATME_MASK                         0x80u
-#define MCG_SC_ATME_SHIFT                        7
-/* ATCVH Bit Fields */
-#define MCG_ATCVH_ATCVH_MASK                     0xFFu
-#define MCG_ATCVH_ATCVH_SHIFT                    0
-#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
-/* ATCVL Bit Fields */
-#define MCG_ATCVL_ATCVL_MASK                     0xFFu
-#define MCG_ATCVL_ATCVL_SHIFT                    0
-#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
-/* C8 Bit Fields */
-#define MCG_C8_LOLRE_MASK                        0x40u
-#define MCG_C8_LOLRE_SHIFT                       6
-
-/**
- * @}
- */ /* end of group MCG_Register_Masks */
-
-
-/* MCG - Peripheral instance base addresses */
-/** Peripheral MCG base address */
-#define MCG_BASE                                 (0x40064000u)
-/** Peripheral MCG base pointer */
-#define MCG                                      ((MCG_Type *)MCG_BASE)
-/** Array initializer of MCG peripheral base pointers */
-#define MCG_BASES                                { MCG }
-
-/**
- * @}
- */ /* end of group MCG_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- MCM Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
- * @{
- */
-
-/** MCM - Register Layout Typedef */
-typedef struct {
-       uint8_t RESERVED_0[8];
-  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
-  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
-  __IO uint32_t PLACR;                             /**< Platform Control Register, offset: 0xC */
-       uint8_t RESERVED_1[48];
-  __IO uint32_t CPO;                               /**< Compute Operation Control Register, offset: 0x40 */
-} MCM_Type;
-
-/* ----------------------------------------------------------------------------
-   -- MCM Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCM_Register_Masks MCM Register Masks
- * @{
- */
-
-/* PLASC Bit Fields */
-#define MCM_PLASC_ASC_MASK                       0xFFu
-#define MCM_PLASC_ASC_SHIFT                      0
-#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
-/* PLAMC Bit Fields */
-#define MCM_PLAMC_AMC_MASK                       0xFFu
-#define MCM_PLAMC_AMC_SHIFT                      0
-#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
-/* PLACR Bit Fields */
-#define MCM_PLACR_ARB_MASK                       0x200u
-#define MCM_PLACR_ARB_SHIFT                      9
-#define MCM_PLACR_CFCC_MASK                      0x400u
-#define MCM_PLACR_CFCC_SHIFT                     10
-#define MCM_PLACR_DFCDA_MASK                     0x800u
-#define MCM_PLACR_DFCDA_SHIFT                    11
-#define MCM_PLACR_DFCIC_MASK                     0x1000u
-#define MCM_PLACR_DFCIC_SHIFT                    12
-#define MCM_PLACR_DFCC_MASK                      0x2000u
-#define MCM_PLACR_DFCC_SHIFT                     13
-#define MCM_PLACR_EFDS_MASK                      0x4000u
-#define MCM_PLACR_EFDS_SHIFT                     14
-#define MCM_PLACR_DFCS_MASK                      0x8000u
-#define MCM_PLACR_DFCS_SHIFT                     15
-#define MCM_PLACR_ESFC_MASK                      0x10000u
-#define MCM_PLACR_ESFC_SHIFT                     16
-/* CPO Bit Fields */
-#define MCM_CPO_CPOREQ_MASK                      0x1u
-#define MCM_CPO_CPOREQ_SHIFT                     0
-#define MCM_CPO_CPOACK_MASK                      0x2u
-#define MCM_CPO_CPOACK_SHIFT                     1
-#define MCM_CPO_CPOWOI_MASK                      0x4u
-#define MCM_CPO_CPOWOI_SHIFT                     2
-
-/**
- * @}
- */ /* end of group MCM_Register_Masks */
-
-
-/* MCM - Peripheral instance base addresses */
-/** Peripheral MCM base address */
-#define MCM_BASE                                 (0xF0003000u)
-/** Peripheral MCM base pointer */
-#define MCM                                      ((MCM_Type *)MCM_BASE)
-/** Array initializer of MCM peripheral base pointers */
-#define MCM_BASES                                { MCM }
-
-/**
- * @}
- */ /* end of group MCM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- MTB Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
- * @{
- */
-
-/** MTB - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t POSITION;                          /**< MTB Position Register, offset: 0x0 */
-  __IO uint32_t MASTER;                            /**< MTB Master Register, offset: 0x4 */
-  __IO uint32_t FLOW;                              /**< MTB Flow Register, offset: 0x8 */
-  __I  uint32_t BASE;                              /**< MTB Base Register, offset: 0xC */
-       uint8_t RESERVED_0[3824];
-  __I  uint32_t MODECTRL;                          /**< Integration Mode Control Register, offset: 0xF00 */
-       uint8_t RESERVED_1[156];
-  __I  uint32_t TAGSET;                            /**< Claim TAG Set Register, offset: 0xFA0 */
-  __I  uint32_t TAGCLEAR;                          /**< Claim TAG Clear Register, offset: 0xFA4 */
-       uint8_t RESERVED_2[8];
-  __I  uint32_t LOCKACCESS;                        /**< Lock Access Register, offset: 0xFB0 */
-  __I  uint32_t LOCKSTAT;                          /**< Lock Status Register, offset: 0xFB4 */
-  __I  uint32_t AUTHSTAT;                          /**< Authentication Status Register, offset: 0xFB8 */
-  __I  uint32_t DEVICEARCH;                        /**< Device Architecture Register, offset: 0xFBC */
-       uint8_t RESERVED_3[8];
-  __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
-  __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
-  __I  uint32_t PERIPHID[8];                       /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
-  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
-} MTB_Type;
-
-/* ----------------------------------------------------------------------------
-   -- MTB Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MTB_Register_Masks MTB Register Masks
- * @{
- */
-
-/* POSITION Bit Fields */
-#define MTB_POSITION_WRAP_MASK                   0x4u
-#define MTB_POSITION_WRAP_SHIFT                  2
-#define MTB_POSITION_POINTER_MASK                0xFFFFFFF8u
-#define MTB_POSITION_POINTER_SHIFT               3
-#define MTB_POSITION_POINTER(x)                  (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
-/* MASTER Bit Fields */
-#define MTB_MASTER_MASK_MASK                     0x1Fu
-#define MTB_MASTER_MASK_SHIFT                    0
-#define MTB_MASTER_MASK(x)                       (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
-#define MTB_MASTER_TSTARTEN_MASK                 0x20u
-#define MTB_MASTER_TSTARTEN_SHIFT                5
-#define MTB_MASTER_TSTOPEN_MASK                  0x40u
-#define MTB_MASTER_TSTOPEN_SHIFT                 6
-#define MTB_MASTER_SFRWPRIV_MASK                 0x80u
-#define MTB_MASTER_SFRWPRIV_SHIFT                7
-#define MTB_MASTER_RAMPRIV_MASK                  0x100u
-#define MTB_MASTER_RAMPRIV_SHIFT                 8
-#define MTB_MASTER_HALTREQ_MASK                  0x200u
-#define MTB_MASTER_HALTREQ_SHIFT                 9
-#define MTB_MASTER_EN_MASK                       0x80000000u
-#define MTB_MASTER_EN_SHIFT                      31
-/* FLOW Bit Fields */
-#define MTB_FLOW_AUTOSTOP_MASK                   0x1u
-#define MTB_FLOW_AUTOSTOP_SHIFT                  0
-#define MTB_FLOW_AUTOHALT_MASK                   0x2u
-#define MTB_FLOW_AUTOHALT_SHIFT                  1
-#define MTB_FLOW_WATERMARK_MASK                  0xFFFFFFF8u
-#define MTB_FLOW_WATERMARK_SHIFT                 3
-#define MTB_FLOW_WATERMARK(x)                    (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
-/* BASE Bit Fields */
-#define MTB_BASE_BASEADDR_MASK                   0xFFFFFFFFu
-#define MTB_BASE_BASEADDR_SHIFT                  0
-#define MTB_BASE_BASEADDR(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
-/* MODECTRL Bit Fields */
-#define MTB_MODECTRL_MODECTRL_MASK               0xFFFFFFFFu
-#define MTB_MODECTRL_MODECTRL_SHIFT              0
-#define MTB_MODECTRL_MODECTRL(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
-/* TAGSET Bit Fields */
-#define MTB_TAGSET_TAGSET_MASK                   0xFFFFFFFFu
-#define MTB_TAGSET_TAGSET_SHIFT                  0
-#define MTB_TAGSET_TAGSET(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
-/* TAGCLEAR Bit Fields */
-#define MTB_TAGCLEAR_TAGCLEAR_MASK               0xFFFFFFFFu
-#define MTB_TAGCLEAR_TAGCLEAR_SHIFT              0
-#define MTB_TAGCLEAR_TAGCLEAR(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
-/* LOCKACCESS Bit Fields */
-#define MTB_LOCKACCESS_LOCKACCESS_MASK           0xFFFFFFFFu
-#define MTB_LOCKACCESS_LOCKACCESS_SHIFT          0
-#define MTB_LOCKACCESS_LOCKACCESS(x)             (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
-/* LOCKSTAT Bit Fields */
-#define MTB_LOCKSTAT_LOCKSTAT_MASK               0xFFFFFFFFu
-#define MTB_LOCKSTAT_LOCKSTAT_SHIFT              0
-#define MTB_LOCKSTAT_LOCKSTAT(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
-/* AUTHSTAT Bit Fields */
-#define MTB_AUTHSTAT_BIT0_MASK                   0x1u
-#define MTB_AUTHSTAT_BIT0_SHIFT                  0
-#define MTB_AUTHSTAT_BIT1_MASK                   0x2u
-#define MTB_AUTHSTAT_BIT1_SHIFT                  1
-#define MTB_AUTHSTAT_BIT2_MASK                   0x4u
-#define MTB_AUTHSTAT_BIT2_SHIFT                  2
-#define MTB_AUTHSTAT_BIT3_MASK                   0x8u
-#define MTB_AUTHSTAT_BIT3_SHIFT                  3
-/* DEVICEARCH Bit Fields */
-#define MTB_DEVICEARCH_DEVICEARCH_MASK           0xFFFFFFFFu
-#define MTB_DEVICEARCH_DEVICEARCH_SHIFT          0
-#define MTB_DEVICEARCH_DEVICEARCH(x)             (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
-/* DEVICECFG Bit Fields */
-#define MTB_DEVICECFG_DEVICECFG_MASK             0xFFFFFFFFu
-#define MTB_DEVICECFG_DEVICECFG_SHIFT            0
-#define MTB_DEVICECFG_DEVICECFG(x)               (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
-/* DEVICETYPID Bit Fields */
-#define MTB_DEVICETYPID_DEVICETYPID_MASK         0xFFFFFFFFu
-#define MTB_DEVICETYPID_DEVICETYPID_SHIFT        0
-#define MTB_DEVICETYPID_DEVICETYPID(x)           (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
-/* PERIPHID Bit Fields */
-#define MTB_PERIPHID_PERIPHID_MASK               0xFFFFFFFFu
-#define MTB_PERIPHID_PERIPHID_SHIFT              0
-#define MTB_PERIPHID_PERIPHID(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
-/* COMPID Bit Fields */
-#define MTB_COMPID_COMPID_MASK                   0xFFFFFFFFu
-#define MTB_COMPID_COMPID_SHIFT                  0
-#define MTB_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
-
-/**
- * @}
- */ /* end of group MTB_Register_Masks */
-
-
-/* MTB - Peripheral instance base addresses */
-/** Peripheral MTB base address */
-#define MTB_BASE                                 (0xF0000000u)
-/** Peripheral MTB base pointer */
-#define MTB                                      ((MTB_Type *)MTB_BASE)
-/** Array initializer of MTB peripheral base pointers */
-#define MTB_BASES                                { MTB }
-
-/**
- * @}
- */ /* end of group MTB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- MTBDWT Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
- * @{
- */
-
-/** MTBDWT - Register Layout Typedef */
-typedef struct {
-  __I  uint32_t CTRL;                              /**< MTB DWT Control Register, offset: 0x0 */
-       uint8_t RESERVED_0[28];
-  struct {                                         /* offset: 0x20, array step: 0x10 */
-    __IO uint32_t COMP;                              /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
-    __IO uint32_t MASK;                              /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
-    __IO uint32_t FCT;                               /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
-         uint8_t RESERVED_0[4];
-  } COMPARATOR[2];
-       uint8_t RESERVED_1[448];
-  __IO uint32_t TBCTRL;                            /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
-       uint8_t RESERVED_2[3524];
-  __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
-  __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
-  __I  uint32_t PERIPHID[8];                       /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
-  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
-} MTBDWT_Type;
-
-/* ----------------------------------------------------------------------------
-   -- MTBDWT Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
- * @{
- */
-
-/* CTRL Bit Fields */
-#define MTBDWT_CTRL_DWTCFGCTRL_MASK              0xFFFFFFFu
-#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT             0
-#define MTBDWT_CTRL_DWTCFGCTRL(x)                (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
-#define MTBDWT_CTRL_NUMCMP_MASK                  0xF0000000u
-#define MTBDWT_CTRL_NUMCMP_SHIFT                 28
-#define MTBDWT_CTRL_NUMCMP(x)                    (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
-/* COMP Bit Fields */
-#define MTBDWT_COMP_COMP_MASK                    0xFFFFFFFFu
-#define MTBDWT_COMP_COMP_SHIFT                   0
-#define MTBDWT_COMP_COMP(x)                      (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
-/* MASK Bit Fields */
-#define MTBDWT_MASK_MASK_MASK                    0x1Fu
-#define MTBDWT_MASK_MASK_SHIFT                   0
-#define MTBDWT_MASK_MASK(x)                      (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
-/* FCT Bit Fields */
-#define MTBDWT_FCT_FUNCTION_MASK                 0xFu
-#define MTBDWT_FCT_FUNCTION_SHIFT                0
-#define MTBDWT_FCT_FUNCTION(x)                   (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
-#define MTBDWT_FCT_DATAVMATCH_MASK               0x100u
-#define MTBDWT_FCT_DATAVMATCH_SHIFT              8
-#define MTBDWT_FCT_DATAVSIZE_MASK                0xC00u
-#define MTBDWT_FCT_DATAVSIZE_SHIFT               10
-#define MTBDWT_FCT_DATAVSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
-#define MTBDWT_FCT_DATAVADDR0_MASK               0xF000u
-#define MTBDWT_FCT_DATAVADDR0_SHIFT              12
-#define MTBDWT_FCT_DATAVADDR0(x)                 (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
-#define MTBDWT_FCT_MATCHED_MASK                  0x1000000u
-#define MTBDWT_FCT_MATCHED_SHIFT                 24
-/* TBCTRL Bit Fields */
-#define MTBDWT_TBCTRL_ACOMP0_MASK                0x1u
-#define MTBDWT_TBCTRL_ACOMP0_SHIFT               0
-#define MTBDWT_TBCTRL_ACOMP1_MASK                0x2u
-#define MTBDWT_TBCTRL_ACOMP1_SHIFT               1
-#define MTBDWT_TBCTRL_NUMCOMP_MASK               0xF0000000u
-#define MTBDWT_TBCTRL_NUMCOMP_SHIFT              28
-#define MTBDWT_TBCTRL_NUMCOMP(x)                 (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
-/* DEVICECFG Bit Fields */
-#define MTBDWT_DEVICECFG_DEVICECFG_MASK          0xFFFFFFFFu
-#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT         0
-#define MTBDWT_DEVICECFG_DEVICECFG(x)            (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
-/* DEVICETYPID Bit Fields */
-#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK      0xFFFFFFFFu
-#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT     0
-#define MTBDWT_DEVICETYPID_DEVICETYPID(x)        (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
-/* PERIPHID Bit Fields */
-#define MTBDWT_PERIPHID_PERIPHID_MASK            0xFFFFFFFFu
-#define MTBDWT_PERIPHID_PERIPHID_SHIFT           0
-#define MTBDWT_PERIPHID_PERIPHID(x)              (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
-/* COMPID Bit Fields */
-#define MTBDWT_COMPID_COMPID_MASK                0xFFFFFFFFu
-#define MTBDWT_COMPID_COMPID_SHIFT               0
-#define MTBDWT_COMPID_COMPID(x)                  (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
-
-/**
- * @}
- */ /* end of group MTBDWT_Register_Masks */
-
-
-/* MTBDWT - Peripheral instance base addresses */
-/** Peripheral MTBDWT base address */
-#define MTBDWT_BASE                              (0xF0001000u)
-/** Peripheral MTBDWT base pointer */
-#define MTBDWT                                   ((MTBDWT_Type *)MTBDWT_BASE)
-/** Array initializer of MTBDWT peripheral base pointers */
-#define MTBDWT_BASES                             { MTBDWT }
-
-/**
- * @}
- */ /* end of group MTBDWT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- NV Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
- * @{
- */
-
-/** NV - Register Layout Typedef */
-typedef struct {
-  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
-  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
-  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
-  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
-  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
-  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
-  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
-  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
-  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
-  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
-  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
-  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
-  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
-  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
-} NV_Type;
-
-/* ----------------------------------------------------------------------------
-   -- NV Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup NV_Register_Masks NV Register Masks
- * @{
- */
-
-/* BACKKEY3 Bit Fields */
-#define NV_BACKKEY3_KEY_MASK                     0xFFu
-#define NV_BACKKEY3_KEY_SHIFT                    0
-#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
-/* BACKKEY2 Bit Fields */
-#define NV_BACKKEY2_KEY_MASK                     0xFFu
-#define NV_BACKKEY2_KEY_SHIFT                    0
-#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
-/* BACKKEY1 Bit Fields */
-#define NV_BACKKEY1_KEY_MASK                     0xFFu
-#define NV_BACKKEY1_KEY_SHIFT                    0
-#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
-/* BACKKEY0 Bit Fields */
-#define NV_BACKKEY0_KEY_MASK                     0xFFu
-#define NV_BACKKEY0_KEY_SHIFT                    0
-#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
-/* BACKKEY7 Bit Fields */
-#define NV_BACKKEY7_KEY_MASK                     0xFFu
-#define NV_BACKKEY7_KEY_SHIFT                    0
-#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
-/* BACKKEY6 Bit Fields */
-#define NV_BACKKEY6_KEY_MASK                     0xFFu
-#define NV_BACKKEY6_KEY_SHIFT                    0
-#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
-/* BACKKEY5 Bit Fields */
-#define NV_BACKKEY5_KEY_MASK                     0xFFu
-#define NV_BACKKEY5_KEY_SHIFT                    0
-#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
-/* BACKKEY4 Bit Fields */
-#define NV_BACKKEY4_KEY_MASK                     0xFFu
-#define NV_BACKKEY4_KEY_SHIFT                    0
-#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
-/* FPROT3 Bit Fields */
-#define NV_FPROT3_PROT_MASK                      0xFFu
-#define NV_FPROT3_PROT_SHIFT                     0
-#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define NV_FPROT2_PROT_MASK                      0xFFu
-#define NV_FPROT2_PROT_SHIFT                     0
-#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define NV_FPROT1_PROT_MASK                      0xFFu
-#define NV_FPROT1_PROT_SHIFT                     0
-#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define NV_FPROT0_PROT_MASK                      0xFFu
-#define NV_FPROT0_PROT_SHIFT                     0
-#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
-/* FSEC Bit Fields */
-#define NV_FSEC_SEC_MASK                         0x3u
-#define NV_FSEC_SEC_SHIFT                        0
-#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
-#define NV_FSEC_FSLACC_MASK                      0xCu
-#define NV_FSEC_FSLACC_SHIFT                     2
-#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
-#define NV_FSEC_MEEN_MASK                        0x30u
-#define NV_FSEC_MEEN_SHIFT                       4
-#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
-#define NV_FSEC_KEYEN_MASK                       0xC0u
-#define NV_FSEC_KEYEN_SHIFT                      6
-#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define NV_FOPT_LPBOOT0_MASK                     0x1u
-#define NV_FOPT_LPBOOT0_SHIFT                    0
-#define NV_FOPT_NMI_DIS_MASK                     0x4u
-#define NV_FOPT_NMI_DIS_SHIFT                    2
-#define NV_FOPT_RESET_PIN_CFG_MASK               0x8u
-#define NV_FOPT_RESET_PIN_CFG_SHIFT              3
-#define NV_FOPT_LPBOOT1_MASK                     0x10u
-#define NV_FOPT_LPBOOT1_SHIFT                    4
-#define NV_FOPT_FAST_INIT_MASK                   0x20u
-#define NV_FOPT_FAST_INIT_SHIFT                  5
-
-/**
- * @}
- */ /* end of group NV_Register_Masks */
-
-
-/* NV - Peripheral instance base addresses */
-/** Peripheral FTFA_FlashConfig base address */
-#define FTFA_FlashConfig_BASE                    (0x400u)
-/** Peripheral FTFA_FlashConfig base pointer */
-#define FTFA_FlashConfig                         ((NV_Type *)FTFA_FlashConfig_BASE)
-/** Array initializer of NV peripheral base pointers */
-#define NV_BASES                                 { FTFA_FlashConfig }
-
-/**
- * @}
- */ /* end of group NV_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- OSC Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
- * @{
- */
-
-/** OSC - Register Layout Typedef */
-typedef struct {
-  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
-} OSC_Type;
-
-/* ----------------------------------------------------------------------------
-   -- OSC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup OSC_Register_Masks OSC Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define OSC_CR_SC16P_MASK                        0x1u
-#define OSC_CR_SC16P_SHIFT                       0
-#define OSC_CR_SC8P_MASK                         0x2u
-#define OSC_CR_SC8P_SHIFT                        1
-#define OSC_CR_SC4P_MASK                         0x4u
-#define OSC_CR_SC4P_SHIFT                        2
-#define OSC_CR_SC2P_MASK                         0x8u
-#define OSC_CR_SC2P_SHIFT                        3
-#define OSC_CR_EREFSTEN_MASK                     0x20u
-#define OSC_CR_EREFSTEN_SHIFT                    5
-#define OSC_CR_ERCLKEN_MASK                      0x80u
-#define OSC_CR_ERCLKEN_SHIFT                     7
-
-/**
- * @}
- */ /* end of group OSC_Register_Masks */
-
-
-/* OSC - Peripheral instance base addresses */
-/** Peripheral OSC0 base address */
-#define OSC0_BASE                                (0x40065000u)
-/** Peripheral OSC0 base pointer */
-#define OSC0                                     ((OSC_Type *)OSC0_BASE)
-/** Array initializer of OSC peripheral base pointers */
-#define OSC_BASES                                { OSC0 }
-
-/**
- * @}
- */ /* end of group OSC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- PIT Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
- * @{
- */
-
-/** PIT - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
-       uint8_t RESERVED_0[220];
-  __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
-  __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
-       uint8_t RESERVED_1[24];
-  struct {                                         /* offset: 0x100, array step: 0x10 */
-    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
-    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
-    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
-    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
-  } CHANNEL[2];
-} PIT_Type;
-
-/* ----------------------------------------------------------------------------
-   -- PIT Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PIT_Register_Masks PIT Register Masks
- * @{
- */
-
-/* MCR Bit Fields */
-#define PIT_MCR_FRZ_MASK                         0x1u
-#define PIT_MCR_FRZ_SHIFT                        0
-#define PIT_MCR_MDIS_MASK                        0x2u
-#define PIT_MCR_MDIS_SHIFT                       1
-/* LTMR64H Bit Fields */
-#define PIT_LTMR64H_LTH_MASK                     0xFFFFFFFFu
-#define PIT_LTMR64H_LTH_SHIFT                    0
-#define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
-/* LTMR64L Bit Fields */
-#define PIT_LTMR64L_LTL_MASK                     0xFFFFFFFFu
-#define PIT_LTMR64L_LTL_SHIFT                    0
-#define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
-/* LDVAL Bit Fields */
-#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
-#define PIT_LDVAL_TSV_SHIFT                      0
-#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
-/* CVAL Bit Fields */
-#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
-#define PIT_CVAL_TVL_SHIFT                       0
-#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
-/* TCTRL Bit Fields */
-#define PIT_TCTRL_TEN_MASK                       0x1u
-#define PIT_TCTRL_TEN_SHIFT                      0
-#define PIT_TCTRL_TIE_MASK                       0x2u
-#define PIT_TCTRL_TIE_SHIFT                      1
-#define PIT_TCTRL_CHN_MASK                       0x4u
-#define PIT_TCTRL_CHN_SHIFT                      2
-/* TFLG Bit Fields */
-#define PIT_TFLG_TIF_MASK                        0x1u
-#define PIT_TFLG_TIF_SHIFT                       0
-
-/**
- * @}
- */ /* end of group PIT_Register_Masks */
-
-
-/* PIT - Peripheral instance base addresses */
-/** Peripheral PIT base address */
-#define PIT_BASE                                 (0x40037000u)
-/** Peripheral PIT base pointer */
-#define PIT                                      ((PIT_Type *)PIT_BASE)
-/** Array initializer of PIT peripheral base pointers */
-#define PIT_BASES                                { PIT }
-
-/**
- * @}
- */ /* end of group PIT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- PMC Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
- * @{
- */
-
-/** PMC - Register Layout Typedef */
-typedef struct {
-  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
-  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
-  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
-} PMC_Type;
-
-/* ----------------------------------------------------------------------------
-   -- PMC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PMC_Register_Masks PMC Register Masks
- * @{
- */
-
-/* LVDSC1 Bit Fields */
-#define PMC_LVDSC1_LVDV_MASK                     0x3u
-#define PMC_LVDSC1_LVDV_SHIFT                    0
-#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
-#define PMC_LVDSC1_LVDRE_MASK                    0x10u
-#define PMC_LVDSC1_LVDRE_SHIFT                   4
-#define PMC_LVDSC1_LVDIE_MASK                    0x20u
-#define PMC_LVDSC1_LVDIE_SHIFT                   5
-#define PMC_LVDSC1_LVDACK_MASK                   0x40u
-#define PMC_LVDSC1_LVDACK_SHIFT                  6
-#define PMC_LVDSC1_LVDF_MASK                     0x80u
-#define PMC_LVDSC1_LVDF_SHIFT                    7
-/* LVDSC2 Bit Fields */
-#define PMC_LVDSC2_LVWV_MASK                     0x3u
-#define PMC_LVDSC2_LVWV_SHIFT                    0
-#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
-#define PMC_LVDSC2_LVWIE_MASK                    0x20u
-#define PMC_LVDSC2_LVWIE_SHIFT                   5
-#define PMC_LVDSC2_LVWACK_MASK                   0x40u
-#define PMC_LVDSC2_LVWACK_SHIFT                  6
-#define PMC_LVDSC2_LVWF_MASK                     0x80u
-#define PMC_LVDSC2_LVWF_SHIFT                    7
-/* REGSC Bit Fields */
-#define PMC_REGSC_BGBE_MASK                      0x1u
-#define PMC_REGSC_BGBE_SHIFT                     0
-#define PMC_REGSC_REGONS_MASK                    0x4u
-#define PMC_REGSC_REGONS_SHIFT                   2
-#define PMC_REGSC_ACKISO_MASK                    0x8u
-#define PMC_REGSC_ACKISO_SHIFT                   3
-#define PMC_REGSC_BGEN_MASK                      0x10u
-#define PMC_REGSC_BGEN_SHIFT                     4
-
-/**
- * @}
- */ /* end of group PMC_Register_Masks */
-
-
-/* PMC - Peripheral instance base addresses */
-/** Peripheral PMC base address */
-#define PMC_BASE                                 (0x4007D000u)
-/** Peripheral PMC base pointer */
-#define PMC                                      ((PMC_Type *)PMC_BASE)
-/** Array initializer of PMC peripheral base pointers */
-#define PMC_BASES                                { PMC }
-
-/**
- * @}
- */ /* end of group PMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- PORT Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
- * @{
- */
-
-/** PORT - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
-  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
-  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
-       uint8_t RESERVED_0[24];
-  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
-} PORT_Type;
-
-/* ----------------------------------------------------------------------------
-   -- PORT Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PORT_Register_Masks PORT Register Masks
- * @{
- */
-
-/* PCR Bit Fields */
-#define PORT_PCR_PS_MASK                         0x1u
-#define PORT_PCR_PS_SHIFT                        0
-#define PORT_PCR_PE_MASK                         0x2u
-#define PORT_PCR_PE_SHIFT                        1
-#define PORT_PCR_SRE_MASK                        0x4u
-#define PORT_PCR_SRE_SHIFT                       2
-#define PORT_PCR_PFE_MASK                        0x10u
-#define PORT_PCR_PFE_SHIFT                       4
-#define PORT_PCR_DSE_MASK                        0x40u
-#define PORT_PCR_DSE_SHIFT                       6
-#define PORT_PCR_MUX_MASK                        0x700u
-#define PORT_PCR_MUX_SHIFT                       8
-#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
-#define PORT_PCR_IRQC_MASK                       0xF0000u
-#define PORT_PCR_IRQC_SHIFT                      16
-#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
-#define PORT_PCR_ISF_MASK                        0x1000000u
-#define PORT_PCR_ISF_SHIFT                       24
-/* GPCLR Bit Fields */
-#define PORT_GPCLR_GPWD_MASK                     0xFFFFu
-#define PORT_GPCLR_GPWD_SHIFT                    0
-#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
-#define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
-#define PORT_GPCLR_GPWE_SHIFT                    16
-#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
-/* GPCHR Bit Fields */
-#define PORT_GPCHR_GPWD_MASK                     0xFFFFu
-#define PORT_GPCHR_GPWD_SHIFT                    0
-#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
-#define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
-#define PORT_GPCHR_GPWE_SHIFT                    16
-#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
-/* ISFR Bit Fields */
-#define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
-#define PORT_ISFR_ISF_SHIFT                      0
-#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
-
-/**
- * @}
- */ /* end of group PORT_Register_Masks */
-
-
-/* PORT - Peripheral instance base addresses */
-/** Peripheral PORTA base address */
-#define PORTA_BASE                               (0x40049000u)
-/** Peripheral PORTA base pointer */
-#define PORTA                                    ((PORT_Type *)PORTA_BASE)
-/** Peripheral PORTB base address */
-#define PORTB_BASE                               (0x4004A000u)
-/** Peripheral PORTB base pointer */
-#define PORTB                                    ((PORT_Type *)PORTB_BASE)
-/** Peripheral PORTC base address */
-#define PORTC_BASE                               (0x4004B000u)
-/** Peripheral PORTC base pointer */
-#define PORTC                                    ((PORT_Type *)PORTC_BASE)
-/** Peripheral PORTD base address */
-#define PORTD_BASE                               (0x4004C000u)
-/** Peripheral PORTD base pointer */
-#define PORTD                                    ((PORT_Type *)PORTD_BASE)
-/** Peripheral PORTE base address */
-#define PORTE_BASE                               (0x4004D000u)
-/** Peripheral PORTE base pointer */
-#define PORTE                                    ((PORT_Type *)PORTE_BASE)
-/** Array initializer of PORT peripheral base pointers */
-#define PORT_BASES                               { PORTA, PORTB, PORTC, PORTD, PORTE }
-
-/**
- * @}
- */ /* end of group PORT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- RCM Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
- * @{
- */
-
-/** RCM - Register Layout Typedef */
-typedef struct {
-  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
-  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
-       uint8_t RESERVED_0[2];
-  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
-  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
-} RCM_Type;
-
-/* ----------------------------------------------------------------------------
-   -- RCM Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RCM_Register_Masks RCM Register Masks
- * @{
- */
-
-/* SRS0 Bit Fields */
-#define RCM_SRS0_WAKEUP_MASK                     0x1u
-#define RCM_SRS0_WAKEUP_SHIFT                    0
-#define RCM_SRS0_LVD_MASK                        0x2u
-#define RCM_SRS0_LVD_SHIFT                       1
-#define RCM_SRS0_LOC_MASK                        0x4u
-#define RCM_SRS0_LOC_SHIFT                       2
-#define RCM_SRS0_LOL_MASK                        0x8u
-#define RCM_SRS0_LOL_SHIFT                       3
-#define RCM_SRS0_WDOG_MASK                       0x20u
-#define RCM_SRS0_WDOG_SHIFT                      5
-#define RCM_SRS0_PIN_MASK                        0x40u
-#define RCM_SRS0_PIN_SHIFT                       6
-#define RCM_SRS0_POR_MASK                        0x80u
-#define RCM_SRS0_POR_SHIFT                       7
-/* SRS1 Bit Fields */
-#define RCM_SRS1_LOCKUP_MASK                     0x2u
-#define RCM_SRS1_LOCKUP_SHIFT                    1
-#define RCM_SRS1_SW_MASK                         0x4u
-#define RCM_SRS1_SW_SHIFT                        2
-#define RCM_SRS1_MDM_AP_MASK                     0x8u
-#define RCM_SRS1_MDM_AP_SHIFT                    3
-#define RCM_SRS1_SACKERR_MASK                    0x20u
-#define RCM_SRS1_SACKERR_SHIFT                   5
-/* RPFC Bit Fields */
-#define RCM_RPFC_RSTFLTSRW_MASK                  0x3u
-#define RCM_RPFC_RSTFLTSRW_SHIFT                 0
-#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
-#define RCM_RPFC_RSTFLTSS_MASK                   0x4u
-#define RCM_RPFC_RSTFLTSS_SHIFT                  2
-/* RPFW Bit Fields */
-#define RCM_RPFW_RSTFLTSEL_MASK                  0x1Fu
-#define RCM_RPFW_RSTFLTSEL_SHIFT                 0
-#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
-
-/**
- * @}
- */ /* end of group RCM_Register_Masks */
-
-
-/* RCM - Peripheral instance base addresses */
-/** Peripheral RCM base address */
-#define RCM_BASE                                 (0x4007F000u)
-/** Peripheral RCM base pointer */
-#define RCM                                      ((RCM_Type *)RCM_BASE)
-/** Array initializer of RCM peripheral base pointers */
-#define RCM_BASES                                { RCM }
-
-/**
- * @}
- */ /* end of group RCM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- ROM Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
- * @{
- */
-
-/** ROM - Register Layout Typedef */
-typedef struct {
-  __I  uint32_t ENTRY[3];                          /**< Entry, array offset: 0x0, array step: 0x4 */
-  __I  uint32_t TABLEMARK;                         /**< End of Table Marker Register, offset: 0xC */
-       uint8_t RESERVED_0[4028];
-  __I  uint32_t SYSACCESS;                         /**< System Access Register, offset: 0xFCC */
-  __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
-  __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
-  __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
-  __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
-  __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
-  __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
-  __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
-  __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
-  __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
-} ROM_Type;
-
-/* ----------------------------------------------------------------------------
-   -- ROM Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ROM_Register_Masks ROM Register Masks
- * @{
- */
-
-/* ENTRY Bit Fields */
-#define ROM_ENTRY_ENTRY_MASK                     0xFFFFFFFFu
-#define ROM_ENTRY_ENTRY_SHIFT                    0
-#define ROM_ENTRY_ENTRY(x)                       (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
-/* TABLEMARK Bit Fields */
-#define ROM_TABLEMARK_MARK_MASK                  0xFFFFFFFFu
-#define ROM_TABLEMARK_MARK_SHIFT                 0
-#define ROM_TABLEMARK_MARK(x)                    (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
-/* SYSACCESS Bit Fields */
-#define ROM_SYSACCESS_SYSACCESS_MASK             0xFFFFFFFFu
-#define ROM_SYSACCESS_SYSACCESS_SHIFT            0
-#define ROM_SYSACCESS_SYSACCESS(x)               (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
-/* PERIPHID4 Bit Fields */
-#define ROM_PERIPHID4_PERIPHID_MASK              0xFFFFFFFFu
-#define ROM_PERIPHID4_PERIPHID_SHIFT             0
-#define ROM_PERIPHID4_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
-/* PERIPHID5 Bit Fields */
-#define ROM_PERIPHID5_PERIPHID_MASK              0xFFFFFFFFu
-#define ROM_PERIPHID5_PERIPHID_SHIFT             0
-#define ROM_PERIPHID5_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
-/* PERIPHID6 Bit Fields */
-#define ROM_PERIPHID6_PERIPHID_MASK              0xFFFFFFFFu
-#define ROM_PERIPHID6_PERIPHID_SHIFT             0
-#define ROM_PERIPHID6_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
-/* PERIPHID7 Bit Fields */
-#define ROM_PERIPHID7_PERIPHID_MASK              0xFFFFFFFFu
-#define ROM_PERIPHID7_PERIPHID_SHIFT             0
-#define ROM_PERIPHID7_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
-/* PERIPHID0 Bit Fields */
-#define ROM_PERIPHID0_PERIPHID_MASK              0xFFFFFFFFu
-#define ROM_PERIPHID0_PERIPHID_SHIFT             0
-#define ROM_PERIPHID0_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
-/* PERIPHID1 Bit Fields */
-#define ROM_PERIPHID1_PERIPHID_MASK              0xFFFFFFFFu
-#define ROM_PERIPHID1_PERIPHID_SHIFT             0
-#define ROM_PERIPHID1_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
-/* PERIPHID2 Bit Fields */
-#define ROM_PERIPHID2_PERIPHID_MASK              0xFFFFFFFFu
-#define ROM_PERIPHID2_PERIPHID_SHIFT             0
-#define ROM_PERIPHID2_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
-/* PERIPHID3 Bit Fields */
-#define ROM_PERIPHID3_PERIPHID_MASK              0xFFFFFFFFu
-#define ROM_PERIPHID3_PERIPHID_SHIFT             0
-#define ROM_PERIPHID3_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
-/* COMPID Bit Fields */
-#define ROM_COMPID_COMPID_MASK                   0xFFFFFFFFu
-#define ROM_COMPID_COMPID_SHIFT                  0
-#define ROM_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
-
-/**
- * @}
- */ /* end of group ROM_Register_Masks */
-
-
-/* ROM - Peripheral instance base addresses */
-/** Peripheral ROM base address */
-#define ROM_BASE                                 (0xF0002000u)
-/** Peripheral ROM base pointer */
-#define ROM                                      ((ROM_Type *)ROM_BASE)
-/** Array initializer of ROM peripheral base pointers */
-#define ROM_BASES                                { ROM }
-
-/**
- * @}
- */ /* end of group ROM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- RTC Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
- * @{
- */
-
-/** RTC - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
-  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
-  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
-  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
-  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
-  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
-  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
-  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
-} RTC_Type;
-
-/* ----------------------------------------------------------------------------
-   -- RTC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RTC_Register_Masks RTC Register Masks
- * @{
- */
-
-/* TSR Bit Fields */
-#define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
-#define RTC_TSR_TSR_SHIFT                        0
-#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
-/* TPR Bit Fields */
-#define RTC_TPR_TPR_MASK                         0xFFFFu
-#define RTC_TPR_TPR_SHIFT                        0
-#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
-/* TAR Bit Fields */
-#define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
-#define RTC_TAR_TAR_SHIFT                        0
-#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
-/* TCR Bit Fields */
-#define RTC_TCR_TCR_MASK                         0xFFu
-#define RTC_TCR_TCR_SHIFT                        0
-#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
-#define RTC_TCR_CIR_MASK                         0xFF00u
-#define RTC_TCR_CIR_SHIFT                        8
-#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
-#define RTC_TCR_TCV_MASK                         0xFF0000u
-#define RTC_TCR_TCV_SHIFT                        16
-#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
-#define RTC_TCR_CIC_MASK                         0xFF000000u
-#define RTC_TCR_CIC_SHIFT                        24
-#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
-/* CR Bit Fields */
-#define RTC_CR_SWR_MASK                          0x1u
-#define RTC_CR_SWR_SHIFT                         0
-#define RTC_CR_WPE_MASK                          0x2u
-#define RTC_CR_WPE_SHIFT                         1
-#define RTC_CR_SUP_MASK                          0x4u
-#define RTC_CR_SUP_SHIFT                         2
-#define RTC_CR_UM_MASK                           0x8u
-#define RTC_CR_UM_SHIFT                          3
-#define RTC_CR_OSCE_MASK                         0x100u
-#define RTC_CR_OSCE_SHIFT                        8
-#define RTC_CR_CLKO_MASK                         0x200u
-#define RTC_CR_CLKO_SHIFT                        9
-#define RTC_CR_SC16P_MASK                        0x400u
-#define RTC_CR_SC16P_SHIFT                       10
-#define RTC_CR_SC8P_MASK                         0x800u
-#define RTC_CR_SC8P_SHIFT                        11
-#define RTC_CR_SC4P_MASK                         0x1000u
-#define RTC_CR_SC4P_SHIFT                        12
-#define RTC_CR_SC2P_MASK                         0x2000u
-#define RTC_CR_SC2P_SHIFT                        13
-/* SR Bit Fields */
-#define RTC_SR_TIF_MASK                          0x1u
-#define RTC_SR_TIF_SHIFT                         0
-#define RTC_SR_TOF_MASK                          0x2u
-#define RTC_SR_TOF_SHIFT                         1
-#define RTC_SR_TAF_MASK                          0x4u
-#define RTC_SR_TAF_SHIFT                         2
-#define RTC_SR_TCE_MASK                          0x10u
-#define RTC_SR_TCE_SHIFT                         4
-/* LR Bit Fields */
-#define RTC_LR_TCL_MASK                          0x8u
-#define RTC_LR_TCL_SHIFT                         3
-#define RTC_LR_CRL_MASK                          0x10u
-#define RTC_LR_CRL_SHIFT                         4
-#define RTC_LR_SRL_MASK                          0x20u
-#define RTC_LR_SRL_SHIFT                         5
-#define RTC_LR_LRL_MASK                          0x40u
-#define RTC_LR_LRL_SHIFT                         6
-/* IER Bit Fields */
-#define RTC_IER_TIIE_MASK                        0x1u
-#define RTC_IER_TIIE_SHIFT                       0
-#define RTC_IER_TOIE_MASK                        0x2u
-#define RTC_IER_TOIE_SHIFT                       1
-#define RTC_IER_TAIE_MASK                        0x4u
-#define RTC_IER_TAIE_SHIFT                       2
-#define RTC_IER_TSIE_MASK                        0x10u
-#define RTC_IER_TSIE_SHIFT                       4
-#define RTC_IER_WPON_MASK                        0x80u
-#define RTC_IER_WPON_SHIFT                       7
-
-/**
- * @}
- */ /* end of group RTC_Register_Masks */
-
-
-/* RTC - Peripheral instance base addresses */
-/** Peripheral RTC base address */
-#define RTC_BASE                                 (0x4003D000u)
-/** Peripheral RTC base pointer */
-#define RTC                                      ((RTC_Type *)RTC_BASE)
-/** Array initializer of RTC peripheral base pointers */
-#define RTC_BASES                                { RTC }
-
-/**
- * @}
- */ /* end of group RTC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- SIM Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
- * @{
- */
-
-/** SIM - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
-  __IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
-       uint8_t RESERVED_0[4092];
-  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
-       uint8_t RESERVED_1[4];
-  __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
-  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
-       uint8_t RESERVED_2[4];
-  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
-       uint8_t RESERVED_3[8];
-  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
-       uint8_t RESERVED_4[12];
-  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
-  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
-  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
-  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
-  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
-       uint8_t RESERVED_5[4];
-  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
-  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
-       uint8_t RESERVED_6[4];
-  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
-  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
-  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
-       uint8_t RESERVED_7[156];
-  __IO uint32_t COPC;                              /**< COP Control Register, offset: 0x1100 */
-  __O  uint32_t SRVCOP;                            /**< Service COP Register, offset: 0x1104 */
-} SIM_Type;
-
-/* ----------------------------------------------------------------------------
-   -- SIM Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SIM_Register_Masks SIM Register Masks
- * @{
- */
-
-/* SOPT1 Bit Fields */
-#define SIM_SOPT1_OSC32KSEL_MASK                 0xC0000u
-#define SIM_SOPT1_OSC32KSEL_SHIFT                18
-#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
-#define SIM_SOPT1_USBVSTBY_MASK                  0x20000000u
-#define SIM_SOPT1_USBVSTBY_SHIFT                 29
-#define SIM_SOPT1_USBSSTBY_MASK                  0x40000000u
-#define SIM_SOPT1_USBSSTBY_SHIFT                 30
-#define SIM_SOPT1_USBREGEN_MASK                  0x80000000u
-#define SIM_SOPT1_USBREGEN_SHIFT                 31
-/* SOPT1CFG Bit Fields */
-#define SIM_SOPT1CFG_URWE_MASK                   0x1000000u
-#define SIM_SOPT1CFG_URWE_SHIFT                  24
-#define SIM_SOPT1CFG_UVSWE_MASK                  0x2000000u
-#define SIM_SOPT1CFG_UVSWE_SHIFT                 25
-#define SIM_SOPT1CFG_USSWE_MASK                  0x4000000u
-#define SIM_SOPT1CFG_USSWE_SHIFT                 26
-/* SOPT2 Bit Fields */
-#define SIM_SOPT2_RTCCLKOUTSEL_MASK              0x10u
-#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             4
-#define SIM_SOPT2_CLKOUTSEL_MASK                 0xE0u
-#define SIM_SOPT2_CLKOUTSEL_SHIFT                5
-#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
-#define SIM_SOPT2_PLLFLLSEL_MASK                 0x10000u
-#define SIM_SOPT2_PLLFLLSEL_SHIFT                16
-#define SIM_SOPT2_USBSRC_MASK                    0x40000u
-#define SIM_SOPT2_USBSRC_SHIFT                   18
-#define SIM_SOPT2_TPMSRC_MASK                    0x3000000u
-#define SIM_SOPT2_TPMSRC_SHIFT                   24
-#define SIM_SOPT2_TPMSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
-#define SIM_SOPT2_UART0SRC_MASK                  0xC000000u
-#define SIM_SOPT2_UART0SRC_SHIFT                 26
-#define SIM_SOPT2_UART0SRC(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
-/* SOPT4 Bit Fields */
-#define SIM_SOPT4_TPM1CH0SRC_MASK                0x40000u
-#define SIM_SOPT4_TPM1CH0SRC_SHIFT               18
-#define SIM_SOPT4_TPM2CH0SRC_MASK                0x100000u
-#define SIM_SOPT4_TPM2CH0SRC_SHIFT               20
-#define SIM_SOPT4_TPM0CLKSEL_MASK                0x1000000u
-#define SIM_SOPT4_TPM0CLKSEL_SHIFT               24
-#define SIM_SOPT4_TPM1CLKSEL_MASK                0x2000000u
-#define SIM_SOPT4_TPM1CLKSEL_SHIFT               25
-#define SIM_SOPT4_TPM2CLKSEL_MASK                0x4000000u
-#define SIM_SOPT4_TPM2CLKSEL_SHIFT               26
-/* SOPT5 Bit Fields */
-#define SIM_SOPT5_UART0TXSRC_MASK                0x3u
-#define SIM_SOPT5_UART0TXSRC_SHIFT               0
-#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
-#define SIM_SOPT5_UART0RXSRC_MASK                0x4u
-#define SIM_SOPT5_UART0RXSRC_SHIFT               2
-#define SIM_SOPT5_UART1TXSRC_MASK                0x30u
-#define SIM_SOPT5_UART1TXSRC_SHIFT               4
-#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
-#define SIM_SOPT5_UART1RXSRC_MASK                0x40u
-#define SIM_SOPT5_UART1RXSRC_SHIFT               6
-#define SIM_SOPT5_UART0ODE_MASK                  0x10000u
-#define SIM_SOPT5_UART0ODE_SHIFT                 16
-#define SIM_SOPT5_UART1ODE_MASK                  0x20000u
-#define SIM_SOPT5_UART1ODE_SHIFT                 17
-#define SIM_SOPT5_UART2ODE_MASK                  0x40000u
-#define SIM_SOPT5_UART2ODE_SHIFT                 18
-/* SOPT7 Bit Fields */
-#define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
-#define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
-#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
-#define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
-#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
-#define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
-#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
-/* SDID Bit Fields */
-#define SIM_SDID_PINID_MASK                      0xFu
-#define SIM_SDID_PINID_SHIFT                     0
-#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
-#define SIM_SDID_DIEID_MASK                      0xF80u
-#define SIM_SDID_DIEID_SHIFT                     7
-#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
-#define SIM_SDID_REVID_MASK                      0xF000u
-#define SIM_SDID_REVID_SHIFT                     12
-#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
-#define SIM_SDID_SRAMSIZE_MASK                   0xF0000u
-#define SIM_SDID_SRAMSIZE_SHIFT                  16
-#define SIM_SDID_SRAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
-#define SIM_SDID_SERIESID_MASK                   0xF00000u
-#define SIM_SDID_SERIESID_SHIFT                  20
-#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
-#define SIM_SDID_SUBFAMID_MASK                   0xF000000u
-#define SIM_SDID_SUBFAMID_SHIFT                  24
-#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
-#define SIM_SDID_FAMID_MASK                      0xF0000000u
-#define SIM_SDID_FAMID_SHIFT                     28
-#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
-/* SCGC4 Bit Fields */
-#define SIM_SCGC4_I2C0_MASK                      0x40u
-#define SIM_SCGC4_I2C0_SHIFT                     6
-#define SIM_SCGC4_I2C1_MASK                      0x80u
-#define SIM_SCGC4_I2C1_SHIFT                     7
-#define SIM_SCGC4_UART0_MASK                     0x400u
-#define SIM_SCGC4_UART0_SHIFT                    10
-#define SIM_SCGC4_UART1_MASK                     0x800u
-#define SIM_SCGC4_UART1_SHIFT                    11
-#define SIM_SCGC4_UART2_MASK                     0x1000u
-#define SIM_SCGC4_UART2_SHIFT                    12
-#define SIM_SCGC4_USBOTG_MASK                    0x40000u
-#define SIM_SCGC4_USBOTG_SHIFT                   18
-#define SIM_SCGC4_CMP_MASK                       0x80000u
-#define SIM_SCGC4_CMP_SHIFT                      19
-#define SIM_SCGC4_SPI0_MASK                      0x400000u
-#define SIM_SCGC4_SPI0_SHIFT                     22
-#define SIM_SCGC4_SPI1_MASK                      0x800000u
-#define SIM_SCGC4_SPI1_SHIFT                     23
-/* SCGC5 Bit Fields */
-#define SIM_SCGC5_LPTMR_MASK                     0x1u
-#define SIM_SCGC5_LPTMR_SHIFT                    0
-#define SIM_SCGC5_TSI_MASK                       0x20u
-#define SIM_SCGC5_TSI_SHIFT                      5
-#define SIM_SCGC5_PORTA_MASK                     0x200u
-#define SIM_SCGC5_PORTA_SHIFT                    9
-#define SIM_SCGC5_PORTB_MASK                     0x400u
-#define SIM_SCGC5_PORTB_SHIFT                    10
-#define SIM_SCGC5_PORTC_MASK                     0x800u
-#define SIM_SCGC5_PORTC_SHIFT                    11
-#define SIM_SCGC5_PORTD_MASK                     0x1000u
-#define SIM_SCGC5_PORTD_SHIFT                    12
-#define SIM_SCGC5_PORTE_MASK                     0x2000u
-#define SIM_SCGC5_PORTE_SHIFT                    13
-/* SCGC6 Bit Fields */
-#define SIM_SCGC6_FTF_MASK                       0x1u
-#define SIM_SCGC6_FTF_SHIFT                      0
-#define SIM_SCGC6_DMAMUX_MASK                    0x2u
-#define SIM_SCGC6_DMAMUX_SHIFT                   1
-#define SIM_SCGC6_PIT_MASK                       0x800000u
-#define SIM_SCGC6_PIT_SHIFT                      23
-#define SIM_SCGC6_TPM0_MASK                      0x1000000u
-#define SIM_SCGC6_TPM0_SHIFT                     24
-#define SIM_SCGC6_TPM1_MASK                      0x2000000u
-#define SIM_SCGC6_TPM1_SHIFT                     25
-#define SIM_SCGC6_TPM2_MASK                      0x4000000u
-#define SIM_SCGC6_TPM2_SHIFT                     26
-#define SIM_SCGC6_ADC0_MASK                      0x8000000u
-#define SIM_SCGC6_ADC0_SHIFT                     27
-#define SIM_SCGC6_RTC_MASK                       0x20000000u
-#define SIM_SCGC6_RTC_SHIFT                      29
-#define SIM_SCGC6_DAC0_MASK                      0x80000000u
-#define SIM_SCGC6_DAC0_SHIFT                     31
-/* SCGC7 Bit Fields */
-#define SIM_SCGC7_DMA_MASK                       0x100u
-#define SIM_SCGC7_DMA_SHIFT                      8
-/* CLKDIV1 Bit Fields */
-#define SIM_CLKDIV1_OUTDIV4_MASK                 0x70000u
-#define SIM_CLKDIV1_OUTDIV4_SHIFT                16
-#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
-#define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
-#define SIM_CLKDIV1_OUTDIV1_SHIFT                28
-#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
-/* FCFG1 Bit Fields */
-#define SIM_FCFG1_FLASHDIS_MASK                  0x1u
-#define SIM_FCFG1_FLASHDIS_SHIFT                 0
-#define SIM_FCFG1_FLASHDOZE_MASK                 0x2u
-#define SIM_FCFG1_FLASHDOZE_SHIFT                1
-#define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
-#define SIM_FCFG1_PFSIZE_SHIFT                   24
-#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
-/* FCFG2 Bit Fields */
-#define SIM_FCFG2_MAXADDR_MASK                   0x7F000000u
-#define SIM_FCFG2_MAXADDR_SHIFT                  24
-#define SIM_FCFG2_MAXADDR(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
-/* UIDMH Bit Fields */
-#define SIM_UIDMH_UID_MASK                       0xFFFFu
-#define SIM_UIDMH_UID_SHIFT                      0
-#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
-/* UIDML Bit Fields */
-#define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
-#define SIM_UIDML_UID_SHIFT                      0
-#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
-/* UIDL Bit Fields */
-#define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
-#define SIM_UIDL_UID_SHIFT                       0
-#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
-/* COPC Bit Fields */
-#define SIM_COPC_COPW_MASK                       0x1u
-#define SIM_COPC_COPW_SHIFT                      0
-#define SIM_COPC_COPCLKS_MASK                    0x2u
-#define SIM_COPC_COPCLKS_SHIFT                   1
-#define SIM_COPC_COPT_MASK                       0xCu
-#define SIM_COPC_COPT_SHIFT                      2
-#define SIM_COPC_COPT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
-/* SRVCOP Bit Fields */
-#define SIM_SRVCOP_SRVCOP_MASK                   0xFFu
-#define SIM_SRVCOP_SRVCOP_SHIFT                  0
-#define SIM_SRVCOP_SRVCOP(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
-
-/**
- * @}
- */ /* end of group SIM_Register_Masks */
-
-
-/* SIM - Peripheral instance base addresses */
-/** Peripheral SIM base address */
-#define SIM_BASE                                 (0x40047000u)
-/** Peripheral SIM base pointer */
-#define SIM                                      ((SIM_Type *)SIM_BASE)
-/** Array initializer of SIM peripheral base pointers */
-#define SIM_BASES                                { SIM }
-
-/**
- * @}
- */ /* end of group SIM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- SMC Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
- * @{
- */
-
-/** SMC - Register Layout Typedef */
-typedef struct {
-  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
-  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
-  __IO uint8_t STOPCTRL;                           /**< Stop Control Register, offset: 0x2 */
-  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
-} SMC_Type;
-
-/* ----------------------------------------------------------------------------
-   -- SMC Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SMC_Register_Masks SMC Register Masks
- * @{
- */
-
-/* PMPROT Bit Fields */
-#define SMC_PMPROT_AVLLS_MASK                    0x2u
-#define SMC_PMPROT_AVLLS_SHIFT                   1
-#define SMC_PMPROT_ALLS_MASK                     0x8u
-#define SMC_PMPROT_ALLS_SHIFT                    3
-#define SMC_PMPROT_AVLP_MASK                     0x20u
-#define SMC_PMPROT_AVLP_SHIFT                    5
-/* PMCTRL Bit Fields */
-#define SMC_PMCTRL_STOPM_MASK                    0x7u
-#define SMC_PMCTRL_STOPM_SHIFT                   0
-#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
-#define SMC_PMCTRL_STOPA_MASK                    0x8u
-#define SMC_PMCTRL_STOPA_SHIFT                   3
-#define SMC_PMCTRL_RUNM_MASK                     0x60u
-#define SMC_PMCTRL_RUNM_SHIFT                    5
-#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
-/* STOPCTRL Bit Fields */
-#define SMC_STOPCTRL_VLLSM_MASK                  0x7u
-#define SMC_STOPCTRL_VLLSM_SHIFT                 0
-#define SMC_STOPCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
-#define SMC_STOPCTRL_PORPO_MASK                  0x20u
-#define SMC_STOPCTRL_PORPO_SHIFT                 5
-#define SMC_STOPCTRL_PSTOPO_MASK                 0xC0u
-#define SMC_STOPCTRL_PSTOPO_SHIFT                6
-#define SMC_STOPCTRL_PSTOPO(x)                   (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
-/* PMSTAT Bit Fields */
-#define SMC_PMSTAT_PMSTAT_MASK                   0x7Fu
-#define SMC_PMSTAT_PMSTAT_SHIFT                  0
-#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
-
-/**
- * @}
- */ /* end of group SMC_Register_Masks */
-
-
-/* SMC - Peripheral instance base addresses */
-/** Peripheral SMC base address */
-#define SMC_BASE                                 (0x4007E000u)
-/** Peripheral SMC base pointer */
-#define SMC                                      ((SMC_Type *)SMC_BASE)
-/** Array initializer of SMC peripheral base pointers */
-#define SMC_BASES                                { SMC }
-
-/**
- * @}
- */ /* end of group SMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- SPI Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
- * @{
- */
-
-/** SPI - Register Layout Typedef */
-typedef struct {
-  __IO uint8_t C1;                                 /**< SPI control register 1, offset: 0x0 */
-  __IO uint8_t C2;                                 /**< SPI control register 2, offset: 0x1 */
-  __IO uint8_t BR;                                 /**< SPI baud rate register, offset: 0x2 */
-  __I  uint8_t S;                                  /**< SPI status register, offset: 0x3 */
-       uint8_t RESERVED_0[1];
-  __IO uint8_t D;                                  /**< SPI data register, offset: 0x5 */
-       uint8_t RESERVED_1[1];
-  __IO uint8_t M;                                  /**< SPI match register, offset: 0x7 */
-} SPI_Type;
-
-/* ----------------------------------------------------------------------------
-   -- SPI Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SPI_Register_Masks SPI Register Masks
- * @{
- */
-
-/* C1 Bit Fields */
-#define SPI_C1_LSBFE_MASK                        0x1u
-#define SPI_C1_LSBFE_SHIFT                       0
-#define SPI_C1_SSOE_MASK                         0x2u
-#define SPI_C1_SSOE_SHIFT                        1
-#define SPI_C1_CPHA_MASK                         0x4u
-#define SPI_C1_CPHA_SHIFT                        2
-#define SPI_C1_CPOL_MASK                         0x8u
-#define SPI_C1_CPOL_SHIFT                        3
-#define SPI_C1_MSTR_MASK                         0x10u
-#define SPI_C1_MSTR_SHIFT                        4
-#define SPI_C1_SPTIE_MASK                        0x20u
-#define SPI_C1_SPTIE_SHIFT                       5
-#define SPI_C1_SPE_MASK                          0x40u
-#define SPI_C1_SPE_SHIFT                         6
-#define SPI_C1_SPIE_MASK                         0x80u
-#define SPI_C1_SPIE_SHIFT                        7
-/* C2 Bit Fields */
-#define SPI_C2_SPC0_MASK                         0x1u
-#define SPI_C2_SPC0_SHIFT                        0
-#define SPI_C2_SPISWAI_MASK                      0x2u
-#define SPI_C2_SPISWAI_SHIFT                     1
-#define SPI_C2_RXDMAE_MASK                       0x4u
-#define SPI_C2_RXDMAE_SHIFT                      2
-#define SPI_C2_BIDIROE_MASK                      0x8u
-#define SPI_C2_BIDIROE_SHIFT                     3
-#define SPI_C2_MODFEN_MASK                       0x10u
-#define SPI_C2_MODFEN_SHIFT                      4
-#define SPI_C2_TXDMAE_MASK                       0x20u
-#define SPI_C2_TXDMAE_SHIFT                      5
-#define SPI_C2_SPLPIE_MASK                       0x40u
-#define SPI_C2_SPLPIE_SHIFT                      6
-#define SPI_C2_SPMIE_MASK                        0x80u
-#define SPI_C2_SPMIE_SHIFT                       7
-/* BR Bit Fields */
-#define SPI_BR_SPR_MASK                          0xFu
-#define SPI_BR_SPR_SHIFT                         0
-#define SPI_BR_SPR(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
-#define SPI_BR_SPPR_MASK                         0x70u
-#define SPI_BR_SPPR_SHIFT                        4
-#define SPI_BR_SPPR(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
-/* S Bit Fields */
-#define SPI_S_MODF_MASK                          0x10u
-#define SPI_S_MODF_SHIFT                         4
-#define SPI_S_SPTEF_MASK                         0x20u
-#define SPI_S_SPTEF_SHIFT                        5
-#define SPI_S_SPMF_MASK                          0x40u
-#define SPI_S_SPMF_SHIFT                         6
-#define SPI_S_SPRF_MASK                          0x80u
-#define SPI_S_SPRF_SHIFT                         7
-/* D Bit Fields */
-#define SPI_D_Bits_MASK                          0xFFu
-#define SPI_D_Bits_SHIFT                         0
-#define SPI_D_Bits(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
-/* M Bit Fields */
-#define SPI_M_Bits_MASK                          0xFFu
-#define SPI_M_Bits_SHIFT                         0
-#define SPI_M_Bits(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
-
-/**
- * @}
- */ /* end of group SPI_Register_Masks */
-
-
-/* SPI - Peripheral instance base addresses */
-/** Peripheral SPI0 base address */
-#define SPI0_BASE                                (0x40076000u)
-/** Peripheral SPI0 base pointer */
-#define SPI0                                     ((SPI_Type *)SPI0_BASE)
-/** Peripheral SPI1 base address */
-#define SPI1_BASE                                (0x40077000u)
-/** Peripheral SPI1 base pointer */
-#define SPI1                                     ((SPI_Type *)SPI1_BASE)
-/** Array initializer of SPI peripheral base pointers */
-#define SPI_BASES                                { SPI0, SPI1 }
-
-/**
- * @}
- */ /* end of group SPI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- TPM Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
- * @{
- */
-
-/** TPM - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t SC;                                /**< Status and Control, offset: 0x0 */
-  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
-  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
-  struct {                                         /* offset: 0xC, array step: 0x8 */
-    __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
-    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
-  } CONTROLS[6];
-       uint8_t RESERVED_0[20];
-  __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x50 */
-       uint8_t RESERVED_1[48];
-  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
-} TPM_Type;
-
-/* ----------------------------------------------------------------------------
-   -- TPM Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup TPM_Register_Masks TPM Register Masks
- * @{
- */
-
-/* SC Bit Fields */
-#define TPM_SC_PS_MASK                           0x7u
-#define TPM_SC_PS_SHIFT                          0
-#define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
-#define TPM_SC_CMOD_MASK                         0x18u
-#define TPM_SC_CMOD_SHIFT                        3
-#define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
-#define TPM_SC_CPWMS_MASK                        0x20u
-#define TPM_SC_CPWMS_SHIFT                       5
-#define TPM_SC_TOIE_MASK                         0x40u
-#define TPM_SC_TOIE_SHIFT                        6
-#define TPM_SC_TOF_MASK                          0x80u
-#define TPM_SC_TOF_SHIFT                         7
-#define TPM_SC_DMA_MASK                          0x100u
-#define TPM_SC_DMA_SHIFT                         8
-/* CNT Bit Fields */
-#define TPM_CNT_COUNT_MASK                       0xFFFFu
-#define TPM_CNT_COUNT_SHIFT                      0
-#define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
-/* MOD Bit Fields */
-#define TPM_MOD_MOD_MASK                         0xFFFFu
-#define TPM_MOD_MOD_SHIFT                        0
-#define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
-/* CnSC Bit Fields */
-#define TPM_CnSC_DMA_MASK                        0x1u
-#define TPM_CnSC_DMA_SHIFT                       0
-#define TPM_CnSC_ELSA_MASK                       0x4u
-#define TPM_CnSC_ELSA_SHIFT                      2
-#define TPM_CnSC_ELSB_MASK                       0x8u
-#define TPM_CnSC_ELSB_SHIFT                      3
-#define TPM_CnSC_MSA_MASK                        0x10u
-#define TPM_CnSC_MSA_SHIFT                       4
-#define TPM_CnSC_MSB_MASK                        0x20u
-#define TPM_CnSC_MSB_SHIFT                       5
-#define TPM_CnSC_CHIE_MASK                       0x40u
-#define TPM_CnSC_CHIE_SHIFT                      6
-#define TPM_CnSC_CHF_MASK                        0x80u
-#define TPM_CnSC_CHF_SHIFT                       7
-/* CnV Bit Fields */
-#define TPM_CnV_VAL_MASK                         0xFFFFu
-#define TPM_CnV_VAL_SHIFT                        0
-#define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
-/* STATUS Bit Fields */
-#define TPM_STATUS_CH0F_MASK                     0x1u
-#define TPM_STATUS_CH0F_SHIFT                    0
-#define TPM_STATUS_CH1F_MASK                     0x2u
-#define TPM_STATUS_CH1F_SHIFT                    1
-#define TPM_STATUS_CH2F_MASK                     0x4u
-#define TPM_STATUS_CH2F_SHIFT                    2
-#define TPM_STATUS_CH3F_MASK                     0x8u
-#define TPM_STATUS_CH3F_SHIFT                    3
-#define TPM_STATUS_CH4F_MASK                     0x10u
-#define TPM_STATUS_CH4F_SHIFT                    4
-#define TPM_STATUS_CH5F_MASK                     0x20u
-#define TPM_STATUS_CH5F_SHIFT                    5
-#define TPM_STATUS_TOF_MASK                      0x100u
-#define TPM_STATUS_TOF_SHIFT                     8
-/* CONF Bit Fields */
-#define TPM_CONF_DOZEEN_MASK                     0x20u
-#define TPM_CONF_DOZEEN_SHIFT                    5
-#define TPM_CONF_DBGMODE_MASK                    0xC0u
-#define TPM_CONF_DBGMODE_SHIFT                   6
-#define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
-#define TPM_CONF_GTBEEN_MASK                     0x200u
-#define TPM_CONF_GTBEEN_SHIFT                    9
-#define TPM_CONF_CSOT_MASK                       0x10000u
-#define TPM_CONF_CSOT_SHIFT                      16
-#define TPM_CONF_CSOO_MASK                       0x20000u
-#define TPM_CONF_CSOO_SHIFT                      17
-#define TPM_CONF_CROT_MASK                       0x40000u
-#define TPM_CONF_CROT_SHIFT                      18
-#define TPM_CONF_TRGSEL_MASK                     0xF000000u
-#define TPM_CONF_TRGSEL_SHIFT                    24
-#define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
-
-/**
- * @}
- */ /* end of group TPM_Register_Masks */
-
-
-/* TPM - Peripheral instance base addresses */
-/** Peripheral TPM0 base address */
-#define TPM0_BASE                                (0x40038000u)
-/** Peripheral TPM0 base pointer */
-#define TPM0                                     ((TPM_Type *)TPM0_BASE)
-/** Peripheral TPM1 base address */
-#define TPM1_BASE                                (0x40039000u)
-/** Peripheral TPM1 base pointer */
-#define TPM1                                     ((TPM_Type *)TPM1_BASE)
-/** Peripheral TPM2 base address */
-#define TPM2_BASE                                (0x4003A000u)
-/** Peripheral TPM2 base pointer */
-#define TPM2                                     ((TPM_Type *)TPM2_BASE)
-/** Array initializer of TPM peripheral base pointers */
-#define TPM_BASES                                { TPM0, TPM1, TPM2 }
-
-/**
- * @}
- */ /* end of group TPM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- TSI Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
- * @{
- */
-
-/** TSI - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t GENCS;                             /**< TSI General Control and Status Register, offset: 0x0 */
-  __IO uint32_t DATA;                              /**< TSI DATA Register, offset: 0x4 */
-  __IO uint32_t TSHD;                              /**< TSI Threshold Register, offset: 0x8 */
-} TSI_Type;
-
-/* ----------------------------------------------------------------------------
-   -- TSI Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup TSI_Register_Masks TSI Register Masks
- * @{
- */
-
-/* GENCS Bit Fields */
-#define TSI_GENCS_CURSW_MASK                     0x2u
-#define TSI_GENCS_CURSW_SHIFT                    1
-#define TSI_GENCS_EOSF_MASK                      0x4u
-#define TSI_GENCS_EOSF_SHIFT                     2
-#define TSI_GENCS_SCNIP_MASK                     0x8u
-#define TSI_GENCS_SCNIP_SHIFT                    3
-#define TSI_GENCS_STM_MASK                       0x10u
-#define TSI_GENCS_STM_SHIFT                      4
-#define TSI_GENCS_STPE_MASK                      0x20u
-#define TSI_GENCS_STPE_SHIFT                     5
-#define TSI_GENCS_TSIIEN_MASK                    0x40u
-#define TSI_GENCS_TSIIEN_SHIFT                   6
-#define TSI_GENCS_TSIEN_MASK                     0x80u
-#define TSI_GENCS_TSIEN_SHIFT                    7
-#define TSI_GENCS_NSCN_MASK                      0x1F00u
-#define TSI_GENCS_NSCN_SHIFT                     8
-#define TSI_GENCS_NSCN(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
-#define TSI_GENCS_PS_MASK                        0xE000u
-#define TSI_GENCS_PS_SHIFT                       13
-#define TSI_GENCS_PS(x)                          (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
-#define TSI_GENCS_EXTCHRG_MASK                   0x70000u
-#define TSI_GENCS_EXTCHRG_SHIFT                  16
-#define TSI_GENCS_EXTCHRG(x)                     (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
-#define TSI_GENCS_DVOLT_MASK                     0x180000u
-#define TSI_GENCS_DVOLT_SHIFT                    19
-#define TSI_GENCS_DVOLT(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
-#define TSI_GENCS_REFCHRG_MASK                   0xE00000u
-#define TSI_GENCS_REFCHRG_SHIFT                  21
-#define TSI_GENCS_REFCHRG(x)                     (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
-#define TSI_GENCS_MODE_MASK                      0xF000000u
-#define TSI_GENCS_MODE_SHIFT                     24
-#define TSI_GENCS_MODE(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
-#define TSI_GENCS_ESOR_MASK                      0x10000000u
-#define TSI_GENCS_ESOR_SHIFT                     28
-#define TSI_GENCS_OUTRGF_MASK                    0x80000000u
-#define TSI_GENCS_OUTRGF_SHIFT                   31
-/* DATA Bit Fields */
-#define TSI_DATA_TSICNT_MASK                     0xFFFFu
-#define TSI_DATA_TSICNT_SHIFT                    0
-#define TSI_DATA_TSICNT(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
-#define TSI_DATA_SWTS_MASK                       0x400000u
-#define TSI_DATA_SWTS_SHIFT                      22
-#define TSI_DATA_DMAEN_MASK                      0x800000u
-#define TSI_DATA_DMAEN_SHIFT                     23
-#define TSI_DATA_TSICH_MASK                      0xF0000000u
-#define TSI_DATA_TSICH_SHIFT                     28
-#define TSI_DATA_TSICH(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
-/* TSHD Bit Fields */
-#define TSI_TSHD_THRESL_MASK                     0xFFFFu
-#define TSI_TSHD_THRESL_SHIFT                    0
-#define TSI_TSHD_THRESL(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
-#define TSI_TSHD_THRESH_MASK                     0xFFFF0000u
-#define TSI_TSHD_THRESH_SHIFT                    16
-#define TSI_TSHD_THRESH(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
-
-/**
- * @}
- */ /* end of group TSI_Register_Masks */
-
-
-/* TSI - Peripheral instance base addresses */
-/** Peripheral TSI0 base address */
-#define TSI0_BASE                                (0x40045000u)
-/** Peripheral TSI0 base pointer */
-#define TSI0                                     ((TSI_Type *)TSI0_BASE)
-/** Array initializer of TSI peripheral base pointers */
-#define TSI_BASES                                { TSI0 }
-
-/**
- * @}
- */ /* end of group TSI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- UART Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
- * @{
- */
-
-/** UART - Register Layout Typedef */
-typedef struct {
-  __IO uint8_t BDH;                                /**< UART Baud Rate Register: High, offset: 0x0 */
-  __IO uint8_t BDL;                                /**< UART Baud Rate Register: Low, offset: 0x1 */
-  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
-  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
-  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
-  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
-  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
-  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
-  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0x8 */
-} UART_Type;
-
-/* ----------------------------------------------------------------------------
-   -- UART Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup UART_Register_Masks UART Register Masks
- * @{
- */
-
-/* BDH Bit Fields */
-#define UART_BDH_SBR_MASK                        0x1Fu
-#define UART_BDH_SBR_SHIFT                       0
-#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
-#define UART_BDH_SBNS_MASK                       0x20u
-#define UART_BDH_SBNS_SHIFT                      5
-#define UART_BDH_RXEDGIE_MASK                    0x40u
-#define UART_BDH_RXEDGIE_SHIFT                   6
-#define UART_BDH_LBKDIE_MASK                     0x80u
-#define UART_BDH_LBKDIE_SHIFT                    7
-/* BDL Bit Fields */
-#define UART_BDL_SBR_MASK                        0xFFu
-#define UART_BDL_SBR_SHIFT                       0
-#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
-/* C1 Bit Fields */
-#define UART_C1_PT_MASK                          0x1u
-#define UART_C1_PT_SHIFT                         0
-#define UART_C1_PE_MASK                          0x2u
-#define UART_C1_PE_SHIFT                         1
-#define UART_C1_ILT_MASK                         0x4u
-#define UART_C1_ILT_SHIFT                        2
-#define UART_C1_WAKE_MASK                        0x8u
-#define UART_C1_WAKE_SHIFT                       3
-#define UART_C1_M_MASK                           0x10u
-#define UART_C1_M_SHIFT                          4
-#define UART_C1_RSRC_MASK                        0x20u
-#define UART_C1_RSRC_SHIFT                       5
-#define UART_C1_UARTSWAI_MASK                    0x40u
-#define UART_C1_UARTSWAI_SHIFT                   6
-#define UART_C1_LOOPS_MASK                       0x80u
-#define UART_C1_LOOPS_SHIFT                      7
-/* C2 Bit Fields */
-#define UART_C2_SBK_MASK                         0x1u
-#define UART_C2_SBK_SHIFT                        0
-#define UART_C2_RWU_MASK                         0x2u
-#define UART_C2_RWU_SHIFT                        1
-#define UART_C2_RE_MASK                          0x4u
-#define UART_C2_RE_SHIFT                         2
-#define UART_C2_TE_MASK                          0x8u
-#define UART_C2_TE_SHIFT                         3
-#define UART_C2_ILIE_MASK                        0x10u
-#define UART_C2_ILIE_SHIFT                       4
-#define UART_C2_RIE_MASK                         0x20u
-#define UART_C2_RIE_SHIFT                        5
-#define UART_C2_TCIE_MASK                        0x40u
-#define UART_C2_TCIE_SHIFT                       6
-#define UART_C2_TIE_MASK                         0x80u
-#define UART_C2_TIE_SHIFT                        7
-/* S1 Bit Fields */
-#define UART_S1_PF_MASK                          0x1u
-#define UART_S1_PF_SHIFT                         0
-#define UART_S1_FE_MASK                          0x2u
-#define UART_S1_FE_SHIFT                         1
-#define UART_S1_NF_MASK                          0x4u
-#define UART_S1_NF_SHIFT                         2
-#define UART_S1_OR_MASK                          0x8u
-#define UART_S1_OR_SHIFT                         3
-#define UART_S1_IDLE_MASK                        0x10u
-#define UART_S1_IDLE_SHIFT                       4
-#define UART_S1_RDRF_MASK                        0x20u
-#define UART_S1_RDRF_SHIFT                       5
-#define UART_S1_TC_MASK                          0x40u
-#define UART_S1_TC_SHIFT                         6
-#define UART_S1_TDRE_MASK                        0x80u
-#define UART_S1_TDRE_SHIFT                       7
-/* S2 Bit Fields */
-#define UART_S2_RAF_MASK                         0x1u
-#define UART_S2_RAF_SHIFT                        0
-#define UART_S2_LBKDE_MASK                       0x2u
-#define UART_S2_LBKDE_SHIFT                      1
-#define UART_S2_BRK13_MASK                       0x4u
-#define UART_S2_BRK13_SHIFT                      2
-#define UART_S2_RWUID_MASK                       0x8u
-#define UART_S2_RWUID_SHIFT                      3
-#define UART_S2_RXINV_MASK                       0x10u
-#define UART_S2_RXINV_SHIFT                      4
-#define UART_S2_RXEDGIF_MASK                     0x40u
-#define UART_S2_RXEDGIF_SHIFT                    6
-#define UART_S2_LBKDIF_MASK                      0x80u
-#define UART_S2_LBKDIF_SHIFT                     7
-/* C3 Bit Fields */
-#define UART_C3_PEIE_MASK                        0x1u
-#define UART_C3_PEIE_SHIFT                       0
-#define UART_C3_FEIE_MASK                        0x2u
-#define UART_C3_FEIE_SHIFT                       1
-#define UART_C3_NEIE_MASK                        0x4u
-#define UART_C3_NEIE_SHIFT                       2
-#define UART_C3_ORIE_MASK                        0x8u
-#define UART_C3_ORIE_SHIFT                       3
-#define UART_C3_TXINV_MASK                       0x10u
-#define UART_C3_TXINV_SHIFT                      4
-#define UART_C3_TXDIR_MASK                       0x20u
-#define UART_C3_TXDIR_SHIFT                      5
-#define UART_C3_T8_MASK                          0x40u
-#define UART_C3_T8_SHIFT                         6
-#define UART_C3_R8_MASK                          0x80u
-#define UART_C3_R8_SHIFT                         7
-/* D Bit Fields */
-#define UART_D_R0T0_MASK                         0x1u
-#define UART_D_R0T0_SHIFT                        0
-#define UART_D_R1T1_MASK                         0x2u
-#define UART_D_R1T1_SHIFT                        1
-#define UART_D_R2T2_MASK                         0x4u
-#define UART_D_R2T2_SHIFT                        2
-#define UART_D_R3T3_MASK                         0x8u
-#define UART_D_R3T3_SHIFT                        3
-#define UART_D_R4T4_MASK                         0x10u
-#define UART_D_R4T4_SHIFT                        4
-#define UART_D_R5T5_MASK                         0x20u
-#define UART_D_R5T5_SHIFT                        5
-#define UART_D_R6T6_MASK                         0x40u
-#define UART_D_R6T6_SHIFT                        6
-#define UART_D_R7T7_MASK                         0x80u
-#define UART_D_R7T7_SHIFT                        7
-/* C4 Bit Fields */
-#define UART_C4_LBKDDMAS_MASK                    0x8u
-#define UART_C4_LBKDDMAS_SHIFT                   3
-#define UART_C4_ILDMAS_MASK                      0x10u
-#define UART_C4_ILDMAS_SHIFT                     4
-#define UART_C4_RDMAS_MASK                       0x20u
-#define UART_C4_RDMAS_SHIFT                      5
-#define UART_C4_TCDMAS_MASK                      0x40u
-#define UART_C4_TCDMAS_SHIFT                     6
-#define UART_C4_TDMAS_MASK                       0x80u
-#define UART_C4_TDMAS_SHIFT                      7
-
-/**
- * @}
- */ /* end of group UART_Register_Masks */
-
-
-/* UART - Peripheral instance base addresses */
-/** Peripheral UART1 base address */
-#define UART1_BASE                               (0x4006B000u)
-/** Peripheral UART1 base pointer */
-#define UART1                                    ((UART_Type *)UART1_BASE)
-/** Peripheral UART2 base address */
-#define UART2_BASE                               (0x4006C000u)
-/** Peripheral UART2 base pointer */
-#define UART2                                    ((UART_Type *)UART2_BASE)
-/** Array initializer of UART peripheral base pointers */
-#define UART_BASES                               { UART1, UART2 }
-
-/**
- * @}
- */ /* end of group UART_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- UARTLP Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer
- * @{
- */
-
-/** UARTLP - Register Layout Typedef */
-typedef struct {
-  __IO uint8_t BDH;                                /**< UART Baud Rate Register High, offset: 0x0 */
-  __IO uint8_t BDL;                                /**< UART Baud Rate Register Low, offset: 0x1 */
-  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
-  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
-  __IO uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
-  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
-  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
-  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
-  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
-  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
-  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
-  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
-} UARTLP_Type;
-
-/* ----------------------------------------------------------------------------
-   -- UARTLP Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup UARTLP_Register_Masks UARTLP Register Masks
- * @{
- */
-
-/* BDH Bit Fields */
-#define UARTLP_BDH_SBR_MASK                      0x1Fu
-#define UARTLP_BDH_SBR_SHIFT                     0
-#define UARTLP_BDH_SBR(x)                        (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK)
-#define UARTLP_BDH_SBNS_MASK                     0x20u
-#define UARTLP_BDH_SBNS_SHIFT                    5
-#define UARTLP_BDH_RXEDGIE_MASK                  0x40u
-#define UARTLP_BDH_RXEDGIE_SHIFT                 6
-#define UARTLP_BDH_LBKDIE_MASK                   0x80u
-#define UARTLP_BDH_LBKDIE_SHIFT                  7
-/* BDL Bit Fields */
-#define UARTLP_BDL_SBR_MASK                      0xFFu
-#define UARTLP_BDL_SBR_SHIFT                     0
-#define UARTLP_BDL_SBR(x)                        (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK)
-/* C1 Bit Fields */
-#define UARTLP_C1_PT_MASK                        0x1u
-#define UARTLP_C1_PT_SHIFT                       0
-#define UARTLP_C1_PE_MASK                        0x2u
-#define UARTLP_C1_PE_SHIFT                       1
-#define UARTLP_C1_ILT_MASK                       0x4u
-#define UARTLP_C1_ILT_SHIFT                      2
-#define UARTLP_C1_WAKE_MASK                      0x8u
-#define UARTLP_C1_WAKE_SHIFT                     3
-#define UARTLP_C1_M_MASK                         0x10u
-#define UARTLP_C1_M_SHIFT                        4
-#define UARTLP_C1_RSRC_MASK                      0x20u
-#define UARTLP_C1_RSRC_SHIFT                     5
-#define UARTLP_C1_DOZEEN_MASK                    0x40u
-#define UARTLP_C1_DOZEEN_SHIFT                   6
-#define UARTLP_C1_LOOPS_MASK                     0x80u
-#define UARTLP_C1_LOOPS_SHIFT                    7
-/* C2 Bit Fields */
-#define UARTLP_C2_SBK_MASK                       0x1u
-#define UARTLP_C2_SBK_SHIFT                      0
-#define UARTLP_C2_RWU_MASK                       0x2u
-#define UARTLP_C2_RWU_SHIFT                      1
-#define UARTLP_C2_RE_MASK                        0x4u
-#define UARTLP_C2_RE_SHIFT                       2
-#define UARTLP_C2_TE_MASK                        0x8u
-#define UARTLP_C2_TE_SHIFT                       3
-#define UARTLP_C2_ILIE_MASK                      0x10u
-#define UARTLP_C2_ILIE_SHIFT                     4
-#define UARTLP_C2_RIE_MASK                       0x20u
-#define UARTLP_C2_RIE_SHIFT                      5
-#define UARTLP_C2_TCIE_MASK                      0x40u
-#define UARTLP_C2_TCIE_SHIFT                     6
-#define UARTLP_C2_TIE_MASK                       0x80u
-#define UARTLP_C2_TIE_SHIFT                      7
-/* S1 Bit Fields */
-#define UARTLP_S1_PF_MASK                        0x1u
-#define UARTLP_S1_PF_SHIFT                       0
-#define UARTLP_S1_FE_MASK                        0x2u
-#define UARTLP_S1_FE_SHIFT                       1
-#define UARTLP_S1_NF_MASK                        0x4u
-#define UARTLP_S1_NF_SHIFT                       2
-#define UARTLP_S1_OR_MASK                        0x8u
-#define UARTLP_S1_OR_SHIFT                       3
-#define UARTLP_S1_IDLE_MASK                      0x10u
-#define UARTLP_S1_IDLE_SHIFT                     4
-#define UARTLP_S1_RDRF_MASK                      0x20u
-#define UARTLP_S1_RDRF_SHIFT                     5
-#define UARTLP_S1_TC_MASK                        0x40u
-#define UARTLP_S1_TC_SHIFT                       6
-#define UARTLP_S1_TDRE_MASK                      0x80u
-#define UARTLP_S1_TDRE_SHIFT                     7
-/* S2 Bit Fields */
-#define UARTLP_S2_RAF_MASK                       0x1u
-#define UARTLP_S2_RAF_SHIFT                      0
-#define UARTLP_S2_LBKDE_MASK                     0x2u
-#define UARTLP_S2_LBKDE_SHIFT                    1
-#define UARTLP_S2_BRK13_MASK                     0x4u
-#define UARTLP_S2_BRK13_SHIFT                    2
-#define UARTLP_S2_RWUID_MASK                     0x8u
-#define UARTLP_S2_RWUID_SHIFT                    3
-#define UARTLP_S2_RXINV_MASK                     0x10u
-#define UARTLP_S2_RXINV_SHIFT                    4
-#define UARTLP_S2_MSBF_MASK                      0x20u
-#define UARTLP_S2_MSBF_SHIFT                     5
-#define UARTLP_S2_RXEDGIF_MASK                   0x40u
-#define UARTLP_S2_RXEDGIF_SHIFT                  6
-#define UARTLP_S2_LBKDIF_MASK                    0x80u
-#define UARTLP_S2_LBKDIF_SHIFT                   7
-/* C3 Bit Fields */
-#define UARTLP_C3_PEIE_MASK                      0x1u
-#define UARTLP_C3_PEIE_SHIFT                     0
-#define UARTLP_C3_FEIE_MASK                      0x2u
-#define UARTLP_C3_FEIE_SHIFT                     1
-#define UARTLP_C3_NEIE_MASK                      0x4u
-#define UARTLP_C3_NEIE_SHIFT                     2
-#define UARTLP_C3_ORIE_MASK                      0x8u
-#define UARTLP_C3_ORIE_SHIFT                     3
-#define UARTLP_C3_TXINV_MASK                     0x10u
-#define UARTLP_C3_TXINV_SHIFT                    4
-#define UARTLP_C3_TXDIR_MASK                     0x20u
-#define UARTLP_C3_TXDIR_SHIFT                    5
-#define UARTLP_C3_R9T8_MASK                      0x40u
-#define UARTLP_C3_R9T8_SHIFT                     6
-#define UARTLP_C3_R8T9_MASK                      0x80u
-#define UARTLP_C3_R8T9_SHIFT                     7
-/* D Bit Fields */
-#define UARTLP_D_R0T0_MASK                       0x1u
-#define UARTLP_D_R0T0_SHIFT                      0
-#define UARTLP_D_R1T1_MASK                       0x2u
-#define UARTLP_D_R1T1_SHIFT                      1
-#define UARTLP_D_R2T2_MASK                       0x4u
-#define UARTLP_D_R2T2_SHIFT                      2
-#define UARTLP_D_R3T3_MASK                       0x8u
-#define UARTLP_D_R3T3_SHIFT                      3
-#define UARTLP_D_R4T4_MASK                       0x10u
-#define UARTLP_D_R4T4_SHIFT                      4
-#define UARTLP_D_R5T5_MASK                       0x20u
-#define UARTLP_D_R5T5_SHIFT                      5
-#define UARTLP_D_R6T6_MASK                       0x40u
-#define UARTLP_D_R6T6_SHIFT                      6
-#define UARTLP_D_R7T7_MASK                       0x80u
-#define UARTLP_D_R7T7_SHIFT                      7
-/* MA1 Bit Fields */
-#define UARTLP_MA1_MA_MASK                       0xFFu
-#define UARTLP_MA1_MA_SHIFT                      0
-#define UARTLP_MA1_MA(x)                         (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK)
-/* MA2 Bit Fields */
-#define UARTLP_MA2_MA_MASK                       0xFFu
-#define UARTLP_MA2_MA_SHIFT                      0
-#define UARTLP_MA2_MA(x)                         (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK)
-/* C4 Bit Fields */
-#define UARTLP_C4_OSR_MASK                       0x1Fu
-#define UARTLP_C4_OSR_SHIFT                      0
-#define UARTLP_C4_OSR(x)                         (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK)
-#define UARTLP_C4_M10_MASK                       0x20u
-#define UARTLP_C4_M10_SHIFT                      5
-#define UARTLP_C4_MAEN2_MASK                     0x40u
-#define UARTLP_C4_MAEN2_SHIFT                    6
-#define UARTLP_C4_MAEN1_MASK                     0x80u
-#define UARTLP_C4_MAEN1_SHIFT                    7
-/* C5 Bit Fields */
-#define UARTLP_C5_RESYNCDIS_MASK                 0x1u
-#define UARTLP_C5_RESYNCDIS_SHIFT                0
-#define UARTLP_C5_BOTHEDGE_MASK                  0x2u
-#define UARTLP_C5_BOTHEDGE_SHIFT                 1
-#define UARTLP_C5_RDMAE_MASK                     0x20u
-#define UARTLP_C5_RDMAE_SHIFT                    5
-#define UARTLP_C5_TDMAE_MASK                     0x80u
-#define UARTLP_C5_TDMAE_SHIFT                    7
-
-/**
- * @}
- */ /* end of group UARTLP_Register_Masks */
-
-
-/* UARTLP - Peripheral instance base addresses */
-/** Peripheral UART0 base address */
-#define UART0_BASE                               (0x4006A000u)
-/** Peripheral UART0 base pointer */
-#define UART0                                    ((UARTLP_Type *)UART0_BASE)
-/** Array initializer of UARTLP peripheral base pointers */
-#define UARTLP_BASES                             { UART0 }
-
-/**
- * @}
- */ /* end of group UARTLP_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- USB Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
- * @{
- */
-
-/** USB - Register Layout Typedef */
-typedef struct {
-  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
-       uint8_t RESERVED_0[3];
-  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
-       uint8_t RESERVED_1[3];
-  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
-       uint8_t RESERVED_2[3];
-  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
-       uint8_t RESERVED_3[3];
-  __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status register, offset: 0x10 */
-       uint8_t RESERVED_4[3];
-  __IO uint8_t OTGICR;                             /**< OTG Interrupt Control Register, offset: 0x14 */
-       uint8_t RESERVED_5[3];
-  __IO uint8_t OTGSTAT;                            /**< OTG Status register, offset: 0x18 */
-       uint8_t RESERVED_6[3];
-  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
-       uint8_t RESERVED_7[99];
-  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
-       uint8_t RESERVED_8[3];
-  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
-       uint8_t RESERVED_9[3];
-  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
-       uint8_t RESERVED_10[3];
-  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
-       uint8_t RESERVED_11[3];
-  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
-       uint8_t RESERVED_12[3];
-  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
-       uint8_t RESERVED_13[3];
-  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
-       uint8_t RESERVED_14[3];
-  __IO uint8_t BDTPAGE1;                           /**< BDT Page Register 1, offset: 0x9C */
-       uint8_t RESERVED_15[3];
-  __IO uint8_t FRMNUML;                            /**< Frame Number Register Low, offset: 0xA0 */
-       uint8_t RESERVED_16[3];
-  __IO uint8_t FRMNUMH;                            /**< Frame Number Register High, offset: 0xA4 */
-       uint8_t RESERVED_17[3];
-  __IO uint8_t TOKEN;                              /**< Token register, offset: 0xA8 */
-       uint8_t RESERVED_18[3];
-  __IO uint8_t SOFTHLD;                            /**< SOF Threshold Register, offset: 0xAC */
-       uint8_t RESERVED_19[3];
-  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
-       uint8_t RESERVED_20[3];
-  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
-       uint8_t RESERVED_21[11];
-  struct {                                         /* offset: 0xC0, array step: 0x4 */
-    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
-         uint8_t RESERVED_0[3];
-  } ENDPOINT[16];
-  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
-       uint8_t RESERVED_22[3];
-  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
-       uint8_t RESERVED_23[3];
-  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
-       uint8_t RESERVED_24[3];
-  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control Register 0, offset: 0x10C */
-} USB_Type;
-
-/* ----------------------------------------------------------------------------
-   -- USB Register Masks
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup USB_Register_Masks USB Register Masks
- * @{
- */
-
-/* PERID Bit Fields */
-#define USB_PERID_ID_MASK                        0x3Fu
-#define USB_PERID_ID_SHIFT                       0
-#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
-/* IDCOMP Bit Fields */
-#define USB_IDCOMP_NID_MASK                      0x3Fu
-#define USB_IDCOMP_NID_SHIFT                     0
-#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
-/* REV Bit Fields */
-#define USB_REV_REV_MASK                         0xFFu
-#define USB_REV_REV_SHIFT                        0
-#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
-/* ADDINFO Bit Fields */
-#define USB_ADDINFO_IEHOST_MASK                  0x1u
-#define USB_ADDINFO_IEHOST_SHIFT                 0
-#define USB_ADDINFO_IRQNUM_MASK                  0xF8u
-#define USB_ADDINFO_IRQNUM_SHIFT                 3
-#define USB_ADDINFO_IRQNUM(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
-/* OTGISTAT Bit Fields */
-#define USB_OTGISTAT_AVBUSCHG_MASK               0x1u
-#define USB_OTGISTAT_AVBUSCHG_SHIFT              0
-#define USB_OTGISTAT_B_SESS_CHG_MASK             0x4u
-#define USB_OTGISTAT_B_SESS_CHG_SHIFT            2
-#define USB_OTGISTAT_SESSVLDCHG_MASK             0x8u
-#define USB_OTGISTAT_SESSVLDCHG_SHIFT            3
-#define USB_OTGISTAT_LINE_STATE_CHG_MASK         0x20u
-#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        5
-#define USB_OTGISTAT_ONEMSEC_MASK                0x40u
-#define USB_OTGISTAT_ONEMSEC_SHIFT               6
-#define USB_OTGISTAT_IDCHG_MASK                  0x80u
-#define USB_OTGISTAT_IDCHG_SHIFT                 7
-/* OTGICR Bit Fields */
-#define USB_OTGICR_AVBUSEN_MASK                  0x1u
-#define USB_OTGICR_AVBUSEN_SHIFT                 0
-#define USB_OTGICR_BSESSEN_MASK                  0x4u
-#define USB_OTGICR_BSESSEN_SHIFT                 2
-#define USB_OTGICR_SESSVLDEN_MASK                0x8u
-#define USB_OTGICR_SESSVLDEN_SHIFT               3
-#define USB_OTGICR_LINESTATEEN_MASK              0x20u
-#define USB_OTGICR_LINESTATEEN_SHIFT             5
-#define USB_OTGICR_ONEMSECEN_MASK                0x40u
-#define USB_OTGICR_ONEMSECEN_SHIFT               6
-#define USB_OTGICR_IDEN_MASK                     0x80u
-#define USB_OTGICR_IDEN_SHIFT                    7
-/* OTGSTAT Bit Fields */
-#define USB_OTGSTAT_AVBUSVLD_MASK                0x1u
-#define USB_OTGSTAT_AVBUSVLD_SHIFT               0
-#define USB_OTGSTAT_BSESSEND_MASK                0x4u
-#define USB_OTGSTAT_BSESSEND_SHIFT               2
-#define USB_OTGSTAT_SESS_VLD_MASK                0x8u
-#define USB_OTGSTAT_SESS_VLD_SHIFT               3
-#define USB_OTGSTAT_LINESTATESTABLE_MASK         0x20u
-#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        5
-#define USB_OTGSTAT_ONEMSECEN_MASK               0x40u
-#define USB_OTGSTAT_ONEMSECEN_SHIFT              6
-#define USB_OTGSTAT_ID_MASK                      0x80u
-#define USB_OTGSTAT_ID_SHIFT                     7
-/* OTGCTL Bit Fields */
-#define USB_OTGCTL_OTGEN_MASK                    0x4u
-#define USB_OTGCTL_OTGEN_SHIFT                   2
-#define USB_OTGCTL_DMLOW_MASK                    0x10u
-#define USB_OTGCTL_DMLOW_SHIFT                   4
-#define USB_OTGCTL_DPLOW_MASK                    0x20u
-#define USB_OTGCTL_DPLOW_SHIFT                   5
-#define USB_OTGCTL_DPHIGH_MASK                   0x80u
-#define USB_OTGCTL_DPHIGH_SHIFT                  7
-/* ISTAT Bit Fields */
-#define USB_ISTAT_USBRST_MASK                    0x1u
-#define USB_ISTAT_USBRST_SHIFT                   0
-#define USB_ISTAT_ERROR_MASK                     0x2u
-#define USB_ISTAT_ERROR_SHIFT                    1
-#define USB_ISTAT_SOFTOK_MASK                    0x4u
-#define USB_ISTAT_SOFTOK_SHIFT                   2
-#define USB_ISTAT_TOKDNE_MASK                    0x8u
-#define USB_ISTAT_TOKDNE_SHIFT                   3
-#define USB_ISTAT_SLEEP_MASK                     0x10u
-#define USB_ISTAT_SLEEP_SHIFT                    4
-#define USB_ISTAT_RESUME_MASK                    0x20u
-#define USB_ISTAT_RESUME_SHIFT                   5
-#define USB_ISTAT_ATTACH_MASK                    0x40u
-#define USB_ISTAT_ATTACH_SHIFT                   6
-#define USB_ISTAT_STALL_MASK                     0x80u
-#define USB_ISTAT_STALL_SHIFT                    7
-/* INTEN Bit Fields */
-#define USB_INTEN_USBRSTEN_MASK                  0x1u
-#define USB_INTEN_USBRSTEN_SHIFT                 0
-#define USB_INTEN_ERROREN_MASK                   0x2u
-#define USB_INTEN_ERROREN_SHIFT                  1
-#define USB_INTEN_SOFTOKEN_MASK                  0x4u
-#define USB_INTEN_SOFTOKEN_SHIFT                 2
-#define USB_INTEN_TOKDNEEN_MASK                  0x8u
-#define USB_INTEN_TOKDNEEN_SHIFT                 3
-#define USB_INTEN_SLEEPEN_MASK                   0x10u
-#define USB_INTEN_SLEEPEN_SHIFT                  4
-#define USB_INTEN_RESUMEEN_MASK                  0x20u
-#define USB_INTEN_RESUMEEN_SHIFT                 5
-#define USB_INTEN_ATTACHEN_MASK                  0x40u
-#define USB_INTEN_ATTACHEN_SHIFT                 6
-#define USB_INTEN_STALLEN_MASK                   0x80u
-#define USB_INTEN_STALLEN_SHIFT                  7
-/* ERRSTAT Bit Fields */
-#define USB_ERRSTAT_PIDERR_MASK                  0x1u
-#define USB_ERRSTAT_PIDERR_SHIFT                 0
-#define USB_ERRSTAT_CRC5EOF_MASK                 0x2u
-#define USB_ERRSTAT_CRC5EOF_SHIFT                1
-#define USB_ERRSTAT_CRC16_MASK                   0x4u
-#define USB_ERRSTAT_CRC16_SHIFT                  2
-#define USB_ERRSTAT_DFN8_MASK                    0x8u
-#define USB_ERRSTAT_DFN8_SHIFT                   3
-#define USB_ERRSTAT_BTOERR_MASK                  0x10u
-#define USB_ERRSTAT_BTOERR_SHIFT                 4
-#define USB_ERRSTAT_DMAERR_MASK                  0x20u
-#define USB_ERRSTAT_DMAERR_SHIFT                 5
-#define USB_ERRSTAT_BTSERR_MASK                  0x80u
-#define USB_ERRSTAT_BTSERR_SHIFT                 7
-/* ERREN Bit Fields */
-#define USB_ERREN_PIDERREN_MASK                  0x1u
-#define USB_ERREN_PIDERREN_SHIFT                 0
-#define USB_ERREN_CRC5EOFEN_MASK                 0x2u
-#define USB_ERREN_CRC5EOFEN_SHIFT                1
-#define USB_ERREN_CRC16EN_MASK                   0x4u
-#define USB_ERREN_CRC16EN_SHIFT                  2
-#define USB_ERREN_DFN8EN_MASK                    0x8u
-#define USB_ERREN_DFN8EN_SHIFT                   3
-#define USB_ERREN_BTOERREN_MASK                  0x10u
-#define USB_ERREN_BTOERREN_SHIFT                 4
-#define USB_ERREN_DMAERREN_MASK                  0x20u
-#define USB_ERREN_DMAERREN_SHIFT                 5
-#define USB_ERREN_BTSERREN_MASK                  0x80u
-#define USB_ERREN_BTSERREN_SHIFT                 7
-/* STAT Bit Fields */
-#define USB_STAT_ODD_MASK                        0x4u
-#define USB_STAT_ODD_SHIFT                       2
-#define USB_STAT_TX_MASK                         0x8u
-#define USB_STAT_TX_SHIFT                        3
-#define USB_STAT_ENDP_MASK                       0xF0u
-#define USB_STAT_ENDP_SHIFT                      4
-#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
-/* CTL Bit Fields */
-#define USB_CTL_USBENSOFEN_MASK                  0x1u
-#define USB_CTL_USBENSOFEN_SHIFT                 0
-#define USB_CTL_ODDRST_MASK                      0x2u
-#define USB_CTL_ODDRST_SHIFT                     1
-#define USB_CTL_RESUME_MASK                      0x4u
-#define USB_CTL_RESUME_SHIFT                     2
-#define USB_CTL_HOSTMODEEN_MASK                  0x8u
-#define USB_CTL_HOSTMODEEN_SHIFT                 3
-#define USB_CTL_RESET_MASK                       0x10u
-#define USB_CTL_RESET_SHIFT                      4
-#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          0x20u
-#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         5
-#define USB_CTL_SE0_MASK                         0x40u
-#define USB_CTL_SE0_SHIFT                        6
-#define USB_CTL_JSTATE_MASK                      0x80u
-#define USB_CTL_JSTATE_SHIFT                     7
-/* ADDR Bit Fields */
-#define USB_ADDR_ADDR_MASK                       0x7Fu
-#define USB_ADDR_ADDR_SHIFT                      0
-#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
-#define USB_ADDR_LSEN_MASK                       0x80u
-#define USB_ADDR_LSEN_SHIFT                      7
-/* BDTPAGE1 Bit Fields */
-#define USB_BDTPAGE1_BDTBA_MASK                  0xFEu
-#define USB_BDTPAGE1_BDTBA_SHIFT                 1
-#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
-/* FRMNUML Bit Fields */
-#define USB_FRMNUML_FRM_MASK                     0xFFu
-#define USB_FRMNUML_FRM_SHIFT                    0
-#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
-/* FRMNUMH Bit Fields */
-#define USB_FRMNUMH_FRM_MASK                     0x7u
-#define USB_FRMNUMH_FRM_SHIFT                    0
-#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
-/* TOKEN Bit Fields */
-#define USB_TOKEN_TOKENENDPT_MASK                0xFu
-#define USB_TOKEN_TOKENENDPT_SHIFT               0
-#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
-#define USB_TOKEN_TOKENPID_MASK                  0xF0u
-#define USB_TOKEN_TOKENPID_SHIFT                 4
-#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
-/* SOFTHLD Bit Fields */
-#define USB_SOFTHLD_CNT_MASK                     0xFFu
-#define USB_SOFTHLD_CNT_SHIFT                    0
-#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
-/* BDTPAGE2 Bit Fields */
-#define USB_BDTPAGE2_BDTBA_MASK                  0xFFu
-#define USB_BDTPAGE2_BDTBA_SHIFT                 0
-#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
-/* BDTPAGE3 Bit Fields */
-#define USB_BDTPAGE3_BDTBA_MASK                  0xFFu
-#define USB_BDTPAGE3_BDTBA_SHIFT                 0
-#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
-/* ENDPT Bit Fields */
-#define USB_ENDPT_EPHSHK_MASK                    0x1u
-#define USB_ENDPT_EPHSHK_SHIFT                   0
-#define USB_ENDPT_EPSTALL_MASK                   0x2u
-#define USB_ENDPT_EPSTALL_SHIFT                  1
-#define USB_ENDPT_EPTXEN_MASK                    0x4u
-#define USB_ENDPT_EPTXEN_SHIFT                   2
-#define USB_ENDPT_EPRXEN_MASK                    0x8u
-#define USB_ENDPT_EPRXEN_SHIFT                   3
-#define USB_ENDPT_EPCTLDIS_MASK                  0x10u
-#define USB_ENDPT_EPCTLDIS_SHIFT                 4
-#define USB_ENDPT_RETRYDIS_MASK                  0x40u
-#define USB_ENDPT_RETRYDIS_SHIFT                 6
-#define USB_ENDPT_HOSTWOHUB_MASK                 0x80u
-#define USB_ENDPT_HOSTWOHUB_SHIFT                7
-/* USBCTRL Bit Fields */
-#define USB_USBCTRL_PDE_MASK                     0x40u
-#define USB_USBCTRL_PDE_SHIFT                    6
-#define USB_USBCTRL_SUSP_MASK                    0x80u
-#define USB_USBCTRL_SUSP_SHIFT                   7
-/* OBSERVE Bit Fields */
-#define USB_OBSERVE_DMPD_MASK                    0x10u
-#define USB_OBSERVE_DMPD_SHIFT                   4
-#define USB_OBSERVE_DPPD_MASK                    0x40u
-#define USB_OBSERVE_DPPD_SHIFT                   6
-#define USB_OBSERVE_DPPU_MASK                    0x80u
-#define USB_OBSERVE_DPPU_SHIFT                   7
-/* CONTROL Bit Fields */
-#define USB_CONTROL_DPPULLUPNONOTG_MASK          0x10u
-#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         4
-/* USBTRC0 Bit Fields */
-#define USB_USBTRC0_USB_RESUME_INT_MASK          0x1u
-#define USB_USBTRC0_USB_RESUME_INT_SHIFT         0
-#define USB_USBTRC0_SYNC_DET_MASK                0x2u
-#define USB_USBTRC0_SYNC_DET_SHIFT               1
-#define USB_USBTRC0_USBRESMEN_MASK               0x20u
-#define USB_USBTRC0_USBRESMEN_SHIFT              5
-#define USB_USBTRC0_USBRESET_MASK                0x80u
-#define USB_USBTRC0_USBRESET_SHIFT               7
-
-/**
- * @}
- */ /* end of group USB_Register_Masks */
-
-
-/* USB - Peripheral instance base addresses */
-/** Peripheral USB0 base address */
-#define USB0_BASE                                (0x40072000u)
-/** Peripheral USB0 base pointer */
-#define USB0                                     ((USB_Type *)USB0_BASE)
-/** Array initializer of USB peripheral base pointers */
-#define USB_BASES                                { USB0 }
-
-/**
- * @}
- */ /* end of group USB_Peripheral_Access_Layer */
-
-
-/*
-** End of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
-  #pragma pop
-#elif defined(__CWCC__)
-  #pragma pop
-#elif defined(__GNUC__)
-  /* leave anonymous unions enabled */
-#elif defined(__IAR_SYSTEMS_ICC__)
-  #pragma language=default
-#else
-  #error Not supported compiler type
-#endif
-
-/**
- * @}
- */ /* end of group Peripheral_access_layer */
-
-
-/* ----------------------------------------------------------------------------
-   -- Backward Compatibility
-   ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
- * @{
- */
-
-/* No backward compatibility issues. */
-
-/**
- * @}
- */ /* end of group Backward_Compatibility_Symbols */
-
-
-#endif  /* #if !defined(MKL25Z4_H_) */
-
-/* MKL25Z4.h, eof. */

--- a/vendor/Freescale/KL25Z/cmsis/cmsis.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,13 +0,0 @@
-/* mbed Microcontroller Library - CMSIS
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * A generic CMSIS include header, pulling in LPC11U24 specifics
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "MKL25Z4.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/vendor/Freescale/KL25Z/cmsis/cmsis_nvic.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
- * Copyright (c) 2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-#include "cmsis_nvic.h"
-
-#define NVIC_NUM_VECTORS (16 + 32)            // CORE + MCU Peripherals
-#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFF000)  // Vectors positioned at start of RAM
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-    static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
-		int i;
-    
-    // Copy and switch to dynamic vectors if first time called
-    if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
-        uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
-        for (i=0; i<NVIC_NUM_VECTORS; i++) {
-            vectors[i] = old_vectors[i];
-        }
-        SCB->VTOR = (uint32_t)vectors;
-    }
-    
-    vectors[IRQn + 16] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t *vectors = (uint32_t*)SCB->VTOR;
-    return vectors[IRQn + 16];
-}

--- a/vendor/Freescale/KL25Z/cmsis/cmsis_nvic.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,23 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/Freescale/KL25Z/cmsis/core_cm0.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,279 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.c
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Source File
- * @version  V2.00
- * @date     10. September 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-
-/* ##########################  Core Instruction Access  ######################### */
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __CLREX(void)
-{
-  clrex
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_CONTROL(void)
-{
-  mrs r0, control
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_CONTROL(uint32_t control)
-{
-  msr control, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_IPSR(void)
-{
-  mrs r0, ipsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_APSR(void)
-{
-  mrs r0, apsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_xPSR(void)
-{
-  mrs r0, xpsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_PSP(void)
-{
-  mrs r0, psp
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
-  msr psp, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_MSP(void)
-{
-  mrs r0, msp
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
-  msr msp, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_PRIMASK(void)
-{
-  mrs r0, primask
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
-  msr primask, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
- 
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif

--- a/vendor/Freescale/KL25Z/cmsis/core_cm0plus.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,778 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0plus.h
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V3.02
- * @date     05. November 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex-M0+
-  @{
- */
-
-/*  CMSIS CM0P definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
-#define __CM0PLUS_CMSIS_VERSION_SUB  (0x01)                                /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
-                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0PLUS_REV
-    #define __CM0PLUS_REV             0x0000
-    #warning "__CM0PLUS_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-#if (__VTOR_PRESENT == 1)
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-#else
-       uint32_t RESERVED0;
-#endif
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if (__VTOR_PRESENT == 1)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0+ Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
-
-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

--- a/vendor/Freescale/KL25Z/cmsis/core_cmFunc.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,616 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V3.02
- * @date     24. May 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */

--- a/vendor/Freescale/KL25Z/cmsis/core_cmInstr.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,643 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V3.03
- * @date     29. August 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-#define __ISB()                           __isb(0xF)
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()                           __dsb(0xF)
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB()                           __dmb(0xF)
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __RBIT                            __rbit
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-
-  __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
-  return(op1);
-}
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint8_t result;
-
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint16_t result;
-
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
-  uint8_t result;
-
-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

--- a/vendor/Freescale/KL25Z/cmsis/system_MKL25Z4.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,263 +0,0 @@
-/*
-** ###################################################################
-**     Processor:           MKL25Z128VLK4
-**     Compilers:           ARM Compiler
-**                          Freescale C/C++ for Embedded ARM
-**                          GNU C Compiler
-**                          IAR ANSI C/C++ Compiler for ARM
-**
-**     Reference manual:    KL25RM, Rev.1, Jun 2012
-**     Version:             rev. 1.1, 2012-06-21
-**
-**     Abstract:
-**         Provides a system configuration function and a global variable that
-**         contains the system frequency. It configures the device and initializes
-**         the oscillator (PLL) that is part of the microcontroller device.
-**
-**     Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-**
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
-**
-**     Revisions:
-**     - rev. 1.0 (2012-06-13)
-**         Initial version.
-**     - rev. 1.1 (2012-06-21)
-**         Update according to reference manual rev. 1.
-**
-** ###################################################################
-*/
-
-/**
- * @file MKL25Z4
- * @version 1.1
- * @date 2012-06-21
- * @brief Device specific configuration file for MKL25Z4 (implementation file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#include <stdint.h>
-#include "MKL25Z4.h"
-
-#define DISABLE_WDOG    1
-
-#define CLOCK_SETUP     1
-/* Predefined clock setups
-   0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
-         Reference clock source for MCG module is the slow internal clock source 32.768kHz
-         Core clock = 41.94MHz, BusClock = 13.98MHz
-   1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
-         Reference clock source for MCG module is an external crystal 8MHz
-         Core clock = 48MHz, BusClock = 24MHz
-   2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
-         Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
-         Core clock = 8MHz, BusClock = 8MHz
-*/
-
-/*----------------------------------------------------------------------------
-  Define clock source values
- *----------------------------------------------------------------------------*/
-#if (CLOCK_SETUP == 0)
-    #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
-    #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
-    #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
-    #define DEFAULT_SYSTEM_CLOCK            41943040u /* Default System clock value */
-#elif (CLOCK_SETUP == 1)
-    #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
-    #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
-    #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
-    #define DEFAULT_SYSTEM_CLOCK            48000000u /* Default System clock value */
-#elif (CLOCK_SETUP == 2)
-    #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
-    #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
-    #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
-    #define DEFAULT_SYSTEM_CLOCK            8000000u /* Default System clock value */
-#endif /* (CLOCK_SETUP == 2) */
-
-
-/* ----------------------------------------------------------------------------
-   -- Core clock
-   ---------------------------------------------------------------------------- */
-
-uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
-
-/* ----------------------------------------------------------------------------
-   -- SystemInit()
-   ---------------------------------------------------------------------------- */
-
-void SystemInit (void) {
-#if (DISABLE_WDOG)
-  /* Disable the WDOG module */
-  /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
-  SIM->COPC = (uint32_t)0x00u;
-#endif /* (DISABLE_WDOG) */
-#if (CLOCK_SETUP == 0)
-  /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
-  SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
-  /* Switch to FEI Mode */
-  /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
-  MCG->C1 = (uint8_t)0x06U;
-  /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
-  MCG->C2 = (uint8_t)0x00U;
-  /* MCG->C4: DMX32=0,DRST_DRS=1 */
-  MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
-  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
-  OSC0->CR = (uint8_t)0x80U;
-  /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
-  MCG->C5 = (uint8_t)0x00U;
-  /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
-  MCG->C6 = (uint8_t)0x00U;
-  while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
-  }
-  while((MCG->S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
-  }
-#elif (CLOCK_SETUP == 1)
-  /* SIM->SCGC5: PORTA=1 */
-  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
-  /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
-  SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
-  /* PORTA->PCR18: ISF=0,MUX=0 */
-  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
-  /* PORTA->PCR19: ISF=0,MUX=0 */
-  PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
-  /* Switch to FBE Mode */
-  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
-  OSC0->CR = (uint8_t)0x89U;
-  /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
-  MCG->C2 = (uint8_t)0x24U;
-  /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
-  MCG->C1 = (uint8_t)0x9AU;
-  /* MCG->C4: DMX32=0,DRST_DRS=0 */
-  MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
-  /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
-  MCG->C5 = (uint8_t)0x01U;
-  /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
-  MCG->C6 = (uint8_t)0x00U;
-  while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
-  }
-  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
-  }
-  /* Switch to PBE Mode */
-  /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
-  MCG->C6 = (uint8_t)0x40U;
-  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
-  }
-  while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
-  }
-  /* Switch to PEE Mode */
-  /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
-  MCG->C1 = (uint8_t)0x1AU;
-  while((MCG->S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
-  }
-#elif (CLOCK_SETUP == 2)
-  /* SIM->SCGC5: PORTA=1 */
-  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
-  /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
-  SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
-  /* PORTA->PCR18: ISF=0,MUX=0 */
-  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
-  /* PORTA->PCR19: ISF=0,MUX=0 */
-  PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
-  /* Switch to FBE Mode */
-  /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
-  OSC0->CR = (uint8_t)0x89U;
-  /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
-  MCG->C2 = (uint8_t)0x24U;
-  /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
-  MCG->C1 = (uint8_t)0x9AU;
-  /* MCG->C4: DMX32=0,DRST_DRS=0 */
-  MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
-  /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
-  MCG->C5 = (uint8_t)0x00U;
-  /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
-  MCG->C6 = (uint8_t)0x00U;
-  while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
-  }
-  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
-  }
-  /* Switch to BLPE Mode */
-  /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
-  MCG->C2 = (uint8_t)0x26U;
-  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
-  }
-#endif /* (CLOCK_SETUP == 2) */
-}
-
-/* ----------------------------------------------------------------------------
-   -- SystemCoreClockUpdate()
-   ---------------------------------------------------------------------------- */
-
-void SystemCoreClockUpdate (void) {
-  uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
-  uint8_t Divider;
-
-  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
-    /* Output of FLL or PLL is selected */
-    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
-      /* FLL is selected */
-      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
-        /* External reference clock is selected */
-        MCGOUTClock = CPU_XTAL_CLK_HZ;                                       /* System oscillator drives MCG clock */
-        Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
-        MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
-        if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
-          MCGOUTClock /= 32u;                                                  /* If high range is enabled, additional 32 divider is active */
-        } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
-      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
-        MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
-      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
-      /* Select correct multiplier to calculate the MCG output clock  */
-      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
-        case 0x0u:
-          MCGOUTClock *= 640u;
-          break;
-        case 0x20u:
-          MCGOUTClock *= 1280u;
-          break;
-        case 0x40u:
-          MCGOUTClock *= 1920u;
-          break;
-        case 0x60u:
-          MCGOUTClock *= 2560u;
-          break;
-        case 0x80u:
-          MCGOUTClock *= 732u;
-          break;
-        case 0xA0u:
-          MCGOUTClock *= 1464u;
-          break;
-        case 0xC0u:
-          MCGOUTClock *= 2197u;
-          break;
-        case 0xE0u:
-          MCGOUTClock *= 2929u;
-          break;
-        default:
-          break;
-      }
-    } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
-      /* PLL is selected */
-      Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
-      MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider);                     /* Calculate the PLL reference clock */
-      Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
-      MCGOUTClock *= Divider;                       /* Calculate the MCG output clock */
-    } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
-  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
-    /* Internal reference clock is selected */
-    if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
-      MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
-    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
-      MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));  /* Fast internal reference clock selected */
-    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
-  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
-    /* External reference clock is selected */
-    MCGOUTClock = CPU_XTAL_CLK_HZ;                                           /* System oscillator drives MCG clock */
-  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
-    /* Reserved value */
-    return;
-  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
-  SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
-}

--- a/vendor/Freescale/KL25Z/cmsis/system_MKL25Z4.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,84 +0,0 @@
-/*
-** ###################################################################
-**     Processor:           MKL25Z128VLK4
-**     Compilers:           ARM Compiler
-**                          Freescale C/C++ for Embedded ARM
-**                          GNU C Compiler
-**                          IAR ANSI C/C++ Compiler for ARM
-**
-**     Reference manual:    KL25RM, Rev.1, Jun 2012
-**     Version:             rev. 1.1, 2012-06-21
-**
-**     Abstract:
-**         Provides a system configuration function and a global variable that
-**         contains the system frequency. It configures the device and initializes
-**         the oscillator (PLL) that is part of the microcontroller device.
-**
-**     Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-**
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
-**
-**     Revisions:
-**     - rev. 1.0 (2012-06-13)
-**         Initial version.
-**     - rev. 1.1 (2012-06-21)
-**         Update according to reference manual rev. 1.
-**
-** ###################################################################
-*/
-
-/**
- * @file MKL25Z4
- * @version 1.1
- * @date 2012-06-21
- * @brief Device specific configuration file for MKL25Z4 (header file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#ifndef SYSTEM_MKL25Z4_H_
-#define SYSTEM_MKL25Z4_H_                        /**< Symbol preventing repeated inclusion */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-/**
- * @brief System clock frequency (core clock)
- *
- * The system clock frequency supplied to the SysTick timer and the processor
- * core clock. This variable can be used by the user application to setup the
- * SysTick timer or configure other parameters. It may also be used by debugger to
- * query the frequency of the debug timer or configure the trace clock speed
- * SystemCoreClock is initialized with a correct predefined value.
- */
-extern uint32_t SystemCoreClock;
-
-/**
- * @brief Setup the microcontroller system.
- *
- * Typically this function configures the oscillator (PLL) that is part of the
- * microcontroller device. For systems with variable clock speed it also updates
- * the variable SystemCoreClock. SystemInit is called from startup_device file.
- */
-void SystemInit (void);
-
-/**
- * @brief Updates the SystemCoreClock variable.
- *
- * It must be called whenever the core clock is changed during program
- * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
- * the current core clock.
- */
-void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* #if !defined(SYSTEM_MKL25Z4_H_) */

--- a/vendor/Freescale/KL25Z/cmsis/uARM/MKL25Z4.sct	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,14 +0,0 @@
-
-LR_IROM1 0x00000000 0x20000  {    ; load region size_region (32k)
-  ER_IROM1 0x00000000 0x20000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
-  ; 0x4000 - 0xC0 = 0x3F40
-  RW_IRAM1 0x1FFFF0C0 0x3F40 {
-   .ANY (+RW +ZI)
-  }
-}
-

--- a/vendor/Freescale/KL25Z/cmsis/uARM/startup_MKL25Z4.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,353 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_MKL25Z4.s
-; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
-; *           MKL25Z4
-; * @version: 1.1
-; * @date:    2012-6-21
-; *
-; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-;*
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; *****************************************************************************/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __initial_sp
-
-Stack_Mem       SPACE   Stack_Size
-__initial_sp        EQU     0x20003000  ; Top of RAM
-
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp  ; Top of Stack
-                DCD     Reset_Handler  ; Reset Handler
-                DCD     NMI_Handler  ; NMI Handler
-                DCD     HardFault_Handler  ; Hard Fault Handler
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     SVC_Handler  ; SVCall Handler
-                DCD     0  ; Reserved
-                DCD     0  ; Reserved
-                DCD     PendSV_Handler  ; PendSV Handler
-                DCD     SysTick_Handler  ; SysTick Handler
-
-                ; External Interrupts
-                DCD     DMA0_IRQHandler  ; DMA channel 0 transfer complete interrupt
-                DCD     DMA1_IRQHandler  ; DMA channel 1 transfer complete interrupt
-                DCD     DMA2_IRQHandler  ; DMA channel 2 transfer complete interrupt
-                DCD     DMA3_IRQHandler  ; DMA channel 3 transfer complete interrupt
-                DCD     Reserved20_IRQHandler  ; Reserved interrupt 20
-                DCD     FTFA_IRQHandler  ; FTFA interrupt
-                DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
-                DCD     LLW_IRQHandler  ; Low Leakage Wakeup
-                DCD     I2C0_IRQHandler  ; I2C0 interrupt
-                DCD     I2C1_IRQHandler  ; I2C0 interrupt 25
-                DCD     SPI0_IRQHandler  ; SPI0 interrupt
-                DCD     SPI1_IRQHandler  ; SPI1 interrupt
-                DCD     UART0_IRQHandler  ; UART0 status/error interrupt
-                DCD     UART1_IRQHandler  ; UART1 status/error interrupt
-                DCD     UART2_IRQHandler  ; UART2 status/error interrupt
-                DCD     ADC0_IRQHandler  ; ADC0 interrupt
-                DCD     CMP0_IRQHandler  ; CMP0 interrupt
-                DCD     TPM0_IRQHandler  ; TPM0 fault, overflow and channels interrupt
-                DCD     TPM1_IRQHandler  ; TPM1 fault, overflow and channels interrupt
-                DCD     TPM2_IRQHandler  ; TPM2 fault, overflow and channels interrupt
-                DCD     RTC_IRQHandler  ; RTC interrupt
-                DCD     RTC_Seconds_IRQHandler  ; RTC seconds interrupt
-                DCD     PIT_IRQHandler  ; PIT timer interrupt
-                DCD     Reserved39_IRQHandler  ; Reserved interrupt 39
-                DCD     USB0_IRQHandler  ; USB0 interrupt
-                DCD     DAC0_IRQHandler  ; DAC interrupt
-                DCD     TSI0_IRQHandler  ; TSI0 interrupt
-                DCD     MCG_IRQHandler  ; MCG interrupt
-                DCD     LPTimer_IRQHandler  ; LPTimer interrupt
-                DCD     Reserved45_IRQHandler  ; Reserved interrupt 45
-                DCD     PORTA_IRQHandler  ; Port A interrupt
-                DCD     PORTD_IRQHandler  ; Port D interrupt
-__Vectors_End
-
-__Vectors_Size 	EQU     __Vectors_End - __Vectors
-
-; <h> Flash Configuration
-;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
-;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
-;   <h> Backdoor Comparison Key
-;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
-;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
-;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
-;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
-;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
-;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
-;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
-;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
-BackDoorK0      EQU     0xFF
-BackDoorK1      EQU     0xFF
-BackDoorK2      EQU     0xFF
-BackDoorK3      EQU     0xFF
-BackDoorK4      EQU     0xFF
-BackDoorK5      EQU     0xFF
-BackDoorK6      EQU     0xFF
-BackDoorK7      EQU     0xFF
-;   </h>
-;   <h> Program flash protection bytes (FPROT)
-;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
-;     <i> Each bit protects a 1/32 region of the program flash memory.
-;     <h> FPROT0
-;       <i> Program flash protection bytes
-;       <i> 1/32 - 8/32 region
-;       <o.0>   FPROT0.0
-;       <o.1>   FPROT0.1
-;       <o.2>   FPROT0.2
-;       <o.3>   FPROT0.3
-;       <o.4>   FPROT0.4
-;       <o.5>   FPROT0.5
-;       <o.6>   FPROT0.6
-;       <o.7>   FPROT0.7
-nFPROT0         EQU     0x00
-FPROT0          EQU     nFPROT0:EOR:0xFF
-;     </h>
-;     <h> FPROT1
-;       <i> Program Flash Region Protect Register 1
-;       <i> 9/32 - 16/32 region
-;       <o.0>   FPROT1.0
-;       <o.1>   FPROT1.1
-;       <o.2>   FPROT1.2
-;       <o.3>   FPROT1.3
-;       <o.4>   FPROT1.4
-;       <o.5>   FPROT1.5
-;       <o.6>   FPROT1.6
-;       <o.7>   FPROT1.7
-nFPROT1         EQU     0x00
-FPROT1          EQU     nFPROT1:EOR:0xFF
-;     </h>
-;     <h> FPROT2
-;       <i> Program Flash Region Protect Register 2
-;       <i> 17/32 - 24/32 region
-;       <o.0>   FPROT2.0
-;       <o.1>   FPROT2.1
-;       <o.2>   FPROT2.2
-;       <o.3>   FPROT2.3
-;       <o.4>   FPROT2.4
-;       <o.5>   FPROT2.5
-;       <o.6>   FPROT2.6
-;       <o.7>   FPROT2.7
-nFPROT2         EQU     0x00
-FPROT2          EQU     nFPROT2:EOR:0xFF
-;     </h>
-;     <h> FPROT3
-;       <i> Program Flash Region Protect Register 3
-;       <i> 25/32 - 32/32 region
-;       <o.0>   FPROT3.0
-;       <o.1>   FPROT3.1
-;       <o.2>   FPROT3.2
-;       <o.3>   FPROT3.3
-;       <o.4>   FPROT3.4
-;       <o.5>   FPROT3.5
-;       <o.6>   FPROT3.6
-;       <o.7>   FPROT3.7
-nFPROT3         EQU     0x00
-FPROT3          EQU     nFPROT3:EOR:0xFF
-;     </h>
-;   </h>
-;   </h>
-;   <h> Flash nonvolatile option byte (FOPT)
-;     <i> Allows the user to customize the operation of the MCU at boot time.
-;     <o.0>  LPBOOT0
-;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
-;       <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
-;     <o.4>  LPBOOT1
-;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
-;       <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
-;     <o.2>  NMI_DIS
-;       <0=> NMI interrupts are always blocked
-;       <1=> NMI pin/interrupts reset default to enabled
-;     <o.3>  RESET_PIN_CFG
-;       <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
-;       <1=> RESET pin is dedicated
-;     <o.3>  FAST_INIT
-;       <0=> Slower initialization
-;       <1=> Fast Initialization
-FOPT            EQU     0xFF
-;   </h>
-;   <h> Flash security byte (FSEC)
-;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
-;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
-;     <o.0..1> SEC
-;       <2=> MCU security status is unsecure
-;       <3=> MCU security status is secure
-;         <i> Flash Security
-;         <i> This bits define the security state of the MCU.
-;     <o.2..3> FSLACC
-;       <2=> Freescale factory access denied
-;       <3=> Freescale factory access granted
-;         <i> Freescale Failure Analysis Access Code
-;         <i> This bits define the security state of the MCU.
-;     <o.4..5> MEEN
-;       <2=> Mass erase is disabled
-;       <3=> Mass erase is enabled
-;         <i> Mass Erase Enable Bits
-;         <i> Enables and disables mass erase capability of the FTFL module
-;     <o.6..7> KEYEN
-;       <2=> Backdoor key access enabled
-;       <3=> Backdoor key access disabled
-;         <i> Backdoor key Security Enable
-;         <i> These bits enable and disable backdoor key access to the FTFL module.
-FSEC            EQU     0xFE
-;   </h>
-
-                IF      :LNOT::DEF:RAM_TARGET
-                AREA    |.ARM.__at_0x400|, CODE, READONLY
-                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
-                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
-                DCB     FPROT0,     FPROT1,     FPROT2,     FPROT3
-                DCB     FSEC,       FOPT,       0xFF,     0xFF
-                ENDIF
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-                EXPORT  DMA0_IRQHandler     [WEAK]
-                EXPORT  DMA1_IRQHandler     [WEAK]
-                EXPORT  DMA2_IRQHandler     [WEAK]
-                EXPORT  DMA3_IRQHandler     [WEAK]
-                EXPORT  Reserved20_IRQHandler     [WEAK]
-                EXPORT  FTFA_IRQHandler     [WEAK]
-                EXPORT  LVD_LVW_IRQHandler     [WEAK]
-                EXPORT  LLW_IRQHandler     [WEAK]
-                EXPORT  I2C0_IRQHandler     [WEAK]
-                EXPORT  I2C1_IRQHandler     [WEAK]
-                EXPORT  SPI0_IRQHandler     [WEAK]
-                EXPORT  SPI1_IRQHandler     [WEAK]
-                EXPORT  UART0_IRQHandler     [WEAK]
-                EXPORT  UART1_IRQHandler     [WEAK]
-                EXPORT  UART2_IRQHandler     [WEAK]
-                EXPORT  ADC0_IRQHandler     [WEAK]
-                EXPORT  CMP0_IRQHandler     [WEAK]
-                EXPORT  TPM0_IRQHandler     [WEAK]
-                EXPORT  TPM1_IRQHandler     [WEAK]
-                EXPORT  TPM2_IRQHandler     [WEAK]
-                EXPORT  RTC_IRQHandler     [WEAK]
-                EXPORT  RTC_Seconds_IRQHandler     [WEAK]
-                EXPORT  PIT_IRQHandler     [WEAK]
-                EXPORT  Reserved39_IRQHandler     [WEAK]
-                EXPORT  USB0_IRQHandler     [WEAK]
-                EXPORT  DAC0_IRQHandler     [WEAK]
-                EXPORT  TSI0_IRQHandler     [WEAK]
-                EXPORT  MCG_IRQHandler     [WEAK]
-                EXPORT  LPTimer_IRQHandler     [WEAK]
-                EXPORT  Reserved45_IRQHandler     [WEAK]
-                EXPORT  PORTA_IRQHandler     [WEAK]
-                EXPORT  PORTD_IRQHandler     [WEAK]
-                EXPORT  DefaultISR                      [WEAK]
-
-DMA0_IRQHandler
-DMA1_IRQHandler
-DMA2_IRQHandler
-DMA3_IRQHandler
-Reserved20_IRQHandler
-FTFA_IRQHandler
-LVD_LVW_IRQHandler
-LLW_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-SPI0_IRQHandler
-SPI1_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-ADC0_IRQHandler
-CMP0_IRQHandler
-TPM0_IRQHandler
-TPM1_IRQHandler
-TPM2_IRQHandler
-RTC_IRQHandler
-RTC_Seconds_IRQHandler
-PIT_IRQHandler
-Reserved39_IRQHandler
-USB0_IRQHandler
-DAC0_IRQHandler
-TSI0_IRQHandler
-MCG_IRQHandler
-LPTimer_IRQHandler
-Reserved45_IRQHandler
-PORTA_IRQHandler
-PORTD_IRQHandler
-DefaultISR
-
-                B       .
-
-                ENDP
-
-
-                ALIGN
-                END

--- a/vendor/Freescale/KL25Z/cmsis/uARM/sys.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * Setup a fixed single stack/heap memory model, 
- *  between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/vendor/Freescale/KL25Z/hal/PeripheralNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,86 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    UART_0 = (int)UART0_BASE,
-    UART_1 = (int)UART1_BASE,
-    UART_2 = (int)UART2_BASE
-} UARTName;
-#define STDIO_UART_TX     USBTX
-#define STDIO_UART_RX     USBRX
-#define STDIO_UART        UART_0
-
-typedef enum {
-    I2C_0 = (int)I2C0_BASE,
-    I2C_1 = (int)I2C1_BASE,
-} I2CName;
-
-#define TPM_SHIFT   8
-typedef enum {
-    PWM_1  = (0 << TPM_SHIFT) | (0),  // TPM0 CH0
-    PWM_2  = (0 << TPM_SHIFT) | (1),  // TPM0 CH1
-    PWM_3  = (0 << TPM_SHIFT) | (2),  // TPM0 CH2
-    PWM_4  = (0 << TPM_SHIFT) | (3),  // TPM0 CH3
-    PWM_5  = (0 << TPM_SHIFT) | (4),  // TPM0 CH4
-    PWM_6  = (0 << TPM_SHIFT) | (5),  // TPM0 CH5
-
-    PWM_7  = (1 << TPM_SHIFT) | (0),  // TPM1 CH0
-    PWM_8  = (1 << TPM_SHIFT) | (1),  // TPM1 CH1
-
-    PWM_9  = (2 << TPM_SHIFT) | (0),  // TPM2 CH0
-    PWM_10 = (2 << TPM_SHIFT) | (1)   // TPM2 CH1
-} PWMName;
-
-typedef enum {
-    ADC0_SE0  =  0,
-    ADC0_SE3  =  3,
-    ADC0_SE4b =  4,
-    ADC0_SE5b =  5,
-    ADC0_SE6b =  6,
-    ADC0_SE7b =  7,
-    ADC0_SE8  =  8,
-    ADC0_SE9  =  9,
-    ADC0_SE11 = 11,
-    ADC0_SE12 = 12,
-    ADC0_SE13 = 13,
-    ADC0_SE14 = 14,
-    ADC0_SE15 = 15,
-    ADC0_SE23 = 23
-} ADCName;
-
-typedef enum {
-    DAC_0 = 0
-} DACName;
-
-
-typedef enum {
-    SPI_0 = (int)SPI0_BASE,
-    SPI_1 = (int)SPI1_BASE,
-} SPIName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/Freescale/KL25Z/hal/PinNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,247 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT  12
-
-typedef enum {
-    PTA0 = 0x0,
-    PTA1 = 0x4,
-    PTA2 = 0x8,
-    PTA3 = 0xc,
-    PTA4 = 0x10,
-    PTA5 = 0x14,
-    PTA6 = 0x18,
-    PTA7 = 0x1c,
-    PTA8 = 0x20,
-    PTA9 = 0x24,
-    PTA10 = 0x28,
-    PTA11 = 0x2c,
-    PTA12 = 0x30,
-    PTA13 = 0x34,
-    PTA14 = 0x38,
-    PTA15 = 0x3c,
-    PTA16 = 0x40,
-    PTA17 = 0x44,
-    PTA18 = 0x48,
-    PTA19 = 0x4c,
-    PTA20 = 0x50,
-    PTA21 = 0x54,
-    PTA22 = 0x58,
-    PTA23 = 0x5c,
-    PTA24 = 0x60,
-    PTA25 = 0x64,
-    PTA26 = 0x68,
-    PTA27 = 0x6c,
-    PTA28 = 0x70,
-    PTA29 = 0x74,
-    PTA30 = 0x78,
-    PTA31 = 0x7c,
-    PTB0 = 0x1000,
-    PTB1 = 0x1004,
-    PTB2 = 0x1008,
-    PTB3 = 0x100c,
-    PTB4 = 0x1010,
-    PTB5 = 0x1014,
-    PTB6 = 0x1018,
-    PTB7 = 0x101c,
-    PTB8 = 0x1020,
-    PTB9 = 0x1024,
-    PTB10 = 0x1028,
-    PTB11 = 0x102c,
-    PTB12 = 0x1030,
-    PTB13 = 0x1034,
-    PTB14 = 0x1038,
-    PTB15 = 0x103c,
-    PTB16 = 0x1040,
-    PTB17 = 0x1044,
-    PTB18 = 0x1048,
-    PTB19 = 0x104c,
-    PTB20 = 0x1050,
-    PTB21 = 0x1054,
-    PTB22 = 0x1058,
-    PTB23 = 0x105c,
-    PTB24 = 0x1060,
-    PTB25 = 0x1064,
-    PTB26 = 0x1068,
-    PTB27 = 0x106c,
-    PTB28 = 0x1070,
-    PTB29 = 0x1074,
-    PTB30 = 0x1078,
-    PTB31 = 0x107c,
-    PTC0 = 0x2000,
-    PTC1 = 0x2004,
-    PTC2 = 0x2008,
-    PTC3 = 0x200c,
-    PTC4 = 0x2010,
-    PTC5 = 0x2014,
-    PTC6 = 0x2018,
-    PTC7 = 0x201c,
-    PTC8 = 0x2020,
-    PTC9 = 0x2024,
-    PTC10 = 0x2028,
-    PTC11 = 0x202c,
-    PTC12 = 0x2030,
-    PTC13 = 0x2034,
-    PTC14 = 0x2038,
-    PTC15 = 0x203c,
-    PTC16 = 0x2040,
-    PTC17 = 0x2044,
-    PTC18 = 0x2048,
-    PTC19 = 0x204c,
-    PTC20 = 0x2050,
-    PTC21 = 0x2054,
-    PTC22 = 0x2058,
-    PTC23 = 0x205c,
-    PTC24 = 0x2060,
-    PTC25 = 0x2064,
-    PTC26 = 0x2068,
-    PTC27 = 0x206c,
-    PTC28 = 0x2070,
-    PTC29 = 0x2074,
-    PTC30 = 0x2078,
-    PTC31 = 0x207c,
-    PTD0 = 0x3000,
-    PTD1 = 0x3004,
-    PTD2 = 0x3008,
-    PTD3 = 0x300c,
-    PTD4 = 0x3010,
-    PTD5 = 0x3014,
-    PTD6 = 0x3018,
-    PTD7 = 0x301c,
-    PTD8 = 0x3020,
-    PTD9 = 0x3024,
-    PTD10 = 0x3028,
-    PTD11 = 0x302c,
-    PTD12 = 0x3030,
-    PTD13 = 0x3034,
-    PTD14 = 0x3038,
-    PTD15 = 0x303c,
-    PTD16 = 0x3040,
-    PTD17 = 0x3044,
-    PTD18 = 0x3048,
-    PTD19 = 0x304c,
-    PTD20 = 0x3050,
-    PTD21 = 0x3054,
-    PTD22 = 0x3058,
-    PTD23 = 0x305c,
-    PTD24 = 0x3060,
-    PTD25 = 0x3064,
-    PTD26 = 0x3068,
-    PTD27 = 0x306c,
-    PTD28 = 0x3070,
-    PTD29 = 0x3074,
-    PTD30 = 0x3078,
-    PTD31 = 0x307c,
-    PTE0 = 0x4000,
-    PTE1 = 0x4004,
-    PTE2 = 0x4008,
-    PTE3 = 0x400c,
-    PTE4 = 0x4010,
-    PTE5 = 0x4014,
-    PTE6 = 0x4018,
-    PTE7 = 0x401c,
-    PTE8 = 0x4020,
-    PTE9 = 0x4024,
-    PTE10 = 0x4028,
-    PTE11 = 0x402c,
-    PTE12 = 0x4030,
-    PTE13 = 0x4034,
-    PTE14 = 0x4038,
-    PTE15 = 0x403c,
-    PTE16 = 0x4040,
-    PTE17 = 0x4044,
-    PTE18 = 0x4048,
-    PTE19 = 0x404c,
-    PTE20 = 0x4050,
-    PTE21 = 0x4054,
-    PTE22 = 0x4058,
-    PTE23 = 0x405c,
-    PTE24 = 0x4060,
-    PTE25 = 0x4064,
-    PTE26 = 0x4068,
-    PTE27 = 0x406c,
-    PTE28 = 0x4070,
-    PTE29 = 0x4074,
-    PTE30 = 0x4078,
-    PTE31 = 0x407c,
-
-    LED_RED = PTB18,
-    LED_GREEN = PTB19,
-    LED_BLUE = PTD1,
-
-    // mbed original LED naming
-    LED1 = LED_BLUE,
-    LED2 = LED_GREEN,
-    LED3 = LED_RED,
-    LED4 = LED_RED,
-
-    // USB Pins
-    USBTX = PTA2,
-    USBRX = PTA1,
-
-    // Arduino Headers
-    D0 = PTA1,
-    D1 = PTA2,
-    D2 = PTD4,
-    D3 = PTA12,
-    D4 = PTA4,
-    D5 = PTA5,
-    D6 = PTC8,
-    D7 = PTC9,
-    D8 = PTA13,
-    D9 = PTD5,
-    D10 = PTD0,
-    D11 = PTD2,
-    D12 = PTD3,
-    D13 = PTD1,
-    D14 = PTE0,
-    D15 = PTE1,
-
-    A0 = PTB0,
-    A1 = PTB1,
-    A2 = PTB2,
-    A3 = PTB3,
-    A4 = PTC2,
-    A5 = PTC1,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
-    PullNone = 0,
-    PullDown = 2,
-    PullUp = 3,
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/Freescale/KL25Z/hal/PortNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,34 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PortA = 0,
-    PortB = 1,
-    PortC = 2,
-    PortD = 3,
-    PortE = 4
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif

--- a/vendor/Freescale/KL25Z/hal/analogin_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,87 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "analogin_api.h"
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_ADC[] = {
-    {PTE20, ADC0_SE0,  0},
-    {PTE22, ADC0_SE3,  0},
-    {PTE29, ADC0_SE4b, 0},
-    {PTE30, ADC0_SE23, 0},
-    {PTB0,  ADC0_SE8,  0},
-    {PTB1,  ADC0_SE9,  0},
-    {PTB2,  ADC0_SE12, 0},
-    {PTB3,  ADC0_SE13, 0},
-    {PTC0,  ADC0_SE14, 0},
-    {PTC1,  ADC0_SE15, 0},
-    {PTC2,  ADC0_SE11, 0},
-    {PTD1,  ADC0_SE5b, 0},
-    {PTD5,  ADC0_SE6b, 0},
-    {PTD6,  ADC0_SE7b, 0},
-    {NC,    NC,        0}
-};
-
-void analogin_init(analogin_t *obj, PinName pin) {
-    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
-    if (obj->adc == (uint32_t)NC) {
-        error("ADC pin mapping failed");
-    }
-
-    SIM->SCGC6 |= SIM_SCGC6_ADC0_MASK;
-
-    uint32_t port = (uint32_t)pin >> PORT_SHIFT;
-    SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port);
-
-    ADC0->SC1[1] = ADC_SC1_ADCH(obj->adc);
-
-    ADC0->CFG1 = ADC_CFG1_ADLPC_MASK    // Low-Power Configuration
-               | ADC_CFG1_ADIV(3)       // Clock Divide Select: (Input Clock)/8
-               | ADC_CFG1_ADLSMP_MASK   // Long Sample Time
-               | ADC_CFG1_MODE(3)       // (16)bits Resolution
-               | ADC_CFG1_ADICLK(1);    // Input Clock: (Bus Clock)/2
-
-    ADC0->CFG2 = ADC_CFG2_MUXSEL_MASK   // ADxxb channels are selected
-               | ADC_CFG2_ADACKEN_MASK  // Asynchronous Clock Output Enable
-               | ADC_CFG2_ADHSC_MASK    // High-Speed Configuration
-               | ADC_CFG2_ADLSTS(0);    // Long Sample Time Select
-
-    ADC0->SC2 = ADC_SC2_REFSEL(0);      // Default Voltage Reference
-
-    ADC0->SC3 = ADC_SC3_AVGE_MASK       // Hardware Average Enable
-              | ADC_SC3_AVGS(0);        // 4 Samples Averaged
-
-    pinmap_pinout(pin, PinMap_ADC);
-}
-
-uint16_t analogin_read_u16(analogin_t *obj) {
-    // start conversion
-    ADC0->SC1[0] = ADC_SC1_ADCH(obj->adc);
-
-    // Wait Conversion Complete
-    while ((ADC0->SC1[0] & ADC_SC1_COCO_MASK) != ADC_SC1_COCO_MASK);
-
-    // Return value
-    return (uint16_t)ADC0->R[0];
-}
-
-float analogin_read(analogin_t *obj) {
-    uint16_t value = analogin_read_u16(obj);
-    return (float)value * (1.0f / (float)0xFFFF);
-}
-

--- a/vendor/Freescale/KL25Z/hal/analogout_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,86 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "analogout_api.h"
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-#define RANGE_12BIT     0xFFF
-
-static const PinMap PinMap_DAC[] = {
-    {PTE30, DAC_0, 0},
-    {NC   , NC   , 0}
-};
-
-void analogout_init(dac_t *obj, PinName pin) {
-    obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
-    if (obj->dac == (uint32_t)NC) {
-        error("DAC pin mapping failed");
-    }
-
-    SIM->SCGC6 |= SIM_SCGC6_DAC0_MASK;
-
-    uint32_t port = (uint32_t)pin >> PORT_SHIFT;
-    SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port);
-
-    DAC0->DAT[obj->dac].DATH = 0;
-    DAC0->DAT[obj->dac].DATL = 0;
-
-    DAC0->C1 = DAC_C1_DACBFMD_MASK;     // One-Time Scan Mode
-
-    DAC0->C0 = DAC_C0_DACEN_MASK        // Enable
-             | DAC_C0_DACSWTRG_MASK;    // Software Trigger
-
-    pinmap_pinout(pin, PinMap_DAC);
-
-    analogout_write_u16(obj, 0);
-}
-
-void analogout_free(dac_t *obj) {}
-
-static inline void dac_write(dac_t *obj, int value) {
-    DAC0->DAT[obj->dac].DATL = (uint8_t)( value       & 0xFF);
-    DAC0->DAT[obj->dac].DATH = (uint8_t)((value >> 8) & 0xFF);
-}
-
-static inline int dac_read(dac_t *obj) {
-    return ((DAC0->DAT[obj->dac].DATH << 8) | DAC0->DAT[obj->dac].DATL);
-}
-
-void analogout_write(dac_t *obj, float value) {
-    if (value < 0.0) {
-        dac_write(obj, 0);
-    } else if (value > 1.0) {
-        dac_write(obj, RANGE_12BIT);
-    } else {
-        dac_write(obj, value * (float)RANGE_12BIT);
-    }
-}
-
-void analogout_write_u16(dac_t *obj, uint16_t value) {
-    dac_write(obj, value >> 4); // 12-bit
-}
-
-float analogout_read(dac_t *obj) {
-    uint32_t value = dac_read(obj);
-    return (float)value * (1.0f / (float)RANGE_12BIT);
-}
-
-uint16_t analogout_read_u16(dac_t *obj) {
-    uint32_t value = dac_read(obj); // 12-bit
-    return (value << 4) | ((value >> 8) & 0x003F);
-}

--- a/vendor/Freescale/KL25Z/hal/device.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,58 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-#define DEVICE_PORTIN           1
-#define DEVICE_PORTOUT          1
-#define DEVICE_PORTINOUT        1
-
-#define DEVICE_INTERRUPTIN      1
-
-#define DEVICE_ANALOGIN         1
-#define DEVICE_ANALOGOUT        1
-
-#define DEVICE_SERIAL           1
-
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
-
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         1
-
-#define DEVICE_CAN              0
-
-#define DEVICE_RTC              1
-
-#define DEVICE_ETHERNET         0
-
-#define DEVICE_PWMOUT           1
-
-#define DEVICE_SEMIHOST         1
-#define DEVICE_LOCALFILESYSTEM  0
-#define DEVICE_ID_LENGTH       24
-
-#define DEVICE_SLEEP            0
-
-#define DEVICE_DEBUG_AWARENESS  0
-
-#define DEVICE_STDIO_MESSAGES   1
-
-#define DEVICE_ERROR_RED        1
-
-#include "objects.h"
-
-#endif

--- a/vendor/Freescale/KL25Z/hal/gpio_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "gpio_api.h"
-#include "pinmap.h"
-
-uint32_t gpio_set(PinName pin) {
-    pin_function(pin, 1);
-    return 1 << ((pin & 0x7F) >> 2);
-}
-
-void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
-    if(pin == NC) return;
-
-    obj->pin = pin;
-    obj->mask = gpio_set(pin);
-
-    unsigned int port = (unsigned int)pin >> PORT_SHIFT;
-
-    FGPIO_Type *reg = (FGPIO_Type *)(FPTA_BASE + port * 0x40);
-    obj->reg_set = &reg->PSOR;
-    obj->reg_clr = &reg->PCOR;
-    obj->reg_in  = &reg->PDIR;
-    obj->reg_dir = &reg->PDDR;
-
-    gpio_dir(obj, direction);
-    switch (direction) {
-        case PIN_OUTPUT: pin_mode(pin, PullNone); break;
-        case PIN_INPUT : pin_mode(pin, PullDown); break;
-    }
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode) {
-    pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction) {
-    switch (direction) {
-        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
-        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
-    }
-}

--- a/vendor/Freescale/KL25Z/hal/gpio_irq_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,145 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stddef.h>
-#include "cmsis.h"
-
-#include "gpio_irq_api.h"
-#include "error.h"
-
-#define CHANNEL_NUM    64
-
-static uint32_t channel_ids[CHANNEL_NUM] = {0};
-static gpio_irq_handler irq_handler;
-
-#define IRQ_DISABLED        (0)
-#define IRQ_RAISING_EDGE    PORT_PCR_IRQC(9)
-#define IRQ_FALLING_EDGE    PORT_PCR_IRQC(10)
-#define IRQ_EITHER_EDGE     PORT_PCR_IRQC(11)
-
-static void handle_interrupt_in(PORT_Type *port, int ch_base) {
-    uint32_t mask = 0, i;
-
-    for (i = 0; i < 32; i++) {
-        uint32_t pmask = (1 << i);
-        if (port->ISFR & pmask) {
-            mask |= pmask;
-            uint32_t id = channel_ids[ch_base + i];
-            if (id == 0) continue;
-
-            FGPIO_Type *gpio;
-            gpio_irq_event event = IRQ_NONE;
-            switch (port->PCR[i] & PORT_PCR_IRQC_MASK) {
-                case IRQ_RAISING_EDGE:
-                    event = IRQ_RISE;
-                    break;
-
-                case IRQ_FALLING_EDGE:
-                    event = IRQ_FALL;
-                    break;
-
-                case IRQ_EITHER_EDGE:
-                    gpio = (port == PORTA) ? (FPTA) : (FPTD);
-                    event = (gpio->PDIR & pmask) ? (IRQ_RISE) : (IRQ_FALL);
-                    break;
-            }
-            if (event != IRQ_NONE)
-                irq_handler(id, event);
-        }
-    }
-    port->ISFR = mask;
-}
-
-void gpio_irqA(void) {handle_interrupt_in(PORTA, 0);}
-void gpio_irqD(void) {handle_interrupt_in(PORTD, 32);}
-
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
-    if (pin == NC) return -1;
-
-    irq_handler = handler;
-
-    obj->port = pin >> PORT_SHIFT;
-    obj->pin = (pin & 0x7F) >> 2;
-
-    uint32_t ch_base, vector;
-    IRQn_Type irq_n;
-    switch (obj->port) {
-            case PortA:
-                ch_base = 0;  irq_n = PORTA_IRQn; vector = (uint32_t)gpio_irqA;
-                break;
-
-            case PortD:
-                ch_base = 32; irq_n = PORTD_IRQn; vector = (uint32_t)gpio_irqD;
-                break;
-
-            default:
-                error("gpio_irq only supported on port A and D\n");
-                break;
-    }
-    NVIC_SetVector(irq_n, vector);
-    NVIC_EnableIRQ(irq_n);
-
-    obj->ch = ch_base + obj->pin;
-    channel_ids[obj->ch] = id;
-
-    return 0;
-}
-
-void gpio_irq_free(gpio_irq_t *obj) {
-    channel_ids[obj->ch] = 0;
-}
-
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
-    PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port);
-
-    uint32_t irq_settings = IRQ_DISABLED;
-
-    switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) {
-        case IRQ_DISABLED:
-            if (enable) {
-                irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE);
-            }
-            break;
-
-        case IRQ_RAISING_EDGE:
-            if (enable) {
-                irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE);
-            } else {
-                if (event == IRQ_FALL)
-                    irq_settings = IRQ_RAISING_EDGE;
-            }
-            break;
-
-        case IRQ_FALLING_EDGE:
-            if (enable) {
-                irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE);
-            } else {
-                if (event == IRQ_RISE)
-                    irq_settings = IRQ_FALLING_EDGE;
-            }
-            break;
-
-        case IRQ_EITHER_EDGE:
-            if (enable) {
-                irq_settings = IRQ_EITHER_EDGE;
-            } else {
-                irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE);
-            }
-            break;
-    }
-
-    // Interrupt configuration and clear interrupt
-    port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK;
-}

--- a/vendor/Freescale/KL25Z/hal/gpio_object.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    PinName  pin;
-    uint32_t mask;
-
-    __IO uint32_t *reg_dir;
-    __IO uint32_t *reg_set;
-    __IO uint32_t *reg_clr;
-    __I  uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
-    if (value)
-        *obj->reg_set = obj->mask;
-    else
-        *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
-    return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/Freescale/KL25Z/hal/i2c_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,406 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "i2c_api.h"
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_I2C_SDA[] = {
-    {PTE25, I2C_0, 5},
-    {PTC9,  I2C_0, 2},
-    {PTE0,  I2C_1, 6},
-    {PTB1,  I2C_0, 2},
-    {PTB3,  I2C_0, 2},
-    {NC  ,  NC   , 0}
-};
-
-static const PinMap PinMap_I2C_SCL[] = {
-    {PTE24, I2C_0, 5},
-    {PTC8,  I2C_0, 2},
-    {PTE1,  I2C_1, 6},
-    {PTB0,  I2C_0, 2},
-    {PTB2,  I2C_0, 2},
-    {NC  ,  NC,    0}
-};
-
-static const uint16_t ICR[0x40] = {
-      20,   22,   24,   26,   28,
-      30,   34,   40,   28,   32,
-      36,   40,   44,   48,   56,
-      68,   48,   56,   64,   72,
-      80,   88,  104,  128,   80,
-      96,  112,  128,  144,  160,
-      192,  240,  160,  192,  224,
-      256,  288,  320,  384,  480,
-      320,  384,  448,  512,  576,
-      640,  768,  960,  640,  768,
-      896, 1024, 1152, 1280, 1536,
-      1920, 1280, 1536, 1792, 2048,
-      2304, 2560, 3072, 3840
-};
-
-static uint8_t first_read;
-
-
-void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
-    // determine the I2C to use
-    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
-    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
-    obj->i2c = (I2C_Type*)pinmap_merge(i2c_sda, i2c_scl);
-    if ((int)obj->i2c == NC) {
-        error("I2C pin mapping failed");
-    }
-
-    // enable power
-    switch ((int)obj->i2c) {
-        case I2C_0: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 6; break;
-        case I2C_1: SIM->SCGC5 |= 1 << 11; SIM->SCGC4 |= 1 << 7; break;
-    }
-
-    // set default frequency at 100k
-    i2c_frequency(obj, 100000);
-
-    // enable I2C interface
-    obj->i2c->C1 |= 0x80;
-
-    pinmap_pinout(sda, PinMap_I2C_SDA);
-    pinmap_pinout(scl, PinMap_I2C_SCL);
-    
-    first_read = 1;
-}
-
-int i2c_start(i2c_t *obj) {
-    // if we are in the middle of a transaction
-    // activate the repeat_start flag
-    if (obj->i2c->S & I2C_S_BUSY_MASK) {
-        obj->i2c->C1 |= 0x04;
-    } else {
-        obj->i2c->C1 |= I2C_C1_MST_MASK;
-        obj->i2c->C1 |= I2C_C1_TX_MASK;
-    }
-    first_read = 1;
-    return 0;
-}
-
-void i2c_stop(i2c_t *obj) {
-    volatile uint32_t n = 0;
-    obj->i2c->C1 &= ~I2C_C1_MST_MASK;
-    obj->i2c->C1 &= ~I2C_C1_TX_MASK;
-
-    // It seems that there are timing problems
-    // when there is no waiting time after a STOP.
-    // This wait is also included on the samples
-    // code provided with the freedom board
-    for (n = 0; n < 100; n++) __NOP();
-    first_read = 1;
-}
-
-static int timeout_status_poll(i2c_t *obj, uint32_t mask) {
-    uint32_t i, timeout = 1000;
-    
-    for (i = 0; i < timeout; i++) {
-        if (obj->i2c->S & mask)
-            return 0;
-    }
-    
-    return 1;
-}
-
-// this function waits the end of a tx transfer and return the status of the transaction:
-//    0: OK ack received
-//    1: OK ack not received
-//    2: failure
-static int i2c_wait_end_tx_transfer(i2c_t *obj) {
-    
-    // wait for the interrupt flag
-    if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) {
-        return 2;
-    }
-    
-    obj->i2c->S |= I2C_S_IICIF_MASK;
-    
-    // wait transfer complete
-    if (timeout_status_poll(obj, I2C_S_TCF_MASK)) {
-        return 2;
-    }
-
-    // check if we received the ACK or not
-    return obj->i2c->S & I2C_S_RXAK_MASK ? 1 : 0;
-}
-
-// this function waits the end of a rx transfer and return the status of the transaction:
-//    0: OK
-//    1: failure
-static int i2c_wait_end_rx_transfer(i2c_t *obj) {
-    // wait for the end of the rx transfer
-    if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) {
-        return 1;
-    }
-    
-    obj->i2c->S |= I2C_S_IICIF_MASK;
-    
-    return 0;
-}
-
-static void i2c_send_nack(i2c_t *obj) {
-    obj->i2c->C1 |= I2C_C1_TXAK_MASK; // NACK
-}
-
-static void i2c_send_ack(i2c_t *obj) {
-    obj->i2c->C1 &= ~I2C_C1_TXAK_MASK; // ACK
-}
-
-static int i2c_do_write(i2c_t *obj, int value) {
-    // write the data
-    obj->i2c->D = value;
-
-    // init and wait the end of the transfer
-    return i2c_wait_end_tx_transfer(obj);
-}
-
-static int i2c_do_read(i2c_t *obj, char * data, int last) {
-    if (last)
-        i2c_send_nack(obj);
-    else
-        i2c_send_ack(obj);
-
-    *data = (obj->i2c->D & 0xFF);
-
-    // start rx transfer and wait the end of the transfer
-    return i2c_wait_end_rx_transfer(obj);
-}
-
-void i2c_frequency(i2c_t *obj, int hz) {
-    uint8_t icr = 0;
-    uint8_t mult = 0;
-    uint32_t error = 0;
-    uint32_t p_error = 0xffffffff;
-    uint32_t ref = 0;
-    uint8_t i, j;
-    // bus clk
-    uint32_t PCLK = 24000000u;
-    uint32_t pulse = PCLK / (hz * 2);
-
-    // we look for the values that minimize the error
-
-    // test all the MULT values
-    for (i = 1; i < 5; i*=2) {
-        for (j = 0; j < 0x40; j++) {
-            ref = PCLK / (i*ICR[j]);
-            error = (ref > hz) ? ref - hz : hz - ref;
-            if (error < p_error) {
-                icr = j;
-                mult = i/2;
-                p_error = error;
-            }
-        }
-    }
-    pulse = icr | (mult << 6);
-
-    // I2C Rate
-    obj->i2c->F = pulse;
-}
-
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
-    uint8_t count;
-    char dummy_read, *ptr;
-
-    if (i2c_start(obj)) {
-        i2c_stop(obj);
-        return 1;
-    }
-
-    if (i2c_do_write(obj, (address | 0x01))) {
-        i2c_stop(obj);
-        return 1;
-    }
-
-    // set rx mode
-    obj->i2c->C1 &= ~I2C_C1_TX_MASK;
-
-    // Read in bytes
-    for (count = 0; count < (length); count++) {
-        ptr = (count == 0) ? &dummy_read : &data[count - 1];
-        uint8_t stop_ = (count == (length - 1)) ? 1 : 0;
-        if (i2c_do_read(obj, ptr, stop_)) {
-            i2c_stop(obj);
-            return 1;
-        }
-    }
-
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-    }
-
-    // last read
-    data[count-1] = obj->i2c->D;
-
-    return 0;
-}
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
-    int i;
-
-    if (i2c_start(obj)) {
-        i2c_stop(obj);
-        return 1;
-    }
-
-    if (i2c_do_write(obj, (address & 0xFE))) {
-        i2c_stop(obj);
-        return 1;
-    }
-
-    for (i = 0; i < length; i++) {
-        if(i2c_do_write(obj, data[i])) {
-            i2c_stop(obj);
-            return 1;
-        }
-    }
-
-    if (stop) {
-        i2c_stop(obj);
-    }
-
-    return 0;
-}
-
-void i2c_reset(i2c_t *obj) {
-    i2c_stop(obj);
-}
-
-int i2c_byte_read(i2c_t *obj, int last) {
-    char data;
-    
-    // set rx mode
-    obj->i2c->C1 &= ~I2C_C1_TX_MASK;
-    
-    if(first_read) {
-        // first dummy read
-        i2c_do_read(obj, &data, 0);
-        first_read = 0;
-    }
-    
-    if (last) {
-        // set tx mode
-        obj->i2c->C1 |= I2C_C1_TX_MASK;
-        return obj->i2c->D;
-    }
-        
-    i2c_do_read(obj, &data, last);
-    
-    return data;
-}
-
-int i2c_byte_write(i2c_t *obj, int data) {
-    first_read = 1;
-    
-    // set tx mode
-    obj->i2c->C1 |= I2C_C1_TX_MASK;
-    
-    return !i2c_do_write(obj, (data & 0xFF));
-}
-
-
-#if DEVICE_I2CSLAVE
-void i2c_slave_mode(i2c_t *obj, int enable_slave) {
-    if (enable_slave) {
-        // set slave mode
-        obj->i2c->C1 &= ~I2C_C1_MST_MASK;
-        obj->i2c->C1 |= I2C_C1_IICIE_MASK;
-    } else {
-        // set master mode
-        obj->i2c->C1 |= I2C_C1_MST_MASK;
-    }
-}
-
-int i2c_slave_receive(i2c_t *obj) {
-    switch(obj->i2c->S) {
-        // read addressed
-        case 0xE6: return 1;
-        
-        // write addressed
-        case 0xE2: return 3;
-        
-        default: return 0;
-    }
-}
-
-int i2c_slave_read(i2c_t *obj, char *data, int length) {
-    uint8_t dummy_read, count;
-    uint8_t * ptr;
-    
-    // set rx mode
-    obj->i2c->C1 &= ~I2C_C1_TX_MASK;
-    
-    // first dummy read
-    dummy_read = obj->i2c->D;
-    if(i2c_wait_end_rx_transfer(obj)) {
-        return 0;
-    }
-    
-    // read address
-    dummy_read = obj->i2c->D;
-    if(i2c_wait_end_rx_transfer(obj)) {
-        return 0;
-    }
-    
-    // read (length - 1) bytes
-    for (count = 0; count < (length - 1); count++) {
-        data[count] = obj->i2c->D;
-        if(i2c_wait_end_rx_transfer(obj)) {
-            return 0;
-        }
-    }
-
-    // read last byte
-    ptr = (length == 0) ? &dummy_read : (uint8_t *)&data[count];
-    *ptr = obj->i2c->D;
-    
-    return (length) ? (count + 1) : 0;
-}
-
-int i2c_slave_write(i2c_t *obj, const char *data, int length) {
-    uint32_t i, count = 0;
-    
-    // set tx mode
-    obj->i2c->C1 |= I2C_C1_TX_MASK;
-    
-    for (i = 0; i < length; i++) {
-        if(i2c_do_write(obj, data[count++]) == 2) {
-            return 0;
-        }
-    }
-    
-    // set rx mode
-    obj->i2c->C1 &= ~I2C_C1_TX_MASK;
-    
-    // dummy rx transfer needed
-    // otherwise the master cannot generate a stop bit
-    obj->i2c->D;
-    if(i2c_wait_end_rx_transfer(obj) == 2) {
-        return 0;
-    }
-    
-    return count;
-}
-
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
-    obj->i2c->A1 = address & 0xfe;
-}
-#endif
-

--- a/vendor/Freescale/KL25Z/hal/objects.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    uint32_t port;
-    uint32_t pin;
-    uint32_t ch;
-};
-
-struct port_s {
-    __IO uint32_t *reg_dir;
-    __IO uint32_t *reg_out;
-    __I  uint32_t *reg_in;
-    PortName port;
-    uint32_t mask;
-};
-
-struct pwmout_s {
-    __IO uint32_t *MOD;
-    __IO uint32_t *CNT;
-    __IO uint32_t *CnV;
-};
-
-struct serial_s {
-    UARTLP_Type *uart;
-    int index;
-};
-
-struct analogin_s {
-    ADCName adc;
-};
-
-struct dac_s {
-    DACName dac;
-};
-
-struct i2c_s {
-    I2C_Type *i2c;
-};
-
-struct spi_s {
-    SPI_Type *spi;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/Freescale/KL25Z/hal/pinmap.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,39 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "pinmap.h"
-#include "error.h"
-
-void pin_function(PinName pin, int function) {
-    if (pin == (uint32_t)NC) return;
-
-    uint32_t port_n = (uint32_t)pin >> PORT_SHIFT;
-    uint32_t pin_n  = (uint32_t)(pin & 0x7C) >> 2;
-
-    SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port_n);
-    __IO uint32_t* pin_pcr = &(((PORT_Type *)(PORTA_BASE + 0x1000 * port_n)))->PCR[pin_n];
-
-    // pin mux bits: [10:8] -> 11100000000 = (0x700)
-    *pin_pcr = (*pin_pcr & ~0x700) | (function << 8);
-}
-
-void pin_mode(PinName pin, PinMode mode) {
-    if (pin == (uint32_t)NC) { return; }
-
-    __IO uint32_t* pin_pcr = (__IO uint32_t*)(PORTA_BASE + pin);
-
-    // pin pullup bits: [1:0] -> 11 = (0x3)
-    *pin_pcr = (*pin_pcr & ~0x3) | mode;
-}

--- a/vendor/Freescale/KL25Z/hal/port_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,68 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "port_api.h"
-#include "pinmap.h"
-#include "gpio_api.h"
-
-PinName port_pin(PortName port, int pin_n) {
-    return (PinName)((port << PORT_SHIFT) | (pin_n << 2));
-}
-
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
-    obj->port = port;
-    obj->mask = mask;
-
-    FGPIO_Type *reg = (FGPIO_Type *)(FPTA_BASE + port * 0x40);
-
-    obj->reg_out = &reg->PDOR;
-    obj->reg_in  = &reg->PDIR;
-    obj->reg_dir = &reg->PDDR;
-
-    uint32_t i;
-    // The function is set per pin: reuse gpio logic
-    for (i=0; i<32; i++) {
-        if (obj->mask & (1<<i)) {
-            gpio_set(port_pin(obj->port, i));
-        }
-    }
-
-    port_dir(obj, dir);
-}
-
-void port_mode(port_t *obj, PinMode mode) {
-    uint32_t i;
-    // The mode is set per pin: reuse pinmap logic
-    for (i=0; i<32; i++) {
-        if (obj->mask & (1<<i)) {
-            pin_mode(port_pin(obj->port, i), mode);
-        }
-    }
-}
-
-void port_dir(port_t *obj, PinDirection dir) {
-    switch (dir) {
-        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
-        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
-    }
-}
-
-void port_write(port_t *obj, int value) {
-    *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
-}
-
-int port_read(port_t *obj) {
-    return (*obj->reg_in & obj->mask);
-}

--- a/vendor/Freescale/KL25Z/hal/pwmout_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "pwmout_api.h"
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_PWM[] = {
-    // LEDs
-    {LED_RED  , PWM_9 , 3}, // PTB18, TPM2 CH0
-    {LED_GREEN, PWM_10, 3}, // PTB19, TPM2 CH1
-    {LED_BLUE , PWM_2 , 4}, // PTD1 , TPM0 CH1
-
-    // Arduino digital pinout
-    {D0,  PWM_9 , 3}, // PTA1 , TPM2 CH0
-    {D1,  PWM_10, 3}, // PTA2 , TPM2 CH1
-    {D2,  PWM_5 , 4}, // PTD4 , TPM0 CH4
-    {D3,  PWM_7 , 3}, // PTA12, TPM1 CH0
-    {D4,  PWM_2 , 3}, // PTA4 , TPM0 CH1
-    {D5,  PWM_3 , 3}, // PTA5 , TPM0 CH2
-    {D6,  PWM_5 , 3}, // PTC8 , TPM0 CH4
-    {D7,  PWM_6 , 3}, // PTC9 , TPM0 CH5
-    {D8,  PWM_8 , 3}, // PTA13, TPM1 CH1
-    {D9,  PWM_6 , 4}, // PTD5 , TPM0 CH5
-    {D10, PWM_1 , 4}, // PTD0 , TPM0 CH0
-    {D11, PWM_3 , 4}, // PTD2 , TPM0 CH2
-    {D12, PWM_4 , 4}, // PTD3 , TPM0 CH3
-    {D13, PWM_2 , 4}, // PTD1 , TPM0 CH1
-    {NC , NC    , 0}
-};
-
-#define PWM_CLOCK_MHZ       (0.75) // (48)MHz / 64 = (0.75)MHz
-
-void pwmout_init(pwmout_t* obj, PinName pin) {
-    // determine the channel
-    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
-    if (pwm == (uint32_t)NC)
-        error("PwmOut pin mapping failed");
-
-    unsigned int port = (unsigned int)pin >> PORT_SHIFT;
-    unsigned int tpm_n = (pwm >> TPM_SHIFT);
-    unsigned int ch_n = (pwm & 0xFF);
-
-    SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port);
-    SIM->SCGC6 |= 1 << (SIM_SCGC6_TPM0_SHIFT + tpm_n);
-    SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); // Clock source: MCGFLLCLK or MCGPLLCLK
-
-    TPM_Type *tpm = (TPM_Type *)(TPM0_BASE + 0x1000 * tpm_n);
-    tpm->SC = TPM_SC_CMOD(1) | TPM_SC_PS(6); // (48)MHz / 64 = (0.75)MHz
-    tpm->CONTROLS[ch_n].CnSC = (TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK); /* No Interrupts; High True pulses on Edge Aligned PWM */
-
-    obj->CnV = &tpm->CONTROLS[ch_n].CnV;
-    obj->MOD = &tpm->MOD;
-    obj->CNT = &tpm->CNT;
-
-    // default to 20ms: standard for servos, and fine for e.g. brightness control
-    pwmout_period_ms(obj, 20);
-    pwmout_write    (obj, 0);
-
-    // Wire pinout
-    pinmap_pinout(pin, PinMap_PWM);
-}
-
-void pwmout_free(pwmout_t* obj) {}
-
-void pwmout_write(pwmout_t* obj, float value) {
-    if (value < 0.0) {
-        value = 0.0;
-    } else if (value > 1.0) {
-        value = 1.0;
-    }
-
-    *obj->CnV = (uint32_t)((float)(*obj->MOD) * value);
-    *obj->CNT = 0;
-}
-
-float pwmout_read(pwmout_t* obj) {
-    float v = (float)(*obj->CnV) / (float)(*obj->MOD);
-    return (v > 1.0) ? (1.0) : (v);
-}
-
-void pwmout_period(pwmout_t* obj, float seconds) {
-    pwmout_period_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_period_ms(pwmout_t* obj, int ms) {
-    pwmout_period_us(obj, ms * 1000);
-}
-
-// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
-    float dc = pwmout_read(obj);
-    *obj->MOD = PWM_CLOCK_MHZ * us;
-    pwmout_write(obj, dc);
-}
-
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
-    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
-    pwmout_pulsewidth_us(obj, ms * 1000);
-}
-
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
-    *obj->CnV = PWM_CLOCK_MHZ * us;
-}

--- a/vendor/Freescale/KL25Z/hal/rtc_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,95 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "rtc_api.h"
-
-#if DEVICE_RTC
-
-static void init(void) {
-    // enable PORTC clock
-    SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
-
-    // enable RTC clock
-    SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
-
-    /*
-    * configure PTC1 with alternate function 1: RTC_CLKIN
-    * As the kl25z board does not have a 32kHz osc,
-    * we use an external clock generated by the
-    * interface chip
-    */
-    PORTC->PCR[1] &= ~PORT_PCR_MUX_MASK;
-    PORTC->PCR[1] = PORT_PCR_MUX(1);
-
-    // select RTC_CLKIN as RTC clock source
-    SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
-    SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(2);
-}
-
-void rtc_init(void) {
-    init();
-
-    //Configure the TSR. default value: 1
-    RTC->TSR = 1;
-
-    // enable counter
-    RTC->SR |= RTC_SR_TCE_MASK;
-}
-
-void rtc_free(void) {
-    // [TODO]
-}
-
-/*
- * Little check routine to see if the RTC has been enabled
- * 0 = Disabled, 1 = Enabled
- */
-int rtc_isenabled(void) {
-    // even if the RTC module is enabled,
-    // as we use RTC_CLKIN and an external clock,
-    // we need to reconfigure the pins. That is why we
-    // call init() if the rtc is enabled
-
-    // if RTC not enabled return 0
-    SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
-    SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
-    if ((RTC->SR & RTC_SR_TCE_MASK) == 0)
-        return 0;
-
-    init();
-    return 1;
-}
-
-time_t rtc_read(void) {
-    return RTC->TSR;
-}
-
-void rtc_write(time_t t) {
-    // disable counter
-    RTC->SR &= ~RTC_SR_TCE_MASK;
-
-    // we do not write 0 into TSR
-    // to avoid invalid time
-    if (t == 0)
-        t = 1;
-
-    // write seconds
-    RTC->TSR = t;
-
-    // re-enable counter
-    RTC->SR |= RTC_SR_TCE_MASK;
-}
-
-#endif

--- a/vendor/Freescale/KL25Z/hal/serial_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,296 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "serial_api.h"
-
-// math.h required for floating point operations for baud rate calculation
-#include <math.h>
-
-#include <string.h>
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-/******************************************************************************
- * INITIALIZATION
- ******************************************************************************/
-static const PinMap PinMap_UART_TX[] = {
-    {PTC4, UART_1, 3},
-    {PTA2, UART_0, 2},
-    {PTD5, UART_2, 3},
-    {PTD3, UART_2, 3},
-    {NC  , NC    , 0}
-};
-
-static const PinMap PinMap_UART_RX[] = {
-    {PTC3, UART_1, 3},
-    {PTA1, UART_0, 2},
-    {PTD4, UART_2, 3},
-    {PTD2, UART_2, 3},
-    {NC  , NC    , 0}
-};
-
-#define UART_NUM    3
-static uint32_t serial_irq_ids[UART_NUM] = {0};
-static uart_irq_handler irq_handler;
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
-    // determine the UART to use
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-    UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    if ((int)uart == NC) {
-        error("Serial pinout mapping failed");
-    }
-
-    obj->uart = (UARTLP_Type *)uart;
-    // enable clk
-    switch (uart) {
-        case UART_0: SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK | (1<<SIM_SOPT2_UART0SRC_SHIFT);
-                     SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; break;
-        case UART_1: SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK; SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; break;
-        case UART_2: SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK; SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; break;
-    }
-    // Disable UART before changing registers
-    obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
-    
-    switch (uart) {
-        case UART_0: obj->index = 0; break;
-        case UART_1: obj->index = 1; break;
-        case UART_2: obj->index = 2; break;
-    }
-
-    // set default baud rate and format
-    serial_baud  (obj, 9600);
-    serial_format(obj, 8, ParityNone, 1);
-
-    // pinout the chosen uart
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-
-    // set rx/tx pins in PullUp mode
-    pin_mode(tx, PullUp);
-    pin_mode(rx, PullUp);
-
-    obj->uart->C2 |= (UART_C2_RE_MASK | UART_C2_TE_MASK);
-
-    if (uart == STDIO_UART) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj) {
-    serial_irq_ids[obj->index] = 0;
-}
-
-// serial_baud
-//
-// set the baud rate, taking in to account the current SystemFrequency
-//
-// The LPC2300 and LPC1700 have a divider and a fractional divider to control the
-// baud rate. The formula is:
-//
-// Baudrate = (1 / PCLK) * 16 * DL * (1 + DivAddVal / MulVal)
-//   where:
-//     1 < MulVal <= 15
-//     0 <= DivAddVal < 14
-//     DivAddVal < MulVal
-//
-void serial_baud(serial_t *obj, int baudrate) {
-    
-    // save C2 state
-    uint8_t c2_state = (obj->uart->C2 & (UART_C2_RE_MASK | UART_C2_TE_MASK));
-    
-    // Disable UART before changing registers
-    obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
-    
-    // [TODO] not hardcode this value
-    uint32_t PCLK = (obj->uart == UART0) ? 48000000u : 24000000u;
-
-    // First we check to see if the basic divide with no DivAddVal/MulVal
-    // ratio gives us an integer result. If it does, we set DivAddVal = 0,
-    // MulVal = 1. Otherwise, we search the valid ratio value range to find
-    // the closest match. This could be more elegant, using search methods
-    // and/or lookup tables, but the brute force method is not that much
-    // slower, and is more maintainable.
-    uint16_t DL = PCLK / (16 * baudrate);
-
-    // set BDH and BDL
-    obj->uart->BDH = (obj->uart->BDH & ~(0x1f)) | ((DL >> 8) & 0x1f);
-    obj->uart->BDL = (obj->uart->BDL & ~(0xff)) | ((DL >> 0) & 0xff);
-    
-    // restore C2 state
-    obj->uart->C2 |= c2_state;
-}
-
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
-    uint8_t m10 = 0;
-    
-    // save C2 state
-    uint8_t c2_state = (obj->uart->C2 & (UART_C2_RE_MASK | UART_C2_TE_MASK));
-    
-    // Disable UART before changing registers
-    obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
-    
-    // 8 data bits = 0 ... 9 data bits = 1
-    if ((data_bits < 8) || (data_bits > 9)) {
-        error("Invalid number of bits (%d) in serial format, should be 8..9\r\n", data_bits);
-    }
-    data_bits -= 8;
-
-    uint8_t parity_enable, parity_select;
-    switch (parity) {
-        case ParityNone: parity_enable = 0; parity_select = 0; break;
-        case ParityOdd : parity_enable = 1; parity_select = 1; data_bits++; break;
-        case ParityEven: parity_enable = 1; parity_select = 0; data_bits++; break;
-        default:
-            error("Invalid serial parity setting\r\n");
-            return;
-    }
-
-    // 1 stop bits = 0, 2 stop bits = 1
-    if ((stop_bits != 1) && (stop_bits != 2)) {
-        error("Invalid stop bits specified\r\n");
-    }
-    stop_bits -= 1;
-    
-    // 9 data bits + parity
-    if (data_bits == 2) {
-        // only uart0 supports 10 bit communication
-        if (obj->index != 0) {
-            error("Invalid number of bits (9) to be used with parity\r\n");
-        }
-        data_bits = 0;
-        m10 = 1;
-    }
-
-    // data bits, parity and parity mode
-    obj->uart->C1 = ((data_bits << 4)
-                  |  (parity_enable << 1)
-                  |  (parity_select << 0));
-    
-    // enable 10bit mode if needed
-    if (obj->index == 0) {
-        obj->uart->C4 &= ~UARTLP_C4_M10_MASK;
-        obj->uart->C4 |= (m10 << UARTLP_C4_M10_SHIFT);
-    }
-    
-    // stop bits
-    obj->uart->BDH &= ~UART_BDH_SBNS_MASK;
-    obj->uart->BDH |= (stop_bits << UART_BDH_SBNS_SHIFT);
-    
-    // restore C2 state
-    obj->uart->C2 |= c2_state;
-}
-
-/******************************************************************************
- * INTERRUPTS HANDLING
- ******************************************************************************/
-static inline void uart_irq(uint8_t status, uint32_t index) {
-    if (serial_irq_ids[index] != 0) {
-        if (status & UART_S1_TDRE_MASK)
-            irq_handler(serial_irq_ids[index], TxIrq);
-
-        if (status & UART_S1_RDRF_MASK)
-            irq_handler(serial_irq_ids[index], RxIrq);
-    }
-}
-
-void uart0_irq() {
-    uart_irq(UART0->S1, 0);
-    if (UART0->S1 & UART_S1_OR_MASK)
-        UART0->S1 |= UART_S1_OR_MASK;
-}
-void uart1_irq() {uart_irq(UART1->S1, 1);}
-void uart2_irq() {uart_irq(UART2->S1, 2);}
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
-    irq_handler = handler;
-    serial_irq_ids[obj->index] = id;
-}
-
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
-    IRQn_Type irq_n = (IRQn_Type)0;
-    uint32_t vector = 0;
-    switch ((int)obj->uart) {
-        case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
-        case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
-        case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
-    }
-
-    if (enable) {
-        switch (irq) {
-            case RxIrq: obj->uart->C2 |= (UART_C2_RIE_MASK); break;
-            case TxIrq: obj->uart->C2 |= (UART_C2_TIE_MASK); break;
-        }
-        NVIC_SetVector(irq_n, vector);
-        NVIC_EnableIRQ(irq_n);
-
-    } else { // disable
-        int all_disabled = 0;
-        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
-        switch (irq) {
-            case RxIrq: obj->uart->C2 &= ~(UART_C2_RIE_MASK); break;
-            case TxIrq: obj->uart->C2 &= ~(UART_C2_TIE_MASK); break;
-        }
-        switch (other_irq) {
-            case RxIrq: all_disabled = (obj->uart->C2 & (UART_C2_RIE_MASK)) == 0; break;
-            case TxIrq: all_disabled = (obj->uart->C2 & (UART_C2_TIE_MASK)) == 0; break;
-        }
-        if (all_disabled)
-            NVIC_DisableIRQ(irq_n);
-    }
-}
-
-/******************************************************************************
- * READ/WRITE
- ******************************************************************************/
-int serial_getc(serial_t *obj) {
-    while (!serial_readable(obj));
-    return obj->uart->D;
-}
-
-void serial_putc(serial_t *obj, int c) {
-    while (!serial_writable(obj));
-    obj->uart->D = c;
-}
-
-int serial_readable(serial_t *obj) {
-    // check overrun
-    if (obj->uart->S1 &  UART_S1_OR_MASK) {
-        obj->uart->S1 |= UART_S1_OR_MASK;
-    }
-    return (obj->uart->S1 & UART_S1_RDRF_MASK);
-}
-
-int serial_writable(serial_t *obj) {
-    // check overrun
-    if (obj->uart->S1 &  UART_S1_OR_MASK) {
-        obj->uart->S1 |= UART_S1_OR_MASK;
-    }
-    return (obj->uart->S1 & UART_S1_TDRE_MASK);
-}
-
-void serial_clear(serial_t *obj) {
-}
-
-void serial_pinout_tx(PinName tx) {
-    pinmap_pinout(tx, PinMap_UART_TX);
-}

--- a/vendor/Freescale/KL25Z/hal/spi_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,175 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "spi_api.h"
-
-#include <math.h>
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_SPI_SCLK[] = {
-    {PTE2, SPI_1, 2},
-    {PTC5, SPI_0, 2},
-    {PTD1, SPI_0, 2},
-    {NC  , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_MOSI[] = {
-    {PTE1, SPI_1, 2},
-    {PTC6, SPI_0, 2},
-    {PTD2, SPI_0, 2},
-    {NC  , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_MISO[] = {
-    {PTE3, SPI_1, 2},
-    {PTC7, SPI_0, 2},
-    {PTD3, SPI_0, 2},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_SSEL[] = {
-    {PTE4, SPI_1, 2},
-    {PTC4, SPI_0, 2},
-    {PTD0, SPI_0, 2},
-    {NC  , NC   , 0}
-};
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
-    // determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
-    obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
-    if ((int)obj->spi == NC) {
-        error("SPI pinout mapping failed");
-    }
-
-    // enable power and clocking
-    switch ((int)obj->spi) {
-        case SPI_0: SIM->SCGC5 |= 1 << 11; SIM->SCGC4 |= 1 << 22; break;
-        case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
-    }
-
-    // set default format and frequency
-    if (ssel == NC) {
-        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
-    } else {
-        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
-    }
-    spi_frequency(obj, 1000000);
-
-    // enable SPI
-    obj->spi->C1 |= SPI_C1_SPE_MASK;
-
-    // pin out the spi pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    }
-}
-
-void spi_free(spi_t *obj) {
-    // [TODO]
-}
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
-    if (bits != 8) {
-        error("Only 8bits SPI supported");
-    }
-
-    if ((mode < 0) || (mode > 3)) {
-        error("SPI mode unsupported");
-    }
-
-    uint8_t polarity = (mode & 0x2) ? 1 : 0;
-    uint8_t phase = (mode & 0x1) ? 1 : 0;
-    uint8_t c1_data = ((!slave) << 4) | (polarity << 3) | (phase << 2);
-
-    // clear MSTR, CPOL and CPHA bits
-    obj->spi->C1 &= ~(0x7 << 2);
-
-    // write new value
-    obj->spi->C1 |= c1_data;
-}
-
-void spi_frequency(spi_t *obj, int hz) {
-    uint32_t error = 0;
-    uint32_t p_error = 0xffffffff;
-    uint32_t ref = 0;
-    uint8_t  spr = 0;
-    uint8_t  ref_spr = 0;
-    uint8_t  ref_prescaler = 0;
-
-    // bus clk
-    uint32_t PCLK = 48000000u;
-    uint8_t prescaler = 1;
-    uint8_t divisor = 2;
-
-    for (prescaler = 1; prescaler <= 8; prescaler++) {
-        divisor = 2;
-        for (spr = 0; spr <= 8; spr++) {
-            ref = PCLK / (prescaler*divisor);
-            error = (ref > hz) ? ref - hz : hz - ref;
-            if (error < p_error) {
-                ref_spr = spr;
-                ref_prescaler = prescaler - 1;
-                p_error = error;
-            }
-            divisor *= 2;
-        }
-    }
-
-    // set SPPR and SPR
-    obj->spi->BR = ((ref_prescaler & 0x7) << 4) | (ref_spr & 0xf);
-}
-
-static inline int spi_writeable(spi_t * obj) {
-    return (obj->spi->S & SPI_S_SPTEF_MASK) ? 1 : 0;
-}
-
-static inline int spi_readable(spi_t * obj) {
-    return (obj->spi->S & SPI_S_SPRF_MASK) ? 1 : 0;
-}
-
-int spi_master_write(spi_t *obj, int value) {
-    // wait tx buffer empty
-    while(!spi_writeable(obj));
-    obj->spi->D = (value & 0xff);
-
-    // wait rx buffer full
-    while (!spi_readable(obj));
-    return obj->spi->D & 0xff;
-}
-
-int spi_slave_receive(spi_t *obj) {
-    return spi_readable(obj);
-}
-
-int spi_slave_read(spi_t *obj) {
-    return obj->spi->D;
-}
-
-void spi_slave_write(spi_t *obj, int value) {
-    while (!spi_writeable(obj));
-    obj->spi->D = value;
-}

--- a/vendor/Freescale/KL25Z/hal/us_ticker.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,146 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stddef.h>
-#include "us_ticker_api.h"
-#include "PeripheralNames.h"
-
-static void pit_init(void);
-static void lptmr_init(void);
-
-static int us_ticker_inited = 0;
-
-void us_ticker_init(void) {
-    if (us_ticker_inited) return;
-    us_ticker_inited = 1;
-    
-    pit_init();
-    lptmr_init();
-}
-
-/******************************************************************************
- * Timer for us timing.
- ******************************************************************************/
-static void pit_init(void) {
-    SIM->SCGC6 |= SIM_SCGC6_PIT_MASK;   // Clock PIT
-    PIT->MCR = 0;                       // Enable PIT
-    
-    // Channel 1
-    PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF;
-    PIT->CHANNEL[1].TCTRL = PIT_TCTRL_CHN_MASK;    // Chain to timer 0, disable Interrupts
-    PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_TEN_MASK;   // Start timer 1
-    
-    // Use channel 0 as a prescaler for channel 1
-    PIT->CHANNEL[0].LDVAL = 23;
-    PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK;    // Start timer 0, disable interrupts
-}
-
-uint32_t us_ticker_read() {
-    if (!us_ticker_inited)
-        us_ticker_init();
-    
-    // The PIT is a countdown timer
-    return ~(PIT->CHANNEL[1].CVAL);
-}
-
-/******************************************************************************
- * Timer Event
- * 
- * It schedules interrupts at given (32bit)us interval of time.
- * It is implemented used the 16bit Low Power Timer that remains powered in all
- * power modes.
- ******************************************************************************/
-static void lptmr_isr(void);
-
-static void lptmr_init(void) {
-    /* Clock the timer */
-    SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
-    
-    /* Reset */
-    LPTMR0->CSR = 0;
-    
-    /* Set interrupt handler */
-    NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr);
-    NVIC_EnableIRQ(LPTimer_IRQn);
-    
-    /* Clock at (1)MHz -> (1)tick/us */
-    LPTMR0->PSR = LPTMR_PSR_PCS(3);       // OSCERCLK -> 8MHz
-    LPTMR0->PSR |= LPTMR_PSR_PRESCALE(2); // divide by 8
-}
-
-void us_ticker_disable_interrupt(void) {
-    LPTMR0->CSR &= ~LPTMR_CSR_TIE_MASK;
-}
-
-void us_ticker_clear_interrupt(void) {
-    // we already clear interrupt in lptmr_isr
-}
-
-static uint32_t us_ticker_int_counter = 0;
-static uint16_t us_ticker_int_remainder = 0;
-
-static void lptmr_set(unsigned short count) {
-    /* Reset */
-    LPTMR0->CSR = 0;
-    
-    /* Set the compare register */
-    LPTMR0->CMR = count;
-    
-    /* Enable interrupt */
-    LPTMR0->CSR |= LPTMR_CSR_TIE_MASK;
-    
-    /* Start the timer */
-    LPTMR0->CSR |= LPTMR_CSR_TEN_MASK;
-}
-
-static void lptmr_isr(void) {
-    // write 1 to TCF to clear the LPT timer compare flag
-    LPTMR0->CSR |= LPTMR_CSR_TCF_MASK;
-    
-    if (us_ticker_int_counter > 0) {
-        lptmr_set(0xFFFF);
-        us_ticker_int_counter--;
-    
-    } else {
-        if (us_ticker_int_remainder > 0) {
-            lptmr_set(us_ticker_int_remainder);
-            us_ticker_int_remainder = 0;
-        
-        } else {
-            // This function is going to disable the interrupts if there are
-            // no other events in the queue
-            us_ticker_irq_handler();
-        }
-    }
-}
-
-void us_ticker_set_interrupt(unsigned int timestamp) {
-    int delta = (int)(timestamp - us_ticker_read());
-    if (delta <= 0) {
-        // This event was in the past:
-        us_ticker_irq_handler();
-        return;
-    }
-    
-    us_ticker_int_counter   = (uint32_t)(delta >> 16);
-    us_ticker_int_remainder = (uint16_t)(0xFFFF & delta);
-    if (us_ticker_int_counter > 0) {
-        lptmr_set(0xFFFF);
-        us_ticker_int_counter--;
-    } else {
-        lptmr_set(us_ticker_int_remainder);
-        us_ticker_int_remainder = 0;
-    }
-}

--- a/vendor/NXP/LPC11U24/cmsis/ARM/LPC11U24.sct	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,14 +0,0 @@
-
-LR_IROM1 0x00000000 0x8000  {    ; load region size_region (32k)
-  ER_IROM1 0x00000000 0x8000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
-  ; 8KB - 0xC0 = 0xF40
-  RW_IRAM1 0x100000C0 0xF40  {
-   .ANY (+RW +ZI)
-  }
-}
-

--- a/vendor/NXP/LPC11U24/cmsis/ARM/startup_LPC11xx.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,308 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC11xx.s
-; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
-; *           for the NXP LPC11xx Device Series 
-; * @version: V1.0
-; * @date:    25. Nov. 2008
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2008 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
-; * processor based microcontrollers.  This file can be freely distributed 
-; * within development tools that are supporting such ARM based processors. 
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-__initial_sp        EQU     0x10001000  ; Top of RAM from LPC11U
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-				; for LPC11Uxx (With USB)
-                DCD     FLEX_INT0_IRQHandler      ; All GPIO pin can be routed to FLEX_INTx
-                DCD     FLEX_INT1_IRQHandler          
-                DCD     FLEX_INT2_IRQHandler                       
-                DCD     FLEX_INT3_IRQHandler                         
-                DCD     FLEX_INT4_IRQHandler                        
-                DCD     FLEX_INT5_IRQHandler
-                DCD     FLEX_INT6_IRQHandler
-                DCD     FLEX_INT7_IRQHandler                       
-                DCD     GINT0_IRQHandler                         
-                DCD     GINT1_IRQHandler          ; PIO0 (0:7)              
-                DCD     Reserved_IRQHandler	      ; Reserved
-                DCD     Reserved_IRQHandler
-                DCD     Reserved_IRQHandler       
-                DCD     Reserved_IRQHandler                       
-                DCD     SSP1_IRQHandler           ; SSP1               
-                DCD     I2C_IRQHandler            ; I2C
-                DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
-                DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
-                DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
-                DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
-                DCD     SSP0_IRQHandler           ; SSP0
-                DCD     UART_IRQHandler           ; UART
-                DCD     USB_IRQHandler            ; USB IRQ
-                DCD     USB_FIQHandler            ; USB FIQ
-                DCD     ADC_IRQHandler            ; A/D Converter
-                DCD     WDT_IRQHandler            ; Watchdog timer
-                DCD     BOD_IRQHandler            ; Brown Out Detect
-                DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
-                DCD     Reserved_IRQHandler	    ; Reserved
-                DCD     Reserved_IRQHandler       ; Reserved
-                DCD     USBWakeup_IRQHandler      ; USB wake up
-                DCD     Reserved_IRQHandler       ; Reserved
-	
-	;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
-                
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-	
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-	
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)                
-
-; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled 
-; for particular peripheral.
-;NMI_Handler     PROC
-;                EXPORT  NMI_Handler               [WEAK]
-;                B       .
-;                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-Reserved_IRQHandler PROC
-                EXPORT  Reserved_IRQHandler       [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-; for LPC11Uxx (With USB)
-                EXPORT  NMI_Handler               [WEAK]
-                EXPORT  FLEX_INT0_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT1_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT2_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT3_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT4_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT5_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT6_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT7_IRQHandler      [WEAK]
-                EXPORT  GINT0_IRQHandler          [WEAK]
-                EXPORT  GINT1_IRQHandler          [WEAK]
-                EXPORT  SSP1_IRQHandler           [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  TIMER16_0_IRQHandler      [WEAK]
-                EXPORT  TIMER16_1_IRQHandler      [WEAK]
-                EXPORT  TIMER32_0_IRQHandler      [WEAK]
-                EXPORT  TIMER32_1_IRQHandler      [WEAK]
-                EXPORT  SSP0_IRQHandler           [WEAK]
-                EXPORT  UART_IRQHandler           [WEAK]
-
-                EXPORT  USB_IRQHandler            [WEAK]
-                EXPORT  USB_FIQHandler            [WEAK]
-                EXPORT  ADC_IRQHandler            [WEAK]
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  BOD_IRQHandler            [WEAK]
-                EXPORT  FMC_IRQHandler            [WEAK]
-                EXPORT	USBWakeup_IRQHandler      [WEAK]
-
-NMI_Handler
-FLEX_INT0_IRQHandler
-FLEX_INT1_IRQHandler
-FLEX_INT2_IRQHandler
-FLEX_INT3_IRQHandler
-FLEX_INT4_IRQHandler
-FLEX_INT5_IRQHandler
-FLEX_INT6_IRQHandler
-FLEX_INT7_IRQHandler
-GINT0_IRQHandler
-GINT1_IRQHandler
-SSP1_IRQHandler
-I2C_IRQHandler
-TIMER16_0_IRQHandler
-TIMER16_1_IRQHandler
-TIMER32_0_IRQHandler
-TIMER32_1_IRQHandler
-SSP0_IRQHandler
-UART_IRQHandler
-USB_IRQHandler
-USB_FIQHandler
-ADC_IRQHandler
-WDT_IRQHandler
-BOD_IRQHandler
-FMC_IRQHandler
-USBWakeup_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- a/vendor/NXP/LPC11U24/cmsis/ARM/sys.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * Setup a fixed single stack/heap memory model, 
- *  between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/vendor/NXP/LPC11U24/cmsis/GCC_ARM/LPC11U24.ld	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,154 +0,0 @@
-/* Linker script for mbed LPC1768 */
-
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
-  RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0xF40
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- * 
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .text :
-    {
-        KEEP(*(.isr_vector))
-        *(.text.Reset_Handler)
-        *(.text.SystemInit)
-        
-        /* Only vectors and code running at reset are safe to be in first 512
-           bytes since RAM can be mapped into this area for RAM based interrupt
-           vectors. */
-        . = 0x00000200;
-        *(.text*)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        KEEP(*(.eh_frame*))
-    } > FLASH
-
-    .ARM.extab : 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
-    __exidx_end = .;
-
-    __etext = .;
-        
-    .data : AT (__etext)
-    {
-        __data_start__ = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE (__fini_array_end = .);
-
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-
-    } > RAM
-
-    .bss :
-    {
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > RAM
-    
-    .heap :
-    {
-        __end__ = .;
-        end = __end__;
-        *(.heap*)
-        __HeapLimit = .;
-    } > RAM
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy :
-    {
-        *(.stack)
-    } > RAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
-

--- a/vendor/NXP/LPC11U24/cmsis/GCC_ARM/startup_LPC11xx.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,213 +0,0 @@
-/* File: startup_ARMCM0.S
- * Purpose: startup file for Cortex-M0 devices. Should use with 
- *   GCC for ARM Embedded Processors
- * Version: V1.2
- * Date: 15 Nov 2011
- * 
- * Copyright (c) 2011, ARM Limited
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
-    * Redistributions of source code must retain the above copyright
-      notice, this list of conditions and the following disclaimer.
-    * Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-    * Neither the name of the ARM Limited nor the
-      names of its contributors may be used to endorse or promote products
-      derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-    .syntax unified
-    .arch armv6-m
-
-/* Memory Model
-   The HEAP starts at the end of the DATA section and grows upward.
-   
-   The STACK starts at the end of the RAM and grows downward.
-   
-   The HEAP and stack STACK are only checked at compile time:
-   (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
-   
-   This is just a check for the bare minimum for the Heap+Stack area before
-   aborting compilation, it is not the run time limit:
-   Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
- */
-    .section .stack
-    .align 3
-#ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
-#else
-    .equ    Stack_Size, 0x80
-#endif
-    .globl    __StackTop
-    .globl    __StackLimit
-__StackLimit:
-    .space    Stack_Size
-    .size __StackLimit, . - __StackLimit
-__StackTop:
-    .size __StackTop, . - __StackTop
-
-    .section .heap
-    .align 3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0x80
-#endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
-__HeapBase:
-    .space    Heap_Size
-    .size __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size __HeapLimit, . - __HeapLimit
-    
-    .section .isr_vector
-    .align 2
-    .globl __isr_vector
-__isr_vector:
-    .long    __StackTop            /* Top of Stack */
-    .long    Reset_Handler         /* Reset Handler */
-    .long    NMI_Handler           /* NMI Handler */
-    .long    HardFault_Handler     /* Hard Fault Handler */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    SVC_Handler           /* SVCall Handler */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    PendSV_Handler        /* PendSV Handler */
-    .long    SysTick_Handler       /* SysTick Handler */
-
-/* LPC11xx interrupts */
-    .long   WAKEUP_IRQHandler         /* 16  0 Wake-up on  pin  PIO0_0             */
-    .long   WAKEUP_IRQHandler         /* 17  1 Wake-up on  pin  PIO0_1             */
-    .long   WAKEUP_IRQHandler         /* 18  2 Wake-up on  pin  PIO0_2             */
-    .long   WAKEUP_IRQHandler         /* 19  3 Wake-up on  pin  PIO0_3             */
-    .long   WAKEUP_IRQHandler         /* 20  4 Wake-up on  pin  PIO0_4             */
-    .long   WAKEUP_IRQHandler         /* 21  5 Wake-up on  pin  PIO0_5             */
-    .long   WAKEUP_IRQHandler         /* 22  6 Wake-up on  pin  PIO0_6             */
-    .long   WAKEUP_IRQHandler         /* 23  7 Wake-up on  pin  PIO0_7             */
-    .long   WAKEUP_IRQHandler         /* 24  8 Wake-up on  pin  PIO0_8             */
-    .long   WAKEUP_IRQHandler         /* 25  9 Wake-up on  pin  PIO0_9             */
-    .long   WAKEUP_IRQHandler         /* 26 10 Wake-up on  pin  PIO0_10            */
-    .long   WAKEUP_IRQHandler         /* 27 11 Wake-up on  pin  PIO0_11            */
-    .long   WAKEUP_IRQHandler         /* 28 12 Wake-up on  pin  PIO1_0             */
-    .long   Default_Handler           /* 29 13                                     */
-    .long   SSP1_IRQHandler           /* 30 14 SSP1                                */
-    .long   I2C_IRQHandler            /* 31 15 I2C0 SI (state change)              */
-    .long   TIMER16_0_IRQHandler      /* 32 16 CT16B0 16 bit timer 0               */
-    .long   TIMER16_1_IRQHandler      /* 33 17 CT16B1 16 bit timer 1               */
-    .long   TIMER32_0_IRQHandler      /* 34 18 CT32B0 32 bit timer 0               */
-    .long   TIMER32_1_IRQHandler      /* 35 19 CT32B1 32 bit timer 1               */
-    .long   SSP0_IRQHandler           /* 36 20 SSP                                 */
-    .long   UART_IRQHandler           /* 37 21 UART                                */
-    .long   Default_Handler           /* 38 22                                     */
-    .long   Default_Handler           /* 39 23                                     */
-    .long   ADC_IRQHandler            /* 40 24 ADC end of conversion               */
-    .long   WDT_IRQHandler            /* 41 25 Watchdog interrupt (WDINT)          */
-    .long   BOD_IRQHandler            /* 42 26 BOD Brown-out detect                */
-    .long   Default_Handler           /* 43 27                                     */
-    .long   PIOINT3_IRQHandler        /* 44 28 PIO_3  GPIO interrupt status of port 3 */
-    .long   PIOINT2_IRQHandler        /* 45 29 PIO_2  GPIO interrupt status of port 2 */
-    .long   PIOINT1_IRQHandler        /* 46 30 PIO_1  GPIO interrupt status of port 1 */
-    .long   PIOINT0_IRQHandler        /* 47 31 PIO_0  GPIO interrupt status of port 0 */
-    
-    .size    __isr_vector, . - __isr_vector
-
-    .section .text.Reset_Handler
-    .thumb
-    .thumb_func
-    .align 2
-    .globl    Reset_Handler
-    .type    Reset_Handler, %function
-Reset_Handler:
-/*     Loop to copy data from read only memory to RAM. The ranges
- *      of copy from/to are specified by following symbols evaluated in 
- *      linker script.
- *      __etext: End of code section, i.e., begin of data sections to copy from.
- *      __data_start__/__data_end__: RAM address range that data should be
- *      copied to. Both must be aligned to 4 bytes boundary.  */
-
-    ldr    r1, =__etext
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
-
-    subs    r3, r2
-    ble    .flash_to_ram_loop_end
-
-    movs    r4, 0
-.flash_to_ram_loop:
-    ldr    r0, [r1,r4]
-    str    r0, [r2,r4]
-    adds    r4, 4
-    cmp    r4, r3
-    blt    .flash_to_ram_loop
-.flash_to_ram_loop_end:
-
-    ldr    r0, =SystemInit
-    blx    r0
-    ldr    r0, =_start
-    bx    r0
-    .pool
-    .size Reset_Handler, . - Reset_Handler
-    
-    .text
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-    .macro    def_default_handler    handler_name
-    .align 1
-    .thumb_func
-    .weak    \handler_name
-    .type    \handler_name, %function
-\handler_name :
-    b    .
-    .size    \handler_name, . - \handler_name
-    .endm
-    
-    def_default_handler    NMI_Handler
-    def_default_handler    HardFault_Handler
-    def_default_handler    SVC_Handler
-    def_default_handler    PendSV_Handler
-    def_default_handler    SysTick_Handler
-    def_default_handler    Default_Handler
-    
-    def_default_handler    WAKEUP_IRQHandler
-    def_default_handler    SSP1_IRQHandler
-    def_default_handler    I2C_IRQHandler
-    def_default_handler    TIMER16_0_IRQHandler
-    def_default_handler    TIMER16_1_IRQHandler
-    def_default_handler    TIMER32_0_IRQHandler
-    def_default_handler    TIMER32_1_IRQHandler
-    def_default_handler    SSP0_IRQHandler
-    def_default_handler    UART_IRQHandler
-    def_default_handler    ADC_IRQHandler
-    def_default_handler    WDT_IRQHandler
-    def_default_handler    BOD_IRQHandler
-    def_default_handler    PIOINT3_IRQHandler
-    def_default_handler    PIOINT2_IRQHandler
-    def_default_handler    PIOINT1_IRQHandler
-    def_default_handler    PIOINT0_IRQHandler
-
-    .weak    DEF_IRQHandler
-    .set    DEF_IRQHandler, Default_Handler
-
-    .end
-

--- a/vendor/NXP/LPC11U24/cmsis/GCC_CR/LPC11U24.ld	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,152 +0,0 @@
-/* mbed - LPC11U24 linker script
- * Based linker script generated by Code Red Technologies Red Suite 4.1
- */
-GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32k */
-  RamLoc4 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0xF40 /* 4k */
-  RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
-}
-  /* Define a symbol for the top of each memory region */
-  __top_MFlash32 = 0x0 + 0x8000;
-  __top_RamLoc4 = 0x10000000 + 0x1000;
-  __top_RamUsb2 = 0x20004000 + 0x800;
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-
-    /* MAIN TEXT SECTION */ 
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        KEEP(*(.isr_vector))
-        
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data)) ;
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2)) ;
-        LONG(  SIZEOF(.data_RAM2));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-        
-
-        *(.after_vectors*)
-        
-        *(.text*)
-        *(.rodata .rodata.*)
-        . = ALIGN(4);
-        
-        /* C++ constructors etc */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-        
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-        
-        KEEP(*(.fini));
-        
-        . = ALIGN(0x4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-        
-        . = ALIGN(0x4);
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-        /* End C++ */
-    } > MFlash32
-
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this.
-     */
-    .ARM.extab : ALIGN(4)
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlash32
-    __exidx_start = .;
-    
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > MFlash32
-    __exidx_end = .;
-    
-    _etext = .;
-        
-    
-    .data_RAM2 : ALIGN(4)
-    {
-       FILL(0xff)
-        *(.data.$RAM2*)
-        *(.data.$RamUsb2*)
-       . = ALIGN(4) ;
-    } > RamUsb2 AT>MFlash32
-    
-    /* MAIN DATA SECTION */
-
-    .uninit_RESERVED : ALIGN(4)
-    {
-        KEEP(*(.bss.$RESERVED*))
-    } > RamLoc4
-
-    .data : ALIGN(4)
-    {
-        FILL(0xff)
-        _data = .;
-        *(vtable)
-        *(.data*)
-        . = ALIGN(4) ;
-        _edata = .;
-    } > RamLoc4 AT>MFlash32
-
-    
-    .bss_RAM2 : ALIGN(4)
-    {
-        *(.bss.$RAM2*)
-        *(.bss.$RamUsb2*)
-       . = ALIGN(4) ;
-    } > RamUsb2
-
-    /* MAIN BSS SECTION */
-    .bss : ALIGN(4)
-    {
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc4
-    
-    PROVIDE(_pvHeapStart = .);
-    PROVIDE(_vStackTop = __top_RamLoc4 - 0);
-}

--- a/vendor/NXP/LPC11U24/cmsis/GCC_CR/startup_LPC11xx.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,161 +0,0 @@
-extern "C" {
-
-#include "LPC11Uxx.h"
-
-#define WEAK          __attribute__ ((weak))
-#define ALIAS(f)      __attribute__ ((weak, alias (#f)))
-#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))
-
-     void ResetISR            (void);
-WEAK void NMI_Handler         (void);
-WEAK void HardFault_Handler   (void);
-WEAK void SVCall_Handler      (void);
-WEAK void PendSV_Handler      (void);
-WEAK void SysTick_Handler     (void);
-WEAK void IntDefaultHandler   (void);
-     void FLEX_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
-     void FLEX_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
-     void FLEX_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
-     void FLEX_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
-     void FLEX_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
-     void FLEX_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
-     void FLEX_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
-     void FLEX_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
-     void GINT0_IRQHandler    (void) ALIAS(IntDefaultHandler);
-     void GINT1_IRQHandler    (void) ALIAS(IntDefaultHandler);
-     void SSP1_IRQHandler     (void) ALIAS(IntDefaultHandler);
-     void I2C_IRQHandler      (void) ALIAS(IntDefaultHandler);
-     void TIMER16_0_IRQHandler(void) ALIAS(IntDefaultHandler);
-     void TIMER16_1_IRQHandler(void) ALIAS(IntDefaultHandler);
-     void TIMER32_0_IRQHandler(void) ALIAS(IntDefaultHandler);
-     void TIMER32_1_IRQHandler(void) ALIAS(IntDefaultHandler);
-     void SSP0_IRQHandler     (void) ALIAS(IntDefaultHandler);
-     void UART_IRQHandler     (void) ALIAS(IntDefaultHandler);
-     void USB_IRQHandler      (void) ALIAS(IntDefaultHandler);
-     void USB_FIQHandler      (void) ALIAS(IntDefaultHandler);
-     void ADC_IRQHandler      (void) ALIAS(IntDefaultHandler);
-     void WDT_IRQHandler      (void) ALIAS(IntDefaultHandler);
-     void BOD_IRQHandler      (void) ALIAS(IntDefaultHandler);
-     void FMC_IRQHandler      (void) ALIAS(IntDefaultHandler);
-     void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
-
-extern void __libc_init_array(void);
-extern int main(void);
-extern void _vStackTop(void);
-
-extern void (* const g_pfnVectors[])(void);
-__attribute__ ((section(".isr_vector")))
-void (* const g_pfnVectors[])(void) = {
-    &_vStackTop,
-    ResetISR,
-    NMI_Handler,
-    HardFault_Handler,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    0,
-    SVCall_Handler,
-    0,
-    0,
-    PendSV_Handler,
-    SysTick_Handler,
-    FLEX_INT0_IRQHandler,
-    FLEX_INT1_IRQHandler,
-    FLEX_INT2_IRQHandler,
-    FLEX_INT3_IRQHandler,
-    FLEX_INT4_IRQHandler,
-    FLEX_INT5_IRQHandler,
-    FLEX_INT6_IRQHandler,
-    FLEX_INT7_IRQHandler,
-    GINT0_IRQHandler,
-    GINT1_IRQHandler,
-    0,
-    0,
-    0,
-    0,
-    SSP1_IRQHandler,
-    I2C_IRQHandler,
-    TIMER16_0_IRQHandler,
-    TIMER16_1_IRQHandler,
-    TIMER32_0_IRQHandler,
-    TIMER32_1_IRQHandler,
-    SSP0_IRQHandler,
-    UART_IRQHandler,
-    USB_IRQHandler,
-    USB_FIQHandler,
-    ADC_IRQHandler,
-    WDT_IRQHandler,
-    BOD_IRQHandler,
-    FMC_IRQHandler,
-    0,
-    0,
-    USBWakeup_IRQHandler,
-    0,
-};
-
-AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
-    unsigned int *pulDest = (unsigned int*) start;
-    unsigned int *pulSrc = (unsigned int*) romstart;
-    unsigned int loop;
-    for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
-}
-
-AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
-    unsigned int *pulDest = (unsigned int*) start;
-    unsigned int loop;
-    for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
-}
-
-extern unsigned int __data_section_table;
-extern unsigned int __data_section_table_end;
-extern unsigned int __bss_section_table_end;
-
-AFTER_VECTORS void ResetISR(void) {
-    unsigned int LoadAddr, ExeAddr, SectionLen;
-    unsigned int *SectionTableAddr;
-    
-    // Data Init
-    SectionTableAddr = &__data_section_table;
-    while (SectionTableAddr < &__data_section_table_end) {
-        LoadAddr = *SectionTableAddr++;
-        ExeAddr = *SectionTableAddr++;
-        SectionLen = *SectionTableAddr++;
-        data_init(LoadAddr, ExeAddr, SectionLen);
-    }
-    
-    // BSS Init
-    while (SectionTableAddr < &__bss_section_table_end) {
-        ExeAddr = *SectionTableAddr++;
-        SectionLen = *SectionTableAddr++;
-        bss_init(ExeAddr, SectionLen);
-    }
-    
-    SystemInit();
-    __libc_init_array();
-    main();
-    while (1) {;}
-}
-
-AFTER_VECTORS void NMI_Handler      (void) {while(1){}}
-AFTER_VECTORS void HardFault_Handler(void) {while(1){}}
-AFTER_VECTORS void SVCall_Handler   (void) {while(1){}}
-AFTER_VECTORS void PendSV_Handler   (void) {while(1){}}
-AFTER_VECTORS void SysTick_Handler  (void) {while(1){}}
-AFTER_VECTORS void IntDefaultHandler(void) {while(1){}}
-
-#include <stdlib.h>
-
-void *operator new  (size_t size) {return malloc(size);}
-void *operator new[](size_t size) {return malloc(size);}
-
-void operator delete  (void *p) {free(p);}
-void operator delete[](void *p) {free(p);}
-
-int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {
-    return 0;
-}
-
-}

--- a/vendor/NXP/LPC11U24/cmsis/GCC_CS/LPC11U24.ld	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,206 +0,0 @@
-/* Linker script for mbed LPC1768
- *
- * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
- * BugURL:https://support.codesourcery.com/GNUToolchain/
- *
- *  Copyright 2007 CodeSourcery.
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply. */
-
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-ENTRY(__cs3_reset_cortex_m)
-SEARCH_DIR(.)
-
-/*
-ram ORIGIN: 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
-ram LENGTH: 8KB - 0xC0 = 0xF40
-*/
-MEMORY
-{
-  rom (rx)  : ORIGIN = 0x00000000, LENGTH = 32K
-  
-  ram (rwx) : ORIGIN = 0x100000C0, LENGTH = 0xF40
-}
-
-/* These force the linker to search for particular symbols from
- * the start of the link process and thus ensure the user's
- * overrides are picked up
- */
-EXTERN(__cs3_reset_cortex_m)
-EXTERN(__cs3_interrupt_vector_cortex_m)
-EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
-
-PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
-PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
-PROVIDE(__cs3_heap_start = _end);
-PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
-
-SECTIONS
-{
-  .text :
-  {
-    CREATE_OBJECT_SYMBOLS
-    __cs3_region_start_rom = .;
-    *(.cs3.region-head.rom)
-    __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
-    *(.cs3.interrupt_vector)
-    /* Make sure we pulled in an interrupt vector.  */
-    ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
-    *(.rom)
-    *(.rom.b)
-
-    __cs3_reset = __cs3_reset_cortex_m;
-    *(.cs3.reset)
-    /* Make sure we pulled in some reset code.  */
-    ASSERT (. != __cs3_reset, "No reset code");
-
-    *(.text .text.* .gnu.linkonce.t.*)
-    *(.plt)
-    *(.gnu.warning)
-    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
-
-    *(.rodata .rodata.* .gnu.linkonce.r.*)
-
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-    *(.gcc_except_table)
-    *(.eh_frame_hdr)
-    *(.eh_frame)
-
-    . = ALIGN(4);
-    KEEP(*(.init))
-
-    . = ALIGN(4);
-    __preinit_array_start = .;
-    KEEP (*(.preinit_array))
-    __preinit_array_end = .;
-
-    . = ALIGN(4);
-    __init_array_start = .;
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array))
-    __init_array_end = .;
-
-    . = ALIGN(0x4);
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*crtend.o(.ctors))
-
-    . = ALIGN(4);
-    KEEP(*(.fini))
-
-    . = ALIGN(4);
-    __fini_array_start = .;
-    KEEP (*(.fini_array))
-    KEEP (*(SORT(.fini_array.*)))
-    __fini_array_end = .;
-
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*crtend.o(.dtors))
-
-    . = ALIGN(4);
-    __cs3_regions = .;
-    LONG (0)
-    LONG (__cs3_region_init_ram)
-    LONG (__cs3_region_start_ram)
-    LONG (__cs3_region_init_size_ram)
-    LONG (__cs3_region_zero_size_ram)
-  }
-
-  /* .ARM.exidx is sorted, so has to go in its own output section.  */
-  __exidx_start = .;
-  .ARM.exidx :
-  {
-    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-  } >rom
-  __exidx_end = .;
-  .text.align :
-  {
-    . = ALIGN(8);
-    _etext = .;
-  } >rom
-  __cs3_region_size_rom = LENGTH(rom);
-  __cs3_region_num = 1;
-  
-  .data :
-  {
-    __cs3_region_start_ram = .;
-    *(.cs3.region-head.ram)
-    KEEP(*(.jcr))
-    *(.got.plt) *(.got)
-    *(.shdata)
-    *(.data .data.* .gnu.linkonce.d.*)
-    *(.ram)
-    . = ALIGN (8);
-    _edata = .;
-  } >ram AT>rom
-  .bss :
-  {
-    *(.shbss)
-    *(.bss .bss.* .gnu.linkonce.b.*)
-    *(COMMON)
-    *(.ram.b)
-    . = ALIGN (8);
-    _end = .;
-    __end = .;
-  } >ram AT>rom
-  
-  .heap (NOLOAD) :
-  {
-    *(.heap)
-  } >ram
-  .stack (__cs3_stack - __cs3_stack_size) (NOLOAD):
-  {
-    *(.stack)
-    _estack = .;
-    PROVIDE(estack = .);
-  } >ram
-
-  __cs3_region_init_ram = LOADADDR (.data);
-  __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
-  __cs3_region_zero_size_ram = _end - _edata;
-  __cs3_region_size_ram = LENGTH(ram);
-  __cs3_region_num = 1;
-
-  .stab 0 (NOLOAD) : { *(.stab) }
-  .stabstr 0 (NOLOAD) : { *(.stabstr) }
-  /* DWARF debug sections.
-   * Symbols in the DWARF debugging sections are relative to the beginning
-   * of the section so we begin them at 0.  */
-  /* DWARF 1 */
-  .debug          0 : { *(.debug) }
-  .line           0 : { *(.line) }
-  /* GNU DWARF 1 extensions */
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
-  .debug_sfnames  0 : { *(.debug_sfnames) }
-  /* DWARF 1.1 and DWARF 2 */
-  .debug_aranges  0 : { *(.debug_aranges) }
-  .debug_pubnames 0 : { *(.debug_pubnames) }
-  /* DWARF 2 */
-  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-  .debug_abbrev   0 : { *(.debug_abbrev) }
-  .debug_line     0 : { *(.debug_line) }
-  .debug_frame    0 : { *(.debug_frame) }
-  .debug_str      0 : { *(.debug_str) }
-  .debug_loc      0 : { *(.debug_loc) }
-  .debug_macinfo  0 : { *(.debug_macinfo) }
-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
-  .debug_funcnames 0 : { *(.debug_funcnames) }
-  .debug_typenames 0 : { *(.debug_typenames) }
-  .debug_varnames  0 : { *(.debug_varnames) }
-
-  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
-  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
-  /DISCARD/ : { *(.note.GNU-stack) }
-}

--- a/vendor/NXP/LPC11U24/cmsis/GCC_CS/startup_LPC11xx.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,112 +0,0 @@
-    .equ    Stack_Size, 0x80
-    .section ".stack", "w"
-    .align  3
-    .globl  __cs3_stack_mem
-    .globl  __cs3_stack_size
-__cs3_stack_mem:
-    .if     Stack_Size
-    .space  Stack_Size
-    .endif
-    .size   __cs3_stack_mem,  . - __cs3_stack_mem
-    .set    __cs3_stack_size, . - __cs3_stack_mem
-
-    .equ    Heap_Size,  0x80
-    .section ".heap", "w"
-    .align  3
-    .globl  __cs3_heap_start
-    .globl  __cs3_heap_end
-__cs3_heap_start:
-    .if     Heap_Size
-    .space  Heap_Size
-    .endif
-__cs3_heap_end:
-
-    .section ".cs3.interrupt_vector"
-    .globl  __cs3_interrupt_vector_cortex_m
-    .type   __cs3_interrupt_vector_cortex_m, %object
-
-__cs3_interrupt_vector_cortex_m:
-    .long   __cs3_stack
-    .long   __cs3_reset
-    .long   NMI_Handler
-    .long   HardFault_Handler
-    .long   0
-    .long   0
-    .long   0
-    .long   0
-    .long   0
-    .long   0
-    .long   0
-    .long   SVC_Handler
-    .long   0
-    .long   0
-    .long   PendSV_Handler
-    .long   SysTick_Handler
-
-    .long   DEF_IRQHandler
-
-    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
-
-    .thumb
-
-    .section .cs3.reset,"x",%progbits
-    .thumb_func
-    .globl  __cs3_reset_cortex_m
-    .type   __cs3_reset_cortex_m, %function
-__cs3_reset_cortex_m:
-    .fnstart
-    LDR     R0, =SystemInit
-    BLX     R0
-    LDR     R0,=__cs3_start_c
-    BX      R0
-    .pool
-    .cantunwind
-    .fnend
-    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
-
-    .section ".text"
-
-    .weak   NMI_Handler
-    .type   NMI_Handler, %function
-NMI_Handler:
-    B       .
-    .size   NMI_Handler, . - NMI_Handler
-
-    .weak   HardFault_Handler
-    .type   HardFault_Handler, %function
-HardFault_Handler:
-    B       .
-    .size   HardFault_Handler, . - HardFault_Handler
-
-    .weak   SVC_Handler
-    .type   SVC_Handler, %function
-SVC_Handler:
-    B       .
-    .size   SVC_Handler, . - SVC_Handler
-
-    .weak   PendSV_Handler
-    .type   PendSV_Handler, %function
-PendSV_Handler:
-    B       .
-    .size   PendSV_Handler, . - PendSV_Handler
-
-    .weak   SysTick_Handler
-    .type   SysTick_Handler, %function
-SysTick_Handler:
-    B       .
-    .size   SysTick_Handler, . - SysTick_Handler
-
-    .globl  Default_Handler
-    .type   Default_Handler, %function
-Default_Handler:
-    B       .
-    .size   Default_Handler, . - Default_Handler
-
-    .macro  IRQ handler
-    .weak   \handler
-    .set    \handler, Default_Handler
-    .endm
-
-    IRQ     DEF_IRQHandler
-
-    .end

--- a/vendor/NXP/LPC11U24/cmsis/GCC_CS/sys.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,79 +0,0 @@
-#include "cmsis.h"
-#include <sys/types.h>
-#include <errno.h>
-
-extern "C" {
-
-struct SCS3Regions {
-    unsigned long   Dummy;
-    unsigned long*  InitRam;
-    unsigned long*  StartRam;
-    unsigned long   InitSizeRam;
-    unsigned long   ZeroSizeRam;
-};
-
-extern unsigned long __cs3_regions;
-extern unsigned long __cs3_heap_start;
-
-int  main(void);
-void __libc_init_array(void);
-void exit(int ErrorCode);
-
-static void *heap_pointer = NULL;
-
-void __cs3_start_c(void) {
-    static SCS3Regions* pCS3Regions = (SCS3Regions*)&__cs3_regions;
-    unsigned long* pulDest;
-    unsigned long* pulSrc;
-    unsigned long  ByteCount;
-    unsigned long  i;
-    
-    pulSrc = pCS3Regions->InitRam;
-    pulDest = pCS3Regions->StartRam;
-    ByteCount = pCS3Regions->InitSizeRam;
-    if (pulSrc != pulDest) {
-        for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
-            *(pulDest++) = *(pulSrc++);
-        }
-    } else {
-        pulDest = (unsigned long*)(void*)((char*)pulDest + ByteCount);
-    }
-    
-    ByteCount = pCS3Regions->ZeroSizeRam;
-    for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
-        *(pulDest++) = 0;
-    }
-    
-    heap_pointer = &__cs3_heap_start;
-     __libc_init_array();
-    exit(main());
-}
-
-int _kill(int pid, int sig) {
-    errno = EINVAL;
-    return -1;
-}
-
-void _exit(int status) {
-    exit(status);
-}
-
-int _getpid(void) {
-    return 1;
-}
-
-void *_sbrk(unsigned int incr) {
-    void *mem;
-    
-    unsigned int next = ((((unsigned int)heap_pointer + incr) + 7) & ~7);
-    if (next > __get_MSP()) {
-        mem = NULL;
-    } else {
-        mem = (void *)heap_pointer;
-    }
-    heap_pointer = (void *)next;
-    
-    return mem;
-}
-
-}

--- a/vendor/NXP/LPC11U24/cmsis/LPC11Uxx.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,670 +0,0 @@
-
-/****************************************************************************************************//**
- * @file     LPC11Uxx.h
- *
- *
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
- *           default LPC11Uxx Device Series
- *
- * @version  V0.1
- * @date     21. March 2011
- *
- * @note     Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
- *
- *           from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
- *           created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
- *
- *******************************************************************************************************/
-
-// ################################################################################
-// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000
-// ################################################################################
-
-/** @addtogroup NXP
-  * @{
-  */
-
-/** @addtogroup LPC11Uxx
-  * @{
-  */
-
-#ifndef __LPC11UXX_H__
-#define __LPC11UXX_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-
-#if defined ( __CC_ARM   )
-  #pragma anon_unions
-#endif
-
- /* Interrupt Number Definition */
-
-typedef enum {
-// -------------------------  Cortex-M0 Processor Exceptions Numbers  -----------------------------
-  Reset_IRQn                        = -15,  /*!<   1  Reset Vector, invoked on Power up and warm reset */
-  NonMaskableInt_IRQn               = -14,  /*!<   2  Non maskable Interrupt, cannot be stopped or preempted */
-  HardFault_IRQn                    = -13,  /*!<   3  Hard Fault, all classes of Fault */
-  SVCall_IRQn                       = -5,   /*!<  11  System Service Call via SVC instruction */
-  DebugMonitor_IRQn                 = -4,   /*!<  12  Debug Monitor                    */
-  PendSV_IRQn                       = -2,   /*!<  14  Pendable request for system service */
-  SysTick_IRQn                      = -1,   /*!<  15  System Tick Timer                */
-// ---------------------------  LPC11Uxx Specific Interrupt Numbers  ------------------------------
-FLEX_INT0_IRQn                = 0,        /*!< All I/O pins can be routed to below 8 interrupts. */
-  FLEX_INT1_IRQn                = 1,
-  FLEX_INT2_IRQn                = 2,
-  FLEX_INT3_IRQn                = 3,
-  FLEX_INT4_IRQn                = 4,   
-  FLEX_INT5_IRQn                = 5,        
-  FLEX_INT6_IRQn                = 6,        
-  FLEX_INT7_IRQn                = 7,        
-  GINT0_IRQn                    = 8,        /*!< Grouped Interrupt 0                              */
-  GINT1_IRQn                    = 9,        /*!< Grouped Interrupt 1                              */
-  Reserved0_IRQn                = 10,       /*!< Reserved Interrupt                               */
-  Reserved1_IRQn                = 11,       
-  Reserved2_IRQn                = 12,       
-  Reserved3_IRQn                = 13,       
-  SSP1_IRQn                     = 14,       /*!< SSP1 Interrupt                                   */
-  I2C_IRQn                      = 15,       /*!< I2C Interrupt                                    */
-  TIMER_16_0_IRQn               = 16,       /*!< 16-bit Timer0 Interrupt                          */
-  TIMER_16_1_IRQn               = 17,       /*!< 16-bit Timer1 Interrupt                          */
-  TIMER_32_0_IRQn               = 18,       /*!< 32-bit Timer0 Interrupt                          */
-  TIMER_32_1_IRQn               = 19,       /*!< 32-bit Timer1 Interrupt                          */
-  SSP0_IRQn                     = 20,       /*!< SSP0 Interrupt                                   */
-  UART_IRQn                     = 21,       /*!< UART Interrupt                                   */
-  USB_IRQn                      = 22,       /*!< USB IRQ Interrupt                                */
-  USB_FIQn                      = 23,       /*!< USB FIQ Interrupt                                */
-  ADC_IRQn                      = 24,       /*!< A/D Converter Interrupt                          */
-  WDT_IRQn                      = 25,       /*!< Watchdog timer Interrupt                         */  
-  BOD_IRQn                      = 26,       /*!< Brown Out Detect(BOD) Interrupt                  */
-  FMC_IRQn                      = 27,       /*!< Flash Memory Controller Interrupt                */
-  Reserved4_IRQn                = 28,       /*!< Reserved Interrupt                               */
-  Reserved5_IRQn                = 29,       /*!< Reserved Interrupt                               */
-  USBWakeup_IRQn                = 30,       /*!< USB wakeup Interrupt                             */
-  Reserved6_IRQn                = 31,       /*!< Reserved Interrupt                               */
-} IRQn_Type;
-
-
-/** @addtogroup Configuration_of_CMSIS
-  * @{
-  */
-
-/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
-
-#define __MPU_PRESENT             0         /*!< MPU present or not                    */
-#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used */
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include "core_cm0.h"                       /*!< Cortex-M0 processor and core peripherals */
-#include "system_LPC11Uxx.h"                /*!< LPC11Uxx System                       */
-
-/** @addtogroup Device_Peripheral_Registers
-  * @{
-  */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          I2C                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3  (I2C)
-  */
-
-typedef struct {                            /*!< (@ 0x40000000) I2C Structure          */
-  __IO uint32_t CONSET;                     /*!< (@ 0x40000000) I2C Control Set Register */
-  __I  uint32_t STAT;                       /*!< (@ 0x40000004) I2C Status Register */
-  __IO uint32_t DAT;                        /*!< (@ 0x40000008) I2C Data Register.  */
-  __IO uint32_t ADR0;                       /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
-  __IO uint32_t SCLH;                       /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
-  __IO uint32_t SCLL;                       /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
-  __IO uint32_t CONCLR;                     /*!< (@ 0x40000018) I2C Control Clear Register*/
-  __IO uint32_t MMCTRL;                     /*!< (@ 0x4000001C) Monitor mode control register*/
-  __IO uint32_t ADR1;                       /*!< (@ 0x40000020) I2C Slave Address Register 1*/
-  __IO uint32_t ADR2;                       /*!< (@ 0x40000024) I2C Slave Address Register 2*/
-  __IO uint32_t ADR3;                       /*!< (@ 0x40000028) I2C Slave Address Register 3*/
-  __I  uint32_t DATA_BUFFER;                /*!< (@ 0x4000002C) Data buffer register */
-union{
-  __IO uint32_t MASK[4];                    /*!< (@ 0x40000030) I2C Slave address mask register */
-  struct{
-  __IO uint32_t MASK0;
-  __IO uint32_t MASK1;
-  __IO uint32_t MASK2;
-  __IO uint32_t MASK3;
-  };
-  };
-} LPC_I2C_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         WWDT                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3  (WWDT)
-  */
-
-typedef struct {                            /*!< (@ 0x40004000) WWDT Structure         */
-  __IO uint32_t MOD;                        /*!< (@ 0x40004000) Watchdog mode register*/
-  __IO uint32_t TC;                         /*!< (@ 0x40004004) Watchdog timer constant register */
-  __IO uint32_t FEED;                       /*!< (@ 0x40004008) Watchdog feed sequence register */
-  __I  uint32_t TV;                         /*!< (@ 0x4000400C) Watchdog timer value register */
-  __IO uint32_t CLKSEL;                     /*!< (@ 0x40004010) Watchdog clock select register. */
-  __IO uint32_t WARNINT;                    /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
-  __IO uint32_t WINDOW;                     /*!< (@ 0x40004018) Watchdog Window compare value. */
-} LPC_WWDT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         USART                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3  (USART)
-  */
-
-typedef struct {                            /*!< (@ 0x40008000) USART Structure        */
-  
-  union {
-    __IO uint32_t DLL;                      /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
-    __O  uint32_t THR;                      /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
-    __I  uint32_t RBR;                      /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
-  };
-  
-  union {
-    __IO uint32_t IER;                      /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
-    __IO uint32_t DLM;                      /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
-  };
-  
-  union {
-    __O  uint32_t FCR;                      /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
-    __I  uint32_t IIR;                      /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
-  };
-  __IO uint32_t LCR;                        /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
-  __IO uint32_t MCR;                        /*!< (@ 0x40008010) Modem Control Register. */
-  __I  uint32_t LSR;                        /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
-  __I  uint32_t MSR;                        /*!< (@ 0x40008018) Modem Status Register. */
-  __IO uint32_t SCR;                        /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
-  __IO uint32_t ACR;                        /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
-  __IO uint32_t ICR;                        /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
-  __IO uint32_t FDR;                        /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
-  __IO uint32_t OSR;                        /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
-  __IO uint32_t TER;                        /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
-  __I  uint32_t RESERVED0[3];
-  __IO uint32_t HDEN;                       /*!< (@ 0x40008040) Half duplex enable register. */
-  __I  uint32_t RESERVED1;
-  __IO uint32_t SCICTRL;                    /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
-  __IO uint32_t RS485CTRL;                  /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
-  __IO uint32_t RS485ADRMATCH;              /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
-  __IO uint32_t RS485DLY;                   /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
-  __IO uint32_t SYNCCTRL; 
-} LPC_USART_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        Timer                                       -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3  
-  */
-
-typedef struct {                            /*!< (@ 0x40014000) CT32B0 Structure        */
-  __IO uint32_t IR;                         /*!< (@ 0x40014000) Interrupt Register      */
-  __IO uint32_t TCR;                        /*!< (@ 0x40014004) Timer Control Register  */
-  __IO uint32_t TC;                         /*!< (@ 0x40014008) Timer Counter 		*/
-  __IO uint32_t PR;                         /*!< (@ 0x4001400C) Prescale Register  	*/
-  __IO uint32_t PC;                         /*!< (@ 0x40014010) Prescale Counter	 */
-  __IO uint32_t MCR;                        /*!< (@ 0x40014014) Match Control Register */
-  union {
-  __IO uint32_t MR[4];                      /*!< (@ 0x40014018) Match Register */
-  struct{
-  __IO uint32_t MR0;                        /*!< (@ 0x40018018) Match Register. MR0 */
-  __IO uint32_t MR1;                        /*!< (@ 0x4001801C) Match Register. MR1 */
-  __IO uint32_t MR2;                        /*!< (@ 0x40018020) Match Register. MR2 */
-  __IO uint32_t MR3;                        /*!< (@ 0x40018024) Match Register. MR3 */
-  };
-  };
-  __IO uint32_t CCR;                        /*!< (@ 0x40014028) Capture Control Register */
-  union{
-  __I  uint32_t CR[4];                      /*!< (@ 0x4001402C) Capture Register  */
-    struct{
-  __I  uint32_t CR0;			    /*!< (@ 0x4001802C) Capture Register. CR 0 */
-  __I  uint32_t CR1;			    /*!< (@ 0x40018030) Capture Register. CR 1 */
-  __I  uint32_t CR2;			    /*!< (@ 0x40018034) Capture Register. CR 2 */
-  __I  uint32_t CR3;			    /*!< (@ 0x40018038) Capture Register. CR 3 */
-  };
-  };
-__IO uint32_t EMR;                        /*!< (@ 0x4001403C) External Match Register */
-  __I  uint32_t RESERVED0[12];
-  __IO uint32_t CTCR;                       /*!< (@ 0x40014070) Count Control Register */
-  __IO uint32_t PWMC;                       /*!< (@ 0x40014074) PWM Control Register */
-} LPC_CTxxBx_Type;
-
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          ADC                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3  (ADC)
-  */
-
-typedef struct {                            /*!< (@ 0x4001C000) ADC Structure          */
-  __IO uint32_t CR;                         /*!< (@ 0x4001C000) A/D Control Register */
-  __IO uint32_t GDR;                        /*!< (@ 0x4001C004) A/D Global Data Register */
-  __I  uint32_t RESERVED0[1];
-  __IO uint32_t INTEN;                      /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
-  union{
-  __I  uint32_t DR[8];                      /*!< (@ 0x4001C010) A/D Channel Data Register*/
-    struct{
-  __IO uint32_t DR0;                      	/*!< (@ 0x40020010) A/D Channel Data Register 0*/
-  __IO uint32_t DR1;                      	/*!< (@ 0x40020014) A/D Channel Data Register 1*/
-  __IO uint32_t DR2;                      	/*!< (@ 0x40020018) A/D Channel Data Register 2*/
-  __IO uint32_t DR3;                      	/*!< (@ 0x4002001C) A/D Channel Data Register 3*/
-  __IO uint32_t DR4;                      	/*!< (@ 0x40020020) A/D Channel Data Register 4*/
-  __IO uint32_t DR5;                      	/*!< (@ 0x40020024) A/D Channel Data Register 5*/
-  __IO uint32_t DR6;                      	/*!< (@ 0x40020028) A/D Channel Data Register 6*/
-  __IO uint32_t DR7;                      	/*!< (@ 0x4002002C) A/D Channel Data Register 7*/
-  };
-  };
-  __I  uint32_t STAT;                       /*!< (@ 0x4001C030) A/D Status Register.  */
-} LPC_ADC_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          PMU                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3  (PMU)
-  */
-
-typedef struct {                            /*!< (@ 0x40038000) PMU Structure          */
-  __IO uint32_t PCON;                       /*!< (@ 0x40038000) Power control register */
-  union{
-  __IO uint32_t GPREG[4];                   /*!< (@ 0x40038004) General purpose register 0 */
-  struct{
-  __IO uint32_t GPREG0;                   	/*!< (@ 0x40038004) General purpose register 0 */
-  __IO uint32_t GPREG1;                   	/*!< (@ 0x40038008) General purpose register 1 */
-  __IO uint32_t GPREG2;                   	/*!< (@ 0x4003800C) General purpose register 2 */
-  __IO uint32_t GPREG3;                   	/*!< (@ 0x40038010) General purpose register 3 */
-  };
-  };
-} LPC_PMU_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       FLASHCTRL                                      -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3  (FLASHCTRL)
-  */
-
-typedef struct {                            /*!< (@ 0x4003C000) FLASHCTRL Structure    */
-  __I  uint32_t RESERVED0[4];
-  __IO uint32_t FLASHCFG;                   /*!< (@ 0x4003C010) Flash memory access time configuration register */
-  __I  uint32_t RESERVED1[3];
-  __IO uint32_t FMSSTART;                   /*!< (@ 0x4003C020) Signature start address register */
-  __IO uint32_t FMSSTOP;                    /*!< (@ 0x4003C024) Signature stop-address register */
-  __I  uint32_t RESERVED2[1];
-  __I  uint32_t FMSW0;                      /*!< (@ 0x4003C02C) Word 0 [31:0]          */
-  __I  uint32_t FMSW1;                      /*!< (@ 0x4003C030) Word 1 [63:32]         */
-  __I  uint32_t FMSW2;                      /*!< (@ 0x4003C034) Word 2 [95:64]         */
-  __I  uint32_t FMSW3;                      /*!< (@ 0x4003C038) Word 3 [127:96]        */
-  __I  uint32_t RESERVED3[1001];
-  __I  uint32_t FMSTAT;                     /*!< (@ 0x4003CFE0) Signature generation status register */
-  __I  uint32_t RESERVED4[1];
-  __IO uint32_t FMSTATCLR;                  /*!< (@ 0x4003CFE8) Signature generation status clear register */
-} LPC_FLASHCTRL_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                         SSP0/1                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3  (SSP0)
-  */
-
-typedef struct {                            /*!< (@ 0x40040000) SSP0 Structure         */
-  __IO uint32_t CR0;                        /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
-  __IO uint32_t CR1;                        /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
-  __IO uint32_t DR;                         /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
-  __I  uint32_t SR;                         /*!< (@ 0x4004000C) Status Register        */
-  __IO uint32_t CPSR;                       /*!< (@ 0x40040010) Clock Prescale Register */
-  __IO uint32_t IMSC;                       /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
-  __I  uint32_t RIS;                        /*!< (@ 0x40040018) Raw Interrupt Status Register */
-  __I  uint32_t MIS;                        /*!< (@ 0x4004001C) Masked Interrupt Status Register */
-  __IO uint32_t ICR;                        /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
-} LPC_SSPx_Type;
-
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       IOCONFIG                                       -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3  (IOCONFIG)
-  */
-
-typedef struct {                            /*!< (@ 0x40044000) IOCONFIG Structure     */
-  __IO uint32_t RESET_PIO0_0;               /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
-  __IO uint32_t PIO0_1;                     /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
-  __IO uint32_t PIO0_2;                     /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
-  __IO uint32_t PIO0_3;                     /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
-  __IO uint32_t PIO0_4;                     /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
-  __IO uint32_t PIO0_5;                     /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
-  __IO uint32_t PIO0_6;                     /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
-  __IO uint32_t PIO0_7;                     /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
-  __IO uint32_t PIO0_8;                     /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
-  __IO uint32_t PIO0_9;                     /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
-  __IO uint32_t SWCLK_PIO0_10;              /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
-  __IO uint32_t TDI_PIO0_11;                /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
-  __IO uint32_t TMS_PIO0_12;                /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
-  __IO uint32_t TDO_PIO0_13;                /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
-  __IO uint32_t TRST_PIO0_14;               /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
-  __IO uint32_t SWDIO_PIO0_15;              /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
-  __IO uint32_t PIO0_16;                    /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
-  __IO uint32_t PIO0_17;                    /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
-  __IO uint32_t PIO0_18;                    /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
-  __IO uint32_t PIO0_19;                    /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
-  __IO uint32_t PIO0_20;                    /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
-  __IO uint32_t PIO0_21;                    /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
-  __IO uint32_t PIO0_22;                    /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
-  __IO uint32_t PIO0_23;                    /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
-  __IO uint32_t PIO1_0;                 /*!< Offset: 0x060 */
-  __IO uint32_t PIO1_1;         
-  __IO uint32_t PIO1_2;       
-  __IO uint32_t PIO1_3;      
-  __IO uint32_t PIO1_4;                 /*!< Offset: 0x070 */
-  __IO uint32_t PIO1_5;                     /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
-  __IO uint32_t PIO1_6;     
-  __IO uint32_t PIO1_7;       
-  __IO uint32_t PIO1_8;                 /*!< Offset: 0x080 */
-  __IO uint32_t PIO1_9;        
-  __IO uint32_t PIO1_10;        
-  __IO uint32_t PIO1_11;       
-  __IO uint32_t PIO1_12;                /*!< Offset: 0x090 */
-  __IO uint32_t PIO1_13;                    /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
-  __IO uint32_t PIO1_14;                    /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
-  __IO uint32_t PIO1_15;                    /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
-  __IO uint32_t PIO1_16;                    /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
-  __IO uint32_t PIO1_17;
-  __IO uint32_t PIO1_18;
-  __IO uint32_t PIO1_19;                    /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
-  __IO uint32_t PIO1_20;                    /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
-  __IO uint32_t PIO1_21;                    /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
-  __IO uint32_t PIO1_22;                    /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
-  __IO uint32_t PIO1_23;                    /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
-  __IO uint32_t PIO1_24;                    /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
-  __IO uint32_t PIO1_25;                    /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
-  __IO uint32_t PIO1_26;                    /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
-  __IO uint32_t PIO1_27;                    /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
-  __IO uint32_t PIO1_28;                    /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
-  __IO uint32_t PIO1_29;                    /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
-  __IO uint32_t PIO1_30;
-  __IO uint32_t PIO1_31;                    /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
-} LPC_IOCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                        SYSCON                                        -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3  (SYSCON)
-  */
-
-typedef struct {                            /*!< (@ 0x40048000) SYSCON Structure       */
-  __IO uint32_t SYSMEMREMAP;                /*!< (@ 0x40048000) System memory remap    */
-  __IO uint32_t PRESETCTRL;                 /*!< (@ 0x40048004) Peripheral reset control */
-  __IO uint32_t SYSPLLCTRL;                 /*!< (@ 0x40048008) System PLL control     */
-  __I  uint32_t SYSPLLSTAT;                 /*!< (@ 0x4004800C) System PLL status      */
-  __IO uint32_t USBPLLCTRL;                 /*!< (@ 0x40048010) USB PLL control        */
-  __I  uint32_t USBPLLSTAT;                 /*!< (@ 0x40048014) USB PLL status         */
-  __I  uint32_t RESERVED0[2];
-  __IO uint32_t SYSOSCCTRL;                 /*!< (@ 0x40048020) System oscillator control */
-  __IO uint32_t WDTOSCCTRL;                 /*!< (@ 0x40048024) Watchdog oscillator control */
-  __I  uint32_t RESERVED1[2];
-  __IO uint32_t SYSRSTSTAT;                 /*!< (@ 0x40048030) System reset status register */
-  __I  uint32_t RESERVED2[3];
-  __IO uint32_t SYSPLLCLKSEL;               /*!< (@ 0x40048040) System PLL clock source select */
-  __IO uint32_t SYSPLLCLKUEN;               /*!< (@ 0x40048044) System PLL clock source update enable */
-  __IO uint32_t USBPLLCLKSEL;               /*!< (@ 0x40048048) USB PLL clock source select */
-  __IO uint32_t USBPLLCLKUEN;               /*!< (@ 0x4004804C) USB PLL clock source update enable */
-  __I  uint32_t RESERVED3[8];
-  __IO uint32_t MAINCLKSEL;                 /*!< (@ 0x40048070) Main clock source select */
-  __IO uint32_t MAINCLKUEN;                 /*!< (@ 0x40048074) Main clock source update enable */
-  __IO uint32_t SYSAHBCLKDIV;               /*!< (@ 0x40048078) System clock divider   */
-  __I  uint32_t RESERVED4[1];
-  __IO uint32_t SYSAHBCLKCTRL;              /*!< (@ 0x40048080) System clock control   */
-  __I  uint32_t RESERVED5[4];
-  __IO uint32_t SSP0CLKDIV;                 /*!< (@ 0x40048094) SSP0 clock divider     */
-  __IO uint32_t UARTCLKDIV;                 /*!< (@ 0x40048098) UART clock divider     */
-  __IO uint32_t SSP1CLKDIV;                 /*!< (@ 0x4004809C) SSP1 clock divider     */
-  __I  uint32_t RESERVED6[8];
-  __IO uint32_t USBCLKSEL;                  /*!< (@ 0x400480C0) USB clock source select */
-  __IO uint32_t USBCLKUEN;                  /*!< (@ 0x400480C4) USB clock source update enable */
-  __IO uint32_t USBCLKDIV;                  /*!< (@ 0x400480C8) USB clock source divider */
-  __I  uint32_t RESERVED7[5];
-  __IO uint32_t CLKOUTSEL;                  /*!< (@ 0x400480E0) CLKOUT clock source select */
-  __IO uint32_t CLKOUTUEN;                  /*!< (@ 0x400480E4) CLKOUT clock source update enable */
-  __IO uint32_t CLKOUTDIV;                  /*!< (@ 0x400480E8) CLKOUT clock divider   */
-  __I  uint32_t RESERVED8[5];
-  __I  uint32_t PIOPORCAP0;                 /*!< (@ 0x40048100) POR captured PIO status 0 */
-  __I  uint32_t PIOPORCAP1;                 /*!< (@ 0x40048104) POR captured PIO status 1 */
-  __I  uint32_t RESERVED9[18];
-  __IO uint32_t BODCTRL;                    /*!< (@ 0x40048150) Brown-Out Detect       */
-  __IO uint32_t SYSTCKCAL;                  /*!< (@ 0x40048154) System tick counter calibration */
-  __I  uint32_t RESERVED10[6];
-  __IO uint32_t IRQLATENCY;                 /*!< (@ 0x40048170) IQR delay */
-  __IO uint32_t NMISRC;                     /*!< (@ 0x40048174) NMI Source Control     */
-  __IO uint32_t PINTSEL[8];                 /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
-  __IO uint32_t USBCLKCTRL;                 /*!< (@ 0x40048198) USB clock control      */
-  __I  uint32_t USBCLKST;                   /*!< (@ 0x4004819C) USB clock status       */
-  __I  uint32_t RESERVED11[25];
-  __IO uint32_t STARTERP0;                  /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
-  __I  uint32_t RESERVED12[3];
-  __IO uint32_t STARTERP1;                  /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
-  __I  uint32_t RESERVED13[6];
-  __IO uint32_t PDSLEEPCFG;                 /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
-  __IO uint32_t PDAWAKECFG;                 /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
-  __IO uint32_t PDRUNCFG;                   /*!< (@ 0x40048238) Power configuration register */
-  __I  uint32_t RESERVED14[110];
-  __I  uint32_t DEVICE_ID;                  /*!< (@ 0x400483F4) Device ID              */
-} LPC_SYSCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                     GPIO_PIN_INT                                     -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (GPIO_PIN_INT)
-  */
-
-typedef struct {                            /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
-  __IO uint32_t ISEL;                       /*!< (@ 0x4004C000) Pin Interrupt Mode register */
-  __IO uint32_t IENR;                       /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
-  __IO uint32_t SIENR;                      /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
-  __IO uint32_t CIENR;                      /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
-  __IO uint32_t IENF;                       /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
-  __IO uint32_t SIENF;                      /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
-  __IO uint32_t CIENF;                      /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
-  __IO uint32_t RISE;                       /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
-  __IO uint32_t FALL;                       /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
-  __IO uint32_t IST;                        /*!< (@ 0x4004C024) Pin Interrupt Status register */
-} LPC_GPIO_PIN_INT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                    GPIO_GROUP_INT0/1                                   -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (GPIO_GROUP_INT0)
-  */
-
-typedef struct {                            /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
-  __IO uint32_t CTRL;                       /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
-  __I  uint32_t RESERVED0[7];
-  __IO uint32_t PORT_POL[2];                /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
-  __I  uint32_t RESERVED1[6];
-  __IO uint32_t PORT_ENA[2];                /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
-} LPC_GPIO_GROUP_INTx_Type;
-
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                          USB                                         -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3  (USB)
-  */
-
-typedef struct {                            /*!< (@ 0x40080000) USB Structure          */
-  __IO uint32_t DEVCMDSTAT;                 /*!< (@ 0x40080000) USB Device Command/Status register */
-  __IO uint32_t INFO;                       /*!< (@ 0x40080004) USB Info register      */
-  __IO uint32_t EPLISTSTART;                /*!< (@ 0x40080008) USB EP Command/Status List start address */
-  __IO uint32_t DATABUFSTART;               /*!< (@ 0x4008000C) USB Data buffer start address */
-  __IO uint32_t LPM;                        /*!< (@ 0x40080010) Link Power Management register */
-  __IO uint32_t EPSKIP;                     /*!< (@ 0x40080014) USB Endpoint skip      */
-  __IO uint32_t EPINUSE;                    /*!< (@ 0x40080018) USB Endpoint Buffer in use */
-  __IO uint32_t EPBUFCFG;                   /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
-  __IO uint32_t INTSTAT;                    /*!< (@ 0x40080020) USB interrupt status register */
-  __IO uint32_t INTEN;                      /*!< (@ 0x40080024) USB interrupt enable register */
-  __IO uint32_t INTSETSTAT;                 /*!< (@ 0x40080028) USB set interrupt status register */
-  __IO uint32_t INTROUTING;                 /*!< (@ 0x4008002C) USB interrupt routing register */
-  __I  uint32_t RESERVED0[1];
-  __I  uint32_t EPTOGGLE;                   /*!< (@ 0x40080034) USB Endpoint toggle register */
-} LPC_USB_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       GPIO_PORT                                      -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (GPIO_PORT)
-  */
-
-typedef struct {                            
-  union {
-    struct {
-      __IO uint8_t B0[32];                       /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
-      __IO uint8_t B1[32];                       /*!< (@ 0x50000020) Byte pin registers port 1 */
-    };
-    __IO uint8_t B[64];                       /*!< (@ 0x50000000) Byte pin registers port 0/1 */
-  };
-  __I  uint32_t RESERVED0[1008];
-  union {
-    struct {
-      __IO uint32_t W0[32];                      /*!< (@ 0x50001000) Word pin registers port 0 */
-      __IO uint32_t W1[32];                      /*!< (@ 0x50001080) Word pin registers port 1 */
-    };
-    __IO uint32_t W[64];                       /*!< (@ 0x50001000) Word pin registers port 0/1 */
-  };
-       uint32_t RESERVED1[960];
-  __IO uint32_t DIR[2];			/* 0x2000 */
-       uint32_t RESERVED2[30];
-  __IO uint32_t MASK[2];		/* 0x2080 */
-       uint32_t RESERVED3[30];
-  __IO uint32_t PIN[2];			/* 0x2100 */
-       uint32_t RESERVED4[30];
-  __IO uint32_t MPIN[2];		/* 0x2180 */
-       uint32_t RESERVED5[30];
-  __IO uint32_t SET[2];			/* 0x2200 */
-       uint32_t RESERVED6[30];
-  __O  uint32_t CLR[2];			/* 0x2280 */
-       uint32_t RESERVED7[30];
-  __O  uint32_t NOT[2];			/* 0x2300 */
-} LPC_GPIO_Type;
-
-
-#if defined ( __CC_ARM   )
-  #pragma no_anon_unions
-#endif
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                 Peripheral memory map                                -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C_BASE              (0x40000000)
-#define LPC_WWDT_BASE             (0x40004000)
-#define LPC_USART_BASE            (0x40008000)
-#define LPC_CT16B0_BASE           (0x4000C000)
-#define LPC_CT16B1_BASE           (0x40010000)
-#define LPC_CT32B0_BASE           (0x40014000)
-#define LPC_CT32B1_BASE           (0x40018000)
-#define LPC_ADC_BASE              (0x4001C000)
-#define LPC_PMU_BASE              (0x40038000)
-#define LPC_FLASHCTRL_BASE        (0x4003C000)
-#define LPC_SSP0_BASE             (0x40040000)
-#define LPC_SSP1_BASE             (0x40058000)
-#define LPC_IOCON_BASE            (0x40044000)
-#define LPC_SYSCON_BASE           (0x40048000)
-#define LPC_GPIO_PIN_INT_BASE     (0x4004C000)
-#define LPC_GPIO_GROUP_INT0_BASE  (0x4005C000)
-#define LPC_GPIO_GROUP_INT1_BASE  (0x40060000)
-#define LPC_USB_BASE              (0x40080000)
-#define LPC_GPIO_BASE             (0x50000000)
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                Peripheral declaration                                -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C                   ((LPC_I2C_Type            *) LPC_I2C_BASE)
-#define LPC_WWDT                  ((LPC_WWDT_Type           *) LPC_WWDT_BASE)
-#define LPC_USART                 ((LPC_USART_Type          *) LPC_USART_BASE)
-#define LPC_CT16B0                ((LPC_CTxxBx_Type         *) LPC_CT16B0_BASE)
-#define LPC_CT16B1                ((LPC_CTxxBx_Type         *) LPC_CT16B1_BASE)
-#define LPC_CT32B0                ((LPC_CTxxBx_Type         *) LPC_CT32B0_BASE)
-#define LPC_CT32B1                ((LPC_CTxxBx_Type         *) LPC_CT32B1_BASE)
-#define LPC_ADC                   ((LPC_ADC_Type            *) LPC_ADC_BASE)
-#define LPC_PMU                   ((LPC_PMU_Type            *) LPC_PMU_BASE)
-#define LPC_FLASHCTRL             ((LPC_FLASHCTRL_Type      *) LPC_FLASHCTRL_BASE)
-#define LPC_SSP0                  ((LPC_SSPx_Type           *) LPC_SSP0_BASE)
-#define LPC_SSP1                  ((LPC_SSPx_Type           *) LPC_SSP1_BASE)
-#define LPC_IOCON                 ((LPC_IOCON_Type          *) LPC_IOCON_BASE)
-#define LPC_SYSCON                ((LPC_SYSCON_Type         *) LPC_SYSCON_BASE)
-#define LPC_GPIO_PIN_INT          ((LPC_GPIO_PIN_INT_Type   *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0       ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1       ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_USB                   ((LPC_USB_Type            *) LPC_USB_BASE)
-#define LPC_GPIO                  ((LPC_GPIO_Type           *) LPC_GPIO_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group (null) */
-/** @} */ /* End of group LPC11Uxx */
-
-#ifdef __cplusplus
-}
-#endif 
-
-
-#endif  // __LPC11UXX_H__

--- a/vendor/NXP/LPC11U24/cmsis/cmsis.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,13 +0,0 @@
-/* mbed Microcontroller Library - CMSIS
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * A generic CMSIS include header, pulling in LPC11U24 specifics
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "LPC11Uxx.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/vendor/NXP/LPC11U24/cmsis/cmsis_nvic.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,58 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
- * Copyright (c) 2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-
-#include "cmsis_nvic.h"
-
-/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
- * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0), 
- * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF 
- * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
- * 
- * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
- * above the vector table before 0x200 will actually go to RAM. So we need to provide 
- * a solution where the compiler gets the right results based on the memory map
- *
- * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
- *  - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
- *  - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
- * 
- * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there  
- *  - No flash accesses will go to ram, as there will be nothing there
- *  - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
- *  - RAM overhead: 0, FLASH overhead: 320 bytes
- *
- * Option 2 is the one to go for, as RAM is the most valuable resource
- */
-
-#define NVIC_NUM_VECTORS (16 + 32)            // CORE + MCU Peripherals
-#define NVIC_RAM_VECTOR_ADDRESS (0x10000000)  // Vectors positioned at start of RAM
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-    int i;
-    // Space for dynamic vectors, initialised to allocate in R/W
-    static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
-    
-    // Copy and switch to dynamic vectors if first time called
-    if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {     
-      uint32_t *old_vectors = (uint32_t *)0;         // FLASH vectors are at 0x0
-      for(i = 0; i < NVIC_NUM_VECTORS; i++) {    
-            vectors[i] = old_vectors[i];
-        }
-        LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
-    }
-
-    // Set the vector 
-    vectors[IRQn + 16] = vector; 
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    // We can always read vectors at 0x0, as the addresses are remapped
-    uint32_t *vectors = (uint32_t*)0; 
-
-    // Return the vector
-    return vectors[IRQn + 16];
-}
-

--- a/vendor/NXP/LPC11U24/cmsis/cmsis_nvic.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,23 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC11U24/cmsis/core_cm0.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,279 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.c
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Source File
- * @version  V2.00
- * @date     10. September 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-
-/* ##########################  Core Instruction Access  ######################### */
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __CLREX(void)
-{
-  clrex
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_CONTROL(void)
-{
-  mrs r0, control
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_CONTROL(uint32_t control)
-{
-  msr control, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_IPSR(void)
-{
-  mrs r0, ipsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_APSR(void)
-{
-  mrs r0, apsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_xPSR(void)
-{
-  mrs r0, xpsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_PSP(void)
-{
-  mrs r0, psp
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
-  msr psp, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_MSP(void)
-{
-  mrs r0, msp
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
-  msr msp, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_PRIMASK(void)
-{
-  mrs r0, primask
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
-  msr primask, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
- 
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif

--- a/vendor/NXP/LPC11U24/cmsis/core_cm0.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,667 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V3.02
- * @date     05. November 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M0
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM0_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-       uint32_t RESERVED0;
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
-
-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

--- a/vendor/NXP/LPC11U24/cmsis/core_cmFunc.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,616 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V3.02
- * @date     24. May 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */

--- a/vendor/NXP/LPC11U24/cmsis/core_cmInstr.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,643 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V3.03
- * @date     29. August 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-#define __ISB()                           __isb(0xF)
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()                           __dsb(0xF)
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB()                           __dmb(0xF)
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __RBIT                            __rbit
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-
-  __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
-  return(op1);
-}
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint8_t result;
-
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint16_t result;
-
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
-  uint8_t result;
-
-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

--- a/vendor/NXP/LPC11U24/cmsis/power_api.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,82 +0,0 @@
-/****************************************************************************
- *   $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267                   $
- *   Project: NXP LPC11Uxx software example  
- *
- *   Description:
- *     Power API Header File for NXP LPC11Uxx Device Series 
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __LPC11UXX_POWER_API_H__
-#define __LPC11UXX_POWER_API_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-#define PWRROMD_PRESENT
-
-typedef	struct _PWRD {
-  void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
-  void (*set_power)(unsigned int cmd[], unsigned int resp[]);
-}  PWRD;
-
-typedef	struct _ROM {
-#ifdef USBROMD_PRESENT
-   const USB * pUSBD;
-#else
-   const unsigned p_usbd;
-#endif /* USBROMD_PRESENT */
-   const unsigned p_clib;
-   const unsigned p_cand;
-#ifdef PWRROMD_PRESENT
-   const PWRD * pPWRD;
-#else
-   const unsigned p_pwrd;
-#endif /* PWRROMD_PRESENT */
-   const unsigned p_dev1;
-   const unsigned p_dev2;
-   const unsigned p_dev3;
-   const unsigned p_dev4; 
-}  ROM;
-
-//PLL setup related definitions
-#define	CPU_FREQ_EQU  		0       //main PLL freq must be equal to the specified 
-#define	CPU_FREQ_LTE		1       //main PLL freq must be less than or equal the specified
-#define	CPU_FREQ_GTE		2       //main PLL freq must be greater than or equal the specified
-#define	CPU_FREQ_APPROX		3       //main PLL freq must be as close as possible the specified
-
-#define	PLL_CMD_SUCCESS		0       //PLL setup successfully found
-#define	PLL_INVALID_FREQ	1       //specified freq out of range (either input or output)
-#define	PLL_INVALID_MODE	2       //invalid mode (see above for valid) specified
-#define	PLL_FREQ_NOT_FOUND	3       //specified freq not found under specified conditions
-#define	PLL_NOT_LOCKED		4       //PLL not locked => no changes to the PLL setup
-
-//power setup elated definitions
-#define	PARAM_DEFAULT			0   //default power settings (voltage regulator, flash interface)
-#define	PARAM_CPU_PERFORMANCE	1   //setup for maximum CPU performance (higher current, more computation)
-#define	PARAM_EFFICIENCY		2   //balanced setting (power vs CPU performance)
-#define	PARAM_LOW_CURRENT		3   //lowest active current, lowest CPU performance
-
-#define	PARAM_CMD_SUCCESS		0   //power setting successfully found
-#define	PARAM_INVALID_FREQ		1   //specified freq out of range (=0 or > 50 MHz)
-#define	PARAM_INVALID_MODE		2   //specified mode not valid (see above for valid)
-
-#define MAX_CLOCK_KHZ_PARAM                50000
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* __LPC11UXX_POWER_API_H__ */
-

--- a/vendor/NXP/LPC11U24/cmsis/system_LPC11Uxx.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,450 +0,0 @@
-/******************************************************************************
- * @file     system_LPC11Uxx.c
- * @purpose  CMSIS Cortex-M3 Device Peripheral Access Layer Source File
- *           for the NXP LPC13xx Device Series
- * @version  V1.10
- * @date     24. November 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#include <stdint.h>
-#include "LPC11Uxx.h"
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-
-/*--------------------- Clock Configuration ----------------------------------
-//
-// <e> Clock Configuration
-//   <h> System Oscillator Control Register (SYSOSCCTRL)
-//     <o1.0>      BYPASS: System Oscillator Bypass Enable
-//                     <i> If enabled then PLL input (sys_osc_clk) is fed
-//                     <i> directly from XTALIN and XTALOUT pins.
-//     <o1.9>      FREQRANGE: System Oscillator Frequency Range
-//                     <i> Determines frequency range for Low-power oscillator.
-//                   <0=> 1 - 20 MHz
-//                   <1=> 15 - 25 MHz
-//   </h>
-//
-//   <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
-//     <o2.0..4>   DIVSEL: Select Divider for Fclkana
-//                     <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
-//                   <0-31>
-//     <o2.5..8>   FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
-//                   <0=> Undefined
-//                   <1=> 0.5 MHz
-//                   <2=> 0.8 MHz
-//                   <3=> 1.1 MHz
-//                   <4=> 1.4 MHz
-//                   <5=> 1.6 MHz
-//                   <6=> 1.8 MHz
-//                   <7=> 2.0 MHz
-//                   <8=> 2.2 MHz
-//                   <9=> 2.4 MHz
-//                   <10=> 2.6 MHz
-//                   <11=> 2.7 MHz
-//                   <12=> 2.9 MHz
-//                   <13=> 3.1 MHz
-//                   <14=> 3.2 MHz
-//                   <15=> 3.4 MHz
-//   </h>
-//
-//   <h> System PLL Control Register (SYSPLLCTRL)
-//                   <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
-//                   <i> F_clkin must be in the range of  10 MHz to  25 MHz
-//                   <i> F_CCO   must be in the range of 156 MHz to 320 MHz
-//     <o3.0..4>   MSEL: Feedback Divider Selection
-//                     <i> M = MSEL + 1
-//                   <0-31>
-//     <o3.5..6>   PSEL: Post Divider Selection
-//                   <0=> P = 1
-//                   <1=> P = 2
-//                   <2=> P = 4
-//                   <3=> P = 8
-//   </h>
-//
-//   <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
-//     <o4.0..1>   SEL: System PLL Clock Source
-//                   <0=> IRC Oscillator
-//                   <1=> System Oscillator
-//                   <2=> Reserved
-//                   <3=> Reserved
-//   </h>
-//
-//   <h> Main Clock Source Select Register (MAINCLKSEL)
-//     <o5.0..1>   SEL: Clock Source for Main Clock
-//                   <0=> IRC Oscillator
-//                   <1=> Input Clock to System PLL
-//                   <2=> WDT Oscillator
-//                   <3=> System PLL Clock Out
-//   </h>
-//
-//   <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
-//     <o6.0..7>   DIV: System AHB Clock Divider
-//                     <i> Divides main clock to provide system clock to core, memories, and peripherals.
-//                     <i> 0 = is disabled
-//                   <0-255>
-//   </h>
-//
-//   <h> USB PLL Control Register (USBPLLCTRL)
-//                   <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
-//                   <i> F_clkin must be in the range of  10 MHz to  25 MHz
-//                   <i> F_CCO   must be in the range of 156 MHz to 320 MHz
-//     <o7.0..4>   MSEL: Feedback Divider Selection
-//                     <i> M = MSEL + 1
-//                   <0-31>
-//     <o7.5..6>   PSEL: Post Divider Selection
-//                   <0=> P = 1
-//                   <1=> P = 2
-//                   <2=> P = 4
-//                   <3=> P = 8
-//   </h>
-//
-//   <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
-//     <o8.0..1>   SEL: USB PLL Clock Source
-//                     <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
-//                   <0=> IRC Oscillator
-//                   <1=> System Oscillator
-//                   <2=> Reserved
-//                   <3=> Reserved
-//   </h>
-//
-//   <h> USB Clock Source Select Register (USBCLKSEL)
-//     <o9.0..1>   SEL: System PLL Clock Source
-//                   <0=> USB PLL out
-//                   <1=> Main clock
-//                   <2=> Reserved
-//                   <3=> Reserved
-//   </h>
-//
-//   <h> USB Clock Divider Register (USBCLKDIV)
-//     <o10.0..7>  DIV: USB Clock Divider
-//                     <i> Divides USB clock to 48 MHz.
-//                     <i> 0 = is disabled
-//                   <0-255>
-//   </h>
-// </e>
-*/
-#define CLOCK_SETUP           1
-#define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
-#define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
-#define SYSPLLCTRL_Val        0x00000023              // Reset: 0x000
-#define SYSPLLCLKSEL_Val      0x00000001              // Reset: 0x000
-#define MAINCLKSEL_Val        0x00000003              // Reset: 0x000
-#define SYSAHBCLKDIV_Val      0x00000001              // Reset: 0x001
-#define USBPLLCTRL_Val        0x00000023              // Reset: 0x000
-#define USBPLLCLKSEL_Val      0x00000001              // Reset: 0x000
-#define USBCLKSEL_Val         0x00000000              // Reset: 0x000
-#define USBCLKDIV_Val         0x00000001              // Reset: 0x001
-
-/*
-//-------- <<< end of configuration section >>> ------------------------------
-*/
-
-/*----------------------------------------------------------------------------
-  Check the register settings
- *----------------------------------------------------------------------------*/
-#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
-#define CHECK_RSVD(val, mask)                     (val & mask)
-
-/* Clock Configuration -------------------------------------------------------*/
-#if (CHECK_RSVD((SYSOSCCTRL_Val),  ~0x00000003))
-   #error "SYSOSCCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((WDTOSCCTRL_Val),  ~0x000001FF))
-   #error "WDTOSCCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
-   #error "SYSPLLCLKSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((SYSPLLCTRL_Val),  ~0x000001FF))
-   #error "SYSPLLCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((MAINCLKSEL_Val),  ~0x00000003))
-   #error "MAINCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
-   #error "SYSAHBCLKDIV: Value out of range!"
-#endif
-
-#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
-   #error "USBPLLCLKSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((USBPLLCTRL_Val),  ~0x000001FF))
-   #error "USBPLLCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
-   #error "USBCLKSEL: Value out of range!"
-#endif
-
-#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
-   #error "USBCLKDIV: Value out of range!"
-#endif
-
-
-/*----------------------------------------------------------------------------
-  DEFINES
- *----------------------------------------------------------------------------*/
-    
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define __XTAL            (12000000UL)    /* Oscillator frequency             */
-#define __SYS_OSC_CLK     (    __XTAL)    /* Main oscillator frequency        */
-#define __IRC_OSC_CLK     (12000000UL)    /* Internal RC oscillator frequency */
-
-
-#define __FREQSEL   ((WDTOSCCTRL_Val >> 5) & 0x0F)
-#define __DIVSEL   (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
-
-#if (CLOCK_SETUP)                         /* Clock Setup              */
-  #if  (__FREQSEL ==  0)
-    #define __WDT_OSC_CLK        ( 0)                  /* undefined */
-  #elif (__FREQSEL ==  1)
-    #define __WDT_OSC_CLK        ( 500000 / __DIVSEL)
-  #elif (__FREQSEL ==  2)
-    #define __WDT_OSC_CLK        ( 800000 / __DIVSEL)
-  #elif (__FREQSEL ==  3)
-    #define __WDT_OSC_CLK        (1100000 / __DIVSEL)
-  #elif (__FREQSEL ==  4)
-    #define __WDT_OSC_CLK        (1400000 / __DIVSEL)
-  #elif (__FREQSEL ==  5)
-    #define __WDT_OSC_CLK        (1600000 / __DIVSEL)
-  #elif (__FREQSEL ==  6)
-    #define __WDT_OSC_CLK        (1800000 / __DIVSEL)
-  #elif (__FREQSEL ==  7)
-    #define __WDT_OSC_CLK        (2000000 / __DIVSEL)
-  #elif (__FREQSEL ==  8)
-    #define __WDT_OSC_CLK        (2200000 / __DIVSEL)
-  #elif (__FREQSEL ==  9)
-    #define __WDT_OSC_CLK        (2400000 / __DIVSEL)
-  #elif (__FREQSEL == 10)
-    #define __WDT_OSC_CLK        (2600000 / __DIVSEL)
-  #elif (__FREQSEL == 11)
-    #define __WDT_OSC_CLK        (2700000 / __DIVSEL)
-  #elif (__FREQSEL == 12)
-    #define __WDT_OSC_CLK        (2900000 / __DIVSEL)
-  #elif (__FREQSEL == 13)
-    #define __WDT_OSC_CLK        (3100000 / __DIVSEL)
-  #elif (__FREQSEL == 14)
-    #define __WDT_OSC_CLK        (3200000 / __DIVSEL)
-  #else
-    #define __WDT_OSC_CLK        (3400000 / __DIVSEL)
-  #endif
-
-  /* sys_pllclkin calculation */
-  #if   ((SYSPLLCLKSEL_Val & 0x03) == 0)
-    #define __SYS_PLLCLKIN           (__IRC_OSC_CLK)
-  #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
-    #define __SYS_PLLCLKIN           (__SYS_OSC_CLK)
-  #else
-    #define __SYS_PLLCLKIN           (0)
-  #endif
-
-  #define  __SYS_PLLCLKOUT         (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
-
-  /* main clock calculation */
-  #if   ((MAINCLKSEL_Val & 0x03) == 0)
-    #define __MAIN_CLOCK             (__IRC_OSC_CLK)
-  #elif ((MAINCLKSEL_Val & 0x03) == 1)
-    #define __MAIN_CLOCK             (__SYS_PLLCLKIN)
-  #elif ((MAINCLKSEL_Val & 0x03) == 2)
-    #if (__FREQSEL ==  0)
-      #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
-    #else
-      #define __MAIN_CLOCK           (__WDT_OSC_CLK)
-    #endif
-  #elif ((MAINCLKSEL_Val & 0x03) == 3)
-    #define __MAIN_CLOCK             (__SYS_PLLCLKOUT)
-  #else
-    #define __MAIN_CLOCK             (0)
-  #endif
-
-  #define __SYSTEM_CLOCK             (__MAIN_CLOCK / SYSAHBCLKDIV_Val)         
-
-#else
-  #define __SYSTEM_CLOCK             (__IRC_OSC_CLK)
-#endif  // CLOCK_SETUP 
-
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
-
-
-/*----------------------------------------------------------------------------
-  Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
-{
-  uint32_t wdt_osc = 0;
-
-  /* Determine clock frequency according to clock register values             */
-  switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
-    case 0:  wdt_osc =       0; break;
-    case 1:  wdt_osc =  500000; break;
-    case 2:  wdt_osc =  800000; break;
-    case 3:  wdt_osc = 1100000; break;
-    case 4:  wdt_osc = 1400000; break;
-    case 5:  wdt_osc = 1600000; break;
-    case 6:  wdt_osc = 1800000; break;
-    case 7:  wdt_osc = 2000000; break;
-    case 8:  wdt_osc = 2200000; break;
-    case 9:  wdt_osc = 2400000; break;
-    case 10: wdt_osc = 2600000; break;
-    case 11: wdt_osc = 2700000; break;
-    case 12: wdt_osc = 2900000; break;
-    case 13: wdt_osc = 3100000; break;
-    case 14: wdt_osc = 3200000; break;
-    case 15: wdt_osc = 3400000; break;
-  }
-  wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
- 
-  switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
-    case 0:                             /* Internal RC oscillator             */
-      SystemCoreClock = __IRC_OSC_CLK;
-      break;
-    case 1:                             /* Input Clock to System PLL          */
-      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
-          case 0:                       /* Internal RC oscillator             */
-            SystemCoreClock = __IRC_OSC_CLK;
-            break;
-          case 1:                       /* System oscillator                  */
-            SystemCoreClock = __SYS_OSC_CLK;
-            break;
-          case 2:                       /* Reserved                           */
-          case 3:                       /* Reserved                           */
-            SystemCoreClock = 0;
-            break;
-      }
-      break;
-    case 2:                             /* WDT Oscillator                     */
-      SystemCoreClock = wdt_osc;
-      break;
-    case 3:                             /* System PLL Clock Out               */
-      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
-          case 0:                       /* Internal RC oscillator             */
-            if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
-              SystemCoreClock = __IRC_OSC_CLK;
-            } else {
-              SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
-            }
-            break;
-          case 1:                       /* System oscillator                  */
-            if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
-              SystemCoreClock = __SYS_OSC_CLK;
-            } else {
-              SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
-            }
-            break;
-          case 2:                       /* Reserved                           */
-          case 3:                       /* Reserved                           */
-            SystemCoreClock = 0;
-            break;
-      }
-      break;
-  }
-
-  SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;  
-
-}
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void) {
-  volatile uint32_t i;
-
-#if (CLOCK_SETUP)                                 /* Clock Setup              */
-
-#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
-  LPC_SYSCON->PDRUNCFG     &= ~(1 << 5);          /* Power-up System Osc      */
-  LPC_SYSCON->SYSOSCCTRL    = SYSOSCCTRL_Val;
-  for (i = 0; i < 200; i++) __NOP();
-#endif
-
-  LPC_SYSCON->SYSPLLCLKSEL  = SYSPLLCLKSEL_Val;   /* Select PLL Input         */
-  LPC_SYSCON->SYSPLLCLKUEN  = 0x01;               /* Update Clock Source      */
-  LPC_SYSCON->SYSPLLCLKUEN  = 0x00;               /* Toggle Update Register   */
-  LPC_SYSCON->SYSPLLCLKUEN  = 0x01;
-  while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01));     /* Wait Until Updated       */
-#if ((MAINCLKSEL_Val & 0x03) == 3)                /* Main Clock is PLL Out    */
-  LPC_SYSCON->SYSPLLCTRL    = SYSPLLCTRL_Val;
-  LPC_SYSCON->PDRUNCFG     &= ~(1 << 7);          /* Power-up SYSPLL          */
-  while (!(LPC_SYSCON->SYSPLLSTAT & 0x01));	      /* Wait Until PLL Locked    */
-#endif
-
-#if (((MAINCLKSEL_Val & 0x03) == 2) )
-  LPC_SYSCON->WDTOSCCTRL    = WDTOSCCTRL_Val;
-  LPC_SYSCON->PDRUNCFG     &= ~(1 << 6);          /* Power-up WDT Clock       */
-  for (i = 0; i < 200; i++) __NOP();
-#endif
-
-  LPC_SYSCON->MAINCLKSEL    = MAINCLKSEL_Val;     /* Select PLL Clock Output  */
-  LPC_SYSCON->MAINCLKUEN    = 0x01;               /* Update MCLK Clock Source */
-  LPC_SYSCON->MAINCLKUEN    = 0x00;               /* Toggle Update Register   */
-  LPC_SYSCON->MAINCLKUEN    = 0x01;
-  while (!(LPC_SYSCON->MAINCLKUEN & 0x01));       /* Wait Until Updated       */
-
-  LPC_SYSCON->SYSAHBCLKDIV  = SYSAHBCLKDIV_Val;
-
-#if ((USBCLKDIV_Val & 0x1FF) != 0)                /* USB clock is used        */
-  LPC_SYSCON->PDRUNCFG     &= ~(1 << 10);         /* Power-up USB PHY         */
-
-#if ((USBCLKSEL_Val & 0x003) == 0)                /* USB clock is USB PLL out */
-  LPC_SYSCON->PDRUNCFG     &= ~(1 <<  8);         /* Power-up USB PLL         */
-  LPC_SYSCON->USBPLLCLKSEL  = USBPLLCLKSEL_Val;   /* Select PLL Input         */
-  LPC_SYSCON->USBPLLCLKUEN  = 0x01;               /* Update Clock Source      */
-  LPC_SYSCON->USBPLLCLKUEN  = 0x00;               /* Toggle Update Register   */
-  LPC_SYSCON->USBPLLCLKUEN  = 0x01;
-  while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01));     /* Wait Until Updated       */
-  LPC_SYSCON->USBPLLCTRL    = USBPLLCTRL_Val;
-  while (!(LPC_SYSCON->USBPLLSTAT   & 0x01));     /* Wait Until PLL Locked    */
-  LPC_SYSCON->USBCLKSEL     = 0x00;               /* Select USB PLL           */
-#endif
-
-  LPC_SYSCON->USBCLKSEL     = USBCLKSEL_Val;      /* Select USB Clock         */
-  LPC_SYSCON->USBCLKDIV     = USBCLKDIV_Val;      /* Set USB clock divider    */
-
-#else                                             /* USB clock is not used    */                        
-  LPC_SYSCON->PDRUNCFG     |=  (1 << 10);         /* Power-down USB PHY       */
-  LPC_SYSCON->PDRUNCFG     |=  (1 <<  8);         /* Power-down USB PLL       */
-#endif
-
-#endif
-
-  /* System clock to the IOCON needs to be enabled or
-  most of the I/O related peripherals won't work. */
-  LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
-}

--- a/vendor/NXP/LPC11U24/cmsis/system_LPC11Uxx.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,64 +0,0 @@
-/**************************************************************************//**
- * @file     system_LPC11Uxx.h
- * @brief    CMSIS Cortex-M0 Device Peripheral Access Layer Header File
- *           for the NXP LPC11Uxx Device Series
- * @version  V1.10
- * @date     24. November 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC11Uxx_H
-#define __SYSTEM_LPC11Uxx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock 
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC11Uxx_H */

--- a/vendor/NXP/LPC11U24/cmsis/uARM/LPC11U24.sct	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,14 +0,0 @@
-
-LR_IROM1 0x00000000 0x8000  {    ; load region size_region (32k)
-  ER_IROM1 0x00000000 0x8000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
-  ; 8KB - 0xC0 = 0xF40
-  RW_IRAM1 0x100000C0 0xF40  {
-   .ANY (+RW +ZI)
-  }
-}
-

--- a/vendor/NXP/LPC11U24/cmsis/uARM/startup_LPC11xx.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,325 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC11xx.s
-; * @purpose: CMSIS Cortex-M0 Core Device Startup File 
-; *           for the NXP LPC11xx Device Series 
-; * @version: V1.0
-; * @date:    25. Nov. 2008
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2008 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 
-; * processor based microcontrollers.  This file can be freely distributed 
-; * within development tools that are supporting such ARM based processors. 
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __initial_sp
-
-Stack_Mem       SPACE   Stack_Size
-__initial_sp        EQU     0x10001000  ; Top of RAM from LPC11U
-
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-				; for LPC11Uxx (With USB)
-                DCD     FLEX_INT0_IRQHandler      ; All GPIO pin can be routed to FLEX_INTx
-                DCD     FLEX_INT1_IRQHandler          
-                DCD     FLEX_INT2_IRQHandler                       
-                DCD     FLEX_INT3_IRQHandler                         
-                DCD     FLEX_INT4_IRQHandler                        
-                DCD     FLEX_INT5_IRQHandler
-                DCD     FLEX_INT6_IRQHandler
-                DCD     FLEX_INT7_IRQHandler                       
-                DCD     GINT0_IRQHandler                         
-                DCD     GINT1_IRQHandler          ; PIO0 (0:7)              
-                DCD     Reserved_IRQHandler	      ; Reserved
-                DCD     Reserved_IRQHandler
-                DCD     Reserved_IRQHandler       
-                DCD     Reserved_IRQHandler                       
-                DCD     SSP1_IRQHandler           ; SSP1               
-                DCD     I2C_IRQHandler            ; I2C
-                DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
-                DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
-                DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
-                DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
-                DCD     SSP0_IRQHandler           ; SSP0
-                DCD     UART_IRQHandler           ; UART
-                DCD     USB_IRQHandler            ; USB IRQ
-                DCD     USB_FIQHandler            ; USB FIQ
-                DCD     ADC_IRQHandler            ; A/D Converter
-                DCD     WDT_IRQHandler            ; Watchdog timer
-                DCD     BOD_IRQHandler            ; Brown Out Detect
-                DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
-                DCD     Reserved_IRQHandler	    ; Reserved
-                DCD     Reserved_IRQHandler       ; Reserved
-                DCD     USBWakeup_IRQHandler      ; USB wake up
-                DCD     Reserved_IRQHandler       ; Reserved
-	
-	;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
-                
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-
-        	DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-                DCD     0xFFFFFFFF                ; Datafill
-	
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-	
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)                
-
-; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled 
-; for particular peripheral.
-;NMI_Handler     PROC
-;                EXPORT  NMI_Handler               [WEAK]
-;                B       .
-;                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-Reserved_IRQHandler PROC
-                EXPORT  Reserved_IRQHandler       [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-; for LPC11Uxx (With USB)
-                EXPORT  NMI_Handler               [WEAK]
-                EXPORT  FLEX_INT0_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT1_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT2_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT3_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT4_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT5_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT6_IRQHandler      [WEAK]
-                EXPORT  FLEX_INT7_IRQHandler      [WEAK]
-                EXPORT  GINT0_IRQHandler          [WEAK]
-                EXPORT  GINT1_IRQHandler          [WEAK]
-                EXPORT  SSP1_IRQHandler           [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  TIMER16_0_IRQHandler      [WEAK]
-                EXPORT  TIMER16_1_IRQHandler      [WEAK]
-                EXPORT  TIMER32_0_IRQHandler      [WEAK]
-                EXPORT  TIMER32_1_IRQHandler      [WEAK]
-                EXPORT  SSP0_IRQHandler           [WEAK]
-                EXPORT  UART_IRQHandler           [WEAK]
-
-                EXPORT  USB_IRQHandler            [WEAK]
-                EXPORT  USB_FIQHandler            [WEAK]
-                EXPORT  ADC_IRQHandler            [WEAK]
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  BOD_IRQHandler            [WEAK]
-                EXPORT  FMC_IRQHandler            [WEAK]
-                EXPORT	USBWakeup_IRQHandler      [WEAK]
-
-NMI_Handler
-FLEX_INT0_IRQHandler
-FLEX_INT1_IRQHandler
-FLEX_INT2_IRQHandler
-FLEX_INT3_IRQHandler
-FLEX_INT4_IRQHandler
-FLEX_INT5_IRQHandler
-FLEX_INT6_IRQHandler
-FLEX_INT7_IRQHandler
-GINT0_IRQHandler
-GINT1_IRQHandler
-SSP1_IRQHandler
-I2C_IRQHandler
-TIMER16_0_IRQHandler
-TIMER16_1_IRQHandler
-TIMER32_0_IRQHandler
-TIMER32_1_IRQHandler
-SSP0_IRQHandler
-UART_IRQHandler
-USB_IRQHandler
-USB_FIQHandler
-ADC_IRQHandler
-WDT_IRQHandler
-BOD_IRQHandler
-FMC_IRQHandler
-USBWakeup_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- a/vendor/NXP/LPC11U24/cmsis/uARM/sys.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * Setup a fixed single stack/heap memory model, 
- *  between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/vendor/NXP/LPC11U24/hal/PeripheralNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,71 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    UART_0 = (int)LPC_USART_BASE
-} UARTName;
-
-typedef enum {
-    I2C_0 = (int)LPC_I2C_BASE
-} I2CName;
-
-typedef enum {
-    ADC0_0 = 0,
-    ADC0_1,
-    ADC0_2,
-    ADC0_3,
-    ADC0_4,
-    ADC0_5,
-    ADC0_6,
-    ADC0_7
-} ADCName;
-
-typedef enum {
-    SPI_0 = (int)LPC_SSP0_BASE,
-    SPI_1 = (int)LPC_SSP1_BASE
-} SPIName;
-
-typedef enum {
-    PWM_1 = 0,
-    PWM_2,
-    PWM_3,
-    PWM_4,
-    PWM_5,
-    PWM_6,
-    PWM_7,
-    PWM_8,
-    PWM_9,
-    PWM_10,
-    PWM_11
-} PWMName;
-
-#define STDIO_UART_TX     USBTX
-#define STDIO_UART_RX     USBRX
-#define STDIO_UART        UART_0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC11U24/hal/PinNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,165 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT  5
-
-typedef enum {
-    // LPC11U Pin Names
-    P0_0 = 0,
-    P0_1 = 1,
-    P0_2 = 2,
-    P0_3 = 3,
-    P0_4 = 4,
-    P0_5 = 5,
-    P0_6 = 6,
-    P0_7 = 7,
-    P0_8 = 8,
-    P0_9 = 9,
-    P0_10 = 10,
-    P0_11 = 11,
-    P0_12 = 12,
-    P0_13 = 13,
-    P0_14 = 14,
-    P0_15 = 15,
-    P0_16 = 16,
-    P0_17 = 17,
-    P0_18 = 18,
-    P0_19 = 19,
-    P0_20 = 20,
-    P0_21 = 21,
-    P0_22 = 22,
-    P0_23 = 23,
-    P0_24 = 24,
-    P0_25 = 25,
-    P0_26 = 26,
-    P0_27 = 27,
-
-    P1_0 = 32,
-    P1_1 = 33,
-    P1_2 = 34,
-    P1_3 = 35,
-    P1_4 = 36,
-    P1_5 = 37,
-    P1_6 = 38,
-    P1_7 = 39,
-    P1_8 = 40,
-    P1_9 = 41,
-    P1_10 = 42,
-    P1_11 = 43,
-    P1_12 = 44,
-    P1_13 = 45,
-    P1_14 = 46,
-    P1_15 = 47,
-    P1_16 = 48,
-    P1_17 = 49,
-    P1_18 = 50,
-    P1_19 = 51,
-    P1_20 = 52,
-    P1_21 = 53,
-    P1_22 = 54,
-    P1_23 = 55,
-    P1_24 = 56,
-    P1_25 = 57,
-    P1_26 = 58,
-    P1_27 = 59,
-    P1_28 = 60,
-    P1_29 = 61,
-
-    P1_31 = 63,
-
-    // mbed DIP Pin Names
-    p5  = P0_9,
-    p6  = P0_8,
-    p7  = P1_29,
-    p8  = P0_2,
-    p9  = P1_27,
-    p10 = P1_26,
-    p11 = P1_22,
-    p12 = P1_21,
-    p13 = P1_20,
-    p14 = P1_23,
-    p15 = P0_11,
-    p16 = P0_12,
-    p17 = P0_13,
-    p18 = P0_14,
-    p19 = P0_16,
-    p20 = P0_22,
-    p21 = P0_7,
-    p22 = P0_17,
-    p23 = P1_17,
-    p24 = P1_18,
-    p25 = P1_24,
-    p26 = P1_25,
-    p27 = P0_4,
-    p28 = P0_5,
-    p29 = P1_5,
-    p30 = P1_2,
-
-    p33 = P0_3,
-    p34 = P1_15,
-    p35 = P0_20,
-    p36 = P0_21,
-
-    // Other mbed Pin Names
-    LED1 = P1_8,
-    LED2 = P1_9,
-    LED3 = P1_10,
-    LED4 = P1_11,
-
-    USBTX = P0_19,
-    USBRX = P0_18,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF,
-} PinName;
-
-typedef enum {
-    CHANNEL0 = FLEX_INT0_IRQn,
-    CHANNEL1 = FLEX_INT1_IRQn,
-    CHANNEL2 = FLEX_INT2_IRQn,
-    CHANNEL3 = FLEX_INT3_IRQn,
-    CHANNEL4 = FLEX_INT4_IRQn,
-    CHANNEL5 = FLEX_INT5_IRQn,
-    CHANNEL6 = FLEX_INT6_IRQn,
-    CHANNEL7 = FLEX_INT7_IRQn
-} Channel;
-
-typedef enum {
-    PullUp = 2,
-    PullDown = 1,
-    PullNone = 0,
-    Repeater = 3,
-    OpenDrain = 4
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC11U24/hal/PortNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    Port0 = 0,
-    Port1 = 1
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif

--- a/vendor/NXP/LPC11U24/hal/analogin_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,126 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "analogin_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-#define ANALOGIN_MEDIAN_FILTER      1
-
-#define ADC_10BIT_RANGE             0x3FF
-#define ADC_12BIT_RANGE             0xFFF
-
-static inline int div_round_up(int x, int y) {
-  return (x + (y - 1)) / y;
-}
-
-static const PinMap PinMap_ADC[] = {
-    {P0_11, ADC0_0, 0x02},
-    {P0_12, ADC0_1, 0x02},
-    {P0_13, ADC0_2, 0x02},
-    {P0_14, ADC0_3, 0x02},
-    {P0_15, ADC0_4, 0x02},
-    {P0_16, ADC0_5, 0x01},
-    {P0_22, ADC0_6, 0x01},
-    {P0_23, ADC0_7, 0x01},
-    {NC   , NC    , 0   }
-};
-
-#define LPC_IOCON0_BASE (LPC_IOCON_BASE)
-#define LPC_IOCON1_BASE (LPC_IOCON_BASE + 0x60)
-
-#define ADC_RANGE    ADC_10BIT_RANGE
-
-void analogin_init(analogin_t *obj, PinName pin) {
-    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
-    if (obj->adc == (uint32_t)NC) {
-        error("ADC pin mapping failed");
-    }
-    
-    // Power up ADC
-    LPC_SYSCON->PDRUNCFG &= ~ (1 << 4);
-    LPC_SYSCON->SYSAHBCLKCTRL |= ((uint32_t)1 << 13);
-
-    uint32_t pin_number = (uint32_t)pin;
-    __IO uint32_t *reg = (pin_number < 32) ? (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) : (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
-
-    // set pin to ADC mode
-    *reg &= ~(1 << 7); // set ADMODE = 0 (analog mode)
-
-    uint32_t PCLK = SystemCoreClock;
-    uint32_t MAX_ADC_CLK = 4500000;
-    uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
-
-    LPC_ADC->CR = (0 << 0)      // no channels selected
-                | (clkdiv << 8) // max of 4.5MHz
-                | (0 << 16)     // BURST = 0, software controlled
-                | ( 0 << 17 );  // CLKS = 0, not applicable
-    
-    pinmap_pinout(pin, PinMap_ADC);
-}
-
-static inline uint32_t adc_read(analogin_t *obj) {
-    // Select the appropriate channel and start conversion
-    LPC_ADC->CR &= ~0xFF;
-    LPC_ADC->CR |= 1 << (int)obj->adc;
-    LPC_ADC->CR |= 1 << 24;
-    
-    // Repeatedly get the sample data until DONE bit
-    unsigned int data;
-    do {
-        data = LPC_ADC->GDR;
-    } while ((data & ((unsigned int)1 << 31)) == 0);
-    
-    // Stop conversion
-    LPC_ADC->CR &= ~(1 << 24);
-    
-    return (data >> 6) & ADC_RANGE; // 10 bit
-}
-
-static inline void order(uint32_t *a, uint32_t *b) {
-    if (*a > *b) {
-        uint32_t t = *a;
-        *a = *b;
-        *b = t;
-    }
-}
-
-static inline uint32_t adc_read_u32(analogin_t *obj) {
-    uint32_t value;
-#if ANALOGIN_MEDIAN_FILTER
-    uint32_t v1 = adc_read(obj);
-    uint32_t v2 = adc_read(obj);
-    uint32_t v3 = adc_read(obj);
-    order(&v1, &v2);
-    order(&v2, &v3);
-    order(&v1, &v2);
-    value = v2;
-#else
-    value = adc_read(obj);
-#endif
-    return value;
-}
-
-uint16_t analogin_read_u16(analogin_t *obj) {
-    uint32_t value = adc_read_u32(obj);
-    
-    return (value << 6) | ((value >> 4) & 0x003F); // 10 bit
-}
-
-float analogin_read(analogin_t *obj) {
-    uint32_t value = adc_read_u32(obj);
-    return (float)value * (1.0f / (float)ADC_RANGE);
-}

--- a/vendor/NXP/LPC11U24/hal/device.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,59 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-#define DEVICE_PORTIN           1
-#define DEVICE_PORTOUT          1
-#define DEVICE_PORTINOUT        1
-
-#define DEVICE_INTERRUPTIN      1
-
-#define DEVICE_ANALOGIN         1
-#define DEVICE_ANALOGOUT        0
-
-#define DEVICE_SERIAL           1
-
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
-
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         1
-
-#define DEVICE_CAN              0
-
-#define DEVICE_RTC              0
-
-#define DEVICE_ETHERNET         0
-
-#define DEVICE_PWMOUT           1
-
-#define DEVICE_SEMIHOST         1
-#define DEVICE_LOCALFILESYSTEM  1
-#define DEVICE_ID_LENGTH       32
-#define DEVICE_MAC_OFFSET      20
-
-#define DEVICE_SLEEP            1
-
-#define DEVICE_DEBUG_AWARENESS  0
-
-#define DEVICE_STDIO_MESSAGES   1
-
-#define DEVICE_ERROR_PATTERN    1
-
-#include "objects.h"
-
-#endif

--- a/vendor/NXP/LPC11U24/hal/gpio_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,59 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "gpio_api.h"
-#include "pinmap.h"
-
-uint32_t gpio_set(PinName pin) {
-    int f = ((pin == P0_11) ||
-             (pin == P0_12) ||
-             (pin == P0_13) ||
-             (pin == P0_14)) ? (1) : (0);
-    
-    pin_function(pin, f);
-    
-    return (1 << ((int)pin & 0x1F));
-}
-
-void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
-    if(pin == NC) return;
-
-    obj->pin = pin;
-    obj->mask = gpio_set(pin);
-    
-    unsigned int port = (unsigned int)pin >> PORT_SHIFT;
-    
-    obj->reg_set = &LPC_GPIO->SET[port];
-    obj->reg_clr = &LPC_GPIO->CLR[port];
-    obj->reg_in  = &LPC_GPIO->PIN[port];
-    obj->reg_dir = &LPC_GPIO->DIR[port];
-    
-    gpio_dir(obj, direction);
-    switch (direction) {
-        case PIN_OUTPUT: pin_mode(pin, PullNone); break;
-        case PIN_INPUT : pin_mode(pin, PullDown); break;
-    }
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode) {
-    pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction) {
-    switch (direction) {
-        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
-        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
-    }
-}

--- a/vendor/NXP/LPC11U24/hal/gpio_irq_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,133 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stddef.h>
-#include "cmsis.h"
-#include "gpio_irq_api.h"
-#include "error.h"
-
-#define CHANNEL_NUM    8
-#define LPC_GPIO_X LPC_GPIO_PIN_INT
-#define PININT_IRQ 0
-
-static uint32_t channel_ids[CHANNEL_NUM] = {0};
-static gpio_irq_handler irq_handler;
-
-static inline void handle_interrupt_in(uint32_t channel) {
-    uint32_t ch_bit = (1 << channel);
-    // Return immediately if:
-    //   * The interrupt was already served
-    //   * There is no user handler
-    //   * It is a level interrupt, not an edge interrupt
-    if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
-         (channel_ids[channel] == 0      ) ||
-         (LPC_GPIO_X->ISEL & ch_bit      ) ) return;
-
-    if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
-        irq_handler(channel_ids[channel], IRQ_RISE);
-        LPC_GPIO_X->RISE = ch_bit;
-    }
-    if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
-        irq_handler(channel_ids[channel], IRQ_FALL);
-    }
-    LPC_GPIO_X->IST = ch_bit;
-}
-
-void gpio_irq0(void) {handle_interrupt_in(0);}
-void gpio_irq1(void) {handle_interrupt_in(1);}
-void gpio_irq2(void) {handle_interrupt_in(2);}
-void gpio_irq3(void) {handle_interrupt_in(3);}
-void gpio_irq4(void) {handle_interrupt_in(4);}
-void gpio_irq5(void) {handle_interrupt_in(5);}
-void gpio_irq6(void) {handle_interrupt_in(6);}
-void gpio_irq7(void) {handle_interrupt_in(7);}
-
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
-    if (pin == NC) return -1;
-    
-    irq_handler = handler;
-    
-    int found_free_channel = 0;
-    int i = 0;
-    for (i=0; i<CHANNEL_NUM; i++) {
-        if (channel_ids[i] == 0) {
-            channel_ids[i] = id;
-            obj->ch = i;
-            found_free_channel = 1;
-            break;
-        }
-    }
-    if (!found_free_channel) return -1;
-    
-    /* Enable AHB clock to the GPIO domain. */
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
-    
-    /* Enable AHB clock to the FlexInt, GroupedInt domain. */
-    LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
-    
-    /* To select a pin for any of the eight pin interrupts, write the pin number
-     * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
-     * @see: mbed_capi/PinNames.h
-     */
-    LPC_SYSCON->PINTSEL[obj->ch] = (pin >> 5) ? (pin - 8) : (pin);
-    
-    // Interrupt Wake-Up Enable
-    LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
-    
-    void (*channels_irq)(void) = NULL;
-    switch (obj->ch) {
-        case 0: channels_irq = &gpio_irq0; break;
-        case 1: channels_irq = &gpio_irq1; break;
-        case 2: channels_irq = &gpio_irq2; break;
-        case 3: channels_irq = &gpio_irq3; break;
-        case 4: channels_irq = &gpio_irq4; break;
-        case 5: channels_irq = &gpio_irq5; break;
-        case 6: channels_irq = &gpio_irq6; break;
-        case 7: channels_irq = &gpio_irq7; break;
-    }
-    NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
-    NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
-    
-    return 0;
-}
-
-void gpio_irq_free(gpio_irq_t *obj) {
-    channel_ids[obj->ch] = 0;
-    LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
-}
-
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
-    unsigned int ch_bit = (1 << obj->ch);
-    
-    // Clear interrupt
-    if (!(LPC_GPIO_X->ISEL & ch_bit))
-        LPC_GPIO_X->IST = ch_bit;
-    
-    // Edge trigger
-    LPC_GPIO_X->ISEL &= ~ch_bit;
-    if (event == IRQ_RISE) {
-        if (enable) {
-            LPC_GPIO_X->IENR |= ch_bit;
-        } else {
-            LPC_GPIO_X->IENR &= ~ch_bit;
-        }
-    } else {
-        if (enable) {
-            LPC_GPIO_X->IENF |= ch_bit;
-        } else {
-            LPC_GPIO_X->IENF &= ~ch_bit;
-        }
-    }
-}

--- a/vendor/NXP/LPC11U24/hal/gpio_object.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    PinName  pin;
-    uint32_t mask;
-
-    __IO uint32_t *reg_dir;
-    __IO uint32_t *reg_set;
-    __IO uint32_t *reg_clr;
-    __I  uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
-    if (value)
-        *obj->reg_set = obj->mask;
-    else
-        *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
-    return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC11U24/hal/i2c_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,380 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "i2c_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_I2C_SDA[] = {
-    {P0_5, I2C_0, 1},
-    {NC  , NC   , 0}
-};
-
-static const PinMap PinMap_I2C_SCL[] = {
-    {P0_4, I2C_0, 1},
-    {NC  , NC,    0}
-};
-
-#define I2C_CONSET(x)       (x->i2c->CONSET)
-#define I2C_CONCLR(x)       (x->i2c->CONCLR)
-#define I2C_STAT(x)         (x->i2c->STAT)
-#define I2C_DAT(x)          (x->i2c->DAT)
-#define I2C_SCLL(x, val)    (x->i2c->SCLL = val)
-#define I2C_SCLH(x, val)    (x->i2c->SCLH = val)
-
-static const uint32_t I2C_addr_offset[2][4] = {
-    {0x0C, 0x20, 0x24, 0x28},
-    {0x30, 0x34, 0x38, 0x3C}
-};
-
-static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
-    I2C_CONCLR(obj) = (start << 5)
-                    | (stop << 4)
-                    | (interrupt << 3)
-                    | (acknowledge << 2);
-}
-
-static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
-    I2C_CONSET(obj) = (start << 5)
-                    | (stop << 4)
-                    | (interrupt << 3)
-                    | (acknowledge << 2);
-}
-
-// Clear the Serial Interrupt (SI)
-static inline void i2c_clear_SI(i2c_t *obj) {
-    i2c_conclr(obj, 0, 0, 1, 0);
-}
-
-static inline int i2c_status(i2c_t *obj) {
-    return I2C_STAT(obj);
-}
-
-// Wait until the Serial Interrupt (SI) is set
-static int i2c_wait_SI(i2c_t *obj) {
-    int timeout = 0;
-    while (!(I2C_CONSET(obj) & (1 << 3))) {
-        timeout++;
-        if (timeout > 100000) return -1;
-    }
-    return 0;
-}
-
-static inline void i2c_interface_enable(i2c_t *obj) {
-    I2C_CONSET(obj) = 0x40;
-}
-
-static inline void i2c_power_enable(i2c_t *obj) {
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5);
-    LPC_SYSCON->PRESETCTRL |= 1 << 1;
-}
-
-void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
-    // determine the SPI to use
-    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
-    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
-    obj->i2c = (LPC_I2C_Type *)pinmap_merge(i2c_sda, i2c_scl);
-    
-    if ((int)obj->i2c == NC) {
-        error("I2C pin mapping failed");
-    }
-    
-    // enable power
-    i2c_power_enable(obj);
-    
-    // set default frequency at 100k
-    i2c_frequency(obj, 100000);
-    i2c_conclr(obj, 1, 1, 1, 1);
-    i2c_interface_enable(obj);
-    
-    pinmap_pinout(sda, PinMap_I2C_SDA);
-    pinmap_pinout(scl, PinMap_I2C_SCL);
-}
-
-inline int i2c_start(i2c_t *obj) {
-    int status = 0;
-    // 8.1 Before master mode can be entered, I2CON must be initialised to:
-    //  - I2EN STA STO SI AA - -
-    //  -  1    0   0   0  x - -
-    // if AA = 0, it can't enter slave mode
-    i2c_conclr(obj, 1, 1, 1, 1);
-    
-    // The master mode may now be entered by setting the STA bit
-    // this will generate a start condition when the bus becomes free
-    i2c_conset(obj, 1, 0, 0, 1);
-    
-    i2c_wait_SI(obj);
-    status = i2c_status(obj);
-    
-    // Clear start bit now transmitted, and interrupt bit
-    i2c_conclr(obj, 1, 0, 0, 0);
-    return status;
-}
-
-inline void i2c_stop(i2c_t *obj) {
-    // write the stop bit
-    i2c_conset(obj, 0, 1, 0, 0);
-    i2c_clear_SI(obj);
-    
-    // wait for STO bit to reset
-    while(I2C_CONSET(obj) & (1 << 4));
-}
-
-
-static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
-    // write the data
-    I2C_DAT(obj) = value;
-    
-    // clear SI to init a send
-    i2c_clear_SI(obj);
-    
-    // wait and return status
-    i2c_wait_SI(obj);
-    return i2c_status(obj);
-}
-
-static inline int i2c_do_read(i2c_t *obj, int last) {
-    // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
-    if (last) {
-        i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
-    } else {
-        i2c_conset(obj, 0, 0, 0, 1); // send a ACK
-    }
-    
-    // accept byte
-    i2c_clear_SI(obj);
-    
-    // wait for it to arrive
-    i2c_wait_SI(obj);
-    
-    // return the data
-    return (I2C_DAT(obj) & 0xFF);
-}
-
-void i2c_frequency(i2c_t *obj, int hz) {
-    // No peripheral clock divider on the M0
-    uint32_t PCLK = SystemCoreClock;
-    
-    uint32_t pulse = PCLK / (hz * 2);
-    
-    // I2C Rate
-    I2C_SCLL(obj, pulse);
-    I2C_SCLH(obj, pulse);
-}
-
-// The I2C does a read or a write as a whole operation
-// There are two types of error conditions it can encounter
-//  1) it can not obtain the bus
-//  2) it gets error responses at part of the transmission
-//
-// We tackle them as follows:
-//  1) we retry until we get the bus. we could have a "timeout" if we can not get it
-//      which basically turns it in to a 2)
-//  2) on error, we use the standard error mechanisms to report/debug
-//
-// Therefore an I2C transaction should always complete. If it doesn't it is usually
-// because something is setup wrong (e.g. wiring), and we don't need to programatically
-// check for that
-
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
-    int count, status;
-    
-    status = i2c_start(obj);
-    
-    if ((status != 0x10) && (status != 0x08)) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    status = i2c_do_write(obj, (address | 0x01), 1);
-    if (status != 0x40) {
-        i2c_stop(obj);
-        return status;
-    }
-
-    // Read in all except last byte
-    for (count = 0; count < (length - 1); count++) {
-        int value = i2c_do_read(obj, 0);
-        status = i2c_status(obj);
-        if (status != 0x50) {
-            i2c_stop(obj);
-            return status;
-        }
-        data[count] = (char) value;
-    }
-
-    // read in last byte
-    int value = i2c_do_read(obj, 1);
-    status = i2c_status(obj);
-    if (status != 0x58) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    data[count] = (char) value;
-    
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-    }
-    
-    return 0;
-}
-
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
-    int i, status;
-    
-    status = i2c_start(obj);
-    
-    if ((status != 0x10) && (status != 0x08)) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    status = i2c_do_write(obj, (address & 0xFE), 1);
-    if (status != 0x18) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    for (i=0; i<length; i++) {
-        status = i2c_do_write(obj, data[i], 0);
-        if(status != 0x28) {
-            i2c_stop(obj);
-            return status;
-        }
-    }
-    
-    // clearing the serial interrupt here might cause an unintended rewrite of the last byte
-    // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
-    // i2c_clear_SI(obj);
-    
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-    }
-    
-    return 0;
-}
-
-void i2c_reset(i2c_t *obj) {
-    i2c_stop(obj);
-}
-
-int i2c_byte_read(i2c_t *obj, int last) {
-    return (i2c_do_read(obj, last) & 0xFF);
-}
-
-int i2c_byte_write(i2c_t *obj, int data) {
-    int ack;
-    int status = i2c_do_write(obj, (data & 0xFF), 0);
-    
-    switch(status) {
-        case 0x18: case 0x28:       // Master transmit ACKs
-            ack = 1;
-            break;
-        case 0x40:                  // Master receive address transmitted ACK
-            ack = 1;
-            break;
-        case 0xB8:                  // Slave transmit ACK
-            ack = 1;
-            break;
-        default:
-            ack = 0;
-            break;
-    }
-
-    return ack;
-}
-
-void i2c_slave_mode(i2c_t *obj, int enable_slave) {
-    if (enable_slave != 0) {
-        i2c_conclr(obj, 1, 1, 1, 0);
-        i2c_conset(obj, 0, 0, 0, 1);
-    } else {
-        i2c_conclr(obj, 1, 1, 1, 1);
-    }
-}
-
-int i2c_slave_receive(i2c_t *obj) {
-    int status;
-    int retval;
-    
-    status = i2c_status(obj);
-    switch(status) {
-        case 0x60: retval = 3; break;
-        case 0x70: retval = 2; break;
-        case 0xA8: retval = 1; break;
-        default  : retval = 0; break;
-    }
-    
-    return(retval);
-}
-
-int i2c_slave_read(i2c_t *obj, char *data, int length) {
-    int count = 0;
-    int status;
-    
-    do {
-        i2c_clear_SI(obj);
-        i2c_wait_SI(obj);
-        status = i2c_status(obj);
-        if((status == 0x80) || (status == 0x90)) {
-            data[count] = I2C_DAT(obj) & 0xFF;
-        }
-        count++;
-    } while (((status == 0x80) || (status == 0x90) ||
-            (status == 0x060) || (status == 0x70)) && (count < length));
-    
-    if(status != 0xA0) {
-        i2c_stop(obj);
-    }
-    
-    i2c_clear_SI(obj);
-    
-    return (count - 1);
-}
-
-int i2c_slave_write(i2c_t *obj, const char *data, int length) {
-    int count = 0;
-    int status;
-    
-    if(length <= 0) {
-        return(0);
-    }
-    
-    do {
-        status = i2c_do_write(obj, data[count], 0);
-        count++;
-    } while ((count < length) && (status == 0xB8));
-    
-    if((status != 0xC0) && (status != 0xC8)) {
-        i2c_stop(obj);
-    }
-    
-    i2c_clear_SI(obj);
-    
-    return(count);
-}
-
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
-    uint32_t addr;
-    
-    if ((idx >= 0) && (idx <= 3)) {
-        addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
-        *((uint32_t *) addr) = address & 0xFF;
-    }
-}

--- a/vendor/NXP/LPC11U24/hal/objects.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    uint32_t ch;
-};
-
-struct port_s {
-    __IO uint32_t *reg_dir;
-    __IO uint32_t *reg_mpin;
-    PortName port;
-    uint32_t mask;
-};
-
-struct pwmout_s {
-    PWMName pwm;
-};
-
-struct serial_s {
-    LPC_USART_Type *uart;
-    int index;
-};
-
-struct analogin_s {
-    ADCName adc;
-};
-
-struct i2c_s {
-    LPC_I2C_Type *i2c;
-};
-
-struct spi_s {
-    LPC_SSPx_Type *spi;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC11U24/hal/pinmap.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "pinmap.h"
-#include "error.h"
-
-#define LPC_IOCON0_BASE (LPC_IOCON_BASE)
-#define LPC_IOCON1_BASE (LPC_IOCON_BASE + 0x60)
-
-void pin_function(PinName pin, int function) {
-    if (pin == (uint32_t)NC) return;
-    
-    uint32_t pin_number = (uint32_t)pin;
-    
-    __IO uint32_t *reg = (pin_number < 32) ?
-            (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
-            (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
-    
-    // pin function bits: [2:0] -> 111 = (0x7)
-    *reg = (*reg & ~0x7) | (function & 0x7);
-}
-
-void pin_mode(PinName pin, PinMode mode) {
-    if (pin == (uint32_t)NC) { return; }
-    
-    uint32_t pin_number = (uint32_t)pin;
-    uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2;
-    
-    __IO uint32_t *reg = (pin_number < 32) ?
-            (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
-            (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
-    uint32_t tmp = *reg;
-    
-    // pin mode bits: [4:3] -> 11000 = (0x3 << 3)
-    tmp &= ~(0x3 << 3);
-    tmp |= (mode & 0x3) << 3;
-    
-    // drain
-    tmp &= ~(0x1 << 10);
-    tmp |= drain << 10;
-    
-    *reg = tmp;
-}

--- a/vendor/NXP/LPC11U24/hal/port_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,67 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "port_api.h"
-#include "pinmap.h"
-#include "gpio_api.h"
-
-PinName port_pin(PortName port, int pin_n) {
-    return (PinName)((port << PORT_SHIFT) | pin_n);
-}
-
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
-    obj->port = port;
-    obj->mask = mask;
-    
-    LPC_GPIO->MASK[port] = ~mask;
-    
-    obj->reg_mpin = &LPC_GPIO->MPIN[port];
-    obj->reg_dir = &LPC_GPIO->DIR[port];
-    
-    uint32_t i;
-    // The function is set per pin: reuse gpio logic
-    for (i=0; i<32; i++) {
-        if (obj->mask & (1<<i)) {
-            gpio_set(port_pin(obj->port, i));
-        }
-    }
-    
-    port_dir(obj, dir);
-}
-
-void port_mode(port_t *obj, PinMode mode) {
-    uint32_t i;
-    // The mode is set per pin: reuse pinmap logic
-    for (i=0; i<32; i++) {
-        if (obj->mask & (1<<i)) {
-            pin_mode(port_pin(obj->port, i), mode);
-        }
-    }
-}
-
-void port_dir(port_t *obj, PinDirection dir) {
-    switch (dir) {
-        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
-        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
-    }
-}
-
-void port_write(port_t *obj, int value) {
-    *obj->reg_mpin = value;
-}
-
-int port_read(port_t *obj) {
-    return (*obj->reg_mpin);
-}

--- a/vendor/NXP/LPC11U24/hal/pwmout_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,183 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "pwmout_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-#define TCR_CNT_EN       0x00000001
-#define TCR_RESET        0x00000002
-
-/* To have a PWM where we can change both the period and the duty cycle,
- * we need an entire timer. With the following conventions:
- *   * MR3 is used for the PWM period
- *   * MR0, MR1, MR2 are used for the duty cycle
- */
-static const PinMap PinMap_PWM[] = {
-    /* CT16B0 */
-    {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2},    /* MR0 */
-    {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2},   /* MR1 */
-    {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2},   /* MR2 */
-
-    /* CT16B1 */
-    {P0_21, PWM_4, 1},                      /* MR0 */
-    {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1},   /* MR1 */
-
-    /* CT32B0 */
-    {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1},   /* MR0 */
-    {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1},   /* MR1 */
-    {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1},   /* MR2 */
-
-    /* CT32B1 */
-    {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1},  /* MR0 */
-    {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1},  /* MR1 */
-    {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1},  /* MR2 */
-
-    {NC, NC, 0}
-};
-
-typedef struct {
-    uint8_t timer;
-    uint8_t mr;
-} timer_mr;
-
-static timer_mr pwm_timer_map[11] = {
-    {0, 0}, {0, 1}, {0, 2},
-    {1, 0}, {1, 1},
-    {2, 0}, {2, 1}, {2, 2},
-    {3, 0}, {3, 1}, {3, 2},
-};
-
-static LPC_CTxxBx_Type *Timers[4] = {
-    LPC_CT16B0, LPC_CT16B1,
-    LPC_CT32B0, LPC_CT32B1
-};
-
-static unsigned int pwm_clock_mhz;
-
-void pwmout_init(pwmout_t* obj, PinName pin) {
-    // determine the channel
-    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
-    if (pwm == (uint32_t)NC)
-        error("PwmOut pin mapping failed");
-    
-    obj->pwm = pwm;
-    
-    // Timer registers
-    timer_mr tid = pwm_timer_map[pwm];
-    LPC_CTxxBx_Type *timer = Timers[tid.timer];
-    
-    // Disable timer
-    timer->TCR = 0;
-    
-    // Power the correspondent timer
-    LPC_SYSCON->SYSAHBCLKCTRL |= 1 << (tid.timer + 7);
-    
-    /* Enable PWM function */
-    timer->PWMC = (1 << 3)|(1 << 2)|(1 << 1)|(1 << 0);
-    
-    /* Reset Functionality on MR3 controlling the PWM period */
-    timer->MCR = 1 << 10;
-    
-    pwm_clock_mhz = SystemCoreClock / 1000000;
-    
-    // default to 20ms: standard for servos, and fine for e.g. brightness control
-    pwmout_period_ms(obj, 20);
-    pwmout_write    (obj, 0);
-    
-    // Wire pinout
-    pinmap_pinout(pin, PinMap_PWM);
-}
-
-void pwmout_free(pwmout_t* obj) {
-    // [TODO]
-}
-
-void pwmout_write(pwmout_t* obj, float value) {
-    if (value < 0.0f) {
-        value = 0.0;
-    } else if (value > 1.0f) {
-        value = 1.0;
-    }
-    
-    timer_mr tid = pwm_timer_map[obj->pwm];
-    LPC_CTxxBx_Type *timer = Timers[tid.timer];
-    uint32_t t_off = timer->MR3 - (uint32_t)((float)(timer->MR3) * value);
-    
-    timer->TCR = TCR_RESET;
-    timer->MR[tid.mr] = t_off;
-    timer->TCR = TCR_CNT_EN;
-}
-
-float pwmout_read(pwmout_t* obj) {
-    timer_mr tid = pwm_timer_map[obj->pwm];
-    LPC_CTxxBx_Type *timer = Timers[tid.timer];
-    
-    float v = (float)(timer->MR3 - timer->MR[tid.mr]) / (float)(timer->MR3);
-    return (v > 1.0f) ? (1.0f) : (v);
-}
-
-void pwmout_period(pwmout_t* obj, float seconds) {
-    pwmout_period_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_period_ms(pwmout_t* obj, int ms) {
-    pwmout_period_us(obj, ms * 1000);
-}
-
-// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
-    int i = 0;
-    uint32_t period_ticks = pwm_clock_mhz * us;
-    
-    timer_mr tid = pwm_timer_map[obj->pwm];
-    LPC_CTxxBx_Type *timer = Timers[tid.timer];
-    uint32_t old_period_ticks = timer->MR3;
-    
-    timer->TCR = TCR_RESET;
-    timer->MR3 = period_ticks;
-    
-    // Scale the pulse width to preserve the duty ratio
-    if (old_period_ticks > 0) {
-        for (i=0; i<3; i++) {
-            uint32_t t_off = period_ticks - (uint32_t)(((uint64_t)timer->MR[i] * (uint64_t)period_ticks) / (uint64_t)old_period_ticks);
-            timer->MR[i] = t_off;
-        }
-    }
-    timer->TCR = TCR_CNT_EN;
-}
-
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
-    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
-    pwmout_pulsewidth_us(obj, ms * 1000);
-}
-
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
-    uint32_t t_on = (uint32_t)(((uint64_t)SystemCoreClock * (uint64_t)us) / (uint64_t)1000000);
-    timer_mr tid = pwm_timer_map[obj->pwm];
-    LPC_CTxxBx_Type *timer = Timers[tid.timer];
-    
-    timer->TCR = TCR_RESET;
-    if (t_on > timer->MR3) {
-        pwmout_period_us(obj, us);
-    }
-    uint32_t t_off = timer->MR3 - t_on;
-    timer->MR[tid.mr] = t_off;
-    timer->TCR = TCR_CNT_EN;
-}

--- a/vendor/NXP/LPC11U24/hal/serial_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,273 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// math.h required for floating point operations for baud rate calculation
-#include <math.h>
-#include <string.h>
-
-#include "serial_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-/******************************************************************************
- * INITIALIZATION
- ******************************************************************************/
-#define UART_NUM    1
-
-static const PinMap PinMap_UART_TX[] = {
-    {P0_19, UART_0, 1},
-    {P1_13, UART_0, 3},
-    {P1_27, UART_0, 2},
-    { NC  , NC    , 0}
-};
-
-static const PinMap PinMap_UART_RX[] = {
-    {P0_18, UART_0, 1},
-    {P1_14, UART_0, 3},
-    {P1_26, UART_0, 2},
-    {NC   , NC    , 0}
-};
-
-static uint32_t serial_irq_ids[UART_NUM] = {0};
-static uart_irq_handler irq_handler;
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
-    int is_stdio_uart = 0;
-    
-    // determine the UART to use
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-    UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    if ((int)uart == NC) {
-        error("Serial pinout mapping failed");
-    }
-    
-    obj->uart = (LPC_USART_Type *)uart;
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
-    
-    // [TODO] Consider more elegant approach
-    // disconnect USBTX/RX mapping mux, for case when switching ports
-    pin_function(USBTX, 0);
-    pin_function(USBRX, 0);
-    
-    // enable fifos and default rx trigger level
-    obj->uart->FCR = 1 << 0  // FIFO Enable - 0 = Disables, 1 = Enabled
-                   | 0 << 1  // Rx Fifo Reset
-                   | 0 << 2  // Tx Fifo Reset
-                   | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
-    
-    // disable irqs
-    obj->uart->IER = 0 << 0  // Rx Data available irq enable
-                   | 0 << 1  // Tx Fifo empty irq enable
-                   | 0 << 2; // Rx Line Status irq enable
-    
-    // set default baud rate and format
-    serial_baud  (obj, 9600);
-    serial_format(obj, 8, ParityNone, 1);
-    
-    // pinout the chosen uart
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    
-    // set rx/tx pins in PullUp mode
-    pin_mode(tx, PullUp);
-    pin_mode(rx, PullUp);
-    
-    switch (uart) {
-        case UART_0: obj->index = 0; break;
-    }
-    
-    is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
-    
-    if (is_stdio_uart) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj) {
-    serial_irq_ids[obj->index] = 0;
-}
-
-// serial_baud
-// set the baud rate, taking in to account the current SystemFrequency
-void serial_baud(serial_t *obj, int baudrate) {
-    LPC_SYSCON->UARTCLKDIV = 0x1;
-    uint32_t PCLK = SystemCoreClock;
-    // First we check to see if the basic divide with no DivAddVal/MulVal
-    // ratio gives us an integer result. If it does, we set DivAddVal = 0,
-    // MulVal = 1. Otherwise, we search the valid ratio value range to find
-    // the closest match. This could be more elegant, using search methods
-    // and/or lookup tables, but the brute force method is not that much
-    // slower, and is more maintainable.
-    uint16_t DL = PCLK / (16 * baudrate);
-    
-    uint8_t DivAddVal = 0;
-    uint8_t MulVal = 1;
-    int hit = 0;
-    uint16_t dlv;
-    uint8_t mv, dav;
-    if ((PCLK % (16 * baudrate)) != 0) {     // Checking for zero remainder
-        float err_best = (float) baudrate;
-        uint16_t dlmax = DL;
-        for ( dlv = (dlmax/2); (dlv <= dlmax) && !hit; dlv++) {
-            for ( mv = 1; mv <= 15; mv++) {
-                for ( dav = 1; dav < mv; dav++) {
-                    float ratio = 1.0f + ((float) dav / (float) mv);
-                    float calcbaud = (float)PCLK / (16.0f * (float) dlv * ratio);
-                    float err = fabs(((float) baudrate - calcbaud) / (float) baudrate);
-                    if (err < err_best) {
-                        DL = dlv;
-                        DivAddVal = dav;
-                        MulVal = mv;
-                        err_best = err;
-                        if (err < 0.001f) {
-                            hit = 1;
-                        }
-                    }
-                }
-            }
-        }
-    }
-    
-    // set LCR[DLAB] to enable writing to divider registers
-    obj->uart->LCR |= (1 << 7);
-    
-    // set divider values
-    obj->uart->DLM = (DL >> 8) & 0xFF;
-    obj->uart->DLL = (DL >> 0) & 0xFF;
-    obj->uart->FDR = (uint32_t) DivAddVal << 0
-                   | (uint32_t) MulVal    << 4;
-    
-    // clear LCR[DLAB]
-    obj->uart->LCR &= ~(1 << 7);
-}
-
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
-    // 0: 1 stop bits, 1: 2 stop bits
-    if (stop_bits != 1 && stop_bits != 2) {
-        error("Invalid stop bits specified");
-    }
-    stop_bits -= 1;
-    
-    // 0: 5 data bits ... 3: 8 data bits
-    if (data_bits < 5 || data_bits > 8) {
-        error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
-    }
-    data_bits -= 5;
-
-    int parity_enable, parity_select;
-    switch (parity) {
-        case ParityNone: parity_enable = 0; parity_select = 0; break;
-        case ParityOdd : parity_enable = 1; parity_select = 0; break;
-        case ParityEven: parity_enable = 1; parity_select = 1; break;
-        case ParityForced1: parity_enable = 1; parity_select = 2; break;
-        case ParityForced0: parity_enable = 1; parity_select = 3; break;
-        default:
-            error("Invalid serial parity setting");
-            return;
-    }
-    
-    obj->uart->LCR = data_bits            << 0
-                   | stop_bits            << 2
-                   | parity_enable        << 3
-                   | parity_select        << 4;
-}
-
-/******************************************************************************
- * INTERRUPTS HANDLING
- ******************************************************************************/
-static inline void uart_irq(uint32_t iir, uint32_t index) {
-    // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
-    SerialIrq irq_type;
-    switch (iir) {
-        case 1: irq_type = TxIrq; break;
-        case 2: irq_type = RxIrq; break;
-        default: return;
-    }
-    
-    if (serial_irq_ids[index] != 0)
-        irq_handler(serial_irq_ids[index], irq_type);
-}
-
-void uart0_irq() {uart_irq((LPC_USART->IIR >> 1) & 0x7, 0);}
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
-    irq_handler = handler;
-    serial_irq_ids[obj->index] = id;
-}
-
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
-    IRQn_Type irq_n = (IRQn_Type)0;
-    uint32_t vector = 0;
-    switch ((int)obj->uart) {
-        case UART_0: irq_n=UART_IRQn ; vector = (uint32_t)&uart0_irq; break;
-    }
-    
-    if (enable) {
-        obj->uart->IER |= 1 << irq;
-        NVIC_SetVector(irq_n, vector);
-        NVIC_EnableIRQ(irq_n);
-    } else { // disable
-        int all_disabled = 0;
-        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
-
-        obj->uart->IER &= ~(1 << irq);
-        all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
-        
-        if (all_disabled)
-            NVIC_DisableIRQ(irq_n);
-    }
-}
-
-/******************************************************************************
- * READ/WRITE
- ******************************************************************************/
-int serial_getc(serial_t *obj) {
-    while (!serial_readable(obj));
-    return obj->uart->RBR;
-}
-
-void serial_putc(serial_t *obj, int c) {
-    while (!serial_writable(obj));
-    obj->uart->THR = c;
-    
-    uint32_t lsr = obj->uart->LSR;
-    lsr = lsr;
-    uint32_t thr = obj->uart->THR;
-    thr = thr;
-}
-
-int serial_readable(serial_t *obj) {
-    return obj->uart->LSR & 0x01;
-}
-
-int serial_writable(serial_t *obj) {
-    return obj->uart->LSR & 0x20;
-}
-
-void serial_clear(serial_t *obj) {
-    obj->uart->FCR = 1 << 1  // rx FIFO reset
-                   | 1 << 2  // tx FIFO reset
-                   | 0 << 6; // interrupt depth
-}
-
-void serial_pinout_tx(PinName tx) {
-    pinmap_pinout(tx, PinMap_UART_TX);
-}

--- a/vendor/NXP/LPC11U24/hal/sleep.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "sleep_api.h"
-#include "cmsis.h"
-#include "mbed_interface.h"
-
-void sleep(void) {
-    // ensure debug is disconnected
-    mbed_interface_disconnect();
-    
-    // PCON[PD] set to sleep
-    LPC_PMU->PCON = 0x0;
-    
-    // SRC[SLEEPDEEP] set to 0 = sleep
-    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
-    
-    // wait for interrupt
-    __WFI();
-}
-
-/*
-* The mbed lpc1768 does not support the deepsleep mode
-* as a debugger is connected to it (the mbed interface).
-*
-* As mentionned in an application note from NXP:
-*
-*       http://www.po-star.com/public/uploads/20120319123122_141.pdf
-*
-*       {{{
-*       The user should be aware of certain limitations during debugging.
-*       The most important is that, due to limitations of the Cortex-M3
-*       integration, the LPC17xx cannot wake up in the usual manner from
-*       Deep Sleep and Power-down modes. It is recommended not to use these
-*       modes during debug. Once an application is downloaded via JTAG/SWD
-*       interface, the USB to SWD/JTAG debug adapter (Keil ULINK2 for example)
-*       should be removed from the target board, and thereafter, power cycle
-*       the LPC17xx to allow wake-up from deep sleep and power-down modes
-*       }}}
-*
-*       As the interface firmware does not reset the target when a
-*       mbed_interface_disconnect() semihosting call is made, the
-*       core cannot wake-up from deepsleep.
-*
-*       We treat a deepsleep() as a normal sleep().
-*/
-
-void deepsleep(void) {
-    // ensure debug is disconnected
-    mbed_interface_disconnect();
-    
-    // PCON[PD] set to deepsleep
-    LPC_PMU->PCON = 0x1;
-    
-    // SRC[SLEEPDEEP] set to 1 = deep sleep
-    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-    
-    // Power up everything after powerdown
-    LPC_SYSCON->PDAWAKECFG &= 0xFFFFF800;
-    
-    // wait for interrupt
-    __WFI();
-}

--- a/vendor/NXP/LPC11U24/hal/spi_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,218 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <math.h>
-#include "spi_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_SPI_SCLK[] = {
-    {P0_6 , SPI_0, 0x02},
-    {P0_10, SPI_0, 0x02},
-    {P1_29, SPI_0, 0x01},
-    {P1_15, SPI_1, 0x03},
-    {P1_20, SPI_1, 0x02},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_MOSI[] = {
-    {P0_9 , SPI_0, 0x01},
-    {P0_21, SPI_1, 0x02},
-    {P1_22, SPI_1, 0x02},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_MISO[] = {
-    {P0_8 , SPI_0, 0x01},
-    {P0_22, SPI_1, 0x03},
-    {P1_21, SPI_1, 0x02},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_SSEL[] = {
-    {P0_2 , SPI_0, 0x01},
-    {P1_19, SPI_1, 0x02},
-    {P1_23, SPI_1, 0x02},
-    {NC   , NC   , 0}
-};
-
-static inline int ssp_disable(spi_t *obj);
-static inline int ssp_enable(spi_t *obj);
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
-    // determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-    
-    obj->spi = (LPC_SSPx_Type*)pinmap_merge(spi_data, spi_cntl);
-    
-    if ((int)obj->spi == NC) {
-        error("SPI pinout mapping failed");
-    }
-    
-    // enable power and clocking
-    switch ((int)obj->spi) {
-        case SPI_0:
-            LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11;
-            LPC_SYSCON->SSP0CLKDIV = 0x01;
-            LPC_SYSCON->PRESETCTRL |= 1 << 0;
-            break;
-        case SPI_1:
-            LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18;
-            LPC_SYSCON->SSP1CLKDIV = 0x01;
-            LPC_SYSCON->PRESETCTRL |= 1 << 2;
-            break;
-    }
-    
-    // set default format and frequency
-    if (ssel == NC) {
-        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
-    } else {
-        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
-    }
-    spi_frequency(obj, 1000000);
-    
-    // enable the ssp channel
-    ssp_enable(obj);
-    
-    // pin out the spi pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    }
-}
-
-void spi_free(spi_t *obj) {}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
-    ssp_disable(obj);
-    
-    if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
-        error("SPI format error");
-    }
-    
-    int polarity = (mode & 0x2) ? 1 : 0;
-    int phase = (mode & 0x1) ? 1 : 0;
-    
-    // set it up
-    int DSS = bits - 1;            // DSS (data select size)
-    int SPO = (polarity) ? 1 : 0;  // SPO - clock out polarity
-    int SPH = (phase) ? 1 : 0;     // SPH - clock out phase
-    
-    int FRF = 0;                   // FRF (frame format) = SPI
-    uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
-    tmp |= DSS << 0
-        | FRF << 4
-        | SPO << 6
-        | SPH << 7;
-    obj->spi->CR0 = tmp;
-    
-    tmp = obj->spi->CR1;
-    tmp &= ~(0xD);
-    tmp |= 0 << 0                   // LBM - loop back mode - off
-        | ((slave) ? 1 : 0) << 2   // MS - master slave mode, 1 = slave
-        | 0 << 3;                  // SOD - slave output disable - na
-    obj->spi->CR1 = tmp;
-    
-    ssp_enable(obj);
-}
-
-void spi_frequency(spi_t *obj, int hz) {
-    ssp_disable(obj);
-    
-    uint32_t PCLK = SystemCoreClock;
-    
-    int prescaler;
-    
-    for (prescaler = 2; prescaler <= 254; prescaler += 2) {
-        int prescale_hz = PCLK / prescaler;
-        
-        // calculate the divider
-        int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
-        
-        // check we can support the divider
-        if (divider < 256) {
-            // prescaler
-            obj->spi->CPSR = prescaler;
-            
-            // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
-            obj->spi->CR0 |= (divider - 1) << 8;
-            ssp_enable(obj);
-            return;
-        }
-    }
-    error("Couldn't setup requested SPI frequency");
-}
-
-static inline int ssp_disable(spi_t *obj) {
-    return obj->spi->CR1 &= ~(1 << 1);
-}
-
-static inline int ssp_enable(spi_t *obj) {
-    return obj->spi->CR1 |= (1 << 1);
-}
-
-static inline int ssp_readable(spi_t *obj) {
-    return obj->spi->SR & (1 << 2);
-}
-
-static inline int ssp_writeable(spi_t *obj) {
-    return obj->spi->SR & (1 << 1);
-}
-
-static inline void ssp_write(spi_t *obj, int value) {
-    while (!ssp_writeable(obj));
-    obj->spi->DR = value;
-}
-
-static inline int ssp_read(spi_t *obj) {
-    while (!ssp_readable(obj));
-    return obj->spi->DR;
-}
-
-static inline int ssp_busy(spi_t *obj) {
-    return (obj->spi->SR & (1 << 4)) ? (1) : (0);
-}
-
-int spi_master_write(spi_t *obj, int value) {
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj) {
-    return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
-};
-
-int spi_slave_read(spi_t *obj) {
-    return obj->spi->DR;
-}
-
-void spi_slave_write(spi_t *obj, int value) {
-    while (ssp_writeable(obj) == 0) ;
-    obj->spi->DR = value;
-}
-
-int spi_busy(spi_t *obj) {
-    return ssp_busy(obj);
-}

--- a/vendor/NXP/LPC11U24/hal/us_ticker.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,62 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stddef.h>
-#include "us_ticker_api.h"
-#include "PeripheralNames.h"
-
-#define US_TICKER_TIMER          ((LPC_CTxxBx_Type *)LPC_CT32B1_BASE)
-#define US_TICKER_TIMER_IRQn     TIMER_32_1_IRQn
-
-int us_ticker_inited = 0;
-
-void us_ticker_init(void) {
-    if (us_ticker_inited) return;
-    us_ticker_inited = 1;
-    
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10); // Clock TIMER_1
-    uint32_t PCLK = SystemCoreClock;
-    
-    US_TICKER_TIMER->TCR = 0x2;  // reset
-    
-    uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks)
-    US_TICKER_TIMER->PR = prescale - 1;
-    US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0
-    
-    NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
-    NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
-}
-
-uint32_t us_ticker_read() {
-    if (!us_ticker_inited)
-        us_ticker_init();
-    
-    return US_TICKER_TIMER->TC;
-}
-
-void us_ticker_set_interrupt(unsigned int timestamp) {
-    // set match value
-    US_TICKER_TIMER->MR0 = timestamp;
-    // enable match interrupt
-    US_TICKER_TIMER->MCR |= 1;
-}
-
-void us_ticker_disable_interrupt(void) {
-    US_TICKER_TIMER->MCR &= ~1;
-}
-
-void us_ticker_clear_interrupt(void) {
-    US_TICKER_TIMER->IR = 1;
-}

--- a/vendor/NXP/LPC1768/cmsis/ARM/LPC1768.sct	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,22 +0,0 @@
-
-LR_IROM1 0x00000000 0x80000  {    ; load region size_region
-  ER_IROM1 0x00000000 0x80000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; 8_byte_aligned(49 vect * 4 bytes) =  8_byte_aligned(0xC4) = 0xC8
-  ; 32KB - 0xC8 = 0x7F38
-  RW_IRAM1 0x100000C8 0x7F38  {
-   .ANY (+RW +ZI)
-  }
-  RW_IRAM2 0x2007C000 0x4000  {  ; RW data, ETH RAM
-   .ANY (AHBSRAM0)
-  }
-  RW_IRAM3 0x20080000 0x4000  {  ; RW data, ETH RAM
-   .ANY (AHBSRAM1)
-  }
-  RW_IRAM4 0x40038000 0x0800  {  ; RW data, CAN RAM
-   .ANY (CANRAM)
-  }
-}

--- a/vendor/NXP/LPC1768/cmsis/ARM/startup_LPC17xx.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,226 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC17xx.s
-; * @purpose: CMSIS Cortex-M3 Core Device Startup File 
-; *           for the NXP LPC17xx Device Series 
-; * @version: V1.02, modified for mbed
-; * @date:    27. July 2009, modified 3rd Aug 2009
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2009 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
-; * processor based microcontrollers.  This file can be freely distributed 
-; * within development tools that are supporting such ARM based processors. 
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-__initial_sp        EQU     0x10008000  ; Top of RAM from LPC1768
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ; 16: Watchdog Timer
-                DCD     TIMER0_IRQHandler         ; 17: Timer0
-                DCD     TIMER1_IRQHandler         ; 18: Timer1
-                DCD     TIMER2_IRQHandler         ; 19: Timer2
-                DCD     TIMER3_IRQHandler         ; 20: Timer3
-                DCD     UART0_IRQHandler          ; 21: UART0
-                DCD     UART1_IRQHandler          ; 22: UART1
-                DCD     UART2_IRQHandler          ; 23: UART2
-                DCD     UART3_IRQHandler          ; 24: UART3
-                DCD     PWM1_IRQHandler           ; 25: PWM1
-                DCD     I2C0_IRQHandler           ; 26: I2C0
-                DCD     I2C1_IRQHandler           ; 27: I2C1
-                DCD     I2C2_IRQHandler           ; 28: I2C2
-                DCD     SPI_IRQHandler            ; 29: SPI
-                DCD     SSP0_IRQHandler           ; 30: SSP0
-                DCD     SSP1_IRQHandler           ; 31: SSP1
-                DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
-                DCD     RTC_IRQHandler            ; 33: Real Time Clock
-                DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
-                DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
-                DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
-                DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
-                DCD     ADC_IRQHandler            ; 38: A/D Converter
-                DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
-                DCD     USB_IRQHandler            ; 40: USB
-                DCD     CAN_IRQHandler            ; 41: CAN
-                DCD     DMA_IRQHandler            ; 42: General Purpose DMA
-                DCD     I2S_IRQHandler            ; 43: I2S
-                DCD     ENET_IRQHandler           ; 44: Ethernet
-                DCD     RIT_IRQHandler            ; 45: Repetitive Interrupt Timer
-                DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
-                DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
-                DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
-
-
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)                
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  TIMER0_IRQHandler         [WEAK]
-                EXPORT  TIMER1_IRQHandler         [WEAK]
-                EXPORT  TIMER2_IRQHandler         [WEAK]
-                EXPORT  TIMER3_IRQHandler         [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  PWM1_IRQHandler           [WEAK]
-                EXPORT  I2C0_IRQHandler           [WEAK]
-                EXPORT  I2C1_IRQHandler           [WEAK]
-                EXPORT  I2C2_IRQHandler           [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-                EXPORT  SSP0_IRQHandler           [WEAK]
-                EXPORT  SSP1_IRQHandler           [WEAK]
-                EXPORT  PLL0_IRQHandler           [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  EINT0_IRQHandler          [WEAK]
-                EXPORT  EINT1_IRQHandler          [WEAK]
-                EXPORT  EINT2_IRQHandler          [WEAK]
-                EXPORT  EINT3_IRQHandler          [WEAK]
-                EXPORT  ADC_IRQHandler            [WEAK]
-                EXPORT  BOD_IRQHandler            [WEAK]
-                EXPORT  USB_IRQHandler            [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  DMA_IRQHandler            [WEAK]
-                EXPORT  I2S_IRQHandler            [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  RIT_IRQHandler            [WEAK]
-                EXPORT  MCPWM_IRQHandler          [WEAK]
-                EXPORT  QEI_IRQHandler            [WEAK]
-                EXPORT  PLL1_IRQHandler           [WEAK]
-
-WDT_IRQHandler           
-TIMER0_IRQHandler         
-TIMER1_IRQHandler         
-TIMER2_IRQHandler         
-TIMER3_IRQHandler         
-UART0_IRQHandler          
-UART1_IRQHandler          
-UART2_IRQHandler          
-UART3_IRQHandler          
-PWM1_IRQHandler           
-I2C0_IRQHandler           
-I2C1_IRQHandler           
-I2C2_IRQHandler           
-SPI_IRQHandler            
-SSP0_IRQHandler           
-SSP1_IRQHandler           
-PLL0_IRQHandler           
-RTC_IRQHandler            
-EINT0_IRQHandler          
-EINT1_IRQHandler          
-EINT2_IRQHandler          
-EINT3_IRQHandler          
-ADC_IRQHandler            
-BOD_IRQHandler            
-USB_IRQHandler            
-CAN_IRQHandler            
-DMA_IRQHandler          
-I2S_IRQHandler            
-ENET_IRQHandler       
-RIT_IRQHandler          
-MCPWM_IRQHandler             
-QEI_IRQHandler            
-PLL1_IRQHandler           
-
-                B       .
-
-                ENDP
-                
-                ALIGN
-                END

--- a/vendor/NXP/LPC1768/cmsis/ARM/sys.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * Setup a fixed single stack/heap memory model, 
- *  between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/vendor/NXP/LPC1768/cmsis/GCC_ARM/LPC1768.ld	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,149 +0,0 @@
-/* Linker script for mbed LPC1768 */
-
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
-  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38
-
-  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
-  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- * 
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .text :
-    {
-        KEEP(*(.isr_vector))
-        *(.text*)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        KEEP(*(.eh_frame*))
-    } > FLASH
-
-    .ARM.extab : 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
-    __exidx_end = .;
-
-    __etext = .;
-        
-    .data : AT (__etext)
-    {
-        __data_start__ = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE (__fini_array_end = .);
-
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-
-    } > RAM
-
-    .bss :
-    {
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        __bss_end__ = .;
-    } > RAM
-    
-    .heap :
-    {
-        __end__ = .;
-        end = __end__;
-        *(.heap*)
-        __HeapLimit = .;
-    } > RAM
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy :
-    {
-        *(.stack)
-    } > RAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}

--- a/vendor/NXP/LPC1768/cmsis/GCC_ARM/startup_LPC17xx.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,219 +0,0 @@
-/* File: startup_ARMCM3.s
- * Purpose: startup file for Cortex-M3/M4 devices. Should use with 
- *   GNU Tools for ARM Embedded Processors
- * Version: V1.1
- * Date: 17 June 2011
- * 
- * Copyright (C) 2011 ARM Limited. All rights reserved.
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- */
-    .syntax unified
-    .arch armv7-m
-
-/* Memory Model
-   The HEAP starts at the end of the DATA section and grows upward.
-   
-   The STACK starts at the end of the RAM and grows downward.
-   
-   The HEAP and stack STACK are only checked at compile time:
-   (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
-   
-   This is just a check for the bare minimum for the Heap+Stack area before
-   aborting compilation, it is not the run time limit:
-   Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
- */
-    .section .stack
-    .align 3
-#ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
-#else
-    .equ    Stack_Size, 0xc00
-#endif
-    .globl    __StackTop
-    .globl    __StackLimit
-__StackLimit:
-    .space    Stack_Size
-    .size __StackLimit, . - __StackLimit
-__StackTop:
-    .size __StackTop, . - __StackTop
-
-    .section .heap
-    .align 3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0x800
-#endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
-__HeapBase:
-    .space    Heap_Size
-    .size __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size __HeapLimit, . - __HeapLimit
-    
-    .section .isr_vector
-    .align 2
-    .globl __isr_vector
-__isr_vector:
-    .long    __StackTop            /* Top of Stack */
-    .long    Reset_Handler         /* Reset Handler */
-    .long    NMI_Handler           /* NMI Handler */
-    .long    HardFault_Handler     /* Hard Fault Handler */
-    .long    MemManage_Handler     /* MPU Fault Handler */
-    .long    BusFault_Handler      /* Bus Fault Handler */
-    .long    UsageFault_Handler    /* Usage Fault Handler */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    SVC_Handler           /* SVCall Handler */
-    .long    DebugMon_Handler      /* Debug Monitor Handler */
-    .long    0                     /* Reserved */
-    .long    PendSV_Handler        /* PendSV Handler */
-    .long    SysTick_Handler       /* SysTick Handler */
-
-    /* External interrupts */
-    .long   WDT_IRQHandler              /* 16: Watchdog Timer               */
-    .long   TIMER0_IRQHandler           /* 17: Timer0                       */
-    .long   TIMER1_IRQHandler           /* 18: Timer1                       */
-    .long   TIMER2_IRQHandler           /* 19: Timer2                       */
-    .long   TIMER3_IRQHandler           /* 20: Timer3                       */
-    .long   UART0_IRQHandler            /* 21: UART0                        */
-    .long   UART1_IRQHandler            /* 22: UART1                        */
-    .long   UART2_IRQHandler            /* 23: UART2                        */
-    .long   UART3_IRQHandler            /* 24: UART3                        */
-    .long   PWM1_IRQHandler             /* 25: PWM1                         */
-    .long   I2C0_IRQHandler             /* 26: I2C0                         */
-    .long   I2C1_IRQHandler             /* 27: I2C1                         */
-    .long   I2C2_IRQHandler             /* 28: I2C2                         */
-    .long   SPI_IRQHandler              /* 29: SPI                          */
-    .long   SSP0_IRQHandler             /* 30: SSP0                         */
-    .long   SSP1_IRQHandler             /* 31: SSP1                         */
-    .long   PLL0_IRQHandler             /* 32: PLL0 Lock (Main PLL)         */
-    .long   RTC_IRQHandler              /* 33: Real Time Clock              */
-    .long   EINT0_IRQHandler            /* 34: External Interrupt 0         */
-    .long   EINT1_IRQHandler            /* 35: External Interrupt 1         */
-    .long   EINT2_IRQHandler            /* 36: External Interrupt 2         */
-    .long   EINT3_IRQHandler            /* 37: External Interrupt 3         */
-    .long   ADC_IRQHandler              /* 38: A/D Converter                */
-    .long   BOD_IRQHandler              /* 39: Brown-Out Detect             */
-    .long   USB_IRQHandler              /* 40: USB                          */
-    .long   CAN_IRQHandler              /* 41: CAN                          */
-    .long   DMA_IRQHandler              /* 42: General Purpose DMA          */
-    .long   I2S_IRQHandler              /* 43: I2S                          */
-    .long   ENET_IRQHandler             /* 44: Ethernet                     */
-    .long   RIT_IRQHandler              /* 45: Repetitive Interrupt Timer   */
-    .long   MCPWM_IRQHandler            /* 46: Motor Control PWM            */
-    .long   QEI_IRQHandler              /* 47: Quadrature Encoder Interface */
-    .long   PLL1_IRQHandler             /* 48: PLL1 Lock (USB PLL)          */
-    .long   USBActivity_IRQHandler      /* 49: USB Activity                 */
-    .long   CANActivity_IRQHandler      /* 50: CAN Activity                 */
-
-    .size    __isr_vector, . - __isr_vector
-
-    .text
-    .thumb
-    .thumb_func
-    .align 2
-    .globl    Reset_Handler
-    .type    Reset_Handler, %function
-Reset_Handler:
-/*     Loop to copy data from read only memory to RAM. The ranges
- *      of copy from/to are specified by following symbols evaluated in 
- *      linker script.
- *      _etext: End of code section, i.e., begin of data sections to copy from.
- *      __data_start__/__data_end__: RAM address range that data should be
- *      copied to. Both must be aligned to 4 bytes boundary.  */
-
-    ldr    r1, =__etext
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
-
-.flash_to_ram_loop:
-    cmp     r2, r3
-    ittt    lt
-    ldrlt   r0, [r1], #4
-    strlt   r0, [r2], #4
-    blt    .flash_to_ram_loop
-
-    ldr    r0, =SystemInit
-    blx    r0
-    ldr    r0, =_start
-    bx    r0
-    .pool
-    .size Reset_Handler, . - Reset_Handler
-    
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-    .macro    def_default_handler    handler_name
-    .align 1
-    .thumb_func
-    .weak    \handler_name
-    .type    \handler_name, %function
-\handler_name :
-    b    .
-    .size    \handler_name, . - \handler_name
-    .endm
-    
-    def_default_handler    NMI_Handler
-    def_default_handler    HardFault_Handler
-    def_default_handler    MemManage_Handler
-    def_default_handler    BusFault_Handler
-    def_default_handler    UsageFault_Handler
-    def_default_handler    SVC_Handler
-    def_default_handler    DebugMon_Handler
-    def_default_handler    PendSV_Handler
-    def_default_handler    SysTick_Handler
-    def_default_handler    Default_Handler
-    
-    def_default_handler     WDT_IRQHandler
-    def_default_handler     TIMER0_IRQHandler
-    def_default_handler     TIMER1_IRQHandler
-    def_default_handler     TIMER2_IRQHandler
-    def_default_handler     TIMER3_IRQHandler
-    def_default_handler     UART0_IRQHandler
-    def_default_handler     UART1_IRQHandler
-    def_default_handler     UART2_IRQHandler
-    def_default_handler     UART3_IRQHandler
-    def_default_handler     PWM1_IRQHandler
-    def_default_handler     I2C0_IRQHandler
-    def_default_handler     I2C1_IRQHandler
-    def_default_handler     I2C2_IRQHandler
-    def_default_handler     SPI_IRQHandler
-    def_default_handler     SSP0_IRQHandler
-    def_default_handler     SSP1_IRQHandler
-    def_default_handler     PLL0_IRQHandler
-    def_default_handler     RTC_IRQHandler
-    def_default_handler     EINT0_IRQHandler
-    def_default_handler     EINT1_IRQHandler
-    def_default_handler     EINT2_IRQHandler
-    def_default_handler     EINT3_IRQHandler
-    def_default_handler     ADC_IRQHandler
-    def_default_handler     BOD_IRQHandler
-    def_default_handler     USB_IRQHandler
-    def_default_handler     CAN_IRQHandler
-    def_default_handler     DMA_IRQHandler
-    def_default_handler     I2S_IRQHandler
-    def_default_handler     ENET_IRQHandler
-    def_default_handler     RIT_IRQHandler
-    def_default_handler     MCPWM_IRQHandler
-    def_default_handler     QEI_IRQHandler
-    def_default_handler     PLL1_IRQHandler
-    def_default_handler     USBActivity_IRQHandler
-    def_default_handler     CANActivity_IRQHandler
-
-    .weak    DEF_IRQHandler
-    .set    DEF_IRQHandler, Default_Handler
-
-    .end
-

--- a/vendor/NXP/LPC1768/cmsis/GCC_CR/LPC1768.ld	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,153 +0,0 @@
-/* mbed - LPC1768 linker script
- * Based linker script generated by Code Red Technologies Red Suite 4.1
- */
-GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
-  RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 /* 32k */
-  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */
-
-}
-  /* Define a symbol for the top of each memory region */
-  __top_MFlash512 = 0x0 + 0x80000;
-  __top_RamLoc32 = 0x10000000 + 0x8000;
-  __top_RamAHB32 = 0x2007c000 + 0x8000;
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-
-    /* MAIN TEXT SECTION */ 
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        KEEP(*(.isr_vector))
-        
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data)) ;
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2)) ;
-        LONG(  SIZEOF(.data_RAM2));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-        
-
-        *(.after_vectors*)
-        
-        *(.text*)
-        *(.rodata .rodata.*)
-        . = ALIGN(4);
-        
-        /* C++ constructors etc */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-        
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-        
-        KEEP(*(.fini));
-        
-        . = ALIGN(0x4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-        
-        . = ALIGN(0x4);
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-        /* End C++ */
-    } > MFlash512
-
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this.
-     */
-    .ARM.extab : ALIGN(4)
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlash512
-    __exidx_start = .;
-    
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > MFlash512
-    __exidx_end = .;
-    
-    _etext = .;
-        
-    
-    .data_RAM2 : ALIGN(4)
-    {
-       FILL(0xff)
-        *(.data.$RAM2*)
-        *(.data.$RamAHB32*)
-       . = ALIGN(4) ;
-    } > RamAHB32 AT>MFlash512
-    
-    /* MAIN DATA SECTION */
-
-    .uninit_RESERVED : ALIGN(4)
-    {
-        KEEP(*(.bss.$RESERVED*))
-    } > RamLoc32
-
-    .data : ALIGN(4)
-    {
-        FILL(0xff)
-        _data = .;
-        *(vtable)
-        *(.data*)
-        . = ALIGN(4) ;
-        _edata = .;
-    } > RamLoc32 AT>MFlash512
-
-    
-    .bss_RAM2 : ALIGN(4)
-    {
-        *(.bss.$RAM2*)
-        *(.bss.$RamAHB32*)
-       . = ALIGN(4) ;
-    } > RamAHB32
-
-    /* MAIN BSS SECTION */
-    .bss : ALIGN(4)
-    {
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc32
-    
-    PROVIDE(_pvHeapStart = .);
-    PROVIDE(_vStackTop = __top_RamLoc32 - 0);
-}

--- a/vendor/NXP/LPC1768/cmsis/GCC_CR/startup_LPC17xx.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,177 +0,0 @@
-extern "C" {
-
-#include "LPC17xx.h"
-
-#define WEAK          __attribute__ ((weak))
-#define ALIAS(f)      __attribute__ ((weak, alias (#f)))
-#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))
-
-extern unsigned int __data_section_table;
-extern unsigned int __data_section_table_end;
-extern unsigned int __bss_section_table;
-extern unsigned int __bss_section_table_end;
-
-extern void __libc_init_array(void);
-extern int main(void);
-extern void _vStackTop(void);
-extern void (* const g_pfnVectors[])(void);
-
-     void ResetISR          (void);
-WEAK void NMI_Handler       (void);
-WEAK void HardFault_Handler (void);
-WEAK void MemManage_Handler (void);
-WEAK void BusFault_Handler  (void);
-WEAK void UsageFault_Handler(void);
-WEAK void SVCall_Handler    (void);
-WEAK void DebugMon_Handler  (void);
-WEAK void PendSV_Handler    (void);
-WEAK void SysTick_Handler   (void);
-WEAK void IntDefaultHandler (void);
-
-void WDT_IRQHandler        (void) ALIAS(IntDefaultHandler);
-void TIMER0_IRQHandler     (void) ALIAS(IntDefaultHandler);
-void TIMER1_IRQHandler     (void) ALIAS(IntDefaultHandler);
-void TIMER2_IRQHandler     (void) ALIAS(IntDefaultHandler);
-void TIMER3_IRQHandler     (void) ALIAS(IntDefaultHandler);
-void UART0_IRQHandler      (void) ALIAS(IntDefaultHandler);
-void UART1_IRQHandler      (void) ALIAS(IntDefaultHandler);
-void UART2_IRQHandler      (void) ALIAS(IntDefaultHandler);
-void UART3_IRQHandler      (void) ALIAS(IntDefaultHandler);
-void PWM1_IRQHandler       (void) ALIAS(IntDefaultHandler);
-void I2C0_IRQHandler       (void) ALIAS(IntDefaultHandler);
-void I2C1_IRQHandler       (void) ALIAS(IntDefaultHandler);
-void I2C2_IRQHandler       (void) ALIAS(IntDefaultHandler);
-void SPI_IRQHandler        (void) ALIAS(IntDefaultHandler);
-void SSP0_IRQHandler       (void) ALIAS(IntDefaultHandler);
-void SSP1_IRQHandler       (void) ALIAS(IntDefaultHandler);
-void PLL0_IRQHandler       (void) ALIAS(IntDefaultHandler);
-void RTC_IRQHandler        (void) ALIAS(IntDefaultHandler);
-void EINT0_IRQHandler      (void) ALIAS(IntDefaultHandler);
-void EINT1_IRQHandler      (void) ALIAS(IntDefaultHandler);
-void EINT2_IRQHandler      (void) ALIAS(IntDefaultHandler);
-void EINT3_IRQHandler      (void) ALIAS(IntDefaultHandler);
-void ADC_IRQHandler        (void) ALIAS(IntDefaultHandler);
-void BOD_IRQHandler        (void) ALIAS(IntDefaultHandler);
-void USB_IRQHandler        (void) ALIAS(IntDefaultHandler);
-void CAN_IRQHandler        (void) ALIAS(IntDefaultHandler);
-void DMA_IRQHandler        (void) ALIAS(IntDefaultHandler);
-void I2S_IRQHandler        (void) ALIAS(IntDefaultHandler);
-void ENET_IRQHandler       (void) ALIAS(IntDefaultHandler);
-void RIT_IRQHandler        (void) ALIAS(IntDefaultHandler);
-void MCPWM_IRQHandler      (void) ALIAS(IntDefaultHandler);
-void QEI_IRQHandler        (void) ALIAS(IntDefaultHandler);
-void PLL1_IRQHandler       (void) ALIAS(IntDefaultHandler);
-void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
-
-__attribute__ ((section(".isr_vector")))
-void (* const g_pfnVectors[])(void) = {
-    &_vStackTop, ResetISR, NMI_Handler,
-    HardFault_Handler,
-    MemManage_Handler,
-    BusFault_Handler,
-    UsageFault_Handler,
-    0,
-    0,
-    0,
-    0,
-    SVCall_Handler,
-    DebugMon_Handler,
-    0,
-    PendSV_Handler,
-    SysTick_Handler,
-    WDT_IRQHandler,
-    TIMER0_IRQHandler,
-    TIMER1_IRQHandler,
-    TIMER2_IRQHandler,
-    TIMER3_IRQHandler,
-    UART0_IRQHandler,
-    UART1_IRQHandler,
-    UART2_IRQHandler,
-    UART3_IRQHandler,
-    PWM1_IRQHandler,
-    I2C0_IRQHandler,
-    I2C1_IRQHandler,
-    I2C2_IRQHandler,
-    SPI_IRQHandler,
-    SSP0_IRQHandler,
-    SSP1_IRQHandler,
-    PLL0_IRQHandler,
-    RTC_IRQHandler,
-    EINT0_IRQHandler,
-    EINT1_IRQHandler,
-    EINT2_IRQHandler,
-    EINT3_IRQHandler,
-    ADC_IRQHandler,
-    BOD_IRQHandler,
-    USB_IRQHandler,
-    CAN_IRQHandler,
-    DMA_IRQHandler,
-    I2S_IRQHandler,
-    ENET_IRQHandler,
-    RIT_IRQHandler,
-    MCPWM_IRQHandler,
-    QEI_IRQHandler,
-    PLL1_IRQHandler,
-    USBActivity_IRQHandler,
-    CANActivity_IRQHandler,
-};
-
-AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
-    unsigned int *pulDest = (unsigned int*) start;
-    unsigned int *pulSrc = (unsigned int*) romstart;
-    unsigned int loop;
-    for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
-}
-
-AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
-    unsigned int *pulDest = (unsigned int*) start;
-    unsigned int loop;
-    for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
-}
-
-AFTER_VECTORS void ResetISR(void) {
-    unsigned int LoadAddr, ExeAddr, SectionLen;
-    unsigned int *SectionTableAddr;
-    
-    SectionTableAddr = &__data_section_table;
-    
-    while (SectionTableAddr < &__data_section_table_end) {
-        LoadAddr = *SectionTableAddr++;
-        ExeAddr = *SectionTableAddr++;
-        SectionLen = *SectionTableAddr++;
-        data_init(LoadAddr, ExeAddr, SectionLen);
-    }
-    while (SectionTableAddr < &__bss_section_table_end) {
-        ExeAddr = *SectionTableAddr++;
-        SectionLen = *SectionTableAddr++;
-        bss_init(ExeAddr, SectionLen);
-    }
-    
-    SystemInit();
-    __libc_init_array();
-    main();
-    while (1) {;}
-}
-
-AFTER_VECTORS void NMI_Handler       (void) {}
-AFTER_VECTORS void HardFault_Handler (void) {}
-AFTER_VECTORS void MemManage_Handler (void) {}
-AFTER_VECTORS void BusFault_Handler  (void) {}
-AFTER_VECTORS void UsageFault_Handler(void) {}
-AFTER_VECTORS void SVCall_Handler    (void) {}
-AFTER_VECTORS void DebugMon_Handler  (void) {}
-AFTER_VECTORS void PendSV_Handler    (void) {}
-AFTER_VECTORS void SysTick_Handler   (void) {}
-AFTER_VECTORS void IntDefaultHandler (void) {}
-
-int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
-}
-
-#include <stdlib.h>
-
-void *operator new(size_t size)  {return malloc(size);}
-void *operator new[](size_t size){return malloc(size);}
-
-void operator delete(void *p)   {free(p);}
-void operator delete[](void *p) {free(p);}

--- a/vendor/NXP/LPC1768/cmsis/GCC_CS/LPC1768.ld	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,212 +0,0 @@
-/* Linker script for mbed LPC1768
- *
- * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
- * BugURL:https://support.codesourcery.com/GNUToolchain/
- *
- *  Copyright 2007 CodeSourcery.
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply. */
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-ENTRY(__cs3_reset_cortex_m)
-SEARCH_DIR(.)
-
-/*
-ram ORIGIN: 8_byte_aligned(49 vect * 4 bytes) =  8_byte_aligned(0xC4) = 0xC8
-ram LENGTH: 32KB - 0xC8 = 0x7F38
-*/
-MEMORY
-{
-  rom (rx)  : ORIGIN = 0x00000000, LENGTH = 512K
-  
-  ram (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38
-  
-  ram1(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
-  ram2(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
-}
-
-/* These force the linker to search for particular symbols from
- * the start of the link process and thus ensure the user's
- * overrides are picked up
- */
-EXTERN(__cs3_reset_cortex_m)
-EXTERN(__cs3_interrupt_vector_cortex_m)
-EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
-
-PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
-PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
-PROVIDE(__cs3_heap_start = _end);
-PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
-
-SECTIONS
-{
-  .text :
-  {
-    CREATE_OBJECT_SYMBOLS
-    __cs3_region_start_rom = .;
-    *(.cs3.region-head.rom)
-    __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
-    *(.cs3.interrupt_vector)
-    /* Make sure we pulled in an interrupt vector.  */
-    ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
-    *(.rom)
-    *(.rom.b)
-
-    __cs3_reset = __cs3_reset_cortex_m;
-    *(.cs3.reset)
-    /* Make sure we pulled in some reset code.  */
-    ASSERT (. != __cs3_reset, "No reset code");
-
-    *(.text .text.* .gnu.linkonce.t.*)
-    *(.plt)
-    *(.gnu.warning)
-    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
-
-    *(.rodata .rodata.* .gnu.linkonce.r.*)
-
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-    *(.gcc_except_table)
-    *(.eh_frame_hdr)
-    *(.eh_frame)
-
-    . = ALIGN(4);
-    KEEP(*(.init))
-
-    . = ALIGN(4);
-    __preinit_array_start = .;
-    KEEP (*(.preinit_array))
-    __preinit_array_end = .;
-
-    . = ALIGN(4);
-    __init_array_start = .;
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array))
-    __init_array_end = .;
-
-    . = ALIGN(0x4);
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*crtend.o(.ctors))
-
-    . = ALIGN(4);
-    KEEP(*(.fini))
-
-    . = ALIGN(4);
-    __fini_array_start = .;
-    KEEP (*(.fini_array))
-    KEEP (*(SORT(.fini_array.*)))
-    __fini_array_end = .;
-
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*crtend.o(.dtors))
-
-    . = ALIGN(4);
-    __cs3_regions = .;
-    LONG (0)
-    LONG (__cs3_region_init_ram)
-    LONG (__cs3_region_start_ram)
-    LONG (__cs3_region_init_size_ram)
-    LONG (__cs3_region_zero_size_ram)
-  }
-
-  /* .ARM.exidx is sorted, so has to go in its own output section.  */
-  __exidx_start = .;
-  .ARM.exidx :
-  {
-    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-  } >rom
-  __exidx_end = .;
-  .text.align :
-  {
-    . = ALIGN(8);
-    _etext = .;
-  } >rom
-  __cs3_region_size_rom = LENGTH(rom);
-  __cs3_region_num = 1;
-  
-  .data :
-  {
-    __cs3_region_start_ram = .;
-    *(.cs3.region-head.ram)
-    KEEP(*(.jcr))
-    *(.got.plt) *(.got)
-    *(.shdata)
-    *(.data .data.* .gnu.linkonce.d.*)
-    *(.ram)
-    . = ALIGN (8);
-    _edata = .;
-  } >ram AT>rom
-  .bss :
-  {
-    *(.shbss)
-    *(.bss .bss.* .gnu.linkonce.b.*)
-    *(COMMON)
-    *(.ram.b)
-    . = ALIGN (8);
-    _end = .;
-    __end = .;
-  } >ram AT>rom
-  /* This used for USB RAM section */
-	.usb_ram (NOLOAD):
-	{
-		*.o (USB_RAM)
-	} > ram2
-  .heap (NOLOAD) :
-  {
-    *(.heap)
-  } >ram
-  .stack (__cs3_stack - __cs3_stack_size) (NOLOAD):
-  {
-    *(.stack)
-    _estack = .;
-    PROVIDE(estack = .);
-  } >ram
-
-  __cs3_region_init_ram = LOADADDR (.data);
-  __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
-  __cs3_region_zero_size_ram = _end - _edata;
-  __cs3_region_size_ram = LENGTH(ram);
-  __cs3_region_num = 1;
-
-  .stab 0 (NOLOAD) : { *(.stab) }
-  .stabstr 0 (NOLOAD) : { *(.stabstr) }
-  /* DWARF debug sections.
-   * Symbols in the DWARF debugging sections are relative to the beginning
-   * of the section so we begin them at 0.  */
-  /* DWARF 1 */
-  .debug          0 : { *(.debug) }
-  .line           0 : { *(.line) }
-  /* GNU DWARF 1 extensions */
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
-  .debug_sfnames  0 : { *(.debug_sfnames) }
-  /* DWARF 1.1 and DWARF 2 */
-  .debug_aranges  0 : { *(.debug_aranges) }
-  .debug_pubnames 0 : { *(.debug_pubnames) }
-  /* DWARF 2 */
-  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-  .debug_abbrev   0 : { *(.debug_abbrev) }
-  .debug_line     0 : { *(.debug_line) }
-  .debug_frame    0 : { *(.debug_frame) }
-  .debug_str      0 : { *(.debug_str) }
-  .debug_loc      0 : { *(.debug_loc) }
-  .debug_macinfo  0 : { *(.debug_macinfo) }
-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
-  .debug_funcnames 0 : { *(.debug_funcnames) }
-  .debug_typenames 0 : { *(.debug_typenames) }
-  .debug_varnames  0 : { *(.debug_varnames) }
-
-  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
-  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
-  /DISCARD/ : { *(.note.GNU-stack) }
-}

--- a/vendor/NXP/LPC1768/cmsis/GCC_CS/startup_LPC17xx.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,204 +0,0 @@
-    .equ    Stack_Size, 0x1024
-    .section ".stack", "w"
-    .align  3
-    .globl  __cs3_stack_mem
-    .globl  __cs3_stack_size
-__cs3_stack_mem:
-    .if     Stack_Size
-    .space  Stack_Size
-    .endif
-    .size   __cs3_stack_mem,  . - __cs3_stack_mem
-    .set    __cs3_stack_size, . - __cs3_stack_mem
-
-    .equ    Heap_Size,  0x8000
-    .section ".heap", "w"
-    .align  3
-    .globl  __cs3_heap_start
-    .globl  __cs3_heap_end
-__cs3_heap_start:
-    .if     Heap_Size
-    .space  Heap_Size
-    .endif
-__cs3_heap_end:
-
-
-    .section ".cs3.interrupt_vector"
-    .globl  __cs3_interrupt_vector_cortex_m
-    .type   __cs3_interrupt_vector_cortex_m, %object
-
-__cs3_interrupt_vector_cortex_m:
-    .long   __cs3_stack
-    .long   __cs3_reset
-    .long   NMI_Handler
-    .long   HardFault_Handler
-    .long   MemManage_Handler
-    .long   BusFault_Handler
-    .long   UsageFault_Handler
-    .long   0
-    .long   0
-    .long   0
-    .long   0
-    .long   SVC_Handler
-    .long   DebugMon_Handler
-    .long   0
-    .long   PendSV_Handler
-    .long   SysTick_Handler
-
-    .long   WDT_IRQHandler
-    .long   TIMER0_IRQHandler
-    .long   TIMER1_IRQHandler
-    .long   TIMER2_IRQHandler
-    .long   TIMER3_IRQHandler
-    .long   UART0_IRQHandler
-    .long   UART1_IRQHandler
-    .long   UART2_IRQHandler
-    .long   UART3_IRQHandler
-    .long   PWM1_IRQHandler
-    .long   I2C0_IRQHandler
-    .long   I2C1_IRQHandler
-    .long   I2C2_IRQHandler
-    .long   SPI_IRQHandler
-    .long   SSP0_IRQHandler
-    .long   SSP1_IRQHandler
-    .long   PLL0_IRQHandler
-    .long   RTC_IRQHandler
-    .long   EINT0_IRQHandler
-    .long   EINT1_IRQHandler
-    .long   EINT2_IRQHandler
-    .long   EINT3_IRQHandler
-    .long   ADC_IRQHandler
-    .long   BOD_IRQHandler
-    .long   USB_IRQHandler
-    .long   CAN_IRQHandler
-    .long   DMA_IRQHandler
-    .long   I2S_IRQHandler
-    .long   ENET_IRQHandler
-    .long   RIT_IRQHandler
-    .long   MCPWM_IRQHandler
-    .long   QEI_IRQHandler
-    .long   PLL1_IRQHandler
-    .long	USBActivity_IRQHandler
-    .long 	CANActivity_IRQHandler
-
-    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
-
-    .thumb
-
-    .section .cs3.reset,"x",%progbits
-    .thumb_func
-    .globl  __cs3_reset_cortex_m
-    .type   __cs3_reset_cortex_m, %function
-__cs3_reset_cortex_m:
-    .fnstart
-    LDR     R0, =SystemInit
-    BLX     R0
-    LDR     R0, =__cs3_start_c
-    BX      R0
-    .pool
-    .cantunwind
-    .fnend
-    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
-
-    .section ".text"
-
-    .weak   NMI_Handler
-    .type   NMI_Handler, %function
-NMI_Handler:
-    B       .
-    .size   NMI_Handler, . - NMI_Handler
-
-    .weak   HardFault_Handler
-    .type   HardFault_Handler, %function
-HardFault_Handler:
-    B       .
-    .size   HardFault_Handler, . - HardFault_Handler
-
-    .weak   MemManage_Handler
-    .type   MemManage_Handler, %function
-MemManage_Handler:
-    B       .
-    .size   MemManage_Handler, . - MemManage_Handler
-
-    .weak   BusFault_Handler
-    .type   BusFault_Handler, %function
-BusFault_Handler:
-    B       .
-    .size   BusFault_Handler, . - BusFault_Handler
-
-    .weak   UsageFault_Handler
-    .type   UsageFault_Handler, %function
-UsageFault_Handler:
-    B       .
-    .size   UsageFault_Handler, . - UsageFault_Handler
-
-    .weak   SVC_Handler
-    .type   SVC_Handler, %function
-SVC_Handler:
-    B       .
-    .size   SVC_Handler, . - SVC_Handler
-
-    .weak   DebugMon_Handler
-    .type   DebugMon_Handler, %function
-DebugMon_Handler:
-    B       .
-    .size   DebugMon_Handler, . - DebugMon_Handler
-
-    .weak   PendSV_Handler
-    .type   PendSV_Handler, %function
-PendSV_Handler:
-    B       .
-    .size   PendSV_Handler, . - PendSV_Handler
-
-    .weak   SysTick_Handler
-    .type   SysTick_Handler, %function
-SysTick_Handler:
-    B       .
-    .size   SysTick_Handler, . - SysTick_Handler
-
-    .globl  Default_Handler
-    .type   Default_Handler, %function
-Default_Handler:
-    B       .
-    .size   Default_Handler, . - Default_Handler
-
-    .macro  IRQ handler
-    .weak   \handler
-    .set    \handler, Default_Handler
-    .endm
-
-    IRQ     WDT_IRQHandler
-    IRQ     TIMER0_IRQHandler
-    IRQ     TIMER1_IRQHandler
-    IRQ     TIMER2_IRQHandler
-    IRQ     TIMER3_IRQHandler
-    IRQ     UART0_IRQHandler
-    IRQ     UART1_IRQHandler
-    IRQ     UART2_IRQHandler
-    IRQ     UART3_IRQHandler
-    IRQ     PWM1_IRQHandler
-    IRQ     I2C0_IRQHandler
-    IRQ     I2C1_IRQHandler
-    IRQ     I2C2_IRQHandler
-    IRQ     SPI_IRQHandler
-    IRQ     SSP0_IRQHandler
-    IRQ     SSP1_IRQHandler
-    IRQ     PLL0_IRQHandler
-    IRQ     RTC_IRQHandler
-    IRQ     EINT0_IRQHandler
-    IRQ     EINT1_IRQHandler
-    IRQ     EINT2_IRQHandler
-    IRQ     EINT3_IRQHandler
-    IRQ     ADC_IRQHandler
-    IRQ     BOD_IRQHandler
-    IRQ     USB_IRQHandler
-    IRQ     CAN_IRQHandler
-    IRQ     DMA_IRQHandler
-    IRQ     I2S_IRQHandler
-    IRQ     ENET_IRQHandler
-    IRQ     RIT_IRQHandler
-    IRQ     MCPWM_IRQHandler
-    IRQ     QEI_IRQHandler
-    IRQ     PLL1_IRQHandler
-    IRQ		USBActivity_IRQHandler
-    IRQ		CANActivity_IRQHandler
-    .end

--- a/vendor/NXP/LPC1768/cmsis/GCC_CS/sys.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,80 +0,0 @@
-#include "cmsis.h"
-#include <sys/types.h>
-#include <errno.h>
-
-extern "C" {
-
-struct SCS3Regions {
-    unsigned long   Dummy;
-    unsigned long*  InitRam;
-    unsigned long*  StartRam;
-    unsigned long   InitSizeRam;
-    unsigned long   ZeroSizeRam;
-};
-
-extern unsigned long __cs3_regions;
-extern unsigned long __cs3_heap_start;
-
-int  main(void);
-void __libc_init_array(void);
-void exit(int ErrorCode);
-
-static void *heap_pointer = NULL;
-
-void __cs3_start_c(void) {
-    static SCS3Regions* pCS3Regions = (SCS3Regions*)&__cs3_regions;
-    unsigned long* pulDest;
-    unsigned long* pulSrc;
-    unsigned long  ByteCount;
-    unsigned long  i;
-    
-    pulSrc = pCS3Regions->InitRam;
-    pulDest = pCS3Regions->StartRam;
-    ByteCount = pCS3Regions->InitSizeRam;
-    if (pulSrc != pulDest) {
-        for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
-            *(pulDest++) = *(pulSrc++);
-        }
-    } else {
-        pulDest = (unsigned long*)(void*)((char*)pulDest + ByteCount);
-    }
-    
-    ByteCount = pCS3Regions->ZeroSizeRam;
-    for(i = 0 ; i < ByteCount ; i += sizeof(unsigned long)) {
-        *(pulDest++) = 0;
-    }
-    
-    heap_pointer = &__cs3_heap_start;
-     __libc_init_array();
-    
-    exit(main());
-}
-
-int _kill(int pid, int sig) {
-    errno = EINVAL;
-    return -1;
-}
-
-void _exit(int status) {
-    exit(status);
-}
-
-int _getpid(void) {
-	return 1;
-}
-
-void *_sbrk(unsigned int incr) {
-    void *mem;
-    
-    unsigned int next = ((((unsigned int)heap_pointer + incr) + 7) & ~7);
-    if (next > __get_MSP()) {
-        mem = NULL;
-    } else {
-        mem = (void *)heap_pointer;
-    }
-    heap_pointer = (void *)next;
-    
-    return mem;
-}
-
-}

--- a/vendor/NXP/LPC1768/cmsis/IAR/LPC17xx.icf	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-/* [ROM] */
-define symbol __intvec_start__     = 0x00000000;
-define symbol __region_ROM_start__ = 0x00000000;
-define symbol __CRP_start__        = 0x000002FC;
-define symbol __CRP_end__          = 0x000002FF;
-define symbol __region_ROM_end__   = 0x0007FFFF;
-
-/* [RAM] Vector table dynamic copy: 8_byte_aligned(49 vect * 4 bytes) =  8_byte_aligned(0xC4) = 0xC8*/
-define symbol __NVIC_start__       = 0x10000000;
-define symbol __NVIC_end__         = 0x100000C7;
-define symbol __region_RAM_start__ = 0x100000C8;
-define symbol __region_RAM_end__   = 0x1000FFDF;
-define symbol _AHB_RAM_start__     = 0x2007C000;
-define symbol _AHB_RAM_end__       = 0x20083FFF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-
-define region ROM_region     = mem:[from __region_ROM_start__   to __region_ROM_end__] - mem:[from  __CRP_start__ to __CRP_end__];
-define region CRP_region     = mem:[from  __CRP_start__ to __CRP_end__];
-
-define region RAM_region     = mem:[from __region_RAM_start__   to __region_RAM_end__];
-define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
-
-/* Stack and Heap */
-define symbol __size_cstack__   = 0x800;
-define symbol __size_heap__     = 0x800;
-define block CSTACK    with alignment = 8, size = __size_cstack__   { };
-define block HEAP      with alignment = 8, size = __size_heap__     { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
-
-initialize by copy with packing = zeros { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__intvec_start__ { section .intvec };
-place at address mem:0x2FC { section CRPKEY };
-place in ROM_region     { readonly };
-place in RAM_region     { readwrite, block STACKHEAP };
-place in AHB_RAM_region { section USB_RAM };
-place in CRP_region     { section .crp };

--- a/vendor/NXP/LPC1768/cmsis/IAR/startup_LPC17xx.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,375 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC17xx.s
-; * @purpose: CMSIS Cortex-M3 Core Device Startup File
-; *           for the NXP LPC17xx Device Series
-; * @version: V1.03
-; * @date:    09. February 2010
-; *----------------------------------------------------------------------------
-; *
-; * Copyright (C) 2010 ARM Limited. All rights reserved.
-; *
-; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
-; * processor based microcontrollers.  This file can be freely distributed
-; * within development tools that are supporting such ARM based processors.
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; ******************************************************************************/
-
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
-
-        DATA
-
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     MemManage_Handler
-        DCD     BusFault_Handler
-        DCD     UsageFault_Handler
-__vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     DebugMon_Handler
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ; 16: Watchdog Timer
-        DCD     TIMER0_IRQHandler         ; 17: Timer0
-        DCD     TIMER1_IRQHandler         ; 18: Timer1
-        DCD     TIMER2_IRQHandler         ; 19: Timer2
-        DCD     TIMER3_IRQHandler         ; 20: Timer3
-        DCD     UART0_IRQHandler          ; 21: UART0
-        DCD     UART1_IRQHandler          ; 22: UART1
-        DCD     UART2_IRQHandler          ; 23: UART2
-        DCD     UART3_IRQHandler          ; 24: UART3
-        DCD     PWM1_IRQHandler           ; 25: PWM1
-        DCD     I2C0_IRQHandler           ; 26: I2C0
-        DCD     I2C1_IRQHandler           ; 27: I2C1
-        DCD     I2C2_IRQHandler           ; 28: I2C2
-        DCD     SPI_IRQHandler            ; 29: SPI
-        DCD     SSP0_IRQHandler           ; 30: SSP0
-        DCD     SSP1_IRQHandler           ; 31: SSP1
-        DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
-        DCD     RTC_IRQHandler            ; 33: Real Time Clock
-        DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
-        DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
-        DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
-        DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
-        DCD     ADC_IRQHandler            ; 38: A/D Converter
-        DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
-        DCD     USB_IRQHandler            ; 40: USB
-        DCD     CAN_IRQHandler            ; 41: CAN
-        DCD     DMA_IRQHandler            ; 42: General Purpose DMA
-        DCD     I2S_IRQHandler            ; 43: I2S
-        DCD     ENET_IRQHandler           ; 44: Ethernet
-        DCD     RIT_IRQHandler            ; 45: Repetitive Interrupt Timer
-        DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
-        DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
-        DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
-        DCD			USBActivity_IRQHandler	  ; 49: USB Activity Interrupt
-        DCD			CANActivity_IRQHandler	  ; 50: CAN Activity Interrupt
-__Vectors_End
-
-__Vectors       EQU   __vector_table
-__Vectors_Size 	EQU 	__Vectors_End - __Vectors
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK TIMER0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER0_IRQHandler
-        B TIMER0_IRQHandler
-
-        PUBWEAK TIMER1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER1_IRQHandler
-        B TIMER1_IRQHandler
-
-        PUBWEAK TIMER2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER2_IRQHandler
-        B TIMER2_IRQHandler
-
-        PUBWEAK TIMER3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER3_IRQHandler
-        B TIMER3_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK PWM1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PWM1_IRQHandler
-        B PWM1_IRQHandler
-
-        PUBWEAK I2C0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C0_IRQHandler
-        B I2C0_IRQHandler
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-
-        PUBWEAK SPI_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI_IRQHandler
-        B SPI_IRQHandler
-
-        PUBWEAK SSP0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SSP0_IRQHandler
-        B SSP0_IRQHandler
-
-        PUBWEAK SSP1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SSP1_IRQHandler
-        B SSP1_IRQHandler
-
-        PUBWEAK PLL0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PLL0_IRQHandler
-        B PLL0_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK EINT0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT0_IRQHandler
-        B EINT0_IRQHandler
-
-        PUBWEAK EINT1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT1_IRQHandler
-        B EINT1_IRQHandler
-
-        PUBWEAK EINT2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT2_IRQHandler
-        B EINT2_IRQHandler
-
-        PUBWEAK EINT3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT3_IRQHandler
-        B EINT3_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC_IRQHandler
-        B ADC_IRQHandler
-
-        PUBWEAK BOD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-BOD_IRQHandler
-        B BOD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK DMA_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA_IRQHandler
-        B DMA_IRQHandler
-
-        PUBWEAK I2S_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2S_IRQHandler
-        B I2S_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK RIT_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RIT_IRQHandler
-        B RIT_IRQHandler
-
-        PUBWEAK MCPWM_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-MCPWM_IRQHandler
-        B MCPWM_IRQHandler
-
-        PUBWEAK QEI_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-QEI_IRQHandler
-        B QEI_IRQHandler
-
-        PUBWEAK PLL1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PLL1_IRQHandler
-        B PLL1_IRQHandler
-
-        PUBWEAK USBActivity_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USBActivity_IRQHandler
-        B USBActivity_IRQHandler
-
-        PUBWEAK CANActivity_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CANActivity_IRQHandler
-        B CANActivity_IRQHandler
-
-#ifndef SRAM
-        SECTION .crp:CODE:ROOT(2)
-        DATA
-/* Code Read Protection
-CRP1    0x12345678 - Write to RAM command can not access RAM below 0x10000200.
-                   - Read Memory command: disabled.
-                   - Copy RAM to Flash command: cannot write to Sector 0.
-                   - "Go" command: disabled.
-                   - Erase sector(s) command: can erase any individual sector except 
-                   	 sector 0 only, or can erase all sectors at once.
-                   - Compare command: disabled
-CRP2    0x87654321 - Write to RAM command: disabled.
-                   - Copy RAM to Flash: disabled.
-                   - Erase command: only allows erase of all sectors.
-CRP3    0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
-                     by pulling PIO0_1 LOW is disabled if a valid user code is
-                     present in flash sector 0.
-Caution: If CRP3 is selected, no future factory testing can be
-performed on the device.
-*/
-	DCD	0xFFFFFFFF
-#endif
-        END

--- a/vendor/NXP/LPC1768/cmsis/LPC17xx.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1035 +0,0 @@
-/**************************************************************************//**
- * @file     LPC17xx.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File for 
- *           NXP LPC17xx Device Series
- * @version: V1.09
- * @date:    17. March 2010
-
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __LPC17xx_H__
-#define __LPC17xx_H__
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
-  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
-  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
-  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
-  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
-  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
-  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
-  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
-
-/******  LPC17xx Specific Interrupt Numbers *******************************************************/
-  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
-  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */
-  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */
-  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */
-  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */
-  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */
-  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */
-  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */
-  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */
-  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */
-  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */
-  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */
-  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */
-  SPI_IRQn                      = 13,       /*!< SPI Interrupt                                    */
-  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */
-  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */
-  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
-  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */
-  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */
-  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */
-  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */
-  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */
-  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */
-  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */
-  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */
-  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */
-  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */
-  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */
-  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */
-  RIT_IRQn                      = 29,       /*!< Repetitive Interrupt Timer Interrupt             */
-  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */
-  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */
-  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */
-  USBActivity_IRQn              = 33,       /* USB Activity interrupt                             */
-  CANActivity_IRQn              = 34,       /* CAN Activity interrupt                             */
-} IRQn_Type;
-
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT             1         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-
-#include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */
-#include "system_LPC17xx.h"                 /* System Header                                      */
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral registers structures             */
-/******************************************************************************/
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#endif
-
-/*------------- System Control (SC) ------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t FLASHCFG;               /* Flash Accelerator Module           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t PLL0CON;                /* Clocking and Power Control         */
-  __IO uint32_t PLL0CFG;
-  __I  uint32_t PLL0STAT;
-  __O  uint32_t PLL0FEED;
-       uint32_t RESERVED1[4];
-  __IO uint32_t PLL1CON;
-  __IO uint32_t PLL1CFG;
-  __I  uint32_t PLL1STAT;
-  __O  uint32_t PLL1FEED;
-       uint32_t RESERVED2[4];
-  __IO uint32_t PCON;
-  __IO uint32_t PCONP;
-       uint32_t RESERVED3[15];
-  __IO uint32_t CCLKCFG;
-  __IO uint32_t USBCLKCFG;
-  __IO uint32_t CLKSRCSEL;
-  __IO uint32_t	CANSLEEPCLR;
-  __IO uint32_t	CANWAKEFLAGS;
-       uint32_t RESERVED4[10];
-  __IO uint32_t EXTINT;                 /* External Interrupts                */
-       uint32_t RESERVED5;
-  __IO uint32_t EXTMODE;
-  __IO uint32_t EXTPOLAR;
-       uint32_t RESERVED6[12];
-  __IO uint32_t RSID;                   /* Reset                              */
-       uint32_t RESERVED7[7];
-  __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */
-  __IO uint32_t IRCTRIM;                /* Clock Dividers                     */
-  __IO uint32_t PCLKSEL0;
-  __IO uint32_t PCLKSEL1;
-       uint32_t RESERVED8[4];
-  __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */
-  __IO uint32_t DMAREQSEL;
-  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */
- } LPC_SC_TypeDef;
-
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/
-typedef struct
-{
-  __IO uint32_t PINSEL0;
-  __IO uint32_t PINSEL1;
-  __IO uint32_t PINSEL2;
-  __IO uint32_t PINSEL3;
-  __IO uint32_t PINSEL4;
-  __IO uint32_t PINSEL5;
-  __IO uint32_t PINSEL6;
-  __IO uint32_t PINSEL7;
-  __IO uint32_t PINSEL8;
-  __IO uint32_t PINSEL9;
-  __IO uint32_t PINSEL10;
-       uint32_t RESERVED0[5];
-  __IO uint32_t PINMODE0;
-  __IO uint32_t PINMODE1;
-  __IO uint32_t PINMODE2;
-  __IO uint32_t PINMODE3;
-  __IO uint32_t PINMODE4;
-  __IO uint32_t PINMODE5;
-  __IO uint32_t PINMODE6;
-  __IO uint32_t PINMODE7;
-  __IO uint32_t PINMODE8;
-  __IO uint32_t PINMODE9;
-  __IO uint32_t PINMODE_OD0;
-  __IO uint32_t PINMODE_OD1;
-  __IO uint32_t PINMODE_OD2;
-  __IO uint32_t PINMODE_OD3;
-  __IO uint32_t PINMODE_OD4;
-  __IO uint32_t I2CPADCFG;
-} LPC_PINCON_TypeDef;
-
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-typedef struct
-{
-  union {
-    __IO uint32_t FIODIR;
-    struct {
-      __IO uint16_t FIODIRL;
-      __IO uint16_t FIODIRH;
-    };
-    struct {
-      __IO uint8_t  FIODIR0;
-      __IO uint8_t  FIODIR1;
-      __IO uint8_t  FIODIR2;
-      __IO uint8_t  FIODIR3;
-    };
-  };
-  uint32_t RESERVED0[3];
-  union {
-    __IO uint32_t FIOMASK;
-    struct {
-      __IO uint16_t FIOMASKL;
-      __IO uint16_t FIOMASKH;
-    };
-    struct {
-      __IO uint8_t  FIOMASK0;
-      __IO uint8_t  FIOMASK1;
-      __IO uint8_t  FIOMASK2;
-      __IO uint8_t  FIOMASK3;
-    };
-  };
-  union {
-    __IO uint32_t FIOPIN;
-    struct {
-      __IO uint16_t FIOPINL;
-      __IO uint16_t FIOPINH;
-    };
-    struct {
-      __IO uint8_t  FIOPIN0;
-      __IO uint8_t  FIOPIN1;
-      __IO uint8_t  FIOPIN2;
-      __IO uint8_t  FIOPIN3;
-    };
-  };
-  union {
-    __IO uint32_t FIOSET;
-    struct {
-      __IO uint16_t FIOSETL;
-      __IO uint16_t FIOSETH;
-    };
-    struct {
-      __IO uint8_t  FIOSET0;
-      __IO uint8_t  FIOSET1;
-      __IO uint8_t  FIOSET2;
-      __IO uint8_t  FIOSET3;
-    };
-  };
-  union {
-    __O  uint32_t FIOCLR;
-    struct {
-      __O  uint16_t FIOCLRL;
-      __O  uint16_t FIOCLRH;
-    };
-    struct {
-      __O  uint8_t  FIOCLR0;
-      __O  uint8_t  FIOCLR1;
-      __O  uint8_t  FIOCLR2;
-      __O  uint8_t  FIOCLR3;
-    };
-  };
-} LPC_GPIO_TypeDef;
-
-typedef struct
-{
-  __I  uint32_t IntStatus;
-  __I  uint32_t IO0IntStatR;
-  __I  uint32_t IO0IntStatF;
-  __O  uint32_t IO0IntClr;
-  __IO uint32_t IO0IntEnR;
-  __IO uint32_t IO0IntEnF;
-       uint32_t RESERVED0[3];
-  __I  uint32_t IO2IntStatR;
-  __I  uint32_t IO2IntStatF;
-  __O  uint32_t IO2IntClr;
-  __IO uint32_t IO2IntEnR;
-  __IO uint32_t IO2IntEnF;
-} LPC_GPIOINT_TypeDef;
-
-/*------------- Timer (TIM) --------------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;
-  __IO uint32_t TCR;
-  __IO uint32_t TC;
-  __IO uint32_t PR;
-  __IO uint32_t PC;
-  __IO uint32_t MCR;
-  __IO uint32_t MR0;
-  __IO uint32_t MR1;
-  __IO uint32_t MR2;
-  __IO uint32_t MR3;
-  __IO uint32_t CCR;
-  __I  uint32_t CR0;
-  __I  uint32_t CR1;
-       uint32_t RESERVED0[2];
-  __IO uint32_t EMR;
-       uint32_t RESERVED1[12];
-  __IO uint32_t CTCR;
-} LPC_TIM_TypeDef;
-
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;
-  __IO uint32_t TCR;
-  __IO uint32_t TC;
-  __IO uint32_t PR;
-  __IO uint32_t PC;
-  __IO uint32_t MCR;
-  __IO uint32_t MR0;
-  __IO uint32_t MR1;
-  __IO uint32_t MR2;
-  __IO uint32_t MR3;
-  __IO uint32_t CCR;
-  __I  uint32_t CR0;
-  __I  uint32_t CR1;
-  __I  uint32_t CR2;
-  __I  uint32_t CR3;
-       uint32_t RESERVED0;
-  __IO uint32_t MR4;
-  __IO uint32_t MR5;
-  __IO uint32_t MR6;
-  __IO uint32_t PCR;
-  __IO uint32_t LER;
-       uint32_t RESERVED1[7];
-  __IO uint32_t CTCR;
-} LPC_PWM_TypeDef;
-
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[7];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED2[7];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED3[3];
-  __IO uint32_t ACR;
-  __IO uint8_t  ICR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  FDR;
-       uint8_t  RESERVED5[7];
-  __IO uint8_t  TER;
-       uint8_t  RESERVED6[39];
-  __IO uint32_t FIFOLVL;
-} LPC_UART_TypeDef;
-
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[7];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED2[7];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED3[3];
-  __IO uint32_t ACR;
-  __IO uint8_t  ICR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  FDR;
-       uint8_t  RESERVED5[7];
-  __IO uint8_t  TER;
-       uint8_t  RESERVED6[39];
-  __IO uint32_t FIFOLVL;
-} LPC_UART0_TypeDef;
-
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  MCR;
-       uint8_t  RESERVED2[3];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED3[3];
-  __I  uint8_t  MSR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED5[3];
-  __IO uint32_t ACR;
-       uint32_t RESERVED6;
-  __IO uint32_t FDR;
-       uint32_t RESERVED7;
-  __IO uint8_t  TER;
-       uint8_t  RESERVED8[27];
-  __IO uint8_t  RS485CTRL;
-       uint8_t  RESERVED9[3];
-  __IO uint8_t  ADRMATCH;
-       uint8_t  RESERVED10[3];
-  __IO uint8_t  RS485DLY;
-       uint8_t  RESERVED11[3];
-  __IO uint32_t FIFOLVL;
-} LPC_UART1_TypeDef;
-
-/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t SPCR;
-  __I  uint32_t SPSR;
-  __IO uint32_t SPDR;
-  __IO uint32_t SPCCR;
-       uint32_t RESERVED0[3];
-  __IO uint32_t SPINT;
-} LPC_SPI_TypeDef;
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-typedef struct
-{
-  __IO uint32_t CR0;
-  __IO uint32_t CR1;
-  __IO uint32_t DR;
-  __I  uint32_t SR;
-  __IO uint32_t CPSR;
-  __IO uint32_t IMSC;
-  __IO uint32_t RIS;
-  __IO uint32_t MIS;
-  __IO uint32_t ICR;
-  __IO uint32_t DMACR;
-} LPC_SSP_TypeDef;
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-typedef struct
-{
-  __IO uint32_t I2CONSET;
-  __I  uint32_t I2STAT;
-  __IO uint32_t I2DAT;
-  __IO uint32_t I2ADR0;
-  __IO uint32_t I2SCLH;
-  __IO uint32_t I2SCLL;
-  __O  uint32_t I2CONCLR;
-  __IO uint32_t MMCTRL;
-  __IO uint32_t I2ADR1;
-  __IO uint32_t I2ADR2;
-  __IO uint32_t I2ADR3;
-  __I  uint32_t I2DATA_BUFFER;
-  __IO uint32_t I2MASK0;
-  __IO uint32_t I2MASK1;
-  __IO uint32_t I2MASK2;
-  __IO uint32_t I2MASK3;
-} LPC_I2C_TypeDef;
-
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t I2SDAO;
-  __IO uint32_t I2SDAI;
-  __O  uint32_t I2STXFIFO;
-  __I  uint32_t I2SRXFIFO;
-  __I  uint32_t I2SSTATE;
-  __IO uint32_t I2SDMA1;
-  __IO uint32_t I2SDMA2;
-  __IO uint32_t I2SIRQ;
-  __IO uint32_t I2STXRATE;
-  __IO uint32_t I2SRXRATE;
-  __IO uint32_t I2STXBITRATE;
-  __IO uint32_t I2SRXBITRATE;
-  __IO uint32_t I2STXMODE;
-  __IO uint32_t I2SRXMODE;
-} LPC_I2S_TypeDef;
-
-/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
-typedef struct
-{
-  __IO uint32_t RICOMPVAL;
-  __IO uint32_t RIMASK;
-  __IO uint8_t  RICTRL;
-       uint8_t  RESERVED0[3];
-  __IO uint32_t RICOUNTER;
-} LPC_RIT_TypeDef;
-
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  ILR;
-       uint8_t  RESERVED0[7];
-  __IO uint8_t  CCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  CIIR;
-       uint8_t  RESERVED2[3];
-  __IO uint8_t  AMR;
-       uint8_t  RESERVED3[3];
-  __I  uint32_t CTIME0;
-  __I  uint32_t CTIME1;
-  __I  uint32_t CTIME2;
-  __IO uint8_t  SEC;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  MIN;
-       uint8_t  RESERVED5[3];
-  __IO uint8_t  HOUR;
-       uint8_t  RESERVED6[3];
-  __IO uint8_t  DOM;
-       uint8_t  RESERVED7[3];
-  __IO uint8_t  DOW;
-       uint8_t  RESERVED8[3];
-  __IO uint16_t DOY;
-       uint16_t RESERVED9;
-  __IO uint8_t  MONTH;
-       uint8_t  RESERVED10[3];
-  __IO uint16_t YEAR;
-       uint16_t RESERVED11;
-  __IO uint32_t CALIBRATION;
-  __IO uint32_t GPREG0;
-  __IO uint32_t GPREG1;
-  __IO uint32_t GPREG2;
-  __IO uint32_t GPREG3;
-  __IO uint32_t GPREG4;
-  __IO uint8_t  RTC_AUXEN;
-       uint8_t  RESERVED12[3];
-  __IO uint8_t  RTC_AUX;
-       uint8_t  RESERVED13[3];
-  __IO uint8_t  ALSEC;
-       uint8_t  RESERVED14[3];
-  __IO uint8_t  ALMIN;
-       uint8_t  RESERVED15[3];
-  __IO uint8_t  ALHOUR;
-       uint8_t  RESERVED16[3];
-  __IO uint8_t  ALDOM;
-       uint8_t  RESERVED17[3];
-  __IO uint8_t  ALDOW;
-       uint8_t  RESERVED18[3];
-  __IO uint16_t ALDOY;
-       uint16_t RESERVED19;
-  __IO uint8_t  ALMON;
-       uint8_t  RESERVED20[3];
-  __IO uint16_t ALYEAR;
-       uint16_t RESERVED21;
-} LPC_RTC_TypeDef;
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  WDMOD;
-       uint8_t  RESERVED0[3];
-  __IO uint32_t WDTC;
-  __O  uint8_t  WDFEED;
-       uint8_t  RESERVED1[3];
-  __I  uint32_t WDTV;
-  __IO uint32_t WDCLKSEL;
-} LPC_WDT_TypeDef;
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t ADCR;
-  __IO uint32_t ADGDR;
-       uint32_t RESERVED0;
-  __IO uint32_t ADINTEN;
-  __I  uint32_t ADDR0;
-  __I  uint32_t ADDR1;
-  __I  uint32_t ADDR2;
-  __I  uint32_t ADDR3;
-  __I  uint32_t ADDR4;
-  __I  uint32_t ADDR5;
-  __I  uint32_t ADDR6;
-  __I  uint32_t ADDR7;
-  __I  uint32_t ADSTAT;
-  __IO uint32_t ADTRM;
-} LPC_ADC_TypeDef;
-
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t DACR;
-  __IO uint32_t DACCTRL;
-  __IO uint16_t DACCNTVAL;
-} LPC_DAC_TypeDef;
-
-/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
-typedef struct
-{
-  __I  uint32_t MCCON;
-  __O  uint32_t MCCON_SET;
-  __O  uint32_t MCCON_CLR;
-  __I  uint32_t MCCAPCON;
-  __O  uint32_t MCCAPCON_SET;
-  __O  uint32_t MCCAPCON_CLR;
-  __IO uint32_t MCTIM0;
-  __IO uint32_t MCTIM1;
-  __IO uint32_t MCTIM2;
-  __IO uint32_t MCPER0;
-  __IO uint32_t MCPER1;
-  __IO uint32_t MCPER2;
-  __IO uint32_t MCPW0;
-  __IO uint32_t MCPW1;
-  __IO uint32_t MCPW2;
-  __IO uint32_t MCDEADTIME;
-  __IO uint32_t MCCCP;
-  __IO uint32_t MCCR0;
-  __IO uint32_t MCCR1;
-  __IO uint32_t MCCR2;
-  __I  uint32_t MCINTEN;
-  __O  uint32_t MCINTEN_SET;
-  __O  uint32_t MCINTEN_CLR;
-  __I  uint32_t MCCNTCON;
-  __O  uint32_t MCCNTCON_SET;
-  __O  uint32_t MCCNTCON_CLR;
-  __I  uint32_t MCINTFLAG;
-  __O  uint32_t MCINTFLAG_SET;
-  __O  uint32_t MCINTFLAG_CLR;
-  __O  uint32_t MCCAP_CLR;
-} LPC_MCPWM_TypeDef;
-
-/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
-typedef struct
-{
-  __O  uint32_t QEICON;
-  __I  uint32_t QEISTAT;
-  __IO uint32_t QEICONF;
-  __I  uint32_t QEIPOS;
-  __IO uint32_t QEIMAXPOS;
-  __IO uint32_t CMPOS0;
-  __IO uint32_t CMPOS1;
-  __IO uint32_t CMPOS2;
-  __I  uint32_t INXCNT;
-  __IO uint32_t INXCMP;
-  __IO uint32_t QEILOAD;
-  __I  uint32_t QEITIME;
-  __I  uint32_t QEIVEL;
-  __I  uint32_t QEICAP;
-  __IO uint32_t VELCOMP;
-  __IO uint32_t FILTER;
-       uint32_t RESERVED0[998];
-  __O  uint32_t QEIIEC;
-  __O  uint32_t QEIIES;
-  __I  uint32_t QEIINTSTAT;
-  __I  uint32_t QEIIE;
-  __O  uint32_t QEICLR;
-  __O  uint32_t QEISET;
-} LPC_QEI_TypeDef;
-
-/*------------- Controller Area Network (CAN) --------------------------------*/
-typedef struct
-{
-  __IO uint32_t mask[512];              /* ID Masks                           */
-} LPC_CANAF_RAM_TypeDef;
-
-typedef struct                          /* Acceptance Filter Registers        */
-{
-  __IO uint32_t AFMR;
-  __IO uint32_t SFF_sa;
-  __IO uint32_t SFF_GRP_sa;
-  __IO uint32_t EFF_sa;
-  __IO uint32_t EFF_GRP_sa;
-  __IO uint32_t ENDofTable;
-  __I  uint32_t LUTerrAd;
-  __I  uint32_t LUTerr;
-  __IO uint32_t FCANIE;
-  __IO uint32_t FCANIC0;
-  __IO uint32_t FCANIC1;
-} LPC_CANAF_TypeDef;
-
-typedef struct                          /* Central Registers                  */
-{
-  __I  uint32_t CANTxSR;
-  __I  uint32_t CANRxSR;
-  __I  uint32_t CANMSR;
-} LPC_CANCR_TypeDef;
-
-typedef struct                          /* Controller Registers               */
-{
-  __IO uint32_t MOD;
-  __O  uint32_t CMR;
-  __IO uint32_t GSR;
-  __I  uint32_t ICR;
-  __IO uint32_t IER;
-  __IO uint32_t BTR;
-  __IO uint32_t EWL;
-  __I  uint32_t SR;
-  __IO uint32_t RFS;
-  __IO uint32_t RID;
-  __IO uint32_t RDA;
-  __IO uint32_t RDB;
-  __IO uint32_t TFI1;
-  __IO uint32_t TID1;
-  __IO uint32_t TDA1;
-  __IO uint32_t TDB1;
-  __IO uint32_t TFI2;
-  __IO uint32_t TID2;
-  __IO uint32_t TDA2;
-  __IO uint32_t TDB2;
-  __IO uint32_t TFI3;
-  __IO uint32_t TID3;
-  __IO uint32_t TDA3;
-  __IO uint32_t TDB3;
-} LPC_CAN_TypeDef;
-
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
-typedef struct                          /* Common Registers                   */
-{
-  __I  uint32_t DMACIntStat;
-  __I  uint32_t DMACIntTCStat;
-  __O  uint32_t DMACIntTCClear;
-  __I  uint32_t DMACIntErrStat;
-  __O  uint32_t DMACIntErrClr;
-  __I  uint32_t DMACRawIntTCStat;
-  __I  uint32_t DMACRawIntErrStat;
-  __I  uint32_t DMACEnbldChns;
-  __IO uint32_t DMACSoftBReq;
-  __IO uint32_t DMACSoftSReq;
-  __IO uint32_t DMACSoftLBReq;
-  __IO uint32_t DMACSoftLSReq;
-  __IO uint32_t DMACConfig;
-  __IO uint32_t DMACSync;
-} LPC_GPDMA_TypeDef;
-
-typedef struct                          /* Channel Registers                  */
-{
-  __IO uint32_t DMACCSrcAddr;
-  __IO uint32_t DMACCDestAddr;
-  __IO uint32_t DMACCLLI;
-  __IO uint32_t DMACCControl;
-  __IO uint32_t DMACCConfig;
-} LPC_GPDMACH_TypeDef;
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-typedef struct
-{
-  __I  uint32_t HcRevision;             /* USB Host Registers                 */
-  __IO uint32_t HcControl;
-  __IO uint32_t HcCommandStatus;
-  __IO uint32_t HcInterruptStatus;
-  __IO uint32_t HcInterruptEnable;
-  __IO uint32_t HcInterruptDisable;
-  __IO uint32_t HcHCCA;
-  __I  uint32_t HcPeriodCurrentED;
-  __IO uint32_t HcControlHeadED;
-  __IO uint32_t HcControlCurrentED;
-  __IO uint32_t HcBulkHeadED;
-  __IO uint32_t HcBulkCurrentED;
-  __I  uint32_t HcDoneHead;
-  __IO uint32_t HcFmInterval;
-  __I  uint32_t HcFmRemaining;
-  __I  uint32_t HcFmNumber;
-  __IO uint32_t HcPeriodicStart;
-  __IO uint32_t HcLSTreshold;
-  __IO uint32_t HcRhDescriptorA;
-  __IO uint32_t HcRhDescriptorB;
-  __IO uint32_t HcRhStatus;
-  __IO uint32_t HcRhPortStatus1;
-  __IO uint32_t HcRhPortStatus2;
-       uint32_t RESERVED0[40];
-  __I  uint32_t Module_ID;
-
-  __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */
-  __IO uint32_t OTGIntEn;
-  __O  uint32_t OTGIntSet;
-  __O  uint32_t OTGIntClr;
-  __IO uint32_t OTGStCtrl;
-  __IO uint32_t OTGTmr;
-       uint32_t RESERVED1[58];
-
-  __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */
-  __IO uint32_t USBDevIntEn;
-  __O  uint32_t USBDevIntClr;
-  __O  uint32_t USBDevIntSet;
-
-  __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */
-  __I  uint32_t USBCmdData;
-
-  __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */
-  __O  uint32_t USBTxData;
-  __I  uint32_t USBRxPLen;
-  __O  uint32_t USBTxPLen;
-  __IO uint32_t USBCtrl;
-  __O  uint32_t USBDevIntPri;
-
-  __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */
-  __IO uint32_t USBEpIntEn;
-  __O  uint32_t USBEpIntClr;
-  __O  uint32_t USBEpIntSet;
-  __O  uint32_t USBEpIntPri;
-
-  __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/
-  __O  uint32_t USBEpInd;
-  __IO uint32_t USBMaxPSize;
-
-  __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */
-  __O  uint32_t USBDMARClr;
-  __O  uint32_t USBDMARSet;
-       uint32_t RESERVED2[9];
-  __IO uint32_t USBUDCAH;
-  __I  uint32_t USBEpDMASt;
-  __O  uint32_t USBEpDMAEn;
-  __O  uint32_t USBEpDMADis;
-  __I  uint32_t USBDMAIntSt;
-  __IO uint32_t USBDMAIntEn;
-       uint32_t RESERVED3[2];
-  __I  uint32_t USBEoTIntSt;
-  __O  uint32_t USBEoTIntClr;
-  __O  uint32_t USBEoTIntSet;
-  __I  uint32_t USBNDDRIntSt;
-  __O  uint32_t USBNDDRIntClr;
-  __O  uint32_t USBNDDRIntSet;
-  __I  uint32_t USBSysErrIntSt;
-  __O  uint32_t USBSysErrIntClr;
-  __O  uint32_t USBSysErrIntSet;
-       uint32_t RESERVED4[15];
-
-  union {
-  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
-  __O  uint32_t I2C_TX;
-  };
-  __I  uint32_t I2C_STS;
-  __IO uint32_t I2C_CTL;
-  __IO uint32_t I2C_CLKHI;
-  __O  uint32_t I2C_CLKLO;
-       uint32_t RESERVED5[824];
-
-  union {
-  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
-  __IO uint32_t OTGClkCtrl;
-  };
-  union {
-  __I  uint32_t USBClkSt;
-  __I  uint32_t OTGClkSt;
-  };
-} LPC_USB_TypeDef;
-
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
-typedef struct
-{
-  __IO uint32_t MAC1;                   /* MAC Registers                      */
-  __IO uint32_t MAC2;
-  __IO uint32_t IPGT;
-  __IO uint32_t IPGR;
-  __IO uint32_t CLRT;
-  __IO uint32_t MAXF;
-  __IO uint32_t SUPP;
-  __IO uint32_t TEST;
-  __IO uint32_t MCFG;
-  __IO uint32_t MCMD;
-  __IO uint32_t MADR;
-  __O  uint32_t MWTD;
-  __I  uint32_t MRDD;
-  __I  uint32_t MIND;
-       uint32_t RESERVED0[2];
-  __IO uint32_t SA0;
-  __IO uint32_t SA1;
-  __IO uint32_t SA2;
-       uint32_t RESERVED1[45];
-  __IO uint32_t Command;                /* Control Registers                  */
-  __I  uint32_t Status;
-  __IO uint32_t RxDescriptor;
-  __IO uint32_t RxStatus;
-  __IO uint32_t RxDescriptorNumber;
-  __I  uint32_t RxProduceIndex;
-  __IO uint32_t RxConsumeIndex;
-  __IO uint32_t TxDescriptor;
-  __IO uint32_t TxStatus;
-  __IO uint32_t TxDescriptorNumber;
-  __IO uint32_t TxProduceIndex;
-  __I  uint32_t TxConsumeIndex;
-       uint32_t RESERVED2[10];
-  __I  uint32_t TSV0;
-  __I  uint32_t TSV1;
-  __I  uint32_t RSV;
-       uint32_t RESERVED3[3];
-  __IO uint32_t FlowControlCounter;
-  __I  uint32_t FlowControlStatus;
-       uint32_t RESERVED4[34];
-  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
-  __IO uint32_t RxFilterWoLStatus;
-  __IO uint32_t RxFilterWoLClear;
-       uint32_t RESERVED5;
-  __IO uint32_t HashFilterL;
-  __IO uint32_t HashFilterH;
-       uint32_t RESERVED6[882];
-  __I  uint32_t IntStatus;              /* Module Control Registers           */
-  __IO uint32_t IntEnable;
-  __O  uint32_t IntClear;
-  __O  uint32_t IntSet;
-       uint32_t RESERVED7;
-  __IO uint32_t PowerDown;
-       uint32_t RESERVED8;
-  __IO uint32_t Module_ID;
-} LPC_EMAC_TypeDef;
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#endif
-
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-#define LPC_FLASH_BASE        (0x00000000UL)
-#define LPC_RAM_BASE          (0x10000000UL)
-#define LPC_GPIO_BASE         (0x2009C000UL)
-#define LPC_APB0_BASE         (0x40000000UL)
-#define LPC_APB1_BASE         (0x40080000UL)
-#define LPC_AHB_BASE          (0x50000000UL)
-#define LPC_CM3_BASE          (0xE0000000UL)
-
-/* APB0 peripherals                                                           */
-#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)
-#define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)
-#define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)
-#define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)
-#define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)
-#define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)
-#define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)
-#define LPC_SPI_BASE          (LPC_APB0_BASE + 0x20000)
-#define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)
-#define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)
-#define LPC_PINCON_BASE       (LPC_APB0_BASE + 0x2C000)
-#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)
-#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)
-#define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)
-#define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)
-#define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)
-#define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)
-#define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)
-#define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)
-
-/* APB1 peripherals                                                           */
-#define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)
-#define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)
-#define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)
-#define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)
-#define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)
-#define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)
-#define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)
-#define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)
-#define LPC_RIT_BASE          (LPC_APB1_BASE + 0x30000)
-#define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)
-#define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)
-#define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)
-
-/* AHB peripherals                                                            */
-#define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x04000)
-#define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x04100)
-#define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x04120)
-#define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x04140)
-#define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x04160)
-#define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x04180)
-#define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x041A0)
-#define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x041C0)
-#define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x041E0)
-#define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)
-
-/* GPIOs                                                                      */
-#define LPC_GPIO0_BASE        (LPC_GPIO_BASE + 0x00000)
-#define LPC_GPIO1_BASE        (LPC_GPIO_BASE + 0x00020)
-#define LPC_GPIO2_BASE        (LPC_GPIO_BASE + 0x00040)
-#define LPC_GPIO3_BASE        (LPC_GPIO_BASE + 0x00060)
-#define LPC_GPIO4_BASE        (LPC_GPIO_BASE + 0x00080)
-
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )
-#define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )
-#define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )
-#define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )
-#define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )
-#define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )
-#define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )
-#define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )
-#define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )
-#define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )
-#define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )
-#define LPC_RIT               ((LPC_RIT_TypeDef       *) LPC_RIT_BASE      )
-#define LPC_UART0             ((LPC_UART0_TypeDef     *) LPC_UART0_BASE    )
-#define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )
-#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
-#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
-#define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )
-#define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )
-#define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )
-#define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )
-#define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )
-#define LPC_SPI               ((LPC_SPI_TypeDef       *) LPC_SPI_BASE      )
-#define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )
-#define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )
-#define LPC_PINCON            ((LPC_PINCON_TypeDef    *) LPC_PINCON_BASE   )
-#define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )
-#define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )
-#define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )
-#define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )
-#define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
-#define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )
-#define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )
-#define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )
-#define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )
-#define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )
-#define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )
-#define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )
-#define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )
-#define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )
-#define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )
-#define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )
-#define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )
-#define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )
-#define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )
-#define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )
-#define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )
-#define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )
-
-#endif  // __LPC17xx_H__

--- a/vendor/NXP/LPC1768/cmsis/cmsis.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,13 +0,0 @@
-/* mbed Microcontroller Library - CMSIS
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * A generic CMSIS include header, pulling in LPC1768 specifics
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "LPC17xx.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/vendor/NXP/LPC1768/cmsis/cmsis_nvic.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic for LCP1768
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-#include "cmsis_nvic.h"
-
-#define NVIC_NUM_VECTORS          (16 + 33)     // CORE + MCU Peripherals
-#define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Location of vectors in RAM
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-    static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
-    int i;
-    // Copy and switch to dynamic vectors if first time called
-    if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
-        uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
-        for (i=0; i<NVIC_NUM_VECTORS; i++) {
-            vectors[i] = old_vectors[i];
-        }
-        SCB->VTOR = (uint32_t)vectors;
-    }
-    
-    vectors[IRQn + 16] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t *vectors = (uint32_t*)SCB->VTOR;
-    return vectors[IRQn + 16];
-}
-

--- a/vendor/NXP/LPC1768/cmsis/cmsis_nvic.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,23 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC1768/cmsis/core_cm3.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,339 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.c
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version  V2.02
- * @date     24. March 2011
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-
-/* ##########################  Core Instruction Access  ######################### */
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __CLREX(void)
-{
-  clrex
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_CONTROL(void)
-{
-  mrs r0, control
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_CONTROL(uint32_t control)
-{
-  msr control, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_IPSR(void)
-{
-  mrs r0, ipsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_APSR(void)
-{
-  mrs r0, apsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_xPSR(void)
-{
-  mrs r0, xpsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_PSP(void)
-{
-  mrs r0, psp
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
-  msr psp, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_MSP(void)
-{
-  mrs r0, msp
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
-  msr msp, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t  __get_BASEPRI(void)
-{
-  mrs r0, basepri
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
-  msr basepri, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
- 
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_PRIMASK(void)
-{
-  mrs r0, primask
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
-  msr primask, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
- 
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask Register.
-
-    \return               Fault Mask value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t  __get_FAULTMASK(void)
-{
-  mrs r0, faultmask
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set the Fault Mask
-
-     This function assigns the given value to the Fault Mask Register.
-
-    \param [in]    faultMask  Fault Mask value value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
-  msr faultmask, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif

--- a/vendor/NXP/LPC1768/cmsis/core_cm3.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1612 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V3.02
- * @date     16. July 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M3
-  @{
- */
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM3_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM3_REV
-    #define __CM3_REV               0x0200
-    #warning "__CM3_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if (__CM3_REV < 0x0201)                   /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1[1];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                                 |
-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
-
-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

--- a/vendor/NXP/LPC1768/cmsis/core_cmFunc.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,616 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V3.02
- * @date     24. May 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */

--- a/vendor/NXP/LPC1768/cmsis/core_cmInstr.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,643 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V3.03
- * @date     29. August 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-#define __ISB()                           __isb(0xF)
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()                           __dsb(0xF)
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB()                           __dmb(0xF)
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __RBIT                            __rbit
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-
-  __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
-  return(op1);
-}
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint8_t result;
-
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint16_t result;
-
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
-  uint8_t result;
-
-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

--- a/vendor/NXP/LPC1768/cmsis/system_LPC17xx.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,584 +0,0 @@
-/**************************************************************************//**
- * @file     system_LPC17xx.c
- * @brief    CMSIS Cortex-M3 Device System Source File for
- *           NXP LPC17xx Device Series
- * @version  V1.11
- * @date     21. June 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#include <stdint.h>
-#include "LPC17xx.h"
-
-
-/** @addtogroup LPC17xx_System
- * @{
- */
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-
-/*--------------------- Clock Configuration ----------------------------------
-//
-// <e> Clock Configuration
-//   <h> System Controls and Status Register (SCS)
-//     <o1.4>    OSCRANGE: Main Oscillator Range Select
-//                     <0=>  1 MHz to 20 MHz
-//                     <1=> 15 MHz to 25 MHz
-//     <e1.5>       OSCEN: Main Oscillator Enable
-//     </e>
-//   </h>
-//
-//   <h> Clock Source Select Register (CLKSRCSEL)
-//     <o2.0..1>   CLKSRC: PLL Clock Source Selection
-//                     <0=> Internal RC oscillator
-//                     <1=> Main oscillator
-//                     <2=> RTC oscillator
-//   </h>
-//
-//   <e3> PLL0 Configuration (Main PLL)
-//     <h> PLL0 Configuration Register (PLL0CFG)
-//                     <i> F_cco0 = (2 * M * F_in) / N
-//                     <i> F_in must be in the range of 32 kHz to 50 MHz
-//                     <i> F_cco0 must be in the range of 275 MHz to 550 MHz
-//       <o4.0..14>  MSEL: PLL Multiplier Selection
-//                     <6-32768><#-1>
-//                     <i> M Value
-//       <o4.16..23> NSEL: PLL Divider Selection
-//                     <1-256><#-1>
-//                     <i> N Value
-//     </h>
-//   </e>
-//
-//   <e5> PLL1 Configuration (USB PLL)
-//     <h> PLL1 Configuration Register (PLL1CFG)
-//                     <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
-//                     <i> F_cco1 = F_osc * M * 2 * P
-//                     <i> F_cco1 must be in the range of 156 MHz to 320 MHz
-//       <o6.0..4>   MSEL: PLL Multiplier Selection
-//                     <1-32><#-1>
-//                     <i> M Value (for USB maximum value is 4)
-//       <o6.5..6>   PSEL: PLL Divider Selection
-//                     <0=> 1
-//                     <1=> 2
-//                     <2=> 4
-//                     <3=> 8
-//                     <i> P Value
-//     </h>
-//   </e>
-//
-//   <h> CPU Clock Configuration Register (CCLKCFG)
-//     <o7.0..7>  CCLKSEL: Divide Value for CPU Clock from PLL0
-//                     <1-256><#-1>
-//   </h>
-//
-//   <h> USB Clock Configuration Register (USBCLKCFG)
-//     <o8.0..3>   USBSEL: Divide Value for USB Clock from PLL0
-//                     <0-15>
-//                     <i> Divide is USBSEL + 1
-//   </h>
-//
-//   <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
-//     <o9.0..1>    PCLK_WDT: Peripheral Clock Selection for WDT
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.2..3>    PCLK_TIMER0: Peripheral Clock Selection for TIMER0
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.4..5>    PCLK_TIMER1: Peripheral Clock Selection for TIMER1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.6..7>    PCLK_UART0: Peripheral Clock Selection for UART0
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.8..9>    PCLK_UART1: Peripheral Clock Selection for UART1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.12..13>  PCLK_PWM1: Peripheral Clock Selection for PWM1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.14..15>  PCLK_I2C0: Peripheral Clock Selection for I2C0
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.16..17>  PCLK_SPI: Peripheral Clock Selection for SPI
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.20..21>  PCLK_SSP1: Peripheral Clock Selection for SSP1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.22..23>  PCLK_DAC: Peripheral Clock Selection for DAC
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.24..25>  PCLK_ADC: Peripheral Clock Selection for ADC
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.26..27>  PCLK_CAN1: Peripheral Clock Selection for CAN1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 6
-//     <o9.28..29>  PCLK_CAN2: Peripheral Clock Selection for CAN2
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 6
-//     <o9.30..31>  PCLK_ACF: Peripheral Clock Selection for ACF
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 6
-//   </h>
-//
-//   <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
-//     <o10.0..1>   PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.2..3>   PCLK_GPIO: Peripheral Clock Selection for GPIOs
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.4..5>   PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.6..7>   PCLK_I2C1: Peripheral Clock Selection for I2C1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//   </h>
-//
-//   <h> Power Control for Peripherals Register (PCONP)
-//     <o11.1>      PCTIM0: Timer/Counter 0 power/clock enable
-//     <o11.2>      PCTIM1: Timer/Counter 1 power/clock enable
-//     <o11.3>      PCUART0: UART 0 power/clock enable
-//     <o11.4>      PCUART1: UART 1 power/clock enable
-//     <o11.6>      PCPWM1: PWM 1 power/clock enable
-//     <o11.7>      PCI2C0: I2C interface 0 power/clock enable
-//     <o11.8>      PCSPI: SPI interface power/clock enable
-//     <o11.9>      PCRTC: RTC power/clock enable
-//     <o11.10>     PCSSP1: SSP interface 1 power/clock enable
-//     <o11.12>     PCAD: A/D converter power/clock enable
-//     <o11.13>     PCCAN1: CAN controller 1 power/clock enable
-//     <o11.14>     PCCAN2: CAN controller 2 power/clock enable
-//     <o11.15>     PCGPIO: GPIOs power/clock enable
-//     <o11.16>     PCRIT: Repetitive interrupt timer power/clock enable
-//     <o11.17>     PCMC: Motor control PWM power/clock enable
-//     <o11.18>     PCQEI: Quadrature encoder interface power/clock enable
-//     <o11.19>     PCI2C1: I2C interface 1 power/clock enable
-//     <o11.21>     PCSSP0: SSP interface 0 power/clock enable
-//     <o11.22>     PCTIM2: Timer 2 power/clock enable
-//     <o11.23>     PCTIM3: Timer 3 power/clock enable
-//     <o11.24>     PCUART2: UART 2 power/clock enable
-//     <o11.25>     PCUART3: UART 3 power/clock enable
-//     <o11.26>     PCI2C2: I2C interface 2 power/clock enable
-//     <o11.27>     PCI2S: I2S interface power/clock enable
-//     <o11.29>     PCGPDMA: GP DMA function power/clock enable
-//     <o11.30>     PCENET: Ethernet block power/clock enable
-//     <o11.31>     PCUSB: USB interface power/clock enable
-//   </h>
-//
-//   <h> Clock Output Configuration Register (CLKOUTCFG)
-//     <o12.0..3>   CLKOUTSEL: Selects clock source for CLKOUT
-//                     <0=> CPU clock
-//                     <1=> Main oscillator
-//                     <2=> Internal RC oscillator
-//                     <3=> USB clock
-//                     <4=> RTC oscillator
-//     <o12.4..7>   CLKOUTDIV: Selects clock divider for CLKOUT
-//                     <1-16><#-1>
-//     <o12.8>      CLKOUT_EN: CLKOUT enable control
-//   </h>
-//
-// </e>
-*/
-
-
-
-/** @addtogroup LPC17xx_System_Defines  LPC17xx System Defines
-  @{
- */
-
-#define CLOCK_SETUP           1
-#define SCS_Val               0x00000020
-#define CLKSRCSEL_Val         0x00000001
-#define PLL0_SETUP            1
-
-#ifdef MCB1700
-#    define PLL0CFG_Val           0x00050063
-#    define PLL1_SETUP            1
-#    define PLL1CFG_Val           0x00000023
-#    define CCLKCFG_Val           0x00000003
-#    define USBCLKCFG_Val         0x00000000
-#else
-#    define PLL0CFG_Val           0x0000000B
-#    define PLL1_SETUP            0
-#    define PLL1CFG_Val           0x00000000
-#    define CCLKCFG_Val           0x00000002
-#    define USBCLKCFG_Val         0x00000005
-#endif
-
-#define PCLKSEL0_Val          0x00000000
-#define PCLKSEL1_Val          0x00000000
-#define PCONP_Val             0x042887DE
-#define CLKOUTCFG_Val         0x00000000
-
-
-/*--------------------- Flash Accelerator Configuration ----------------------
-//
-// <e> Flash Accelerator Configuration
-//   <o1.12..15> FLASHTIM: Flash Access Time
-//               <0=> 1 CPU clock (for CPU clock up to 20 MHz)
-//               <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
-//               <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
-//               <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
-//               <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
-//               <5=> 6 CPU clocks (for any CPU clock)
-// </e>
-*/
-#define FLASH_SETUP           1
-#define FLASHCFG_Val          0x0000303A
-
-/*
-//-------- <<< end of configuration section >>> ------------------------------
-*/
-
-/*----------------------------------------------------------------------------
-  Check the register settings
- *----------------------------------------------------------------------------*/
-#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
-#define CHECK_RSVD(val, mask)                     (val & mask)
-
-/* Clock Configuration -------------------------------------------------------*/
-#if (CHECK_RSVD((SCS_Val),       ~0x00000030))
-   #error "SCS: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
-   #error "CLKSRCSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((PLL0CFG_Val),   ~0x00FF7FFF))
-   #error "PLL0CFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
-   #error "PLL1CFG: Invalid values of reserved bits!"
-#endif
-
-#if (PLL0_SETUP)            /* if PLL0 is used */
-  #if (CCLKCFG_Val < 2)     /* CCLKSEL must be greater then 1 */
-    #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
-  #endif
-#endif
-
-#if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
-   #error "CCLKCFG: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
-   #error "USBCLKCFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCLKSEL0_Val),   0x000C0C00))
-   #error "PCLKSEL0: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCLKSEL1_Val),   0x03000300))
-   #error "PCLKSEL1: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCONP_Val),      0x10100821))
-   #error "PCONP: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
-   #error "CLKOUTCFG: Invalid values of reserved bits!"
-#endif
-
-/* Flash Accelerator Configuration -------------------------------------------*/
-#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
-   #error "FLASHCFG: Invalid values of reserved bits!"
-#endif
-
-
-/*----------------------------------------------------------------------------
-  DEFINES
- *----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define XTAL        (12000000UL)        /* Oscillator frequency               */
-#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
-#define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */
-#define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
-
-
-/* F_cco0 = (2 * M * F_in) / N  */
-#define __M               (((PLL0CFG_Val      ) & 0x7FFF) + 1)
-#define __N               (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
-#define __FCCO(__F_IN)    ((2ULL * __M * __F_IN) / __N)
-#define __CCLK_DIV        (((CCLKCFG_Val      ) & 0x00FF) + 1)
-
-/* Determine core clock frequency according to settings */
- #if (PLL0_SETUP)
-    #if   ((CLKSRCSEL_Val & 0x03) == 1)
-        #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
-    #elif ((CLKSRCSEL_Val & 0x03) == 2)
-        #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
-    #else
-        #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
-    #endif
- #else
-    #if   ((CLKSRCSEL_Val & 0x03) == 1)
-        #define __CORE_CLK (OSC_CLK         / __CCLK_DIV)
-    #elif ((CLKSRCSEL_Val & 0x03) == 2)
-        #define __CORE_CLK (RTC_CLK         / __CCLK_DIV)
-    #else
-        #define __CORE_CLK (IRC_OSC         / __CCLK_DIV)
-    #endif
- #endif
-
-/**
- * @}
- */
-
-
-/** @addtogroup LPC17xx_System_Public_Variables  LPC17xx System Public Variables
-  @{
- */
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
-
-/**
- * @}
- */
-
-
-/** @addtogroup LPC17xx_System_Public_Functions  LPC17xx System Public Functions
-  @{
- */
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock
- *         retrieved from cpu registers.
- */void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
-{
-  /* Determine clock frequency according to clock register values             */
-  if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
-    switch (LPC_SC->CLKSRCSEL & 0x03) {
-      case 0:                                /* Int. RC oscillator => PLL0    */
-      case 3:                                /* Reserved, default to Int. RC  */
-        SystemCoreClock = (IRC_OSC *
-                          ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
-                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)       /
-                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
-        break;
-      case 1:                                /* Main oscillator => PLL0       */
-        SystemCoreClock = (OSC_CLK *
-                          ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
-                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)       /
-                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
-        break;
-      case 2:                                /* RTC oscillator => PLL0        */
-        SystemCoreClock = (RTC_CLK *
-                          ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
-                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)       /
-                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
-        break;
-    }
-  } else {
-    switch (LPC_SC->CLKSRCSEL & 0x03) {
-      case 0:                                /* Int. RC oscillator => PLL0    */
-      case 3:                                /* Reserved, default to Int. RC  */
-        SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
-        break;
-      case 1:                                /* Main oscillator => PLL0       */
-        SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
-        break;
-      case 2:                                /* RTC oscillator => PLL0        */
-        SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
-        break;
-    }
-  }
-
-}
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void)
-{
-#if (CLOCK_SETUP)                       /* Clock Setup                        */
-  LPC_SC->SCS       = SCS_Val;
-  if (LPC_SC->SCS & (1 << 5)) {             /* If Main Oscillator is enabled  */
-    while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */
-  }
-
-  LPC_SC->CCLKCFG   = CCLKCFG_Val;      /* Setup Clock Divider                */
-  /* Periphral clock must be selected before PLL0 enabling and connecting
-   * - according errata.lpc1768-16.March.2010 -
-   */
-  LPC_SC->PCLKSEL0  = PCLKSEL0_Val;     /* Peripheral Clock Selection         */
-  LPC_SC->PCLKSEL1  = PCLKSEL1_Val;
-
-#if (PLL0_SETUP)
-  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for PLL0       */
-
-  LPC_SC->PLL0CFG   = PLL0CFG_Val;      /* configure PLL0                     */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-
-  LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-  while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0                    */
-
-  LPC_SC->PLL0CON   = 0x03;             /* PLL0 Enable & Connect              */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-  while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
-#endif
-
-#if (PLL1_SETUP)
-  LPC_SC->PLL1CFG   = PLL1CFG_Val;
-  LPC_SC->PLL1FEED  = 0xAA;
-  LPC_SC->PLL1FEED  = 0x55;
-
-  LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
-  LPC_SC->PLL1FEED  = 0xAA;
-  LPC_SC->PLL1FEED  = 0x55;
-  while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */
-
-  LPC_SC->PLL1CON   = 0x03;             /* PLL1 Enable & Connect              */
-  LPC_SC->PLL1FEED  = 0xAA;
-  LPC_SC->PLL1FEED  = 0x55;
-  while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
-#else
-  LPC_SC->USBCLKCFG = USBCLKCFG_Val;    /* Setup USB Clock Divider            */
-#endif
-
-  LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */
-
-  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
-#endif
-
-#if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
-  LPC_SC->FLASHCFG  = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
-#endif
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */

--- a/vendor/NXP/LPC1768/cmsis/system_LPC17xx.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,60 +0,0 @@
-/******************************************************************************
- * @file:    system_LPC17xx.h
- * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
- *           for the NXP LPC17xx Device Series 
- * @version: V1.02
- * @date:    27. July 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC17xx_H
-#define __SYSTEM_LPC17xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock 
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC17xx_H */

--- a/vendor/NXP/LPC1768/cmsis/uARM/LPC1768.sct	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,22 +0,0 @@
-
-LR_IROM1 0x00000000 0x80000  {    ; load region size_region
-  ER_IROM1 0x00000000 0x80000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; 8_byte_aligned(49 vect * 4 bytes) =  8_byte_aligned(0xC4) = 0xC8
-  ; 32KB - 0xC8 = 0x7F38
-  RW_IRAM1 0x100000C8 0x7F38  {
-   .ANY (+RW +ZI)
-  }
-  RW_IRAM2 0x2007C000 0x4000  {  ; RW data, USB RAM
-   .ANY (AHBSRAM0)
-  }
-  RW_IRAM3 0x20080000 0x4000  {  ; RW data, ETH RAM
-   .ANY (AHBSRAM1)
-  }
-  RW_IRAM4 0x40038000 0x0800  {  ; RW data, CAN RAM
-   .ANY (CANRAM)
-  }
-}

--- a/vendor/NXP/LPC1768/cmsis/uARM/startup_LPC17xx.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,243 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC17xx.s
-; * @purpose: CMSIS Cortex-M3 Core Device Startup File 
-; *           for the NXP LPC17xx Device Series 
-; * @version: V1.02, modified for mbed
-; * @date:    27. July 2009, modified 3rd Aug 2009
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2009 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
-; * processor based microcontrollers.  This file can be freely distributed 
-; * within development tools that are supporting such ARM based processors. 
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __initial_sp
-
-Stack_Mem       SPACE   Stack_Size
-__initial_sp        EQU     0x10008000  ; Top of RAM from LPC1768
-
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ; 16: Watchdog Timer
-                DCD     TIMER0_IRQHandler         ; 17: Timer0
-                DCD     TIMER1_IRQHandler         ; 18: Timer1
-                DCD     TIMER2_IRQHandler         ; 19: Timer2
-                DCD     TIMER3_IRQHandler         ; 20: Timer3
-                DCD     UART0_IRQHandler          ; 21: UART0
-                DCD     UART1_IRQHandler          ; 22: UART1
-                DCD     UART2_IRQHandler          ; 23: UART2
-                DCD     UART3_IRQHandler          ; 24: UART3
-                DCD     PWM1_IRQHandler           ; 25: PWM1
-                DCD     I2C0_IRQHandler           ; 26: I2C0
-                DCD     I2C1_IRQHandler           ; 27: I2C1
-                DCD     I2C2_IRQHandler           ; 28: I2C2
-                DCD     SPI_IRQHandler            ; 29: SPI
-                DCD     SSP0_IRQHandler           ; 30: SSP0
-                DCD     SSP1_IRQHandler           ; 31: SSP1
-                DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
-                DCD     RTC_IRQHandler            ; 33: Real Time Clock
-                DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
-                DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
-                DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
-                DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
-                DCD     ADC_IRQHandler            ; 38: A/D Converter
-                DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
-                DCD     USB_IRQHandler            ; 40: USB
-                DCD     CAN_IRQHandler            ; 41: CAN
-                DCD     DMA_IRQHandler            ; 42: General Purpose DMA
-                DCD     I2S_IRQHandler            ; 43: I2S
-                DCD     ENET_IRQHandler           ; 44: Ethernet
-                DCD     RIT_IRQHandler            ; 45: Repetitive Interrupt Timer
-                DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
-                DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
-                DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
-
-
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)                
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  TIMER0_IRQHandler         [WEAK]
-                EXPORT  TIMER1_IRQHandler         [WEAK]
-                EXPORT  TIMER2_IRQHandler         [WEAK]
-                EXPORT  TIMER3_IRQHandler         [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  PWM1_IRQHandler           [WEAK]
-                EXPORT  I2C0_IRQHandler           [WEAK]
-                EXPORT  I2C1_IRQHandler           [WEAK]
-                EXPORT  I2C2_IRQHandler           [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-                EXPORT  SSP0_IRQHandler           [WEAK]
-                EXPORT  SSP1_IRQHandler           [WEAK]
-                EXPORT  PLL0_IRQHandler           [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  EINT0_IRQHandler          [WEAK]
-                EXPORT  EINT1_IRQHandler          [WEAK]
-                EXPORT  EINT2_IRQHandler          [WEAK]
-                EXPORT  EINT3_IRQHandler          [WEAK]
-                EXPORT  ADC_IRQHandler            [WEAK]
-                EXPORT  BOD_IRQHandler            [WEAK]
-                EXPORT  USB_IRQHandler            [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  DMA_IRQHandler            [WEAK]
-                EXPORT  I2S_IRQHandler            [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  RIT_IRQHandler            [WEAK]
-                EXPORT  MCPWM_IRQHandler          [WEAK]
-                EXPORT  QEI_IRQHandler            [WEAK]
-                EXPORT  PLL1_IRQHandler           [WEAK]
-
-WDT_IRQHandler           
-TIMER0_IRQHandler         
-TIMER1_IRQHandler         
-TIMER2_IRQHandler         
-TIMER3_IRQHandler         
-UART0_IRQHandler          
-UART1_IRQHandler          
-UART2_IRQHandler          
-UART3_IRQHandler          
-PWM1_IRQHandler           
-I2C0_IRQHandler           
-I2C1_IRQHandler           
-I2C2_IRQHandler           
-SPI_IRQHandler            
-SSP0_IRQHandler           
-SSP1_IRQHandler           
-PLL0_IRQHandler           
-RTC_IRQHandler            
-EINT0_IRQHandler          
-EINT1_IRQHandler          
-EINT2_IRQHandler          
-EINT3_IRQHandler          
-ADC_IRQHandler            
-BOD_IRQHandler            
-USB_IRQHandler            
-CAN_IRQHandler            
-DMA_IRQHandler          
-I2S_IRQHandler            
-ENET_IRQHandler       
-RIT_IRQHandler          
-MCPWM_IRQHandler             
-QEI_IRQHandler            
-PLL1_IRQHandler           
-
-                B       .
-
-                ENDP
-                
-                ALIGN
-                END

--- a/vendor/NXP/LPC1768/cmsis/uARM/sys.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * Setup a fixed single stack/heap memory model, 
- *  between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/vendor/NXP/LPC1768/hal/PeripheralNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,80 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    UART_0 = (int)LPC_UART0_BASE,
-    UART_1 = (int)LPC_UART1_BASE,
-    UART_2 = (int)LPC_UART2_BASE,
-    UART_3 = (int)LPC_UART3_BASE
-} UARTName;
-
-typedef enum {
-    ADC0_0 = 0,
-    ADC0_1,
-    ADC0_2,
-    ADC0_3,
-    ADC0_4,
-    ADC0_5,
-    ADC0_6,
-    ADC0_7
-} ADCName;
-
-typedef enum {
-    DAC_0 = 0
-} DACName;
-
-typedef enum {
-    SPI_0 = (int)LPC_SSP0_BASE,
-    SPI_1 = (int)LPC_SSP1_BASE
-} SPIName;
-
-typedef enum {
-    I2C_0 = (int)LPC_I2C0_BASE,
-    I2C_1 = (int)LPC_I2C1_BASE,
-    I2C_2 = (int)LPC_I2C2_BASE
-} I2CName;
-
-typedef enum {
-    PWM_1 = 1,
-    PWM_2,
-    PWM_3,
-    PWM_4,
-    PWM_5,
-    PWM_6
-} PWMName;
-
-typedef enum {
-     CAN_1 = (int)LPC_CAN1_BASE,
-     CAN_2 = (int)LPC_CAN2_BASE
-} CANName;
-
-#define STDIO_UART_TX     USBTX
-#define STDIO_UART_RX     USBRX
-#define STDIO_UART        UART_0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC1768/hal/PinNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,109 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT  5
-
-typedef enum {
-    // LPC Pin Names
-    P0_0 = LPC_GPIO0_BASE,
-          P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
-    P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
-    P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
-    P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
-    P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
-
-    // mbed DIP Pin Names
-    p5 = P0_9,
-    p6 = P0_8,
-    p7 = P0_7,
-    p8 = P0_6,
-    p9 = P0_0,
-    p10 = P0_1,
-    p11 = P0_18,
-    p12 = P0_17,
-    p13 = P0_15,
-    p14 = P0_16,
-    p15 = P0_23,
-    p16 = P0_24,
-    p17 = P0_25,
-    p18 = P0_26,
-    p19 = P1_30,
-    p20 = P1_31,
-    p21 = P2_5,
-    p22 = P2_4,
-    p23 = P2_3,
-    p24 = P2_2,
-    p25 = P2_1,
-    p26 = P2_0,
-    p27 = P0_11,
-    p28 = P0_10,
-    p29 = P0_5,
-    p30 = P0_4,
-
-    // Other mbed Pin Names
-#ifdef MCB1700
-    LED1 = P1_28,
-    LED2 = P1_29,
-    LED3 = P1_31,
-    LED4 = P2_2,
-#else
-    LED1 = P1_18,
-    LED2 = P1_20,
-    LED3 = P1_21,
-    LED4 = P1_23,
-#endif
-    USBTX = P0_2,
-    USBRX = P0_3,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
-    PullUp = 0,
-    PullDown = 3,
-    PullNone = 2,
-    OpenDrain = 4
-} PinMode;
-
-// version of PINCON_TypeDef using register arrays
-typedef struct {
-  __IO uint32_t PINSEL[11];
-       uint32_t RESERVED0[5];
-  __IO uint32_t PINMODE[10];
-  __IO uint32_t PINMODE_OD[5];
-} PINCONARRAY_TypeDef;
-
-#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC1768/hal/PortNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,34 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    Port0 = 0,
-    Port1 = 1,
-    Port2 = 2,
-    Port3 = 3,
-    Port4 = 4
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif

--- a/vendor/NXP/LPC1768/hal/analogin_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,127 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "analogin_api.h"
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-#define ANALOGIN_MEDIAN_FILTER      1
-
-#define ADC_10BIT_RANGE             0x3FF
-#define ADC_12BIT_RANGE             0xFFF
-
-static inline int div_round_up(int x, int y) {
-  return (x + (y - 1)) / y;
-}
-
-static const PinMap PinMap_ADC[] = {
-    {P0_23, ADC0_0, 1},
-    {P0_24, ADC0_1, 1},
-    {P0_25, ADC0_2, 1},
-    {P0_26, ADC0_3, 1},
-    {P1_30, ADC0_4, 3},
-    {P1_31, ADC0_5, 3},
-    {P0_2,  ADC0_7, 2},
-    {P0_3,  ADC0_6, 2},
-    {NC,    NC,     0}
-};
-
-#define ADC_RANGE    ADC_12BIT_RANGE
-
-void analogin_init(analogin_t *obj, PinName pin) {
-    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
-    if (obj->adc == (uint32_t)NC) {
-        error("ADC pin mapping failed");
-    }
-    
-    // ensure power is turned on
-    LPC_SC->PCONP |= (1 << 12);
-    
-    // set PCLK of ADC to /1
-    LPC_SC->PCLKSEL0 &= ~(0x3 << 24);
-    LPC_SC->PCLKSEL0 |= (0x1 << 24);
-    uint32_t PCLK = SystemCoreClock;
-    
-    // calculate minimum clock divider
-    //  clkdiv = divider - 1
-    uint32_t MAX_ADC_CLK = 13000000;
-    uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
-    
-    // Set the generic software-controlled ADC settings
-    LPC_ADC->ADCR = (0 << 0)      // SEL: 0 = no channels selected
-                  | (clkdiv << 8) // CLKDIV: PCLK max ~= 25MHz, /25 to give safe 1MHz at fastest
-                  | (0 << 16)     // BURST: 0 = software control
-                  | (0 << 17)     // CLKS: not applicable
-                  | (1 << 21)     // PDN: 1 = operational
-                  | (0 << 24)     // START: 0 = no start
-                  | (0 << 27);    // EDGE: not applicable
-    
-    pinmap_pinout(pin, PinMap_ADC);
-}
-
-static inline uint32_t adc_read(analogin_t *obj) {
-    // Select the appropriate channel and start conversion
-    LPC_ADC->ADCR &= ~0xFF;
-    LPC_ADC->ADCR |= 1 << (int)obj->adc;
-    LPC_ADC->ADCR |= 1 << 24;
-    
-    // Repeatedly get the sample data until DONE bit
-    unsigned int data;
-    do {
-        data = LPC_ADC->ADGDR;
-    } while ((data & ((unsigned int)1 << 31)) == 0);
-    
-    // Stop conversion
-    LPC_ADC->ADCR &= ~(1 << 24);
-    
-    return (data >> 4) & ADC_RANGE; // 12 bit
-}
-
-static inline void order(uint32_t *a, uint32_t *b) {
-    if (*a > *b) {
-        uint32_t t = *a;
-        *a = *b;
-        *b = t;
-    }
-}
-
-static inline uint32_t adc_read_u32(analogin_t *obj) {
-    uint32_t value;
-#if ANALOGIN_MEDIAN_FILTER
-    uint32_t v1 = adc_read(obj);
-    uint32_t v2 = adc_read(obj);
-    uint32_t v3 = adc_read(obj);
-    order(&v1, &v2);
-    order(&v2, &v3);
-    order(&v1, &v2);
-    value = v2;
-#else
-    value = adc_read(obj);
-#endif
-    return value;
-}
-
-uint16_t analogin_read_u16(analogin_t *obj) {
-    uint32_t value = adc_read_u32(obj);
-    
-    return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
-}
-
-float analogin_read(analogin_t *obj) {
-    uint32_t value = adc_read_u32(obj);
-    return (float)value * (1.0f / (float)ADC_RANGE);
-}

--- a/vendor/NXP/LPC1768/hal/analogout_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,78 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "analogout_api.h"
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_DAC[] = {
-    {P0_26, DAC_0, 2},
-    {NC   , NC   , 0}
-};
-
-void analogout_init(dac_t *obj, PinName pin) {
-    obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
-    if (obj->dac == (uint32_t)NC) {
-        error("DAC pin mapping failed");
-    }
-    
-    // power is on by default, set DAC clk divider is /4
-    LPC_SC->PCLKSEL0 &= ~(0x3 << 22);
-    
-    // map out (must be done before accessing registers)
-    pinmap_pinout(pin, PinMap_DAC);
-    
-    analogout_write_u16(obj, 0);
-}
-
-void analogout_free(dac_t *obj) {}
-
-static inline void dac_write(int value) {
-    value &= 0x3FF; // 10-bit
-    
-    // Set the DAC output
-    LPC_DAC->DACR = (0 << 16)       // bias = 0
-                  | (value << 6);
-}
-
-static inline int dac_read() {
-    return (LPC_DAC->DACR >> 6) & 0x3FF;
-}
-
-void analogout_write(dac_t *obj, float value) {
-    if (value < 0.0f) {
-        dac_write(0);
-    } else if (value > 1.0f) {
-        dac_write(0x3FF);
-    } else {
-        dac_write(value * (float)0x3FF);
-    }
-}
-
-void analogout_write_u16(dac_t *obj, uint16_t value) {
-    dac_write(value >> 6); // 10-bit
-}
-
-float analogout_read(dac_t *obj) {
-    uint32_t value = dac_read();
-    return (float)value * (1.0f / (float)0x3FF);
-}
-
-uint16_t analogout_read_u16(dac_t *obj) {
-    uint32_t value = dac_read(); // 10-bit
-    return (value << 6) | ((value >> 4) & 0x003F);
-}

--- a/vendor/NXP/LPC1768/hal/can_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,300 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "can_api.h"
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-#include <math.h>
-#include <string.h>
-
-/* Acceptance filter mode in AFMR register */
-#define ACCF_OFF                0x01
-#define ACCF_BYPASS             0x02
-#define ACCF_ON                 0x00
-#define ACCF_FULLCAN            0x04
-
-/* There are several bit timing calculators on the internet.
-http://www.port.de/engl/canprod/sv_req_form.html
-http://www.kvaser.com/can/index.htm
-*/
-
-static const PinMap PinMap_CAN_RD[] = {
-    {P0_0 , CAN_1, 1},
-    {P0_4 , CAN_2, 2},
-    {P0_21, CAN_1, 3},
-    {P2_7 , CAN_2, 1},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_CAN_TD[] = {
-    {P0_1 , CAN_1, 1},
-    {P0_5 , CAN_2, 2},
-    {P0_22, CAN_1, 3},
-    {P2_8 , CAN_2, 1},
-    {NC   , NC   , 0}
-};
-
-// Type definition to hold a CAN message
-struct CANMsg {
-    unsigned int  reserved1 : 16;
-    unsigned int  dlc       :  4; // Bits 16..19: DLC - Data Length Counter
-    unsigned int  reserved0 : 10;
-    unsigned int  rtr       :  1; // Bit 30: Set if this is a RTR message
-    unsigned int  type      :  1; // Bit 31: Set if this is a 29-bit ID message
-    unsigned int  id;             // CAN Message ID (11-bit or 29-bit)
-    unsigned char data[8];        // CAN Message Data Bytes 0-7
-};
-typedef struct CANMsg CANMsg;
-
-static uint32_t can_disable(can_t *obj) {
-    uint32_t sm = obj->dev->MOD;
-    obj->dev->MOD |= 1;
-    return sm;
-}
-
-static inline void can_enable(can_t *obj) {
-    if (obj->dev->MOD & 1) {
-        obj->dev->MOD &= ~(1);
-    }
-}
-
-static int can_pclk(can_t *obj) {
-    int value = 0;
-    switch ((int)obj->dev) {
-        case CAN_1: value = (LPC_SC->PCLKSEL0 & (0x3 << 26)) >> 26; break;
-        case CAN_2: value = (LPC_SC->PCLKSEL0 & (0x3 << 28)) >> 28; break;
-    }
-
-    switch (value) {
-        case 1: return 1;
-        case 2: return 2;
-        case 3: return 6;
-        default: return 4;
-    }
-}
-
-// This table has the sampling points as close to 75% as possible. The first
-// value is TSEG1, the second TSEG2.
-static const int timing_pts[23][2] = {
-    {0x0, 0x0},      // 2,  50%
-    {0x1, 0x0},      // 3,  67%
-    {0x2, 0x0},      // 4,  75%
-    {0x3, 0x0},      // 5,  80%
-    {0x3, 0x1},      // 6,  67%
-    {0x4, 0x1},      // 7,  71%
-    {0x5, 0x1},      // 8,  75%
-    {0x6, 0x1},      // 9,  78%
-    {0x6, 0x2},      // 10, 70%
-    {0x7, 0x2},      // 11, 73%
-    {0x8, 0x2},      // 12, 75%
-    {0x9, 0x2},      // 13, 77%
-    {0x9, 0x3},      // 14, 71%
-    {0xA, 0x3},      // 15, 73%
-    {0xB, 0x3},      // 16, 75%
-    {0xC, 0x3},      // 17, 76%
-    {0xD, 0x3},      // 18, 78%
-    {0xD, 0x4},      // 19, 74%
-    {0xE, 0x4},      // 20, 75%
-    {0xF, 0x4},      // 21, 76%
-    {0xF, 0x5},      // 22, 73%
-    {0xF, 0x6},      // 23, 70%
-    {0xF, 0x7},      // 24, 67%
-};
-
-static unsigned int can_speed(unsigned int sclk, unsigned int pclk, unsigned int cclk, unsigned char psjw) {
-    uint32_t    btr;
-    uint16_t    brp = 0;
-    uint32_t    calcbit;
-    uint32_t    bitwidth;
-    int         hit = 0;
-    int         bits;
-    
-    bitwidth = sclk / (pclk * cclk);
-    
-    brp = bitwidth / 0x18;
-    while ((!hit) && (brp < bitwidth / 4)) {
-        brp++;
-        for (bits = 22; bits > 0; bits--) {
-            calcbit = (bits + 3) * (brp + 1);
-            if (calcbit == bitwidth) {
-                hit = 1;
-                break;
-            }
-        }
-    }
-    
-    if (hit) {
-        btr = ((timing_pts[bits][1] << 20) & 0x00700000)
-            | ((timing_pts[bits][0] << 16) & 0x000F0000)
-            | ((psjw                << 14) & 0x0000C000)
-            | ((brp                 <<  0) & 0x000003FF);
-    } else {
-        btr = 0xFFFFFFFF;
-    }
-    
-    return btr;
-
-}
-
-void can_init(can_t *obj, PinName rd, PinName td) {
-    CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
-    CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
-    obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
-    if ((int)obj->dev == NC) {
-        error("CAN pin mapping failed");
-    }
-
-    switch ((int)obj->dev) {
-        case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
-        case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
-    }
-
-    pinmap_pinout(rd, PinMap_CAN_RD);
-    pinmap_pinout(td, PinMap_CAN_TD);
-
-    can_reset(obj);
-    obj->dev->IER = 0;             // Disable Interrupts
-    can_frequency(obj, 100000);
-
-    LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
-}
-
-void can_free(can_t *obj) {
-    switch ((int)obj->dev) {
-        case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
-        case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
-    }
-}
-
-int can_frequency(can_t *obj, int f) {
-    int pclk = can_pclk(obj);
-    
-    int btr = can_speed(SystemCoreClock, pclk, (unsigned int)f, 1);
-
-    if (btr > 0) {
-        uint32_t modmask = can_disable(obj);
-        obj->dev->BTR = btr;
-        obj->dev->MOD = modmask;
-        return 1;
-    } else {
-        return 0;
-    }
-}
-
-int can_write(can_t *obj, CAN_Message msg, int cc) {
-    unsigned int CANStatus;
-    CANMsg m;
-
-    can_enable(obj);
-
-    m.id   = msg.id ;
-    m.dlc  = msg.len & 0xF;
-    m.rtr  = msg.type;
-    m.type = msg.format;
-    memcpy(m.data, msg.data, msg.len);
-    const unsigned int *buf = (const unsigned int *)&m;
-
-    CANStatus = obj->dev->SR;
-    if (CANStatus & 0x00000004) {
-        obj->dev->TFI1 = buf[0] & 0xC00F0000;
-        obj->dev->TID1 = buf[1];
-        obj->dev->TDA1 = buf[2];
-        obj->dev->TDB1 = buf[3];
-        if(cc) {
-            obj->dev->CMR = 0x30;
-        } else {
-            obj->dev->CMR = 0x21;
-        }
-        return 1;
-
-    } else if (CANStatus & 0x00000400) {
-        obj->dev->TFI2 = buf[0] & 0xC00F0000;
-        obj->dev->TID2 = buf[1];
-        obj->dev->TDA2 = buf[2];
-        obj->dev->TDB2 = buf[3];
-        if (cc) {
-            obj->dev->CMR = 0x50;
-        } else {
-            obj->dev->CMR = 0x41;
-        }
-        return 1;
-
-    } else if (CANStatus & 0x00040000) {
-        obj->dev->TFI3 = buf[0] & 0xC00F0000;
-        obj->dev->TID3 = buf[1];
-        obj->dev->TDA3 = buf[2];
-        obj->dev->TDB3 = buf[3];
-        if (cc) {
-            obj->dev->CMR = 0x90;
-        } else {
-            obj->dev->CMR = 0x81;
-        }
-        return 1;
-    }
-
-    return 0;
-}
-
-int can_read(can_t *obj, CAN_Message *msg) {
-    CANMsg x;
-    unsigned int *i = (unsigned int *)&x;
-
-    can_enable(obj);
-
-    if (obj->dev->GSR & 0x1) {
-        *i++ = obj->dev->RFS;  // Frame
-        *i++ = obj->dev->RID;  // ID
-        *i++ = obj->dev->RDA;  // Data A
-        *i++ = obj->dev->RDB;  // Data B
-        obj->dev->CMR = 0x04;  // release receive buffer
-
-        msg->id     = x.id;
-        msg->len    = x.dlc;
-        msg->format = (x.type)? CANExtended : CANStandard;
-        msg->type   = (x.rtr)?  CANRemote:    CANData;
-        memcpy(msg->data,x.data,x.dlc);
-        return 1;
-    }
-
-    return 0;
-}
-
-void can_reset(can_t *obj) {
-    can_disable(obj);
-    obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
-}
-
-unsigned char can_rderror(can_t *obj) {
-    return (obj->dev->GSR >> 16) & 0xFF;
-}
-
-unsigned char can_tderror(can_t *obj) {
-    return (obj->dev->GSR >> 24) & 0xFF;
-}
-
-void can_monitor(can_t *obj, int silent) {
-    uint32_t mod_mask = can_disable(obj);
-    if (silent) {
-        obj->dev->MOD |= (1 << 1);
-    } else {
-        obj->dev->MOD &= ~(1 << 1);
-    }
-    if (!(mod_mask & 1)) {
-        can_enable(obj);
-    }
-}

--- a/vendor/NXP/LPC1768/hal/device.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,59 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-#define DEVICE_PORTIN           1
-#define DEVICE_PORTOUT          1
-#define DEVICE_PORTINOUT        1
-
-#define DEVICE_INTERRUPTIN      1
-
-#define DEVICE_ANALOGIN         1
-#define DEVICE_ANALOGOUT        1
-
-#define DEVICE_SERIAL           1
-
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
-
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         1
-
-#define DEVICE_CAN              1
-
-#define DEVICE_RTC              1
-
-#define DEVICE_ETHERNET         1
-
-#define DEVICE_PWMOUT           1
-
-#define DEVICE_SEMIHOST         1
-#define DEVICE_LOCALFILESYSTEM  1
-#define DEVICE_ID_LENGTH       32
-#define DEVICE_MAC_OFFSET      20
-
-#define DEVICE_SLEEP            1
-
-#define DEVICE_DEBUG_AWARENESS  1
-
-#define DEVICE_STDIO_MESSAGES   1
-
-#define DEVICE_ERROR_PATTERN    1
-
-#include "objects.h"
-
-#endif

--- a/vendor/NXP/LPC1768/hal/ethernet_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,948 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "ethernet_api.h"
-
-#include <string.h>
-#include "cmsis.h"
-#include "mbed_interface.h"
-#include "toolchain.h"
-#include "error.h"
-
-#define NEW_LOGIC       0
-#define NEW_ETH_BUFFER  0
-
-#if NEW_ETH_BUFFER
-
-#define NUM_RX_FRAG         4           // Number of Rx Fragments (== packets)
-#define NUM_TX_FRAG         3           // Number of Tx Fragments (== packets)
-
-#define ETH_MAX_FLEN        1536         // Maximum Ethernet Frame Size
-#define ETH_FRAG_SIZE       ETH_MAX_FLEN // Packet Fragment size (same as packet length)
-
-#else
-
-// Memfree calculation:
-// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
-//                (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
-/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
-#define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */
-#define NUM_TX_FRAG         3           /* Num.of TX Fragments 3*1536= 4.6kB */
-//#define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
-
-//#define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
-#define ETH_FRAG_SIZE       0x300       /* Packet Fragment size 1536/2 Bytes   */
-#define ETH_MAX_FLEN        0x300       /* Max. Ethernet Frame Size          */
-
-const int ethernet_MTU_SIZE  = 0x300;
-
-#endif
-
-#define ETHERNET_ADDR_SIZE 6
-
-PACKED struct RX_DESC_TypeDef {                        /* RX Descriptor struct              */
-   unsigned int Packet;
-   unsigned int Ctrl;
-};
-typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
-
-PACKED struct RX_STAT_TypeDef {                        /* RX Status struct                  */
-   unsigned int Info;
-   unsigned int HashCRC;
-};
-typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
-
-PACKED struct TX_DESC_TypeDef {                        /* TX Descriptor struct              */
-   unsigned int Packet;
-   unsigned int Ctrl;
-};
-typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
-
-PACKED struct TX_STAT_TypeDef {                        /* TX Status struct                  */
-   unsigned int Info;
-};
-typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
-
-/* MAC Configuration Register 1 */
-#define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
-#define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
-#define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
-#define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
-#define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
-#define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
-#define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
-#define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
-#define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
-#define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
-#define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
-
-/* MAC Configuration Register 2 */
-#define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
-#define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
-#define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
-#define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
-#define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
-#define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
-#define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
-#define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
-#define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
-#define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
-#define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
-#define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
-#define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
-
-/* Back-to-Back Inter-Packet-Gap Register */
-#define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
-#define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
-
-/* Non Back-to-Back Inter-Packet-Gap Register */
-#define IPGR_DEF            0x00000012  /* Recommended value                 */
-
-/* Collision Window/Retry Register */
-#define CLRT_DEF            0x0000370F  /* Default value                     */
-
-/* PHY Support Register */
-#define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
-//#define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */
-#define SUPP_RES_RMII       0x00000000  /* Reset Reduced MII Logic           */
-
-/* Test Register */
-#define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
-#define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
-#define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
-
-/* MII Management Configuration Register */
-#define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
-#define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
-#define MCFG_CLK_SEL        0x0000003C  /* Clock Select Mask                 */
-#define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
-
-/* MII Management Command Register */
-#define MCMD_READ           0x00000001  /* MII Read                          */
-#define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
-
-#define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
-#define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
-
-/* MII Management Address Register */
-#define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
-#define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
-
-/* MII Management Indicators Register */
-#define MIND_BUSY           0x00000001  /* MII is Busy                       */
-#define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
-#define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
-#define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
-
-/* Command Register */
-#define CR_RX_EN            0x00000001  /* Enable Receive                    */
-#define CR_TX_EN            0x00000002  /* Enable Transmit                   */
-#define CR_REG_RES          0x00000008  /* Reset Host Registers              */
-#define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
-#define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
-#define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
-#define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
-#define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
-#define CR_RMII             0x00000200  /* Reduced MII Interface             */
-#define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
-
-/* Status Register */
-#define SR_RX_EN            0x00000001  /* Enable Receive                    */
-#define SR_TX_EN            0x00000002  /* Enable Transmit                   */
-
-/* Transmit Status Vector 0 Register */
-#define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
-#define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
-#define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
-#define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
-#define TSV0_MCAST          0x00000010  /* Multicast Destination             */
-#define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
-#define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
-#define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
-#define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
-#define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
-#define TSV0_GIANT          0x00000400  /* Giant Frame                       */
-#define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
-#define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
-#define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
-#define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
-#define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
-#define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
-
-/* Transmit Status Vector 1 Register */
-#define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
-#define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
-
-/* Receive Status Vector Register */
-#define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
-#define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
-#define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
-#define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
-#define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
-#define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
-#define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
-#define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
-#define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
-#define RSV_MCAST           0x01000000  /* Multicast Frame                   */
-#define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
-#define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
-#define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
-#define RSV_PAUSE           0x10000000  /* Pause Frame                       */
-#define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
-#define RSV_VLAN            0x40000000  /* VLAN Frame                        */
-
-/* Flow Control Counter Register */
-#define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
-#define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
-
-/* Flow Control Status Register */
-#define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
-
-/* Receive Filter Control Register */
-#define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
-#define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
-#define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
-#define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
-#define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
-#define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
-#define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
-#define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
-
-/* Receive Filter WoL Status/Clear Registers */
-#define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
-#define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
-#define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
-#define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
-#define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
-#define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
-#define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
-#define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
-
-/* Interrupt Status/Enable/Clear/Set Registers */
-#define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
-#define INT_RX_ERR          0x00000002  /* Receive Error                     */
-#define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
-#define INT_RX_DONE         0x00000008  /* Receive Done                      */
-#define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
-#define INT_TX_ERR          0x00000020  /* Transmit Error                    */
-#define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
-#define INT_TX_DONE         0x00000080  /* Transmit Done                     */
-#define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
-#define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
-
-/* Power Down Register */
-#define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
-
-/* RX Descriptor Control Word */
-#define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
-#define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
-
-/* RX Status Hash CRC Word */
-#define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
-#define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
-
-/* RX Status Information Word */
-#define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
-#define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
-#define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
-#define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
-#define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
-#define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
-#define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
-#define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
-#define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
-#define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
-#define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
-#define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
-#define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
-#define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
-#define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
-
-//#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
-#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
-                            RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
-
-
-/* TX Descriptor Control Word */
-#define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
-#define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
-#define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
-#define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
-#define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
-#define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
-#define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
-
-/* TX Status Information Word */
-#define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
-#define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
-#define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
-#define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
-#define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
-#define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
-#define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
-#define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
-
-/* ENET Device Revision ID */
-#define OLD_EMAC_MODULE_ID  0x39022000  /* Rev. ID for first rev '-'         */
-
-/* DP83848C PHY Registers */
-#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
-#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
-#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
-#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
-#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
-#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
-#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
-#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
-
-/* PHY Extended Registers */
-#define PHY_REG_STS         0x10        /* Status Register                   */
-#define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */
-#define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */
-#define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */
-#define PHY_REG_RECR        0x15        /* Receive Error Counter             */
-#define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */
-#define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */
-#define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */
-#define PHY_REG_PHYCR       0x19        /* PHY Control Register              */
-#define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */
-#define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */
-#define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */
-
-#define PHY_REG_SCSR        0x1F        /* PHY Special Control/Status Register */
-
-#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
-#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
-#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
-#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
-#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */
-
-#define DP83848C_DEF_ADR    0x0100      /* Default PHY device address        */
-#define DP83848C_ID         0x20005C90  /* PHY Identifier - DP83848C         */
-
-#define LAN8720_ID          0x0007C0F0  /* PHY Identifier - LAN8720          */
-
-#define PHY_STS_LINK        0x0001      /* PHY Status Link Mask              */
-#define PHY_STS_SPEED       0x0002      /* PHY Status Speed Mask             */
-#define PHY_STS_DUPLEX      0x0004      /* PHY Status Duplex Mask            */
-
-#define PHY_BMCR_RESET      0x8000      /* PHY Reset                         */
-
-#define PHY_BMSR_LINK       0x0004      /* PHY BMSR Link valid               */
-
-#define PHY_SCSR_100MBIT    0x0008      /* Speed: 1=100 MBit, 0=10Mbit       */
-#define PHY_SCSR_DUPLEX     0x0010      /* PHY Duplex Mask                   */
-
-
-static int phy_read(unsigned int PhyReg);
-static int phy_write(unsigned int PhyReg, unsigned short Data);
-
-static void txdscr_init(void);
-static void rxdscr_init(void);
-
-#if defined (__ICCARM__)
-#   define AHBSRAM1
-#elif defined(TOOLCHAIN_GCC_CR)
-#   define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
-#else
-#   define AHBSRAM1     __attribute__((section("AHBSRAM1"),aligned))
-#endif
-
-AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
-AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
-AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
-AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
-AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
-AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
-
-
-#if NEW_LOGIC
-static int rx_consume_offset = -1;
-static int tx_produce_offset = -1;
-#else
-static int send_doff =  0;
-static int send_idx  = -1;
-static int send_size =  0;
-
-static int receive_soff =  0;
-static int receive_idx  = -1;
-#endif
-
-static uint32_t phy_id = 0;
-
-static inline int rinc(int idx, int mod) {
-  ++idx;
-  idx %= mod;
-  return idx;
-}
-
-//extern unsigned int SystemFrequency;
-static inline unsigned int clockselect() {
-  if(SystemCoreClock < 10000000) {
-    return 1;
-  } else if(SystemCoreClock <  15000000) {
-    return 2;
-  } else if(SystemCoreClock <  20000000) {
-    return 3;
-  } else if(SystemCoreClock <  25000000) {
-    return 4;
-  } else if(SystemCoreClock <  35000000) {
-    return 5;
-  } else if(SystemCoreClock <  50000000) {
-    return 6;
-  } else if(SystemCoreClock <  70000000) {
-    return 7;
-  } else if(SystemCoreClock <  80000000) {
-    return 8;
-  } else if(SystemCoreClock <  90000000) {
-    return 9;
-  } else if(SystemCoreClock < 100000000) {
-    return 10;
-  } else if(SystemCoreClock < 120000000) {
-    return 11;
-  } else if(SystemCoreClock < 130000000) {
-    return 12;
-  } else if(SystemCoreClock < 140000000) {
-    return 13;
-  } else if(SystemCoreClock < 150000000) {
-    return 15;
-  } else if(SystemCoreClock < 160000000) {
-    return 16;
-  } else {
-    return 0;
-  }
-}
-
-#ifndef min
-#define min(x, y) (((x)<(y))?(x):(y))
-#endif
-
-/*----------------------------------------------------------------------------
-  Ethernet Device initialize
- *----------------------------------------------------------------------------*/
-int ethernet_init() {
-  int regv, tout;
-  char mac[ETHERNET_ADDR_SIZE];
-  unsigned int clock = clockselect();
-  
-  LPC_SC->PCONP |= 0x40000000;                       /* Power Up the EMAC controller. */
-  
-  LPC_PINCON->PINSEL2 = 0x50150105;                  /* Enable P1 Ethernet Pins. */
-  LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
-
-   /* Reset all EMAC internal modules. */
-  LPC_EMAC->MAC1    = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
-                      MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
-  LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
-
-  for(tout = 100; tout; tout--) __NOP();             /* A short delay after reset. */
-
-  LPC_EMAC->MAC1 = MAC1_PASS_ALL;                    /* Initialize MAC control registers. */
-  LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
-  LPC_EMAC->MAXF = ETH_MAX_FLEN;
-  LPC_EMAC->CLRT = CLRT_DEF;
-  LPC_EMAC->IPGR = IPGR_DEF;
-
-  LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;    /* Enable Reduced MII interface. */
-
-  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;    /* Set clock */
-  LPC_EMAC->MCFG |= MCFG_RES_MII;                    /* and reset */
-
-  for(tout = 100; tout; tout--) __NOP();             /* A short delay */
-
-  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
-  LPC_EMAC->MCMD = 0;
-
-  LPC_EMAC->SUPP = SUPP_RES_RMII;                    /* Reset Reduced MII Logic. */
-
-  for (tout = 100; tout; tout--) __NOP();            /* A short delay */
-
-  LPC_EMAC->SUPP = 0;
-
-  phy_write(PHY_REG_BMCR, PHY_BMCR_RESET);           /* perform PHY reset */
-  for(tout = 0x20000; ; tout--) {                    /* Wait for hardware reset to end. */
-    regv = phy_read(PHY_REG_BMCR);
-    if(regv < 0 || tout == 0) {
-       return -1;                                    /* Error */
-    }
-    if(!(regv & PHY_BMCR_RESET)) {
-       break;                                        /* Reset complete. */
-    }
-  }
-
-  phy_id =  (phy_read(PHY_REG_IDR1) << 16);
-  phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
-
-  if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
-      error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
-  }
-
-  ethernet_set_link(-1, 0);
-
-  /* Set the Ethernet MAC Address registers */
-  ethernet_address(mac);
-  LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
-  LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
-  LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
-
-  txdscr_init();                                      /* initialize DMA TX Descriptor */
-  rxdscr_init();                                      /* initialize DMA RX Descriptor */
-
-  LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
-                                                      /* Receive Broadcast, Perfect Match Packets */
-
-  LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;    /* Enable EMAC interrupts. */
-  LPC_EMAC->IntClear  = 0xFFFF;                       /* Reset all interrupts */
-
-
-  LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);        /* Enable receive and transmit mode of MAC Ethernet core */
-  LPC_EMAC->MAC1     |= MAC1_REC_EN;
-
-#if NEW_LOGIC
-  rx_consume_offset = -1;
-  tx_produce_offset = -1;
-#else
-  send_doff =  0;
-  send_idx  = -1;
-  send_size =  0;
-
-  receive_soff =  0;
-  receive_idx  = -1;
-#endif
-
-  return 0;
-}
-
-/*----------------------------------------------------------------------------
-  Ethernet Device Uninitialize
- *----------------------------------------------------------------------------*/
-void ethernet_free() {
-    LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
-    LPC_EMAC->IntClear   =  0xFFFF;
-    
-    LPC_SC->PCONP   &= ~0x40000000;       /* Power down the EMAC controller. */
-    
-    LPC_PINCON->PINSEL2 &= ~0x50150105;   /* Disable P1 ethernet pins. */
-    LPC_PINCON->PINSEL3  = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000000;
-}
-
-// if(TxProduceIndex == TxConsumeIndex) buffer array is empty
-// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
-// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
-// TxConsumeIndex - The buffer that will/is beign sent by hardware
-
-int ethernet_write(const char *data, int slen) {
-
-#if NEW_LOGIC
-
-   if(tx_produce_offset < 0) { // mark as active if not already
-     tx_produce_offset = 0;
-   }
-
-   int index = LPC_EMAC->TxProduceIndex;
-
-   int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
-   int requested = slen;
-   int ncopy = min(remaining, requested);
-
-   void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
-   void *psrc = (void *)(data);
-
-   if(ncopy > 0 ){
-     if(data != NULL) {
-       memcpy(pdst, psrc, ncopy);
-     } else {
-       memset(pdst, 0, ncopy);
-     }
-   }
-
-   tx_produce_offset += ncopy;
-
-   return ncopy;
-
-#else
-    void       *pdst, *psrc;
-    const int   dlen = ETH_FRAG_SIZE;
-    int         copy = 0;
-    int         soff = 0;
-
-    if(send_idx == -1) {
-        send_idx = LPC_EMAC->TxProduceIndex;
-    }
-
-    if(slen + send_doff > ethernet_MTU_SIZE) {
-       return -1;
-    }
-
-    do {
-        copy = min(slen - soff, dlen - send_doff);
-        pdst = (void *)(txdesc[send_idx].Packet + send_doff);
-        psrc = (void *)(data + soff);
-        if(send_doff + copy > ETH_FRAG_SIZE) {
-            txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
-            send_idx = rinc(send_idx, NUM_TX_FRAG);
-            send_doff = 0;
-        }
-
-        if(data != NULL) {
-            memcpy(pdst, psrc, copy);
-        } else {
-            memset(pdst, 0, copy);
-        }
-
-        soff += copy;
-        send_doff += copy;
-        send_size += copy;
-    } while(soff != slen);
-
-    return soff;
-#endif
-}
-
-int ethernet_send() {
-
-#if NEW_LOGIC
-  if(tx_produce_offset < 0) { // no buffer active
-    return -1;
-  }
-
-  // ensure there is a link
-  if(!ethernet_link()) {
-    return -2;
-  }
-
-  // we have been writing in to a buffer, so finalise it
-  int size = tx_produce_offset;
-  int index = LPC_EMAC->TxProduceIndex;
-  txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
-
-  // Increment ProduceIndex to allow it to be sent
-  // We can only do this if the next slot is free
-  int next = rinc(index, NUM_TX_FRAG);
-  while(next == LPC_EMAC->TxConsumeIndex) {
-    for(int i=0; i<1000; i++) { __NOP(); }
-  }
-
-  LPC_EMAC->TxProduceIndex = next;
-  tx_produce_offset = -1;
-  return size;
-
-#else
-    int s = send_size;
-    txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
-    send_idx  = rinc(send_idx, NUM_TX_FRAG);
-    LPC_EMAC->TxProduceIndex = send_idx;
-    send_doff =  0;
-    send_idx  = -1;
-    send_size =  0;
-    return s;
-#endif
-}
-
-// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
-// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
-//
-// if(RxConsumeIndex == RxProduceIndex) buffer array is empty
-// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
-
-// Recevies an arrived ethernet packet.
-// Receiving an ethernet packet will drop the last received ethernet packet
-// and make a new ethernet packet ready to read.
-// Returns size of packet, else 0 if nothing to receive
-
-// We read from RxConsumeIndex from position rx_consume_offset
-// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
-// rx_consume_offset = -1 // no frame
-// rx_consume_offset = 0  // start of frame
-// Assumption: A fragment should alway be a whole frame
-
-int ethernet_receive() {
-#if NEW_LOGIC
-
-  // if we are currently reading a valid RxConsume buffer, increment to the next one
-  if(rx_consume_offset >= 0) {
-    LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
-  }
-
-  // if the buffer is empty, mark it as no valid buffer
-  if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
-    rx_consume_offset = -1;
-    return 0;
-  }
-
-  uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
-  rx_consume_offset = 0;
-
-  // check if it is not marked as last or for errors
-  if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
-    return -1;
-  }
-
-  int size = (info & RINFO_SIZE) + 1;
-  return size - 4; // don't include checksum bytes
-
-#else
-    if(receive_idx == -1) {
-      receive_idx = LPC_EMAC->RxConsumeIndex;
-    } else {
-        while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && (receive_idx != LPC_EMAC->RxProduceIndex)) {
-            receive_idx  = rinc(receive_idx, NUM_RX_FRAG);
-        }
-        unsigned int info =   rxstat[receive_idx].Info;
-        int slen =  (info & RINFO_SIZE) + 1;
-
-        if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
-            /* Invalid frame, ignore it and free buffer. */
-            receive_idx = rinc(receive_idx, NUM_RX_FRAG);
-        }
-        receive_idx = rinc(receive_idx, NUM_RX_FRAG);
-        receive_soff = 0;
-
-        LPC_EMAC->RxConsumeIndex = receive_idx;
-    }
-
-    if(receive_idx == LPC_EMAC->RxProduceIndex) {
-        receive_idx = -1;
-        return 0;
-    }
-
-    return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
-#endif
-}
-
-// Read from an recevied ethernet packet.
-// After receive returnd a number bigger than 0 it is
-// possible to read bytes from this packet.
-// Read will write up to size bytes into data.
-// It is possible to use read multible times.
-// Each time read will start reading after the last read byte before.
-
-int ethernet_read(char *data, int dlen) {
-#if NEW_LOGIC
-  // Check we have a valid buffer to read
-  if(rx_consume_offset < 0) {
-    return 0;
-  }
-
-  // Assume 1 fragment block
-  uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
-  int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
-
-  int remaining = size - rx_consume_offset;
-  int requested = dlen;
-  int ncopy = min(remaining, requested);
-
-  void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
-  void *pdst = (void *)(data);
-
-  if(data != NULL && ncopy > 0) {
-    memcpy(pdst, psrc, ncopy);
-  }
-
-  rx_consume_offset += ncopy;
-
-  return ncopy;
-#else
-    int          slen;
-    int          copy   = 0;
-    unsigned int more;
-    unsigned int info;
-    void        *pdst, *psrc;
-    int          doff = 0;
-
-    if(receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
-        return 0;
-    }
-
-    do {
-        info =   rxstat[receive_idx].Info;
-        more = !(info & RINFO_LAST_FLAG);
-        slen =  (info & RINFO_SIZE) + 1;
-
-        if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
-            /* Invalid frame, ignore it and free buffer. */
-            receive_idx = rinc(receive_idx, NUM_RX_FRAG);
-        } else {
-
-            copy = min(slen - receive_soff, dlen - doff);
-            psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
-            pdst = (void *)(data + doff);
-
-            if(data != NULL) {
-                /* check if Buffer available */
-                memcpy(pdst, psrc, copy);
-            }
-
-            receive_soff += copy;
-            doff += copy;
-
-            if((more && (receive_soff == slen))) {
-                receive_idx = rinc(receive_idx, NUM_RX_FRAG);
-                receive_soff = 0;
-            }
-        }
-    } while(more && !(doff == dlen) && !receive_soff);
-
-    return doff;
-#endif
-}
-
-int ethernet_link(void) {
-
-    if (phy_id == DP83848C_ID) {
-      return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
-    }
-    else { // LAN8720_ID
-      return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
-    }
-}
-
-static int phy_write(unsigned int PhyReg, unsigned short Data) {
-    unsigned int timeOut;
-
-    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-    LPC_EMAC->MWTD = Data;
-
-    for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) {     /* Wait until operation completed */
-        if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
-            return 0;
-        }
-    }
-
-    return -1;
-}
-
-
-static int phy_read(unsigned int PhyReg) {
-    unsigned int timeOut;
-
-    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-    LPC_EMAC->MCMD = MCMD_READ;
-
-    for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) {     /* Wait until operation completed */
-        if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
-            LPC_EMAC->MCMD = 0;
-            return LPC_EMAC->MRDD;                           /* Return a 16-bit value. */
-        }
-    }
-
-    return -1;
-}
-
-
-static void txdscr_init() {
-    int i;
-
-    for(i = 0; i < NUM_TX_FRAG; i++) {
-        txdesc[i].Packet = (uint32_t)&txbuf[i];
-        txdesc[i].Ctrl   = 0;
-        txstat[i].Info   = 0;
-    }
-
-    LPC_EMAC->TxDescriptor       = (uint32_t)txdesc;         /* Set EMAC Transmit Descriptor Registers. */
-    LPC_EMAC->TxStatus           = (uint32_t)txstat;
-    LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
-
-    LPC_EMAC->TxProduceIndex  = 0;                           /* Tx Descriptors Point to 0 */
-}
-
-
-static void rxdscr_init() {
-    int i;
-
-    for(i = 0; i < NUM_RX_FRAG; i++) {
-        rxdesc[i].Packet  = (uint32_t)&rxbuf[i];
-        rxdesc[i].Ctrl    = RCTRL_INT | (ETH_FRAG_SIZE-1);
-        rxstat[i].Info    = 0;
-        rxstat[i].HashCRC = 0;
-    }
-
-    LPC_EMAC->RxDescriptor       = (uint32_t)rxdesc;        /* Set EMAC Receive Descriptor Registers. */
-    LPC_EMAC->RxStatus           = (uint32_t)rxstat;
-    LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
-
-    LPC_EMAC->RxConsumeIndex  = 0;                          /* Rx Descriptors Point to 0 */
-}
-
-void ethernet_address(char *mac) {
-    mbed_mac_address(mac);
-}
-
-void ethernet_set_link(int speed, int duplex) {
-    unsigned short phy_data;
-    int tout;
-
-    if((speed < 0) || (speed > 1)) {
-
-        phy_data = PHY_AUTO_NEG;
-
-    } else {
-
-        phy_data = (((unsigned short) speed << 13) |
-                    ((unsigned short) duplex << 8));
-    }
-
-    phy_write(PHY_REG_BMCR, phy_data);
-
-    for(tout = 100; tout; tout--) { __NOP(); }     /* A short delay */
-
-    switch(phy_id) {
-    case DP83848C_ID:
-
-        phy_data = phy_read(PHY_REG_STS);
-
-        if(phy_data & PHY_STS_DUPLEX) {
-            LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
-            LPC_EMAC->Command |= CR_FULL_DUP;
-            LPC_EMAC->IPGT = IPGT_FULL_DUP;
-        } else {
-        LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
-            LPC_EMAC->Command &= ~CR_FULL_DUP;
-            LPC_EMAC->IPGT = IPGT_HALF_DUP;
-        }
-
-        if(phy_data & PHY_STS_SPEED) {
-            LPC_EMAC->SUPP &= ~SUPP_SPEED;
-        } else {
-            LPC_EMAC->SUPP |= SUPP_SPEED;
-        }
-
-
-        break;
-    case LAN8720_ID:
-
-        phy_data = phy_read(PHY_REG_SCSR);
-
-        if (phy_data & PHY_SCSR_DUPLEX) {
-            LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
-            LPC_EMAC->Command |= CR_FULL_DUP;
-            LPC_EMAC->IPGT = IPGT_FULL_DUP;
-        } else {
-            LPC_EMAC->Command &= ~CR_FULL_DUP;
-            LPC_EMAC->IPGT = IPGT_HALF_DUP;
-        }
-
-        if(phy_data & PHY_SCSR_100MBIT) {
-            LPC_EMAC->SUPP |= SUPP_SPEED;
-        } else {
-            LPC_EMAC->SUPP &= ~SUPP_SPEED;
-        }
-
-
-        break;
-    }
-
-
-}

--- a/vendor/NXP/LPC1768/hal/gpio_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,52 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "gpio_api.h"
-#include "pinmap.h"
-
-uint32_t gpio_set(PinName pin) {
-    pin_function(pin, 0);
-    return (1 << ((int)pin & 0x1F));
-}
-
-void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
-    if(pin == NC) return;
-    
-    obj->pin = pin;
-    obj->mask = gpio_set(pin);
-    
-    LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *) ((int)pin & ~0x1F);
-    obj->reg_set = &port_reg->FIOSET;
-    obj->reg_clr = &port_reg->FIOCLR;
-    obj->reg_in  = &port_reg->FIOPIN;
-    obj->reg_dir = &port_reg->FIODIR;
-    
-    gpio_dir(obj, direction);
-    switch (direction) {
-        case PIN_OUTPUT: pin_mode(pin, PullNone); break;
-        case PIN_INPUT : pin_mode(pin, PullDown); break;
-    }
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode) {
-    pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction) {
-    switch (direction) {
-        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
-        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
-    }
-}

--- a/vendor/NXP/LPC1768/hal/gpio_irq_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,144 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stddef.h>
-
-#include "gpio_irq_api.h"
-#include "error.h"
-#include "cmsis.h"
-
-#define CHANNEL_NUM     48
-
-static uint32_t channel_ids[CHANNEL_NUM] = {0};
-static gpio_irq_handler irq_handler;
-
-static void handle_interrupt_in(void) {
-    // Read in all current interrupt registers. We do this once as the
-    // GPIO interrupt registers are on the APB bus, and this is slow.
-    uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
-    uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
-    uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
-    uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
-    uint32_t mask0 = 0;
-    uint32_t mask2 = 0;
-    int i;
-
-    // P0.0-0.31
-    for (i = 0; i < 32; i++) {
-        uint32_t pmask = (1 << i);
-        if (rise0 & pmask) {
-            mask0 |= pmask;
-            if (channel_ids[i] != 0)
-                irq_handler(channel_ids[i], IRQ_RISE);
-        }
-        if (fall0 & pmask) {
-            mask0 |= pmask;
-            if (channel_ids[i] != 0)
-                irq_handler(channel_ids[i], IRQ_FALL);
-        }
-    }
-    
-    // P2.0-2.15
-    for (i = 0; i < 16; i++) {
-        uint32_t pmask = (1 << i);
-        int channel_index = i + 32;
-        if (rise2 & pmask) {
-            mask2 |= pmask;
-            if (channel_ids[channel_index] != 0)
-                irq_handler(channel_ids[channel_index], IRQ_RISE);
-        }
-        if (fall2 & pmask) {
-            mask2 |= pmask;
-            if (channel_ids[channel_index] != 0)
-                irq_handler(channel_ids[channel_index], IRQ_FALL);
-        }
-    }
-
-    // Clear the interrupts we just handled
-    LPC_GPIOINT->IO0IntClr = mask0;
-    LPC_GPIOINT->IO2IntClr = mask2;
-}
-
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
-    if (pin == NC) return -1;
-    
-    irq_handler = handler;
-    
-    obj->port = (int)pin & ~0x1F;
-    obj->pin = (int)pin & 0x1F;
-    
-    // Interrupts available only on GPIO0 and GPIO2
-    if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
-        error("pins on this port cannot generate interrupts\n");
-    }
-    
-    // put us in the interrupt table
-    int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
-    channel_ids[index] = id;
-    obj->ch = index;
-    
-    NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
-    NVIC_EnableIRQ(EINT3_IRQn);
-    return 0;
-}
-
-void gpio_irq_free(gpio_irq_t *obj) {
-    channel_ids[obj->ch] = 0;
-}
-
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
-    // ensure nothing is pending
-    switch (obj->port) {
-         case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
-         case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
-    }
-
-    // enable the pin interrupt
-    if (event == IRQ_RISE) {
-        switch (obj->port) {
-            case LPC_GPIO0_BASE:
-                if (enable) {
-                    LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
-                } else {
-                    LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
-                }
-                break;
-            case LPC_GPIO2_BASE:
-                if (enable) {
-                    LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
-                } else {
-                    LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
-                }
-                break;
-        }
-    } else {
-        switch (obj->port) {
-            case LPC_GPIO0_BASE:
-                if (enable) {
-                    LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
-                } else {
-                    LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
-                }
-                break;
-            case LPC_GPIO2_BASE:
-                if (enable) {
-                    LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
-                } else {
-                    LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
-                }
-                break;
-        }
-    }
-}

--- a/vendor/NXP/LPC1768/hal/gpio_object.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    PinName  pin;
-    uint32_t mask;
-
-    __IO uint32_t *reg_dir;
-    __IO uint32_t *reg_set;
-    __IO uint32_t *reg_clr;
-    __I  uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
-    if (value)
-        *obj->reg_set = obj->mask;
-    else
-        *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
-    return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC1768/hal/i2c_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,390 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "i2c_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_I2C_SDA[] = {
-    {P0_0 , I2C_1, 3},
-    {P0_10, I2C_2, 2},
-    {P0_19, I2C_1, 3},
-    {P0_27, I2C_0, 1},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_I2C_SCL[] = {
-    {P0_1 , I2C_1, 3},
-    {P0_11, I2C_2, 2},
-    {P0_20, I2C_1, 3},
-    {P0_28, I2C_0, 1},
-    {NC   , NC,    0}
-};
-
-#define I2C_CONSET(x)       (x->i2c->I2CONSET)
-#define I2C_CONCLR(x)       (x->i2c->I2CONCLR)
-#define I2C_STAT(x)         (x->i2c->I2STAT)
-#define I2C_DAT(x)          (x->i2c->I2DAT)
-#define I2C_SCLL(x, val)    (x->i2c->I2SCLL = val)
-#define I2C_SCLH(x, val)    (x->i2c->I2SCLH = val)
-
-static const uint32_t I2C_addr_offset[2][4] = {
-    {0x0C, 0x20, 0x24, 0x28},
-    {0x30, 0x34, 0x38, 0x3C}
-};
-
-static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
-    I2C_CONCLR(obj) = (start << 5)
-                    | (stop << 4)
-                    | (interrupt << 3)
-                    | (acknowledge << 2);
-}
-
-static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
-    I2C_CONSET(obj) = (start << 5)
-                    | (stop << 4)
-                    | (interrupt << 3)
-                    | (acknowledge << 2);
-}
-
-// Clear the Serial Interrupt (SI)
-static inline void i2c_clear_SI(i2c_t *obj) {
-    i2c_conclr(obj, 0, 0, 1, 0);
-}
-
-static inline int i2c_status(i2c_t *obj) {
-    return I2C_STAT(obj);
-}
-
-// Wait until the Serial Interrupt (SI) is set
-static int i2c_wait_SI(i2c_t *obj) {
-    int timeout = 0;
-    while (!(I2C_CONSET(obj) & (1 << 3))) {
-        timeout++;
-        if (timeout > 100000) return -1;
-    }
-    return 0;
-}
-
-static inline void i2c_interface_enable(i2c_t *obj) {
-    I2C_CONSET(obj) = 0x40;
-}
-
-static inline void i2c_power_enable(i2c_t *obj) {
-    switch ((int)obj->i2c) {
-        case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
-        case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
-        case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
-    }
-}
-
-void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
-    // determine the SPI to use
-    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
-    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
-    obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
-    
-    if ((int)obj->i2c == NC) {
-        error("I2C pin mapping failed");
-    }
-    
-    // enable power
-    i2c_power_enable(obj);
-    
-    // set default frequency at 100k
-    i2c_frequency(obj, 100000);
-    i2c_conclr(obj, 1, 1, 1, 1);
-    i2c_interface_enable(obj);
-    
-    pinmap_pinout(sda, PinMap_I2C_SDA);
-    pinmap_pinout(scl, PinMap_I2C_SCL);
-}
-
-inline int i2c_start(i2c_t *obj) {
-    int status = 0;
-    // 8.1 Before master mode can be entered, I2CON must be initialised to:
-    //  - I2EN STA STO SI AA - -
-    //  -  1    0   0   0  x - -
-    // if AA = 0, it can't enter slave mode
-    i2c_conclr(obj, 1, 1, 1, 1);
-    
-    // The master mode may now be entered by setting the STA bit
-    // this will generate a start condition when the bus becomes free
-    i2c_conset(obj, 1, 0, 0, 1);
-    
-    i2c_wait_SI(obj);
-    status = i2c_status(obj);
-    
-    // Clear start bit now transmitted, and interrupt bit
-    i2c_conclr(obj, 1, 0, 0, 0);
-    return status;
-}
-
-inline void i2c_stop(i2c_t *obj) {
-    // write the stop bit
-    i2c_conset(obj, 0, 1, 0, 0);
-    i2c_clear_SI(obj);
-    
-    // wait for STO bit to reset
-    while(I2C_CONSET(obj) & (1 << 4));
-}
-
-static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
-    // write the data
-    I2C_DAT(obj) = value;
-    
-    // clear SI to init a send
-    i2c_clear_SI(obj);
-    
-    // wait and return status
-    i2c_wait_SI(obj);
-    return i2c_status(obj);
-}
-
-static inline int i2c_do_read(i2c_t *obj, int last) {
-    // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
-    if(last) {
-        i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
-    } else {
-        i2c_conset(obj, 0, 0, 0, 1); // send a ACK
-    }
-    
-    // accept byte
-    i2c_clear_SI(obj);
-    
-    // wait for it to arrive
-    i2c_wait_SI(obj);
-    
-    // return the data
-    return (I2C_DAT(obj) & 0xFF);
-}
-
-void i2c_frequency(i2c_t *obj, int hz) {
-    // [TODO] set pclk to /4
-    uint32_t PCLK = SystemCoreClock / 4;
-    
-    uint32_t pulse = PCLK / (hz * 2);
-    
-    // I2C Rate
-    I2C_SCLL(obj, pulse);
-    I2C_SCLH(obj, pulse);
-}
-
-// The I2C does a read or a write as a whole operation
-// There are two types of error conditions it can encounter
-//  1) it can not obtain the bus
-//  2) it gets error responses at part of the transmission
-//
-// We tackle them as follows:
-//  1) we retry until we get the bus. we could have a "timeout" if we can not get it
-//      which basically turns it in to a 2)
-//  2) on error, we use the standard error mechanisms to report/debug
-//
-// Therefore an I2C transaction should always complete. If it doesn't it is usually
-// because something is setup wrong (e.g. wiring), and we don't need to programatically
-// check for that
-
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
-    int count, status;
-    
-    status = i2c_start(obj);
-    
-    if ((status != 0x10) && (status != 0x08)) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    status = i2c_do_write(obj, (address | 0x01), 1);
-    if (status != 0x40) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    // Read in all except last byte
-    for (count = 0; count < (length - 1); count++) {
-        int value = i2c_do_read(obj, 0);
-        status = i2c_status(obj);
-        if (status != 0x50) {
-            i2c_stop(obj);
-            return status;
-        }
-        data[count] = (char) value;
-    }
-    
-    // read in last byte
-    int value = i2c_do_read(obj, 1);
-    status = i2c_status(obj);
-    if (status != 0x58) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    data[count] = (char) value;
-    
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-    }
-    
-    return 0;
-}
-
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
-    int i, status;
-    
-    status = i2c_start(obj);
-    
-    if ((status != 0x10) && (status != 0x08)) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    status = i2c_do_write(obj, (address & 0xFE), 1);
-    if (status != 0x18) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    for (i=0; i<length; i++) {
-        status = i2c_do_write(obj, data[i], 0);
-        if(status != 0x28) {
-            i2c_stop(obj);
-            return status;
-        }
-    }
-    
-    // clearing the serial interrupt here might cause an unintended rewrite of the last byte
-    // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
-    // i2c_clear_SI(obj);
-    
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-    }
-    
-    return 0;
-}
-
-void i2c_reset(i2c_t *obj) {
-    i2c_stop(obj);
-}
-
-int i2c_byte_read(i2c_t *obj, int last) {
-    return (i2c_do_read(obj, last) & 0xFF);
-}
-
-int i2c_byte_write(i2c_t *obj, int data) {
-    int ack;
-    int status = i2c_do_write(obj, (data & 0xFF), 0);
-    
-    switch(status) {
-        case 0x18: case 0x28:       // Master transmit ACKs
-            ack = 1;
-            break;
-        case 0x40:                  // Master receive address transmitted ACK
-            ack = 1;
-            break;
-        case 0xB8:                  // Slave transmit ACK
-            ack = 1;
-            break;
-        default:
-            ack = 0;
-            break;
-    }
-    
-    return ack;
-}
-
-void i2c_slave_mode(i2c_t *obj, int enable_slave) {
-    if (enable_slave != 0) {
-        i2c_conclr(obj, 1, 1, 1, 0);
-        i2c_conset(obj, 0, 0, 0, 1);
-    } else {
-        i2c_conclr(obj, 1, 1, 1, 1);
-    }
-}
-
-int i2c_slave_receive(i2c_t *obj) {
-    int status;
-    int retval;
-    
-    status = i2c_status(obj);
-    switch(status) {
-        case 0x60: retval = 3; break;
-        case 0x70: retval = 2; break;
-        case 0xA8: retval = 1; break;
-        default  : retval = 0; break;
-    }
-    
-    return(retval);
-}
-
-int i2c_slave_read(i2c_t *obj, char *data, int length) {
-    int count = 0;
-    int status;
-    
-    do {
-        i2c_clear_SI(obj);
-        i2c_wait_SI(obj);
-        status = i2c_status(obj);
-        if((status == 0x80) || (status == 0x90)) {
-            data[count] = I2C_DAT(obj) & 0xFF;
-        }
-        count++;
-    } while (((status == 0x80) || (status == 0x90) ||
-            (status == 0x060) || (status == 0x70)) && (count < length));
-    
-    if(status != 0xA0) {
-        i2c_stop(obj);
-    }
-    
-    i2c_clear_SI(obj);
-    
-    return (count - 1);
-}
-
-int i2c_slave_write(i2c_t *obj, const char *data, int length) {
-    int count = 0;
-    int status;
-    
-    if(length <= 0) {
-        return(0);
-    }
-    
-    do {
-        status = i2c_do_write(obj, data[count], 0);
-        count++;
-    } while ((count < length) && (status == 0xB8));
-    
-    if ((status != 0xC0) && (status != 0xC8)) {
-        i2c_stop(obj);
-    }
-    
-    i2c_clear_SI(obj);
-    
-    return(count);
-}
-
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
-    uint32_t addr;
-    
-    if ((idx >= 0) && (idx <= 3)) {
-        addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
-        *((uint32_t *) addr) = address & 0xFF;
-        addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
-        *((uint32_t *) addr) = mask & 0xFE;
-    }
-}

--- a/vendor/NXP/LPC1768/hal/objects.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,78 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    uint32_t port;
-    uint32_t pin;
-    uint32_t ch;
-};
-
-struct port_s {
-    __IO uint32_t *reg_dir;
-    __IO uint32_t *reg_out;
-    __I  uint32_t *reg_in;
-    PortName port;
-    uint32_t mask;
-};
-
-struct pwmout_s {
-    __IO uint32_t *MR;
-    PWMName pwm;
-};
-
-struct serial_s {
-    LPC_UART_TypeDef *uart;
-    int index;
-};
-
-struct analogin_s {
-    ADCName adc;
-};
-
-struct dac_s {
-    DACName dac;
-};
-
-struct can_s {
-    LPC_CAN_TypeDef *dev;
-};
-
-struct i2c_s {
-    LPC_I2C_TypeDef *i2c;
-};
-
-struct spi_s {
-    LPC_SSP_TypeDef *spi;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC1768/hal/pinmap.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "pinmap.h"
-#include "error.h"
-
-void pin_function(PinName pin, int function) {
-    if (pin == (uint32_t)NC) return;
-    
-    uint32_t pin_number = (uint32_t)pin - (uint32_t)P0_0;
-    int index = pin_number >> 4;
-    int offset = (pin_number & 0xF) << 1;
-    
-    PINCONARRAY->PINSEL[index] &= ~(0x3 << offset);
-    PINCONARRAY->PINSEL[index] |= function << offset;
-}
-
-void pin_mode(PinName pin, PinMode mode) {
-    if (pin == (uint32_t)NC) { return; }
-    
-    uint32_t pin_number = (uint32_t)pin - (uint32_t)P0_0;
-    int index = pin_number >> 5;
-    int offset = pin_number & 0x1F;
-    uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2;
-    
-    PINCONARRAY->PINMODE_OD[index] &= ~(drain << offset);
-    PINCONARRAY->PINMODE_OD[index] |= drain << offset;
-    
-    if (!drain) {
-        index = pin_number >> 4;
-        offset = (pin_number & 0xF) << 1;
-        
-        PINCONARRAY->PINMODE[index] &= ~(0x3 << offset);
-        PINCONARRAY->PINMODE[index] |= (uint32_t)mode << offset;
-    }
-}

--- a/vendor/NXP/LPC1768/hal/port_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,71 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "port_api.h"
-#include "pinmap.h"
-#include "gpio_api.h"
-
-PinName port_pin(PortName port, int pin_n) {
-    return (PinName)(LPC_GPIO0_BASE + ((port << PORT_SHIFT) | pin_n));
-}
-
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
-    obj->port = port;
-    obj->mask = mask;
-    
-    LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *)(LPC_GPIO0_BASE + ((int)port * 0x20));
-    
-    // Do not use masking, because it prevents the use of the unmasked pins
-    // port_reg->FIOMASK = ~mask;
-    
-    obj->reg_out = &port_reg->FIOPIN;
-    obj->reg_in  = &port_reg->FIOPIN;
-    obj->reg_dir  = &port_reg->FIODIR;
-    
-    uint32_t i;
-    // The function is set per pin: reuse gpio logic
-    for (i=0; i<32; i++) {
-        if (obj->mask & (1<<i)) {
-            gpio_set(port_pin(obj->port, i));
-        }
-    }
-
-    port_dir(obj, dir);
-}
-
-void port_mode(port_t *obj, PinMode mode) {
-    uint32_t i;
-    // The mode is set per pin: reuse pinmap logic
-    for (i=0; i<32; i++) {
-        if (obj->mask & (1<<i)) {
-            pin_mode(port_pin(obj->port, i), mode);
-        }
-    }
-}
-
-void port_dir(port_t *obj, PinDirection dir) {
-    switch (dir) {
-        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
-        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
-    }
-}
-
-void port_write(port_t *obj, int value) {
-    *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
-}
-
-int port_read(port_t *obj) {
-    return (*obj->reg_in & obj->mask);
-}

--- a/vendor/NXP/LPC1768/hal/pwmout_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,172 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "pwmout_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-#define TCR_CNT_EN       0x00000001
-#define TCR_RESET        0x00000002
-
-//  PORT ID, PWM ID, Pin function
-static const PinMap PinMap_PWM[] = {
-    {P1_18, PWM_1, 2},
-    {P1_20, PWM_2, 2},
-    {P1_21, PWM_3, 2},
-    {P1_23, PWM_4, 2},
-    {P1_24, PWM_5, 2},
-    {P1_26, PWM_6, 2},
-    {P2_0 , PWM_1, 1},
-    {P2_1 , PWM_2, 1},
-    {P2_2 , PWM_3, 1},
-    {P2_3 , PWM_4, 1},
-    {P2_4 , PWM_5, 1},
-    {P2_5 , PWM_6, 1},
-    {P3_25, PWM_2, 3},
-    {P3_26, PWM_3, 3},
-    {NC, NC, 0}
-};
-
-__IO uint32_t *PWM_MATCH[] = {
-    &(LPC_PWM1->MR0),
-    &(LPC_PWM1->MR1),
-    &(LPC_PWM1->MR2),
-    &(LPC_PWM1->MR3),
-    &(LPC_PWM1->MR4),
-    &(LPC_PWM1->MR5),
-    &(LPC_PWM1->MR6)
-};
-
-#define TCR_PWM_EN       0x00000008
-
-static unsigned int pwm_clock_mhz;
-
-void pwmout_init(pwmout_t* obj, PinName pin) {
-    // determine the channel
-    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
-    if (pwm == (uint32_t)NC)
-        error("PwmOut pin mapping failed");
-    
-    obj->pwm = pwm;
-    obj->MR = PWM_MATCH[pwm];
-    
-    // ensure the power is on
-    LPC_SC->PCONP |= 1 << 6;
-    
-    // ensure clock to /4
-    LPC_SC->PCLKSEL0 &= ~(0x3 << 12);     // pclk = /4
-    LPC_PWM1->PR = 0;                     // no pre-scale
-    
-    // ensure single PWM mode
-    LPC_PWM1->MCR = 1 << 1; // reset TC on match 0
-    
-    // enable the specific PWM output
-    LPC_PWM1->PCR |= 1 << (8 + pwm);
-    
-    pwm_clock_mhz = SystemCoreClock / 4000000;
-    
-    // default to 20ms: standard for servos, and fine for e.g. brightness control
-    pwmout_period_ms(obj, 20);
-    pwmout_write    (obj, 0);
-    
-    // Wire pinout
-    pinmap_pinout(pin, PinMap_PWM);
-}
-
-void pwmout_free(pwmout_t* obj) {
-    // [TODO]
-}
-
-void pwmout_write(pwmout_t* obj, float value) {
-    if (value < 0.0f) {
-        value = 0.0;
-    } else if (value > 1.0f) {
-        value = 1.0;
-    }
-    
-    // set channel match to percentage
-    uint32_t v = (uint32_t)((float)(LPC_PWM1->MR0) * value);
-    
-    // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
-    if (v == LPC_PWM1->MR0) {
-        v++;
-    }
-    
-    *obj->MR = v;
-    
-    // accept on next period start
-    LPC_PWM1->LER |= 1 << obj->pwm;
-}
-
-float pwmout_read(pwmout_t* obj) {
-    float v = (float)(*obj->MR) / (float)(LPC_PWM1->MR0);
-    return (v > 1.0f) ? (1.0f) : (v);
-}
-
-void pwmout_period(pwmout_t* obj, float seconds) {
-    pwmout_period_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_period_ms(pwmout_t* obj, int ms) {
-    pwmout_period_us(obj, ms * 1000);
-}
-
-// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
-    // calculate number of ticks
-    uint32_t ticks = pwm_clock_mhz * us;
-
-    // set reset
-    LPC_PWM1->TCR = TCR_RESET;
-
-    // set the global match register
-    LPC_PWM1->MR0 = ticks;
-
-    // Scale the pulse width to preserve the duty ratio
-    if (LPC_PWM1->MR0 > 0) {
-        *obj->MR = (*obj->MR * ticks) / LPC_PWM1->MR0;
-    }
-
-    // set the channel latch to update value at next period start
-    LPC_PWM1->LER |= 1 << 0;
-
-    // enable counter and pwm, clear reset
-    LPC_PWM1->TCR = TCR_CNT_EN | TCR_PWM_EN;
-}
-
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
-    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
-    pwmout_pulsewidth_us(obj, ms * 1000);
-}
-
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
-    // calculate number of ticks
-    uint32_t v = pwm_clock_mhz * us;
-    
-    // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
-    if (v == LPC_PWM1->MR0) {
-        v++;
-    }
-    
-    // set the match register value
-    *obj->MR = v;
-    
-    // set the channel latch to update value at next period start
-    LPC_PWM1->LER |= 1 << obj->pwm;
-}

--- a/vendor/NXP/LPC1768/hal/rtc_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "rtc_api.h"
-
-// ensure rtc is running (unchanged if already running)
-
-/* Setup the RTC based on a time structure, ensuring RTC is enabled
- *
- * Can be clocked by a 32.768KHz oscillator or prescale divider based on the APB clock
- * - We want to use the 32khz clock, allowing for sleep mode
- *
- * Most registers are not changed by a Reset
- * - We must initialize these registers between power-on and setting the RTC into operation
-
- * Clock Control Register
- *  RTC_CCR[0] : Enable - 0 = Disabled, 1 = Enabled
- *  RTC_CCR[1] : Reset - 0 = Normal, 1 = Reset
- *  RTC_CCR[4] : Clock Source - 0 = Prescaler, 1 = 32k Xtal
- *
- * The RTC may already be running, so we should set it up
- * without impacting if it is the case
- */
-void rtc_init(void) {
-    LPC_SC->PCONP |= 0x200; // Ensure power is on
-    LPC_RTC->CCR = 0x00;
-    
-    LPC_RTC->CCR |= 1 << 0; // Ensure the RTC is enabled
-}
-
-void rtc_free(void) {
-    // [TODO]
-}
-
-/*
- * Little check routine to see if the RTC has been enabled
- *
- * Clock Control Register
- *  RTC_CCR[0] : 0 = Disabled, 1 = Enabled
- *
- */
-int rtc_isenabled(void) {
-    return(((LPC_RTC->CCR) & 0x01) != 0);
-}
-
-/*
- * RTC Registers
- *  RTC_SEC        Seconds 0-59
- *  RTC_MIN        Minutes 0-59
- *  RTC_HOUR    Hour 0-23
- *  RTC_DOM        Day of Month 1-28..31
- *  RTC_DOW        Day of Week 0-6
- *  RTC_DOY        Day of Year 1-365
- *  RTC_MONTH    Month 1-12
- *  RTC_YEAR    Year 0-4095
- *
- * struct tm
- *  tm_sec        seconds after the minute 0-61
- *  tm_min        minutes after the hour 0-59
- *  tm_hour        hours since midnight 0-23
- *  tm_mday        day of the month 1-31
- *  tm_mon        months since January 0-11
- *  tm_year        years since 1900
- *  tm_wday        days since Sunday 0-6
- *  tm_yday        days since January 1 0-365
- *  tm_isdst    Daylight Saving Time flag
- */
-time_t rtc_read(void) {
-    // Setup a tm structure based on the RTC
-    struct tm timeinfo;
-    timeinfo.tm_sec = LPC_RTC->SEC;
-    timeinfo.tm_min = LPC_RTC->MIN;
-    timeinfo.tm_hour = LPC_RTC->HOUR;
-    timeinfo.tm_mday = LPC_RTC->DOM;
-    timeinfo.tm_mon = LPC_RTC->MONTH - 1;
-    timeinfo.tm_year = LPC_RTC->YEAR - 1900;
-    
-    // Convert to timestamp
-    time_t t = mktime(&timeinfo);
-    
-    return t;
-}
-
-void rtc_write(time_t t) {
-    // Convert the time in to a tm
-    struct tm *timeinfo = localtime(&t);
-    
-    // Pause clock, and clear counter register (clears us count)
-    LPC_RTC->CCR |= 2;
-    
-    // Set the RTC
-    LPC_RTC->SEC = timeinfo->tm_sec;
-    LPC_RTC->MIN = timeinfo->tm_min;
-    LPC_RTC->HOUR = timeinfo->tm_hour;
-    LPC_RTC->DOM = timeinfo->tm_mday;
-    LPC_RTC->MONTH = timeinfo->tm_mon + 1;
-    LPC_RTC->YEAR = timeinfo->tm_year + 1900;
-    
-    // Restart clock
-    LPC_RTC->CCR &= ~((uint32_t)2);
-}

--- a/vendor/NXP/LPC1768/hal/serial_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,309 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// math.h required for floating point operations for baud rate calculation
-#include <math.h>
-#include <string.h>
-
-#include "serial_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-/******************************************************************************
- * INITIALIZATION
- ******************************************************************************/
-#define UART_NUM    4
-
-static const PinMap PinMap_UART_TX[] = {
-    {P0_0,  UART_3, 2},
-    {P0_2,  UART_0, 1},
-    {P0_10, UART_2, 1},
-    {P0_15, UART_1, 1},
-    {P0_25, UART_3, 3},
-    {P2_0 , UART_1, 2},
-    {P2_8 , UART_2, 2},
-    {P4_28, UART_3, 3},
-    {NC   , NC    , 0}
-};
-
-static const PinMap PinMap_UART_RX[] = {
-    {P0_1 , UART_3, 2},
-    {P0_3 , UART_0, 1},
-    {P0_11, UART_2, 1},
-    {P0_16, UART_1, 1},
-    {P0_26, UART_3, 3},
-    {P2_1 , UART_1, 2},
-    {P2_9 , UART_2, 2},
-    {P4_29, UART_3, 3},
-    {NC   , NC    , 0}
-};
-
-static uint32_t serial_irq_ids[UART_NUM] = {0};
-static uart_irq_handler irq_handler;
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
-    int is_stdio_uart = 0;
-    
-    // determine the UART to use
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-    UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    if ((int)uart == NC) {
-        error("Serial pinout mapping failed");
-    }
-    
-    obj->uart = (LPC_UART_TypeDef *)uart;
-    // enable power
-    switch (uart) {
-        case UART_0: LPC_SC->PCONP |= 1 <<  3; break;
-        case UART_1: LPC_SC->PCONP |= 1 <<  4; break;
-        case UART_2: LPC_SC->PCONP |= 1 << 24; break;
-        case UART_3: LPC_SC->PCONP |= 1 << 25; break;
-    }
-    
-    // enable fifos and default rx trigger level
-    obj->uart->FCR = 1 << 0  // FIFO Enable - 0 = Disables, 1 = Enabled
-                   | 0 << 1  // Rx Fifo Reset
-                   | 0 << 2  // Tx Fifo Reset
-                   | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
-
-    // disable irqs
-    obj->uart->IER = 0 << 0  // Rx Data available irq enable
-                   | 0 << 1  // Tx Fifo empty irq enable
-                   | 0 << 2; // Rx Line Status irq enable
-    
-    // set default baud rate and format
-    serial_baud  (obj, 9600);
-    serial_format(obj, 8, ParityNone, 1);
-    
-    // pinout the chosen uart
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    
-    // set rx/tx pins in PullUp mode
-    pin_mode(tx, PullUp);
-    pin_mode(rx, PullUp);
-    
-    switch (uart) {
-        case UART_0: obj->index = 0; break;
-        case UART_1: obj->index = 1; break;
-        case UART_2: obj->index = 2; break;
-        case UART_3: obj->index = 3; break;
-    }
-    
-    is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
-    
-    if (is_stdio_uart) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj) {
-    serial_irq_ids[obj->index] = 0;
-}
-
-// serial_baud
-// set the baud rate, taking in to account the current SystemFrequency
-void serial_baud(serial_t *obj, int baudrate) {
-    // The LPC2300 and LPC1700 have a divider and a fractional divider to control the
-    // baud rate. The formula is:
-    //
-    // Baudrate = (1 / PCLK) * 16 * DL * (1 + DivAddVal / MulVal)
-    //   where:
-    //     1 < MulVal <= 15
-    //     0 <= DivAddVal < 14
-    //     DivAddVal < MulVal
-    //
-    // set pclk to /1
-    switch ((int)obj->uart) {
-        case UART_0: LPC_SC->PCLKSEL0 &= ~(0x3 <<  6); LPC_SC->PCLKSEL0 |= (0x1 <<  6); break;
-        case UART_1: LPC_SC->PCLKSEL0 &= ~(0x3 <<  8); LPC_SC->PCLKSEL0 |= (0x1 <<  8); break;
-        case UART_2: LPC_SC->PCLKSEL1 &= ~(0x3 << 16); LPC_SC->PCLKSEL1 |= (0x1 << 16); break;
-        case UART_3: LPC_SC->PCLKSEL1 &= ~(0x3 << 18); LPC_SC->PCLKSEL1 |= (0x1 << 18); break;
-        default: error("serial_baud"); break;
-    }
-    
-    uint32_t PCLK = SystemCoreClock;
-    
-    // First we check to see if the basic divide with no DivAddVal/MulVal
-    // ratio gives us an integer result. If it does, we set DivAddVal = 0,
-    // MulVal = 1. Otherwise, we search the valid ratio value range to find
-    // the closest match. This could be more elegant, using search methods
-    // and/or lookup tables, but the brute force method is not that much
-    // slower, and is more maintainable.
-    uint16_t DL = PCLK / (16 * baudrate);
-
-    uint8_t DivAddVal = 0;
-    uint8_t MulVal = 1;
-    int hit = 0;
-    uint16_t dlv;
-    uint8_t mv, dav;
-    if ((PCLK % (16 * baudrate)) != 0) {     // Checking for zero remainder
-        float err_best = (float) baudrate;
-        uint16_t dlmax = DL;
-        for ( dlv = (dlmax/2); (dlv <= dlmax) && !hit; dlv++) {
-            for ( mv = 1; mv <= 15; mv++) {
-                for ( dav = 1; dav < mv; dav++) {
-                    float ratio = 1.0f + ((float) dav / (float) mv);
-                    float calcbaud = (float)PCLK / (16.0f * (float) dlv * ratio);
-                    float err = fabs(((float) baudrate - calcbaud) / (float) baudrate);
-                    if (err < err_best) {
-                        DL = dlv;
-                        DivAddVal = dav;
-                        MulVal = mv;
-                        err_best = err;
-                        if (err < 0.001f) {
-                            hit = 1;
-                        }
-                    }
-                }
-            }
-        }
-    }
-    
-    // set LCR[DLAB] to enable writing to divider registers
-    obj->uart->LCR |= (1 << 7);
-    
-    // set divider values
-    obj->uart->DLM = (DL >> 8) & 0xFF;
-    obj->uart->DLL = (DL >> 0) & 0xFF;
-    obj->uart->FDR = (uint32_t) DivAddVal << 0
-                   | (uint32_t) MulVal    << 4;
-    
-    // clear LCR[DLAB]
-    obj->uart->LCR &= ~(1 << 7);
-}
-
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
-    // 0: 1 stop bits, 1: 2 stop bits
-    if (stop_bits != 1 && stop_bits != 2) {
-        error("Invalid stop bits specified");
-    }
-    stop_bits -= 1;
-    
-    // 0: 5 data bits ... 3: 8 data bits
-    if (data_bits < 5 || data_bits > 8) {
-        error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
-    }
-    data_bits -= 5;
-
-    int parity_enable, parity_select;
-    switch (parity) {
-        case ParityNone: parity_enable = 0; parity_select = 0; break;
-        case ParityOdd : parity_enable = 1; parity_select = 0; break;
-        case ParityEven: parity_enable = 1; parity_select = 1; break;
-        case ParityForced1: parity_enable = 1; parity_select = 2; break;
-        case ParityForced0: parity_enable = 1; parity_select = 3; break;
-        default:
-            error("Invalid serial parity setting");
-            return;
-    }
-    
-    obj->uart->LCR = data_bits            << 0
-                   | stop_bits            << 2
-                   | parity_enable        << 3
-                   | parity_select        << 4;
-}
-
-/******************************************************************************
- * INTERRUPTS HANDLING
- ******************************************************************************/
-static inline void uart_irq(uint32_t iir, uint32_t index) {
-    // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
-    SerialIrq irq_type;
-    switch (iir) {
-        case 1: irq_type = TxIrq; break;
-        case 2: irq_type = RxIrq; break;
-        default: return;
-    }
-    
-    if (serial_irq_ids[index] != 0)
-        irq_handler(serial_irq_ids[index], irq_type);
-}
-
-void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0);}
-void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);}
-void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2);}
-void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3);}
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
-    irq_handler = handler;
-    serial_irq_ids[obj->index] = id;
-}
-
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
-    IRQn_Type irq_n = (IRQn_Type)0;
-    uint32_t vector = 0;
-    switch ((int)obj->uart) {
-        case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
-        case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
-        case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
-        case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
-    }
-    
-    if (enable) {
-        obj->uart->IER |= 1 << irq;
-        NVIC_SetVector(irq_n, vector);
-        NVIC_EnableIRQ(irq_n);
-    } else { // disable
-        int all_disabled = 0;
-        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
-        obj->uart->IER &= ~(1 << irq);
-        all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
-        if (all_disabled)
-            NVIC_DisableIRQ(irq_n);
-    }
-}
-
-/******************************************************************************
- * READ/WRITE
- ******************************************************************************/
-int serial_getc(serial_t *obj) {
-    while (!serial_readable(obj));
-    return obj->uart->RBR;
-}
-
-void serial_putc(serial_t *obj, int c) {
-    while (!serial_writable(obj));
-    obj->uart->THR = c;
-    
-    uint32_t lsr = obj->uart->LSR;
-    lsr = lsr;
-    uint32_t thr = obj->uart->THR;
-    thr = thr;
-}
-
-int serial_readable(serial_t *obj) {
-    return obj->uart->LSR & 0x01;
-}
-
-int serial_writable(serial_t *obj) {
-    return obj->uart->LSR & 0x20;
-}
-
-void serial_clear(serial_t *obj) {
-    obj->uart->FCR = 1 << 1  // rx FIFO reset
-                   | 1 << 2  // tx FIFO reset
-                   | 0 << 6; // interrupt depth
-}
-
-void serial_pinout_tx(PinName tx) {
-    pinmap_pinout(tx, PinMap_UART_TX);
-}

--- a/vendor/NXP/LPC1768/hal/sleep.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "sleep_api.h"
-#include "cmsis.h"
-#include "mbed_interface.h"
-
-void sleep(void) {
-    // ensure debug is disconnected
-    mbed_interface_disconnect();
-    
-    // PCON[PD] set to sleep
-    LPC_SC->PCON = 0x0;
-    
-    // SRC[SLEEPDEEP] set to 0 = sleep
-    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
-    
-    // wait for interrupt
-    __WFI();
-}
-
-/*
-* The mbed lpc1768 does not support the deepsleep mode
-* as a debugger is connected to it (the mbed interface).
-*
-* As mentionned in an application note from NXP:
-*
-*       http://www.po-star.com/public/uploads/20120319123122_141.pdf
-*
-*       {{{
-*       The user should be aware of certain limitations during debugging.
-*       The most important is that, due to limitations of the Cortex-M3
-*       integration, the LPC17xx cannot wake up in the usual manner from
-*       Deep Sleep and Power-down modes. It is recommended not to use these
-*       modes during debug. Once an application is downloaded via JTAG/SWD
-*       interface, the USB to SWD/JTAG debug adapter (Keil ULINK2 for example)
-*       should be removed from the target board, and thereafter, power cycle
-*       the LPC17xx to allow wake-up from deep sleep and power-down modes
-*       }}}
-*
-*       As the interface firmware does not reset the target when a
-*       mbed_interface_disconnect() semihosting call is made, the
-*       core cannot wake-up from deepsleep.
-*
-*       We treat a deepsleep() as a normal sleep().
-*/
-
-void deepsleep(void) {
-    // ensure debug is disconnected
-    mbed_interface_disconnect();
-    
-    // PCON[PD] set to deepsleep
-    sleep();
-}

--- a/vendor/NXP/LPC1768/hal/spi_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,222 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <math.h>
-
-#include "spi_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_SPI_SCLK[] = {
-    {P0_7 , SPI_1, 2},
-    {P0_15, SPI_0, 2},
-    {P1_20, SPI_0, 3},
-    {P1_31, SPI_1, 2},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_MOSI[] = {
-    {P0_9 , SPI_1, 2},
-    {P0_13, SPI_1, 2},
-    {P0_18, SPI_0, 2},
-    {P1_24, SPI_0, 3},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_MISO[] = {
-    {P0_8 , SPI_1, 2},
-    {P0_12, SPI_1, 2},
-    {P0_17, SPI_0, 2},
-    {P1_23, SPI_0, 3},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_SSEL[] = {
-    {P0_6 , SPI_1, 2},
-    {P0_11, SPI_1, 2},
-    {P0_16, SPI_0, 2},
-    {P1_21, SPI_0, 3},
-    {NC   , NC   , 0}
-};
-
-static inline int ssp_disable(spi_t *obj);
-static inline int ssp_enable(spi_t *obj);
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
-    // determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-    obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
-    if ((int)obj->spi == NC) {
-        error("SPI pinout mapping failed");
-    }
-    
-    // enable power and clocking
-    switch ((int)obj->spi) {
-        case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
-        case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
-    }
-    
-    // set default format and frequency
-    if (ssel == NC) {
-        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
-    } else {
-        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
-    }
-    spi_frequency(obj, 1000000);
-    
-    // enable the ssp channel
-    ssp_enable(obj);
-
-    // pin out the spi pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    }
-}
-
-void spi_free(spi_t *obj) {}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
-    ssp_disable(obj);
-    if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
-        error("SPI format error");
-    }
-    
-    int polarity = (mode & 0x2) ? 1 : 0;
-    int phase = (mode & 0x1) ? 1 : 0;
-    
-    // set it up
-    int DSS = bits - 1;            // DSS (data select size)
-    int SPO = (polarity) ? 1 : 0;  // SPO - clock out polarity
-    int SPH = (phase) ? 1 : 0;     // SPH - clock out phase
-    
-    int FRF = 0;                   // FRF (frame format) = SPI
-    uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
-    tmp |= DSS << 0
-        | FRF << 4
-        | SPO << 6
-        | SPH << 7;
-    obj->spi->CR0 = tmp;
-    
-    tmp = obj->spi->CR1;
-    tmp &= ~(0xD);
-    tmp |= 0 << 0                   // LBM - loop back mode - off
-        | ((slave) ? 1 : 0) << 2   // MS - master slave mode, 1 = slave
-        | 0 << 3;                  // SOD - slave output disable - na
-    obj->spi->CR1 = tmp;
-    
-    ssp_enable(obj);
-}
-
-void spi_frequency(spi_t *obj, int hz) {
-    ssp_disable(obj);
-    
-    // setup the spi clock diveder to /1
-    switch ((int)obj->spi) {
-        case SPI_0:
-            LPC_SC->PCLKSEL1 &= ~(3 << 10);
-            LPC_SC->PCLKSEL1 |=  (1 << 10);
-            break;
-        case SPI_1:
-            LPC_SC->PCLKSEL0 &= ~(3 << 20);
-            LPC_SC->PCLKSEL0 |=  (1 << 20);
-            break;
-    }
-    
-    uint32_t PCLK = SystemCoreClock;
-    
-    int prescaler;
-    
-    for (prescaler = 2; prescaler <= 254; prescaler += 2) {
-        int prescale_hz = PCLK / prescaler;
-        
-        // calculate the divider
-        int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
-        
-        // check we can support the divider
-        if (divider < 256) {
-            // prescaler
-            obj->spi->CPSR = prescaler;
-            
-            // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
-            obj->spi->CR0 |= (divider - 1) << 8;
-            ssp_enable(obj);
-            return;
-        }
-    }
-    error("Couldn't setup requested SPI frequency");
-}
-
-static inline int ssp_disable(spi_t *obj) {
-    return obj->spi->CR1 &= ~(1 << 1);
-}
-
-static inline int ssp_enable(spi_t *obj) {
-    return obj->spi->CR1 |= (1 << 1);
-}
-
-static inline int ssp_readable(spi_t *obj) {
-    return obj->spi->SR & (1 << 2);
-}
-
-static inline int ssp_writeable(spi_t *obj) {
-    return obj->spi->SR & (1 << 1);
-}
-
-static inline void ssp_write(spi_t *obj, int value) {
-    while (!ssp_writeable(obj));
-    obj->spi->DR = value;
-}
-
-static inline int ssp_read(spi_t *obj) {
-    while (!ssp_readable(obj));
-    return obj->spi->DR;
-}
-
-static inline int ssp_busy(spi_t *obj) {
-    return (obj->spi->SR & (1 << 4)) ? (1) : (0);
-}
-
-int spi_master_write(spi_t *obj, int value) {
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj) {
-    return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
-};
-
-int spi_slave_read(spi_t *obj) {
-    return obj->spi->DR;
-}
-
-void spi_slave_write(spi_t *obj, int value) {
-    while (ssp_writeable(obj) == 0) ;
-    obj->spi->DR = value;
-}
-
-int spi_busy(spi_t *obj) {
-    return ssp_busy(obj);
-}

--- a/vendor/NXP/LPC1768/hal/us_ticker.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,64 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stddef.h>
-#include "us_ticker_api.h"
-#include "PeripheralNames.h"
-
-#define US_TICKER_TIMER      ((LPC_TIM_TypeDef *)LPC_TIM3_BASE)
-#define US_TICKER_TIMER_IRQn TIMER3_IRQn
-
-int us_ticker_inited = 0;
-
-void us_ticker_init(void) {
-    if (us_ticker_inited) return;
-    us_ticker_inited = 1;
-    
-    LPC_SC->PCONP |= 1 << 23; // Clock TIMER_3
-    
-    US_TICKER_TIMER->CTCR = 0x0; // timer mode
-    uint32_t PCLK = SystemCoreClock / 4;
-    
-    US_TICKER_TIMER->TCR = 0x2;  // reset
-    
-    uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks)
-    US_TICKER_TIMER->PR = prescale - 1;
-    US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0
-    
-    NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
-    NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
-}
-
-uint32_t us_ticker_read() {
-    if (!us_ticker_inited)
-        us_ticker_init();
-    
-    return US_TICKER_TIMER->TC;
-}
-
-void us_ticker_set_interrupt(unsigned int timestamp) {
-    // set match value
-    US_TICKER_TIMER->MR0 = timestamp;
-    // enable match interrupt
-    US_TICKER_TIMER->MCR |= 1;
-}
-
-void us_ticker_disable_interrupt(void) {
-    US_TICKER_TIMER->MCR &= ~1;
-}
-
-void us_ticker_clear_interrupt(void) {
-    US_TICKER_TIMER->IR = 1;
-}

--- a/vendor/NXP/LPC2368/cmsis/ARM/LPC2368.sct	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,24 +0,0 @@
-
-LR_IROM1 0x00000000 0x80000  {    ; load region size_region
-  ER_IROM1 0x00000000 0x80000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  RW_IRAM1 0x40000120 0x7EE0  {  ; RW data, inc space for realmonitor
-   .ANY (+RW +ZI)
-  }
-  RW_IRAM2 0x7FD00000 0x2000  {  ; RW data, USB RAM
-   .ANY (AHBSRAM0)
-  }
-  RW_IRAM3 0x7FE00000 0x4000  {  ; RW data, ETH RAM
-   .ANY (AHBSRAM1)
-  }
-  RW_IRAM4 0xE0038000 0x0800  {  ; RW data, CAN RAM
-   .ANY (CANRAM)
-  }
-  RW_IRAM5 0xE0084000 0x0800  {  ; RW data, RTC RAM
-   .ANY (RTCRAM)
-  }
-}
-

--- a/vendor/NXP/LPC2368/cmsis/ARM/sys.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * Setup a fixed single stack/heap memory model, 
- *  between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/vendor/NXP/LPC2368/cmsis/ARM/vector_functions.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,248 +0,0 @@
-;/* mbed Microcontroller Library - InterruptIn
-; * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
-; */
- 
-#line 1 "vector_functions.s"
-;
-;
-;
-
-#line 1 "vector_defns.h"
-
-
-
- 
-
-
-
- 
-
-#line 21 "vector_defns.h"
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#line 47 "vector_defns.h"
-
-
-#line 58 "vector_defns.h"
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#line 6 "vector_functions.s"
-
-
-        AREA    VECFUNCS, CODE, READONLY
-        ARM
-        PRESERVE8
-
-
-
-
-
-        EXPORT __mbed_fiq [WEAK]
-        EXPORT __mbed_undef [WEAK]
-        EXPORT __mbed_prefetch_abort [WEAK]
-        EXPORT __mbed_data_abort [WEAK]
-        EXPORT __mbed_irq [WEAK]
-        EXPORT __mbed_swi [WEAK]
-        EXPORT __mbed_dcc_irq [WEAK]
-        EXPORT __mbed_reset [WEAK]
-        IMPORT __mbed_init_realmonitor
-
-;
-;
-__mbed_fiq
-        B       __mbed_fiq
-
-;
-;
-__mbed_undef
-        LDR     PC, =0x7fffffa0
-
-;
-;
-__mbed_prefetch_abort
-        LDR     PC, =0x7fffffb0
-
-;
-;
-__mbed_data_abort
-        LDR     PC, =0x7fffffc0
-
-;
-;
-;
-;
-;
-;
-;
-;
-;
-__mbed_irq
-        ;
-        MSR     CPSR_c, #0x1F:OR:0x80:OR:0x40
-                
-        ;
-        STMDB   sp!, {r0-r3,r12,lr}    
-
-        ;
-        MOV	r0, #0xFFFFFF00
-        LDR	r0, [r0]	
-
-        ;
-        MOV     lr, pc       
-        BX      r0           
-			    				
-        ;
-        MOV	r0, #0xFFFFFF00
-        STR	r0, [r0]			;
-				
-        ;
-        LDMFD   sp!,{r0-r3,r12,lr}
-
-        ;
-        MSR     CPSR_c, #0x12:OR:0x80:OR:0x40
-
-        ;
-        SUBS    pc, lr, #4 
-
-;
-;
-;
-;
-__mbed_swi
-        ;
-        ;
-        STMFD   sp!, {a4, r4, ip, lr}
-
-        ;
-        LDR     r4, =0x40000040
-
-        ;
-        ;
-        LDR     a4, =0x00940000
-        LDR	PC, =0x7ffff820				
-
-;
-;
-;
-;
-__mbed_dcc_irq
-
-        ;
-			
-        ;
-        LDMFD    sp!,{r0-r3,r12,lr}
-
-        ;
-        MSR     CPSR_c, #0x12:OR:0x80:OR:0x40
-
-        ;
-				
-        ;
-        SUB     lr, lr, #4              ;
-        STMFD   sp!, {ip,lr}            ;
-			
-        ;
-        LDR     LR, =0xfffff000
-        STR     LR, [LR, #0xf00]
-			
-        ;
-        ;
-        ;
-        ;
-        LDR     PC, =0x7fffffe0			 
-
-;
-; __mbed_reset is called after reset
-; we setup the stacks and realmonitor, then call Reset_Handler like on M3
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                MOV     LR, PC       
-                BX      R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-__mbed_reset
-
-        ;
-
-        LDR     R0, =(0x40000000 + 0x8000)
-
-        ;
-        MSR     CPSR_c, #0x1B:OR:0x80:OR:0x40
-        MOV     SP, R0
-        SUB     R0, R0, #0x00000040
-
-        ;
-        MSR     CPSR_c, #0x17:OR:0x80:OR:0x40
-        MOV     SP, R0
-        SUB     R0, R0, #0x00000040
-
-        ;
-        MSR     CPSR_c, #0x11:OR:0x80:OR:0x40
-        MOV     SP, R0
-        SUB     R0, R0, #0x00000000
-
-        ;
-        MSR     CPSR_c, #0x12:OR:0x80:OR:0x40
-        MOV     SP, R0
-        SUB     R0, R0, #0x00000040
-
-        ;
-        MSR     CPSR_c, #0x13:OR:0x80:OR:0x40
-        MOV     SP, R0
-        SUB     R0, R0, #0x00000040
-
-        ;
-        MSR     CPSR_c, #0x10
-        MOV     SP, R0
-
-        ;
-        LDR     R0, =__mbed_init_realmonitor
-        MOV     LR, PC       
-        BX      R0           
-        
-        ;
-        LDR     R0, =Reset_Handler
-        BX      R0
-
-        
-        END

--- a/vendor/NXP/LPC2368/cmsis/ARM/vector_table.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,99 +0,0 @@
-;/* mbed Microcontroller Library - InterruptIn
-; * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
-; */
- 
-#line 1 "vector_table.s"
-;
-
-
- 
-
-#line 1 "vector_defns.h"
-
-
-
- 
-
-
-
- 
-
-#line 21 "vector_defns.h"
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#line 47 "vector_defns.h"
-
-
-#line 58 "vector_defns.h"
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#line 7 "vector_table.s"
-        
-;
-
-
-        AREA    RESET, CODE, READONLY
-        ARM
-;        ENTRY
-        PRESERVE8
-
-
-
-
-
-;        EXPORT __main
-        IMPORT __mbed_reset
-        IMPORT __mbed_undef
-        IMPORT __mbed_swi
-        IMPORT __mbed_prefetch_abort
-        IMPORT __mbed_data_abort
-        IMPORT __mbed_irq
-        IMPORT __mbed_fiq
-
-;
-
- 
-;__main
-        LDR     PC, =__mbed_reset
-        LDR     PC, =__mbed_undef
-        LDR     PC, =__mbed_swi
-        LDR     PC, =__mbed_prefetch_abort
-        LDR     PC, =__mbed_data_abort
-        NOP     ;
-        LDR     PC, =__mbed_irq
-        LDR     PC, =__mbed_fiq
-        
-
-        END

--- a/vendor/NXP/LPC2368/cmsis/GCC_ARM/LPC2368.ld	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,206 +0,0 @@
-OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(vectors)
-
-/* Memory Definitions: */
-MEMORY
-{
-    Flash  (rx)  : ORIGIN = 0x00000000, LENGTH = 512k
-    Ram    (rwx) : ORIGIN = 0x40000000, LENGTH = 32k
-    UsbRam (rw)  : ORIGIN = 0x7FD00000, LENGTH = 8k
-    EthRam (rw)  : ORIGIN = 0x7FE00000, LENGTH = 16k
-    CanRam (rw)  : ORIGIN = 0xE0038000, LENGTH = 2k
-    BatRam (rw)  : ORIGIN = 0xE0084000, LENGTH = 2k
-}
-
-/* Stack sizes: */
-UND_Stack_Size = 16;
-SVC_Stack_Size = 512;
-ABT_Stack_Size = 16;
-FIQ_Stack_Size = 16;
-IRQ_Stack_Size = 256;
-Stack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;
-
-/* Stack tops for each mode: */
-__und_stack_top__ = __stacks_top__;
-__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;
-__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;
-__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;
-__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;
-
-/* C-accessible symbols for memory address ranges: */
-__FLASH_segment_start__ = ORIGIN( Flash );
-__FLASH_segment_end__   = ORIGIN( Flash ) + LENGTH( Flash );
-__SRAM_segment_start__  = ORIGIN( Ram );
-__SRAM_segment_end__    = ORIGIN( Ram ) + LENGTH( Ram );
-
-/* Stacks (full descending) at top of RAM, grows downward:
- *
- * __stack_min__ is used by the malloc implementation to ensure heap never collides
- * with stack (assuming stack never grows beyond Stack_Size_Total in length) */
-__stacks_top__ = __SRAM_segment_end__;
-__stacks_min__ = __SRAM_segment_end__ - Stack_Size_Total;
-
-SECTIONS
-{
-    /* first section is .text which is used for code */
-    __text_start__ = . ;
-    .text : {
-        __privileged_code_start__ = . ;
-        KEEP( *( .vectors ) )
-        *( .privileged_code )
-    
-        __privileged_code_end__ = .;
-
-        *( .text .text.* .gnu.linkonce.t.* )
-        *( .plt )
-        *( .gnu.warning )
-        *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )
-        
-        *( .rodata .rodata.* .gnu.linkonce.r.* )
-        
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-        *(.gcc_except_table)
-        *(.eh_frame_hdr)
-        *(.eh_frame)
-        
-        . = ALIGN( 4 ) ;
-        KEEP( *( .init ) )
-        . = ALIGN( 4 ) ;
-        __preinit_array_start = . ;
-        KEEP( *( .preinit_array ) )
-        __preinit_array_end = . ;
-        . = ALIGN( 4 ) ;
-        __init_array_start = . ;
-        KEEP( *( SORT( .init_array.* ) ) )
-        KEEP( *( .init_array ) )
-        __init_array_end = . ;
-        
-        . = ALIGN( 4 ) ;
-        KEEP( *crtbegin.o( .ctors ) )
-        KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )
-        KEEP( *( SORT( .ctors.* ) ) )
-        KEEP( *crtend.o( .ctors ) )
-        
-        . = ALIGN( 4 ) ;
-        KEEP( *( .fini ) )
-        . = ALIGN( 4 ) ;
-        __fini_array_start = . ;
-        KEEP( *( .fini_array ) )
-        KEEP( *( SORT( .fini_array.* ) ) )
-        __fini_array_end = . ;
-        
-        KEEP( *crtbegin.o( .dtors ) )
-        KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )
-        KEEP( *( SORT( .dtors.* ) ) )
-        KEEP( *crtend.o( .dtors ) )
-    
-    } >Flash
-    
-    __exidx_start = . ;
-    .ARM.exidx : {
-        *( .ARM.exidx* .gnu.linkonce.armexidx.* )
-    } >Flash
-    __exidx_end = . ;
-    
-    .text.align : { . = ALIGN( 8 ) ; } >Flash /* Alignment schenanigans */
-    __text_end__ = . ;
-    
-    /* .bss section -- used for uninitialized data */
-    /* Located at the start of RAM */
-    .bss (NOLOAD) : {
-        __bss_start__ = . ;
-        *crt0.o( .ram_vectors )
-        
-        __user_bss_start__ = . ;
-        *( .user_bss )
-        __user_bss_end__ = . ;
-        
-        *( .shbss )
-        *( .bss .bss.* .gnu.linkonce.b.* )
-        *( COMMON )
-        *( .ram.b )
-        . = ALIGN( 8 ) ;
-        
-        __bss_end__ = . ;
-    } >Ram AT>Flash
-
-    /* .data section -- used for initialized data */
-    .data : {
-        __data_start__ = . ;
-        KEEP( *( .jcr ) )
-        *( .got.plt ) *( .got )
-        *( .shdata )
-        *( .data .data.* .gnu.linkonce.d.* )
-        *( .ram )
-        . = ALIGN( 8 ) ;
-        __data_end__ = . ;
-    } >Ram AT>Flash
-
-    __data_init_start__ = LOADADDR( .data ) ;
-
-    /* Heap starts here and grows up in memory */
-    . = ALIGN( 8 ) ;
-    __heap_start__ = . ;
-
-    .stab    0 (NOLOAD) : { *(.stab) }
-    .stabstr 0 (NOLOAD) : { *(.stabstr) }
-    /* DWARF debug sections. */
-    /* Symbols in the DWARF debugging sections are relative to the  */
-    /* beginning of the section so we begin them at 0.              */
-    /* DWARF 1 */
-    .debug           0 : { *(.debug) }
-    .line            0 : { *(.line) }
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo   0 : { *(.debug_srcinfo) }
-    .debug_sfnames   0 : { *(.debug_sfnames) }
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges   0 : { *(.debug_aranges) }
-    .debug_pubnames  0 : { *(.debug_pubnames) }
-    /* DWARF 2 */
-    .debug_info      0 : { *(.debug_info .gnu.linkonce.wi.*) }
-    .debug_abbrev    0 : { *(.debug_abbrev) }
-    .debug_line      0 : { *(.debug_line) }
-    .debug_frame     0 : { *(.debug_frame) }
-    .debug_str       0 : { *(.debug_str) }
-    .debug_loc       0 : { *(.debug_loc) }
-    .debug_macinfo   0 : { *(.debug_macinfo) }
-    /* SGI/MIPS DWARF 2 extensions */
-    .debug_weaknames 0 : { *(.debug_weaknames) }
-    .debug_funcnames 0 : { *(.debug_funcnames) }
-    .debug_typenames 0 : { *(.debug_typenames) }
-    .debug_varnames  0 : { *(.debug_varnames) }
-    /* DWARF 3 */
-    .debug_pubtypes  0 : { *(.debug_pubtypes) }
-    .debug_ranges    0 : { *(.debug_ranges) }
-    
-    .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }
-    .ARM.attributes     0 : {
-        KEEP( *( .ARM.attributes ) )
-        KEEP( *( .gnu.attributes ) )
-    }
-    /DISCARD/             : { *( .note.GNU-stack ) }
-    
-    /* C data can be defined as being in special purpose RAMs using
-     * __attribute__ ((section ("ethram"))) for example. */
-    .usbram (NOLOAD):
-    {
-        *( .usbram )
-        *( .usbram.* )
-    } > UsbRam
-    .ethram (NOLOAD):
-    {
-        *( .ethram )
-        *( .ethram.* )
-    } > EthRam
-    .canram (NOLOAD):
-    {
-        *( .canram )
-        *( .canram.* )
-    } > CanRam
-    .batram (NOLOAD):
-    {
-        *( .batram )
-        *( .batram.* )
-    } > BatRam
-}

--- a/vendor/NXP/LPC2368/cmsis/GCC_ARM/vector_functions.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,180 +0,0 @@
-# 1 "vector_functions.s"
-# 1 "<built-in>"
-# 1 "<command line>"
-# 1 "vector_functions.s"
-;
-;
-;
-
-# 1 "vector_defns.h" 1
-# 6 "vector_functions.s" 2
-
-
-
-
-
-
-        .section VECFUNCS, "ax"
-        .arm
-
-
-        .weak __mbed_fiq
-        .weak __mbed_undef
-        .weak __mbed_prefetch_abort
-        .weak __mbed_data_abort
-        .weak __mbed_irq
-        .weak __mbed_swi
-        .weak __mbed_dcc_irq
-        .weak __mbed_reset
-        .global __mbed_init_realmonitor
-        .global __mbed_init
-
-;
-;
-__mbed_fiq:
-        B __mbed_fiq
-
-;
-;
-__mbed_undef:
-        LDR PC, =0x7fffffa0
-
-;
-;
-__mbed_prefetch_abort:
-        LDR PC, =0x7fffffb0
-
-;
-;
-__mbed_data_abort:
-        LDR PC, =0x7fffffc0
-
-;
-;
-;
-;
-;
-;
-;
-;
-;
-__mbed_irq:
-        ;
-        MSR CPSR_c, #0x1F|0x80|0x40
-
-        ;
-        STMDB sp!, {r0-r3,r12,lr}
-
-        ;
-        MOV r0, #0xFFFFFF00
-        LDR r0, [r0]
-
-        ;
-        MOV lr, pc
-        BX r0
-
-        ;
-        MOV r0, #0xFFFFFF00
-        STR r0, [r0] ;
-
-        ;
-        LDMFD sp!,{r0-r3,r12,lr}
-
-        ;
-        MSR CPSR_c, #0x12|0x80|0x40
-
-        ;
-        SUBS pc, lr, #4
-
-;
-;
-;
-;
-__mbed_swi:
-        ;
-        ;
-        STMFD sp!, {a4, r4, ip, lr}
-
-        ;
-        LDR r4, =0x40000040
-
-        ;
-        ;
-        LDR a4, =0x00940000
-        LDR PC, =0x7ffff820
-
-;
-;
-;
-;
-__mbed_dcc_irq:
-
-        ;
-
-        ;
-        LDMFD sp!,{r0-r3,r12,lr}
-
-        ;
-        MSR CPSR_c, #0x12|0x80|0x40
-
-        ;
-
-        ;
-        SUB lr, lr, #4 ;
-        STMFD sp!, {ip,lr} ;
-
-        ;
-        LDR LR, =0xfffff000
-        STR LR, [LR, #0xf00]
-
-        ;
-        ;
-        ;
-        ;
-        LDR PC, =0x7fffffe0
-
-;
-;
-__mbed_reset:
-
-        ;
-
-        LDR R0, =(0x40000000 + 0x8000)
-
-        ;
-        MSR CPSR_c, #0x1B|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000040
-
-        ;
-        MSR CPSR_c, #0x17|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000040
-
-        ;
-        MSR CPSR_c, #0x11|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000000
-
-        ;
-        MSR CPSR_c, #0x12|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000040
-
-        ;
-        MSR CPSR_c, #0x13|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000040
-
-        ;
-        MSR CPSR_c, #0x10
-        MOV SP, R0
-
-        ;
-        LDR R0, =__mbed_init_realmonitor
-        MOV LR, PC
-        BX R0
-
-        ;
-        LDR R0, =__mbed_init
-        BX R0

--- a/vendor/NXP/LPC2368/cmsis/GCC_ARM/vector_table.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-# 1 "vector_table.s"
-# 1 "<built-in>"
-# 1 "<command line>"
-# 1 "vector_table.s"
-;
-
-
-
-
-# 1 "vector_defns.h" 1
-# 7 "vector_table.s" 2
-
-;
-
-
-
-
-
-
-
-        .section VECTOR_TABLE, "ax"
-        .arm
-
-
-        .global __main
-        .global __mbed_reset
-        .global __mbed_undef
-        .global __mbed_swi
-        .global __mbed_prefetch_abort
-        .global __mbed_data_abort
-        .global __mbed_irq
-        .global __mbed_fiq
-
-;
-
-
-__main:
-        LDR PC, =__mbed_reset
-        LDR PC, =__mbed_undef
-        LDR PC, =__mbed_swi
-        LDR PC, =__mbed_prefetch_abort
-        LDR PC, =__mbed_data_abort
-        NOP ;
-        LDR PC, =__mbed_irq
-        LDR PC, =__mbed_fiq

--- a/vendor/NXP/LPC2368/cmsis/GCC_CR/LPC2368.ld	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,208 +0,0 @@
-OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(vectors)
-
-GROUP(-lsupc++ -lm -lc -lgcc)
-
-/* Memory Definitions: */
-MEMORY
-{
-    Flash  (rx)  : ORIGIN = 0x00000000, LENGTH = 512k
-    Ram    (rwx) : ORIGIN = 0x40000000, LENGTH = 32k
-    UsbRam (rw)  : ORIGIN = 0x7FD00000, LENGTH = 8k
-    EthRam (rw)  : ORIGIN = 0x7FE00000, LENGTH = 16k
-    CanRam (rw)  : ORIGIN = 0xE0038000, LENGTH = 2k
-    BatRam (rw)  : ORIGIN = 0xE0084000, LENGTH = 2k
-}
-
-/* Stack sizes: */
-UND_Stack_Size = 16;
-SVC_Stack_Size = 512;
-ABT_Stack_Size = 16;
-FIQ_Stack_Size = 16;
-IRQ_Stack_Size = 256;
-Stack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;
-
-/* Stack tops for each mode: */
-__und_stack_top__ = __stacks_top__;
-__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;
-__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;
-__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;
-__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;
-
-/* C-accessible symbols for memory address ranges: */
-__FLASH_segment_start__ = ORIGIN( Flash );
-__FLASH_segment_end__   = ORIGIN( Flash ) + LENGTH( Flash );
-__SRAM_segment_start__  = ORIGIN( Ram );
-__SRAM_segment_end__    = ORIGIN( Ram ) + LENGTH( Ram );
-
-/* Stacks (full descending) at top of RAM, grows downward:
- *
- * __stack_min__ is used by the malloc implementation to ensure heap never collides
- * with stack (assuming stack never grows beyond Stack_Size_Total in length) */
-__stacks_top__ = __SRAM_segment_end__;
-__stacks_min__ = __SRAM_segment_end__ - Stack_Size_Total;
-
-SECTIONS
-{
-    /* first section is .text which is used for code */
-    __text_start__ = . ;
-    .text : {
-        __privileged_code_start__ = . ;
-        KEEP( *( .vectors ) )
-        *( .privileged_code )
-    
-        __privileged_code_end__ = .;
-
-        *( .text .text.* .gnu.linkonce.t.* )
-        *( .plt )
-        *( .gnu.warning )
-        *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )
-        
-        *( .rodata .rodata.* .gnu.linkonce.r.* )
-        
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-        *(.gcc_except_table)
-        *(.eh_frame_hdr)
-        *(.eh_frame)
-        
-        . = ALIGN( 4 ) ;
-        KEEP( *( .init ) )
-        . = ALIGN( 4 ) ;
-        __preinit_array_start = . ;
-        KEEP( *( .preinit_array ) )
-        __preinit_array_end = . ;
-        . = ALIGN( 4 ) ;
-        __init_array_start = . ;
-        KEEP( *( SORT( .init_array.* ) ) )
-        KEEP( *( .init_array ) )
-        __init_array_end = . ;
-        
-        . = ALIGN( 4 ) ;
-        KEEP( *crtbegin.o( .ctors ) )
-        KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )
-        KEEP( *( SORT( .ctors.* ) ) )
-        KEEP( *crtend.o( .ctors ) )
-        
-        . = ALIGN( 4 ) ;
-        KEEP( *( .fini ) )
-        . = ALIGN( 4 ) ;
-        __fini_array_start = . ;
-        KEEP( *( .fini_array ) )
-        KEEP( *( SORT( .fini_array.* ) ) )
-        __fini_array_end = . ;
-        
-        KEEP( *crtbegin.o( .dtors ) )
-        KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )
-        KEEP( *( SORT( .dtors.* ) ) )
-        KEEP( *crtend.o( .dtors ) )
-    
-    } >Flash
-    
-    __exidx_start = . ;
-    .ARM.exidx : {
-        *( .ARM.exidx* .gnu.linkonce.armexidx.* )
-    } >Flash
-    __exidx_end = . ;
-    
-    .text.align : { . = ALIGN( 8 ) ; } >Flash /* Alignment schenanigans */
-    __text_end__ = . ;
-    
-    /* .bss section -- used for uninitialized data */
-    /* Located at the start of RAM */
-    .bss (NOLOAD) : {
-        __bss_start__ = . ;
-        *crt0.o( .ram_vectors )
-        
-        __user_bss_start__ = . ;
-        *( .user_bss )
-        __user_bss_end__ = . ;
-        
-        *( .shbss )
-        *( .bss .bss.* .gnu.linkonce.b.* )
-        *( COMMON )
-        *( .ram.b )
-        . = ALIGN( 8 ) ;
-        
-        __bss_end__ = . ;
-    } >Ram AT>Flash
-
-    /* .data section -- used for initialized data */
-    .data : {
-        __data_start__ = . ;
-        KEEP( *( .jcr ) )
-        *( .got.plt ) *( .got )
-        *( .shdata )
-        *( .data .data.* .gnu.linkonce.d.* )
-        *( .ram )
-        . = ALIGN( 8 ) ;
-        __data_end__ = . ;
-    } >Ram AT>Flash
-
-    __data_init_start__ = LOADADDR( .data ) ;
-
-    /* Heap starts here and grows up in memory */
-    . = ALIGN( 8 ) ;
-    __heap_start__ = . ;
-
-    .stab    0 (NOLOAD) : { *(.stab) }
-    .stabstr 0 (NOLOAD) : { *(.stabstr) }
-    /* DWARF debug sections. */
-    /* Symbols in the DWARF debugging sections are relative to the  */
-    /* beginning of the section so we begin them at 0.              */
-    /* DWARF 1 */
-    .debug           0 : { *(.debug) }
-    .line            0 : { *(.line) }
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo   0 : { *(.debug_srcinfo) }
-    .debug_sfnames   0 : { *(.debug_sfnames) }
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges   0 : { *(.debug_aranges) }
-    .debug_pubnames  0 : { *(.debug_pubnames) }
-    /* DWARF 2 */
-    .debug_info      0 : { *(.debug_info .gnu.linkonce.wi.*) }
-    .debug_abbrev    0 : { *(.debug_abbrev) }
-    .debug_line      0 : { *(.debug_line) }
-    .debug_frame     0 : { *(.debug_frame) }
-    .debug_str       0 : { *(.debug_str) }
-    .debug_loc       0 : { *(.debug_loc) }
-    .debug_macinfo   0 : { *(.debug_macinfo) }
-    /* SGI/MIPS DWARF 2 extensions */
-    .debug_weaknames 0 : { *(.debug_weaknames) }
-    .debug_funcnames 0 : { *(.debug_funcnames) }
-    .debug_typenames 0 : { *(.debug_typenames) }
-    .debug_varnames  0 : { *(.debug_varnames) }
-    /* DWARF 3 */
-    .debug_pubtypes  0 : { *(.debug_pubtypes) }
-    .debug_ranges    0 : { *(.debug_ranges) }
-    
-    .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }
-    .ARM.attributes     0 : {
-        KEEP( *( .ARM.attributes ) )
-        KEEP( *( .gnu.attributes ) )
-    }
-    /DISCARD/             : { *( .note.GNU-stack ) }
-    
-    /* C data can be defined as being in special purpose RAMs using
-     * __attribute__ ((section ("ethram"))) for example. */
-    .usbram (NOLOAD):
-    {
-        *( .usbram )
-        *( .usbram.* )
-    } > UsbRam
-    .ethram (NOLOAD):
-    {
-        *( .ethram )
-        *( .ethram.* )
-    } > EthRam
-    .canram (NOLOAD):
-    {
-        *( .canram )
-        *( .canram.* )
-    } > CanRam
-    .batram (NOLOAD):
-    {
-        *( .batram )
-        *( .batram.* )
-    } > BatRam
-}

--- a/vendor/NXP/LPC2368/cmsis/GCC_CR/vector_functions.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,180 +0,0 @@
-# 1 "vector_functions.s"
-# 1 "<built-in>"
-# 1 "<command line>"
-# 1 "vector_functions.s"
-;
-;
-;
-
-# 1 "vector_defns.h" 1
-# 6 "vector_functions.s" 2
-
-
-
-
-
-
-        .section VECFUNCS, "ax"
-        .arm
-
-
-        .weak __mbed_fiq
-        .weak __mbed_undef
-        .weak __mbed_prefetch_abort
-        .weak __mbed_data_abort
-        .weak __mbed_irq
-        .weak __mbed_swi
-        .weak __mbed_dcc_irq
-        .weak __mbed_reset
-        .global __mbed_init_realmonitor
-        .global __mbed_init
-
-;
-;
-__mbed_fiq:
-        B __mbed_fiq
-
-;
-;
-__mbed_undef:
-        LDR PC, =0x7fffffa0
-
-;
-;
-__mbed_prefetch_abort:
-        LDR PC, =0x7fffffb0
-
-;
-;
-__mbed_data_abort:
-        LDR PC, =0x7fffffc0
-
-;
-;
-;
-;
-;
-;
-;
-;
-;
-__mbed_irq:
-        ;
-        MSR CPSR_c, #0x1F|0x80|0x40
-
-        ;
-        STMDB sp!, {r0-r3,r12,lr}
-
-        ;
-        MOV r0, #0xFFFFFF00
-        LDR r0, [r0]
-
-        ;
-        MOV lr, pc
-        BX r0
-
-        ;
-        MOV r0, #0xFFFFFF00
-        STR r0, [r0] ;
-
-        ;
-        LDMFD sp!,{r0-r3,r12,lr}
-
-        ;
-        MSR CPSR_c, #0x12|0x80|0x40
-
-        ;
-        SUBS pc, lr, #4
-
-;
-;
-;
-;
-__mbed_swi:
-        ;
-        ;
-        STMFD sp!, {a4, r4, ip, lr}
-
-        ;
-        LDR r4, =0x40000040
-
-        ;
-        ;
-        LDR a4, =0x00940000
-        LDR PC, =0x7ffff820
-
-;
-;
-;
-;
-__mbed_dcc_irq:
-
-        ;
-
-        ;
-        LDMFD sp!,{r0-r3,r12,lr}
-
-        ;
-        MSR CPSR_c, #0x12|0x80|0x40
-
-        ;
-
-        ;
-        SUB lr, lr, #4 ;
-        STMFD sp!, {ip,lr} ;
-
-        ;
-        LDR LR, =0xfffff000
-        STR LR, [LR, #0xf00]
-
-        ;
-        ;
-        ;
-        ;
-        LDR PC, =0x7fffffe0
-
-;
-;
-__mbed_reset:
-
-        ;
-
-        LDR R0, =(0x40000000 + 0x8000)
-
-        ;
-        MSR CPSR_c, #0x1B|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000040
-
-        ;
-        MSR CPSR_c, #0x17|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000040
-
-        ;
-        MSR CPSR_c, #0x11|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000000
-
-        ;
-        MSR CPSR_c, #0x12|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000040
-
-        ;
-        MSR CPSR_c, #0x13|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000040
-
-        ;
-        MSR CPSR_c, #0x10
-        MOV SP, R0
-
-        ;
-        LDR R0, =__mbed_init_realmonitor
-        MOV LR, PC
-        BX R0
-
-        ;
-        LDR R0, =__mbed_init
-        BX R0

--- a/vendor/NXP/LPC2368/cmsis/GCC_CR/vector_table.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-# 1 "vector_table.s"
-# 1 "<built-in>"
-# 1 "<command line>"
-# 1 "vector_table.s"
-;
-
-
-
-
-# 1 "vector_defns.h" 1
-# 7 "vector_table.s" 2
-
-;
-
-
-
-
-
-
-
-        .section VECTOR_TABLE, "ax"
-        .arm
-
-
-        .global __main
-        .global __mbed_reset
-        .global __mbed_undef
-        .global __mbed_swi
-        .global __mbed_prefetch_abort
-        .global __mbed_data_abort
-        .global __mbed_irq
-        .global __mbed_fiq
-
-;
-
-
-__main:
-        LDR PC, =__mbed_reset
-        LDR PC, =__mbed_undef
-        LDR PC, =__mbed_swi
-        LDR PC, =__mbed_prefetch_abort
-        LDR PC, =__mbed_data_abort
-        NOP ;
-        LDR PC, =__mbed_irq
-        LDR PC, =__mbed_fiq

--- a/vendor/NXP/LPC2368/cmsis/GCC_CS/LPC2368.ld	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,207 +0,0 @@
-OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(vectors)
-GROUP(-lsupc++ -lm -lc -lcs3unhosted -lcs3 -lgcc)
-
-/* Memory Definitions: */
-MEMORY
-{
-    Flash  (rx)  : ORIGIN = 0x00000000, LENGTH = 512k
-    Ram    (rwx) : ORIGIN = 0x40000000, LENGTH = 32k
-    UsbRam (rw)  : ORIGIN = 0x7FD00000, LENGTH = 8k
-    EthRam (rw)  : ORIGIN = 0x7FE00000, LENGTH = 16k
-    CanRam (rw)  : ORIGIN = 0xE0038000, LENGTH = 2k
-    BatRam (rw)  : ORIGIN = 0xE0084000, LENGTH = 2k
-}
-
-/* Stack sizes: */
-UND_Stack_Size = 16;
-SVC_Stack_Size = 512;
-ABT_Stack_Size = 16;
-FIQ_Stack_Size = 16;
-IRQ_Stack_Size = 256;
-Stack_Size_Total = UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size;
-
-/* Stack tops for each mode: */
-__und_stack_top__ = __stacks_top__;
-__abt_stack_top__ = __und_stack_top__ - UND_Stack_Size ;
-__fiq_stack_top__ = __abt_stack_top__ - ABT_Stack_Size ;
-__irq_stack_top__ = __fiq_stack_top__ - FIQ_Stack_Size ;
-__svc_stack_top__ = __irq_stack_top__ - IRQ_Stack_Size ;
-
-/* C-accessible symbols for memory address ranges: */
-__FLASH_segment_start__ = ORIGIN( Flash );
-__FLASH_segment_end__   = ORIGIN( Flash ) + LENGTH( Flash );
-__SRAM_segment_start__  = ORIGIN( Ram );
-__SRAM_segment_end__    = ORIGIN( Ram ) + LENGTH( Ram );
-
-/* Stacks (full descending) at top of RAM, grows downward:
- *
- * __stack_min__ is used by the malloc implementation to ensure heap never collides
- * with stack (assuming stack never grows beyond Stack_Size_Total in length) */
-__stacks_top__ = __SRAM_segment_end__;
-__stacks_min__ = __SRAM_segment_end__ - Stack_Size_Total;
-
-SECTIONS
-{
-    /* first section is .text which is used for code */
-    __text_start__ = . ;
-    .text : {
-        __privileged_code_start__ = . ;
-        KEEP( *( .vectors ) )
-        *( .privileged_code )
-    
-        __privileged_code_end__ = .;
-
-        *( .text .text.* .gnu.linkonce.t.* )
-        *( .plt )
-        *( .gnu.warning )
-        *( .glue_7t ) *( .glue_7 ) *( .vfp11_veneer )
-        
-        *( .rodata .rodata.* .gnu.linkonce.r.* )
-        
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-        *(.gcc_except_table)
-        *(.eh_frame_hdr)
-        *(.eh_frame)
-        
-        . = ALIGN( 4 ) ;
-        KEEP( *( .init ) )
-        . = ALIGN( 4 ) ;
-        __preinit_array_start = . ;
-        KEEP( *( .preinit_array ) )
-        __preinit_array_end = . ;
-        . = ALIGN( 4 ) ;
-        __init_array_start = . ;
-        KEEP( *( SORT( .init_array.* ) ) )
-        KEEP( *( .init_array ) )
-        __init_array_end = . ;
-        
-        . = ALIGN( 4 ) ;
-        KEEP( *crtbegin.o( .ctors ) )
-        KEEP( *( EXCLUDE_FILE( *crtend.o ) .ctors ) )
-        KEEP( *( SORT( .ctors.* ) ) )
-        KEEP( *crtend.o( .ctors ) )
-        
-        . = ALIGN( 4 ) ;
-        KEEP( *( .fini ) )
-        . = ALIGN( 4 ) ;
-        __fini_array_start = . ;
-        KEEP( *( .fini_array ) )
-        KEEP( *( SORT( .fini_array.* ) ) )
-        __fini_array_end = . ;
-        
-        KEEP( *crtbegin.o( .dtors ) )
-        KEEP( *( EXCLUDE_FILE( *crtend.o ) .dtors ) )
-        KEEP( *( SORT( .dtors.* ) ) )
-        KEEP( *crtend.o( .dtors ) )
-    
-    } >Flash
-    
-    __exidx_start = . ;
-    .ARM.exidx : {
-        *( .ARM.exidx* .gnu.linkonce.armexidx.* )
-    } >Flash
-    __exidx_end = . ;
-    
-    .text.align : { . = ALIGN( 8 ) ; } >Flash /* Alignment schenanigans */
-    __text_end__ = . ;
-    
-    /* .bss section -- used for uninitialized data */
-    /* Located at the start of RAM */
-    .bss (NOLOAD) : {
-        __bss_start__ = . ;
-        *crt0.o( .ram_vectors )
-        
-        __user_bss_start__ = . ;
-        *( .user_bss )
-        __user_bss_end__ = . ;
-        
-        *( .shbss )
-        *( .bss .bss.* .gnu.linkonce.b.* )
-        *( COMMON )
-        *( .ram.b )
-        . = ALIGN( 8 ) ;
-        
-        __bss_end__ = . ;
-    } >Ram AT>Flash
-
-    /* .data section -- used for initialized data */
-    .data : {
-        __data_start__ = . ;
-        KEEP( *( .jcr ) )
-        *( .got.plt ) *( .got )
-        *( .shdata )
-        *( .data .data.* .gnu.linkonce.d.* )
-        *( .ram )
-        . = ALIGN( 8 ) ;
-        __data_end__ = . ;
-    } >Ram AT>Flash
-
-    __data_init_start__ = LOADADDR( .data ) ;
-
-    /* Heap starts here and grows up in memory */
-    . = ALIGN( 8 ) ;
-    __heap_start__ = . ;
-
-    .stab    0 (NOLOAD) : { *(.stab) }
-    .stabstr 0 (NOLOAD) : { *(.stabstr) }
-    /* DWARF debug sections. */
-    /* Symbols in the DWARF debugging sections are relative to the  */
-    /* beginning of the section so we begin them at 0.              */
-    /* DWARF 1 */
-    .debug           0 : { *(.debug) }
-    .line            0 : { *(.line) }
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo   0 : { *(.debug_srcinfo) }
-    .debug_sfnames   0 : { *(.debug_sfnames) }
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges   0 : { *(.debug_aranges) }
-    .debug_pubnames  0 : { *(.debug_pubnames) }
-    /* DWARF 2 */
-    .debug_info      0 : { *(.debug_info .gnu.linkonce.wi.*) }
-    .debug_abbrev    0 : { *(.debug_abbrev) }
-    .debug_line      0 : { *(.debug_line) }
-    .debug_frame     0 : { *(.debug_frame) }
-    .debug_str       0 : { *(.debug_str) }
-    .debug_loc       0 : { *(.debug_loc) }
-    .debug_macinfo   0 : { *(.debug_macinfo) }
-    /* SGI/MIPS DWARF 2 extensions */
-    .debug_weaknames 0 : { *(.debug_weaknames) }
-    .debug_funcnames 0 : { *(.debug_funcnames) }
-    .debug_typenames 0 : { *(.debug_typenames) }
-    .debug_varnames  0 : { *(.debug_varnames) }
-    /* DWARF 3 */
-    .debug_pubtypes  0 : { *(.debug_pubtypes) }
-    .debug_ranges    0 : { *(.debug_ranges) }
-    
-    .note.gnu.arm.ident 0 : { KEEP( *( .note.gnu.arm.ident ) ) }
-    .ARM.attributes     0 : {
-        KEEP( *( .ARM.attributes ) )
-        KEEP( *( .gnu.attributes ) )
-    }
-    /DISCARD/             : { *( .note.GNU-stack ) }
-    
-    /* C data can be defined as being in special purpose RAMs using
-     * __attribute__ ((section ("ethram"))) for example. */
-    .usbram (NOLOAD):
-    {
-        *( .usbram )
-        *( .usbram.* )
-    } > UsbRam
-    .ethram (NOLOAD):
-    {
-        *( .ethram )
-        *( .ethram.* )
-    } > EthRam
-    .canram (NOLOAD):
-    {
-        *( .canram )
-        *( .canram.* )
-    } > CanRam
-    .batram (NOLOAD):
-    {
-        *( .batram )
-        *( .batram.* )
-    } > BatRam
-}

--- a/vendor/NXP/LPC2368/cmsis/GCC_CS/vector_functions.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,180 +0,0 @@
-# 1 "vector_functions.s"
-# 1 "<built-in>"
-# 1 "<command line>"
-# 1 "vector_functions.s"
-;
-;
-;
-
-# 1 "vector_defns.h" 1
-# 6 "vector_functions.s" 2
-
-
-
-
-
-
-        .section VECFUNCS, "ax"
-        .arm
-
-
-        .weak __mbed_fiq
-        .weak __mbed_undef
-        .weak __mbed_prefetch_abort
-        .weak __mbed_data_abort
-        .weak __mbed_irq
-        .weak __mbed_swi
-        .weak __mbed_dcc_irq
-        .weak __mbed_reset
-        .global __mbed_init_realmonitor
-        .global __mbed_init
-
-;
-;
-__mbed_fiq:
-        B __mbed_fiq
-
-;
-;
-__mbed_undef:
-        LDR PC, =0x7fffffa0
-
-;
-;
-__mbed_prefetch_abort:
-        LDR PC, =0x7fffffb0
-
-;
-;
-__mbed_data_abort:
-        LDR PC, =0x7fffffc0
-
-;
-;
-;
-;
-;
-;
-;
-;
-;
-__mbed_irq:
-        ;
-        MSR CPSR_c, #0x1F|0x80|0x40
-
-        ;
-        STMDB sp!, {r0-r3,r12,lr}
-
-        ;
-        MOV r0, #0xFFFFFF00
-        LDR r0, [r0]
-
-        ;
-        MOV lr, pc
-        BX r0
-
-        ;
-        MOV r0, #0xFFFFFF00
-        STR r0, [r0] ;
-
-        ;
-        LDMFD sp!,{r0-r3,r12,lr}
-
-        ;
-        MSR CPSR_c, #0x12|0x80|0x40
-
-        ;
-        SUBS pc, lr, #4
-
-;
-;
-;
-;
-__mbed_swi:
-        ;
-        ;
-        STMFD sp!, {a4, r4, ip, lr}
-
-        ;
-        LDR r4, =0x40000040
-
-        ;
-        ;
-        LDR a4, =0x00940000
-        LDR PC, =0x7ffff820
-
-;
-;
-;
-;
-__mbed_dcc_irq:
-
-        ;
-
-        ;
-        LDMFD sp!,{r0-r3,r12,lr}
-
-        ;
-        MSR CPSR_c, #0x12|0x80|0x40
-
-        ;
-
-        ;
-        SUB lr, lr, #4 ;
-        STMFD sp!, {ip,lr} ;
-
-        ;
-        LDR LR, =0xfffff000
-        STR LR, [LR, #0xf00]
-
-        ;
-        ;
-        ;
-        ;
-        LDR PC, =0x7fffffe0
-
-;
-;
-__mbed_reset:
-
-        ;
-
-        LDR R0, =(0x40000000 + 0x8000)
-
-        ;
-        MSR CPSR_c, #0x1B|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000040
-
-        ;
-        MSR CPSR_c, #0x17|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000040
-
-        ;
-        MSR CPSR_c, #0x11|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000000
-
-        ;
-        MSR CPSR_c, #0x12|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000040
-
-        ;
-        MSR CPSR_c, #0x13|0x80|0x40
-        MOV SP, R0
-        SUB R0, R0, #0x00000040
-
-        ;
-        MSR CPSR_c, #0x10
-        MOV SP, R0
-
-        ;
-        LDR R0, =__mbed_init_realmonitor
-        MOV LR, PC
-        BX R0
-
-        ;
-        LDR R0, =__mbed_init
-        BX R0

--- a/vendor/NXP/LPC2368/cmsis/GCC_CS/vector_table.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-# 1 "vector_table.s"
-# 1 "<built-in>"
-# 1 "<command line>"
-# 1 "vector_table.s"
-;
-
-
-
-
-# 1 "vector_defns.h" 1
-# 7 "vector_table.s" 2
-
-;
-
-
-
-
-
-
-
-        .section VECTOR_TABLE, "ax"
-        .arm
-
-
-        .global __main
-        .global __mbed_reset
-        .global __mbed_undef
-        .global __mbed_swi
-        .global __mbed_prefetch_abort
-        .global __mbed_data_abort
-        .global __mbed_irq
-        .global __mbed_fiq
-
-;
-
-
-__main:
-        LDR PC, =__mbed_reset
-        LDR PC, =__mbed_undef
-        LDR PC, =__mbed_swi
-        LDR PC, =__mbed_prefetch_abort
-        LDR PC, =__mbed_data_abort
-        NOP ;
-        LDR PC, =__mbed_irq
-        LDR PC, =__mbed_fiq

--- a/vendor/NXP/LPC2368/cmsis/LPC23xx.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,864 +0,0 @@
-/* mbed Microcontroller Library - LPC23xx CMSIS-like structs
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- * 
- * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
- */
-
-#ifndef __LPC23xx_H
-#define __LPC23xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-typedef enum IRQn
-{
-/******  LPC23xx Specific Interrupt Numbers *******************************************************/
-  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
-
-  TIMER0_IRQn                   = 4,        /*!< Timer0 Interrupt                                 */
-  TIMER1_IRQn                   = 5,        /*!< Timer1 Interrupt                                 */
-  UART0_IRQn                    = 6,        /*!< UART0 Interrupt                                  */
-  UART1_IRQn                    = 7,        /*!< UART1 Interrupt                                  */
-  PWM1_IRQn                     = 8,        /*!< PWM1 Interrupt                                   */
-  I2C0_IRQn                     = 9,        /*!< I2C0 Interrupt                                   */
-  SPI_IRQn                      = 10,       /*!< SPI Interrupt                                    */
-  SSP0_IRQn                     = 10,       /*!< SSP0 Interrupt                                   */
-  SSP1_IRQn                     = 11,       /*!< SSP1 Interrupt                                   */
-  PLL0_IRQn                     = 12,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
-  RTC_IRQn                      = 13,       /*!< Real Time Clock Interrupt                        */
-  EINT0_IRQn                    = 14,       /*!< External Interrupt 0 Interrupt                   */
-  EINT1_IRQn                    = 15,       /*!< External Interrupt 1 Interrupt                   */
-  EINT2_IRQn                    = 16,       /*!< External Interrupt 2 Interrupt                   */
-  EINT3_IRQn                    = 17,       /*!< External Interrupt 3 Interrupt                   */
-  ADC_IRQn                      = 18,       /*!< A/D Converter Interrupt                          */
-  I2C1_IRQn                     = 19,       /*!< I2C1 Interrupt                                   */
-  BOD_IRQn                      = 20,       /*!< Brown-Out Detect Interrupt                       */
-  ENET_IRQn                     = 21,       /*!< Ethernet Interrupt                               */
-  USB_IRQn                      = 22,       /*!< USB Interrupt                                    */
-  CAN_IRQn                      = 23,       /*!< CAN Interrupt                                    */
-  MIC_IRQn                      = 24,       /*!< Multimedia Interface Controler                   */
-  DMA_IRQn                      = 25,       /*!< General Purpose DMA Interrupt                    */
-  TIMER2_IRQn                   = 26,       /*!< Timer2 Interrupt                                 */
-  TIMER3_IRQn                   = 27,       /*!< Timer3 Interrupt                                 */
-  UART2_IRQn                    = 28,       /*!< UART2 Interrupt                                  */
-  UART3_IRQn                    = 29,       /*!< UART3 Interrupt                                  */
-  I2C2_IRQn                     = 30,       /*!< I2C2 Interrupt                                   */
-  I2S_IRQn                      = 31,       /*!< I2S Interrupt                                    */
-} IRQn_Type;
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the ARM7 Processor and Core Peripherals */
-#define __MPU_PRESENT             0         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-
-#include <core_arm7.h>
-#include "system_LPC23xx.h"                 /* System Header                                      */
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral registers structures             */
-/******************************************************************************/
-#if defined ( __CC_ARM   )
-  #pragma anon_unions
-#endif
-
-/*------------- Vector Interupt Controler (VIC) ------------------------------*/
-typedef struct
-{
-  __I  uint32_t IRQStatus;
-  __I  uint32_t FIQStatus;
-  __I  uint32_t RawIntr;
-  __IO uint32_t IntSelect;
-  __IO uint32_t IntEnable;
-  __O  uint32_t IntEnClr;
-  __IO uint32_t SoftInt;
-  __O  uint32_t SoftIntClr;
-  __IO uint32_t Protection;
-  __IO uint32_t SWPriorityMask;
-  __IO uint32_t RESERVED0[54];
-  __IO uint32_t VectAddr[32];
-  __IO uint32_t RESERVED1[32];
-  __IO uint32_t VectPriority[32];
-  __IO uint32_t RESERVED2[800];
-  __IO uint32_t Address;
-} LPC_VIC_TypeDef;
-
-/*------------- System Control (SC) ------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t MAMCR;
-  __IO uint32_t MAMTIM;
-       uint32_t RESERVED0[14];
-  __IO uint32_t MEMMAP;
-       uint32_t RESERVED1[15];
-  __IO uint32_t PLL0CON;                /* Clocking and Power Control         */
-  __IO uint32_t PLL0CFG;
-  __I  uint32_t PLL0STAT;
-  __O  uint32_t PLL0FEED;
-       uint32_t RESERVED2[12];
-  __IO uint32_t PCON;
-  __IO uint32_t PCONP;
-       uint32_t RESERVED3[15];
-  __IO uint32_t CCLKCFG;
-  __IO uint32_t USBCLKCFG;
-  __IO uint32_t CLKSRCSEL;
-       uint32_t RESERVED4[12];
-  __IO uint32_t EXTINT;                 /* External Interrupts                */
-  __IO uint32_t INTWAKE;
-  __IO uint32_t EXTMODE;
-  __IO uint32_t EXTPOLAR;
-       uint32_t RESERVED6[12];
-  __IO uint32_t RSID;                   /* Reset                              */
-  __IO uint32_t CSPR;
-  __IO uint32_t AHBCFG1;
-  __IO uint32_t AHBCFG2;
-       uint32_t RESERVED7[4];
-  __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */
-  __IO uint32_t IRCTRIM;                /* Clock Dividers                     */
-  __IO uint32_t PCLKSEL0;
-  __IO uint32_t PCLKSEL1;
-       uint32_t RESERVED8[4];
-  __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */
-       uint32_t RESERVED9;
-//  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */
- } LPC_SC_TypeDef;
-
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/
-typedef struct
-{
-  __IO uint32_t PINSEL0;
-  __IO uint32_t PINSEL1;
-  __IO uint32_t PINSEL2;
-  __IO uint32_t PINSEL3;
-  __IO uint32_t PINSEL4;
-  __IO uint32_t PINSEL5;
-  __IO uint32_t PINSEL6;
-  __IO uint32_t PINSEL7;
-  __IO uint32_t PINSEL8;
-  __IO uint32_t PINSEL9;
-  __IO uint32_t PINSEL10;
-       uint32_t RESERVED0[5];
-  __IO uint32_t PINMODE0;
-  __IO uint32_t PINMODE1;
-  __IO uint32_t PINMODE2;
-  __IO uint32_t PINMODE3;
-  __IO uint32_t PINMODE4;
-  __IO uint32_t PINMODE5;
-  __IO uint32_t PINMODE6;
-  __IO uint32_t PINMODE7;
-  __IO uint32_t PINMODE8;
-  __IO uint32_t PINMODE9;
-  __IO uint32_t PINMODE_OD0;
-  __IO uint32_t PINMODE_OD1;
-  __IO uint32_t PINMODE_OD2;
-  __IO uint32_t PINMODE_OD3;
-  __IO uint32_t PINMODE_OD4;
-} LPC_PINCON_TypeDef;
-
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-typedef struct
-{
-  __IO uint32_t FIODIR;
-       uint32_t RESERVED0[3];
-  __IO uint32_t FIOMASK;
-  __IO uint32_t FIOPIN;
-  __IO uint32_t FIOSET;
-  __O  uint32_t FIOCLR;
-} LPC_GPIO_TypeDef;
-
-typedef struct
-{
-  __I  uint32_t IntStatus;
-  __I  uint32_t IO0IntStatR;
-  __I  uint32_t IO0IntStatF;
-  __O  uint32_t IO0IntClr;
-  __IO uint32_t IO0IntEnR;
-  __IO uint32_t IO0IntEnF;
-       uint32_t RESERVED0[3];
-  __I  uint32_t IO2IntStatR;
-  __I  uint32_t IO2IntStatF;
-  __O  uint32_t IO2IntClr;
-  __IO uint32_t IO2IntEnR;
-  __IO uint32_t IO2IntEnF;
-} LPC_GPIOINT_TypeDef;
-
-/*------------- Timer (TIM) --------------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;
-  __IO uint32_t TCR;
-  __IO uint32_t TC;
-  __IO uint32_t PR;
-  __IO uint32_t PC;
-  __IO uint32_t MCR;
-  __IO uint32_t MR0;
-  __IO uint32_t MR1;
-  __IO uint32_t MR2;
-  __IO uint32_t MR3;
-  __IO uint32_t CCR;
-  __I  uint32_t CR0;
-  __I  uint32_t CR1;
-       uint32_t RESERVED0[2];
-  __IO uint32_t EMR;
-       uint32_t RESERVED1[12];
-  __IO uint32_t CTCR;
-} LPC_TIM_TypeDef;
-
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;
-  __IO uint32_t TCR;
-  __IO uint32_t TC;
-  __IO uint32_t PR;
-  __IO uint32_t PC;
-  __IO uint32_t MCR;
-  __IO uint32_t MR0;
-  __IO uint32_t MR1;
-  __IO uint32_t MR2;
-  __IO uint32_t MR3;
-  __IO uint32_t CCR;
-  __I  uint32_t CR0;
-  __I  uint32_t CR1;
-  __I  uint32_t CR2;
-  __I  uint32_t CR3;
-       uint32_t RESERVED0;
-  __IO uint32_t MR4;
-  __IO uint32_t MR5;
-  __IO uint32_t MR6;
-  __IO uint32_t PCR;
-  __IO uint32_t LER;
-       uint32_t RESERVED1[7];
-  __IO uint32_t CTCR;
-} LPC_PWM_TypeDef;
-
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[7];
-  __IO uint8_t  LSR;
-       uint8_t  RESERVED2[7];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED3[3];
-  __IO uint32_t ACR;
-  __IO uint8_t  ICR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  FDR;
-       uint8_t  RESERVED5[7];
-  __IO uint8_t  TER;
-       uint8_t  RESERVED6[27];
-  __IO uint8_t  RS485CTRL;
-       uint8_t  RESERVED7[3];
-  __IO uint8_t  ADRMATCH;
-} LPC_UART_TypeDef;
-
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  MCR;
-       uint8_t  RESERVED2[3];
-  __IO uint8_t  LSR;
-       uint8_t  RESERVED3[3];
-  __IO uint8_t  MSR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED5[3];
-  __IO uint32_t ACR;
-       uint32_t RESERVED6;
-  __IO uint32_t FDR;
-       uint32_t RESERVED7;
-  __IO uint8_t  TER;
-       uint8_t  RESERVED8[27];
-  __IO uint8_t  RS485CTRL;
-       uint8_t  RESERVED9[3];
-  __IO uint8_t  ADRMATCH;
-       uint8_t  RESERVED10[3];
-  __IO uint8_t  RS485DLY;
-} LPC_UART1_TypeDef;
-
-/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t SPCR;
-  __I  uint32_t SPSR;
-  __IO uint32_t SPDR;
-  __IO uint32_t SPCCR;
-       uint32_t RESERVED0[3];
-  __IO uint32_t SPINT;
-} LPC_SPI_TypeDef;
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-typedef struct
-{
-  __IO uint32_t CR0;
-  __IO uint32_t CR1;
-  __IO uint32_t DR;
-  __I  uint32_t SR;
-  __IO uint32_t CPSR;
-  __IO uint32_t IMSC;
-  __IO uint32_t RIS;
-  __IO uint32_t MIS;
-  __IO uint32_t ICR;
-  __IO uint32_t DMACR;
-} LPC_SSP_TypeDef;
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-typedef struct
-{
-  __IO uint32_t I2CONSET;
-  __I  uint32_t I2STAT;
-  __IO uint32_t I2DAT;
-  __IO uint32_t I2ADR0;
-  __IO uint32_t I2SCLH;
-  __IO uint32_t I2SCLL;
-  __O  uint32_t I2CONCLR;
-  __IO uint32_t MMCTRL;
-  __IO uint32_t I2ADR1;
-  __IO uint32_t I2ADR2;
-  __IO uint32_t I2ADR3;
-  __I  uint32_t I2DATA_BUFFER;
-  __IO uint32_t I2MASK0;
-  __IO uint32_t I2MASK1;
-  __IO uint32_t I2MASK2;
-  __IO uint32_t I2MASK3;
-} LPC_I2C_TypeDef;
-
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t I2SDAO;
-  __I  uint32_t I2SDAI;
-  __O  uint32_t I2STXFIFO;
-  __I  uint32_t I2SRXFIFO;
-  __I  uint32_t I2SSTATE;
-  __IO uint32_t I2SDMA1;
-  __IO uint32_t I2SDMA2;
-  __IO uint32_t I2SIRQ;
-  __IO uint32_t I2STXRATE;
-  __IO uint32_t I2SRXRATE;
-  __IO uint32_t I2STXBITRATE;
-  __IO uint32_t I2SRXBITRATE;
-  __IO uint32_t I2STXMODE;
-  __IO uint32_t I2SRXMODE;
-} LPC_I2S_TypeDef;
-
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  ILR;
-       uint8_t  RESERVED0[3];
-  __IO uint8_t  CTC;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  CCR;
-       uint8_t  RESERVED2[3];
-  __IO uint8_t  CIIR;
-       uint8_t  RESERVED3[3];
-  __IO uint8_t  AMR;
-       uint8_t  RESERVED4[3];
-  __I  uint32_t CTIME0;
-  __I  uint32_t CTIME1;
-  __I  uint32_t CTIME2;
-  __IO uint8_t  SEC;
-       uint8_t  RESERVED5[3];
-  __IO uint8_t  MIN;
-       uint8_t  RESERVED6[3];
-  __IO uint8_t  HOUR;
-       uint8_t  RESERVED7[3];
-  __IO uint8_t  DOM;
-       uint8_t  RESERVED8[3];
-  __IO uint8_t  DOW;
-       uint8_t  RESERVED9[3];
-  __IO uint16_t DOY;
-       uint16_t RESERVED10;
-  __IO uint8_t  MONTH;
-       uint8_t  RESERVED11[3];
-  __IO uint16_t YEAR;
-       uint16_t RESERVED12;
-  __IO uint32_t CALIBRATION;
-  __IO uint32_t GPREG0;
-  __IO uint32_t GPREG1;
-  __IO uint32_t GPREG2;
-  __IO uint32_t GPREG3;
-  __IO uint32_t GPREG4;
-  __IO uint8_t  WAKEUPDIS;
-       uint8_t  RESERVED13[3];
-  __IO uint8_t  PWRCTRL;
-       uint8_t  RESERVED14[3];
-  __IO uint8_t  ALSEC;
-       uint8_t  RESERVED15[3];
-  __IO uint8_t  ALMIN;
-       uint8_t  RESERVED16[3];
-  __IO uint8_t  ALHOUR;
-       uint8_t  RESERVED17[3];
-  __IO uint8_t  ALDOM;
-       uint8_t  RESERVED18[3];
-  __IO uint8_t  ALDOW;
-       uint8_t  RESERVED19[3];
-  __IO uint16_t ALDOY;
-       uint16_t RESERVED20;
-  __IO uint8_t  ALMON;
-       uint8_t  RESERVED21[3];
-  __IO uint16_t ALYEAR;
-       uint16_t RESERVED22;
-} LPC_RTC_TypeDef;
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  WDMOD;
-       uint8_t  RESERVED0[3];
-  __IO uint32_t WDTC;
-  __O  uint8_t  WDFEED;
-       uint8_t  RESERVED1[3];
-  __I  uint32_t WDTV;
-  __IO uint32_t WDCLKSEL;
-} LPC_WDT_TypeDef;
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t ADCR;
-  __IO uint32_t ADGDR;
-       uint32_t RESERVED0;
-  __IO uint32_t ADINTEN;
-  __I  uint32_t ADDR0;
-  __I  uint32_t ADDR1;
-  __I  uint32_t ADDR2;
-  __I  uint32_t ADDR3;
-  __I  uint32_t ADDR4;
-  __I  uint32_t ADDR5;
-  __I  uint32_t ADDR6;
-  __I  uint32_t ADDR7;
-  __I  uint32_t ADSTAT;
-  __IO uint32_t ADTRM;
-} LPC_ADC_TypeDef;
-
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t DACR;
-  __IO uint32_t DACCTRL;
-  __IO uint16_t DACCNTVAL;
-} LPC_DAC_TypeDef;
-
-/*------------- Multimedia Card Interface (MCI) ------------------------------*/
-typedef struct
-{
-  __IO uint32_t MCIPower;               /* Power control                      */
-  __IO uint32_t MCIClock;               /* Clock control                      */
-  __IO uint32_t MCIArgument;
-  __IO uint32_t MMCCommand;
-  __I  uint32_t MCIRespCmd;
-  __I  uint32_t MCIResponse0;
-  __I  uint32_t MCIResponse1;
-  __I  uint32_t MCIResponse2;
-  __I  uint32_t MCIResponse3;
-  __IO uint32_t MCIDataTimer;
-  __IO uint32_t MCIDataLength;
-  __IO uint32_t MCIDataCtrl;
-  __I  uint32_t MCIDataCnt;
-} LPC_MCI_TypeDef;
-
-/*------------- Controller Area Network (CAN) --------------------------------*/
-typedef struct
-{
-  __IO uint32_t mask[512];              /* ID Masks                           */
-} LPC_CANAF_RAM_TypeDef;
-
-typedef struct                          /* Acceptance Filter Registers        */
-{
-  __IO uint32_t AFMR;
-  __IO uint32_t SFF_sa;
-  __IO uint32_t SFF_GRP_sa;
-  __IO uint32_t EFF_sa;
-  __IO uint32_t EFF_GRP_sa;
-  __IO uint32_t ENDofTable;
-  __I  uint32_t LUTerrAd;
-  __I  uint32_t LUTerr;
-} LPC_CANAF_TypeDef;
-
-typedef struct                          /* Central Registers                  */
-{
-  __I  uint32_t CANTxSR;
-  __I  uint32_t CANRxSR;
-  __I  uint32_t CANMSR;
-} LPC_CANCR_TypeDef;
-
-typedef struct                          /* Controller Registers               */
-{
-  __IO uint32_t MOD;
-  __O  uint32_t CMR;
-  __IO uint32_t GSR;
-  __I  uint32_t ICR;
-  __IO uint32_t IER;
-  __IO uint32_t BTR;
-  __IO uint32_t EWL;
-  __I  uint32_t SR;
-  __IO uint32_t RFS;
-  __IO uint32_t RID;
-  __IO uint32_t RDA;
-  __IO uint32_t RDB;
-  __IO uint32_t TFI1;
-  __IO uint32_t TID1;
-  __IO uint32_t TDA1;
-  __IO uint32_t TDB1;
-  __IO uint32_t TFI2;
-  __IO uint32_t TID2;
-  __IO uint32_t TDA2;
-  __IO uint32_t TDB2;
-  __IO uint32_t TFI3;
-  __IO uint32_t TID3;
-  __IO uint32_t TDA3;
-  __IO uint32_t TDB3;
-} LPC_CAN_TypeDef;
-
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
-typedef struct                          /* Common Registers                   */
-{
-  __I  uint32_t DMACIntStat;
-  __I  uint32_t DMACIntTCStat;
-  __O  uint32_t DMACIntTCClear;
-  __I  uint32_t DMACIntErrStat;
-  __O  uint32_t DMACIntErrClr;
-  __I  uint32_t DMACRawIntTCStat;
-  __I  uint32_t DMACRawIntErrStat;
-  __I  uint32_t DMACEnbldChns;
-  __IO uint32_t DMACSoftBReq;
-  __IO uint32_t DMACSoftSReq;
-  __IO uint32_t DMACSoftLBReq;
-  __IO uint32_t DMACSoftLSReq;
-  __IO uint32_t DMACConfig;
-  __IO uint32_t DMACSync;
-} LPC_GPDMA_TypeDef;
-
-typedef struct                          /* Channel Registers                  */
-{
-  __IO uint32_t DMACCSrcAddr;
-  __IO uint32_t DMACCDestAddr;
-  __IO uint32_t DMACCLLI;
-  __IO uint32_t DMACCControl;
-  __IO uint32_t DMACCConfig;
-} LPC_GPDMACH_TypeDef;
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-typedef struct
-{
-  __I  uint32_t HcRevision;             /* USB Host Registers                 */
-  __IO uint32_t HcControl;
-  __IO uint32_t HcCommandStatus;
-  __IO uint32_t HcInterruptStatus;
-  __IO uint32_t HcInterruptEnable;
-  __IO uint32_t HcInterruptDisable;
-  __IO uint32_t HcHCCA;
-  __I  uint32_t HcPeriodCurrentED;
-  __IO uint32_t HcControlHeadED;
-  __IO uint32_t HcControlCurrentED;
-  __IO uint32_t HcBulkHeadED;
-  __IO uint32_t HcBulkCurrentED;
-  __I  uint32_t HcDoneHead;
-  __IO uint32_t HcFmInterval;
-  __I  uint32_t HcFmRemaining;
-  __I  uint32_t HcFmNumber;
-  __IO uint32_t HcPeriodicStart;
-  __IO uint32_t HcLSTreshold;
-  __IO uint32_t HcRhDescriptorA;
-  __IO uint32_t HcRhDescriptorB;
-  __IO uint32_t HcRhStatus;
-  __IO uint32_t HcRhPortStatus1;
-  __IO uint32_t HcRhPortStatus2;
-       uint32_t RESERVED0[40];
-  __I  uint32_t Module_ID;
-
-  __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */
-  __IO uint32_t OTGIntEn;
-  __O  uint32_t OTGIntSet;
-  __O  uint32_t OTGIntClr;
-  __IO uint32_t OTGStCtrl;
-  __IO uint32_t OTGTmr;
-       uint32_t RESERVED1[58];
-
-  __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */
-  __IO uint32_t USBDevIntEn;
-  __O  uint32_t USBDevIntClr;
-  __O  uint32_t USBDevIntSet;
-
-  __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */
-  __I  uint32_t USBCmdData;
-
-  __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */
-  __O  uint32_t USBTxData;
-  __I  uint32_t USBRxPLen;
-  __O  uint32_t USBTxPLen;
-  __IO uint32_t USBCtrl;
-  __O  uint32_t USBDevIntPri;
-
-  __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */
-  __IO uint32_t USBEpIntEn;
-  __O  uint32_t USBEpIntClr;
-  __O  uint32_t USBEpIntSet;
-  __O  uint32_t USBEpIntPri;
-
-  __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/
-  __O  uint32_t USBEpInd;
-  __IO uint32_t USBMaxPSize;
-
-  __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */
-  __O  uint32_t USBDMARClr;
-  __O  uint32_t USBDMARSet;
-       uint32_t RESERVED2[9];
-  __IO uint32_t USBUDCAH;
-  __I  uint32_t USBEpDMASt;
-  __O  uint32_t USBEpDMAEn;
-  __O  uint32_t USBEpDMADis;
-  __I  uint32_t USBDMAIntSt;
-  __IO uint32_t USBDMAIntEn;
-       uint32_t RESERVED3[2];
-  __I  uint32_t USBEoTIntSt;
-  __O  uint32_t USBEoTIntClr;
-  __O  uint32_t USBEoTIntSet;
-  __I  uint32_t USBNDDRIntSt;
-  __O  uint32_t USBNDDRIntClr;
-  __O  uint32_t USBNDDRIntSet;
-  __I  uint32_t USBSysErrIntSt;
-  __O  uint32_t USBSysErrIntClr;
-  __O  uint32_t USBSysErrIntSet;
-       uint32_t RESERVED4[15];
-
-  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
-  __O  uint32_t I2C_WO;
-  __I  uint32_t I2C_STS;
-  __IO uint32_t I2C_CTL;
-  __IO uint32_t I2C_CLKHI;
-  __O  uint32_t I2C_CLKLO;
-       uint32_t RESERVED5[823];
-
-  union {
-  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
-  __IO uint32_t OTGClkCtrl;
-  };
-  union {
-  __I  uint32_t USBClkSt;
-  __I  uint32_t OTGClkSt;
-  };
-} LPC_USB_TypeDef;
-
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
-typedef struct
-{
-  __IO uint32_t MAC1;                   /* MAC Registers                      */
-  __IO uint32_t MAC2;
-  __IO uint32_t IPGT;
-  __IO uint32_t IPGR;
-  __IO uint32_t CLRT;
-  __IO uint32_t MAXF;
-  __IO uint32_t SUPP;
-  __IO uint32_t TEST;
-  __IO uint32_t MCFG;
-  __IO uint32_t MCMD;
-  __IO uint32_t MADR;
-  __O  uint32_t MWTD;
-  __I  uint32_t MRDD;
-  __I  uint32_t MIND;
-       uint32_t RESERVED0[2];
-  __IO uint32_t SA0;
-  __IO uint32_t SA1;
-  __IO uint32_t SA2;
-       uint32_t RESERVED1[45];
-  __IO uint32_t Command;                /* Control Registers                  */
-  __I  uint32_t Status;
-  __IO uint32_t RxDescriptor;
-  __IO uint32_t RxStatus;
-  __IO uint32_t RxDescriptorNumber;
-  __I  uint32_t RxProduceIndex;
-  __IO uint32_t RxConsumeIndex;
-  __IO uint32_t TxDescriptor;
-  __IO uint32_t TxStatus;
-  __IO uint32_t TxDescriptorNumber;
-  __IO uint32_t TxProduceIndex;
-  __I  uint32_t TxConsumeIndex;
-       uint32_t RESERVED2[10];
-  __I  uint32_t TSV0;
-  __I  uint32_t TSV1;
-  __I  uint32_t RSV;
-       uint32_t RESERVED3[3];
-  __IO uint32_t FlowControlCounter;
-  __I  uint32_t FlowControlStatus;
-       uint32_t RESERVED4[34];
-  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
-  __IO uint32_t RxFilterWoLStatus;
-  __IO uint32_t RxFilterWoLClear;
-       uint32_t RESERVED5;
-  __IO uint32_t HashFilterL;
-  __IO uint32_t HashFilterH;
-       uint32_t RESERVED6[882];
-  __I  uint32_t IntStatus;              /* Module Control Registers           */
-  __IO uint32_t IntEnable;
-  __O  uint32_t IntClear;
-  __O  uint32_t IntSet;
-       uint32_t RESERVED7;
-  __IO uint32_t PowerDown;
-       uint32_t RESERVED8;
-  __IO uint32_t Module_ID;
-} LPC_EMAC_TypeDef;
-
-#if defined ( __CC_ARM   )
-  #pragma no_anon_unions
-#endif
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-
-/* AHB Peripheral # 0 */
-
-/*
-#define FLASH_BASE            (0x00000000UL)
-#define RAM_BASE              (0x10000000UL)
-#define GPIO_BASE             (0x2009C000UL)
-#define APB0_BASE             (0x40000000UL)
-#define APB1_BASE             (0x40080000UL)
-#define AHB_BASE              (0x50000000UL)
-#define CM3_BASE              (0xE0000000UL)
-*/
-
-// TODO - #define VIC_BASE_ADDR	0xFFFFF000
-
-#define LPC_WDT_BASE              (0xE0000000)
-#define LPC_TIM0_BASE             (0xE0004000)
-#define LPC_TIM1_BASE             (0xE0008000)
-#define LPC_UART0_BASE            (0xE000C000)
-#define LPC_UART1_BASE            (0xE0010000)
-#define LPC_PWM1_BASE             (0xE0018000)
-#define LPC_I2C0_BASE             (0xE001C000)
-#define LPC_SPI_BASE              (0xE0020000)
-#define LPC_RTC_BASE              (0xE0024000)
-#define LPC_GPIOINT_BASE          (0xE0028080)
-#define LPC_PINCON_BASE           (0xE002C000)
-#define LPC_SSP1_BASE             (0xE0030000)
-#define LPC_ADC_BASE              (0xE0034000)
-#define LPC_CANAF_RAM_BASE        (0xE0038000)
-#define LPC_CANAF_BASE            (0xE003C000)
-#define LPC_CANCR_BASE            (0xE0040000)
-#define LPC_CAN1_BASE             (0xE0044000)
-#define LPC_CAN2_BASE             (0xE0048000)
-#define LPC_I2C1_BASE             (0xE005C000)
-#define LPC_SSP0_BASE             (0xE0068000)
-#define LPC_DAC_BASE              (0xE006C000)
-#define LPC_TIM2_BASE             (0xE0070000)
-#define LPC_TIM3_BASE             (0xE0074000)
-#define LPC_UART2_BASE            (0xE0078000)
-#define LPC_UART3_BASE            (0xE007C000)
-#define LPC_I2C2_BASE             (0xE0080000)
-#define LPC_I2S_BASE              (0xE0088000)
-#define LPC_MCI_BASE              (0xE008C000)
-#define LPC_SC_BASE               (0xE01FC000)
-#define LPC_EMAC_BASE             (0xFFE00000)
-#define LPC_GPDMA_BASE            (0xFFE04000)
-#define LPC_GPDMACH0_BASE         (0xFFE04100)
-#define LPC_GPDMACH1_BASE         (0xFFE04120)
-#define LPC_USB_BASE              (0xFFE0C000)
-#define LPC_VIC_BASE              (0xFFFFF000)
-
-/* GPIOs                                                                      */
-#define LPC_GPIO0_BASE            (0x3FFFC000)
-#define LPC_GPIO1_BASE            (0x3FFFC020)
-#define LPC_GPIO2_BASE            (0x3FFFC040)
-#define LPC_GPIO3_BASE            (0x3FFFC060)
-#define LPC_GPIO4_BASE            (0x3FFFC080)
-
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_SC                    ((       LPC_SC_TypeDef *)        LPC_SC_BASE)
-#define LPC_GPIO0                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO0_BASE)
-#define LPC_GPIO1                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO1_BASE)
-#define LPC_GPIO2                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO2_BASE)
-#define LPC_GPIO3                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO3_BASE)
-#define LPC_GPIO4                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO4_BASE)
-#define LPC_WDT                   ((      LPC_WDT_TypeDef *)       LPC_WDT_BASE)
-#define LPC_TIM0                  ((      LPC_TIM_TypeDef *)      LPC_TIM0_BASE)
-#define LPC_TIM1                  ((      LPC_TIM_TypeDef *)      LPC_TIM1_BASE)
-#define LPC_TIM2                  ((      LPC_TIM_TypeDef *)      LPC_TIM2_BASE)
-#define LPC_TIM3                  ((      LPC_TIM_TypeDef *)      LPC_TIM3_BASE)
-#define LPC_UART0                 ((     LPC_UART_TypeDef *)     LPC_UART0_BASE)
-#define LPC_UART1                 ((    LPC_UART1_TypeDef *)     LPC_UART1_BASE)
-#define LPC_UART2                 ((     LPC_UART_TypeDef *)     LPC_UART2_BASE)
-#define LPC_UART3                 ((     LPC_UART_TypeDef *)     LPC_UART3_BASE)
-#define LPC_PWM1                  ((      LPC_PWM_TypeDef *)      LPC_PWM1_BASE)
-#define LPC_I2C0                  ((      LPC_I2C_TypeDef *)      LPC_I2C0_BASE)
-#define LPC_I2C1                  ((      LPC_I2C_TypeDef *)      LPC_I2C1_BASE)
-#define LPC_I2C2                  ((      LPC_I2C_TypeDef *)      LPC_I2C2_BASE)
-#define LPC_I2S                   ((      LPC_I2S_TypeDef *)       LPC_I2S_BASE)
-#define LPC_SPI                   ((      LPC_SPI_TypeDef *)       LPC_SPI_BASE)
-#define LPC_RTC                   ((      LPC_RTC_TypeDef *)       LPC_RTC_BASE)
-#define LPC_GPIOINT               ((  LPC_GPIOINT_TypeDef *)   LPC_GPIOINT_BASE)
-#define LPC_PINCON                ((   LPC_PINCON_TypeDef *)    LPC_PINCON_BASE)
-#define LPC_SSP0                  ((      LPC_SSP_TypeDef *)      LPC_SSP0_BASE)
-#define LPC_SSP1                  ((      LPC_SSP_TypeDef *)      LPC_SSP1_BASE)
-#define LPC_ADC                   ((      LPC_ADC_TypeDef *)       LPC_ADC_BASE)
-#define LPC_DAC                   ((      LPC_DAC_TypeDef *)       LPC_DAC_BASE)
-#define LPC_CANAF_RAM             ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
-#define LPC_CANAF                 ((    LPC_CANAF_TypeDef *)     LPC_CANAF_BASE)
-#define LPC_CANCR                 ((    LPC_CANCR_TypeDef *)     LPC_CANCR_BASE)
-#define LPC_CAN1                  ((      LPC_CAN_TypeDef *)      LPC_CAN1_BASE)
-#define LPC_CAN2                  ((      LPC_CAN_TypeDef *)      LPC_CAN2_BASE)
-#define LPC_MCI                   ((      LPC_MCI_TypeDef *)       LPC_MCI_BASE)
-#define LPC_EMAC                  ((     LPC_EMAC_TypeDef *)      LPC_EMAC_BASE)
-#define LPC_GPDMA                 ((    LPC_GPDMA_TypeDef *)     LPC_GPDMA_BASE)
-#define LPC_GPDMACH0              ((  LPC_GPDMACH_TypeDef *)  LPC_GPDMACH0_BASE)
-#define LPC_GPDMACH1              ((  LPC_GPDMACH_TypeDef *)  LPC_GPDMACH1_BASE)
-#define LPC_USB                   ((      LPC_USB_TypeDef *)       LPC_USB_BASE)
-#define LPC_VIC                   ((      LPC_VIC_TypeDef *)       LPC_VIC_BASE)
-
-#ifdef __cplusplus
- }
-#endif 
-
-#endif  // __LPC23xx_H
-

--- a/vendor/NXP/LPC2368/cmsis/cmsis.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,13 +0,0 @@
-/* mbed Microcontroller Library - CMSIS
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * A generic CMSIS include header, pulling in LPC2368 specifics
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "LPC23xx.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/vendor/NXP/LPC2368/cmsis/cmsis_nvic.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,16 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic for LPC2368
- * Copyright (c) 2009 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-
-#include "cmsis_nvic.h"
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-    LPC_VIC->VectAddr[(int)IRQn] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    return LPC_VIC->VectAddr[(int)IRQn];
-}
-

--- a/vendor/NXP/LPC2368/cmsis/cmsis_nvic.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,23 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC2368/cmsis/core_arm7.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,44 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
- *
- * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
- * based on core_cm3.h, V1.20
- */
-
-#include <stdint.h>
-
-
-/* define compiler specific symbols */
-#if defined   ( __CC_ARM   )
-  #define __ASM            __asm           /*!< asm keyword for armcc           */
-  #define __INLINE         __inline        /*!< inline keyword for armcc        */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm            /*!< asm keyword for iarcc           */
-  #define __INLINE        inline           /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
-
-#elif defined (  __GNUC__  )
-  #define __ASM             __asm          /*!< asm keyword for gcc            */
-  #define __INLINE          inline         /*!< inline keyword for gcc         */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm           /*!< asm keyword for TASKING Compiler          */
-  #define __INLINE         inline          /*!< inline keyword for TASKING Compiler       */
-
-#endif
-
-#if defined ( __CC_ARM   )
-/**
- * @brief  Return the Main Stack Pointer (return current ARM7 stack)
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
-    return __current_sp();
-}
-#endif

--- a/vendor/NXP/LPC2368/cmsis/core_arm7.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,265 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
- *
- * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
- * based on core_cm3.h, V1.20
- */
-
-#ifndef __ARM7_CORE_H__
-#define __ARM7_CORE_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x20)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
-
-/**
- *  Lint configuration \n
- *  ----------------------- \n
- *
- *  The following Lint messages will be suppressed and not shown: \n
- *  \n
- *    --- Error 10: --- \n
- *    register uint32_t __regBasePri         __asm("basepri"); \n
- *    Error 10: Expecting ';' \n
- *     \n
- *    --- Error 530: --- \n
- *    return(__regBasePri); \n
- *    Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
- *     \n
- *    --- Error 550: --- \n
- *      __regBasePri = (basePri & 0x1ff); \n
- *    } \n
- *    Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
- *     \n
- *    --- Error 754: --- \n
- *    uint32_t RESERVED0[24]; \n
- *    Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
- *     \n
- *    --- Error 750: --- \n
- *    #define __CM3_CORE_H__ \n
- *    Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
- *     \n
- *    --- Error 528: --- \n
- *    static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- *    Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
- *     \n
- *    --- Error 751: --- \n
- *    } InterruptType_Type; \n
- *    Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
- * \n
- * \n
- *    Note:  To re-enable a Message, insert a space before 'lint' * \n
- *
- */
-
-/*lint -save */
-/*lint -e10  */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-#include <stdint.h>                           /* Include standard types */
-
-#if defined ( __CC_ARM   )
-/**
- * @brief  Return the Main Stack Pointer (current ARM7 stack)
- *
- * @param  none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-#endif
-
-
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
-  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
-#endif
-
-typedef struct
-{
-  uint32_t IRQStatus;
-  uint32_t FIQStatus;
-  uint32_t RawIntr;
-  uint32_t IntSelect;
-  uint32_t IntEnable;
-  uint32_t IntEnClr;
-  uint32_t SoftInt;
-  uint32_t SoftIntClr;
-  uint32_t Protection;
-  uint32_t SWPriorityMask;
-  uint32_t RESERVED0[54];
-  uint32_t VectAddr[32];
-  uint32_t RESERVED1[32];
-  uint32_t VectPriority[32];
-  uint32_t RESERVED2[800];
-  uint32_t Address;
-} NVIC_TypeDef;
-
-#define NVIC_BASE              (0xFFFFF000)
-#define NVIC                   ((      NVIC_TypeDef *)       NVIC_BASE)
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#ifdef __cplusplus
-#define     __I     volatile                  /*!< defines 'read only' permissions      */
-#else
-#define     __I     volatile const            /*!< defines 'read only' permissions      */
-#endif
-#define     __O     volatile                  /*!< defines 'write only' permissions     */
-#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
-
-
-
-
-
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler           */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler       */
-
-#endif
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq                __enable_fiq
-#define __disable_fault_irq               __disable_fiq
-
-#define __NOP                             __nop
-//#define __WFI                             __wfi
-//#define __WFE                             __wfe
-//#define __SEV                             __sev
-//#define __ISB()                           __isb(0)
-//#define __DSB()                           __dsb(0)
-//#define __DMB()                           __dmb(0)
-//#define __REV                             __rev
-//#define __RBIT                            __rbit
-#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
-#define __STREXB(value, ptr)              __strex(value, ptr)
-#define __STREXH(value, ptr)              __strex(value, ptr)
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-#define __disable_irq()         unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
-                                LPC_VIC->IntEnClr = 0xffffffff
-
-#define __enable_irq()          LPC_VIC->IntEnable = tmp_IntEnable
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-
-#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
-#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
-#define __NOP                                     __no_operation()          /*!< no operation intrinsic in IAR Compiler */ 
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-
-static __INLINE void __enable_irq() {
-    unsigned long temp;
-    __asm__ __volatile__("mrs %0, cpsr\n"
-                         "bic %0, %0, #0x80\n"
-                         "msr cpsr_c, %0"
-                         : "=r" (temp)
-                         :
-                         : "memory");
-}
-
-static __INLINE void __disable_irq() {
-    unsigned long old,temp;
-    __asm__ __volatile__("mrs %0, cpsr\n"
-                         "orr %1, %0, #0xc0\n"
-                         "msr cpsr_c, %1"
-                         : "=r" (old), "=r" (temp)
-                         :
-                         : "memory");
-    // return (old & 0x80) == 0;
-}
-
-static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/**
- * @brief  Enable Interrupt in NVIC Interrupt Controller
- *
- * @param  IRQn_Type IRQn specifies the interrupt number
- * @return none 
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->IntEnable = 1 << (uint32_t)IRQn;
-}
-
-
-/**
- * @brief  Disable the interrupt line for external interrupt specified
- * 
- * @param  IRQn_Type IRQn is the positive number of the external interrupt
- * @return none
- * 
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->IntEnClr = 1 << (uint32_t)IRQn;
-}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ARM7_CORE_H__ */
-
-/*lint -restore */

--- a/vendor/NXP/LPC2368/cmsis/system_LPC23xx.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,144 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
- *
- * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
- */
-
-#include <stdint.h>
-#include "LPC23xx.h"
-
-#define CLOCK_SETUP           1
-#define SCS_Val               0x00000020
-#define CLKSRCSEL_Val         0x00000001
-
-#define PLL0_SETUP            1
-#define PLL0CFG_Val           0x00000013
-#define CCLKCFG_Val           0x00000007
-#define USBCLKCFG_Val         0x00000009
-#define PCLKSEL0_Val          0x00000000
-#define PCLKSEL1_Val          0x00000000
-#define PCONP_Val             0x042887DE
-#define CLKOUTCFG_Val         0x00000000
-#define MAMCR_Val             0x00000001  // there is a bug in the MAM so it should never be fully enabled (only disabled or partially enabled)
-#define MAMTIM_Val            0x00000004
-
-/*----------------------------------------------------------------------------
-  DEFINES
- *----------------------------------------------------------------------------*/
-    
-#define XTAL        (12000000UL)        /* Oscillator frequency               */
-#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
-#define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */
-#define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
-
-/* F_cco0 = (2 * M * F_in) / N  */
-#define __M               (((PLL0CFG_Val      ) & 0x7FFF) + 1)
-#define __N               (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
-#define __FCCO(__F_IN)    ((2 * __M * __F_IN) / __N) 
-#define __CCLK_DIV        (((CCLKCFG_Val      ) & 0x00FF) + 1)
-
-/* Determine core clock frequency according to settings */
- #if (PLL0_SETUP)
-    #if   ((CLKSRCSEL_Val & 0x03) == 1)
-        #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
-    #elif ((CLKSRCSEL_Val & 0x03) == 2)
-        #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
-    #else 
-        #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
-    #endif
- #endif
-
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
-
-/*----------------------------------------------------------------------------
-  Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
-{
-  /* Determine clock frequency according to clock register values             */
-  if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
-    switch (LPC_SC->CLKSRCSEL & 0x03) {
-      case 0:                                /* Int. RC oscillator => PLL0    */
-      case 3:                                /* Reserved, default to Int. RC  */
-        SystemCoreClock = (IRC_OSC * 
-                          (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
-                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   /
-                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
-        break;
-      case 1:                                /* Main oscillator => PLL0       */
-        SystemCoreClock = (OSC_CLK * 
-                          (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
-                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   /
-                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
-        break;
-      case 2:                                /* RTC oscillator => PLL0        */
-        SystemCoreClock = (RTC_CLK * 
-                          (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
-                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   /
-                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
-        break;
-    }
-  } else {
-    switch (LPC_SC->CLKSRCSEL & 0x03) {
-      case 0:                                /* Int. RC oscillator => PLL0    */
-      case 3:                                /* Reserved, default to Int. RC  */
-        SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
-        break;
-      case 1:                                /* Main oscillator => PLL0       */
-        SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
-        break;
-      case 2:                                /* RTC oscillator => PLL0        */
-        SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
-        break;
-    }
-  }
-}
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemFrequency variable.
- */
-void SystemInit (void)
-{
-#if (CLOCK_SETUP)                       /* Clock Setup                        */
-  LPC_SC->SCS       = SCS_Val;
-  if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
-    while ((LPC_SC->SCS & (1 << 6)) == 0);  /* Wait for Oscillator to be ready    */
-  }
-
-  LPC_SC->CCLKCFG   = CCLKCFG_Val;          /* Setup Clock Divider                */
-
-#if (PLL0_SETUP)
-  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;        /* Select Clock Source for PLL0       */
-  LPC_SC->PLL0CFG   = PLL0CFG_Val;
-  LPC_SC->PLL0CON   = 0x01;                 /* PLL0 Enable                        */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-  while (!(LPC_SC->PLL0STAT & (1 << 26)));  /* Wait for PLOCK0                    */
-
-  LPC_SC->PLL0CON   = 0x03;                 /* PLL0 Enable & Connect              */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-#endif
-
-  LPC_SC->USBCLKCFG = USBCLKCFG_Val;        /* Setup USB Clock Divider            */
-#endif
-
-  LPC_SC->PCLKSEL0  = PCLKSEL0_Val;         /* Peripheral Clock Selection         */
-  LPC_SC->PCLKSEL1  = PCLKSEL1_Val;
-
-  LPC_SC->PCONP     = PCONP_Val;            /* Power Control for Peripherals      */
-    
-  // Setup MAM
-  LPC_SC->MAMTIM      = MAMTIM_Val;
-  LPC_SC->MAMCR       = MAMCR_Val;
-}

--- a/vendor/NXP/LPC2368/cmsis/system_LPC23xx.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,44 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
- *
- * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
- * based on cmsis system_LPC17xx.h 
- */
-
-#ifndef __SYSTEM_LPC23xx_H
-#define __SYSTEM_LPC23xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock 
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-
-#ifdef __cplusplus
-}
-#endif 
-
-#endif

--- a/vendor/NXP/LPC2368/cmsis/uARM/LPC2368.sct	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,24 +0,0 @@
-
-LR_IROM1 0x00000000 0x80000  {    ; load region size_region
-  ER_IROM1 0x00000000 0x80000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  RW_IRAM1 0x40000120 0x7EE0  {  ; RW data, inc space for realmonitor
-   .ANY (+RW +ZI)
-  }
-  RW_IRAM2 0x7FD00000 0x2000  {  ; RW data, USB RAM
-   .ANY (AHBSRAM0)
-  }
-  RW_IRAM3 0x7FE00000 0x4000  {  ; RW data, ETH RAM
-   .ANY (AHBSRAM1)
-  }
-  RW_IRAM4 0xE0038000 0x0800  {  ; RW data, CAN RAM
-   .ANY (CANRAM)
-  }
-  RW_IRAM5 0xE0084000 0x0800  {  ; RW data, RTC RAM
-   .ANY (RTCRAM)
-  }
-}
-

--- a/vendor/NXP/LPC2368/cmsis/uARM/sys.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * Setup a fixed single stack/heap memory model, 
- *  between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/vendor/NXP/LPC2368/cmsis/uARM/vector_functions.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,248 +0,0 @@
-;/* mbed Microcontroller Library - InterruptIn
-; * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
-; */
- 
-#line 1 "vector_functions.s"
-;
-;
-;
-
-#line 1 "vector_defns.h"
-
-
-
- 
-
-
-
- 
-
-#line 21 "vector_defns.h"
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#line 47 "vector_defns.h"
-
-
-#line 58 "vector_defns.h"
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#line 6 "vector_functions.s"
-
-
-        AREA    VECFUNCS, CODE, READONLY
-        ARM
-        PRESERVE8
-
-
-
-
-
-        EXPORT __mbed_fiq [WEAK]
-        EXPORT __mbed_undef [WEAK]
-        EXPORT __mbed_prefetch_abort [WEAK]
-        EXPORT __mbed_data_abort [WEAK]
-        EXPORT __mbed_irq [WEAK]
-        EXPORT __mbed_swi [WEAK]
-        EXPORT __mbed_dcc_irq [WEAK]
-        EXPORT __mbed_reset [WEAK]
-        IMPORT __mbed_init_realmonitor
-
-;
-;
-__mbed_fiq
-        B       __mbed_fiq
-
-;
-;
-__mbed_undef
-        LDR     PC, =0x7fffffa0
-
-;
-;
-__mbed_prefetch_abort
-        LDR     PC, =0x7fffffb0
-
-;
-;
-__mbed_data_abort
-        LDR     PC, =0x7fffffc0
-
-;
-;
-;
-;
-;
-;
-;
-;
-;
-__mbed_irq
-        ;
-        MSR     CPSR_c, #0x1F:OR:0x80:OR:0x40
-                
-        ;
-        STMDB   sp!, {r0-r3,r12,lr}    
-
-        ;
-        MOV	r0, #0xFFFFFF00
-        LDR	r0, [r0]	
-
-        ;
-        MOV     lr, pc       
-        BX      r0           
-			    				
-        ;
-        MOV	r0, #0xFFFFFF00
-        STR	r0, [r0]			;
-				
-        ;
-        LDMFD   sp!,{r0-r3,r12,lr}
-
-        ;
-        MSR     CPSR_c, #0x12:OR:0x80:OR:0x40
-
-        ;
-        SUBS    pc, lr, #4 
-
-;
-;
-;
-;
-__mbed_swi
-        ;
-        ;
-        STMFD   sp!, {a4, r4, ip, lr}
-
-        ;
-        LDR     r4, =0x40000040
-
-        ;
-        ;
-        LDR     a4, =0x00940000
-        LDR	PC, =0x7ffff820				
-
-;
-;
-;
-;
-__mbed_dcc_irq
-
-        ;
-			
-        ;
-        LDMFD    sp!,{r0-r3,r12,lr}
-
-        ;
-        MSR     CPSR_c, #0x12:OR:0x80:OR:0x40
-
-        ;
-				
-        ;
-        SUB     lr, lr, #4              ;
-        STMFD   sp!, {ip,lr}            ;
-			
-        ;
-        LDR     LR, =0xfffff000
-        STR     LR, [LR, #0xf00]
-			
-        ;
-        ;
-        ;
-        ;
-        LDR     PC, =0x7fffffe0			 
-
-;
-; __mbed_reset is called after reset
-; we setup the stacks and realmonitor, then call Reset_Handler like on M3
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                MOV     LR, PC       
-                BX      R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-__mbed_reset
-
-        ;
-
-        LDR     R0, =(0x40000000 + 0x8000)
-
-        ;
-        MSR     CPSR_c, #0x1B:OR:0x80:OR:0x40
-        MOV     SP, R0
-        SUB     R0, R0, #0x00000040
-
-        ;
-        MSR     CPSR_c, #0x17:OR:0x80:OR:0x40
-        MOV     SP, R0
-        SUB     R0, R0, #0x00000040
-
-        ;
-        MSR     CPSR_c, #0x11:OR:0x80:OR:0x40
-        MOV     SP, R0
-        SUB     R0, R0, #0x00000000
-
-        ;
-        MSR     CPSR_c, #0x12:OR:0x80:OR:0x40
-        MOV     SP, R0
-        SUB     R0, R0, #0x00000040
-
-        ;
-        MSR     CPSR_c, #0x13:OR:0x80:OR:0x40
-        MOV     SP, R0
-        SUB     R0, R0, #0x00000040
-
-        ;
-        MSR     CPSR_c, #0x10
-        MOV     SP, R0
-
-        ;
-        LDR     R0, =__mbed_init_realmonitor
-        MOV     LR, PC       
-        BX      R0           
-        
-        ;
-        LDR     R0, =Reset_Handler
-        BX      R0
-
-        
-        END

--- a/vendor/NXP/LPC2368/cmsis/uARM/vector_table.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,99 +0,0 @@
-;/* mbed Microcontroller Library - InterruptIn
-; * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
-; */
- 
-#line 1 "vector_table.s"
-;
-
-
- 
-
-#line 1 "vector_defns.h"
-
-
-
- 
-
-
-
- 
-
-#line 21 "vector_defns.h"
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#line 47 "vector_defns.h"
-
-
-#line 58 "vector_defns.h"
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-#line 7 "vector_table.s"
-        
-;
-
-
-        AREA    RESET, CODE, READONLY
-        ARM
-;        ENTRY
-        PRESERVE8
-
-
-
-
-
-;        EXPORT __main
-        IMPORT __mbed_reset
-        IMPORT __mbed_undef
-        IMPORT __mbed_swi
-        IMPORT __mbed_prefetch_abort
-        IMPORT __mbed_data_abort
-        IMPORT __mbed_irq
-        IMPORT __mbed_fiq
-
-;
-
- 
-;__main
-        LDR     PC, =__mbed_reset
-        LDR     PC, =__mbed_undef
-        LDR     PC, =__mbed_swi
-        LDR     PC, =__mbed_prefetch_abort
-        LDR     PC, =__mbed_data_abort
-        NOP     ;
-        LDR     PC, =__mbed_irq
-        LDR     PC, =__mbed_fiq
-        
-
-        END

--- a/vendor/NXP/LPC2368/cmsis/vector_defns.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/* mbed Microcontroller Library - Vectors 
- * Copyright (c) 2006-2009 ARM Limited. All rights reserved. 
- */
-
-#ifndef MBED_VECTOR_DEFNS_H
-#define MBED_VECTOR_DEFNS_H
- 
-// Assember Macros 
-#ifdef __ARMCC_VERSION
-#define EXPORT(x) EXPORT x
-#define WEAK_EXPORT(x) EXPORT x [WEAK]
-#define IMPORT(x) IMPORT x
-#define LABEL(x) x
-#else        
-#define EXPORT(x) .global x
-#define WEAK_EXPORT(x) .weak x
-#define IMPORT(x) .global x
-#define LABEL(x) x:        
-#endif
-
-// RealMonitor
-// Requires RAM (0x40000040-0x4000011F) to be allocated by the linker
-
-// RealMonitor entry points
-#define rm_init_entry 0x7fffff91
-#define rm_undef_handler 0x7fffffa0
-#define rm_prefetchabort_handler 0x7fffffb0
-#define rm_dataabort_handler 0x7fffffc0
-#define rm_irqhandler2 0x7fffffe0
-//#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64
-#define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40
-
-// Unofficial RealMonitor entry points and variables
-#define RM_MSG_SWI 0x00940000 
-#define StateP 0x40000040 
-
-// VIC register addresses
-#define VIC_Base 0xfffff000
-#define VICAddress_Offset 0xf00
-#define VICVectAddr2_Offset 0x108
-#define VICVectAddr3_Offset 0x10c
-#define VICIntEnClr_Offset 0x014
-#define VICIntEnClr    (*(volatile unsigned long *)(VIC_Base + 0x014))
-#define VICVectAddr2   (*(volatile unsigned long *)(VIC_Base + 0x108))
-#define VICVectAddr3   (*(volatile unsigned long *)(VIC_Base + 0x10C))
-
-// ARM Mode bits and Interrupt flags in PSRs
-#define Mode_USR 0x10
-#define Mode_FIQ 0x11
-#define Mode_IRQ 0x12
-#define Mode_SVC 0x13
-#define Mode_ABT 0x17
-#define Mode_UND 0x1B
-#define Mode_SYS 0x1F
-#define I_Bit 0x80    // when I bit is set, IRQ is disabled
-#define F_Bit 0x40    // when F bit is set, FIQ is disabled
-
-// MCU RAM
-#define LPC2368_RAM_ADDRESS 0x40000000	// RAM Base
-#define LPC2368_RAM_SIZE 0x8000		// 32KB 
-
-// ISR Stack Allocation
-#define UND_stack_size  0x00000040
-#define SVC_stack_size  0x00000040
-#define ABT_stack_size  0x00000040
-#define FIQ_stack_size  0x00000000
-#define IRQ_stack_size  0x00000040
-
-#define ISR_stack_size  (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size)
-
-// Full Descending Stack, so top-most stack points to just above the top of RAM
-#define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE)
-#define USR_STACK_TOP	  (LPC2368_STACK_TOP - ISR_stack_size)
-
-#endif

--- a/vendor/NXP/LPC2368/cmsis/vector_realmonitor.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,22 +0,0 @@
-/* mbed Microcontroller Library - RealMonitor
- * Copyright (c) 2006-2009 ARM Limited. All rights reserved. 
- */
-#include "vector_defns.h"
-
-extern void __mbed_dcc_irq(void);
-
-/* Function: __mbed_init_realmonitor
- * Setup the RealMonitor DCC Interrupt Handlers
- */
-void __mbed_init_realmonitor(void) __attribute__((weak));
-void __mbed_init_realmonitor() {
-    // Disable all interrupts
-    VICIntEnClr = 0xffffffff;
-  
-    // Set DCC interrupt vector addresses
-    VICVectAddr2 = (unsigned)&__mbed_dcc_irq;
-    VICVectAddr3 = (unsigned)&__mbed_dcc_irq;  
-
-    // Initialise RealMonitor
-    ((void (*)(void))rm_init_entry)();
-}

--- a/vendor/NXP/LPC2368/hal/PeripheralNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,80 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    UART_0 = (int)LPC_UART0_BASE,
-    UART_1 = (int)LPC_UART1_BASE,
-    UART_2 = (int)LPC_UART2_BASE,
-    UART_3 = (int)LPC_UART3_BASE
-} UARTName;
-
-typedef enum {
-    ADC0_0 = 0,
-    ADC0_1,
-    ADC0_2,
-    ADC0_3,
-    ADC0_4,
-    ADC0_5,
-    ADC0_6,
-    ADC0_7
-} ADCName;
-
-typedef enum {
-    DAC_0 = 0
-} DACName;
-
-typedef enum {
-    SPI_0 = (int)LPC_SSP0_BASE,
-    SPI_1 = (int)LPC_SSP1_BASE
-} SPIName;
-
-typedef enum {
-    I2C_0 = (int)LPC_I2C0_BASE,
-    I2C_1 = (int)LPC_I2C1_BASE,
-    I2C_2 = (int)LPC_I2C2_BASE
-} I2CName;
-
-typedef enum {
-    PWM_1 = 1,
-    PWM_2,
-    PWM_3,
-    PWM_4,
-    PWM_5,
-    PWM_6
-} PWMName;
-
-typedef enum {
-     CAN_1 = (int)LPC_CAN1_BASE,
-     CAN_2 = (int)LPC_CAN2_BASE
-} CANName;
-
-#define STDIO_UART_TX     USBTX
-#define STDIO_UART_RX     USBRX
-#define STDIO_UART        UART_0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC2368/hal/PinNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,103 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT  5
-
-typedef enum {
-    // LPC Pin Names
-    P0_0 = LPC_GPIO0_BASE,
-          P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
-    P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
-    P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
-    P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
-    P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
-
-    // mbed DIP Pin Names
-    p5 = P0_9,
-    p6 = P0_8,
-    p7 = P0_7,
-    p8 = P0_6,
-    p9 = P0_0,
-    p10 = P0_1,
-    p11 = P0_18,
-    p12 = P0_17,
-    p13 = P0_15,
-    p14 = P0_16,
-    p15 = P0_23,
-    p16 = P0_24,
-    p17 = P0_25,
-    p18 = P0_26,
-    p19 = P1_30,
-    p20 = P1_31,
-    p21 = P2_5,
-    p22 = P2_4,
-    p23 = P2_3,
-    p24 = P2_2,
-    p25 = P2_1,
-    p26 = P2_0,
-    p27 = P0_11,
-    p28 = P0_10,
-    p29 = P0_5,
-    p30 = P0_4,
-
-    // Other mbed Pin Names
-    LED1 = P1_18,
-    LED2 = P1_20,
-    LED3 = P1_21,
-    LED4 = P1_23,
-
-    USBTX = P0_2,
-    USBRX = P0_3,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
-    PullUp = 0,
-    PullDown = 3,
-    PullNone = 2,
-    OpenDrain = 4
-} PinMode;
-
-// version of PINCON_TypeDef using register arrays
-typedef struct {
-  __IO uint32_t PINSEL[11];
-       uint32_t RESERVED0[5];
-  __IO uint32_t PINMODE[10];
-} PINCONARRAY_TypeDef;
-
-#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC2368/hal/PortNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,34 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    Port0 = 0,
-    Port1 = 1,
-    Port2 = 2,
-    Port3 = 3,
-    Port4 = 4
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif

--- a/vendor/NXP/LPC2368/hal/analogin_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,125 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "analogin_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-#define ANALOGIN_MEDIAN_FILTER      1
-
-#define ADC_10BIT_RANGE             0x3FF
-#define ADC_12BIT_RANGE             0xFFF
-
-static inline int div_round_up(int x, int y) {
-  return (x + (y - 1)) / y;
-}
-
-static const PinMap PinMap_ADC[] = {
-    {P0_23, ADC0_0, 1},
-    {P0_24, ADC0_1, 1},
-    {P0_25, ADC0_2, 1},
-    {P0_26, ADC0_3, 1},
-    {P1_30, ADC0_4, 3},
-    {P1_31, ADC0_5, 3},
-    {NC,    NC,     0}
-};
-
-#define ADC_RANGE    ADC_10BIT_RANGE
-
-
-void analogin_init(analogin_t *obj, PinName pin) {
-    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
-    if (obj->adc == (uint32_t)NC) {
-        error("ADC pin mapping failed");
-    }
-    
-    // ensure power is turned on
-    LPC_SC->PCONP |= (1 << 12);
-    
-    // set PCLK of ADC to /1
-    LPC_SC->PCLKSEL0 &= ~(0x3 << 24);
-    LPC_SC->PCLKSEL0 |= (0x1 << 24);
-    uint32_t PCLK = SystemCoreClock;
-    
-    // calculate minimum clock divider
-    //  clkdiv = divider - 1
-    uint32_t MAX_ADC_CLK = 13000000;
-    uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
-    
-    // Set the generic software-controlled ADC settings
-    LPC_ADC->ADCR = (0 << 0)      // SEL: 0 = no channels selected
-                  | (clkdiv << 8) // CLKDIV: PCLK max ~= 25MHz, /25 to give safe 1MHz at fastest
-                  | (0 << 16)     // BURST: 0 = software control
-                  | (0 << 17)     // CLKS: not applicable
-                  | (1 << 21)     // PDN: 1 = operational
-                  | (0 << 24)     // START: 0 = no start
-                  | (0 << 27);    // EDGE: not applicable
-    
-    pinmap_pinout(pin, PinMap_ADC);
-}
-
-static inline uint32_t adc_read(analogin_t *obj) {
-    // Select the appropriate channel and start conversion
-    LPC_ADC->ADCR &= ~0xFF;
-    LPC_ADC->ADCR |= 1 << (int)obj->adc;
-    LPC_ADC->ADCR |= 1 << 24;
-    
-    // Repeatedly get the sample data until DONE bit
-    unsigned int data;
-    do {
-        data = LPC_ADC->ADGDR;
-    } while ((data & ((unsigned int)1 << 31)) == 0);
-    
-    // Stop conversion
-    LPC_ADC->ADCR &= ~(1 << 24);
-    
-    return (data >> 6) & ADC_RANGE; // 10 bit
-}
-
-static inline void order(uint32_t *a, uint32_t *b) {
-    if (*a > *b) {
-        uint32_t t = *a;
-        *a = *b;
-        *b = t;
-    }
-}
-
-static inline uint32_t adc_read_u32(analogin_t *obj) {
-    uint32_t value;
-#if ANALOGIN_MEDIAN_FILTER
-    uint32_t v1 = adc_read(obj);
-    uint32_t v2 = adc_read(obj);
-    uint32_t v3 = adc_read(obj);
-    order(&v1, &v2);
-    order(&v2, &v3);
-    order(&v1, &v2);
-    value = v2;
-#else
-    value = adc_read(obj);
-#endif
-    return value;
-}
-
-uint16_t analogin_read_u16(analogin_t *obj) {
-    uint32_t value = adc_read_u32(obj);
-    
-    return (value << 6) | ((value >> 4) & 0x003F); // 10 bit
-}
-
-float analogin_read(analogin_t *obj) {
-    uint32_t value = adc_read_u32(obj);
-    return (float)value * (1.0f / (float)ADC_RANGE);
-}

--- a/vendor/NXP/LPC2368/hal/analogout_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "analogout_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_DAC[] = {
-    {P0_26, DAC_0, 2},
-    {NC   , NC   , 0}
-};
-
-void analogout_init(dac_t *obj, PinName pin) {
-    obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
-    if (obj->dac == (uint32_t)NC) {
-        error("DAC pin mapping failed");
-    }
-    
-    // power is on by default, set DAC clk divider is /4
-    LPC_SC->PCLKSEL0 &= ~(0x3 << 22);
-    
-    // map out (must be done before accessing registers)
-    pinmap_pinout(pin, PinMap_DAC);
-    
-    analogout_write_u16(obj, 0);
-}
-
-void analogout_free(dac_t *obj) {}
-
-static inline void dac_write(int value) {
-    value &= 0x3FF; // 10-bit
-    
-    // Set the DAC output
-    LPC_DAC->DACR = (0 << 16)       // bias = 0
-                  | (value << 6);
-}
-
-static inline int dac_read() {
-    return (LPC_DAC->DACR >> 6) & 0x3FF;
-}
-
-void analogout_write(dac_t *obj, float value) {
-    if (value < 0.0f) {
-        dac_write(0);
-    } else if (value > 1.0f) {
-        dac_write(0x3FF);
-    } else {
-        dac_write(value * (float)0x3FF);
-    }
-}
-
-void analogout_write_u16(dac_t *obj, uint16_t value) {
-    dac_write(value >> 6); // 10-bit
-}
-
-float analogout_read(dac_t *obj) {
-    uint32_t value = dac_read();
-    return (float)value * (1.0f / (float)0x3FF);
-}
-
-uint16_t analogout_read_u16(dac_t *obj) {
-    uint32_t value = dac_read(); // 10-bit
-    return (value << 6) | ((value >> 4) & 0x003F);
-}

--- a/vendor/NXP/LPC2368/hal/can_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,297 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "can_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-#include <math.h>
-#include <string.h>
-
-/* Acceptance filter mode in AFMR register */
-#define ACCF_OFF                0x01
-#define ACCF_BYPASS             0x02
-#define ACCF_ON                 0x00
-#define ACCF_FULLCAN            0x04
-
-/* There are several bit timing calculators on the internet.
-http://www.port.de/engl/canprod/sv_req_form.html
-http://www.kvaser.com/can/index.htm
-*/
-
-static const PinMap PinMap_CAN_RD[] = {
-    {P0_0 , CAN_1, 1},
-    {P0_4 , CAN_2, 2},
-    {P0_21, CAN_1, 3},
-    {P2_7 , CAN_2, 1},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_CAN_TD[] = {
-    {P0_1 , CAN_1, 1},
-    {P0_5 , CAN_2, 2},
-    {P0_22, CAN_1, 3},
-    {P2_8 , CAN_2, 1},
-    {NC   , NC   , 0}
-};
-
-// Type definition to hold a CAN message
-struct CANMsg {
-    unsigned int  reserved1 : 16;
-    unsigned int  dlc       :  4; // Bits 16..19: DLC - Data Length Counter
-    unsigned int  reserved0 : 10;
-    unsigned int  rtr       :  1; // Bit 30: Set if this is a RTR message
-    unsigned int  type      :  1; // Bit 31: Set if this is a 29-bit ID message
-    unsigned int  id;             // CAN Message ID (11-bit or 29-bit)
-    unsigned char data[8];        // CAN Message Data Bytes 0-7
-};
-typedef struct CANMsg CANMsg;
-
-static uint32_t can_disable(can_t *obj) {
-    uint32_t sm = obj->dev->MOD;
-    obj->dev->MOD |= 1;
-    return sm;
-}
-
-static inline void can_enable(can_t *obj) {
-    if (obj->dev->MOD & 1) {
-        obj->dev->MOD &= ~(1);
-    }
-}
-
-static int can_pclk(can_t *obj) {
-    int value = 0;
-    switch ((int)obj->dev) {
-        case CAN_1: value = (LPC_SC->PCLKSEL0 & (0x3 << 26)) >> 26; break;
-        case CAN_2: value = (LPC_SC->PCLKSEL0 & (0x3 << 28)) >> 28; break;
-    }
-    
-    switch (value) {
-        case 1: return 1;
-        case 2: return 2;
-        case 3: return 6;
-        default: return 4;
-    }
-}
-
-// This table has the sampling points as close to 75% as possible. The first
-// value is TSEG1, the second TSEG2.
-static const int timing_pts[23][2] = {
-    {0x0, 0x0},      // 2,  50%
-    {0x1, 0x0},      // 3,  67%
-    {0x2, 0x0},      // 4,  75%
-    {0x3, 0x0},      // 5,  80%
-    {0x3, 0x1},      // 6,  67%
-    {0x4, 0x1},      // 7,  71%
-    {0x5, 0x1},      // 8,  75%
-    {0x6, 0x1},      // 9,  78%
-    {0x6, 0x2},      // 10, 70%
-    {0x7, 0x2},      // 11, 73%
-    {0x8, 0x2},      // 12, 75%
-    {0x9, 0x2},      // 13, 77%
-    {0x9, 0x3},      // 14, 71%
-    {0xA, 0x3},      // 15, 73%
-    {0xB, 0x3},      // 16, 75%
-    {0xC, 0x3},      // 17, 76%
-    {0xD, 0x3},      // 18, 78%
-    {0xD, 0x4},      // 19, 74%
-    {0xE, 0x4},      // 20, 75%
-    {0xF, 0x4},      // 21, 76%
-    {0xF, 0x5},      // 22, 73%
-    {0xF, 0x6},      // 23, 70%
-    {0xF, 0x7},      // 24, 67%
-};
-
-static unsigned int can_speed(unsigned int sclk, unsigned int pclk, unsigned int cclk, unsigned char psjw) {
-    uint32_t    btr;
-    uint16_t    brp = 0;
-    uint32_t    calcbit;
-    uint32_t    bitwidth;
-    int         hit = 0;
-    int         bits;
-    
-    bitwidth = sclk / (pclk * cclk);
-    
-    brp = bitwidth / 0x18;
-    while ((!hit) && (brp < bitwidth / 4)) {
-        brp++;
-        for (bits = 22; bits > 0; bits--) {
-            calcbit = (bits + 3) * (brp + 1);
-            if (calcbit == bitwidth) {
-                hit = 1;
-                break;
-            }
-        }
-    }
-    
-    if (hit) {
-        btr = ((timing_pts[bits][1] << 20) & 0x00700000)
-            | ((timing_pts[bits][0] << 16) & 0x000F0000)
-            | ((psjw                << 14) & 0x0000C000)
-            | ((brp                 <<  0) & 0x000003FF);
-    } else {
-        btr = 0xFFFFFFFF;
-    }
-    
-    return btr;
-}
-
-void can_init(can_t *obj, PinName rd, PinName td) {
-    CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
-    CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
-    obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
-    if ((int)obj->dev == NC) {
-        error("CAN pin mapping failed");
-    }
-    
-    switch ((int)obj->dev) {
-        case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
-        case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
-    }
-    
-    pinmap_pinout(rd, PinMap_CAN_RD);
-    pinmap_pinout(td, PinMap_CAN_TD);
-    
-    can_reset(obj);
-    obj->dev->IER = 0;             // Disable Interrupts
-    can_frequency(obj, 100000);
-    
-    LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
-}
-
-void can_free(can_t *obj) {
-    switch ((int)obj->dev) {
-        case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
-        case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
-    }
-}
-
-int can_frequency(can_t *obj, int f) {
-    int pclk = can_pclk(obj);
-    int btr = can_speed(SystemCoreClock, pclk, (unsigned int)f, 1);
-    
-    if (btr > 0) {
-        uint32_t modmask = can_disable(obj);
-        obj->dev->BTR = btr;
-        obj->dev->MOD = modmask;
-        return 1;
-    } else {
-        return 0;
-    }
-}
-
-int can_write(can_t *obj, CAN_Message msg, int cc) {
-    unsigned int CANStatus;
-    CANMsg m;
-    
-    can_enable(obj);
-    
-    m.id   = msg.id ;
-    m.dlc  = msg.len & 0xF;
-    m.rtr  = msg.type;
-    m.type = msg.format;
-    memcpy(m.data, msg.data, msg.len);
-    const unsigned int *buf = (const unsigned int *)&m;
-    
-    CANStatus = obj->dev->SR;
-    if (CANStatus & 0x00000004) {
-        obj->dev->TFI1 = buf[0] & 0xC00F0000;
-        obj->dev->TID1 = buf[1];
-        obj->dev->TDA1 = buf[2];
-        obj->dev->TDB1 = buf[3];
-        if (cc) {
-            obj->dev->CMR = 0x30;
-        } else {
-            obj->dev->CMR = 0x21;
-        }
-        return 1;
-    
-    } else if (CANStatus & 0x00000400) {
-        obj->dev->TFI2 = buf[0] & 0xC00F0000;
-        obj->dev->TID2 = buf[1];
-        obj->dev->TDA2 = buf[2];
-        obj->dev->TDB2 = buf[3];
-        if (cc) {
-            obj->dev->CMR = 0x50;
-        } else {
-            obj->dev->CMR = 0x41;
-        }
-        return 1;
-    
-    } else if (CANStatus & 0x00040000) {
-        obj->dev->TFI3 = buf[0] & 0xC00F0000;
-        obj->dev->TID3 = buf[1];
-        obj->dev->TDA3 = buf[2];
-        obj->dev->TDB3 = buf[3];
-        if (cc) {
-            obj->dev->CMR = 0x90;
-        } else {
-            obj->dev->CMR = 0x81;
-        }
-        return 1;
-    }
-    
-    return 0;
-}
-
-int can_read(can_t *obj, CAN_Message *msg) {
-    CANMsg x;
-    unsigned int *i = (unsigned int *)&x;
-    
-    can_enable(obj);
-    
-    if (obj->dev->GSR & 0x1) {
-        *i++ = obj->dev->RFS;  // Frame
-        *i++ = obj->dev->RID;  // ID
-        *i++ = obj->dev->RDA;  // Data A
-        *i++ = obj->dev->RDB;  // Data B
-        obj->dev->CMR = 0x04;  // release receive buffer
-        
-        msg->id     = x.id;
-        msg->len    = x.dlc;
-        msg->format = (x.type)? CANExtended : CANStandard;
-        msg->type   = (x.rtr)?  CANRemote:    CANData;
-        memcpy(msg->data,x.data,x.dlc);
-        return 1;
-    }
-    
-    return 0;
-}
-
-void can_reset(can_t *obj) {
-    can_disable(obj);
-    obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
-}
-
-unsigned char can_rderror(can_t *obj) {
-    return (obj->dev->GSR >> 16) & 0xFF;
-}
-
-unsigned char can_tderror(can_t *obj) {
-    return (obj->dev->GSR >> 24) & 0xFF;
-}
-
-void can_monitor(can_t *obj, int silent) {
-    uint32_t mod_mask = can_disable(obj);
-    if (silent) {
-        obj->dev->MOD |= (1 << 1);
-    } else {
-        obj->dev->MOD &= ~(1 << 1);
-    }
-    if (!(mod_mask & 1)) {
-        can_enable(obj);
-    }
-}

--- a/vendor/NXP/LPC2368/hal/device.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,59 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-#define DEVICE_PORTIN           1
-#define DEVICE_PORTOUT          1
-#define DEVICE_PORTINOUT        1
-
-#define DEVICE_INTERRUPTIN      1
-
-#define DEVICE_ANALOGIN         1
-#define DEVICE_ANALOGOUT        1
-
-#define DEVICE_SERIAL           1
-
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
-
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         1
-
-#define DEVICE_CAN              1
-
-#define DEVICE_RTC              1
-
-#define DEVICE_ETHERNET         1
-
-#define DEVICE_PWMOUT           1
-
-#define DEVICE_SEMIHOST         1
-#define DEVICE_LOCALFILESYSTEM  1
-#define DEVICE_ID_LENGTH       32
-#define DEVICE_MAC_OFFSET      20
-
-#define DEVICE_SLEEP            0
-
-#define DEVICE_DEBUG_AWARENESS  0
-
-#define DEVICE_STDIO_MESSAGES   1
-
-#define DEVICE_ERROR_PATTERN    1
-
-#include "objects.h"
-
-#endif

--- a/vendor/NXP/LPC2368/hal/ethernet_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,935 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <string.h>
-
-#include "ethernet_api.h"
-#include "cmsis.h"
-#include "mbed_interface.h"
-#include "toolchain.h"
-#include "error.h"
-
-#define NEW_LOGIC       0
-#define NEW_ETH_BUFFER  0
-
-#if NEW_ETH_BUFFER
-
-#define NUM_RX_FRAG         4           // Number of Rx Fragments (== packets)
-#define NUM_TX_FRAG         3           // Number of Tx Fragments (== packets)
-
-#define ETH_MAX_FLEN        1536         // Maximum Ethernet Frame Size
-#define ETH_FRAG_SIZE       ETH_MAX_FLEN // Packet Fragment size (same as packet length)
-
-#else
-
-// Memfree calculation:
-// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
-//                (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
-/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
-#define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */
-#define NUM_TX_FRAG         3           /* Num.of TX Fragments 3*1536= 4.6kB */
-//#define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
-
-//#define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
-#define ETH_FRAG_SIZE       0x300       /* Packet Fragment size 1536/2 Bytes   */
-#define ETH_MAX_FLEN        0x300       /* Max. Ethernet Frame Size          */
-
-const int ethernet_MTU_SIZE  = 0x300;
-
-#endif
-
-#define ETHERNET_ADDR_SIZE 6
-
-PACKED struct RX_DESC_TypeDef {                        /* RX Descriptor struct              */
-   unsigned int Packet;
-   unsigned int Ctrl;
-};
-typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
-
-PACKED struct RX_STAT_TypeDef {                        /* RX Status struct                  */
-   unsigned int Info;
-   unsigned int HashCRC;
-};
-typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
-
-PACKED struct TX_DESC_TypeDef {                        /* TX Descriptor struct              */
-   unsigned int Packet;
-   unsigned int Ctrl;
-};
-typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
-
-PACKED struct TX_STAT_TypeDef {                        /* TX Status struct                  */
-   unsigned int Info;
-};
-typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
-
-/* MAC Configuration Register 1 */
-#define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
-#define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
-#define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
-#define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
-#define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
-#define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
-#define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
-#define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
-#define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
-#define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
-#define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
-
-/* MAC Configuration Register 2 */
-#define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
-#define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
-#define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
-#define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
-#define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
-#define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
-#define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
-#define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
-#define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
-#define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
-#define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
-#define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
-#define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
-
-/* Back-to-Back Inter-Packet-Gap Register */
-#define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
-#define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
-
-/* Non Back-to-Back Inter-Packet-Gap Register */
-#define IPGR_DEF            0x00000012  /* Recommended value                 */
-
-/* Collision Window/Retry Register */
-#define CLRT_DEF            0x0000370F  /* Default value                     */
-
-/* PHY Support Register */
-#define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
-//#define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */
-#define SUPP_RES_RMII       0x00000000  /* Reset Reduced MII Logic           */
-
-/* Test Register */
-#define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
-#define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
-#define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
-
-/* MII Management Configuration Register */
-#define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
-#define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
-#define MCFG_CLK_SEL        0x0000003C  /* Clock Select Mask                 */
-#define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
-
-/* MII Management Command Register */
-#define MCMD_READ           0x00000001  /* MII Read                          */
-#define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
-
-#define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
-#define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
-
-/* MII Management Address Register */
-#define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
-#define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
-
-/* MII Management Indicators Register */
-#define MIND_BUSY           0x00000001  /* MII is Busy                       */
-#define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
-#define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
-#define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
-
-/* Command Register */
-#define CR_RX_EN            0x00000001  /* Enable Receive                    */
-#define CR_TX_EN            0x00000002  /* Enable Transmit                   */
-#define CR_REG_RES          0x00000008  /* Reset Host Registers              */
-#define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
-#define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
-#define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
-#define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
-#define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
-#define CR_RMII             0x00000200  /* Reduced MII Interface             */
-#define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
-
-/* Status Register */
-#define SR_RX_EN            0x00000001  /* Enable Receive                    */
-#define SR_TX_EN            0x00000002  /* Enable Transmit                   */
-
-/* Transmit Status Vector 0 Register */
-#define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
-#define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
-#define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
-#define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
-#define TSV0_MCAST          0x00000010  /* Multicast Destination             */
-#define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
-#define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
-#define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
-#define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
-#define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
-#define TSV0_GIANT          0x00000400  /* Giant Frame                       */
-#define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
-#define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
-#define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
-#define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
-#define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
-#define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
-
-/* Transmit Status Vector 1 Register */
-#define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
-#define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
-
-/* Receive Status Vector Register */
-#define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
-#define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
-#define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
-#define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
-#define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
-#define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
-#define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
-#define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
-#define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
-#define RSV_MCAST           0x01000000  /* Multicast Frame                   */
-#define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
-#define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
-#define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
-#define RSV_PAUSE           0x10000000  /* Pause Frame                       */
-#define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
-#define RSV_VLAN            0x40000000  /* VLAN Frame                        */
-
-/* Flow Control Counter Register */
-#define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
-#define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
-
-/* Flow Control Status Register */
-#define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
-
-/* Receive Filter Control Register */
-#define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
-#define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
-#define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
-#define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
-#define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
-#define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
-#define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
-#define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
-
-/* Receive Filter WoL Status/Clear Registers */
-#define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
-#define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
-#define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
-#define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
-#define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
-#define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
-#define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
-#define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
-
-/* Interrupt Status/Enable/Clear/Set Registers */
-#define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
-#define INT_RX_ERR          0x00000002  /* Receive Error                     */
-#define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
-#define INT_RX_DONE         0x00000008  /* Receive Done                      */
-#define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
-#define INT_TX_ERR          0x00000020  /* Transmit Error                    */
-#define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
-#define INT_TX_DONE         0x00000080  /* Transmit Done                     */
-#define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
-#define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
-
-/* Power Down Register */
-#define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
-
-/* RX Descriptor Control Word */
-#define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
-#define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
-
-/* RX Status Hash CRC Word */
-#define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
-#define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
-
-/* RX Status Information Word */
-#define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
-#define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
-#define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
-#define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
-#define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
-#define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
-#define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
-#define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
-#define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
-#define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
-#define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
-#define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
-#define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
-#define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
-#define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
-
-//#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
-#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
-                            RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
-
-
-/* TX Descriptor Control Word */
-#define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
-#define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
-#define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
-#define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
-#define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
-#define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
-#define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
-
-/* TX Status Information Word */
-#define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
-#define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
-#define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
-#define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
-#define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
-#define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
-#define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
-#define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
-
-/* ENET Device Revision ID */
-#define OLD_EMAC_MODULE_ID  0x39022000  /* Rev. ID for first rev '-'         */
-
-/* DP83848C PHY Registers */
-#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
-#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
-#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
-#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
-#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
-#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
-#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
-#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
-
-/* PHY Extended Registers */
-#define PHY_REG_STS         0x10        /* Status Register                   */
-#define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */
-#define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */
-#define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */
-#define PHY_REG_RECR        0x15        /* Receive Error Counter             */
-#define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */
-#define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */
-#define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */
-#define PHY_REG_PHYCR       0x19        /* PHY Control Register              */
-#define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */
-#define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */
-#define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */
-
-#define PHY_REG_SCSR        0x1F        /* PHY Special Control/Status Register */
-
-#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
-#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
-#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
-#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
-#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */
-
-#define DP83848C_DEF_ADR    0x0100      /* Default PHY device address        */
-#define DP83848C_ID         0x20005C90  /* PHY Identifier - DP83848C         */
-
-#define LAN8720_ID          0x0007C0F0  /* PHY Identifier - LAN8720          */
-
-#define PHY_STS_LINK        0x0001      /* PHY Status Link Mask              */
-#define PHY_STS_SPEED       0x0002      /* PHY Status Speed Mask             */
-#define PHY_STS_DUPLEX      0x0004      /* PHY Status Duplex Mask            */
-
-#define PHY_BMCR_RESET      0x8000      /* PHY Reset                         */
-
-#define PHY_BMSR_LINK       0x0004      /* PHY BMSR Link valid               */
-
-#define PHY_SCSR_100MBIT    0x0008      /* Speed: 1=100 MBit, 0=10Mbit       */
-#define PHY_SCSR_DUPLEX     0x0010      /* PHY Duplex Mask                   */
-
-
-static int phy_read(unsigned int PhyReg);
-static int phy_write(unsigned int PhyReg, unsigned short Data);
-
-static void txdscr_init(void);
-static void rxdscr_init(void);
-
-#if defined (__ICCARM__)
-#   define AHBSRAM1
-#elif defined(TOOLCHAIN_GCC_CR)
-#   define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
-#else
-#   define AHBSRAM1     __attribute__((section("AHBSRAM1"),aligned))
-#endif
-
-AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
-AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
-AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
-AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
-AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
-AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
-
-
-#if NEW_LOGIC
-static int rx_consume_offset = -1;
-static int tx_produce_offset = -1;
-#else
-static int send_doff =  0;
-static int send_idx  = -1;
-static int send_size =  0;
-
-static int receive_soff =  0;
-static int receive_idx  = -1;
-#endif
-
-static uint32_t phy_id = 0;
-
-static inline int rinc(int idx, int mod) {
-  ++idx;
-  idx %= mod;
-  return idx;
-}
-
-//extern unsigned int SystemFrequency;
-static inline unsigned int clockselect() {
-  if(SystemCoreClock < 10000000) {
-    return 1;
-  } else if(SystemCoreClock <  15000000) {
-    return 2;
-  } else if(SystemCoreClock <  20000000) {
-    return 3;
-  } else if(SystemCoreClock <  25000000) {
-    return 4;
-  } else if(SystemCoreClock <  35000000) {
-    return 5;
-  } else if(SystemCoreClock <  50000000) {
-    return 6;
-  } else if(SystemCoreClock <  70000000) {
-    return 7;
-  } else if(SystemCoreClock <  80000000) {
-    return 8;
-  } else if(SystemCoreClock <  90000000) {
-    return 9;
-  } else if(SystemCoreClock < 100000000) {
-    return 10;
-  } else if(SystemCoreClock < 120000000) {
-    return 11;
-  } else if(SystemCoreClock < 130000000) {
-    return 12;
-  } else if(SystemCoreClock < 140000000) {
-    return 13;
-  } else if(SystemCoreClock < 150000000) {
-    return 15;
-  } else if(SystemCoreClock < 160000000) {
-    return 16;
-  } else {
-    return 0;
-  }
-}
-
-#ifndef min
-#define min(x, y) (((x)<(y))?(x):(y))
-#endif
-
-/*----------------------------------------------------------------------------
-  Ethernet Device initialize
- *----------------------------------------------------------------------------*/
-int ethernet_init() {
-  int regv, tout;
-  char mac[ETHERNET_ADDR_SIZE];
-  unsigned int clock = clockselect();
-  
-  LPC_SC->PCONP |= 0x40000000;                       /* Power Up the EMAC controller. */
-  
-  LPC_PINCON->PINSEL2 = 0x50150105;                  /* Enable P1 Ethernet Pins. */
-  LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
-  
-   /* Reset all EMAC internal modules. */
-  LPC_EMAC->MAC1    = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
-                      MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
-  LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
-
-  for(tout = 100; tout; tout--) __NOP();             /* A short delay after reset. */
-
-  LPC_EMAC->MAC1 = MAC1_PASS_ALL;                    /* Initialize MAC control registers. */
-  LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
-  LPC_EMAC->MAXF = ETH_MAX_FLEN;
-  LPC_EMAC->CLRT = CLRT_DEF;
-  LPC_EMAC->IPGR = IPGR_DEF;
-
-  LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;    /* Enable Reduced MII interface. */
-
-  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;    /* Set clock */
-  LPC_EMAC->MCFG |= MCFG_RES_MII;                    /* and reset */
-
-  for(tout = 100; tout; tout--) __NOP();             /* A short delay */
-
-  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
-  LPC_EMAC->MCMD = 0;
-
-  LPC_EMAC->SUPP = SUPP_RES_RMII;                    /* Reset Reduced MII Logic. */
-
-  for (tout = 100; tout; tout--) __NOP();            /* A short delay */
-
-  LPC_EMAC->SUPP = 0;
-
-  phy_write(PHY_REG_BMCR, PHY_BMCR_RESET);           /* perform PHY reset */
-  for(tout = 0x20000; ; tout--) {                    /* Wait for hardware reset to end. */
-    regv = phy_read(PHY_REG_BMCR);
-    if(regv < 0 || tout == 0) {
-       return -1;                                    /* Error */
-    }
-    if(!(regv & PHY_BMCR_RESET)) {
-       break;                                        /* Reset complete. */
-    }
-  }
-
-  phy_id =  (phy_read(PHY_REG_IDR1) << 16);
-  phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
-
-  if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
-      error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
-  }
-
-  ethernet_set_link(-1, 0);
-
-  /* Set the Ethernet MAC Address registers */
-  ethernet_address(mac);
-  LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
-  LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
-  LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
-
-  txdscr_init();                                      /* initialize DMA TX Descriptor */
-  rxdscr_init();                                      /* initialize DMA RX Descriptor */
-
-  LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
-                                                      /* Receive Broadcast, Perfect Match Packets */
-
-  LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;    /* Enable EMAC interrupts. */
-  LPC_EMAC->IntClear  = 0xFFFF;                       /* Reset all interrupts */
-
-
-  LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);        /* Enable receive and transmit mode of MAC Ethernet core */
-  LPC_EMAC->MAC1     |= MAC1_REC_EN;
-
-#if NEW_LOGIC
-  rx_consume_offset = -1;
-  tx_produce_offset = -1;
-#else
-  send_doff =  0;
-  send_idx  = -1;
-  send_size =  0;
-
-  receive_soff =  0;
-  receive_idx  = -1;
-#endif
-
-  return 0;
-}
-
-/*----------------------------------------------------------------------------
-  Ethernet Device Uninitialize
- *----------------------------------------------------------------------------*/
-void ethernet_free() {
-  LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
-  LPC_EMAC->IntClear   =  0xFFFF;
-  
-  LPC_SC->PCONP   &= ~0x40000000;       /* Power down the EMAC controller. */
-  
-  LPC_PINCON->PINSEL2 &= ~0x50150105;   /* Disable P1 ethernet pins. */
-  LPC_PINCON->PINSEL3  = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000000;
-}
-
-// if(TxProduceIndex == TxConsumeIndex) buffer array is empty
-// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
-// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
-// TxConsumeIndex - The buffer that will/is beign sent by hardware
-
-int ethernet_write(const char *data, int slen) {
-
-#if NEW_LOGIC
-
-   if(tx_produce_offset < 0) { // mark as active if not already
-     tx_produce_offset = 0;
-   }
-
-   int index = LPC_EMAC->TxProduceIndex;
-
-   int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
-   int requested = slen;
-   int ncopy = min(remaining, requested);
-
-   void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
-   void *psrc = (void *)(data);
-
-   if(ncopy > 0 ){
-     if(data != NULL) {
-       memcpy(pdst, psrc, ncopy);
-     } else {
-       memset(pdst, 0, ncopy);
-     }
-   }
-
-   tx_produce_offset += ncopy;
-
-   return ncopy;
-
-#else
-    void       *pdst, *psrc;
-    const int   dlen = ETH_FRAG_SIZE;
-    int         copy = 0;
-    int         soff = 0;
-
-    if(send_idx == -1) {
-        send_idx = LPC_EMAC->TxProduceIndex;
-    }
-
-    if(slen + send_doff > ethernet_MTU_SIZE) {
-       return -1;
-    }
-
-    do {
-        copy = min(slen - soff, dlen - send_doff);
-        pdst = (void *)(txdesc[send_idx].Packet + send_doff);
-        psrc = (void *)(data + soff);
-        if(send_doff + copy > ETH_FRAG_SIZE) {
-            txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
-            send_idx = rinc(send_idx, NUM_TX_FRAG);
-            send_doff = 0;
-        }
-
-        if(data != NULL) {
-            memcpy(pdst, psrc, copy);
-        } else {
-            memset(pdst, 0, copy);
-        }
-
-        soff += copy;
-        send_doff += copy;
-        send_size += copy;
-    } while(soff != slen);
-
-    return soff;
-#endif
-}
-
-int ethernet_send() {
-
-#if NEW_LOGIC
-  if(tx_produce_offset < 0) { // no buffer active
-    return -1;
-  }
-
-  // ensure there is a link
-  if(!ethernet_link()) {
-    return -2;
-  }
-
-  // we have been writing in to a buffer, so finalise it
-  int size = tx_produce_offset;
-  int index = LPC_EMAC->TxProduceIndex;
-  txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
-
-  // Increment ProduceIndex to allow it to be sent
-  // We can only do this if the next slot is free
-  int next = rinc(index, NUM_TX_FRAG);
-  while(next == LPC_EMAC->TxConsumeIndex) {
-    for(int i=0; i<1000; i++) { __NOP(); }
-  }
-
-  LPC_EMAC->TxProduceIndex = next;
-  tx_produce_offset = -1;
-  return size;
-
-#else
-    int s = send_size;
-    txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
-    send_idx  = rinc(send_idx, NUM_TX_FRAG);
-    LPC_EMAC->TxProduceIndex = send_idx;
-    send_doff =  0;
-    send_idx  = -1;
-    send_size =  0;
-    return s;
-#endif
-}
-
-// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
-// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
-//
-// if(RxConsumeIndex == RxProduceIndex) buffer array is empty
-// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
-
-// Recevies an arrived ethernet packet.
-// Receiving an ethernet packet will drop the last received ethernet packet
-// and make a new ethernet packet ready to read.
-// Returns size of packet, else 0 if nothing to receive
-
-// We read from RxConsumeIndex from position rx_consume_offset
-// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
-// rx_consume_offset = -1 // no frame
-// rx_consume_offset = 0  // start of frame
-// Assumption: A fragment should alway be a whole frame
-
-int ethernet_receive() {
-#if NEW_LOGIC
-
-  // if we are currently reading a valid RxConsume buffer, increment to the next one
-  if(rx_consume_offset >= 0) {
-    LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
-  }
-
-  // if the buffer is empty, mark it as no valid buffer
-  if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
-    rx_consume_offset = -1;
-    return 0;
-  }
-
-  uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
-  rx_consume_offset = 0;
-
-  // check if it is not marked as last or for errors
-  if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
-    return -1;
-  }
-
-  int size = (info & RINFO_SIZE) + 1;
-  return size - 4; // don't include checksum bytes
-
-#else
-    if(receive_idx == -1) {
-      receive_idx = LPC_EMAC->RxConsumeIndex;
-    } else {
-        while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && (receive_idx != LPC_EMAC->RxProduceIndex)) {
-            receive_idx  = rinc(receive_idx, NUM_RX_FRAG);
-        }
-        unsigned int info =   rxstat[receive_idx].Info;
-        int slen =  (info & RINFO_SIZE) + 1;
-
-        if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
-            /* Invalid frame, ignore it and free buffer. */
-            receive_idx = rinc(receive_idx, NUM_RX_FRAG);
-        }
-        receive_idx = rinc(receive_idx, NUM_RX_FRAG);
-        receive_soff = 0;
-        
-        LPC_EMAC->RxConsumeIndex = receive_idx;
-    }
-    
-    if(receive_idx == LPC_EMAC->RxProduceIndex) {
-        receive_idx = -1;
-        return 0;
-    }
-    
-    return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
-#endif
-}
-
-// Read from an recevied ethernet packet.
-// After receive returnd a number bigger than 0 it is
-// possible to read bytes from this packet.
-// Read will write up to size bytes into data.
-// It is possible to use read multible times.
-// Each time read will start reading after the last read byte before.
-
-int ethernet_read(char *data, int dlen) {
-#if NEW_LOGIC
-  // Check we have a valid buffer to read
-  if(rx_consume_offset < 0) {
-    return 0;
-  }
-
-  // Assume 1 fragment block
-  uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
-  int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
-
-  int remaining = size - rx_consume_offset;
-  int requested = dlen;
-  int ncopy = min(remaining, requested);
-
-  void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
-  void *pdst = (void *)(data);
-
-  if(data != NULL && ncopy > 0) {
-    memcpy(pdst, psrc, ncopy);
-  }
-
-  rx_consume_offset += ncopy;
-
-  return ncopy;
-#else
-    int          slen;
-    int          copy   = 0;
-    unsigned int more;
-    unsigned int info;
-    void        *pdst, *psrc;
-    int          doff = 0;
-    
-    if(receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
-        return 0;
-    }
-    
-    do {
-        info =   rxstat[receive_idx].Info;
-        more = !(info & RINFO_LAST_FLAG);
-        slen =  (info & RINFO_SIZE) + 1;
-        
-        if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
-            /* Invalid frame, ignore it and free buffer. */
-            receive_idx = rinc(receive_idx, NUM_RX_FRAG);
-        } else {
-            
-            copy = min(slen - receive_soff, dlen - doff);
-            psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
-            pdst = (void *)(data + doff);
-            
-            if(data != NULL) {
-                /* check if Buffer available */
-                memcpy(pdst, psrc, copy);
-            }
-            
-            receive_soff += copy;
-            doff += copy;
-            
-            if((more && (receive_soff == slen))) {
-                receive_idx = rinc(receive_idx, NUM_RX_FRAG);
-                receive_soff = 0;
-            }
-        }
-    } while(more && !(doff == dlen) && !receive_soff);
-    
-    return doff;
-#endif
-}
-
-int ethernet_link(void) {
-    if (phy_id == DP83848C_ID) {
-      return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
-    }
-    else { // LAN8720_ID
-      return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
-    }
-}
-
-static int phy_write(unsigned int PhyReg, unsigned short Data) {
-    unsigned int timeOut;
-    
-    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-    LPC_EMAC->MWTD = Data;
-    
-    for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) {     /* Wait until operation completed */
-        if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
-            return 0;
-        }
-    }
-    
-    return -1;
-}
-
-static int phy_read(unsigned int PhyReg) {
-    unsigned int timeOut;
-    
-    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-    LPC_EMAC->MCMD = MCMD_READ;
-    
-    for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) {     /* Wait until operation completed */
-        if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
-            LPC_EMAC->MCMD = 0;
-            return LPC_EMAC->MRDD;                           /* Return a 16-bit value. */
-        }
-    }
-    
-    return -1;
-}
-
-
-static void txdscr_init() {
-    int i;
-    
-    for(i = 0; i < NUM_TX_FRAG; i++) {
-        txdesc[i].Packet = (uint32_t)&txbuf[i];
-        txdesc[i].Ctrl   = 0;
-        txstat[i].Info   = 0;
-    }
-    
-    LPC_EMAC->TxDescriptor       = (uint32_t)txdesc;         /* Set EMAC Transmit Descriptor Registers. */
-    LPC_EMAC->TxStatus           = (uint32_t)txstat;
-    LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
-    
-    LPC_EMAC->TxProduceIndex  = 0;                           /* Tx Descriptors Point to 0 */
-}
-
-static void rxdscr_init() {
-    int i;
-    
-    for(i = 0; i < NUM_RX_FRAG; i++) {
-        rxdesc[i].Packet  = (uint32_t)&rxbuf[i];
-        rxdesc[i].Ctrl    = RCTRL_INT | (ETH_FRAG_SIZE-1);
-        rxstat[i].Info    = 0;
-        rxstat[i].HashCRC = 0;
-    }
-    
-    LPC_EMAC->RxDescriptor       = (uint32_t)rxdesc;        /* Set EMAC Receive Descriptor Registers. */
-    LPC_EMAC->RxStatus           = (uint32_t)rxstat;
-    LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
-    
-    LPC_EMAC->RxConsumeIndex  = 0;                          /* Rx Descriptors Point to 0 */
-}
-
-void ethernet_address(char *mac) {
-    mbed_mac_address(mac);
-}
-
-void ethernet_set_link(int speed, int duplex) {
-    unsigned short phy_data;
-    int tout;
-    
-    if((speed < 0) || (speed > 1)) {
-        phy_data = PHY_AUTO_NEG;
-    } else {
-        phy_data = (((unsigned short) speed << 13) |
-                    ((unsigned short) duplex << 8));
-    }
-    
-    phy_write(PHY_REG_BMCR, phy_data);
-    
-    for(tout = 100; tout; tout--) { __NOP(); }     /* A short delay */
-    
-    switch(phy_id) {
-        case DP83848C_ID:
-            phy_data = phy_read(PHY_REG_STS);
-            
-            if(phy_data & PHY_STS_DUPLEX) {
-                LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
-                LPC_EMAC->Command |= CR_FULL_DUP;
-                LPC_EMAC->IPGT = IPGT_FULL_DUP;
-            } else {
-            LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
-                LPC_EMAC->Command &= ~CR_FULL_DUP;
-                LPC_EMAC->IPGT = IPGT_HALF_DUP;
-            }
-            
-            if(phy_data & PHY_STS_SPEED) {
-                LPC_EMAC->SUPP &= ~SUPP_SPEED;
-            } else {
-                LPC_EMAC->SUPP |= SUPP_SPEED;
-            }
-            break;
-        
-        case LAN8720_ID:
-            phy_data = phy_read(PHY_REG_SCSR);
-            
-            if (phy_data & PHY_SCSR_DUPLEX) {
-                LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
-                LPC_EMAC->Command |= CR_FULL_DUP;
-                LPC_EMAC->IPGT = IPGT_FULL_DUP;
-            } else {
-                LPC_EMAC->Command &= ~CR_FULL_DUP;
-                LPC_EMAC->IPGT = IPGT_HALF_DUP;
-            }
-            
-            if(phy_data & PHY_SCSR_100MBIT) {
-                LPC_EMAC->SUPP |= SUPP_SPEED;
-            } else {
-                LPC_EMAC->SUPP &= ~SUPP_SPEED;
-            }
-            break;
-    }
-}

--- a/vendor/NXP/LPC2368/hal/gpio_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "gpio_api.h"
-#include "pinmap.h"
-
-uint32_t gpio_set(PinName pin) {
-    LPC_SC->SCS |= 1; // High speed GPIO is enabled on ports 0 and 1
-    
-    pin_function(pin, 0);
-    
-    return (1 << ((int)pin & 0x1F));
-}
-
-void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
-    if (pin == NC) return;
-    
-    obj->pin = pin;
-    obj->mask = gpio_set(pin);
-    
-    LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *) ((int)pin & ~0x1F);
-    
-    obj->reg_set = &port_reg->FIOSET;
-    obj->reg_clr = &port_reg->FIOCLR;
-    obj->reg_in  = &port_reg->FIOPIN;
-    obj->reg_dir = &port_reg->FIODIR;
-    
-    gpio_dir(obj, direction);
-    switch (direction) {
-        case PIN_OUTPUT: pin_mode(pin, PullNone); break;
-        case PIN_INPUT : pin_mode(pin, PullDown); break;
-    }
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode) {
-    pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction) {
-    switch (direction) {
-        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
-        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
-    }
-}

--- a/vendor/NXP/LPC2368/hal/gpio_irq_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,145 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "gpio_irq_api.h"
-#include "error.h"
-#include <stddef.h>
-#include "cmsis.h"
-
-#define CHANNEL_NUM     48
-
-static uint32_t channel_ids[CHANNEL_NUM] = {0};
-static gpio_irq_handler irq_handler;
-
-static void handle_interrupt_in(void) {
-    // Read in all current interrupt registers. We do this once as the
-    // GPIO interrupt registers are on the APB bus, and this is slow.
-    uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
-    uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
-    uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
-    uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
-    uint32_t mask0 = 0;
-    uint32_t mask2 = 0;
-    int i;
-    
-    // P0.0-0.31
-    for (i = 0; i < 32; i++) {
-        uint32_t pmask = (1 << i);
-        if (rise0 & pmask) {
-            mask0 |= pmask;
-            if (channel_ids[i] != 0)
-                irq_handler(channel_ids[i], IRQ_RISE);
-        }
-        if (fall0 & pmask) {
-            mask0 |= pmask;
-            if (channel_ids[i] != 0)
-                irq_handler(channel_ids[i], IRQ_FALL);
-        }
-    }
-    
-    // P2.0-2.15
-    for (i = 0; i < 16; i++) {
-        uint32_t pmask = (1 << i);
-        int channel_index = i + 32;
-        if (rise2 & pmask) {
-            mask2 |= pmask;
-            if (channel_ids[channel_index] != 0)
-                irq_handler(channel_ids[channel_index], IRQ_RISE);
-        }
-        if (fall2 & pmask) {
-            mask2 |= pmask;
-            if (channel_ids[channel_index] != 0)
-                irq_handler(channel_ids[channel_index], IRQ_FALL);
-        }
-    }
-    
-    // Clear the interrupts we just handled
-    LPC_GPIOINT->IO0IntClr = mask0;
-    LPC_GPIOINT->IO2IntClr = mask2;
-}
-
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
-    if (pin == NC) return -1;
-    
-    irq_handler = handler;
-    
-    obj->port = (int)pin & ~0x1F;
-    obj->pin = (int)pin & 0x1F;
-    
-    // Interrupts available only on GPIO0 and GPIO2
-    if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
-        error("pins on this port cannot generate interrupts\n");
-    }
-    
-    // put us in the interrupt table
-    int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
-    channel_ids[index] = id;
-    obj->ch = index;
-    
-    NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
-    NVIC_EnableIRQ(EINT3_IRQn);
-    
-    return 0;
-}
-
-void gpio_irq_free(gpio_irq_t *obj) {
-    channel_ids[obj->ch] = 0;
-}
-
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
-    // ensure nothing is pending
-    switch (obj->port) {
-         case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
-         case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
-    }
-    
-    // enable the pin interrupt
-    if (event == IRQ_RISE) {
-        switch (obj->port) {
-            case LPC_GPIO0_BASE:
-                if (enable) {
-                    LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
-                } else {
-                    LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
-                }
-                break;
-            case LPC_GPIO2_BASE:
-                if (enable) {
-                    LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
-                } else {
-                    LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
-                }
-                break;
-        }
-    } else {
-        switch (obj->port) {
-            case LPC_GPIO0_BASE:
-                if (enable) {
-                    LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
-                } else {
-                    LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
-                }
-                break;
-            
-            case LPC_GPIO2_BASE:
-                if (enable) {
-                    LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
-                } else {
-                    LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
-                }
-                break;
-        }
-    }
-}

--- a/vendor/NXP/LPC2368/hal/gpio_object.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    PinName  pin;
-    uint32_t mask;
-
-    __IO uint32_t *reg_dir;
-    __IO uint32_t *reg_set;
-    __IO uint32_t *reg_clr;
-    __I  uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
-    if (value)
-        *obj->reg_set = obj->mask;
-    else
-        *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
-    return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC2368/hal/i2c_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,390 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "i2c_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_I2C_SDA[] = {
-    {P0_0 , I2C_1, 3},
-    {P0_10, I2C_2, 2},
-    {P0_19, I2C_1, 3},
-    {P0_27, I2C_0, 1},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_I2C_SCL[] = {
-    {P0_1 , I2C_1, 3},
-    {P0_11, I2C_2, 2},
-    {P0_20, I2C_1, 3},
-    {P0_28, I2C_0, 1},
-    {NC   , NC,    0}
-};
-
-#define I2C_CONSET(x)       (x->i2c->I2CONSET)
-#define I2C_CONCLR(x)       (x->i2c->I2CONCLR)
-#define I2C_STAT(x)         (x->i2c->I2STAT)
-#define I2C_DAT(x)          (x->i2c->I2DAT)
-#define I2C_SCLL(x, val)    (x->i2c->I2SCLL = val)
-#define I2C_SCLH(x, val)    (x->i2c->I2SCLH = val)
-
-static const uint32_t I2C_addr_offset[2][4] = {
-    {0x0C, 0x20, 0x24, 0x28},
-    {0x30, 0x34, 0x38, 0x3C}
-};
-
-static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
-    I2C_CONCLR(obj) = (start << 5)
-                    | (stop << 4)
-                    | (interrupt << 3)
-                    | (acknowledge << 2);
-}
-
-static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
-    I2C_CONSET(obj) = (start << 5)
-                    | (stop << 4)
-                    | (interrupt << 3)
-                    | (acknowledge << 2);
-}
-
-// Clear the Serial Interrupt (SI)
-static inline void i2c_clear_SI(i2c_t *obj) {
-    i2c_conclr(obj, 0, 0, 1, 0);
-}
-
-static inline int i2c_status(i2c_t *obj) {
-    return I2C_STAT(obj);
-}
-
-// Wait until the Serial Interrupt (SI) is set
-static int i2c_wait_SI(i2c_t *obj) {
-    int timeout = 0;
-    while (!(I2C_CONSET(obj) & (1 << 3))) {
-        timeout++;
-        if (timeout > 100000) return -1;
-    }
-    return 0;
-}
-
-static inline void i2c_interface_enable(i2c_t *obj) {
-    I2C_CONSET(obj) = 0x40;
-}
-
-static inline void i2c_power_enable(i2c_t *obj) {
-    switch ((int)obj->i2c) {
-        case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
-        case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
-        case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
-    }
-}
-
-void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
-    // determine the SPI to use
-    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
-    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
-    obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
-    
-    if ((int)obj->i2c == NC) {
-        error("I2C pin mapping failed");
-    }
-    
-    // enable power
-    i2c_power_enable(obj);
-    
-    // set default frequency at 100k
-    i2c_frequency(obj, 100000);
-    i2c_conclr(obj, 1, 1, 1, 1);
-    i2c_interface_enable(obj);
-    
-    pinmap_pinout(sda, PinMap_I2C_SDA);
-    pinmap_pinout(scl, PinMap_I2C_SCL);
-}
-
-inline int i2c_start(i2c_t *obj) {
-    int status = 0;
-    // 8.1 Before master mode can be entered, I2CON must be initialised to:
-    //  - I2EN STA STO SI AA - -
-    //  -  1    0   0   0  x - -
-    // if AA = 0, it can't enter slave mode
-    i2c_conclr(obj, 1, 1, 1, 1);
-    
-    // The master mode may now be entered by setting the STA bit
-    // this will generate a start condition when the bus becomes free
-    i2c_conset(obj, 1, 0, 0, 1);
-    
-    i2c_wait_SI(obj);
-    status = i2c_status(obj);
-    
-    // Clear start bit now transmitted, and interrupt bit
-    i2c_conclr(obj, 1, 0, 0, 0);
-    return status;
-}
-
-inline void i2c_stop(i2c_t *obj) {
-    // write the stop bit
-    i2c_conset(obj, 0, 1, 0, 0);
-    i2c_clear_SI(obj);
-    
-    // wait for STO bit to reset
-    while (I2C_CONSET(obj) & (1 << 4));
-}
-
-static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
-    // write the data
-    I2C_DAT(obj) = value;
-    
-    // clear SI to init a send
-    i2c_clear_SI(obj);
-    
-    // wait and return status
-    i2c_wait_SI(obj);
-    return i2c_status(obj);
-}
-
-static inline int i2c_do_read(i2c_t *obj, int last) {
-    // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
-    if (last) {
-        i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
-    } else {
-        i2c_conset(obj, 0, 0, 0, 1); // send a ACK
-    }
-    
-    // accept byte
-    i2c_clear_SI(obj);
-    
-    // wait for it to arrive
-    i2c_wait_SI(obj);
-    
-    // return the data
-    return (I2C_DAT(obj) & 0xFF);
-}
-
-void i2c_frequency(i2c_t *obj, int hz) {
-    // [TODO] set pclk to /4
-    uint32_t PCLK = SystemCoreClock / 4;
-    
-    uint32_t pulse = PCLK / (hz * 2);
-    
-    // I2C Rate
-    I2C_SCLL(obj, pulse);
-    I2C_SCLH(obj, pulse);
-}
-
-// The I2C does a read or a write as a whole operation
-// There are two types of error conditions it can encounter
-//  1) it can not obtain the bus
-//  2) it gets error responses at part of the transmission
-//
-// We tackle them as follows:
-//  1) we retry until we get the bus. we could have a "timeout" if we can not get it
-//      which basically turns it in to a 2)
-//  2) on error, we use the standard error mechanisms to report/debug
-//
-// Therefore an I2C transaction should always complete. If it doesn't it is usually
-// because something is setup wrong (e.g. wiring), and we don't need to programatically
-// check for that
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
-    int count, status;
-    
-    status = i2c_start(obj);
-    
-    if ((status != 0x10) && (status != 0x08)) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    status = i2c_do_write(obj, (address | 0x01), 1);
-    if (status != 0x40) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    // Read in all except last byte
-    for (count = 0; count < (length - 1); count++) {
-        int value = i2c_do_read(obj, 0);
-        status = i2c_status(obj);
-        if (status != 0x50) {
-            i2c_stop(obj);
-            return status;
-        }
-        data[count] = (char) value;
-    }
-    
-    // read in last byte
-    int value = i2c_do_read(obj, 1);
-    status = i2c_status(obj);
-    if (status != 0x58) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    data[count] = (char) value;
-    
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-    }
-    
-    return 0;
-}
-
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
-    int i, status;
-    
-    status = i2c_start(obj);
-    
-    if ((status != 0x10) && (status != 0x08)) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    status = i2c_do_write(obj, (address & 0xFE), 1);
-    if (status != 0x18) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    for (i=0; i<length; i++) {
-        status = i2c_do_write(obj, data[i], 0);
-        if (status != 0x28) {
-            i2c_stop(obj);
-            return status;
-        }
-    }
-    
-    // clearing the serial interrupt here might cause an unintended rewrite of the last byte
-    // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
-    // i2c_clear_SI(obj);
-    
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-    }
-    
-    return 0;
-}
-
-void i2c_reset(i2c_t *obj) {
-    i2c_stop(obj);
-}
-
-int i2c_byte_read(i2c_t *obj, int last) {
-    return (i2c_do_read(obj, last) & 0xFF);
-}
-
-int i2c_byte_write(i2c_t *obj, int data) {
-    int ack;
-    int status = i2c_do_write(obj, (data & 0xFF), 0);
-    
-    switch(status) {
-        case 0x18: case 0x28:       // Master transmit ACKs
-            ack = 1;
-            break;
-        
-        case 0x40:                  // Master receive address transmitted ACK
-            ack = 1;
-            break;
-        
-        case 0xB8:                  // Slave transmit ACK
-            ack = 1;
-            break;
-        
-        default:
-            ack = 0;
-            break;
-    }
-    
-    return ack;
-}
-
-void i2c_slave_mode(i2c_t *obj, int enable_slave) {
-    if (enable_slave != 0) {
-        i2c_conclr(obj, 1, 1, 1, 0);
-        i2c_conset(obj, 0, 0, 0, 1);
-    } else {
-        i2c_conclr(obj, 1, 1, 1, 1);
-    }
-}
-
-int i2c_slave_receive(i2c_t *obj) {
-    int status;
-    int retval;
-    
-    status = i2c_status(obj);
-    switch(status) {
-        case 0x60: retval = 3; break;
-        case 0x70: retval = 2; break;
-        case 0xA8: retval = 1; break;
-        default  : retval = 0; break;
-    }
-    
-    return(retval);
-}
-
-int i2c_slave_read(i2c_t *obj, char *data, int length) {
-    int count = 0;
-    int status;
-    
-    do {
-        i2c_clear_SI(obj);
-        i2c_wait_SI(obj);
-        status = i2c_status(obj);
-        if((status == 0x80) || (status == 0x90)) {
-            data[count] = I2C_DAT(obj) & 0xFF;
-        }
-        count++;
-    } while (((status == 0x80) || (status == 0x90) ||
-            (status == 0x060) || (status == 0x70)) && (count < length));
-    
-    if(status != 0xA0) {
-        i2c_stop(obj);
-    }
-    
-    i2c_clear_SI(obj);
-    
-    return (count - 1);
-}
-
-int i2c_slave_write(i2c_t *obj, const char *data, int length) {
-    int count = 0;
-    int status;
-    
-    if(length <= 0) {
-        return(0);
-    }
-    
-    do {
-        status = i2c_do_write(obj, data[count], 0);
-        count++;
-    } while ((count < length) && (status == 0xB8));
-    
-    if((status != 0xC0) && (status != 0xC8)) {
-        i2c_stop(obj);
-    }
-    
-    i2c_clear_SI(obj);
-    
-    return(count);
-}
-
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
-    uint32_t addr;
-    
-    if ((idx >= 0) && (idx <= 3)) {
-        addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
-        *((uint32_t *) addr) = address & 0xFF;
-    }
-}

--- a/vendor/NXP/LPC2368/hal/objects.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,78 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    uint32_t port;
-    uint32_t pin;
-    uint32_t ch;
-};
-
-struct port_s {
-    __IO uint32_t *reg_dir;
-    __IO uint32_t *reg_out;
-    __I  uint32_t *reg_in;
-    PortName port;
-    uint32_t mask;
-};
-
-struct pwmout_s {
-    __IO uint32_t *MR;
-    PWMName pwm;
-};
-
-struct serial_s {
-    LPC_UART_TypeDef *uart;
-    int index;
-};
-
-struct analogin_s {
-    ADCName adc;
-};
-
-struct dac_s {
-    DACName dac;
-};
-
-struct can_s {
-    LPC_CAN_TypeDef *dev;
-};
-
-struct i2c_s {
-    LPC_I2C_TypeDef *i2c;
-};
-
-struct spi_s {
-    LPC_SSP_TypeDef *spi;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC2368/hal/pinmap.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,47 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "pinmap.h"
-#include "error.h"
-
-void pin_function(PinName pin, int function) {
-    if (pin == (uint32_t)NC) return;
-    
-    uint32_t pin_number = (uint32_t)pin - (uint32_t)P0_0;
-    int index = pin_number >> 4;
-    int offset = (pin_number & 0xF) << 1;
-    
-    PINCONARRAY->PINSEL[index] &= ~(0x3 << offset);
-    PINCONARRAY->PINSEL[index] |= function << offset;
-}
-
-void pin_mode(PinName pin, PinMode mode) {
-    if (pin == (uint32_t)NC) { return; }
-    
-    uint32_t pin_number = (uint32_t)pin - (uint32_t)P0_0;
-    int index = pin_number >> 5;
-    int offset = pin_number & 0x1F;
-    uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2;
-    
-    if (mode == OpenDrain) error("OpenDrain not supported on LPC2368");
-    
-    if (!drain) {
-        index = pin_number >> 4;
-        offset = (pin_number & 0xF) << 1;
-        
-        PINCONARRAY->PINMODE[index] &= ~(0x3 << offset);
-        PINCONARRAY->PINMODE[index] |= (uint32_t)mode << offset;
-    }
-}

--- a/vendor/NXP/LPC2368/hal/port_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,71 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "port_api.h"
-#include "pinmap.h"
-#include "gpio_api.h"
-
-PinName port_pin(PortName port, int pin_n) {
-    return (PinName)(LPC_GPIO0_BASE + ((port << PORT_SHIFT) | pin_n));
-}
-
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
-    obj->port = port;
-    obj->mask = mask;
-    
-    LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *)(LPC_GPIO0_BASE + ((int)port * 0x20));
-    
-    // Do not use masking, because it prevents the use of the unmasked pins
-    // port_reg->FIOMASK = ~mask;
-    
-    obj->reg_out = &port_reg->FIOPIN;
-    obj->reg_in  = &port_reg->FIOPIN;
-    obj->reg_dir  = &port_reg->FIODIR;
-    
-    uint32_t i;
-    // The function is set per pin: reuse gpio logic
-    for (i=0; i<32; i++) {
-        if (obj->mask & (1<<i)) {
-            gpio_set(port_pin(obj->port, i));
-        }
-    }
-    
-    port_dir(obj, dir);
-}
-
-void port_mode(port_t *obj, PinMode mode) {
-    uint32_t i;
-    // The mode is set per pin: reuse pinmap logic
-    for (i=0; i<32; i++) {
-        if (obj->mask & (1<<i)) {
-            pin_mode(port_pin(obj->port, i), mode);
-        }
-    }
-}
-
-void port_dir(port_t *obj, PinDirection dir) {
-    switch (dir) {
-        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
-        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
-    }
-}
-
-void port_write(port_t *obj, int value) {
-    *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
-}
-
-int port_read(port_t *obj) {
-    return (*obj->reg_in & obj->mask);
-}

--- a/vendor/NXP/LPC2368/hal/pwmout_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,172 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "pwmout_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-#define TCR_CNT_EN       0x00000001
-#define TCR_RESET        0x00000002
-
-//  PORT ID, PWM ID, Pin function
-static const PinMap PinMap_PWM[] = {
-    {P1_18, PWM_1, 2},
-    {P1_20, PWM_2, 2},
-    {P1_21, PWM_3, 2},
-    {P1_23, PWM_4, 2},
-    {P1_24, PWM_5, 2},
-    {P1_26, PWM_6, 2},
-    {P2_0 , PWM_1, 1},
-    {P2_1 , PWM_2, 1},
-    {P2_2 , PWM_3, 1},
-    {P2_3 , PWM_4, 1},
-    {P2_4 , PWM_5, 1},
-    {P2_5 , PWM_6, 1},
-    {P3_25, PWM_2, 3},
-    {P3_26, PWM_3, 3},
-    {NC, NC, 0}
-};
-
-__IO uint32_t *PWM_MATCH[] = {
-    &(LPC_PWM1->MR0),
-    &(LPC_PWM1->MR1),
-    &(LPC_PWM1->MR2),
-    &(LPC_PWM1->MR3),
-    &(LPC_PWM1->MR4),
-    &(LPC_PWM1->MR5),
-    &(LPC_PWM1->MR6)
-};
-
-#define TCR_PWM_EN       0x00000008
-
-static unsigned int pwm_clock_mhz;
-
-void pwmout_init(pwmout_t* obj, PinName pin) {
-    // determine the channel
-    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
-    if (pwm == (uint32_t)NC)
-        error("PwmOut pin mapping failed");
-    
-    obj->pwm = pwm;
-    obj->MR = PWM_MATCH[pwm];
-    
-    // ensure the power is on
-    LPC_SC->PCONP |= 1 << 6;
-    
-    // ensure clock to /4
-    LPC_SC->PCLKSEL0 &= ~(0x3 << 12);     // pclk = /4
-    LPC_PWM1->PR = 0;                     // no pre-scale
-    
-    // ensure single PWM mode
-    LPC_PWM1->MCR = 1 << 1; // reset TC on match 0
-    
-    // enable the specific PWM output
-    LPC_PWM1->PCR |= 1 << (8 + pwm);
-    
-    pwm_clock_mhz = SystemCoreClock / 4000000;
-    
-    // default to 20ms: standard for servos, and fine for e.g. brightness control
-    pwmout_period_ms(obj, 20);
-    pwmout_write    (obj, 0);
-    
-    // Wire pinout
-    pinmap_pinout(pin, PinMap_PWM);
-}
-
-void pwmout_free(pwmout_t* obj) {
-    // [TODO]
-}
-
-void pwmout_write(pwmout_t* obj, float value) {
-    if (value < 0.0f) {
-        value = 0.0;
-    } else if (value > 1.0f) {
-        value = 1.0;
-    }
-    
-    // set channel match to percentage
-    uint32_t v = (uint32_t)((float)(LPC_PWM1->MR0) * value);
-    
-    // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
-    if (v == LPC_PWM1->MR0) {
-        v++;
-    }
-    
-    *obj->MR = v;
-    
-    // accept on next period start
-    LPC_PWM1->LER |= 1 << obj->pwm;
-}
-
-float pwmout_read(pwmout_t* obj) {
-    float v = (float)(*obj->MR) / (float)(LPC_PWM1->MR0);
-    return (v > 1.0f) ? (1.0f) : (v);
-}
-
-void pwmout_period(pwmout_t* obj, float seconds) {
-    pwmout_period_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_period_ms(pwmout_t* obj, int ms) {
-    pwmout_period_us(obj, ms * 1000);
-}
-
-// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
-    // calculate number of ticks
-    uint32_t ticks = pwm_clock_mhz * us;
-    
-    // set reset
-    LPC_PWM1->TCR = TCR_RESET;
-    
-    // set the global match register
-    LPC_PWM1->MR0 = ticks;
-    
-    // Scale the pulse width to preserve the duty ratio
-    if (LPC_PWM1->MR0 > 0) {
-        *obj->MR = (*obj->MR * ticks) / LPC_PWM1->MR0;
-    }
-    
-    // set the channel latch to update value at next period start
-    LPC_PWM1->LER |= 1 << 0;
-    
-    // enable counter and pwm, clear reset
-    LPC_PWM1->TCR = TCR_CNT_EN | TCR_PWM_EN;
-}
-
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
-    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
-    pwmout_pulsewidth_us(obj, ms * 1000);
-}
-
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
-    // calculate number of ticks
-    uint32_t v = pwm_clock_mhz * us;
-    
-    // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
-    if (v == LPC_PWM1->MR0) {
-        v++;
-    }
-    
-    // set the match register value
-    *obj->MR = v;
-    
-    // set the channel latch to update value at next period start
-    LPC_PWM1->LER |= 1 << obj->pwm;
-}

--- a/vendor/NXP/LPC2368/hal/rtc_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,117 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "rtc_api.h"
-
-// ensure rtc is running (unchanged if already running)
-
-/* Setup the RTC based on a time structure, ensuring RTC is enabled
- *
- * Can be clocked by a 32.768KHz oscillator or prescale divider based on the APB clock
- * - We want to use the 32khz clock, allowing for sleep mode
- *
- * Most registers are not changed by a Reset
- * - We must initialize these registers between power-on and setting the RTC into operation
-
- * Clock Control Register
- *  RTC_CCR[0] : Enable - 0 = Disabled, 1 = Enabled
- *  RTC_CCR[1] : Reset - 0 = Normal, 1 = Reset
- *  RTC_CCR[4] : Clock Source - 0 = Prescaler, 1 = 32k Xtal
- *
- * The RTC may already be running, so we should set it up
- * without impacting if it is the case
- */
-void rtc_init(void) {
-    LPC_SC->PCONP |= 0x200; // Ensure power is on
-    LPC_RTC->CCR = 0x00;
-    
-    // clock source on 2368 is special test mode on 1768!
-    LPC_RTC->CCR |= 1 << 4;  // Ensure clock source is 32KHz Xtal
-    
-    LPC_RTC->CCR |= 1 << 0; // Ensure the RTC is enabled
-}
-
-void rtc_free(void) {
-    // [TODO]
-}
-
-/*
- * Little check routine to see if the RTC has been enabled
- *
- * Clock Control Register
- *  RTC_CCR[0] : 0 = Disabled, 1 = Enabled
- *
- */
-
-int rtc_isenabled(void) {
-    return(((LPC_RTC->CCR) & 0x01) != 0);
-}
-
-/*
- * RTC Registers
- *  RTC_SEC        Seconds 0-59
- *  RTC_MIN        Minutes 0-59
- *  RTC_HOUR    Hour 0-23
- *  RTC_DOM        Day of Month 1-28..31
- *  RTC_DOW        Day of Week 0-6
- *  RTC_DOY        Day of Year 1-365
- *  RTC_MONTH    Month 1-12
- *  RTC_YEAR    Year 0-4095
- *
- * struct tm
- *  tm_sec        seconds after the minute 0-61
- *  tm_min        minutes after the hour 0-59
- *  tm_hour        hours since midnight 0-23
- *  tm_mday        day of the month 1-31
- *  tm_mon        months since January 0-11
- *  tm_year        years since 1900
- *  tm_wday        days since Sunday 0-6
- *  tm_yday        days since January 1 0-365
- *  tm_isdst    Daylight Saving Time flag
- */
-time_t rtc_read(void) {
-    // Setup a tm structure based on the RTC
-    struct tm timeinfo;
-    timeinfo.tm_sec = LPC_RTC->SEC;
-    timeinfo.tm_min = LPC_RTC->MIN;
-    timeinfo.tm_hour = LPC_RTC->HOUR;
-    timeinfo.tm_mday = LPC_RTC->DOM;
-    timeinfo.tm_mon = LPC_RTC->MONTH - 1;
-    timeinfo.tm_year = LPC_RTC->YEAR - 1900;
-    
-    // Convert to timestamp
-    time_t t = mktime(&timeinfo);
-    
-    return t;
-}
-
-void rtc_write(time_t t) {
-    // Convert the time in to a tm
-    struct tm *timeinfo = localtime(&t);
-    
-    // Pause clock, and clear counter register (clears us count)
-    LPC_RTC->CCR |= 2;
-    
-    // Set the RTC
-    LPC_RTC->SEC = timeinfo->tm_sec;
-    LPC_RTC->MIN = timeinfo->tm_min;
-    LPC_RTC->HOUR = timeinfo->tm_hour;
-    LPC_RTC->DOM = timeinfo->tm_mday;
-    LPC_RTC->MONTH = timeinfo->tm_mon + 1;
-    LPC_RTC->YEAR = timeinfo->tm_year + 1900;
-    
-    // Restart clock
-    LPC_RTC->CCR &= ~((uint32_t)2);
-}

--- a/vendor/NXP/LPC2368/hal/serial_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,309 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// math.h required for floating point operations for baud rate calculation
-#include <math.h>
-#include <string.h>
-
-#include "serial_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-/******************************************************************************
- * INITIALIZATION
- ******************************************************************************/
-#define UART_NUM    4
-
-static const PinMap PinMap_UART_TX[] = {
-    {P0_0,  UART_3, 2},
-    {P0_2,  UART_0, 1},
-    {P0_10, UART_2, 1},
-    {P0_15, UART_1, 1},
-    {P0_25, UART_3, 3},
-    {P2_0 , UART_1, 2},
-    {P2_8 , UART_2, 2},
-    {P4_28, UART_3, 3},
-    {NC   , NC    , 0}
-};
-
-static const PinMap PinMap_UART_RX[] = {
-    {P0_1 , UART_3, 2},
-    {P0_3 , UART_0, 1},
-    {P0_11, UART_2, 1},
-    {P0_16, UART_1, 1},
-    {P0_26, UART_3, 3},
-    {P2_1 , UART_1, 2},
-    {P2_9 , UART_2, 2},
-    {P4_29, UART_3, 3},
-    {NC   , NC    , 0}
-};
-
-static uint32_t serial_irq_ids[UART_NUM] = {0};
-static uart_irq_handler irq_handler;
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
-    int is_stdio_uart = 0;
-    
-    // determine the UART to use
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-    UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    if ((int)uart == NC) {
-        error("Serial pinout mapping failed");
-    }
-    
-    obj->uart = (LPC_UART_TypeDef *)uart;
-    // enable power
-    switch (uart) {
-        case UART_0: LPC_SC->PCONP |= 1 <<  3; break;
-        case UART_1: LPC_SC->PCONP |= 1 <<  4; break;
-        case UART_2: LPC_SC->PCONP |= 1 << 24; break;
-        case UART_3: LPC_SC->PCONP |= 1 << 25; break;
-    }
-    
-    // enable fifos and default rx trigger level
-    obj->uart->FCR = 1 << 0  // FIFO Enable - 0 = Disables, 1 = Enabled
-                   | 0 << 1  // Rx Fifo Reset
-                   | 0 << 2  // Tx Fifo Reset
-                   | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
-
-    // disable irqs
-    obj->uart->IER = 0 << 0  // Rx Data available irq enable
-                   | 0 << 1  // Tx Fifo empty irq enable
-                   | 0 << 2; // Rx Line Status irq enable
-    
-    // set default baud rate and format
-    serial_baud  (obj, 9600);
-    serial_format(obj, 8, ParityNone, 1);
-    
-    // pinout the chosen uart
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    
-    // set rx/tx pins in PullUp mode
-    pin_mode(tx, PullUp);
-    pin_mode(rx, PullUp);
-    
-    switch (uart) {
-        case UART_0: obj->index = 0; break;
-        case UART_1: obj->index = 1; break;
-        case UART_2: obj->index = 2; break;
-        case UART_3: obj->index = 3; break;
-    }
-    
-    is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
-    
-    if (is_stdio_uart) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj) {
-    serial_irq_ids[obj->index] = 0;
-}
-
-// serial_baud
-// set the baud rate, taking in to account the current SystemFrequency
-void serial_baud(serial_t *obj, int baudrate) {
-    // The LPC2300 and LPC1700 have a divider and a fractional divider to control the
-    // baud rate. The formula is:
-    //
-    // Baudrate = (1 / PCLK) * 16 * DL * (1 + DivAddVal / MulVal)
-    //   where:
-    //     1 < MulVal <= 15
-    //     0 <= DivAddVal < 14
-    //     DivAddVal < MulVal
-    //
-    // set pclk to /1
-    switch ((int)obj->uart) {
-        case UART_0: LPC_SC->PCLKSEL0 &= ~(0x3 <<  6); LPC_SC->PCLKSEL0 |= (0x1 <<  6); break;
-        case UART_1: LPC_SC->PCLKSEL0 &= ~(0x3 <<  8); LPC_SC->PCLKSEL0 |= (0x1 <<  8); break;
-        case UART_2: LPC_SC->PCLKSEL1 &= ~(0x3 << 16); LPC_SC->PCLKSEL1 |= (0x1 << 16); break;
-        case UART_3: LPC_SC->PCLKSEL1 &= ~(0x3 << 18); LPC_SC->PCLKSEL1 |= (0x1 << 18); break;
-        default: error("serial_baud"); break;
-    }
-    
-    uint32_t PCLK = SystemCoreClock;
-    
-    // First we check to see if the basic divide with no DivAddVal/MulVal
-    // ratio gives us an integer result. If it does, we set DivAddVal = 0,
-    // MulVal = 1. Otherwise, we search the valid ratio value range to find
-    // the closest match. This could be more elegant, using search methods
-    // and/or lookup tables, but the brute force method is not that much
-    // slower, and is more maintainable.
-    uint16_t DL = PCLK / (16 * baudrate);
-
-    uint8_t DivAddVal = 0;
-    uint8_t MulVal = 1;
-    int hit = 0;
-    uint16_t dlv;
-    uint8_t mv, dav;
-    if ((PCLK % (16 * baudrate)) != 0) {     // Checking for zero remainder
-        float err_best = (float) baudrate;
-        uint16_t dlmax = DL;
-        for ( dlv = (dlmax/2); (dlv <= dlmax) && !hit; dlv++) {
-            for ( mv = 1; mv <= 15; mv++) {
-                for ( dav = 1; dav < mv; dav++) {
-                    float ratio = 1.0f + ((float) dav / (float) mv);
-                    float calcbaud = (float)PCLK / (16.0f * (float) dlv * ratio);
-                    float err = fabs(((float) baudrate - calcbaud) / (float) baudrate);
-                    if (err < err_best) {
-                        DL = dlv;
-                        DivAddVal = dav;
-                        MulVal = mv;
-                        err_best = err;
-                        if (err < 0.001f) {
-                            hit = 1;
-                        }
-                    }
-                }
-            }
-        }
-    }
-    
-    // set LCR[DLAB] to enable writing to divider registers
-    obj->uart->LCR |= (1 << 7);
-    
-    // set divider values
-    obj->uart->DLM = (DL >> 8) & 0xFF;
-    obj->uart->DLL = (DL >> 0) & 0xFF;
-    obj->uart->FDR = (uint32_t) DivAddVal << 0
-                   | (uint32_t) MulVal    << 4;
-    
-    // clear LCR[DLAB]
-    obj->uart->LCR &= ~(1 << 7);
-}
-
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
-    // 0: 1 stop bits, 1: 2 stop bits
-    if (stop_bits != 1 && stop_bits != 2) {
-        error("Invalid stop bits specified");
-    }
-    stop_bits -= 1;
-    
-    // 0: 5 data bits ... 3: 8 data bits
-    if (data_bits < 5 || data_bits > 8) {
-        error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
-    }
-    data_bits -= 5;
-
-    int parity_enable, parity_select;
-    switch (parity) {
-        case ParityNone: parity_enable = 0; parity_select = 0; break;
-        case ParityOdd : parity_enable = 1; parity_select = 0; break;
-        case ParityEven: parity_enable = 1; parity_select = 1; break;
-        case ParityForced1: parity_enable = 1; parity_select = 2; break;
-        case ParityForced0: parity_enable = 1; parity_select = 3; break;
-        default:
-            error("Invalid serial parity setting");
-            return;
-    }
-    
-    obj->uart->LCR = data_bits            << 0
-                   | stop_bits            << 2
-                   | parity_enable        << 3
-                   | parity_select        << 4;
-}
-
-/******************************************************************************
- * INTERRUPTS HANDLING
- ******************************************************************************/
-static inline void uart_irq(uint32_t iir, uint32_t index) {
-    // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
-    SerialIrq irq_type;
-    switch (iir) {
-        case 1: irq_type = TxIrq; break;
-        case 2: irq_type = RxIrq; break;
-        default: return;
-    }
-    
-    if (serial_irq_ids[index] != 0)
-        irq_handler(serial_irq_ids[index], irq_type);
-}
-
-void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0);}
-void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);}
-void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2);}
-void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3);}
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
-    irq_handler = handler;
-    serial_irq_ids[obj->index] = id;
-}
-
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
-    IRQn_Type irq_n = (IRQn_Type)0;
-    uint32_t vector = 0;
-    switch ((int)obj->uart) {
-        case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
-        case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
-        case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
-        case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
-    }
-    
-    if (enable) {
-        obj->uart->IER |= 1 << irq;
-        NVIC_SetVector(irq_n, vector);
-        NVIC_EnableIRQ(irq_n);
-    } else { // disable
-        int all_disabled = 0;
-        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
-        obj->uart->IER &= ~(1 << irq);
-        all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
-        if (all_disabled)
-            NVIC_DisableIRQ(irq_n);
-    }
-}
-
-/******************************************************************************
- * READ/WRITE
- ******************************************************************************/
-int serial_getc(serial_t *obj) {
-    while (!serial_readable(obj));
-    return obj->uart->RBR;
-}
-
-void serial_putc(serial_t *obj, int c) {
-    while (!serial_writable(obj));
-    obj->uart->THR = c;
-    
-    uint32_t lsr = obj->uart->LSR;
-    lsr = lsr;
-    uint32_t thr = obj->uart->THR;
-    thr = thr;
-}
-
-int serial_readable(serial_t *obj) {
-    return obj->uart->LSR & 0x01;
-}
-
-int serial_writable(serial_t *obj) {
-    return obj->uart->LSR & 0x20;
-}
-
-void serial_clear(serial_t *obj) {
-    obj->uart->FCR = 1 << 1  // rx FIFO reset
-                   | 1 << 2  // tx FIFO reset
-                   | 0 << 6; // interrupt depth
-}
-
-void serial_pinout_tx(PinName tx) {
-    pinmap_pinout(tx, PinMap_UART_TX);
-}

--- a/vendor/NXP/LPC2368/hal/spi_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,224 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <math.h>
-
-#include "spi_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_SPI_SCLK[] = {
-    {P0_7 , SPI_1, 2},
-    {P0_15, SPI_0, 2},
-    {P1_20, SPI_0, 3},
-    {P1_31, SPI_1, 2},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_MOSI[] = {
-    {P0_9 , SPI_1, 2},
-    {P0_13, SPI_1, 2},
-    {P0_18, SPI_0, 2},
-    {P1_24, SPI_0, 3},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_MISO[] = {
-    {P0_8 , SPI_1, 2},
-    {P0_12, SPI_1, 2},
-    {P0_17, SPI_0, 2},
-    {P1_23, SPI_0, 3},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_SSEL[] = {
-    {P0_6 , SPI_1, 2},
-    {P0_11, SPI_1, 2},
-    {P0_16, SPI_0, 2},
-    {P1_21, SPI_0, 3},
-    {NC   , NC   , 0}
-};
-
-static inline int ssp_disable(spi_t *obj);
-static inline int ssp_enable(spi_t *obj);
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
-    // determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-    obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
-    
-    if ((int)obj->spi == NC) {
-        error("SPI pinout mapping failed");
-    }
-    
-    // enable power and clocking
-    switch ((int)obj->spi) {
-        case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
-        case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
-    }
-    
-    // set default format and frequency
-    if (ssel == NC) {
-        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
-    } else {
-        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
-    }
-    spi_frequency(obj, 1000000);
-    
-    // enable the ssp channel
-    ssp_enable(obj);
-    
-    // pin out the spi pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    }
-}
-
-void spi_free(spi_t *obj) {}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
-    ssp_disable(obj);
-    
-    if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
-        error("SPI format error");
-    }
-    
-    int polarity = (mode & 0x2) ? 1 : 0;
-    int phase = (mode & 0x1) ? 1 : 0;
-    
-    // set it up
-    int DSS = bits - 1;            // DSS (data select size)
-    int SPO = (polarity) ? 1 : 0;  // SPO - clock out polarity
-    int SPH = (phase) ? 1 : 0;     // SPH - clock out phase
-    
-    int FRF = 0;                   // FRF (frame format) = SPI
-    uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
-    tmp |= DSS << 0
-        | FRF << 4
-        | SPO << 6
-        | SPH << 7;
-    obj->spi->CR0 = tmp;
-    
-    tmp = obj->spi->CR1;
-    tmp &= ~(0xD);
-    tmp |= 0 << 0                   // LBM - loop back mode - off
-        | ((slave) ? 1 : 0) << 2   // MS - master slave mode, 1 = slave
-        | 0 << 3;                  // SOD - slave output disable - na
-    obj->spi->CR1 = tmp;
-    
-    ssp_enable(obj);
-}
-
-void spi_frequency(spi_t *obj, int hz) {
-    ssp_disable(obj);
-    
-    // setup the spi clock diveder to /1
-    switch ((int)obj->spi) {
-        case SPI_0:
-            LPC_SC->PCLKSEL1 &= ~(3 << 10);
-            LPC_SC->PCLKSEL1 |=  (1 << 10);
-            break;
-        case SPI_1:
-            LPC_SC->PCLKSEL0 &= ~(3 << 20);
-            LPC_SC->PCLKSEL0 |=  (1 << 20);
-            break;
-    }
-    
-    uint32_t PCLK = SystemCoreClock;
-    
-    int prescaler;
-    
-    for (prescaler = 2; prescaler <= 254; prescaler += 2) {
-        int prescale_hz = PCLK / prescaler;
-        
-        // calculate the divider
-        int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
-        
-        // check we can support the divider
-        if (divider < 256) {
-            // prescaler
-            obj->spi->CPSR = prescaler;
-            
-            // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
-            obj->spi->CR0 |= (divider - 1) << 8;
-            ssp_enable(obj);
-            return;
-        }
-    }
-    error("Couldn't setup requested SPI frequency");
-}
-
-static inline int ssp_disable(spi_t *obj) {
-    return obj->spi->CR1 &= ~(1 << 1);
-}
-
-static inline int ssp_enable(spi_t *obj) {
-    return obj->spi->CR1 |= (1 << 1);
-}
-
-static inline int ssp_readable(spi_t *obj) {
-    return obj->spi->SR & (1 << 2);
-}
-
-static inline int ssp_writeable(spi_t *obj) {
-    return obj->spi->SR & (1 << 1);
-}
-
-static inline void ssp_write(spi_t *obj, int value) {
-    while (!ssp_writeable(obj));
-    obj->spi->DR = value;
-}
-
-static inline int ssp_read(spi_t *obj) {
-    while (!ssp_readable(obj));
-    return obj->spi->DR;
-}
-
-static inline int ssp_busy(spi_t *obj) {
-    return (obj->spi->SR & (1 << 4)) ? (1) : (0);
-}
-
-int spi_master_write(spi_t *obj, int value) {
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj) {
-    return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
-};
-
-int spi_slave_read(spi_t *obj) {
-    return obj->spi->DR;
-}
-
-void spi_slave_write(spi_t *obj, int value) {
-    while (ssp_writeable(obj) == 0) ;
-    obj->spi->DR = value;
-}
-
-int spi_busy(spi_t *obj) {
-    return ssp_busy(obj);
-}

--- a/vendor/NXP/LPC2368/hal/us_ticker.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,64 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stddef.h>
-#include "us_ticker_api.h"
-#include "PeripheralNames.h"
-
-#define US_TICKER_TIMER      ((LPC_TIM_TypeDef *)LPC_TIM3_BASE)
-#define US_TICKER_TIMER_IRQn TIMER3_IRQn
-
-int us_ticker_inited = 0;
-
-void us_ticker_init(void) {
-    if (us_ticker_inited) return;
-    us_ticker_inited = 1;
-    
-    LPC_SC->PCONP |= 1 << 23; // Clock TIMER_3
-    
-    US_TICKER_TIMER->CTCR = 0x0; // timer mode
-    uint32_t PCLK = SystemCoreClock / 4;
-    
-    US_TICKER_TIMER->TCR = 0x2;  // reset
-    
-    uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks)
-    US_TICKER_TIMER->PR = prescale - 1;
-    US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0
-    
-    NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
-    NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
-}
-
-uint32_t us_ticker_read() {
-    if (!us_ticker_inited)
-        us_ticker_init();
-    
-    return US_TICKER_TIMER->TC;
-}
-
-void us_ticker_set_interrupt(unsigned int timestamp) {
-    // set match value
-    US_TICKER_TIMER->MR0 = timestamp;
-    // enable match interrupt
-    US_TICKER_TIMER->MCR |= 1;
-}
-
-void us_ticker_disable_interrupt(void) {
-    US_TICKER_TIMER->MCR &= ~1;
-}
-
-void us_ticker_clear_interrupt(void) {
-    US_TICKER_TIMER->IR = 1;
-}

--- a/vendor/NXP/LPC4088/cmsis/ARM/LPC407X_8X.sct	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,18 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x00000000 0x00080000  {    ; load region size_region
-  ER_IROM1 0x00000000 0x00080000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  RW_IRAM1 0x100000E8 0x0000FF18  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-  RW_IRAM2 0x20000000 0x00008000  {
-   .ANY (AHBSRAM1)
-  }
-}
-

--- a/vendor/NXP/LPC4088/cmsis/ARM/startup_LPC407x_8x_177x_8x.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,254 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC407x_8x.s
-; * @purpose: CMSIS Cortex-M4 Core Device Startup File
-; *           for the NXP LPC407x_8x Device Series
-; * @version: V1.20
-; * @date:    16. January 2012
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2012 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M4
-; * processor based microcontrollers.  This file can be freely distributed
-; * within development tools that are supporting such ARM based processors.
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-
-
-__initial_sp        EQU     0x10010000  ; Top of RAM from LPC4088
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                ; DCD   0xEFFFF5D6                ; Reserved- vector sum
-                DCD     0xEFFFF39E                ; Reserved- vector sum
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ; 16: Watchdog Timer
-                DCD     TIMER0_IRQHandler         ; 17: Timer0
-                DCD     TIMER1_IRQHandler         ; 18: Timer1
-                DCD     TIMER2_IRQHandler         ; 19: Timer2
-                DCD     TIMER3_IRQHandler         ; 20: Timer3
-                DCD     UART0_IRQHandler          ; 21: UART0
-                DCD     UART1_IRQHandler          ; 22: UART1
-                DCD     UART2_IRQHandler          ; 23: UART2
-                DCD     UART3_IRQHandler          ; 24: UART3
-                DCD     PWM1_IRQHandler           ; 25: PWM1
-                DCD     I2C0_IRQHandler           ; 26: I2C0
-                DCD     I2C1_IRQHandler           ; 27: I2C1
-                DCD     I2C2_IRQHandler           ; 28: I2C2
-                DCD     0                         ; 29: reserved, not for SPIFI anymore
-                DCD     SSP0_IRQHandler           ; 30: SSP0
-                DCD     SSP1_IRQHandler           ; 31: SSP1
-                DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
-                DCD     RTC_IRQHandler            ; 33: Real Time Clock
-                DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
-                DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
-                DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
-                DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
-                DCD     ADC_IRQHandler            ; 38: A/D Converter
-                DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
-                DCD     USB_IRQHandler            ; 40: USB
-                DCD     CAN_IRQHandler            ; 41: CAN
-                DCD     DMA_IRQHandler            ; 42: General Purpose DMA
-                DCD     I2S_IRQHandler            ; 43: I2S
-                DCD     ENET_IRQHandler           ; 44: Ethernet
-                DCD     MCI_IRQHandler            ; 45: SD/MMC card I/F
-                DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
-                DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
-                DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
-                DCD     USBActivity_IRQHandler    ; 49: USB Activity interrupt to wakeup
-                DCD     CANActivity_IRQHandler    ; 50: CAN Activity interrupt to wakeup
-                DCD     UART4_IRQHandler          ; 51: UART4
-                DCD     SSP2_IRQHandler           ; 52: SSP2
-                DCD     LCD_IRQHandler            ; 53: LCD
-                DCD     GPIO_IRQHandler           ; 54: GPIO
-                DCD     PWM0_IRQHandler           ; 55: PWM0
-                DCD     EEPROM_IRQHandler         ; 56: EEPROM
-
-
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  TIMER0_IRQHandler         [WEAK]
-                EXPORT  TIMER1_IRQHandler         [WEAK]
-                EXPORT  TIMER2_IRQHandler         [WEAK]
-                EXPORT  TIMER3_IRQHandler         [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  PWM1_IRQHandler           [WEAK]
-                EXPORT  I2C0_IRQHandler           [WEAK]
-                EXPORT  I2C1_IRQHandler           [WEAK]
-                EXPORT  I2C2_IRQHandler           [WEAK]
-                ;EXPORT  SPIFI_IRQHandler          [WEAK]
-                EXPORT  SSP0_IRQHandler           [WEAK]
-                EXPORT  SSP1_IRQHandler           [WEAK]
-                EXPORT  PLL0_IRQHandler           [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  EINT0_IRQHandler          [WEAK]
-                EXPORT  EINT1_IRQHandler          [WEAK]
-                EXPORT  EINT2_IRQHandler          [WEAK]
-                EXPORT  EINT3_IRQHandler          [WEAK]
-                EXPORT  ADC_IRQHandler            [WEAK]
-                EXPORT  BOD_IRQHandler            [WEAK]
-                EXPORT  USB_IRQHandler            [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  DMA_IRQHandler            [WEAK]
-                EXPORT  I2S_IRQHandler            [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  MCI_IRQHandler            [WEAK]
-                EXPORT  MCPWM_IRQHandler          [WEAK]
-                EXPORT  QEI_IRQHandler            [WEAK]
-                EXPORT  PLL1_IRQHandler           [WEAK]
-                EXPORT  USBActivity_IRQHandler    [WEAK]
-                EXPORT  CANActivity_IRQHandler    [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  SSP2_IRQHandler           [WEAK]
-                EXPORT  LCD_IRQHandler            [WEAK]
-                EXPORT  GPIO_IRQHandler           [WEAK]
-                EXPORT  PWM0_IRQHandler           [WEAK]
-                EXPORT  EEPROM_IRQHandler         [WEAK]
-
-WDT_IRQHandler
-TIMER0_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
-TIMER3_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-PWM1_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-;SPIFI_IRQHandler ;not used
-SSP0_IRQHandler
-SSP1_IRQHandler
-PLL0_IRQHandler
-RTC_IRQHandler
-EINT0_IRQHandler
-EINT1_IRQHandler
-EINT2_IRQHandler
-EINT3_IRQHandler
-ADC_IRQHandler
-BOD_IRQHandler
-USB_IRQHandler
-CAN_IRQHandler
-DMA_IRQHandler
-I2S_IRQHandler
-ENET_IRQHandler
-MCI_IRQHandler
-MCPWM_IRQHandler
-QEI_IRQHandler
-PLL1_IRQHandler
-USBActivity_IRQHandler
-CANActivity_IRQHandler
-UART4_IRQHandler
-SSP2_IRQHandler
-LCD_IRQHandler
-GPIO_IRQHandler
-PWM0_IRQHandler
-EEPROM_IRQHandler
-
-                B       .
-
-                ENDP
-
-
-                ALIGN
-                END

--- a/vendor/NXP/LPC4088/cmsis/ARM/sys.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * Setup a fixed single stack/heap memory model, 
- *  between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/vendor/NXP/LPC4088/cmsis/GCC_CR/LPC407x_8x.ld	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,180 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * (C) Code Red Technologies Ltd, 2008-2013
- * Generated linker script file for LPC4088
- * Created from generic_c.ld (vLPCXpresso v5.1 (2 [Build 2065] [2013-02-20] ))
- * By LPCXpresso v5.1.2 [Build 2065] [2013-02-20]  on Wed Apr 17 14:50:07 CEST 2013
- */
-
-
-GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
-  RamLoc64 (rwx) : ORIGIN = 0x100000E8, LENGTH = 0xFF18 /* 64k */
-  RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32k */
-
-}
-  /* Define a symbol for the top of each memory region */
-  __top_MFlash512 = 0x0 + 0x80000;
-  __top_RamLoc64 = 0x10000000 + 0x10000;
-  __top_RamPeriph32 = 0x20000000 + 0x8000;
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-
-    /* MAIN TEXT SECTION */    
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        KEEP(*(.isr_vector))
-        
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data)) ;
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2)) ;
-        LONG(  SIZEOF(.data_RAM2));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-        
-
-        *(.after_vectors*)
-        
-        *(.text*)
-        *(.rodata .rodata.*)
-        . = ALIGN(4);
-        
-        /* C++ constructors etc */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-        
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-        
-        KEEP(*(.fini));
-        
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-        
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-        /* End C++ */
-    } > MFlash512
-
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
-     */
-    .ARM.extab : ALIGN(4)
-    {
-    	*(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlash512
-    __exidx_start = .;
-    
-    .ARM.exidx : ALIGN(4)
-    {
-    	*(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > MFlash512
-    __exidx_end = .;
-    
-    _etext = .;
-        
-    
-    /* DATA section for RamPeriph32 */
-    .data_RAM2 : ALIGN(4)
-    {
-       FILL(0xff)
-    	*(.data.$RAM2*)
-    	*(.data.$RamPeriph32*)
-       . = ALIGN(4) ;
-    } > RamPeriph32 AT>MFlash512
-    
-    /* MAIN DATA SECTION */
-    
-
-    .uninit_RESERVED : ALIGN(4)
-    {
-        KEEP(*(.bss.$RESERVED*))
-        . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > RamLoc64
-
-    .data : ALIGN(4)
-    {
-        FILL(0xff)
-        _data = .;
-        *(vtable)
-        *(.data*)
-        . = ALIGN(4) ;
-        _edata = .;
-    } > RamLoc64 AT>MFlash512
-
-    /* BSS section for RamPeriph32 */
-    .bss_RAM2 : ALIGN(4)
-    {
-    	*(.bss.$RAM2*)
-    	*(.bss.$RamPeriph32*)
-       . = ALIGN(4) ;
-    } > RamPeriph32
-
-    /* MAIN BSS SECTION */
-    .bss : ALIGN(4)
-    {
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc64
-        
-    /* NOINIT section for RamPeriph32 */
-    .noinit_RAM2 (NOLOAD) : ALIGN(4)
-    {
-    	*(.noinit.$RAM2*)
-    	*(.noinit.$RamPeriph32*)
-       . = ALIGN(4) ;
-    } > RamPeriph32 
-    
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD): ALIGN(4)
-    {
-        _noinit = .;
-        *(.noinit*) 
-         . = ALIGN(4) ;
-        _end_noinit = .;
-    } > RamLoc64
-    
-    PROVIDE(_pvHeapStart = .);
-    PROVIDE(_vStackTop = __top_RamLoc64 - 0);
-}

--- a/vendor/NXP/LPC4088/cmsis/GCC_CR/startup_lpc407x_8x.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,433 +0,0 @@
-//*****************************************************************************
-//   +--+       
-//   | ++----+   
-//   +-++    |  
-//     |     |  
-//   +-+--+  |   
-//   | +--+--+  
-//   +----+    Copyright (c) 2012 Code Red Technologies Ltd.
-//
-// LPC407x_8x Microcontroller Startup code for use with Red Suite
-//
-// Version : 120624
-//
-// Software License Agreement
-// 
-// The software is owned by Code Red Technologies and/or its suppliers, and is 
-// protected under applicable copyright laws.  All rights are reserved.  Any 
-// use in violation of the foregoing restrictions may subject the user to criminal 
-// sanctions under applicable laws, as well as to civil liability for the breach
-// of the terms and conditions of this license.
-// 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
-// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
-// CODE RED TECHNOLOGIES LTD. 
-//
-//*****************************************************************************
-#if defined (__cplusplus)
-#ifdef __REDLIB__
-#error Redlib does not support C++
-#else
-//*****************************************************************************
-//
-// The entry point for the C++ library startup
-//
-//*****************************************************************************
-extern "C" {
-	extern void __libc_init_array(void);
-}
-#endif
-#endif
-
-#define WEAK __attribute__ ((weak))
-#define ALIAS(f) __attribute__ ((weak, alias (#f)))
-
-//#if defined (__USE_CMSIS)
-#include "LPC407x_8x_177x_8x.h"
-//#endif
-
-//*****************************************************************************
-#if defined (__cplusplus)
-extern "C" {
-#endif
-
-//*****************************************************************************
-//
-// Forward declaration of the default handlers. These are aliased.
-// When the application defines a handler (with the same name), this will 
-// automatically take precedence over these weak definitions
-//
-//*****************************************************************************
-     void ResetISR(void);
-WEAK void NMI_Handler(void);
-WEAK void HardFault_Handler(void);
-WEAK void MemManage_Handler(void);
-WEAK void BusFault_Handler(void);
-WEAK void UsageFault_Handler(void);
-WEAK void SVC_Handler(void);
-WEAK void DebugMon_Handler(void);
-WEAK void PendSV_Handler(void);
-WEAK void SysTick_Handler(void);
-WEAK void IntDefaultHandler(void);
-
-//*****************************************************************************
-//
-// Forward declaration of the specific IRQ handlers. These are aliased
-// to the IntDefaultHandler, which is a 'forever' loop. When the application
-// defines a handler (with the same name), this will automatically take 
-// precedence over these weak definitions
-//
-//*****************************************************************************
-void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EINT3_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
-void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
-void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
-void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
-void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
-void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
-void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
-void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
-void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
-void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
-void MCI_IRQHandler(void) ALIAS(IntDefaultHandler);
-void UART4_IRQHandler(void) ALIAS(IntDefaultHandler);
-void SSP2_IRQHandler(void) ALIAS(IntDefaultHandler);
-void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
-void GPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
-void PWM0_IRQHandler(void) ALIAS(IntDefaultHandler);
-void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
-
-//*****************************************************************************
-//
-// The entry point for the application.
-// __main() is the entry point for Redlib based applications
-// main() is the entry point for Newlib based applications
-//
-//*****************************************************************************
-#if defined (__REDLIB__)
-extern void __main(void);
-#endif
-extern int main(void);
-//*****************************************************************************
-//
-// External declaration for the pointer to the stack top from the Linker Script
-//
-//*****************************************************************************
-extern void _vStackTop(void);
-
-//*****************************************************************************
-#if defined (__cplusplus)
-} // extern "C"
-#endif
-//*****************************************************************************
-//
-// The vector table.
-// This relies on the linker script to place at correct location in memory.
-//
-//*****************************************************************************
-extern void (* const g_pfnVectors[])(void);
-__attribute__ ((section(".isr_vector")))
-void (* const g_pfnVectors[])(void) = {
-	// Core Level - CM3
-	&_vStackTop, // The initial stack pointer
-	ResetISR,							// The reset handler
-	NMI_Handler,							// The NMI handler
-	HardFault_Handler,						// The hard fault handler
-	MemManage_Handler,						// The MPU fault handler
-	BusFault_Handler,						// The bus fault handler
-	UsageFault_Handler,						// The usage fault handler
-	0,								// Reserved
-	0,								// Reserved
-	0,								// Reserved
-	0,								// Reserved
-	SVC_Handler,							// SVCall handler
-	DebugMon_Handler,						// Debug monitor handler
-	0,								// Reserved
-	PendSV_Handler,							// The PendSV handler
-	SysTick_Handler,						// The SysTick handler
-
-	// Chip Level - LPC17
-	WDT_IRQHandler,							// 16, 0x40 - WDT
-	TIMER0_IRQHandler,						// 17, 0x44 - TIMER0
-	TIMER1_IRQHandler,						// 18, 0x48 - TIMER1
-	TIMER2_IRQHandler,						// 19, 0x4c - TIMER2
-	TIMER3_IRQHandler,						// 20, 0x50 - TIMER3
-	UART0_IRQHandler,						// 21, 0x54 - UART0
-	UART1_IRQHandler,						// 22, 0x58 - UART1
-	UART2_IRQHandler,						// 23, 0x5c - UART2
-	UART3_IRQHandler,						// 24, 0x60 - UART3
-	PWM1_IRQHandler,						// 25, 0x64 - PWM1
-	I2C0_IRQHandler,						// 26, 0x68 - I2C0
-	I2C1_IRQHandler,						// 27, 0x6c - I2C1
-	I2C2_IRQHandler,						// 28, 0x70 - I2C2
-	IntDefaultHandler,						// 29, Not used
-	SSP0_IRQHandler,						// 30, 0x78 - SSP0
-	SSP1_IRQHandler,						// 31, 0x7c - SSP1
-	PLL0_IRQHandler,						// 32, 0x80 - PLL0 (Main PLL)
-	RTC_IRQHandler,							// 33, 0x84 - RTC
-	EINT0_IRQHandler,						// 34, 0x88 - EINT0
-	EINT1_IRQHandler,						// 35, 0x8c - EINT1
-	EINT2_IRQHandler,						// 36, 0x90 - EINT2
-	EINT3_IRQHandler,						// 37, 0x94 - EINT3
-	ADC_IRQHandler,							// 38, 0x98 - ADC
-	BOD_IRQHandler,							// 39, 0x9c - BOD
-	USB_IRQHandler,							// 40, 0xA0 - USB
-	CAN_IRQHandler,							// 41, 0xa4 - CAN
-	DMA_IRQHandler,							// 42, 0xa8 - GP DMA
-	I2S_IRQHandler,							// 43, 0xac - I2S
-	ENET_IRQHandler,						// 44, 0xb0 - Ethernet
-	MCI_IRQHandler,							// 45, 0xb4 - SD/MMC card I/F
-	MCPWM_IRQHandler,						// 46, 0xb8 - Motor Control PWM
-	QEI_IRQHandler,							// 47, 0xbc - Quadrature Encoder
-	PLL1_IRQHandler,						// 48, 0xc0 - PLL1 (USB PLL)
-	USBActivity_IRQHandler,						// 49, 0xc4 - USB Activity interrupt to wakeup
-	CANActivity_IRQHandler, 					// 50, 0xc8 - CAN Activity interrupt to wakeup
-	UART4_IRQHandler, 						// 51, 0xcc - UART4
-
-	SSP2_IRQHandler, 						// 52, 0xd0 - SSP2
-	LCD_IRQHandler, 						// 53, 0xd4 - LCD
-	GPIO_IRQHandler, 						// 54, 0xd8 - GPIO
-	PWM0_IRQHandler, 						// 55, 0xdc - PWM0
-	EEPROM_IRQHandler, 						// 56, 0xe0 - EEPROM
-
-};
-
-//*****************************************************************************
-// Functions to carry out the initialization of RW and BSS data sections. These
-// are written as separate functions rather than being inlined within the
-// ResetISR() function in order to cope with MCUs with multiple banks of
-// memory.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
-	unsigned int *pulDest = (unsigned int*) start;
-	unsigned int *pulSrc = (unsigned int*) romstart;
-	unsigned int loop;
-	for (loop = 0; loop < len; loop = loop + 4)
-		*pulDest++ = *pulSrc++;
-}
-
-__attribute__ ((section(".after_vectors")))
-void bss_init(unsigned int start, unsigned int len) {
-	unsigned int *pulDest = (unsigned int*) start;
-	unsigned int loop;
-	for (loop = 0; loop < len; loop = loop + 4)
-		*pulDest++ = 0;
-}
-
-//*****************************************************************************
-// The following symbols are constructs generated by the linker, indicating
-// the location of various points in the "Global Section Table". This table is
-// created by the linker via the Code Red managed linker script mechanism. It
-// contains the load address, execution address and length of each RW data
-// section and the execution and length of each BSS (zero initialized) section.
-//*****************************************************************************
-extern unsigned int __data_section_table;
-extern unsigned int __data_section_table_end;
-extern unsigned int __bss_section_table;
-extern unsigned int __bss_section_table_end;
-
-//*****************************************************************************
-// Reset entry point for your code.
-// Sets up a simple runtime environment and initializes the C/C++
-// library.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void
-ResetISR(void) {
-
-    //
-    // Copy the data sections from flash to SRAM.
-    //
-	unsigned int LoadAddr, ExeAddr, SectionLen;
-	unsigned int *SectionTableAddr;
-
-	// Load base address of Global Section Table
-	SectionTableAddr = &__data_section_table;
-
-    // Copy the data sections from flash to SRAM.
-	while (SectionTableAddr < &__data_section_table_end) {
-		LoadAddr = *SectionTableAddr++;
-		ExeAddr = *SectionTableAddr++;
-		SectionLen = *SectionTableAddr++;
-		data_init(LoadAddr, ExeAddr, SectionLen);
-	}
-	// At this point, SectionTableAddr = &__bss_section_table;
-	// Zero fill the bss segment
-	while (SectionTableAddr < &__bss_section_table_end) {
-		ExeAddr = *SectionTableAddr++;
-		SectionLen = *SectionTableAddr++;
-		bss_init(ExeAddr, SectionLen);
-	}
-
-#if defined (__VFP_FP__) && !defined (__SOFTFP__)
-/*
- * Code to enable the Cortex-M4 FPU only included
- * if appropriate build options have been selected.
- * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
- */	 
-    // Read CPACR (located at address 0xE000ED88)
-    // Set bits 20-23 to enable CP10 and CP11 coprocessors
-    // Write back the modified value to the CPACR
-	asm volatile ("LDR.W R0, =0xE000ED88\n\t"
-                  "LDR R1, [R0]\n\t"
-                  "ORR R1, R1, #(0xF << 20)\n\t"
-                  "STR R1, [R0]");	
-#endif // (__VFP_FP__) && !(__SOFTFP__)
-
-	// Check to see if we are running the code from a non-zero
-    // address (eg RAM, external flash), in which case we need
-    // to modify the VTOR register to tell the CPU that the
-    // vector table is located at a non-0x0 address.
-
-	// Note that we do not use the CMSIS register access mechanism,
-	// as there is no guarantee that the project has been configured
-	// to use CMSIS.
-	unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
-		// CMSIS : SCB->VTOR = <address of vector table>
-		*pSCB_VTOR = (unsigned int)g_pfnVectors;
-	}
-
-//#ifdef __USE_CMSIS
-	SystemInit();
-//#endif
-
-#if defined (__cplusplus)
-	//
-	// Call C++ library initialisation
-	//
-	__libc_init_array();
-#endif
-
-#if defined (__REDLIB__)
-	// Call the Redlib library, which in turn calls main()
-	__main() ;
-#else
-	main();
-#endif
-
-	//
-	// main() shouldn't return, but if it does, we'll just enter an infinite loop 
-	//
-	while (1) {
-		;
-	}
-}
-
-//*****************************************************************************
-// Default exception handlers. Override the ones here by defining your own
-// handler routines in your application code.
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void NMI_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void HardFault_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void MemManage_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void BusFault_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void UsageFault_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void SVC_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void DebugMon_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void PendSV_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-__attribute__ ((section(".after_vectors")))
-void SysTick_Handler(void)
-{
-    while(1)
-    {
-    }
-}
-
-//*****************************************************************************
-//
-// Processor ends up here if an unexpected interrupt occurs or a specific
-// handler is not present in the application code.
-//
-//*****************************************************************************
-__attribute__ ((section(".after_vectors")))
-void IntDefaultHandler(void)
-{
-    while(1)
-    {
-    }
-}
-
-#include <stdlib.h>
-
-void *operator new(size_t size)  {return malloc(size);}
-void *operator new[](size_t size){return malloc(size);}
-
-void operator delete(void *p)   {free(p);}
-void operator delete[](void *p) {free(p);}

--- a/vendor/NXP/LPC4088/cmsis/LPC407x_8x_177x_8x.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1521 +0,0 @@
-/****************************************************************************************************//**
-* $Id$		LPC407x_8x_177x_8x.h			2012-04-25
-*//**
- * @file     LPC407x_8x_177x_8x.h
- *
- * @brief    CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for
- *           NXP LPC407x_8x_177x_8x.
- * @version  V0.7
- * @date     20. June 2012
- * @author	NXP MCU SW Application Team
-* 
-* Copyright(C) 2012, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-#ifndef __LPC407x_8x_177x_8x_H__
-#define __LPC407x_8x_177x_8x_H__
-
-#define CORE_M4
-
-// ##################
-// Code Red - excluded extern "C" as unrequired
-// ##################
-#if 0
-#ifdef __cplusplus
-extern "C" {
-#endif
-#endif
-
-
-/* -------------------------  Interrupt Number Definition  ------------------------ */
-
-typedef enum IRQn
-{
-/******  Cortex-M4 Processor Exceptions Numbers ***************************************************/
-  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
-  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
-  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
-  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
-  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
-  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
-  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
-  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
-  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
-  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
-
-/******  LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/
-  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
-  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */
-  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */
-  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */
-  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */
-  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */
-  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */
-  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */
-  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */
-  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */
-  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */
-  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */
-  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */
-  Reserved0_IRQn                = 13,       /*!< Reserved                                         */
-  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */
-  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */
-  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
-  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */
-  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */
-  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */
-  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */
-  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */
-  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */
-  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */
-  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */
-  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */
-  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */
-  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */
-  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */
-  MCI_IRQn                      = 29,       /*!< SD/MMC card I/F Interrupt                        */
-  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */
-  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */
-  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */
-  USBActivity_IRQn              = 33,       /*!< USB Activity interrupt                           */
-  CANActivity_IRQn              = 34,       /*!< CAN Activity interrupt                           */
-  UART4_IRQn                    = 35,       /*!< UART4 Interrupt                                  */
-  SSP2_IRQn                     = 36,       /*!< SSP2 Interrupt                                   */
-  LCD_IRQn                      = 37,       /*!< LCD Interrupt                                    */
-  GPIO_IRQn                     = 38,       /*!< GPIO Interrupt                                   */
-  PWM0_IRQn                     =  39,              /*!<  39  PWM0                                                             */
-  EEPROM_IRQn                   =  40,              /*!<  40  EEPROM                                                           */
-  CMP0_IRQn                     =  41,              /*!<  41  CMP0                                                             */
-  CMP1_IRQn                     =  42               /*!<  42  CMP1                                                             */
-} IRQn_Type;
-
-/* ================================================================================ */
-/* ================      Processor and Core Peripheral Section     ================ */
-/* ================================================================================ */
-#ifdef CORE_M4
-/* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */
-#define __CM4_REV                 0x0000            /*!< Cortex-M4 Core Revision                                               */
-#define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */
-#define __NVIC_PRIO_BITS               5            /*!< Number of Bits used for Priority Levels                               */
-#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
-#define __FPU_PRESENT                  1            /*!< FPU present or not                                                    */
-
-
-#include "core_cm4.h"                               /*!< Cortex-M4 processor and core peripherals                              */
-#else
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT             1         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-
-#include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */
-
-#endif
-
-#include "system_LPC407x_8x_177x_8x.h"                      /*!< LPC408x_7x System                                                     */
-
-
-
-
-
-
-/* ================================================================================ */
-/* ================       Device Specific Peripheral Section       ================ */
-/* ================================================================================ */
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#endif
-
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
-typedef struct                          /* Common Registers                   */
-{
-  __I  uint32_t IntStat;
-  __I  uint32_t IntTCStat;
-  __O  uint32_t IntTCClear;
-  __I  uint32_t IntErrStat;
-  __O  uint32_t IntErrClr;
-  __I  uint32_t RawIntTCStat;
-  __I  uint32_t RawIntErrStat;
-  __I  uint32_t EnbldChns;
-  __IO uint32_t SoftBReq;
-  __IO uint32_t SoftSReq;
-  __IO uint32_t SoftLBReq;
-  __IO uint32_t SoftLSReq;
-  __IO uint32_t Config;
-  __IO uint32_t Sync;
-} LPC_GPDMA_TypeDef;
-
-typedef struct                          /* Channel Registers                  */
-{
-  __IO uint32_t CSrcAddr;
-  __IO uint32_t CDestAddr;
-  __IO uint32_t CLLI;
-  __IO uint32_t CControl;
-  __IO uint32_t CConfig;
-} LPC_GPDMACH_TypeDef;
-
-/*------------- System Control (SC) ------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t FLASHCFG;                   /*!< Offset: 0x000 (R/W)  Flash Accelerator Configuration Register */
-       uint32_t RESERVED0[31];
-  __IO uint32_t PLL0CON;                    /*!< Offset: 0x080 (R/W)  PLL0 Control Register */
-  __IO uint32_t PLL0CFG;                    /*!< Offset: 0x084 (R/W)  PLL0 Configuration Register */
-  __I  uint32_t PLL0STAT;                   /*!< Offset: 0x088 (R/ )  PLL0 Status Register */
-  __O  uint32_t PLL0FEED;                   /*!< Offset: 0x08C ( /W)  PLL0 Feed Register */
-       uint32_t RESERVED1[4];
-  __IO uint32_t PLL1CON;                    /*!< Offset: 0x0A0 (R/W)  PLL1 Control Register */
-  __IO uint32_t PLL1CFG;                    /*!< Offset: 0x0A4 (R/W)  PLL1 Configuration Register */
-  __I  uint32_t PLL1STAT;                   /*!< Offset: 0x0A8 (R/ )  PLL1 Status Register */
-  __O  uint32_t PLL1FEED;                   /*!< Offset: 0x0AC ( /W)  PLL1 Feed Register */
-       uint32_t RESERVED2[4];
-  __IO uint32_t PCON;                       /*!< Offset: 0x0C0 (R/W)  Power Control Register */
-  __IO uint32_t PCONP;                      /*!< Offset: 0x0C4 (R/W)  Power Control for Peripherals Register */
-  __IO uint32_t PCONP1;                      /*!< Offset: 0x0C8 (R/W)  Power Control for Peripherals Register */
-       uint32_t RESERVED3[13];
-  __IO uint32_t EMCCLKSEL;                  /*!< Offset: 0x100 (R/W)  External Memory Controller Clock Selection Register */
-  __IO uint32_t CCLKSEL;                    /*!< Offset: 0x104 (R/W)  CPU Clock Selection Register */
-  __IO uint32_t USBCLKSEL;                  /*!< Offset: 0x108 (R/W)  USB Clock Selection Register */
-  __IO uint32_t CLKSRCSEL;                  /*!< Offset: 0x10C (R/W)  Clock Source Select Register */
-  __IO uint32_t	CANSLEEPCLR;                /*!< Offset: 0x110 (R/W)  CAN Sleep Clear Register */
-  __IO uint32_t	CANWAKEFLAGS;               /*!< Offset: 0x114 (R/W)  CAN Wake-up Flags Register */
-       uint32_t RESERVED4[10];
-  __IO uint32_t EXTINT;                     /*!< Offset: 0x140 (R/W)  External Interrupt Flag Register */
-       uint32_t RESERVED5[1];
-  __IO uint32_t EXTMODE;                    /*!< Offset: 0x148 (R/W)  External Interrupt Mode Register */
-  __IO uint32_t EXTPOLAR;                   /*!< Offset: 0x14C (R/W)  External Interrupt Polarity Register */
-       uint32_t RESERVED6[12];
-  __IO uint32_t RSID;                       /*!< Offset: 0x180 (R/W)  Reset Source Identification Register */
-       uint32_t RESERVED7[7];
-  __IO uint32_t SCS;                        /*!< Offset: 0x1A0 (R/W)  System Controls and Status Register */
-  __IO uint32_t IRCTRIM;                    /*!< Offset: 0x1A4 (R/W) Clock Dividers                     */
-  __IO uint32_t PCLKSEL;                    /*!< Offset: 0x1A8 (R/W)  Peripheral Clock Selection Register */
-       uint32_t RESERVED8;					
-  __IO uint32_t PBOOST;						/*!< Offset: 0x1B0 (R/W)  Power Boost control register */	   
-  __IO uint32_t SPIFICLKSEL;					
-  __IO uint32_t LCD_CFG;                    /*!< Offset: 0x1B8 (R/W)  LCD Configuration and clocking control Register */
-       uint32_t RESERVED10[1];
-  __IO uint32_t USBIntSt;                   /*!< Offset: 0x1C0 (R/W)  USB Interrupt Status Register */
-  __IO uint32_t DMAREQSEL;                  /*!< Offset: 0x1C4 (R/W)  DMA Request Select Register */
-  __IO uint32_t CLKOUTCFG;                  /*!< Offset: 0x1C8 (R/W)  Clock Output Configuration Register */
-  __IO uint32_t RSTCON0;                    /*!< Offset: 0x1CC (R/W)  RESET Control0 Register */
-  __IO uint32_t RSTCON1;                    /*!< Offset: 0x1D0 (R/W)  RESET Control1 Register */
-       uint32_t RESERVED11[2];
-  __IO uint32_t EMCDLYCTL;                  /*!< Offset: 0x1DC (R/W) SDRAM programmable delays          */
-  __IO uint32_t EMCCAL;                     /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
- } LPC_SC_TypeDef;
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
-typedef struct
-{
-  __IO uint32_t MAC1;                   /* MAC Registers                      */
-  __IO uint32_t MAC2;
-  __IO uint32_t IPGT;
-  __IO uint32_t IPGR;
-  __IO uint32_t CLRT;
-  __IO uint32_t MAXF;
-  __IO uint32_t SUPP;
-  __IO uint32_t TEST;
-  __IO uint32_t MCFG;
-  __IO uint32_t MCMD;
-  __IO uint32_t MADR;
-  __O  uint32_t MWTD;
-  __I  uint32_t MRDD;
-  __I  uint32_t MIND;
-       uint32_t RESERVED0[2];
-  __IO uint32_t SA0;
-  __IO uint32_t SA1;
-  __IO uint32_t SA2;
-       uint32_t RESERVED1[45];
-  __IO uint32_t Command;                /* Control Registers                  */
-  __I  uint32_t Status;
-  __IO uint32_t RxDescriptor;
-  __IO uint32_t RxStatus;
-  __IO uint32_t RxDescriptorNumber;
-  __I  uint32_t RxProduceIndex;
-  __IO uint32_t RxConsumeIndex;
-  __IO uint32_t TxDescriptor;
-  __IO uint32_t TxStatus;
-  __IO uint32_t TxDescriptorNumber;
-  __IO uint32_t TxProduceIndex;
-  __I  uint32_t TxConsumeIndex;
-       uint32_t RESERVED2[10];
-  __I  uint32_t TSV0;
-  __I  uint32_t TSV1;
-  __I  uint32_t RSV;
-       uint32_t RESERVED3[3];
-  __IO uint32_t FlowControlCounter;
-  __I  uint32_t FlowControlStatus;
-       uint32_t RESERVED4[34];
-  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
-  __I  uint32_t RxFilterWoLStatus;
-  __O  uint32_t RxFilterWoLClear;
-       uint32_t RESERVED5;
-  __IO uint32_t HashFilterL;
-  __IO uint32_t HashFilterH;
-       uint32_t RESERVED6[882];
-  __I  uint32_t IntStatus;              /* Module Control Registers           */
-  __IO uint32_t IntEnable;
-  __O  uint32_t IntClear;
-  __O  uint32_t IntSet;
-       uint32_t RESERVED7;
-  __IO uint32_t PowerDown;
-       uint32_t RESERVED8;
-  __IO uint32_t Module_ID;
-} LPC_EMAC_TypeDef;
-
-/*------------- LCD controller (LCD) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t TIMH;                   /* LCD Registers                      */
-  __IO uint32_t TIMV;
-  __IO uint32_t POL;
-  __IO uint32_t LE;
-  __IO uint32_t UPBASE;
-  __IO uint32_t LPBASE;
-  __IO uint32_t CTRL;
-  __IO uint32_t INTMSK;
-  __I  uint32_t INTRAW;
-  __I  uint32_t INTSTAT;
-  __O  uint32_t INTCLR;
-  __I  uint32_t UPCURR;
-  __I  uint32_t LPCURR;
-       uint32_t RESERVED0[115];
-  __IO uint32_t PAL[128];
-       uint32_t RESERVED1[256];
-  __IO uint32_t CRSR_IMG[256];
-  __IO uint32_t CRSR_CTRL;
-  __IO uint32_t CRSR_CFG;
-  __IO uint32_t CRSR_PAL0;
-  __IO uint32_t CRSR_PAL1;
-  __IO uint32_t CRSR_XY;
-  __IO uint32_t CRSR_CLIP;
-       uint32_t RESERVED2[2];
-  __IO uint32_t CRSR_INTMSK;
-  __O  uint32_t CRSR_INTCLR;
-  __I  uint32_t CRSR_INTRAW;
-  __I  uint32_t CRSR_INTSTAT;
-} LPC_LCD_TypeDef;
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-typedef struct
-{
-  __I  uint32_t Revision;             /* USB Host Registers                 */
-  __IO uint32_t Control;
-  __IO uint32_t CommandStatus;
-  __IO uint32_t InterruptStatus;
-  __IO uint32_t InterruptEnable;
-  __IO uint32_t InterruptDisable;
-  __IO uint32_t HCCA;
-  __I  uint32_t PeriodCurrentED;
-  __IO uint32_t ControlHeadED;
-  __IO uint32_t ControlCurrentED;
-  __IO uint32_t BulkHeadED;
-  __IO uint32_t BulkCurrentED;
-  __I  uint32_t DoneHead;
-  __IO uint32_t FmInterval;
-  __I  uint32_t FmRemaining;
-  __I  uint32_t FmNumber;
-  __IO uint32_t PeriodicStart;
-  __IO uint32_t LSTreshold;
-  __IO uint32_t RhDescriptorA;
-  __IO uint32_t RhDescriptorB;
-  __IO uint32_t RhStatus;
-  __IO uint32_t RhPortStatus1;
-  __IO uint32_t RhPortStatus2;
-       uint32_t RESERVED0[40];
-  __I  uint32_t Module_ID;
-
-  __I  uint32_t IntSt;               /* USB On-The-Go Registers            */
-  __IO uint32_t IntEn;
-  __O  uint32_t IntSet;
-  __O  uint32_t IntClr;
-  __IO uint32_t StCtrl;
-  __IO uint32_t Tmr;
-       uint32_t RESERVED1[58];
-
-  __I  uint32_t DevIntSt;            /* USB Device Interrupt Registers     */
-  __IO uint32_t DevIntEn;
-  __O  uint32_t DevIntClr;
-  __O  uint32_t DevIntSet;
-
-  __O  uint32_t CmdCode;             /* USB Device SIE Command Registers   */
-  __I  uint32_t CmdData;
-
-  __I  uint32_t RxData;              /* USB Device Transfer Registers      */
-  __O  uint32_t TxData;
-  __I  uint32_t RxPLen;
-  __O  uint32_t TxPLen;
-  __IO uint32_t Ctrl;
-  __O  uint32_t DevIntPri;
-
-  __I  uint32_t EpIntSt;             /* USB Device Endpoint Interrupt Regs */
-  __IO uint32_t EpIntEn;
-  __O  uint32_t EpIntClr;
-  __O  uint32_t EpIntSet;
-  __O  uint32_t EpIntPri;
-
-  __IO uint32_t ReEp;                /* USB Device Endpoint Realization Reg*/
-  __O  uint32_t EpInd;
-  __IO uint32_t MaxPSize;
-
-  __I  uint32_t DMARSt;              /* USB Device DMA Registers           */
-  __O  uint32_t DMARClr;
-  __O  uint32_t DMARSet;
-       uint32_t RESERVED2[9];
-  __IO uint32_t UDCAH;
-  __I  uint32_t EpDMASt;
-  __O  uint32_t EpDMAEn;
-  __O  uint32_t EpDMADis;
-  __I  uint32_t DMAIntSt;
-  __IO uint32_t DMAIntEn;
-       uint32_t RESERVED3[2];
-  __I  uint32_t EoTIntSt;
-  __O  uint32_t EoTIntClr;
-  __O  uint32_t EoTIntSet;
-  __I  uint32_t NDDRIntSt;
-  __O  uint32_t NDDRIntClr;
-  __O  uint32_t NDDRIntSet;
-  __I  uint32_t SysErrIntSt;
-  __O  uint32_t SysErrIntClr;
-  __O  uint32_t SysErrIntSet;
-       uint32_t RESERVED4[15];
-
-  union {
-  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
-  __O  uint32_t I2C_TX;
-  };
-  __IO  uint32_t I2C_STS;
-  __IO uint32_t I2C_CTL;
-  __IO uint32_t I2C_CLKHI;
-  __O  uint32_t I2C_CLKLO;
-       uint32_t RESERVED5[824];
-
-  union {
-  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
-  __IO uint32_t OTGClkCtrl;
-  };
-  union {
-  __I  uint32_t USBClkSt;
-  __I  uint32_t OTGClkSt;
-  };
-} LPC_USB_TypeDef;
-
-/*------------- CRC Engine (CRC) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t MODE;
-  __IO uint32_t SEED;
-  union {
-  __I  uint32_t SUM;
-  struct {
-  __O  uint32_t DATA;
-  } WR_DATA_DWORD;
-  
-  struct {
-  __O  uint16_t DATA;
-       uint16_t RESERVED;
-  }WR_DATA_WORD;
-  
-  struct {
-  __O  uint8_t  DATA;
-       uint8_t  RESERVED[3];
-  	}WR_DATA_BYTE;
-  };
-} LPC_CRC_TypeDef;
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-typedef struct
-{
-  __IO uint32_t DIR;
-       uint32_t RESERVED0[3];
-  __IO uint32_t MASK;
-  __IO uint32_t PIN;
-  __IO uint32_t SET;
-  __O  uint32_t CLR;
-} LPC_GPIO_TypeDef;
-
-typedef struct
-{
-  __I  uint32_t IntStatus;
-  __I  uint32_t IO0IntStatR;
-  __I  uint32_t IO0IntStatF;
-  __O  uint32_t IO0IntClr;
-  __IO uint32_t IO0IntEnR;
-  __IO uint32_t IO0IntEnF;
-       uint32_t RESERVED0[3];
-  __I  uint32_t IO2IntStatR;
-  __I  uint32_t IO2IntStatF;
-  __O  uint32_t IO2IntClr;
-  __IO uint32_t IO2IntEnR;
-  __IO uint32_t IO2IntEnF;
-} LPC_GPIOINT_TypeDef;
-
-/*------------- External Memory Controller (EMC) -----------------------------*/
-typedef struct
-{
-  __IO uint32_t Control;
-  __I  uint32_t Status;
-  __IO uint32_t Config;
-       uint32_t RESERVED0[5];
-  __IO uint32_t DynamicControl;
-  __IO uint32_t DynamicRefresh;
-  __IO uint32_t DynamicReadConfig;
-       uint32_t RESERVED1[1];
-  __IO uint32_t DynamicRP;
-  __IO uint32_t DynamicRAS;
-  __IO uint32_t DynamicSREX;
-  __IO uint32_t DynamicAPR;
-  __IO uint32_t DynamicDAL;
-  __IO uint32_t DynamicWR;
-  __IO uint32_t DynamicRC;
-  __IO uint32_t DynamicRFC;
-  __IO uint32_t DynamicXSR;
-  __IO uint32_t DynamicRRD;
-  __IO uint32_t DynamicMRD;
-       uint32_t RESERVED2[9];
-  __IO uint32_t StaticExtendedWait;
-       uint32_t RESERVED3[31];
-  __IO uint32_t DynamicConfig0;
-  __IO uint32_t DynamicRasCas0;
-       uint32_t RESERVED4[6];
-  __IO uint32_t DynamicConfig1;
-  __IO uint32_t DynamicRasCas1;
-       uint32_t RESERVED5[6];
-  __IO uint32_t DynamicConfig2;
-  __IO uint32_t DynamicRasCas2;
-       uint32_t RESERVED6[6];
-  __IO uint32_t DynamicConfig3;
-  __IO uint32_t DynamicRasCas3;
-       uint32_t RESERVED7[38];
-  __IO uint32_t StaticConfig0;
-  __IO uint32_t StaticWaitWen0;
-  __IO uint32_t StaticWaitOen0;
-  __IO uint32_t StaticWaitRd0;
-  __IO uint32_t StaticWaitPage0;
-  __IO uint32_t StaticWaitWr0;
-  __IO uint32_t StaticWaitTurn0;
-       uint32_t RESERVED8[1];
-  __IO uint32_t StaticConfig1;
-  __IO uint32_t StaticWaitWen1;
-  __IO uint32_t StaticWaitOen1;
-  __IO uint32_t StaticWaitRd1;
-  __IO uint32_t StaticWaitPage1;
-  __IO uint32_t StaticWaitWr1;
-  __IO uint32_t StaticWaitTurn1;
-       uint32_t RESERVED9[1];
-  __IO uint32_t StaticConfig2;
-  __IO uint32_t StaticWaitWen2;
-  __IO uint32_t StaticWaitOen2;
-  __IO uint32_t StaticWaitRd2;
-  __IO uint32_t StaticWaitPage2;
-  __IO uint32_t StaticWaitWr2;
-  __IO uint32_t StaticWaitTurn2;
-       uint32_t RESERVED10[1];
-  __IO uint32_t StaticConfig3;
-  __IO uint32_t StaticWaitWen3;
-  __IO uint32_t StaticWaitOen3;
-  __IO uint32_t StaticWaitRd3;
-  __IO uint32_t StaticWaitPage3;
-  __IO uint32_t StaticWaitWr3;
-  __IO uint32_t StaticWaitTurn3;
-} LPC_EMC_TypeDef;
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  MOD;
-       uint8_t  RESERVED0[3];
-  __IO uint32_t TC;
-  __O  uint8_t  FEED;
-       uint8_t  RESERVED1[3];
-  __I  uint32_t TV;
-       uint32_t RESERVED2;
-  __IO uint32_t WARNINT;
-  __IO uint32_t WINDOW;
-} LPC_WDT_TypeDef;
-
-/*------------- Timer (TIM) --------------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */
-  __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */
-  __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */
-  __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
-  __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
-  __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
-  __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */
-  __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */
-  __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */
-  __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */
-  __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */
-  __I  uint32_t CR1;					/*!< Offset: 0x030 Capture Register 1 (R/ ) */
-       uint32_t RESERVED0[2];
-  __IO uint32_t EMR;                    /*!< Offset: 0x03C External Match Register (R/W) */
-       uint32_t RESERVED1[12];
-  __IO uint32_t CTCR;                   /*!< Offset: 0x070 Count Control Register (R/W) */
-} LPC_TIM_TypeDef;
-
-
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */
-  __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */
-  __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */
-  __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
-  __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
-  __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
-  __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */
-  __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */
-  __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */
-  __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */
-  __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */
-  __I  uint32_t CR1;					/*!< Offset: 0x030 Capture Register 1 (R/ ) */
-  __I  uint32_t CR2;					/*!< Offset: 0x034 Capture Register 2 (R/ ) */
-  __I  uint32_t CR3;					/*!< Offset: 0x038 Capture Register 3 (R/ ) */
-       uint32_t RESERVED0;
-  __IO uint32_t MR4;					/*!< Offset: 0x040 Match Register 4 (R/W) */
-  __IO uint32_t MR5;					/*!< Offset: 0x044 Match Register 5 (R/W) */
-  __IO uint32_t MR6;					/*!< Offset: 0x048 Match Register 6 (R/W) */
-  __IO uint32_t PCR;					/*!< Offset: 0x04C PWM Control Register (R/W) */
-  __IO uint32_t LER;					/*!< Offset: 0x050 Load Enable Register (R/W) */
-       uint32_t RESERVED1[7];
-  __IO uint32_t CTCR;					/*!< Offset: 0x070 Counter Control Register (R/W) */
-} LPC_PWM_TypeDef;
-
-/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
-/* There are three types of UARTs on the chip:
-(1) UART0,UART2, and UART3 are the standard UART.
-(2) UART1 is the standard with modem capability.
-(3) USART(UART4) is the sync/async UART with smart card capability.
-More details can be found on the Users Manual. */
-
-#if 0
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[7];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED2[7];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED3[3];
-  __IO uint32_t ACR;
-  __IO uint8_t  ICR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  FDR;
-       uint8_t  RESERVED5[7];
-  __IO uint8_t  TER;
-       uint8_t  RESERVED6[39];
-  __I  uint8_t  FIFOLVL;
-} LPC_UART_TypeDef;
-#else
-typedef struct
-{
-	union
-	{
-		__I  uint8_t  RBR;
-		__O  uint8_t  THR;
-		__IO uint8_t  DLL;
-		uint32_t RESERVED0;
-	};
-	union
-	{
-		__IO uint8_t  DLM;
-		__IO uint32_t IER;
-	};
-	union
-	{
-		__I  uint32_t IIR;
-		__O  uint8_t  FCR;
-	};
-	__IO uint8_t  LCR;
-	uint8_t  RESERVED1[7];//Reserved
-	__I  uint8_t  LSR;
-	uint8_t  RESERVED2[7];//Reserved
-	__IO uint8_t  SCR;
-	uint8_t  RESERVED3[3];//Reserved
-	__IO uint32_t ACR;
-	__IO uint8_t  ICR;
-	uint8_t  RESERVED4[3];//Reserved
-	__IO uint8_t  FDR;
-	uint8_t  RESERVED5[7];//Reserved
-	__IO uint8_t  TER;
-	uint8_t  RESERVED8[27];//Reserved
-	__IO uint8_t  RS485CTRL;
-	uint8_t  RESERVED9[3];//Reserved
-	__IO uint8_t  ADRMATCH;
-	uint8_t  RESERVED10[3];//Reserved
-	__IO uint8_t  RS485DLY;
-	uint8_t  RESERVED11[3];//Reserved
-	__I  uint8_t  FIFOLVL;
-}LPC_UART_TypeDef;
-#endif
-
-
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  MCR;
-       uint8_t  RESERVED2[3];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED3[3];
-  __I  uint8_t  MSR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED5[3];
-  __IO uint32_t ACR;
-       uint32_t RESERVED6;
-  __IO uint32_t FDR;
-       uint32_t RESERVED7;
-  __IO uint8_t  TER;
-       uint8_t  RESERVED8[27];
-  __IO uint8_t  RS485CTRL;
-       uint8_t  RESERVED9[3];
-  __IO uint8_t  ADRMATCH;
-       uint8_t  RESERVED10[3];
-  __IO uint8_t  RS485DLY;
-       uint8_t  RESERVED11[3];
-  __I  uint8_t  FIFOLVL;
-} LPC_UART1_TypeDef;
-
-typedef struct
-{
-  union {
-  __I  uint32_t  RBR;                   /*!< Offset: 0x000 Receiver Buffer  Register (R/ ) */
-  __O  uint32_t  THR;                   /*!< Offset: 0x000 Transmit Holding Register ( /W) */
-  __IO uint32_t  DLL;                   /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
-  };
-  union {
-  __IO uint32_t  DLM;                   /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
-  __IO uint32_t  IER;                   /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
-  };
-  union {
-  __I  uint32_t  IIR;                   /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
-  __O  uint32_t  FCR;                   /*!< Offset: 0x008 FIFO Control Register ( /W) */
-  };
-  __IO uint32_t  LCR;                   /*!< Offset: 0x00C Line Control Register (R/W) */
-  __IO uint32_t  MCR;                   /*!< Offset: 0x010 Modem control Register (R/W) */
-  __I  uint32_t  LSR;                   /*!< Offset: 0x014 Line Status Register (R/ ) */
-  __I  uint32_t  MSR;                   /*!< Offset: 0x018 Modem status Register (R/ ) */
-  __IO uint32_t  SCR;                   /*!< Offset: 0x01C Scratch Pad Register (R/W) */
-  __IO uint32_t  ACR;                   /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
-  __IO uint32_t  ICR;                   /*!< Offset: 0x024 irDA Control Register (R/W) */
-  __IO uint32_t  FDR;                   /*!< Offset: 0x028 Fractional Divider Register (R/W) */
-  __IO uint32_t  OSR;                   /*!< Offset: 0x02C Over sampling Register (R/W) */
-  __O  uint32_t  POP;                   /*!< Offset: 0x030 NHP Pop Register (W) */
-  __IO uint32_t  MODE;                  /*!< Offset: 0x034 NHP Mode selection Register (W) */
-       uint32_t  RESERVED0[2];
-  __IO uint32_t  HDEN;                  /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
-       uint32_t  RESERVED1;
-  __IO uint32_t  SCI_CTRL;				/*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
-  __IO uint32_t  RS485CTRL;             /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
-  __IO uint32_t  ADRMATCH;              /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
-  __IO uint32_t  RS485DLY;              /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
-  __IO uint32_t  SYNCCTRL;              /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
-  __IO uint32_t  TER;                   /*!< Offset: 0x05C Transmit Enable Register (R/W) */
-       uint32_t  RESERVED2[989];
-  __I  uint32_t  CFG;                   /*!< Offset: 0xFD4 Configuration Register (R) */
-  __O  uint32_t  INTCE;                 /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
-  __O  uint32_t  INTSE;                 /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
-  __I  uint32_t  INTS;                  /*!< Offset: 0xFE0 Interrupt Status Register (R) */
-  __I  uint32_t  INTE;                  /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
-  __O  uint32_t  INTCS;                 /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
-  __O  uint32_t  INTSS;                 /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
-       uint32_t  RESERVED3[3];
-  __I  uint32_t  MID;                   /*!< Offset: 0xFFC Module Identification Register (R) */
-} LPC_UART4_TypeDef;
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-typedef struct
-{
-  __IO uint32_t CONSET;                 /*!< Offset: 0x000 I2C Control Set Register (R/W) */
-  __I  uint32_t STAT;                   /*!< Offset: 0x004 I2C Status Register (R/ ) */
-  __IO uint32_t DAT;                    /*!< Offset: 0x008 I2C Data Register (R/W) */
-  __IO uint32_t ADR0;                   /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
-  __IO uint32_t SCLH;                   /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
-  __IO uint32_t SCLL;                   /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
-  __O  uint32_t CONCLR;                 /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
-  __IO uint32_t MMCTRL;                 /*!< Offset: 0x01C Monitor mode control register (R/W) */
-  __IO uint32_t ADR1;                   /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
-  __IO uint32_t ADR2;                   /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
-  __IO uint32_t ADR3;                   /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
-  __I  uint32_t DATA_BUFFER;            /*!< Offset: 0x02C Data buffer register ( /W) */
-  __IO uint32_t MASK0;                  /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
-  __IO uint32_t MASK1;                  /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
-  __IO uint32_t MASK2;                  /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
-  __IO uint32_t MASK3;                  /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
-} LPC_I2C_TypeDef;
-
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  ILR;
-       uint8_t  RESERVED0[7];
-  __IO uint8_t  CCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  CIIR;
-       uint8_t  RESERVED2[3];
-  __IO uint8_t  AMR;
-       uint8_t  RESERVED3[3];
-  __I  uint32_t CTIME0;
-  __I  uint32_t CTIME1;
-  __I  uint32_t CTIME2;
-  __IO uint8_t  SEC;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  MIN;
-       uint8_t  RESERVED5[3];
-  __IO uint8_t  HOUR;
-       uint8_t  RESERVED6[3];
-  __IO uint8_t  DOM;
-       uint8_t  RESERVED7[3];
-  __IO uint8_t  DOW;
-       uint8_t  RESERVED8[3];
-  __IO uint16_t DOY;
-       uint16_t RESERVED9;
-  __IO uint8_t  MONTH;
-       uint8_t  RESERVED10[3];
-  __IO uint16_t YEAR;
-       uint16_t RESERVED11;
-  __IO uint32_t CALIBRATION;
-  __IO uint32_t GPREG0;
-  __IO uint32_t GPREG1;
-  __IO uint32_t GPREG2;
-  __IO uint32_t GPREG3;
-  __IO uint32_t GPREG4;
-  __IO uint8_t  RTC_AUXEN;
-       uint8_t  RESERVED12[3];
-  __IO uint8_t  RTC_AUX;
-       uint8_t  RESERVED13[3];
-  __IO uint8_t  ALSEC;
-       uint8_t  RESERVED14[3];
-  __IO uint8_t  ALMIN;
-       uint8_t  RESERVED15[3];
-  __IO uint8_t  ALHOUR;
-       uint8_t  RESERVED16[3];
-  __IO uint8_t  ALDOM;
-       uint8_t  RESERVED17[3];
-  __IO uint8_t  ALDOW;
-       uint8_t  RESERVED18[3];
-  __IO uint16_t ALDOY;
-       uint16_t RESERVED19;
-  __IO uint8_t  ALMON;
-       uint8_t  RESERVED20[3];
-  __IO uint16_t ALYEAR;
-       uint16_t RESERVED21;
-  __IO uint32_t ERSTATUS;
-  __IO uint32_t ERCONTROL;
-  __IO uint32_t ERCOUNTERS;
-       uint32_t RESERVED22;
-  __IO uint32_t ERFIRSTSTAMP0;
-  __IO uint32_t ERFIRSTSTAMP1;
-  __IO uint32_t ERFIRSTSTAMP2;
-       uint32_t RESERVED23;
-  __IO uint32_t ERLASTSTAMP0;
-  __IO uint32_t ERLASTSTAMP1;
-  __IO uint32_t ERLASTSTAMP2;
-} LPC_RTC_TypeDef;
-
-
-
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/
-typedef struct
-{
-  __IO uint32_t P0_0;				/* 0x000 */
-  __IO uint32_t P0_1;
-  __IO uint32_t P0_2;
-  __IO uint32_t P0_3;
-  __IO uint32_t P0_4;
-  __IO uint32_t P0_5;
-  __IO uint32_t P0_6;
-  __IO uint32_t P0_7;
-
-  __IO uint32_t P0_8;				/* 0x020 */
-  __IO uint32_t P0_9;
-  __IO uint32_t P0_10;
-  __IO uint32_t P0_11;
-  __IO uint32_t P0_12;
-  __IO uint32_t P0_13;
-  __IO uint32_t P0_14;
-  __IO uint32_t P0_15;
-
-  __IO uint32_t P0_16;				/* 0x040 */
-  __IO uint32_t P0_17;
-  __IO uint32_t P0_18;
-  __IO uint32_t P0_19;
-  __IO uint32_t P0_20;
-  __IO uint32_t P0_21;
-  __IO uint32_t P0_22;
-  __IO uint32_t P0_23;
-
-  __IO uint32_t P0_24;				/* 0x060 */
-  __IO uint32_t P0_25;
-  __IO uint32_t P0_26;
-  __IO uint32_t P0_27;
-  __IO uint32_t P0_28;
-  __IO uint32_t P0_29;
-  __IO uint32_t P0_30;
-  __IO uint32_t P0_31;
-
-  __IO uint32_t P1_0;				/* 0x080 */
-  __IO uint32_t P1_1;
-  __IO uint32_t P1_2;
-  __IO uint32_t P1_3;
-  __IO uint32_t P1_4;
-  __IO uint32_t P1_5;
-  __IO uint32_t P1_6;
-  __IO uint32_t P1_7;
-
-  __IO uint32_t P1_8;				/* 0x0A0 */
-  __IO uint32_t P1_9;
-  __IO uint32_t P1_10;
-  __IO uint32_t P1_11;
-  __IO uint32_t P1_12;
-  __IO uint32_t P1_13;
-  __IO uint32_t P1_14;
-  __IO uint32_t P1_15;
-
-  __IO uint32_t P1_16;				/* 0x0C0 */
-  __IO uint32_t P1_17;
-  __IO uint32_t P1_18;
-  __IO uint32_t P1_19;
-  __IO uint32_t P1_20;
-  __IO uint32_t P1_21;
-  __IO uint32_t P1_22;
-  __IO uint32_t P1_23;
-
-  __IO uint32_t P1_24;				/* 0x0E0 */
-  __IO uint32_t P1_25;
-  __IO uint32_t P1_26;
-  __IO uint32_t P1_27;
-  __IO uint32_t P1_28;
-  __IO uint32_t P1_29;
-  __IO uint32_t P1_30;
-  __IO uint32_t P1_31;
-
-  __IO uint32_t P2_0;				/* 0x100 */
-  __IO uint32_t P2_1;
-  __IO uint32_t P2_2;
-  __IO uint32_t P2_3;
-  __IO uint32_t P2_4;
-  __IO uint32_t P2_5;
-  __IO uint32_t P2_6;
-  __IO uint32_t P2_7;
-
-  __IO uint32_t P2_8;				/* 0x120 */
-  __IO uint32_t P2_9;
-  __IO uint32_t P2_10;
-  __IO uint32_t P2_11;
-  __IO uint32_t P2_12;
-  __IO uint32_t P2_13;
-  __IO uint32_t P2_14;
-  __IO uint32_t P2_15;
-
-  __IO uint32_t P2_16;				/* 0x140 */
-  __IO uint32_t P2_17;
-  __IO uint32_t P2_18;
-  __IO uint32_t P2_19;
-  __IO uint32_t P2_20;
-  __IO uint32_t P2_21;
-  __IO uint32_t P2_22;
-  __IO uint32_t P2_23;
-
-  __IO uint32_t P2_24;				/* 0x160 */
-  __IO uint32_t P2_25;
-  __IO uint32_t P2_26;
-  __IO uint32_t P2_27;
-  __IO uint32_t P2_28;
-  __IO uint32_t P2_29;
-  __IO uint32_t P2_30;
-  __IO uint32_t P2_31;
-
-  __IO uint32_t P3_0;				/* 0x180 */
-  __IO uint32_t P3_1;
-  __IO uint32_t P3_2;
-  __IO uint32_t P3_3;
-  __IO uint32_t P3_4;
-  __IO uint32_t P3_5;
-  __IO uint32_t P3_6;
-  __IO uint32_t P3_7;
-
-  __IO uint32_t P3_8;				/* 0x1A0 */
-  __IO uint32_t P3_9;
-  __IO uint32_t P3_10;
-  __IO uint32_t P3_11;
-  __IO uint32_t P3_12;
-  __IO uint32_t P3_13;
-  __IO uint32_t P3_14;
-  __IO uint32_t P3_15;
-
-  __IO uint32_t P3_16;				/* 0x1C0 */
-  __IO uint32_t P3_17;
-  __IO uint32_t P3_18;
-  __IO uint32_t P3_19;
-  __IO uint32_t P3_20;
-  __IO uint32_t P3_21;
-  __IO uint32_t P3_22;
-  __IO uint32_t P3_23;
-
-  __IO uint32_t P3_24;				/* 0x1E0 */
-  __IO uint32_t P3_25;
-  __IO uint32_t P3_26;
-  __IO uint32_t P3_27;
-  __IO uint32_t P3_28;
-  __IO uint32_t P3_29;
-  __IO uint32_t P3_30;
-  __IO uint32_t P3_31;
-
-  __IO uint32_t P4_0;				/* 0x200 */
-  __IO uint32_t P4_1;
-  __IO uint32_t P4_2;
-  __IO uint32_t P4_3;
-  __IO uint32_t P4_4;
-  __IO uint32_t P4_5;
-  __IO uint32_t P4_6;
-  __IO uint32_t P4_7;
-
-  __IO uint32_t P4_8;				/* 0x220 */
-  __IO uint32_t P4_9;
-  __IO uint32_t P4_10;
-  __IO uint32_t P4_11;
-  __IO uint32_t P4_12;
-  __IO uint32_t P4_13;
-  __IO uint32_t P4_14;
-  __IO uint32_t P4_15;
-
-  __IO uint32_t P4_16;				/* 0x240 */
-  __IO uint32_t P4_17;
-  __IO uint32_t P4_18;
-  __IO uint32_t P4_19;
-  __IO uint32_t P4_20;
-  __IO uint32_t P4_21;
-  __IO uint32_t P4_22;
-  __IO uint32_t P4_23;
-
-  __IO uint32_t P4_24;				/* 0x260 */
-  __IO uint32_t P4_25;
-  __IO uint32_t P4_26;
-  __IO uint32_t P4_27;
-  __IO uint32_t P4_28;
-  __IO uint32_t P4_29;
-  __IO uint32_t P4_30;
-  __IO uint32_t P4_31;
-
-  __IO uint32_t P5_0;				/* 0x280 */
-  __IO uint32_t P5_1;
-  __IO uint32_t P5_2;
-  __IO uint32_t P5_3;
-  __IO uint32_t P5_4;				/* 0x290 */
-} LPC_IOCON_TypeDef;
-
-
-
-
-
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-typedef struct
-{
-  __IO uint32_t CR0;                    /*!< Offset: 0x000 Control Register 0 (R/W) */
-  __IO uint32_t CR1;                    /*!< Offset: 0x004 Control Register 1 (R/W) */
-  __IO uint32_t DR;                     /*!< Offset: 0x008 Data Register (R/W) */
-  __I  uint32_t SR;                     /*!< Offset: 0x00C Status Registe (R/ ) */
-  __IO uint32_t CPSR;                   /*!< Offset: 0x010 Clock Prescale Register (R/W) */
-  __IO uint32_t IMSC;                   /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
-  __IO uint32_t RIS;                    /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
-  __IO uint32_t MIS;                    /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
-  __IO uint32_t ICR;                    /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
-  __IO uint32_t DMACR;
-} LPC_SSP_TypeDef;
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t CR;                     /*!< Offset: 0x000       A/D Control Register (R/W) */
-  __IO uint32_t GDR;                    /*!< Offset: 0x004       A/D Global Data Register (R/W) */
-       uint32_t RESERVED0;
-  __IO uint32_t INTEN;                  /*!< Offset: 0x00C       A/D Interrupt Enable Register (R/W) */
-  __IO uint32_t DR[8];                  /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
-  __I  uint32_t STAT;                   /*!< Offset: 0x030       A/D Status Register (R/ ) */
-  __IO uint32_t ADTRM;
-} LPC_ADC_TypeDef;
-
-/*------------- Controller Area Network (CAN) --------------------------------*/
-typedef struct
-{
-  __IO uint32_t mask[512];              /* ID Masks                           */
-} LPC_CANAF_RAM_TypeDef;
-
-typedef struct                          /* Acceptance Filter Registers        */
-{
-	///Offset: 0x00000000 - Acceptance Filter Register
-	__IO uint32_t AFMR;
-
-	///Offset: 0x00000004 - Standard Frame Individual Start Address Register
-	__IO uint32_t SFF_sa;
-
-	///Offset: 0x00000008 - Standard Frame Group Start Address Register
-	__IO uint32_t SFF_GRP_sa;
-
-	///Offset: 0x0000000C - Extended Frame Start Address Register
-	__IO uint32_t EFF_sa;
-
-	///Offset: 0x00000010 - Extended Frame Group Start Address Register
-	__IO uint32_t EFF_GRP_sa;
-
-	///Offset: 0x00000014 - End of AF Tables register
-	__IO uint32_t ENDofTable;
-
-	///Offset: 0x00000018 - LUT Error Address register
-	__I  uint32_t LUTerrAd;
-
-	///Offset: 0x0000001C - LUT Error Register
-	__I  uint32_t LUTerr;
-
-	///Offset: 0x00000020 - CAN Central Transmit Status Register
-	__IO uint32_t FCANIE;
-
-	///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
-	__IO uint32_t FCANIC0;
-
-	///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
-	__IO uint32_t FCANIC1;
-} LPC_CANAF_TypeDef;
-
-typedef struct                          /* Central Registers                  */
-{
-  __I  uint32_t TxSR;
-  __I  uint32_t RxSR;
-  __I  uint32_t MSR;
-} LPC_CANCR_TypeDef;
-
-typedef struct                          /* Controller Registers               */
-{
-	///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
-	__IO uint32_t MOD;
-
-	///Offset: 0x00000004 - Command bits that affect the state
-	__O  uint32_t CMR;
-
-	///Offset: 0x00000008 - Global Controller Status and Error Counters
-	__IO uint32_t GSR;
-
-	///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
-	__I  uint32_t ICR;
-
-	///Offset: 0x00000010 - Interrupt Enable Register
-	__IO uint32_t IER;
-
-	///Offset: 0x00000014 - Bus Timing Register
-	__IO uint32_t BTR;
-
-	///Offset: 0x00000018 - Error Warning Limit
-	__IO uint32_t EWL;
-
-	///Offset: 0x0000001C - Status Register
-	__I  uint32_t SR;
-
-	///Offset: 0x00000020 - Receive frame status
-	__IO uint32_t RFS;
-
-	///Offset: 0x00000024 - Received Identifier
-	__IO uint32_t RID;
-
-	///Offset: 0x00000028 - Received data bytes 1-4
-	__IO uint32_t RDA;
-
-	///Offset: 0x0000002C - Received data bytes 5-8
-	__IO uint32_t RDB;
-
-	///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
-	__IO uint32_t TFI1;
-
-	///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
-	__IO uint32_t TID1;
-
-	///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
-	__IO uint32_t TDA1;
-
-	///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
-	__IO uint32_t TDB1;
-
-	///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
-	__IO uint32_t TFI2;
-
-	///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
-	__IO uint32_t TID2;
-
-	///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
-	__IO uint32_t TDA2;
-
-	///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
-	__IO uint32_t TDB2;
-
-	///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
-	__IO uint32_t TFI3;
-
-	///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
-	__IO uint32_t TID3;
-
-	///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
-	__IO uint32_t TDA3;
-
-	///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
-	__IO uint32_t TDB3;
-} LPC_CAN_TypeDef;
-
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t CTRL;
-  __IO uint32_t CNTVAL;
-} LPC_DAC_TypeDef;
-
-
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t DAO;
-  __IO uint32_t DAI;
-  __O  uint32_t TXFIFO;
-  __I  uint32_t RXFIFO;
-  __I  uint32_t STATE;
-  __IO uint32_t DMA1;
-  __IO uint32_t DMA2;
-  __IO uint32_t IRQ;
-  __IO uint32_t TXRATE;
-  __IO uint32_t RXRATE;
-  __IO uint32_t TXBITRATE;
-  __IO uint32_t RXBITRATE;
-  __IO uint32_t TXMODE;
-  __IO uint32_t RXMODE;
-} LPC_I2S_TypeDef;
-
-
-
-
-
-
-/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
-typedef struct
-{
-  __I  uint32_t CON;
-  __O  uint32_t CON_SET;
-  __O  uint32_t CON_CLR;
-  __I  uint32_t CAPCON;
-  __O  uint32_t CAPCON_SET;
-  __O  uint32_t CAPCON_CLR;
-  __IO uint32_t TC0;
-  __IO uint32_t TC1;
-  __IO uint32_t TC2;
-  __IO uint32_t LIM0;
-  __IO uint32_t LIM1;
-  __IO uint32_t LIM2;
-  __IO uint32_t MAT0;
-  __IO uint32_t MAT1;
-  __IO uint32_t MAT2;
-  __IO uint32_t DT;
-  __IO uint32_t CP;
-  __IO uint32_t CAP0;
-  __IO uint32_t CAP1;
-  __IO uint32_t CAP2;
-  __I  uint32_t INTEN;
-  __O  uint32_t INTEN_SET;
-  __O  uint32_t INTEN_CLR;
-  __I  uint32_t CNTCON;
-  __O  uint32_t CNTCON_SET;
-  __O  uint32_t CNTCON_CLR;
-  __I  uint32_t INTF;
-  __O  uint32_t INTF_SET;
-  __O  uint32_t INTF_CLR;
-  __O  uint32_t CAP_CLR;
-} LPC_MCPWM_TypeDef;
-
-/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
-typedef struct
-{
-  __O  uint32_t CON;
-  __I  uint32_t STAT;
-  __IO uint32_t CONF;
-  __I  uint32_t POS;
-  __IO uint32_t MAXPOS;
-  __IO uint32_t CMPOS0;
-  __IO uint32_t CMPOS1;
-  __IO uint32_t CMPOS2;
-  __I  uint32_t INXCNT;
-  __IO uint32_t INXCMP0;
-  __IO uint32_t LOAD;
-  __I  uint32_t TIME;
-  __I  uint32_t VEL;
-  __I  uint32_t CAP;
-  __IO uint32_t VELCOMP;
-  __IO uint32_t FILTERPHA;
-  __IO uint32_t FILTERPHB;
-  __IO uint32_t FILTERINX;
-  __IO uint32_t WINDOW;
-  __IO uint32_t INXCMP1;
-  __IO uint32_t INXCMP2;
-       uint32_t RESERVED0[993];
-  __O  uint32_t IEC;
-  __O  uint32_t IES;
-  __I  uint32_t INTSTAT;
-  __I  uint32_t IE;
-  __O  uint32_t CLR;
-  __O  uint32_t SET;
-} LPC_QEI_TypeDef;
-
-/*------------- SD/MMC card Interface (MCI)-----------------------------------*/
-typedef struct
-{
-  __IO uint32_t POWER;
-  __IO uint32_t CLOCK;
-  __IO uint32_t ARGUMENT;
-  __IO uint32_t COMMAND;
-  __I  uint32_t RESP_CMD;
-  __I  uint32_t RESP0;
-  __I  uint32_t RESP1;
-  __I  uint32_t RESP2;
-  __I  uint32_t RESP3;
-  __IO uint32_t DATATMR;
-  __IO uint32_t DATALEN;
-  __IO uint32_t DATACTRL;
-  __I  uint32_t DATACNT;
-  __I  uint32_t STATUS;
-  __O  uint32_t CLEAR;
-  __IO uint32_t MASK0;
-       uint32_t RESERVED0[2];
-  __I  uint32_t FIFOCNT;
-       uint32_t RESERVED1[13];
-  __IO uint32_t FIFO[16];
-} LPC_MCI_TypeDef;
-
-
-
-
-
-
-
-
-
-
-/*------------- EEPROM Controller (EEPROM) -----------------------------------*/
-typedef struct
-{
-  __IO uint32_t CMD;			/* 0x0080 */
-  __IO uint32_t ADDR;
-  __IO uint32_t WDATA;
-  __IO uint32_t RDATA;
-  __IO uint32_t WSTATE;			/* 0x0090 */
-  __IO uint32_t CLKDIV;
-  __IO uint32_t PWRDWN;			/* 0x0098 */
-       uint32_t RESERVED0[975];
-  __IO uint32_t INT_CLR_ENABLE;	/* 0x0FD8 */
-  __IO uint32_t INT_SET_ENABLE;
-  __IO uint32_t INT_STATUS;		/* 0x0FE0 */
-  __IO uint32_t INT_ENABLE;
-  __IO uint32_t INT_CLR_STATUS;
-  __IO uint32_t INT_SET_STATUS;
-} LPC_EEPROM_TypeDef;
-
-
-/*------------- COMPARATOR ----------------------------------------------------*/
-
-typedef struct {                                    /*!< (@ 0x40020000) COMPARATOR Structure                                   */
-  __IO uint32_t  CTRL;                              /*!< (@ 0x40020000) Comparator block control register                      */
-  __IO uint32_t  CTRL0;                             /*!< (@ 0x40020004) Comparator 0 control register                          */
-  __IO uint32_t  CTRL1;                             /*!< (@ 0x40020008) Comparator 1 control register                          */
-} LPC_COMPARATOR_Type;
-
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#endif
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-#define LPC_FLASH_BASE        (0x00000000UL)
-#define LPC_RAM_BASE          (0x10000000UL)
-#define LPC_PERI_RAM_BASE     (0x20000000UL)
-#define LPC_APB0_BASE         (0x40000000UL)
-#define LPC_APB1_BASE         (0x40080000UL)
-#define LPC_AHBRAM1_BASE      (0x20004000UL)
-#define LPC_AHB_BASE          (0x20080000UL)
-#define LPC_CM3_BASE          (0xE0000000UL)
-
-/* APB0 peripherals                                                           */
-#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)
-#define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)
-#define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)
-#define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)
-#define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)
-#define LPC_PWM0_BASE         (LPC_APB0_BASE + 0x14000)
-#define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)
-#define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)
-#define LPC_COMPARATOR_BASE   (LPC_APB0_BASE + 0x20000)					
-#define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)
-#define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)
-#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x2C000)
-#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)
-#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)
-#define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)
-#define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)
-#define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)
-#define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)
-#define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)
-#define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)
-
-/* APB1 peripherals                                                           */
-#define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)
-#define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)
-#define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)
-#define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)
-#define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)
-#define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)
-#define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)
-#define LPC_UART4_BASE        (LPC_APB1_BASE + 0x24000)
-#define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)
-#define LPC_SSP2_BASE         (LPC_APB1_BASE + 0x2C000)
-#define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)
-#define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)
-#define LPC_MCI_BASE          (LPC_APB1_BASE + 0x40000)
-#define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)
-
-/* AHB peripherals                                                            */
-#define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x00100)
-#define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x00120)
-#define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x00140)
-#define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x00160)
-#define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x00180)
-#define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x001A0)
-#define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x001C0)
-#define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x001E0)
-#define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x04000)
-#define LPC_LCD_BASE          (LPC_AHB_BASE  + 0x08000)
-#define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)
-#define LPC_CRC_BASE          (LPC_AHB_BASE  + 0x10000)
-#define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x18000)
-#define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x18020)
-#define LPC_GPIO2_BASE        (LPC_AHB_BASE  + 0x18040)
-#define LPC_GPIO3_BASE        (LPC_AHB_BASE  + 0x18060)
-#define LPC_GPIO4_BASE        (LPC_AHB_BASE  + 0x18080)
-#define LPC_GPIO5_BASE        (LPC_AHB_BASE  + 0x180A0)
-#define LPC_EMC_BASE          (LPC_AHB_BASE  + 0x1C000)
-
-#define LPC_EEPROM_BASE       (LPC_FLASH_BASE+ 0x200080)
-
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )
-#define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )
-#define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )
-#define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )
-#define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )
-#define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )
-#define LPC_UART0             ((LPC_UART_TypeDef      *) LPC_UART0_BASE    )
-#define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )
-#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
-#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
-#define LPC_UART4             ((LPC_UART4_TypeDef     *) LPC_UART4_BASE    )
-#define LPC_PWM0              ((LPC_PWM_TypeDef       *) LPC_PWM0_BASE     )
-#define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )
-#define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )
-#define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )
-#define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )
-#define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )
-#define LPC_COMPARATOR        ((LPC_COMPARATOR_Type	  *) LPC_COMPARATOR_BASE)
-#define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )
-#define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )
-#define LPC_IOCON             ((LPC_IOCON_TypeDef     *) LPC_IOCON_BASE    )
-#define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )
-#define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )
-#define LPC_SSP2              ((LPC_SSP_TypeDef       *) LPC_SSP2_BASE     )
-#define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )
-#define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )
-#define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
-#define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )
-#define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )
-#define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )
-#define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )
-#define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )
-#define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )
-#define LPC_MCI               ((LPC_MCI_TypeDef       *) LPC_MCI_BASE      )
-#define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )
-#define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )
-#define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )
-#define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )
-#define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )
-#define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )
-#define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )
-#define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )
-#define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )
-#define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )
-#define LPC_LCD               ((LPC_LCD_TypeDef       *) LPC_LCD_BASE      )
-#define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )
-#define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )
-#define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )
-#define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )
-#define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )
-#define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )
-#define LPC_GPIO5             ((LPC_GPIO_TypeDef      *) LPC_GPIO5_BASE    )
-#define LPC_EMC               ((LPC_EMC_TypeDef       *) LPC_EMC_BASE      )
-#define LPC_CRC               ((LPC_CRC_TypeDef       *) LPC_CRC_BASE      )
-#define LPC_EEPROM            ((LPC_EEPROM_TypeDef    *) LPC_EEPROM_BASE   )
-
-
-
-#endif  // __LPC407x_8x_177x_8x_H__

--- a/vendor/NXP/LPC4088/cmsis/cmsis.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,13 +0,0 @@
-/* mbed Microcontroller Library - CMSIS
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * A generic CMSIS include header, pulling in LPC407x_8x specifics
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "LPC407x_8x_177x_8x.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/vendor/NXP/LPC4088/cmsis/cmsis_nvic.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic for LCP407x_8x
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-#include "cmsis_nvic.h"
-
-#define NVIC_NUM_VECTORS          (16 + 41)     // CORE + MCU Peripherals
-#define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Location of vectors in RAM
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-    static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
-    int i;
-    // Copy and switch to dynamic vectors if first time called
-    if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
-        uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
-        for (i=0; i<NVIC_NUM_VECTORS; i++) {
-            vectors[i] = old_vectors[i];
-        }
-        SCB->VTOR = (uint32_t)vectors;
-    }
-    
-    vectors[IRQn + 16] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t *vectors = (uint32_t*)SCB->VTOR;
-    return vectors[IRQn + 16];
-}
-

--- a/vendor/NXP/LPC4088/cmsis/cmsis_nvic.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,23 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC4088/cmsis/core_cm4.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4.c
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version  V2.01
- * @date     06. December 2010
- *
- * @note
- * Copyright (C) 2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-/* ARM armcc specific functions */
-
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif

--- a/vendor/NXP/LPC4088/cmsis/core_cm4.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1757 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V3.02
- * @date     16. July 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M4
-  @{
- */
-
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM4_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM4_REV
-    #define __CM4_REV               0x0000
-    #warning "__CM4_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-    \brief      Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/** \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
-  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
-  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-#if (__FPU_PRESENT == 1)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                                 |
-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
-  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
-
-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

--- a/vendor/NXP/LPC4088/cmsis/core_cm4_simd.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,649 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4_simd.h
- * @brief    CMSIS Cortex-M4 SIMD Header File
- * @version  V3.01
- * @date     06. March 2012
- *
- * @note
- * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_SIMD_H
-#define __CORE_CM4_SIMD_H
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_iar.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_ccs.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLALD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLALDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLSLD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLSLDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-/* not yet supported */
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CORE_CM4_SIMD_H */
-
-#ifdef __cplusplus
-}
-#endif

--- a/vendor/NXP/LPC4088/cmsis/core_cmFunc.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,616 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V3.02
- * @date     24. May 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */

--- a/vendor/NXP/LPC4088/cmsis/core_cmInstr.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,643 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V3.03
- * @date     29. August 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-#define __ISB()                           __isb(0xF)
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()                           __dsb(0xF)
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB()                           __dmb(0xF)
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __RBIT                            __rbit
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-
-  __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
-  return(op1);
-}
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint8_t result;
-
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint16_t result;
-
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
-  uint8_t result;
-
-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

--- a/vendor/NXP/LPC4088/cmsis/system_LPC407x_8x_177x_8x.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,571 +0,0 @@
-/**********************************************************************
-* $Id$		system_LPC407x_8x_177x_8x.c			2012-01-16
-*//**
-* @file		system_LPC407x_8x_177x_8x.c
-* @brief	CMSIS Cortex-M3, M4 Device Peripheral Access Layer Source File
-*          	for the NXP LPC407x_8x_177x_8x Device Series
-*
-*			ARM Limited (ARM) is supplying this software for use with
-*			Cortex-M processor based microcontrollers.  This file can be
-*			freely distributed within development tools that are supporting
-*			such ARM based processors.
-*
-* @version	1.2
-* @date		20. June. 2012
-* @author	NXP MCU SW Application Team
-*
-* Copyright(C) 2012, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-**********************************************************************/
-
-#include <stdint.h>
-#include "LPC407x_8x_177x_8x.h"
-#include "system_LPC407x_8x_177x_8x.h"
-
-#define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y))
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-/*--------------------- Clock Configuration ----------------------------------
-//
-//	<e>	Clock Configuration
-//		<h>	System Controls and Status Register (SCS - address 0x400F C1A0)
-//			<o1.0>	EMC Shift Control Bit
-//					<i>		Controls how addresses are output on the EMC address pins for static memories
-//					<0=>	Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0)
-//					<1=>	Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1)
-//
-//			<o1.1>	EMC Reset Disable Bit
-//					<i>		If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition
-//					<i>		If 1, EMC is still retained its state through a warm reset
-//					<0=>	Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0)
-//					<1=>	Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1)
-//
-//			<o1.2>	EMC Burst Control
-//					<i>		Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects
-//					<0=>	Burst enabled (Bit 2 is 0)
-//					<1=>	Bust disbled (Bit 2 is 1)
-//
-//			<o1.3>	MCIPWR Active Level
-//					<i>		Selects the active level for the SD card interface signal SD_PWR
-//					<0=>	SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0)
-//					<1=>	SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1)
-//
-//			<o1.4>	Main Oscillator Range Select
-//					<0=>	In Range 1 MHz to 20 MHz (Bit 4 is 0)
-//					<1=>	In Range 15 MHz to 25 MHz (Bit 4 is 1)
-//
-//			<o1.5>	Main Oscillator enable
-//					<i>		0 (zero) means disabled, 1 means enable
-//
-//			<o1.6>	Main Oscillator status (Read-Only)
-//		</h>
-//
-//		<h>	Clock Source Select Register (CLKSRCSEL - address 0x400F C10C)
-//			<o2.0>	CLKSRC: Select the clock source for sysclk to PLL0 clock
-//					<0=>	Internal RC oscillator (Bit 0 is 0)
-//					<1=>	Main oscillator (Bit 0 is 1)
-//		</h>
-//
-//		<e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084)
-//			<i>			F_in  is in the range of 1 MHz to 25 MHz
-//			<i>			F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
-//			<i>			PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
-//
-//			<o4.0..4>   MSEL: PLL Multiplier Value
-//						<i>				M Value
-//						<1-32><#-1>
-//
-//			<o4.5..6>	PSEL: PLL Divider Value
-//						<i>				P Value
-//						<0=> 			1
-//						<1=>			2
-//						<2=>			4
-//						<3=>			8
-//		</e>
-//
-//		<e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4)
-//			<i>			F_in  is in the range of 1 MHz to 25 MHz
-//			<i>			F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
-//			<i>			PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
-//
-//			<o6.0..4>   MSEL: PLL Multiplier Value
-//						<i>				M Value
-//						<1-32><#-1>
-//
-//			<o6.5..6>	PSEL: PLL Divider Value
-//						<i>		P Value
-//						<0=>	1
-//						<1=>	2
-//						<2=>	4
-//						<3=>	8
-//		</e>
-//
-//		<h>	CPU Clock Selection Register (CCLKSEL - address 0x400F C104)
-//			<o7.0..4>	CCLKDIV: Select the value for divider of CPU clock (CCLK)
-//						<i>		0: The divider is turned off. No clock will be provided to the CPU
-//						<i>		n: The input clock is divided by n to produce the CPU clock
-//						<0-31>
-//
-//			<o7.8>		CCLKSEL: Select the input to the divider of CPU clock
-//						<0=>	sysclk clock is used
-//						<1=>	Main PLL0 clock is used
-//		</h>
-//
-//		<h>	USB Clock Selection Register (USBCLKSEL - 0x400F C108)
-//			<o8.0..4>	USBDIV: USB clock (source PLL0) divider selection
-//						<0=>	Divider is off and no clock provides to USB subsystem
-//						<4=>	Divider value is 4 (The source clock is divided by 4)
-//						<6=>	Divider value is 6 (The source clock is divided by 6)
-//
-//			<o8.8..9>	USBSEL: Select the source for USB clock divider
-//						<i>		When CPU clock is selected, the USB can be accessed
-//						<i>		by software but cannot perform USB functions
-//						<0=>	sysclk clock (the clock input to PLL0)
-//						<1=>	The clock output from PLL0
-//						<2=>	The clock output from PLL1
-//		</h>
-//
-//		<h>	EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100)
-//			<o9.0>	EMCDIV: Set the divider for EMC clock
-//					<0=> Divider value is 1
-//					<1=> Divider value is 2 (EMC clock is equal a half of input clock)
-//		</h>
-//
-//		<h>	Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8)
-//			<o10.0..4>	PCLKDIV: APB Peripheral clock divider
-//						<i>	0: The divider is turned off. No clock will be provided to APB peripherals
-//						<i>	n: The input clock is divided by n to produce the APB peripheral clock
-//						<0-31>
-//		</h>
-//
-//		<h>	SPIFI Clock Selection Register (SPIFICLKSEL - address 0x400F C1B4)
-//			<o11.0..4>	SPIFIDIV: Set the divider for SPIFI clock
-//						<i>	0: The divider is turned off. No clock will be provided to the SPIFI
-//						<i>	n: The input clock is divided by n to produce the SPIFI clock
-//						<0-31>
-//
-//			<o11.8..9>	SPIFISEL: Select the input clock for SPIFI clock divider
-//						<0=>	sysclk clock (the clock input to PLL0)
-//						<1=>	The clock output from PLL0
-//						<2=>	The clock output from PLL1
-//		</h>
-//
-//		<h>	Power Control for Peripherals Register (PCONP - address 0x400F C1C8)
-//			<o12.0>		PCLCD: LCD controller power/clock enable (bit 0)
-//			<o12.1>		PCTIM0: Timer/Counter 0 power/clock enable (bit 1)
-//			<o12.2>		PCTIM1: Timer/Counter 1 power/clock enable (bit 2)
-//			<o12.3>		PCUART0: UART 0 power/clock enable (bit 3)
-//			<o12.4>		PCUART1: UART 1 power/clock enable (bit 4)
-//			<o12.5>		PCPWM0: PWM0 power/clock enable (bit 5)
-//			<o12.6>		PCPWM1: PWM1 power/clock enable (bit 6)
-//			<o12.7>		PCI2C0: I2C 0 interface power/clock enable (bit 7)
-//			<o12.8>		PCUART4: UART 4 power/clock enable (bit 8)
-//			<o12.9>		PCRTC: RTC and Event Recorder power/clock enable (bit 9)
-//			<o12.10>	PCSSP1: SSP 1 interface power/clock enable (bit 10)
-//			<o12.11>	PCEMC: External Memory Controller power/clock enable (bit 11)
-//			<o12.12>	PCADC: A/D converter power/clock enable (bit 12)
-//			<o12.13>	PCCAN1: CAN controller 1 power/clock enable (bit 13)
-//			<o12.14>	PCCAN2: CAN controller 2 power/clock enable (bit 14)
-//			<o12.15>	PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15)
-//			<o12.17>	PCMCPWM: Motor Control PWM power/clock enable (bit 17)
-//			<o12.18>	PCQEI: Quadrature encoder interface power/clock enable (bit 18)
-//			<o12.19>	PCI2C1: I2C 1 interface power/clock enable (bit 19)
-//			<o12.20>	PCSSP2: SSP 2 interface power/clock enable (bit 20)
-//			<o12.21>	PCSSP0: SSP 0 interface power/clock enable (bit 21)
-//			<o12.22>	PCTIM2: Timer 2 power/clock enable (bit 22)
-//			<o12.23>	PCTIM3: Timer 3 power/clock enable (bit 23)
-//			<o12.24>	PCUART2: UART 2 power/clock enable (bit 24)
-//			<o12.25>	PCUART3: UART 3 power/clock enable (bit 25)
-//			<o12.26>	PCI2C2: I2C 2 interface power/clock enable (bit 26)
-//			<o12.27>	PCI2S: I2S interface power/clock enable (bit 27)
-//			<o12.28>	PCSDC: SD Card interface power/clock enable (bit 28)
-//			<o12.29>	PCGPDMA: GPDMA function power/clock enable (bit 29)
-//			<o12.30>	PCENET: Ethernet block power/clock enable (bit 30)
-//			<o12.31>	PCUSB: USB interface power/clock enable (bit 31)
-//		</h>
-//
-//		<h>	Clock Output Configuration Register (CLKOUTCFG)
-//			<o13.0..3>	CLKOUTSEL: Clock Source for CLKOUT Selection
-//						<0=>	CPU clock
-//						<1=>	Main Oscillator
-//						<2=>	Internal RC Oscillator
-//						<3=>	USB clock
-//						<4=>	RTC Oscillator
-//						<5=>	unused
-//						<6=>	Watchdog Oscillator
-//
-//			<o13.4..7>	CLKOUTDIV: Output Clock Divider
-//						<1-16><#-1>
-//
-//			<o13.8>		CLKOUT_EN: CLKOUT enable
-//		</h>
-//
-//	</e>
-*/
-
-#define CLOCK_SETUP           1
-#define SCS_Val               0x00000020
-#define CLKSRCSEL_Val         0x00000001
-#define PLL0_SETUP            1
-#define PLL0CFG_Val           0x00000009
-#define PLL1_SETUP            1
-#define PLL1CFG_Val           0x00000023
-#define CCLKSEL_Val           0x00000101
-#define USBCLKSEL_Val         0x00000201
-#define EMCCLKSEL_Val         0x00000001
-#define PCLKSEL_Val           0x00000002
-#define SPIFICLKSEL_Val       0x00000002
-#define PCONP_Val             0x042887DE
-#define CLKOUTCFG_Val         0x00000100
-
-#ifdef CORE_M4
-#define	LPC_CPACR	        0xE000ED88
-
-#define SCB_MVFR0           0xE000EF40
-#define SCB_MVFR0_RESET     0x10110021
-
-#define SCB_MVFR1           0xE000EF44
-#define SCB_MVFR1_RESET     0x11000011
-#endif
-
-
-/*--------------------- Flash Accelerator Configuration ----------------------
-//
-//	<e>	Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000)
-//		<o1.12..15>	FLASHTIM: Flash Access Time
-//					<0=>	1 CPU clock (for CPU clock up to 20 MHz)
-//					<1=>	2 CPU clocks (for CPU clock up to 40 MHz)
-//					<2=>	3 CPU clocks (for CPU clock up to 60 MHz)
-//					<3=>	4 CPU clocks (for CPU clock up to 80 MHz)
-//					<4=>	5 CPU clocks (for CPU clock up to 100 MHz)
-//					<5=>	6 CPU clocks (for any CPU clock)
-//	</e>
-*/
-
-#define FLASH_SETUP           1
-#define FLASHCFG_Val          0x00005000
-
-/*----------------------------------------------------------------------------
-  Check the register settings
- *----------------------------------------------------------------------------*/
-#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
-#define CHECK_RSVD(val, mask)                     (val & mask)
-
-/* Clock Configuration -------------------------------------------------------*/
-#if (CHECK_RSVD((SCS_Val),       ~0x0000003F))
-   #error "SCS: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
-   #error "CLKSRCSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((PLL0CFG_Val),   ~0x0000007F))
-   #error "PLL0CFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
-   #error "PLL1CFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((CCLKSEL_Val),   ~0x0000011F))
-   #error "CCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
-   #error "USBCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
-   #error "EMCCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
-   #error "PCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
-   #error "PCONP: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
-   #error "CLKOUTCFG: Invalid values of reserved bits!"
-#endif
-
-/* Flash Accelerator Configuration -------------------------------------------*/
-#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
-   #warning "FLASHCFG: Invalid values of reserved bits!"
-#endif
-
-
-/*----------------------------------------------------------------------------
-  DEFINES
- *----------------------------------------------------------------------------*/
-/* pll_out_clk = F_cco / (2 � P)
-   F_cco = pll_in_clk � M � 2 � P */
-#define __M                   ((PLL0CFG_Val & 0x1F) + 1)
-#define __PLL0_CLK(__F_IN)    (__F_IN * __M)
-#define __CCLK_DIV            (CCLKSEL_Val & 0x1F)
-#define __PCLK_DIV			  (PCLKSEL_Val & 0x1F)
-#define __ECLK_DIV			  ((EMCCLKSEL_Val & 0x01) + 1)
-
-/* Determine core clock frequency according to settings */
-#if (CLOCK_SETUP)                       /* Clock Setup                        */
-
-  #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
-   #error "Main Oscillator is selected as clock source but is not enabled!"
-  #endif
-
-  #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
-   #error "Main PLL is selected as clock source but is not enabled!"
-  #endif
-
-  #if ((CCLKSEL_Val & 0x100) == 0)      /* cclk = sysclk */
-    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
-        #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
-		#define __PER_CLK  (IRC_OSC/  __PCLK_DIV)
-        #define __EMC_CLK  (__CORE_CLK/  __ECLK_DIV)
-    #else                               /* sysclk = osc_clk */
-        #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
-        #define __PER_CLK  (OSC_CLK/  __PCLK_DIV)
-        #define __EMC_CLK  (__CORE_CLK/  __ECLK_DIV)
-    #endif
-  #else                                 /* cclk = pll_clk */
-    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
-        #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
-        #define __PER_CLK  (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
-        #define __EMC_CLK  (__CORE_CLK / __ECLK_DIV)
-    #else                               /* sysclk = osc_clk */
-        #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
-        #define __PER_CLK  (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
-		#define __EMC_CLK  (__CORE_CLK / __ECLK_DIV)
-    #endif
-  #endif
-
-#else
-        #define __CORE_CLK (IRC_OSC)
-        #define __PER_CLK  (IRC_OSC)
-        #define __EMC_CLK  (__CORE_CLK)
-#endif
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
-uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk)  */
-uint32_t EMCClock		 = __EMC_CLK; /*!< EMC Clock Frequency 				  */
-uint32_t USBClock 		 = (48000000UL);		  /*!< USB Clock Frequency - this value will
-									be updated after call SystemCoreClockUpdate, should be 48MHz*/
-
-
-/*----------------------------------------------------------------------------
-  Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
-{
-  /* Determine clock frequency according to clock register values             */
-  if ((LPC_SC->CCLKSEL &0x100) == 0) {            /* cclk = sysclk    */
-    if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */
-		  SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F));
-          PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F));
-          EMCClock        = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
-    }
-    else {                                        /* sysclk = osc_clk */
-      if ((LPC_SC->SCS & 0x40) == 0) {
-          SystemCoreClock = 0;                      /* this should never happen! */
-          PeripheralClock = 0;
-          EMCClock        = 0;
-      }
-      else {
-          SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F));
-          PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F));
-          EMCClock        = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
-      }
-    }
-  }
-  else {                                          /* cclk = pll_clk */
-    if ((LPC_SC->PLL0STAT & 0x100) == 0) {        /* PLL0 not enabled */
-          SystemCoreClock = 0;                      /* this should never happen! */
-          PeripheralClock = 0;
-          EMCClock 		  = 0;
-    }
-    else {
-      if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */
-          uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
-          uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
-          uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
-          uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
-          SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div);
-          PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div);
-          EMCClock        = SystemCoreClock / emc_div;
-      }
-      else {                                        /* sysclk = osc_clk */
-        if ((LPC_SC->SCS & 0x40) == 0) {
-          SystemCoreClock = 0;                      /* this should never happen! */
-          PeripheralClock = 0;
-          EMCClock 		  = 0;
-        }
-        else {
-          uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
-          uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
-          uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
-		  uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
-          SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div);
-          PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div);
-          EMCClock        = SystemCoreClock / emc_div;
-        }
-      }
-    }
-  }
-  /* ---update USBClock------------------*/
-  if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
-  {
-	  switch (LPC_SC->USBCLKSEL & 0x1F)
-	  {
-	  case 0:
-		  USBClock = 0; //no clock will be provided to the USB subsystem
-		  break;
-	  case 4:
-	  case 6:
-            {
-                 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
-                 uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F);
-		  if(LPC_SC->CLKSRCSEL & 0x01)	//pll_clk_in = main_osc
-			  USBClock = OSC_CLK * mul / usb_div;
-		  else //pll_clk_in = irc_clk
-			  USBClock = IRC_OSC * mul / usb_div;
-            }
-            break;
-	  default:
-		  USBClock = 0;  /* this should never happen! */
-	  }
-  }
-  else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
-  {
-	  if(LPC_SC->CLKSRCSEL & 0x01)	//pll1_clk_in = main_osc
-	  		USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
-	  else //pll1_clk_in = irc_clk
-	  		USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
-  }
-  else
-	  USBClock = 0; /* this should never happen! */
-}
-
-  /* Determine clock frequency according to clock register values             */
-
-#ifdef CORE_M4
-
-void fpu_init(void)
-{
- // from arm trm manual:
-//                ; CPACR is located at address 0xE000ED88
-//                LDR.W R0, =0xE000ED88
-//                ; Read CPACR
-//                LDR R1, [R0]
-//                ; Set bits 20-23 to enable CP10 and CP11 coprocessors
-//                ORR R1, R1, #(0xF << 20)
-//                ; Write back the modified value to the CPACR
-//                STR R1, [R0]
-
-
-    volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;
-    volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;
-    volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;
-    volatile uint32_t Cpacr;
-    volatile uint32_t Mvfr0;
-    volatile uint32_t Mvfr1;
-    char vfpPresent = 0;
-
-    Mvfr0 = *regMvfr0;
-    Mvfr1 = *regMvfr1;
-
-    vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
-
-    if(vfpPresent)
-    {
-        Cpacr = *regCpacr;
-        Cpacr |= (0xF << 20);
-        *regCpacr = Cpacr;   // enable CP10 and CP11 for full access
-    }
-
-}
-#endif
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void)
-{
-#ifndef __CODE_RED
-#ifdef CORE_M4
-fpu_init();
-#endif
-#endif
-
-#if (CLOCK_SETUP)                       /* Clock Setup                        */
-  LPC_SC->SCS       = SCS_Val;
-  if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
-    while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */
-  }
-
-  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for sysclk/PLL0*/
-
-#if (PLL0_SETUP)
-  LPC_SC->PLL0CFG   = PLL0CFG_Val;
-  LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-  while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0                    */
-#endif
-
-#if (PLL1_SETUP)
-  LPC_SC->PLL1CFG   = PLL1CFG_Val;
-  LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
-  LPC_SC->PLL1FEED  = 0xAA;
-  LPC_SC->PLL1FEED  = 0x55;
-  while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */
-#endif
-
-  LPC_SC->CCLKSEL   = CCLKSEL_Val;      /* Setup Clock Divider                */
-  LPC_SC->USBCLKSEL = USBCLKSEL_Val;    /* Setup USB Clock Divider            */
-  LPC_SC->EMCCLKSEL = EMCCLKSEL_Val;    /* EMC Clock Selection                */
-  LPC_SC->SPIFICLKSEL  = SPIFICLKSEL_Val;  /* SPIFI Clock Selection              */
-  LPC_SC->PCLKSEL   = PCLKSEL_Val;      /* Peripheral Clock Selection         */
-  LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */
-  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
-#endif
-
-  LPC_SC->PBOOST 	|= 0x03;			/* Power Boost control				*/
-
-#if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
-  LPC_SC->FLASHCFG  = FLASHCFG_Val|0x03A;
-#endif
-#ifndef __CODE_RED
-#ifdef  __RAM_MODE__
-  SCB->VTOR  = 0x10000000 & 0x3FFFFF80;
-#else
-  SCB->VTOR  = 0x00000000 & 0x3FFFFF80;
-#endif
-#endif
-  SystemCoreClockUpdate();
-}

--- a/vendor/NXP/LPC4088/cmsis/system_LPC407x_8x_177x_8x.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,89 +0,0 @@
-/**********************************************************************
-* $Id$		system_LPC407x_8x_177x_8x.h			2011-06-02
-*//**
-* @file		system_LPC407x_8x_177x_8x.h
-* @brief	CMSIS Cortex-M3 Device Peripheral Access Layer Source File
-*			for the NXP LPC Device Series
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-*
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-#ifndef __SYSTEM_LPC407x_8x_177x_8x_H
-#define __SYSTEM_LPC407x_8x_177x_8x_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;      /*!< System Clock Frequency (Core Clock)  	*/
-extern uint32_t PeripheralClock;	    /*!< Peripheral Clock Frequency (Pclk) 	    */
-extern uint32_t EMCClock;			        /*!< EMC Clock                              */
-extern uint32_t USBClock;			        /*!< USB Frequency 						              */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define XTAL        (12000000UL)        /* Oscillator frequency               */
-#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
-#define RTC_CLK     (   32768UL)        /* RTC oscillator frequency           */
-#define IRC_OSC     (12000000UL)        /* Internal RC oscillator frequency   */
-#define WDT_OSC		  (  500000UL)		/* Internal WDT oscillator frequency  */
-
-
-
-/*
-//-------- <<< end of configuration section >>> ------------------------------
-*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC407x_8x_177x_8x_H */

--- a/vendor/NXP/LPC4088/hal/PeripheralNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,88 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    UART_0 = (int)LPC_UART0_BASE,
-    UART_1 = (int)LPC_UART1_BASE,
-    UART_2 = (int)LPC_UART2_BASE,
-    UART_3 = (int)LPC_UART3_BASE,
-    UART_4 = (int)LPC_UART4_BASE
-} UARTName;
-
-typedef enum {
-    ADC0_0 = 0,
-    ADC0_1,
-    ADC0_2,
-    ADC0_3,
-    ADC0_4,
-    ADC0_5,
-    ADC0_6,
-    ADC0_7
-} ADCName;
-
-typedef enum {
-    DAC_0 = 0
-} DACName;
-
-typedef enum {
-    SPI_0 = (int)LPC_SSP0_BASE,
-    SPI_1 = (int)LPC_SSP1_BASE,
-    SPI_2 = (int)LPC_SSP2_BASE
-} SPIName;
-
-typedef enum {
-    I2C_0 = (int)LPC_I2C0_BASE,
-    I2C_1 = (int)LPC_I2C1_BASE,
-    I2C_2 = (int)LPC_I2C2_BASE
-} I2CName;
-
-typedef enum {
-    PWM0_1 = 1,
-    PWM0_2,
-    PWM0_3,
-    PWM0_4,
-    PWM0_5,
-    PWM0_6,
-    PWM1_1,
-    PWM1_2,
-    PWM1_3,
-    PWM1_4,
-    PWM1_5,
-    PWM1_6
-} PWMName;
-
-typedef enum {
-     CAN_1 = (int)LPC_CAN1_BASE,
-     CAN_2 = (int)LPC_CAN2_BASE
-} CANName;
-
-#define STDIO_UART_TX     USBTX
-#define STDIO_UART_RX     USBRX
-#define STDIO_UART        UART_0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC4088/hal/PinNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,96 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT  5
-
-typedef enum {
-    // LPC Pin Names
-    P0_0 = /*LPC_GPIO0_BASE*/0,
-          P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
-    P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
-    P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
-    P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
-    P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
-    P5_0, P5_1, P5_2, P5_3, P5_4,
-
-    // mbed DIP Pin Names
-    p5 = P0_9,
-    p6 = P0_8,
-    p7 = P0_7,
-    p8 = P0_6,
-    p9 = P0_0,
-    p10 = P0_1,
-    p11 = P0_18,
-    p12 = P0_17,
-    p13 = P0_15,
-    p14 = P0_16,
-    p15 = P0_23,
-    p16 = P0_24,
-    p17 = P0_25,
-    p18 = P0_26,
-    p19 = P1_30,
-    p20 = P1_31,
-    p21 = P2_5,
-    p22 = P2_4,
-    p23 = P2_3,
-    p24 = P2_2,
-    p25 = P2_1,
-    p26 = P2_0,
-    p27 = P0_11,
-    p28 = P0_10,
-    p29 = P0_5,
-    p30 = P0_4,
-
-    // Other mbed Pin Names
-    LED1 = P2_27,
-    LED2 = P2_26,
-    LED3 = P2_26,
-    LED4 = P2_26,
-
-    USBTX = P0_2,
-    USBRX = P0_3,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
-    PullUp = 0,
-    PullDown = 3,
-    PullNone = 2,
-    OpenDrain = 4
-} PinMode;
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC4088/hal/PortNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,35 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    Port0 = 0,
-    Port1 = 1,
-    Port2 = 2,
-    Port3 = 3,
-    Port4 = 4,
-    Port5 = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif

--- a/vendor/NXP/LPC4088/hal/analogin_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,126 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "analogin_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-#define ANALOGIN_MEDIAN_FILTER      1
-
-#define ADC_10BIT_RANGE             0x3FF
-#define ADC_12BIT_RANGE             0xFFF
-
-static inline int div_round_up(int x, int y) {
-  return (x + (y - 1)) / y;
-}
-
-static const PinMap PinMap_ADC[] = {
-    {P0_23, ADC0_0, 0x01},
-    {P0_24, ADC0_1, 0x01},
-    {P0_25, ADC0_2, 0x01},
-    {P0_26, ADC0_3, 0x01},
-    {P1_30, ADC0_4, 0x03},
-    {P1_31, ADC0_5, 0x03},
-    {P0_12, ADC0_6, 0x03},
-    {P0_13, ADC0_7, 0x03},
-    {NC   , NC    , 0   }
-};
-
-#define ADC_RANGE    ADC_12BIT_RANGE
-
-void analogin_init(analogin_t *obj, PinName pin) {
-    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
-    if (obj->adc == (uint32_t)NC) {
-        error("ADC pin mapping failed");
-    }
-    
-    // ensure power is turned on
-    LPC_SC->PCONP |= (1 << 12);
-    
-    uint32_t PCLK = PeripheralClock;
-    
-    // calculate minimum clock divider
-    //  clkdiv = divider - 1
-    uint32_t MAX_ADC_CLK = 12400000;
-    uint32_t clkdiv = div_round_up(PCLK, MAX_ADC_CLK) - 1;
-    
-    // Set the generic software-controlled ADC settings
-    LPC_ADC->CR = (0 << 0)      // SEL: 0 = no channels selected
-                  | (clkdiv << 8) // CLKDIV:
-                  | (0 << 16)     // BURST: 0 = software control
-                  | (1 << 21)     // PDN: 1 = operational
-                  | (0 << 24)     // START: 0 = no start
-                  | (0 << 27);    // EDGE: not applicable
-    
-    // must enable analog mode (ADMODE = 0)
-    __IO uint32_t *reg = (__IO uint32_t*) (LPC_IOCON_BASE + 4 * pin);
-    *reg &= ~(1 << 7);
-    
-    pinmap_pinout(pin, PinMap_ADC);
-}
-
-static inline uint32_t adc_read(analogin_t *obj) {
-    // Select the appropriate channel and start conversion
-    LPC_ADC->CR &= ~0xFF;
-    LPC_ADC->CR |= 1 << (int)obj->adc;
-    LPC_ADC->CR |= 1 << 24;
-
-    // Repeatedly get the sample data until DONE bit
-    unsigned int data;
-    do {
-        data = LPC_ADC->GDR;
-    } while ((data & ((unsigned int)1 << 31)) == 0);
-
-    // Stop conversion
-    LPC_ADC->CR &= ~(1 << 24);
-    
-    return (data >> 4) & ADC_RANGE; // 12 bit
-}
-
-static inline void order(uint32_t *a, uint32_t *b) {
-    if (*a > *b) {
-        uint32_t t = *a;
-        *a = *b;
-        *b = t;
-    }
-}
-
-static inline uint32_t adc_read_u32(analogin_t *obj) {
-    uint32_t value;
-#if ANALOGIN_MEDIAN_FILTER
-    uint32_t v1 = adc_read(obj);
-    uint32_t v2 = adc_read(obj);
-    uint32_t v3 = adc_read(obj);
-    order(&v1, &v2);
-    order(&v2, &v3);
-    order(&v1, &v2);
-    value = v2;
-#else
-    value = adc_read(obj);
-#endif
-    return value;
-}
-
-uint16_t analogin_read_u16(analogin_t *obj) {
-    uint32_t value = adc_read_u32(obj);
-    
-    return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
-}
-
-float analogin_read(analogin_t *obj) {
-    uint32_t value = adc_read_u32(obj);
-    return (float)value * (1.0f / (float)ADC_RANGE);
-}

--- a/vendor/NXP/LPC4088/hal/analogout_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "analogout_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_DAC[] = {
-    {P0_26, DAC_0, 2},
-    {NC   , NC   , 0}
-};
-
-void analogout_init(dac_t *obj, PinName pin) {
-    obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
-    if (obj->dac == (uint32_t)NC) {
-        error("DAC pin mapping failed");
-    }
-    
-    // DAC enable bit must be set
-    LPC_IOCON->P0_26 |= (1 << 16); // DACEN
-    
-    // map out (must be done before accessing registers)
-    pinmap_pinout(pin, PinMap_DAC);
-    
-    analogout_write_u16(obj, 0);
-}
-
-void analogout_free(dac_t *obj) {}
-
-static inline void dac_write(int value) {
-    value &= 0x3FF; // 10-bit
-    
-    // Set the DAC output
-    LPC_DAC->CR = (0 << 16)       // bias = 0
-                | (value << 6);
-}
-
-static inline int dac_read() {
-    return (LPC_DAC->CR >> 6) & 0x3FF;
-}
-
-void analogout_write(dac_t *obj, float value) {
-    if (value < 0.0f) {
-        dac_write(0);
-    } else if (value > 1.0f) {
-        dac_write(0x3FF);
-    } else {
-        dac_write(value * (float)0x3FF);
-    }
-}
-
-void analogout_write_u16(dac_t *obj, uint16_t value) {
-    dac_write(value >> 6); // 10-bit
-}
-
-float analogout_read(dac_t *obj) {
-    uint32_t value = dac_read();
-    return (float)value * (1.0f / (float)0x3FF);
-}
-
-uint16_t analogout_read_u16(dac_t *obj) {
-    uint32_t value = dac_read(); // 10-bit
-    return (value << 6) | ((value >> 4) & 0x003F);
-}

--- a/vendor/NXP/LPC4088/hal/can_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,282 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <math.h>
-#include <string.h>
-
-#include "can_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-/* Acceptance filter mode in AFMR register */
-#define ACCF_OFF                0x01
-#define ACCF_BYPASS             0x02
-#define ACCF_ON                 0x00
-#define ACCF_FULLCAN            0x04
-
-/* There are several bit timing calculators on the internet.
-http://www.port.de/engl/canprod/sv_req_form.html
-http://www.kvaser.com/can/index.htm
-*/
-
-static const PinMap PinMap_CAN_RD[] = {
-    {P0_0 , CAN_1, 1},
-    {P0_4 , CAN_2, 2},
-    {P0_21, CAN_1, 4},
-    {P2_7 , CAN_2, 1},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_CAN_TD[] = {
-    {P0_1 , CAN_1, 1},
-    {P0_5 , CAN_2, 2},
-    {P0_22, CAN_1, 4},
-    {P2_8 , CAN_2, 1},
-    {NC   , NC   , 0}
-};
-
-// Type definition to hold a CAN message
-struct CANMsg {
-    unsigned int  reserved1 : 16;
-    unsigned int  dlc       :  4; // Bits 16..19: DLC - Data Length Counter
-    unsigned int  reserved0 : 10;
-    unsigned int  rtr       :  1; // Bit 30: Set if this is a RTR message
-    unsigned int  type      :  1; // Bit 31: Set if this is a 29-bit ID message
-    unsigned int  id;             // CAN Message ID (11-bit or 29-bit)
-    unsigned char data[8];        // CAN Message Data Bytes 0-7
-};
-typedef struct CANMsg CANMsg;
-
-static uint32_t can_disable(can_t *obj) {
-    uint32_t sm = obj->dev->MOD;
-    obj->dev->MOD |= 1;
-    return sm;
-}
-
-static inline void can_enable(can_t *obj) {
-    if (obj->dev->MOD & 1) {
-        obj->dev->MOD &= ~(1);
-    }
-}
-
-// This table has the sampling points as close to 75% as possible. The first
-// value is TSEG1, the second TSEG2.
-static const int timing_pts[23][2] = {
-    {0x0, 0x0},      // 2,  50%
-    {0x1, 0x0},      // 3,  67%
-    {0x2, 0x0},      // 4,  75%
-    {0x3, 0x0},      // 5,  80%
-    {0x3, 0x1},      // 6,  67%
-    {0x4, 0x1},      // 7,  71%
-    {0x5, 0x1},      // 8,  75%
-    {0x6, 0x1},      // 9,  78%
-    {0x6, 0x2},      // 10, 70%
-    {0x7, 0x2},      // 11, 73%
-    {0x8, 0x2},      // 12, 75%
-    {0x9, 0x2},      // 13, 77%
-    {0x9, 0x3},      // 14, 71%
-    {0xA, 0x3},      // 15, 73%
-    {0xB, 0x3},      // 16, 75%
-    {0xC, 0x3},      // 17, 76%
-    {0xD, 0x3},      // 18, 78%
-    {0xD, 0x4},      // 19, 74%
-    {0xE, 0x4},      // 20, 75%
-    {0xF, 0x4},      // 21, 76%
-    {0xF, 0x5},      // 22, 73%
-    {0xF, 0x6},      // 23, 70%
-    {0xF, 0x7},      // 24, 67%
-};
-
-static unsigned int can_speed(unsigned int sclk, unsigned int pclk, unsigned int cclk, unsigned char psjw) {
-    uint32_t    btr;
-    uint16_t    brp = 0;
-    uint32_t    calcbit;
-    uint32_t    bitwidth;
-    int         hit = 0;
-    int         bits;
-    
-    bitwidth = sclk / (pclk * cclk);
-    
-    brp = bitwidth / 0x18;
-    while ((!hit) && (brp < bitwidth / 4)) {
-        brp++;
-        for (bits = 22; bits > 0; bits--) {
-            calcbit = (bits + 3) * (brp + 1);
-            if (calcbit == bitwidth) {
-                hit = 1;
-                break;
-            }
-        }
-    }
-    
-    if (hit) {
-        btr = ((timing_pts[bits][1] << 20) & 0x00700000)
-            | ((timing_pts[bits][0] << 16) & 0x000F0000)
-            | ((psjw                << 14) & 0x0000C000)
-            | ((brp                 <<  0) & 0x000003FF);
-    } else {
-        btr = 0xFFFFFFFF;
-    }
-    
-    return btr;
-}
-
-void can_init(can_t *obj, PinName rd, PinName td) {
-    CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
-    CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
-    obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
-    if ((int)obj->dev == NC) {
-        error("CAN pin mapping failed");
-    }
-    
-    switch ((int)obj->dev) {
-        case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
-        case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
-    }
-    
-    pinmap_pinout(rd, PinMap_CAN_RD);
-    pinmap_pinout(td, PinMap_CAN_TD);
-    
-    can_reset(obj);
-    obj->dev->IER = 0;             // Disable Interrupts
-    can_frequency(obj, 100000);
-    
-    LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
-}
-
-void can_free(can_t *obj) {
-    switch ((int)obj->dev) {
-        case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
-        case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
-    }
-}
-
-int can_frequency(can_t *obj, int f) {
-    int pclk = PeripheralClock;
-    int btr = can_speed(SystemCoreClock, pclk, (unsigned int)f, 1);
-    
-    if (btr > 0) {
-        uint32_t modmask = can_disable(obj);
-        obj->dev->BTR = btr;
-        obj->dev->MOD = modmask;
-        return 1;
-    } else {
-        return 0;
-    }
-}
-
-int can_write(can_t *obj, CAN_Message msg, int cc) {
-    unsigned int CANStatus;
-    CANMsg m;
-    
-    can_enable(obj);
-    
-    m.id   = msg.id ;
-    m.dlc  = msg.len & 0xF;
-    m.rtr  = msg.type;
-    m.type = msg.format;
-    memcpy(m.data, msg.data, msg.len);
-    const unsigned int *buf = (const unsigned int *)&m;
-    
-    CANStatus = obj->dev->SR;
-    if (CANStatus & 0x00000004) {
-        obj->dev->TFI1 = buf[0] & 0xC00F0000;
-        obj->dev->TID1 = buf[1];
-        obj->dev->TDA1 = buf[2];
-        obj->dev->TDB1 = buf[3];
-        if(cc) {
-            obj->dev->CMR = 0x30;
-        } else {
-            obj->dev->CMR = 0x21;
-        }
-        return 1;
-    
-    } else if (CANStatus & 0x00000400) {
-        obj->dev->TFI2 = buf[0] & 0xC00F0000;
-        obj->dev->TID2 = buf[1];
-        obj->dev->TDA2 = buf[2];
-        obj->dev->TDB2 = buf[3];
-        if (cc) {
-            obj->dev->CMR = 0x50;
-        } else {
-            obj->dev->CMR = 0x41;
-        }
-        return 1;
-    
-    } else if (CANStatus & 0x00040000) {
-        obj->dev->TFI3 = buf[0] & 0xC00F0000;
-        obj->dev->TID3 = buf[1];
-        obj->dev->TDA3 = buf[2];
-        obj->dev->TDB3 = buf[3];
-        if (cc) {
-            obj->dev->CMR = 0x90;
-        } else {
-            obj->dev->CMR = 0x81;
-        }
-        return 1;
-    }
-    
-    return 0;
-}
-
-int can_read(can_t *obj, CAN_Message *msg) {
-    CANMsg x;
-    unsigned int *i = (unsigned int *)&x;
-    
-    can_enable(obj);
-    
-    if (obj->dev->GSR & 0x1) {
-        *i++ = obj->dev->RFS;  // Frame
-        *i++ = obj->dev->RID;  // ID
-        *i++ = obj->dev->RDA;  // Data A
-        *i++ = obj->dev->RDB;  // Data B
-        obj->dev->CMR = 0x04;  // release receive buffer
-        
-        msg->id     = x.id;
-        msg->len    = x.dlc;
-        msg->format = (x.type)? CANExtended : CANStandard;
-        msg->type   = (x.rtr)?  CANRemote:    CANData;
-        memcpy(msg->data,x.data,x.dlc);
-        return 1;
-    }
-    
-    return 0;
-}
-
-void can_reset(can_t *obj) {
-    can_disable(obj);
-    obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
-}
-
-unsigned char can_rderror(can_t *obj) {
-    return (obj->dev->GSR >> 16) & 0xFF;
-}
-
-unsigned char can_tderror(can_t *obj) {
-    return (obj->dev->GSR >> 24) & 0xFF;
-}
-
-void can_monitor(can_t *obj, int silent) {
-    uint32_t mod_mask = can_disable(obj);
-    if (silent) {
-        obj->dev->MOD |= (1 << 1);
-    } else {
-        obj->dev->MOD &= ~(1 << 1);
-    }
-    if (!(mod_mask & 1)) {
-        can_enable(obj);
-    }
-}

--- a/vendor/NXP/LPC4088/hal/device.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,59 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-#define DEVICE_PORTIN           1
-#define DEVICE_PORTOUT          1
-#define DEVICE_PORTINOUT        1
-
-#define DEVICE_INTERRUPTIN      1
-
-#define DEVICE_ANALOGIN         1
-#define DEVICE_ANALOGOUT        1
-
-#define DEVICE_SERIAL           1
-
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
-
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         1
-
-#define DEVICE_CAN              1
-
-#define DEVICE_RTC              1
-
-#define DEVICE_ETHERNET         1
-
-#define DEVICE_PWMOUT           1
-
-#define DEVICE_SEMIHOST         0 // Need HW?
-#define DEVICE_LOCALFILESYSTEM  0 // Need HW?
-#define DEVICE_ID_LENGTH       32
-#define DEVICE_MAC_OFFSET      20
-
-#define DEVICE_SLEEP            1
-
-#define DEVICE_DEBUG_AWARENESS  1
-
-#define DEVICE_STDIO_MESSAGES   1
-
-#define DEVICE_ERROR_PATTERN    1
-
-#include "objects.h"
-
-#endif

--- a/vendor/NXP/LPC4088/hal/ethernet_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,964 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <string.h>
-
-#include "ethernet_api.h"
-#include "cmsis.h"
-#include "mbed_interface.h"
-#include "toolchain.h"
-#include "error.h"
-
-#define NEW_LOGIC       0
-#define NEW_ETH_BUFFER  0
-
-#if NEW_ETH_BUFFER
-
-#define NUM_RX_FRAG         4           // Number of Rx Fragments (== packets)
-#define NUM_TX_FRAG         3           // Number of Tx Fragments (== packets)
-
-#define ETH_MAX_FLEN        1536         // Maximum Ethernet Frame Size
-#define ETH_FRAG_SIZE       ETH_MAX_FLEN // Packet Fragment size (same as packet length)
-
-#else
-
-// Memfree calculation:
-// (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
-//                (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
-/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
-#define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */
-#define NUM_TX_FRAG         3           /* Num.of TX Fragments 3*1536= 4.6kB */
-//#define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
-
-//#define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
-#define ETH_FRAG_SIZE       0x300       /* Packet Fragment size 1536/2 Bytes   */
-#define ETH_MAX_FLEN        0x300       /* Max. Ethernet Frame Size          */
-
-const int ethernet_MTU_SIZE  = 0x300;
-
-#endif
-
-#define ETHERNET_ADDR_SIZE 6
-
-PACKED struct RX_DESC_TypeDef {                        /* RX Descriptor struct              */
-   unsigned int Packet;
-   unsigned int Ctrl;
-};
-typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
-
-PACKED struct RX_STAT_TypeDef {                        /* RX Status struct                  */
-   unsigned int Info;
-   unsigned int HashCRC;
-};
-typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
-
-PACKED struct TX_DESC_TypeDef {                        /* TX Descriptor struct              */
-   unsigned int Packet;
-   unsigned int Ctrl;
-};
-typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
-
-PACKED struct TX_STAT_TypeDef {                        /* TX Status struct                  */
-   unsigned int Info;
-};
-typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
-
-/* MAC Configuration Register 1 */
-#define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
-#define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
-#define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
-#define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
-#define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
-#define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
-#define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
-#define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
-#define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
-#define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
-#define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
-
-/* MAC Configuration Register 2 */
-#define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
-#define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
-#define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
-#define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
-#define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
-#define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
-#define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
-#define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
-#define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
-#define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
-#define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
-#define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
-#define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
-
-/* Back-to-Back Inter-Packet-Gap Register */
-#define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
-#define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
-
-/* Non Back-to-Back Inter-Packet-Gap Register */
-#define IPGR_DEF            0x00000012  /* Recommended value                 */
-
-/* Collision Window/Retry Register */
-#define CLRT_DEF            0x0000370F  /* Default value                     */
-
-/* PHY Support Register */
-#define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
-//#define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */
-#define SUPP_RES_RMII       0x00000000  /* Reset Reduced MII Logic           */
-
-/* Test Register */
-#define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
-#define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
-#define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
-
-/* MII Management Configuration Register */
-#define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
-#define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
-#define MCFG_CLK_SEL        0x0000003C  /* Clock Select Mask                 */
-#define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
-
-/* MII Management Command Register */
-#define MCMD_READ           0x00000001  /* MII Read                          */
-#define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
-
-#define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
-#define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
-
-/* MII Management Address Register */
-#define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
-#define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
-
-/* MII Management Indicators Register */
-#define MIND_BUSY           0x00000001  /* MII is Busy                       */
-#define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
-#define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
-#define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
-
-/* Command Register */
-#define CR_RX_EN            0x00000001  /* Enable Receive                    */
-#define CR_TX_EN            0x00000002  /* Enable Transmit                   */
-#define CR_REG_RES          0x00000008  /* Reset Host Registers              */
-#define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
-#define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
-#define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
-#define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
-#define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
-#define CR_RMII             0x00000200  /* Reduced MII Interface             */
-#define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
-
-/* Status Register */
-#define SR_RX_EN            0x00000001  /* Enable Receive                    */
-#define SR_TX_EN            0x00000002  /* Enable Transmit                   */
-
-/* Transmit Status Vector 0 Register */
-#define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
-#define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
-#define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
-#define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
-#define TSV0_MCAST          0x00000010  /* Multicast Destination             */
-#define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
-#define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
-#define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
-#define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
-#define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
-#define TSV0_GIANT          0x00000400  /* Giant Frame                       */
-#define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
-#define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
-#define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
-#define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
-#define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
-#define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
-
-/* Transmit Status Vector 1 Register */
-#define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
-#define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
-
-/* Receive Status Vector Register */
-#define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
-#define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
-#define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
-#define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
-#define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
-#define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
-#define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
-#define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
-#define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
-#define RSV_MCAST           0x01000000  /* Multicast Frame                   */
-#define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
-#define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
-#define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
-#define RSV_PAUSE           0x10000000  /* Pause Frame                       */
-#define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
-#define RSV_VLAN            0x40000000  /* VLAN Frame                        */
-
-/* Flow Control Counter Register */
-#define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
-#define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
-
-/* Flow Control Status Register */
-#define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
-
-/* Receive Filter Control Register */
-#define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
-#define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
-#define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
-#define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
-#define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
-#define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
-#define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
-#define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
-
-/* Receive Filter WoL Status/Clear Registers */
-#define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
-#define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
-#define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
-#define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
-#define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
-#define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
-#define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
-#define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
-
-/* Interrupt Status/Enable/Clear/Set Registers */
-#define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
-#define INT_RX_ERR          0x00000002  /* Receive Error                     */
-#define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
-#define INT_RX_DONE         0x00000008  /* Receive Done                      */
-#define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
-#define INT_TX_ERR          0x00000020  /* Transmit Error                    */
-#define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
-#define INT_TX_DONE         0x00000080  /* Transmit Done                     */
-#define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
-#define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
-
-/* Power Down Register */
-#define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
-
-/* RX Descriptor Control Word */
-#define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
-#define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
-
-/* RX Status Hash CRC Word */
-#define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
-#define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
-
-/* RX Status Information Word */
-#define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
-#define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
-#define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
-#define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
-#define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
-#define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
-#define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
-#define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
-#define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
-#define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
-#define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
-#define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
-#define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
-#define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
-#define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
-
-//#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
-#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
-                            RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
-
-
-/* TX Descriptor Control Word */
-#define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
-#define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
-#define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
-#define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
-#define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
-#define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
-#define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
-
-/* TX Status Information Word */
-#define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
-#define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
-#define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
-#define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
-#define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
-#define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
-#define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
-#define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
-
-/* ENET Device Revision ID */
-#define OLD_EMAC_MODULE_ID  0x39022000  /* Rev. ID for first rev '-'         */
-
-/* DP83848C PHY Registers */
-#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
-#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
-#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
-#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
-#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
-#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
-#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
-#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
-
-/* PHY Extended Registers */
-#define PHY_REG_STS         0x10        /* Status Register                   */
-#define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */
-#define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */
-#define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */
-#define PHY_REG_RECR        0x15        /* Receive Error Counter             */
-#define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */
-#define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */
-#define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */
-#define PHY_REG_PHYCR       0x19        /* PHY Control Register              */
-#define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */
-#define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */
-#define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */
-
-#define PHY_REG_SCSR        0x1F        /* PHY Special Control/Status Register */
-
-#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
-#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
-#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
-#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
-#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */
-
-#define DP83848C_DEF_ADR    0x0100      /* Default PHY device address        */
-#define DP83848C_ID         0x20005C90  /* PHY Identifier - DP83848C         */
-
-#define LAN8720_ID          0x0007C0F0  /* PHY Identifier - LAN8720          */
-
-#define PHY_STS_LINK        0x0001      /* PHY Status Link Mask              */
-#define PHY_STS_SPEED       0x0002      /* PHY Status Speed Mask             */
-#define PHY_STS_DUPLEX      0x0004      /* PHY Status Duplex Mask            */
-
-#define PHY_BMCR_RESET      0x8000      /* PHY Reset                         */
-
-#define PHY_BMSR_LINK       0x0004      /* PHY BMSR Link valid               */
-
-#define PHY_SCSR_100MBIT    0x0008      /* Speed: 1=100 MBit, 0=10Mbit       */
-#define PHY_SCSR_DUPLEX     0x0010      /* PHY Duplex Mask                   */
-
-
-static int phy_read(unsigned int PhyReg);
-static int phy_write(unsigned int PhyReg, unsigned short Data);
-
-static void txdscr_init(void);
-static void rxdscr_init(void);
-
-#if defined (__ICCARM__)
-#   define AHBSRAM1
-#elif defined(TOOLCHAIN_GCC_CR)
-#   define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
-#else
-#   define AHBSRAM1     __attribute__((section("AHBSRAM1"),aligned))
-#endif
-
-AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
-AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
-AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
-AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
-AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
-AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
-
-
-#if NEW_LOGIC
-static int rx_consume_offset = -1;
-static int tx_produce_offset = -1;
-#else
-static int send_doff =  0;
-static int send_idx  = -1;
-static int send_size =  0;
-
-static int receive_soff =  0;
-static int receive_idx  = -1;
-#endif
-
-static uint32_t phy_id = 0;
-
-static inline int rinc(int idx, int mod) {
-  ++idx;
-  idx %= mod;
-  return idx;
-}
-
-//extern unsigned int SystemFrequency;
-static inline unsigned int clockselect() {
-  if(SystemCoreClock < 10000000) {
-    return 1;
-  } else if(SystemCoreClock <  15000000) {
-    return 2;
-  } else if(SystemCoreClock <  20000000) {
-    return 3;
-  } else if(SystemCoreClock <  25000000) {
-    return 4;
-  } else if(SystemCoreClock <  35000000) {
-    return 5;
-  } else if(SystemCoreClock <  50000000) {
-    return 6;
-  } else if(SystemCoreClock <  70000000) {
-    return 7;
-  } else if(SystemCoreClock <  80000000) {
-    return 8;
-  } else if(SystemCoreClock <  90000000) {
-    return 9;
-  } else if(SystemCoreClock < 100000000) {
-    return 10;
-  } else if(SystemCoreClock < 120000000) {
-    return 11;
-  } else if(SystemCoreClock < 130000000) {
-    return 12;
-  } else if(SystemCoreClock < 140000000) {
-    return 13;
-  } else if(SystemCoreClock < 150000000) {
-    return 15;
-  } else if(SystemCoreClock < 160000000) {
-    return 16;
-  } else {
-    return 0;
-  }
-}
-
-#ifndef min
-#define min(x, y) (((x)<(y))?(x):(y))
-#endif
-
-/*----------------------------------------------------------------------------
-  Ethernet Device initialize
- *----------------------------------------------------------------------------*/
-int ethernet_init() {
-  int regv, tout;
-  char mac[ETHERNET_ADDR_SIZE];
-  unsigned int clock = clockselect();
-  
-  LPC_SC->PCONP |= 0x40000000;                       /* Power Up the EMAC controller. */
-  
-  LPC_IOCON->P1_0  &= ~0x07;    /*  ENET I/O config */
-  LPC_IOCON->P1_0  |= 0x01;     /* ENET_TXD0 */
-  LPC_IOCON->P1_1  &= ~0x07;
-  LPC_IOCON->P1_1  |= 0x01;     /* ENET_TXD1 */
-  LPC_IOCON->P1_4  &= ~0x07;
-  LPC_IOCON->P1_4  |= 0x01;     /* ENET_TXEN */
-  LPC_IOCON->P1_8  &= ~0x07;
-  LPC_IOCON->P1_8  |= 0x01;     /* ENET_CRS */
-  LPC_IOCON->P1_9  &= ~0x07;
-  LPC_IOCON->P1_9  |= 0x01;     /* ENET_RXD0 */
-  LPC_IOCON->P1_10 &= ~0x07;
-  LPC_IOCON->P1_10 |= 0x01;     /* ENET_RXD1 */
-  LPC_IOCON->P1_14 &= ~0x07;
-  LPC_IOCON->P1_14 |= 0x01;     /* ENET_RX_ER */
-  LPC_IOCON->P1_15 &= ~0x07;
-  LPC_IOCON->P1_15 |= 0x01;     /* ENET_REF_CLK */
-  LPC_IOCON->P1_16 &= ~0x07;    /* ENET/PHY I/O config */
-  LPC_IOCON->P1_16 |= 0x01;     /* ENET_MDC */
-  LPC_IOCON->P1_17 &= ~0x07;
-  LPC_IOCON->P1_17 |= 0x01;     /* ENET_MDIO */
-  
-   /* Reset all EMAC internal modules. */
-  LPC_EMAC->MAC1    = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
-                      MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
-  LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
-
-  for(tout = 100; tout; tout--) __NOP();             /* A short delay after reset. */
-
-  LPC_EMAC->MAC1 = MAC1_PASS_ALL;                    /* Initialize MAC control registers. */
-  LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
-  LPC_EMAC->MAXF = ETH_MAX_FLEN;
-  LPC_EMAC->CLRT = CLRT_DEF;
-  LPC_EMAC->IPGR = IPGR_DEF;
-
-  LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;    /* Enable Reduced MII interface. */
-
-  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;    /* Set clock */
-  LPC_EMAC->MCFG |= MCFG_RES_MII;                    /* and reset */
-
-  for(tout = 100; tout; tout--) __NOP();             /* A short delay */
-
-  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
-  LPC_EMAC->MCMD = 0;
-
-  LPC_EMAC->SUPP = SUPP_RES_RMII;                    /* Reset Reduced MII Logic. */
-
-  for (tout = 100; tout; tout--) __NOP();            /* A short delay */
-
-  LPC_EMAC->SUPP = 0;
-
-  phy_write(PHY_REG_BMCR, PHY_BMCR_RESET);           /* perform PHY reset */
-  for(tout = 0x20000; ; tout--) {                    /* Wait for hardware reset to end. */
-    regv = phy_read(PHY_REG_BMCR);
-    if(regv < 0 || tout == 0) {
-       return -1;                                    /* Error */
-    }
-    if(!(regv & PHY_BMCR_RESET)) {
-       break;                                        /* Reset complete. */
-    }
-  }
-
-  phy_id =  (phy_read(PHY_REG_IDR1) << 16);
-  phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
-
-  if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
-      error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
-  }
-
-  ethernet_set_link(-1, 0);
-
-  /* Set the Ethernet MAC Address registers */
-  ethernet_address(mac);
-  LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
-  LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
-  LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
-
-  txdscr_init();                                      /* initialize DMA TX Descriptor */
-  rxdscr_init();                                      /* initialize DMA RX Descriptor */
-
-  LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
-                                                      /* Receive Broadcast, Perfect Match Packets */
-
-  LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;    /* Enable EMAC interrupts. */
-  LPC_EMAC->IntClear  = 0xFFFF;                       /* Reset all interrupts */
-  
-  LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);        /* Enable receive and transmit mode of MAC Ethernet core */
-  LPC_EMAC->MAC1     |= MAC1_REC_EN;
-
-#if NEW_LOGIC
-  rx_consume_offset = -1;
-  tx_produce_offset = -1;
-#else
-  send_doff =  0;
-  send_idx  = -1;
-  send_size =  0;
-
-  receive_soff =  0;
-  receive_idx  = -1;
-#endif
-
-  return 0;
-}
-
-/*----------------------------------------------------------------------------
-  Ethernet Device Uninitialize
- *----------------------------------------------------------------------------*/
-void ethernet_free() {
-    LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
-    LPC_EMAC->IntClear   =  0xFFFF;
-    
-    LPC_SC->PCONP   &= ~0x40000000;       /* Power down the EMAC controller. */
-    
-    LPC_IOCON->P1_0  &= ~0x07;    /*  ENET I/O config */
-    LPC_IOCON->P1_1  &= ~0x07;
-    LPC_IOCON->P1_4  &= ~0x07;
-    LPC_IOCON->P1_8  &= ~0x07;
-    LPC_IOCON->P1_9  &= ~0x07;
-    LPC_IOCON->P1_10 &= ~0x07;
-    LPC_IOCON->P1_14 &= ~0x07;
-    LPC_IOCON->P1_15 &= ~0x07;
-    LPC_IOCON->P1_16 &= ~0x07;    /* ENET/PHY I/O config */
-    LPC_IOCON->P1_17 &= ~0x07;
-}
-
-// if(TxProduceIndex == TxConsumeIndex) buffer array is empty
-// if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
-// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
-// TxConsumeIndex - The buffer that will/is beign sent by hardware
-
-int ethernet_write(const char *data, int slen) {
-
-#if NEW_LOGIC
-
-   if(tx_produce_offset < 0) { // mark as active if not already
-     tx_produce_offset = 0;
-   }
-
-   int index = LPC_EMAC->TxProduceIndex;
-
-   int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
-   int requested = slen;
-   int ncopy = min(remaining, requested);
-
-   void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
-   void *psrc = (void *)(data);
-
-   if(ncopy > 0 ){
-     if(data != NULL) {
-       memcpy(pdst, psrc, ncopy);
-     } else {
-       memset(pdst, 0, ncopy);
-     }
-   }
-
-   tx_produce_offset += ncopy;
-
-   return ncopy;
-
-#else
-    void       *pdst, *psrc;
-    const int   dlen = ETH_FRAG_SIZE;
-    int         copy = 0;
-    int         soff = 0;
-
-    if(send_idx == -1) {
-        send_idx = LPC_EMAC->TxProduceIndex;
-    }
-
-    if(slen + send_doff > ethernet_MTU_SIZE) {
-       return -1;
-    }
-
-    do {
-        copy = min(slen - soff, dlen - send_doff);
-        pdst = (void *)(txdesc[send_idx].Packet + send_doff);
-        psrc = (void *)(data + soff);
-        if(send_doff + copy > ETH_FRAG_SIZE) {
-            txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
-            send_idx = rinc(send_idx, NUM_TX_FRAG);
-            send_doff = 0;
-        }
-
-        if(data != NULL) {
-            memcpy(pdst, psrc, copy);
-        } else {
-            memset(pdst, 0, copy);
-        }
-
-        soff += copy;
-        send_doff += copy;
-        send_size += copy;
-    } while(soff != slen);
-
-    return soff;
-#endif
-}
-
-int ethernet_send() {
-
-#if NEW_LOGIC
-  if(tx_produce_offset < 0) { // no buffer active
-    return -1;
-  }
-
-  // ensure there is a link
-  if(!ethernet_link()) {
-    return -2;
-  }
-
-  // we have been writing in to a buffer, so finalise it
-  int size = tx_produce_offset;
-  int index = LPC_EMAC->TxProduceIndex;
-  txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
-
-  // Increment ProduceIndex to allow it to be sent
-  // We can only do this if the next slot is free
-  int next = rinc(index, NUM_TX_FRAG);
-  while(next == LPC_EMAC->TxConsumeIndex) {
-    for(int i=0; i<1000; i++) { __NOP(); }
-  }
-
-  LPC_EMAC->TxProduceIndex = next;
-  tx_produce_offset = -1;
-  return size;
-
-#else
-    int s = send_size;
-    txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
-    send_idx  = rinc(send_idx, NUM_TX_FRAG);
-    LPC_EMAC->TxProduceIndex = send_idx;
-    send_doff =  0;
-    send_idx  = -1;
-    send_size =  0;
-    return s;
-#endif
-}
-
-// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
-// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
-//
-// if(RxConsumeIndex == RxProduceIndex) buffer array is empty
-// if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
-
-// Recevies an arrived ethernet packet.
-// Receiving an ethernet packet will drop the last received ethernet packet
-// and make a new ethernet packet ready to read.
-// Returns size of packet, else 0 if nothing to receive
-
-// We read from RxConsumeIndex from position rx_consume_offset
-// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
-// rx_consume_offset = -1 // no frame
-// rx_consume_offset = 0  // start of frame
-// Assumption: A fragment should alway be a whole frame
-
-int ethernet_receive() {
-#if NEW_LOGIC
-
-  // if we are currently reading a valid RxConsume buffer, increment to the next one
-  if(rx_consume_offset >= 0) {
-    LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
-  }
-
-  // if the buffer is empty, mark it as no valid buffer
-  if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
-    rx_consume_offset = -1;
-    return 0;
-  }
-
-  uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
-  rx_consume_offset = 0;
-
-  // check if it is not marked as last or for errors
-  if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
-    return -1;
-  }
-
-  int size = (info & RINFO_SIZE) + 1;
-  return size - 4; // don't include checksum bytes
-
-#else
-    if(receive_idx == -1) {
-      receive_idx = LPC_EMAC->RxConsumeIndex;
-    } else {
-        while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && (receive_idx != LPC_EMAC->RxProduceIndex)) {
-            receive_idx  = rinc(receive_idx, NUM_RX_FRAG);
-        }
-        unsigned int info =   rxstat[receive_idx].Info;
-        int slen =  (info & RINFO_SIZE) + 1;
-
-        if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
-            /* Invalid frame, ignore it and free buffer. */
-            receive_idx = rinc(receive_idx, NUM_RX_FRAG);
-        }
-        receive_idx = rinc(receive_idx, NUM_RX_FRAG);
-        receive_soff = 0;
-
-        LPC_EMAC->RxConsumeIndex = receive_idx;
-    }
-
-    if(receive_idx == LPC_EMAC->RxProduceIndex) {
-        receive_idx = -1;
-        return 0;
-    }
-
-    return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
-#endif
-}
-
-// Read from an recevied ethernet packet.
-// After receive returnd a number bigger than 0 it is
-// possible to read bytes from this packet.
-// Read will write up to size bytes into data.
-// It is possible to use read multible times.
-// Each time read will start reading after the last read byte before.
-
-int ethernet_read(char *data, int dlen) {
-#if NEW_LOGIC
-  // Check we have a valid buffer to read
-  if(rx_consume_offset < 0) {
-    return 0;
-  }
-
-  // Assume 1 fragment block
-  uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
-  int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
-
-  int remaining = size - rx_consume_offset;
-  int requested = dlen;
-  int ncopy = min(remaining, requested);
-
-  void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
-  void *pdst = (void *)(data);
-
-  if(data != NULL && ncopy > 0) {
-    memcpy(pdst, psrc, ncopy);
-  }
-
-  rx_consume_offset += ncopy;
-
-  return ncopy;
-#else
-    int          slen;
-    int          copy   = 0;
-    unsigned int more;
-    unsigned int info;
-    void        *pdst, *psrc;
-    int          doff = 0;
-
-    if(receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
-        return 0;
-    }
-
-    do {
-        info =   rxstat[receive_idx].Info;
-        more = !(info & RINFO_LAST_FLAG);
-        slen =  (info & RINFO_SIZE) + 1;
-
-        if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
-            /* Invalid frame, ignore it and free buffer. */
-            receive_idx = rinc(receive_idx, NUM_RX_FRAG);
-        } else {
-
-            copy = min(slen - receive_soff, dlen - doff);
-            psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
-            pdst = (void *)(data + doff);
-
-            if(data != NULL) {
-                /* check if Buffer available */
-                memcpy(pdst, psrc, copy);
-            }
-
-            receive_soff += copy;
-            doff += copy;
-
-            if((more && (receive_soff == slen))) {
-                receive_idx = rinc(receive_idx, NUM_RX_FRAG);
-                receive_soff = 0;
-            }
-        }
-    } while(more && !(doff == dlen) && !receive_soff);
-
-    return doff;
-#endif
-}
-
-int ethernet_link(void) {
-
-    if (phy_id == DP83848C_ID) {
-      return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
-    }
-    else { // LAN8720_ID
-      return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
-    }
-}
-
-static int phy_write(unsigned int PhyReg, unsigned short Data) {
-    unsigned int timeOut;
-
-    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-    LPC_EMAC->MWTD = Data;
-
-    for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) {     /* Wait until operation completed */
-        if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
-            return 0;
-        }
-    }
-
-    return -1;
-}
-
-
-static int phy_read(unsigned int PhyReg) {
-    unsigned int timeOut;
-
-    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-    LPC_EMAC->MCMD = MCMD_READ;
-
-    for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) {     /* Wait until operation completed */
-        if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
-            LPC_EMAC->MCMD = 0;
-            return LPC_EMAC->MRDD;                           /* Return a 16-bit value. */
-        }
-    }
-
-    return -1;
-}
-
-
-static void txdscr_init() {
-    int i;
-
-    for(i = 0; i < NUM_TX_FRAG; i++) {
-        txdesc[i].Packet = (uint32_t)&txbuf[i];
-        txdesc[i].Ctrl   = 0;
-        txstat[i].Info   = 0;
-    }
-
-    LPC_EMAC->TxDescriptor       = (uint32_t)txdesc;         /* Set EMAC Transmit Descriptor Registers. */
-    LPC_EMAC->TxStatus           = (uint32_t)txstat;
-    LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
-
-    LPC_EMAC->TxProduceIndex  = 0;                           /* Tx Descriptors Point to 0 */
-}
-
-
-static void rxdscr_init() {
-    int i;
-
-    for(i = 0; i < NUM_RX_FRAG; i++) {
-        rxdesc[i].Packet  = (uint32_t)&rxbuf[i];
-        rxdesc[i].Ctrl    = RCTRL_INT | (ETH_FRAG_SIZE-1);
-        rxstat[i].Info    = 0;
-        rxstat[i].HashCRC = 0;
-    }
-
-    LPC_EMAC->RxDescriptor       = (uint32_t)rxdesc;        /* Set EMAC Receive Descriptor Registers. */
-    LPC_EMAC->RxStatus           = (uint32_t)rxstat;
-    LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
-
-    LPC_EMAC->RxConsumeIndex  = 0;                          /* Rx Descriptors Point to 0 */
-}
-
-void ethernet_address(char *mac) {
-    mbed_mac_address(mac);
-}
-
-void ethernet_set_link(int speed, int duplex) {
-    unsigned short phy_data;
-    int tout;
-    
-    if((speed < 0) || (speed > 1)) {
-        phy_data = PHY_AUTO_NEG;
-    } else {
-        phy_data = (((unsigned short) speed << 13) |
-                    ((unsigned short) duplex << 8));
-    }
-    
-    phy_write(PHY_REG_BMCR, phy_data);
-    
-    for (tout = 100; tout; tout--) { __NOP(); }     /* A short delay */
-    
-    switch(phy_id) {
-        case DP83848C_ID:
-            phy_data = phy_read(PHY_REG_STS);
-            
-            if(phy_data & PHY_STS_DUPLEX) {
-                LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
-                LPC_EMAC->Command |= CR_FULL_DUP;
-                LPC_EMAC->IPGT = IPGT_FULL_DUP;
-            } else {
-            LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
-                LPC_EMAC->Command &= ~CR_FULL_DUP;
-                LPC_EMAC->IPGT = IPGT_HALF_DUP;
-            }
-            
-            if(phy_data & PHY_STS_SPEED) {
-                LPC_EMAC->SUPP &= ~SUPP_SPEED;
-            } else {
-                LPC_EMAC->SUPP |= SUPP_SPEED;
-            }
-            break;
-        
-        case LAN8720_ID:
-            phy_data = phy_read(PHY_REG_SCSR);
-            
-            if (phy_data & PHY_SCSR_DUPLEX) {
-                LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
-                LPC_EMAC->Command |= CR_FULL_DUP;
-                LPC_EMAC->IPGT = IPGT_FULL_DUP;
-            } else {
-                LPC_EMAC->Command &= ~CR_FULL_DUP;
-                LPC_EMAC->IPGT = IPGT_HALF_DUP;
-            }
-            
-            if(phy_data & PHY_SCSR_100MBIT) {
-                LPC_EMAC->SUPP |= SUPP_SPEED;
-            } else {
-                LPC_EMAC->SUPP &= ~SUPP_SPEED;
-            }
-            
-            break;
-    }
-}

--- a/vendor/NXP/LPC4088/hal/gpio_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "gpio_api.h"
-#include "pinmap.h"
-
-uint32_t gpio_set(PinName pin) {
-    pin_function(pin, 0);
-    return (1 << ((int)pin & 0x1F));
-}
-
-void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
-    if (pin == NC) return;
-    
-    obj->pin = pin;
-    obj->mask = gpio_set(pin);
-    
-    LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *) ((int)(LPC_GPIO0_BASE+pin) & ~0x1F);
-    
-    obj->reg_set = &port_reg->SET;
-    obj->reg_clr = &port_reg->CLR;
-    obj->reg_in  = &port_reg->PIN;
-    obj->reg_dir = &port_reg->DIR;
-    
-    gpio_dir(obj, direction);
-    switch (direction) {
-        case PIN_OUTPUT: pin_mode(pin, PullNone); break;
-        case PIN_INPUT : pin_mode(pin, PullDown); break;
-    }
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode) {
-    pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction) {
-    switch (direction) {
-        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
-        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
-    }
-}

--- a/vendor/NXP/LPC4088/hal/gpio_irq_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,144 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stddef.h>
-#include "gpio_irq_api.h"
-#include "error.h"
-#include "cmsis.h"
-
-#define CHANNEL_NUM    64
-
-static uint32_t channel_ids[CHANNEL_NUM] = {0};
-static gpio_irq_handler irq_handler;
-
-static void handle_interrupt_in(void) {
-    // Read in all current interrupt registers. We do this once as the
-    // GPIO interrupt registers are on the APB bus, and this is slow.
-    uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
-    uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
-    uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
-    uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
-    uint32_t mask0 = 0;
-    uint32_t mask2 = 0;
-    int i;
-    
-    // P0.0-0.31
-    for (i = 0; i < 32; i++) {
-        uint32_t pmask = (1 << i);
-        if (rise0 & pmask) {
-            mask0 |= pmask;
-            if (channel_ids[i] != 0)
-                irq_handler(channel_ids[i], IRQ_RISE);
-        }
-        if (fall0 & pmask) {
-            mask0 |= pmask;
-            if (channel_ids[i] != 0)
-                irq_handler(channel_ids[i], IRQ_FALL);
-        }
-    }
-    
-    // P2.0-2.31
-    for (i = 0; i < 32; i++) {
-        uint32_t pmask = (1 << i);
-        int channel_index = i + 32;
-        if (rise2 & pmask) {
-            mask2 |= pmask;
-            if (channel_ids[channel_index] != 0)
-                irq_handler(channel_ids[channel_index], IRQ_RISE);
-        }
-        if (fall2 & pmask) {
-            mask2 |= pmask;
-            if (channel_ids[channel_index] != 0)
-                irq_handler(channel_ids[channel_index], IRQ_FALL);
-        }
-    }
-    
-    // Clear the interrupts we just handled
-    LPC_GPIOINT->IO0IntClr = mask0;
-    LPC_GPIOINT->IO2IntClr = mask2;
-}
-
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
-    if (pin == NC) return -1;
-    
-    irq_handler = handler;
-    
-    obj->port = ((int)(LPC_GPIO0_BASE+pin) & ~0x1F);
-    obj->pin = (int)pin % 32;
-    
-    // Interrupts available only on GPIO0 and GPIO2
-    if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
-        error("pins on this port cannot generate interrupts\n");
-    }
-    
-    // put us in the interrupt table
-    int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
-    channel_ids[index] = id;
-    obj->ch = index;
-    
-    NVIC_SetVector(GPIO_IRQn, (uint32_t)handle_interrupt_in);
-    NVIC_EnableIRQ(GPIO_IRQn);
-    
-    return 0;
-}
-
-void gpio_irq_free(gpio_irq_t *obj) {
-    channel_ids[obj->ch] = 0;
-}
-
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
-    // ensure nothing is pending
-    switch (obj->port) {
-         case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
-         case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
-    }
-    
-    // enable the pin interrupt
-    if (event == IRQ_RISE) {
-        switch (obj->port) {
-            case LPC_GPIO0_BASE:
-                if (enable) {
-                    LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
-                } else {
-                    LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
-                }
-                break;
-            case LPC_GPIO2_BASE:
-                if (enable) {
-                    LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
-                } else {
-                    LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
-                }
-                break;
-        }
-    } else {
-        switch (obj->port) {
-            case LPC_GPIO0_BASE:
-                if (enable) {
-                    LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
-                } else {
-                    LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
-                }
-                break;
-            case LPC_GPIO2_BASE:
-                if (enable) {
-                    LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
-                } else {
-                    LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
-                }
-                break;
-        }
-    }
-}

--- a/vendor/NXP/LPC4088/hal/gpio_object.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    PinName  pin;
-    uint32_t mask;
-
-    __IO uint32_t *reg_dir;
-    __IO uint32_t *reg_set;
-    __IO uint32_t *reg_clr;
-    __I  uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
-    if (value)
-        *obj->reg_set = obj->mask;
-    else
-        *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
-    return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC4088/hal/i2c_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,402 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "i2c_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_I2C_SDA[] = {
-    {P0_0 , I2C_1, 3},
-    {P0_10, I2C_2, 2},
-    {P0_19, I2C_1, 3},
-    {P0_27, I2C_0, 1},
-    {P1_15, I2C_2, 3},
-    {P1_30, I2C_0, 4},
-    {P2_14, I2C_1, 2},
-    {P2_30, I2C_2, 2},
-    {P4_20, I2C_2, 4},
-    {P5_2,  I2C_0, 5},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_I2C_SCL[] = {
-    {P0_1 , I2C_1, 3},
-    {P0_11, I2C_2, 2},
-    {P0_20, I2C_1, 3},
-    {P0_28, I2C_0, 1},
-    {P1_31, I2C_0, 4},
-    {P2_15, I2C_1, 2},
-    {P2_31, I2C_2, 2},
-    {P4_21, I2C_2, 2},
-    {P4_29, I2C_2, 4},
-    {P5_3,  I2C_0, 5},
-    {NC   , NC,    0}
-};
-
-#define I2C_CONSET(x)       (x->i2c->CONSET)
-#define I2C_CONCLR(x)       (x->i2c->CONCLR)
-#define I2C_STAT(x)         (x->i2c->STAT)
-#define I2C_DAT(x)          (x->i2c->DAT)
-#define I2C_SCLL(x, val)    (x->i2c->SCLL = val)
-#define I2C_SCLH(x, val)    (x->i2c->SCLH = val)
-
-static const uint32_t I2C_addr_offset[2][4] = {
-    {0x0C, 0x20, 0x24, 0x28},
-    {0x30, 0x34, 0x38, 0x3C}
-};
-
-static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
-    I2C_CONCLR(obj) = (start << 5)
-                    | (stop << 4)
-                    | (interrupt << 3)
-                    | (acknowledge << 2);
-}
-
-static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
-    I2C_CONSET(obj) = (start << 5)
-                    | (stop << 4)
-                    | (interrupt << 3)
-                    | (acknowledge << 2);
-}
-
-// Clear the Serial Interrupt (SI)
-static inline void i2c_clear_SI(i2c_t *obj) {
-    i2c_conclr(obj, 0, 0, 1, 0);
-}
-
-static inline int i2c_status(i2c_t *obj) {
-    return I2C_STAT(obj);
-}
-
-// Wait until the Serial Interrupt (SI) is set
-static int i2c_wait_SI(i2c_t *obj) {
-    int timeout = 0;
-    while (!(I2C_CONSET(obj) & (1 << 3))) {
-        timeout++;
-        if (timeout > 100000) return -1;
-    }
-    return 0;
-}
-
-static inline void i2c_interface_enable(i2c_t *obj) {
-    I2C_CONSET(obj) = 0x40;
-}
-
-static inline void i2c_power_enable(i2c_t *obj) {
-    switch ((int)obj->i2c) {
-        case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
-        case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
-        case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
-    }
-}
-
-void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
-    // determine the SPI to use
-    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
-    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
-    obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
-    if ((int)obj->i2c == NC) {
-        error("I2C pin mapping failed");
-    }
-    
-    // enable power
-    i2c_power_enable(obj);
-    
-    // set default frequency at 100k
-    i2c_frequency(obj, 100000);
-    i2c_conclr(obj, 1, 1, 1, 1);
-    i2c_interface_enable(obj);
-    
-    pinmap_pinout(sda, PinMap_I2C_SDA);
-    pinmap_pinout(scl, PinMap_I2C_SCL);
-}
-
-inline int i2c_start(i2c_t *obj) {
-    int status = 0;
-    // 8.1 Before master mode can be entered, I2CON must be initialised to:
-    //  - I2EN STA STO SI AA - -
-    //  -  1    0   0   0  x - -
-    // if AA = 0, it can't enter slave mode
-    i2c_conclr(obj, 1, 1, 1, 1);
-    
-    // The master mode may now be entered by setting the STA bit
-    // this will generate a start condition when the bus becomes free
-    i2c_conset(obj, 1, 0, 0, 1);
-    
-    i2c_wait_SI(obj);
-    status = i2c_status(obj);
-    
-    // Clear start bit now transmitted, and interrupt bit
-    i2c_conclr(obj, 1, 0, 0, 0);
-    return status;
-}
-
-inline void i2c_stop(i2c_t *obj) {
-    // write the stop bit
-    i2c_conset(obj, 0, 1, 0, 0);
-    i2c_clear_SI(obj);
-    
-    // wait for STO bit to reset
-    while(I2C_CONSET(obj) & (1 << 4));
-}
-
-
-static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
-    // write the data
-    I2C_DAT(obj) = value;
-    
-    // clear SI to init a send
-    i2c_clear_SI(obj);
-    
-    // wait and return status
-    i2c_wait_SI(obj);
-    return i2c_status(obj);
-}
-
-static inline int i2c_do_read(i2c_t *obj, int last) {
-    // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
-    if(last) {
-        i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
-    } else {
-        i2c_conset(obj, 0, 0, 0, 1); // send a ACK
-    }
-    
-    // accept byte
-    i2c_clear_SI(obj);
-    
-    // wait for it to arrive
-    i2c_wait_SI(obj);
-    
-    // return the data
-    return (I2C_DAT(obj) & 0xFF);
-}
-
-void i2c_frequency(i2c_t *obj, int hz) {
-    uint32_t PCLK = PeripheralClock;
-    uint32_t pulse = PCLK / (hz * 2);
-    
-    // I2C Rate
-    I2C_SCLL(obj, pulse);
-    I2C_SCLH(obj, pulse);
-}
-
-// The I2C does a read or a write as a whole operation
-// There are two types of error conditions it can encounter
-//  1) it can not obtain the bus
-//  2) it gets error responses at part of the transmission
-//
-// We tackle them as follows:
-//  1) we retry until we get the bus. we could have a "timeout" if we can not get it
-//      which basically turns it in to a 2)
-//  2) on error, we use the standard error mechanisms to report/debug
-//
-// Therefore an I2C transaction should always complete. If it doesn't it is usually
-// because something is setup wrong (e.g. wiring), and we don't need to programatically
-// check for that
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
-    int count, status;
-    
-    status = i2c_start(obj);
-    
-    if ((status != 0x10) && (status != 0x08)) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    status = i2c_do_write(obj, (address | 0x01), 1);
-    if (status != 0x40) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    // Read in all except last byte
-    for (count = 0; count < (length - 1); count++) {
-        int value = i2c_do_read(obj, 0);
-        status = i2c_status(obj);
-        if (status != 0x50) {
-            i2c_stop(obj);
-            return status;
-        }
-        data[count] = (char) value;
-    }
-    
-    // read in last byte
-    int value = i2c_do_read(obj, 1);
-    status = i2c_status(obj);
-    if (status != 0x58) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    data[count] = (char) value;
-    
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-    }
-    
-    return 0;
-}
-
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
-    int i, status;
-    
-    status = i2c_start(obj);
-    
-    if ((status != 0x10) && (status != 0x08)) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    status = i2c_do_write(obj, (address & 0xFE), 1);
-    if (status != 0x18) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    for (i=0; i<length; i++) {
-        status = i2c_do_write(obj, data[i], 0);
-        if (status != 0x28) {
-            i2c_stop(obj);
-            return status;
-        }
-    }
-    
-    // clearing the serial interrupt here might cause an unintended rewrite of the last byte
-    // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
-    // i2c_clear_SI(obj);
-    
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-    }
-    
-    return 0;
-}
-
-void i2c_reset(i2c_t *obj) {
-    i2c_stop(obj);
-}
-
-int i2c_byte_read(i2c_t *obj, int last) {
-    return (i2c_do_read(obj, last) & 0xFF);
-}
-
-int i2c_byte_write(i2c_t *obj, int data) {
-    int ack;
-    int status = i2c_do_write(obj, (data & 0xFF), 0);
-    
-    switch(status) {
-        case 0x18: case 0x28:       // Master transmit ACKs
-            ack = 1;
-            break;
-        
-        case 0x40:                  // Master receive address transmitted ACK
-            ack = 1;
-            break;
-        
-        case 0xB8:                  // Slave transmit ACK
-            ack = 1;
-            break;
-        
-        default:
-            ack = 0;
-            break;
-    }
-    
-    return ack;
-}
-
-void i2c_slave_mode(i2c_t *obj, int enable_slave) {
-    if (enable_slave != 0) {
-        i2c_conclr(obj, 1, 1, 1, 0);
-        i2c_conset(obj, 0, 0, 0, 1);
-    } else {
-        i2c_conclr(obj, 1, 1, 1, 1);
-    }
-}
-
-int i2c_slave_receive(i2c_t *obj) {
-    int status;
-    int retval;
-    
-    status = i2c_status(obj);
-    switch(status) {
-        case 0x60: retval = 3; break;
-        case 0x70: retval = 2; break;
-        case 0xA8: retval = 1; break;
-        default  : retval = 0; break;
-    }
-    
-    return(retval);
-}
-
-int i2c_slave_read(i2c_t *obj, char *data, int length) {
-    int count = 0;
-    int status;
-    
-    do {
-        i2c_clear_SI(obj);
-        i2c_wait_SI(obj);
-        status = i2c_status(obj);
-        if((status == 0x80) || (status == 0x90)) {
-            data[count] = I2C_DAT(obj) & 0xFF;
-        }
-        count++;
-    } while (((status == 0x80) || (status == 0x90) ||
-            (status == 0x060) || (status == 0x70)) && (count < length));
-    
-    if(status != 0xA0) {
-        i2c_stop(obj);
-    }
-    
-    i2c_clear_SI(obj);
-    
-    return (count - 1);
-}
-
-int i2c_slave_write(i2c_t *obj, const char *data, int length) {
-    int count = 0;
-    int status;
-    
-    if(length <= 0) {
-        return(0);
-    }
-    
-    do {
-        status = i2c_do_write(obj, data[count], 0);
-        count++;
-    } while ((count < length) && (status == 0xB8));
-    
-    if((status != 0xC0) && (status != 0xC8)) {
-        i2c_stop(obj);
-    }
-    
-    i2c_clear_SI(obj);
-    
-    return(count);
-}
-
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
-    uint32_t addr;
-    
-    if ((idx >= 0) && (idx <= 3)) {
-        addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
-        *((uint32_t *) addr) = address & 0xFF;
-        addr = ((uint32_t)obj->i2c) + I2C_addr_offset[1][idx];
-        *((uint32_t *) addr) = mask & 0xFE;
-    }
-}

--- a/vendor/NXP/LPC4088/hal/objects.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,79 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    uint32_t port;
-    uint32_t pin;
-    uint32_t ch;
-};
-
-struct port_s {
-    __IO uint32_t *reg_dir;
-    __IO uint32_t *reg_out;
-    __I  uint32_t *reg_in;
-    PortName port;
-    uint32_t mask;
-};
-
-struct pwmout_s {
-    __IO uint32_t *MR;
-    LPC_PWM_TypeDef *pwm;
-    uint32_t channel;
-};
-
-struct serial_s {
-    LPC_UART_TypeDef *uart;
-    int index;
-};
-
-struct analogin_s {
-    ADCName adc;
-};
-
-struct dac_s {
-    DACName dac;
-};
-
-struct can_s {
-    LPC_CAN_TypeDef *dev;
-};
-
-struct i2c_s {
-    LPC_I2C_TypeDef *i2c;
-};
-
-struct spi_s {
-    LPC_SSP_TypeDef *spi;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC4088/hal/pinmap.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "pinmap.h"
-#include "error.h"
-
-void pin_function(PinName pin, int function) {
-    if (pin == (uint32_t)NC) return;
-    
-    __IO uint32_t *reg = (__IO uint32_t*) (LPC_IOCON_BASE + 4 * pin);
-    
-    // pin function bits: [2:0] -> 111 = (0x7)
-    *reg = (*reg & ~0x7) | (function & 0x7);
-}
-
-void pin_mode(PinName pin, PinMode mode) {
-    if (pin == (uint32_t)NC) { return; }
-    
-    uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2;
-    
-    __IO uint32_t *reg = (__IO uint32_t*) (LPC_IOCON_BASE + 4 * pin);
-    uint32_t tmp = *reg;
-    
-    // pin mode bits: [4:3] -> 11000 = (0x3 << 3)
-    tmp &= ~(0x3 << 3);
-    tmp |= (mode & 0x3) << 3;
-    
-    // drain
-    tmp &= ~(0x1 << 10);
-    tmp |= drain << 10;
-    
-    *reg = tmp;
-}

--- a/vendor/NXP/LPC4088/hal/port_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,70 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "port_api.h"
-#include "pinmap.h"
-#include "gpio_api.h"
-
-PinName port_pin(PortName port, int pin_n) {
-    return (PinName)(LPC_GPIO0_BASE + ((port << PORT_SHIFT) | pin_n));
-}
-
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
-    obj->port = port;
-    obj->mask = mask;
-    
-    LPC_GPIO_TypeDef *port_reg = (LPC_GPIO_TypeDef *)(LPC_GPIO0_BASE + ((int)port * 0x20));
-    
-    port_reg->MASK = ~mask;
-    
-    obj->reg_out = &port_reg->PIN;
-    obj->reg_in  = &port_reg->PIN;
-    obj->reg_dir  = &port_reg->DIR;
-    
-    uint32_t i;
-    // The function is set per pin: reuse gpio logic
-    for (i=0; i<32; i++) {
-        if (obj->mask & (1<<i)) {
-            gpio_set(port_pin(obj->port, i));
-        }
-    }
-    
-    port_dir(obj, dir);
-}
-
-void port_mode(port_t *obj, PinMode mode) {
-    uint32_t i;
-    // The mode is set per pin: reuse pinmap logic
-    for (i=0; i<32; i++) {
-        if (obj->mask & (1<<i)) {
-            pin_mode(port_pin(obj->port, i), mode);
-        }
-    }
-}
-
-void port_dir(port_t *obj, PinDirection dir) {
-    switch (dir) {
-        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
-        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
-    }
-}
-
-void port_write(port_t *obj, int value) {
-    *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
-}
-
-int port_read(port_t *obj) {
-    return (*obj->reg_in & obj->mask);
-}

--- a/vendor/NXP/LPC4088/hal/pwmout_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,190 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "pwmout_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-#define TCR_CNT_EN       0x00000001
-#define TCR_RESET        0x00000002
-
-//  PORT ID, PWM ID, Pin function
-static const PinMap PinMap_PWM[] = {
-    {P1_2,  PWM0_1, 3},
-    {P1_3,  PWM0_2, 3},
-    {P1_5,  PWM0_3, 3},
-    {P1_6,  PWM0_4, 3},
-    {P1_7,  PWM0_5, 3},
-    {P1_11, PWM0_6, 3},
-    {P1_18, PWM1_1, 2},
-    {P1_20, PWM1_2, 2},
-    {P1_21, PWM1_3, 2},
-    {P1_23, PWM1_4, 2},
-    {P1_24, PWM1_5, 2},
-    {P1_26, PWM1_6, 2},
-    {P2_0,  PWM1_1, 1},
-    {P2_1,  PWM1_2, 1},
-    {P2_2,  PWM1_3, 1},
-    {P2_3,  PWM1_4, 1},
-    {P2_4,  PWM1_5, 1},
-    {P2_5,  PWM1_6, 1},
-    {P3_16, PWM0_1, 2},
-    {P3_17, PWM0_2, 2},
-    {P3_18, PWM0_3, 2},
-    {P3_19, PWM0_4, 2},
-    {P3_20, PWM0_5, 2},
-    {P3_21, PWM0_6, 2},
-    {P3_24, PWM1_1, 2},
-    {P3_25, PWM1_2, 2},
-    {P3_26, PWM1_3, 2},
-    {P3_27, PWM1_4, 2},
-    {P3_28, PWM1_5, 2},
-    {P3_29, PWM1_6, 2},
-    {NC, NC, 0}
-};
-
-static const uint32_t PWM_mr_offset[7] = {
-    0x18, 0x1C, 0x20, 0x24, 0x40, 0x44, 0x48
-};
-
-#define TCR_PWM_EN       0x00000008
-static unsigned int pwm_clock_mhz;
-
-void pwmout_init(pwmout_t* obj, PinName pin) {
-    // determine the channel
-    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
-    if (pwm == (uint32_t)NC)
-        error("PwmOut pin mapping failed");
-    
-    obj->channel = pwm;
-    obj->pwm = LPC_PWM0;
-    
-    if (obj->channel > 6) { // PWM1 is used if pwm > 6
-      obj->channel -= 6;
-      obj->pwm = LPC_PWM1;
-    }
-    
-    obj->MR = (__IO uint32_t *)((uint32_t)obj->pwm + PWM_mr_offset[obj->channel]);
-    
-    // ensure the power is on
-    if (obj->pwm == LPC_PWM0) {
-        LPC_SC->PCONP |= 1 << 5;
-    } else {
-        LPC_SC->PCONP |= 1 << 6;
-    }
-    
-    obj->pwm->PR = 0;                     // no pre-scale
-    
-    // ensure single PWM mode
-    obj->pwm->MCR = 1 << 1; // reset TC on match 0
-    
-    // enable the specific PWM output
-    obj->pwm->PCR |= 1 << (8 + obj->channel);
-    
-    pwm_clock_mhz = PeripheralClock / 1000000;
-    
-    // default to 20ms: standard for servos, and fine for e.g. brightness control
-    pwmout_period_ms(obj, 20);
-    pwmout_write    (obj, 0);
-    
-    // Wire pinout
-    pinmap_pinout(pin, PinMap_PWM);
-}
-
-void pwmout_free(pwmout_t* obj) {
-    // [TODO]
-}
-
-void pwmout_write(pwmout_t* obj, float value) {
-    if (value < 0.0f) {
-        value = 0.0;
-    } else if (value > 1.0f) {
-        value = 1.0;
-    }
-    
-    // set channel match to percentage
-    uint32_t v = (uint32_t)((float)(obj->pwm->MR0) * value);
-    
-    // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
-    if (v == obj->pwm->MR0) {
-        v++;
-    }
-    
-    *obj->MR = v;
-    
-    // accept on next period start
-    obj->pwm->LER |= 1 << obj->channel;
-}
-
-float pwmout_read(pwmout_t* obj) {
-    float v = (float)(*obj->MR) / (float)(obj->pwm->MR0);
-    return (v > 1.0f) ? (1.0f) : (v);
-}
-
-void pwmout_period(pwmout_t* obj, float seconds) {
-    pwmout_period_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_period_ms(pwmout_t* obj, int ms) {
-    pwmout_period_us(obj, ms * 1000);
-}
-
-// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us) {
-    // calculate number of ticks
-    uint32_t ticks = pwm_clock_mhz * us;
-    
-    // set reset
-    obj->pwm->TCR = TCR_RESET;
-    
-    // set the global match register
-    obj->pwm->MR0 = ticks;
-    
-    // Scale the pulse width to preserve the duty ratio
-    if (obj->pwm->MR0 > 0) {
-        *obj->MR = (*obj->MR * ticks) / obj->pwm->MR0;
-    }
-    
-    // set the channel latch to update value at next period start
-    obj->pwm->LER |= 1 << 0;
-    
-    // enable counter and pwm, clear reset
-    obj->pwm->TCR = TCR_CNT_EN | TCR_PWM_EN;
-}
-
-void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
-    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
-    pwmout_pulsewidth_us(obj, ms * 1000);
-}
-
-void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
-    // calculate number of ticks
-    uint32_t v = pwm_clock_mhz * us;
-    
-    // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout
-    if (v == obj->pwm->MR0) {
-        v++;
-    }
-    
-    // set the match register value
-    *obj->MR = v;
-    
-    // set the channel latch to update value at next period start
-    obj->pwm->LER |= 1 << obj->channel;
-}

--- a/vendor/NXP/LPC4088/hal/rtc_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,114 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "rtc_api.h"
-
-// ensure rtc is running (unchanged if already running)
-
-/* Setup the RTC based on a time structure, ensuring RTC is enabled
- *
- * Can be clocked by a 32.768KHz oscillator or prescale divider based on the APB clock
- * - We want to use the 32khz clock, allowing for sleep mode
- *
- * Most registers are not changed by a Reset
- * - We must initialize these registers between power-on and setting the RTC into operation
-
- * Clock Control Register
- *  RTC_CCR[0] : Enable - 0 = Disabled, 1 = Enabled
- *  RTC_CCR[1] : Reset - 0 = Normal, 1 = Reset
- *  RTC_CCR[4] : Clock Source - 0 = Prescaler, 1 = 32k Xtal
- *
- * The RTC may already be running, so we should set it up
- * without impacting if it is the case
- */
-void rtc_init(void) {
-    LPC_SC->PCONP |= 0x200; // Ensure power is on
-    LPC_RTC->CCR = 0x00;
-    
-// clock source on 2368 is special test mode on 1768!
-    LPC_RTC->CCR |= 1 << 0; // Ensure the RTC is enabled
-}
-
-void rtc_free(void) {
-    // [TODO]
-}
-
-/*
- * Little check routine to see if the RTC has been enabled
- *
- * Clock Control Register
- *  RTC_CCR[0] : 0 = Disabled, 1 = Enabled
- *
- */
-int rtc_isenabled(void) {
-    return(((LPC_RTC->CCR) & 0x01) != 0);
-}
-
-/*
- * RTC Registers
- *  RTC_SEC        Seconds 0-59
- *  RTC_MIN        Minutes 0-59
- *  RTC_HOUR    Hour 0-23
- *  RTC_DOM        Day of Month 1-28..31
- *  RTC_DOW        Day of Week 0-6
- *  RTC_DOY        Day of Year 1-365
- *  RTC_MONTH    Month 1-12
- *  RTC_YEAR    Year 0-4095
- *
- * struct tm
- *  tm_sec        seconds after the minute 0-61
- *  tm_min        minutes after the hour 0-59
- *  tm_hour        hours since midnight 0-23
- *  tm_mday        day of the month 1-31
- *  tm_mon        months since January 0-11
- *  tm_year        years since 1900
- *  tm_wday        days since Sunday 0-6
- *  tm_yday        days since January 1 0-365
- *  tm_isdst    Daylight Saving Time flag
- */
-time_t rtc_read(void) {
-    // Setup a tm structure based on the RTC
-    struct tm timeinfo;
-    timeinfo.tm_sec = LPC_RTC->SEC;
-    timeinfo.tm_min = LPC_RTC->MIN;
-    timeinfo.tm_hour = LPC_RTC->HOUR;
-    timeinfo.tm_mday = LPC_RTC->DOM;
-    timeinfo.tm_mon = LPC_RTC->MONTH - 1;
-    timeinfo.tm_year = LPC_RTC->YEAR - 1900;
-    
-    // Convert to timestamp
-    time_t t = mktime(&timeinfo);
-    
-    return t;
-}
-
-void rtc_write(time_t t) {
-    // Convert the time in to a tm
-    struct tm *timeinfo = localtime(&t);
-    
-    // Pause clock, and clear counter register (clears us count)
-    LPC_RTC->CCR |= 2;
-    
-    // Set the RTC
-    LPC_RTC->SEC = timeinfo->tm_sec;
-    LPC_RTC->MIN = timeinfo->tm_min;
-    LPC_RTC->HOUR = timeinfo->tm_hour;
-    LPC_RTC->DOM = timeinfo->tm_mday;
-    LPC_RTC->MONTH = timeinfo->tm_mon + 1;
-    LPC_RTC->YEAR = timeinfo->tm_year + 1900;
-    
-    // Restart clock
-    LPC_RTC->CCR &= ~((uint32_t)2);
-}

--- a/vendor/NXP/LPC4088/hal/serial_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,302 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// math.h required for floating point operations for baud rate calculation
-#include <math.h>
-#include <string.h>
-
-#include "serial_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-/******************************************************************************
- * INITIALIZATION
- ******************************************************************************/
-static const PinMap PinMap_UART_TX[] = {
-    {P0_0,  UART_3, 2},
-    {P0_2,  UART_0, 1},
-    {P0_10, UART_2, 1},
-    {P0_15, UART_1, 1},
-    {P1_29, UART_4, 5},
-    {P0_25, UART_3, 3},
-    {P2_0 , UART_1, 2},
-    {P2_8 , UART_2, 2},
-    {P3_16, UART_1, 3},
-    {P4_22, UART_2, 2},
-    {P4_28, UART_3, 2},
-    {P5_4,  UART_4, 4},
-    {NC   , NC    , 0}
-};
-
-static const PinMap PinMap_UART_RX[] = {
-    {P0_1 , UART_3, 2},
-    {P0_3 , UART_0, 1},
-    {P0_11, UART_2, 1},
-    {P0_16, UART_1, 1},
-    {P0_26, UART_3, 3},
-    {P2_1 , UART_1, 2},
-    {P2_9 , UART_2, 2},
-    {P3_17, UART_1, 3},
-    {P4_23, UART_2, 2},
-    {P4_29, UART_3, 2},
-    {P5_3,  UART_4, 4},
-    {NC   , NC    , 0}
-};
-
-#define UART_NUM    5
-
-static uint32_t serial_irq_ids[UART_NUM] = {0};
-static uart_irq_handler irq_handler;
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
-    int is_stdio_uart = 0;
-    
-    // determine the UART to use
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-    UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    if ((int)uart == NC) {
-        error("Serial pinout mapping failed");
-    }
-    
-    obj->uart = (LPC_UART_TypeDef *)uart;
-    // enable power
-    switch (uart) {
-        case UART_0: LPC_SC->PCONP |= 1 <<  3; break;
-        case UART_1: LPC_SC->PCONP |= 1 <<  4; break;
-        case UART_2: LPC_SC->PCONP |= 1 << 24; break;
-        case UART_3: LPC_SC->PCONP |= 1 << 25; break;
-        case UART_4: LPC_SC->PCONP |= 1 <<  8; break;
-    }
-    
-    // enable fifos and default rx trigger level
-    obj->uart->FCR = 1 << 0  // FIFO Enable - 0 = Disables, 1 = Enabled
-                   | 0 << 1  // Rx Fifo Reset
-                   | 0 << 2  // Tx Fifo Reset
-                   | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
-
-    // disable irqs
-    obj->uart->IER = 0 << 0  // Rx Data available irq enable
-                   | 0 << 1  // Tx Fifo empty irq enable
-                   | 0 << 2; // Rx Line Status irq enable
-    
-    // set default baud rate and format
-    serial_baud  (obj, 9600);
-    serial_format(obj, 8, ParityNone, 1);
-    
-    // pinout the chosen uart
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    
-    // set rx/tx pins in PullUp mode
-    pin_mode(tx, PullUp);
-    pin_mode(rx, PullUp);
-    
-    switch (uart) {
-        case UART_0: obj->index = 0; break;
-        case UART_1: obj->index = 1; break;
-        case UART_2: obj->index = 2; break;
-        case UART_3: obj->index = 3; break;
-        case UART_4: obj->index = 4; break;
-    }
-    
-    is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
-    
-    if (is_stdio_uart) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj) {
-    serial_irq_ids[obj->index] = 0;
-}
-
-// serial_baud
-// set the baud rate, taking in to account the current SystemFrequency
-void serial_baud(serial_t *obj, int baudrate) {
-    uint32_t PCLK = PeripheralClock;
-    
-    // First we check to see if the basic divide with no DivAddVal/MulVal
-    // ratio gives us an integer result. If it does, we set DivAddVal = 0,
-    // MulVal = 1. Otherwise, we search the valid ratio value range to find
-    // the closest match. This could be more elegant, using search methods
-    // and/or lookup tables, but the brute force method is not that much
-    // slower, and is more maintainable.
-    uint16_t DL = PCLK / (16 * baudrate);
-
-    uint8_t DivAddVal = 0;
-    uint8_t MulVal = 1;
-    int hit = 0;
-    uint16_t dlv;
-    uint8_t mv, dav;
-    if ((PCLK % (16 * baudrate)) != 0) {     // Checking for zero remainder
-        float err_best = (float) baudrate;
-        uint16_t dlmax = DL;
-        for ( dlv = (dlmax/2); (dlv <= dlmax) && !hit; dlv++) {
-            for ( mv = 1; mv <= 15; mv++) {
-                for ( dav = 1; dav < mv; dav++) {
-                    float ratio = 1.0f + ((float) dav / (float) mv);
-                    float calcbaud = (float)PCLK / (16.0f * (float) dlv * ratio);
-                    float err = fabs(((float) baudrate - calcbaud) / (float) baudrate);
-                    if (err < err_best) {
-                        DL = dlv;
-                        DivAddVal = dav;
-                        MulVal = mv;
-                        err_best = err;
-                        if (err < 0.001f) {
-                            hit = 1;
-                        }
-                    }
-                }
-            }
-        }
-    }
-    
-    // set LCR[DLAB] to enable writing to divider registers
-    obj->uart->LCR |= (1 << 7);
-    
-    // set divider values
-    obj->uart->DLM = (DL >> 8) & 0xFF;
-    obj->uart->DLL = (DL >> 0) & 0xFF;
-    obj->uart->FDR = (uint32_t) DivAddVal << 0
-                   | (uint32_t) MulVal    << 4;
-    
-    // clear LCR[DLAB]
-    obj->uart->LCR &= ~(1 << 7);
-}
-
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
-    // 0: 1 stop bits, 1: 2 stop bits
-    if (stop_bits != 1 && stop_bits != 2) {
-        error("Invalid stop bits specified");
-    }
-    stop_bits -= 1;
-    
-    // 0: 5 data bits ... 3: 8 data bits
-    if (data_bits < 5 || data_bits > 8) {
-        error("Invalid number of bits (%d) in serial format, should be 5..8", data_bits);
-    }
-    data_bits -= 5;
-
-    int parity_enable, parity_select;
-    switch (parity) {
-        case ParityNone: parity_enable = 0; parity_select = 0; break;
-        case ParityOdd : parity_enable = 1; parity_select = 0; break;
-        case ParityEven: parity_enable = 1; parity_select = 1; break;
-        case ParityForced1: parity_enable = 1; parity_select = 2; break;
-        case ParityForced0: parity_enable = 1; parity_select = 3; break;
-        default:
-            error("Invalid serial parity setting");
-            return;
-    }
-    
-    obj->uart->LCR = data_bits            << 0
-                   | stop_bits            << 2
-                   | parity_enable        << 3
-                   | parity_select        << 4;
-}
-
-/******************************************************************************
- * INTERRUPTS HANDLING
- ******************************************************************************/
-static inline void uart_irq(uint32_t iir, uint32_t index) {
-    // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
-    SerialIrq irq_type;
-    switch (iir) {
-        case 1: irq_type = TxIrq; break;
-        case 2: irq_type = RxIrq; break;
-        default: return;
-    }
-    
-    if (serial_irq_ids[index] != 0)
-        irq_handler(serial_irq_ids[index], irq_type);
-}
-
-void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0);}
-void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1);}
-void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2);}
-void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3);}
-void uart4_irq() {uart_irq((LPC_UART4->IIR >> 1) & 0x7, 4);}
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
-    irq_handler = handler;
-    serial_irq_ids[obj->index] = id;
-}
-
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
-    IRQn_Type irq_n = (IRQn_Type)0;
-    uint32_t vector = 0;
-    switch ((int)obj->uart) {
-        case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
-        case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
-        case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
-        case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
-        case UART_4: irq_n=UART4_IRQn; vector = (uint32_t)&uart4_irq; break;
-    }
-    
-    if (enable) {
-        obj->uart->IER |= 1 << irq;
-        NVIC_SetVector(irq_n, vector);
-        NVIC_EnableIRQ(irq_n);
-    } else { // disable
-        int all_disabled = 0;
-        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
-        obj->uart->IER &= ~(1 << irq);
-        all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
-        if (all_disabled)
-            NVIC_DisableIRQ(irq_n);
-    }
-}
-
-/******************************************************************************
- * READ/WRITE
- ******************************************************************************/
-int serial_getc(serial_t *obj) {
-    while (!serial_readable(obj));
-    return obj->uart->RBR;
-}
-
-void serial_putc(serial_t *obj, int c) {
-    while (!serial_writable(obj));
-    obj->uart->THR = c;
-    
-    uint32_t lsr = obj->uart->LSR;
-    lsr = lsr;
-    uint32_t thr = obj->uart->THR;
-    thr = thr;
-}
-
-int serial_readable(serial_t *obj) {
-    return obj->uart->LSR & 0x01;
-}
-
-int serial_writable(serial_t *obj) {
-    return obj->uart->LSR & 0x20;
-}
-
-void serial_clear(serial_t *obj) {
-    obj->uart->FCR = 1 << 1  // rx FIFO reset
-                   | 1 << 2  // tx FIFO reset
-                   | 0 << 6; // interrupt depth
-}
-
-void serial_pinout_tx(PinName tx) {
-    pinmap_pinout(tx, PinMap_UART_TX);
-}

--- a/vendor/NXP/LPC4088/hal/sleep.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,57 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "sleep_api.h"
-#include "cmsis.h"
-#include "mbed_interface.h"
-
-void sleep(void) {
-    LPC_SC->PCON = 0x0;
-    
-    // SRC[SLEEPDEEP] set to 0 = sleep
-    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
-    
-    // wait for interrupt
-    __WFI();
-}
-
-/*
-* The mbed lpc1768 does not support the deepsleep mode
-* as a debugger is connected to it (the mbed interface).
-*
-* As mentionned in an application note from NXP:
-*
-*       http://www.po-star.com/public/uploads/20120319123122_141.pdf
-*
-*       {{{
-*       The user should be aware of certain limitations during debugging.
-*       The most important is that, due to limitations of the Cortex-M3
-*       integration, the LPC17xx cannot wake up in the usual manner from
-*       Deep Sleep and Power-down modes. It is recommended not to use these
-*       modes during debug. Once an application is downloaded via JTAG/SWD
-*       interface, the USB to SWD/JTAG debug adapter (Keil ULINK2 for example)
-*       should be removed from the target board, and thereafter, power cycle
-*       the LPC17xx to allow wake-up from deep sleep and power-down modes
-*       }}}
-*
-*       As the interface firmware does not reset the target when a
-*       mbed_interface_disconnect() semihosting call is made, the
-*       core cannot wake-up from deepsleep.
-*
-*       We treat a deepsleep() as a normal sleep().
-*/
-void deepsleep(void) {
-    sleep();
-}

--- a/vendor/NXP/LPC4088/hal/spi_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,231 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <math.h>
-
-#include "spi_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const PinMap PinMap_SPI_SCLK[] = {
-    {P0_7 , SPI_1, 2},
-    {P0_15, SPI_0, 2},
-    {P1_0,  SPI_2, 4},
-    {P1_19, SPI_1, 5},
-    {P1_20, SPI_0, 5},
-    {P1_31, SPI_1, 2},
-    {P2_22, SPI_0, 2},
-    {P4_20, SPI_1, 3},
-    {P5_2,  SPI_2, 2},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_MOSI[] = {
-    {P0_9 , SPI_1, 2},
-    {P0_13, SPI_1, 2},
-    {P0_18, SPI_0, 2},
-    {P1_1,  SPI_2, 4},
-    {P1_22, SPI_1, 5},
-    {P1_24, SPI_0, 5},
-    {P2_27, SPI_0, 2},
-    {P4_23, SPI_1, 3},
-    {P5_0,  SPI_2, 2},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_MISO[] = {
-    {P0_8 , SPI_1, 2},
-    {P0_12, SPI_1, 2},
-    {P0_17, SPI_0, 2},
-    {P1_4,  SPI_2, 4},
-    {P1_18, SPI_1, 5},
-    {P1_23, SPI_0, 5},
-    {P2_26, SPI_0, 2},
-    {P4_22, SPI_1, 3},
-    {P5_1,  SPI_2, 2},
-    {NC   , NC   , 0}
-};
-
-static const PinMap PinMap_SPI_SSEL[] = {
-    {P0_6 , SPI_1, 2},
-    {P0_14, SPI_1, 2},
-    {P0_16, SPI_0, 2},
-    {P1_8,  SPI_2, 4},
-    {P1_21, SPI_0, 3},
-    {P1_26, SPI_1, 5},
-    {P1_28, SPI_0, 5},
-    {P2_23, SPI_0, 2},
-    {P4_21, SPI_1, 3},
-    {NC   , NC   , 0}
-};
-
-static inline int ssp_disable(spi_t *obj);
-static inline int ssp_enable(spi_t *obj);
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
-    // determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-    obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
-    if ((int)obj->spi == NC) {
-        error("SPI pinout mapping failed");
-    }
-    
-    // enable power and clocking
-    switch ((int)obj->spi) {
-        case SPI_0: LPC_SC->PCONP |= 1 << 21; break;
-        case SPI_1: LPC_SC->PCONP |= 1 << 10; break;
-        case SPI_2: LPC_SC->PCONP |= 1 << 20; break;
-    }
-    
-    // set default format and frequency
-    if (ssel == NC) {
-        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
-    } else {
-        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
-    }
-    spi_frequency(obj, 1000000);
-    
-    // enable the ssp channel
-    ssp_enable(obj);
-    
-    // pin out the spi pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    }
-}
-
-void spi_free(spi_t *obj) {}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
-    ssp_disable(obj);
-    
-    if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
-        error("SPI format error");
-    }
-    
-    int polarity = (mode & 0x2) ? 1 : 0;
-    int phase = (mode & 0x1) ? 1 : 0;
-    
-    // set it up
-    int DSS = bits - 1;            // DSS (data select size)
-    int SPO = (polarity) ? 1 : 0;  // SPO - clock out polarity
-    int SPH = (phase) ? 1 : 0;     // SPH - clock out phase
-    
-    int FRF = 0;                   // FRF (frame format) = SPI
-    uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
-    tmp |= DSS << 0
-        | FRF << 4
-        | SPO << 6
-        | SPH << 7;
-    obj->spi->CR0 = tmp;
-    
-    tmp = obj->spi->CR1;
-    tmp &= ~(0xD);
-    tmp |= 0 << 0                   // LBM - loop back mode - off
-        | ((slave) ? 1 : 0) << 2   // MS - master slave mode, 1 = slave
-        | 0 << 3;                  // SOD - slave output disable - na
-    obj->spi->CR1 = tmp;
-    ssp_enable(obj);
-}
-
-void spi_frequency(spi_t *obj, int hz) {
-    ssp_disable(obj);
-    
-    uint32_t PCLK = PeripheralClock;
-    
-    int prescaler;
-    
-    for (prescaler = 2; prescaler <= 254; prescaler += 2) {
-        int prescale_hz = PCLK / prescaler;
-        
-        // calculate the divider
-        int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
-        
-        // check we can support the divider
-        if (divider < 256) {
-            // prescaler
-            obj->spi->CPSR = prescaler;
-            
-            // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
-            obj->spi->CR0 |= (divider - 1) << 8;
-            ssp_enable(obj);
-            return;
-        }
-    }
-    error("Couldn't setup requested SPI frequency");
-}
-
-static inline int ssp_disable(spi_t *obj) {
-    return obj->spi->CR1 &= ~(1 << 1);
-}
-
-static inline int ssp_enable(spi_t *obj) {
-    return obj->spi->CR1 |= (1 << 1);
-}
-
-static inline int ssp_readable(spi_t *obj) {
-    return obj->spi->SR & (1 << 2);
-}
-
-static inline int ssp_writeable(spi_t *obj) {
-    return obj->spi->SR & (1 << 1);
-}
-
-static inline void ssp_write(spi_t *obj, int value) {
-    while (!ssp_writeable(obj));
-    obj->spi->DR = value;
-}
-
-static inline int ssp_read(spi_t *obj) {
-    while (!ssp_readable(obj));
-    return obj->spi->DR;
-}
-
-static inline int ssp_busy(spi_t *obj) {
-    return (obj->spi->SR & (1 << 4)) ? (1) : (0);
-}
-
-int spi_master_write(spi_t *obj, int value) {
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj) {
-    return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
-};
-
-int spi_slave_read(spi_t *obj) {
-    return obj->spi->DR;
-}
-
-void spi_slave_write(spi_t *obj, int value) {
-    while (ssp_writeable(obj) == 0) ;
-    obj->spi->DR = value;
-}
-
-int spi_busy(spi_t *obj) {
-    return ssp_busy(obj);
-}

--- a/vendor/NXP/LPC4088/hal/us_ticker.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,64 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stddef.h>
-#include "us_ticker_api.h"
-#include "PeripheralNames.h"
-
-#define US_TICKER_TIMER      ((LPC_TIM_TypeDef *)LPC_TIM3_BASE)
-#define US_TICKER_TIMER_IRQn TIMER3_IRQn
-
-int us_ticker_inited = 0;
-
-void us_ticker_init(void) {
-    if (us_ticker_inited) return;
-    us_ticker_inited = 1;
-    
-    LPC_SC->PCONP |= 1 << 23; // Clock TIMER_3
-    
-    US_TICKER_TIMER->CTCR = 0x0; // timer mode
-    uint32_t PCLK = PeripheralClock;
-    
-    US_TICKER_TIMER->TCR = 0x2;  // reset
-    
-    uint32_t prescale = PCLK / 1000000; // default to 1MHz (1 us ticks)
-    US_TICKER_TIMER->PR = prescale - 1;
-    US_TICKER_TIMER->TCR = 1; // enable = 1, reset = 0
-    
-    NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
-    NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
-}
-
-uint32_t us_ticker_read() {
-    if (!us_ticker_inited)
-        us_ticker_init();
-    
-    return US_TICKER_TIMER->TC;
-}
-
-void us_ticker_set_interrupt(unsigned int timestamp) {
-    // set match value
-    US_TICKER_TIMER->MR0 = timestamp;
-    // enable match interrupt
-    US_TICKER_TIMER->MCR |= 1;
-}
-
-void us_ticker_disable_interrupt(void) {
-    US_TICKER_TIMER->MCR &= ~1;
-}
-
-void us_ticker_clear_interrupt(void) {
-    US_TICKER_TIMER->IR = 1;
-}

--- a/vendor/NXP/LPC812/cmsis/LPC8xx.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,687 +0,0 @@
-/****************************************************************************
- *   $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694                     $
- *   Project: NXP LPC8xx software example
- *
- *   Description:
- *     CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
- *     NXP LPC800 Device Series
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors'
- * relevant copyright in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
-****************************************************************************/
-#ifndef __LPC8xx_H__
-#define __LPC8xx_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup LPC8xx_Definitions LPC8xx Definitions
-  This file defines all structures and symbols for LPC8xx:
-    - Registers and bitfields
-    - peripheral base address
-    - PIO definitions
-  @{
-*/
-
-
-/******************************************************************************/
-/*                Processor and Core Peripherals                              */
-/******************************************************************************/
-/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
-  Configuration of the Cortex-M0+ Processor and Core Peripherals
-  @{
-*/
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-typedef enum IRQn
-{
-/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
-  Reset_IRQn                    = -15,    /*!< 1 Reset Vector, invoked on Power up and warm reset*/
-  NonMaskableInt_IRQn           = -14,    /*!< 2 Non Maskable Interrupt                           */
-  HardFault_IRQn                = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                   */
-  SVCall_IRQn                   = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                     */
-  PendSV_IRQn                   = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                     */
-  SysTick_IRQn                  = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                 */
-
-/******  LPC8xx Specific Interrupt Numbers ********************************************************/
-  SPI0_IRQn                     = 0,        /*!< SPI0                                             */
-  SPI1_IRQn                     = 1,        /*!< SPI1                                             */
-  Reserved0_IRQn                = 2,        /*!< Reserved Interrupt                               */
-  UART0_IRQn                    = 3,        /*!< USART0                                            */
-  UART1_IRQn                    = 4,        /*!< USART1                                            */
-  UART2_IRQn                    = 5,        /*!< USART2                                            */
-  Reserved1_IRQn                = 6,        /*!< Reserved Interrupt                               */
-  Reserved2_IRQn                = 7,        /*!< Reserved Interrupt                               */
-  I2C_IRQn                      = 8,        /*!< I2C                                              */
-  SCT_IRQn                      = 9,        /*!< SCT                                              */
-  MRT_IRQn                      = 10,       /*!< MRT                                              */
-  CMP_IRQn                      = 11,       /*!< CMP                                              */
-  WDT_IRQn                      = 12,      /*!< WDT                                              */
-  BOD_IRQn                      = 13,       /*!< BOD                                              */
-  Reserved3_IRQn                = 14,       /*!< Reserved Interrupt                               */
-  WKT_IRQn                      = 15,       /*!< WKT Interrupt                                    */
-  Reserved4_IRQn                = 16,       /*!< Reserved Interrupt                               */
-  Reserved5_IRQn                = 17,       /*!< Reserved Interrupt                               */
-  Reserved6_IRQn                = 18,       /*!< Reserved Interrupt                               */
-  Reserved7_IRQn                = 19,       /*!< Reserved Interrupt                               */
-  Reserved8_IRQn                = 20,       /*!< Reserved Interrupt                               */
-  Reserved9_IRQn                = 21,       /*!< Reserved Interrupt                               */
-  Reserved10_IRQn               = 22,       /*!< Reserved Interrupt                               */
-  Reserved11_IRQn               = 23,       /*!< Reserved Interrupt                               */
-  PININT0_IRQn               	  = 24,       /*!< External Interrupt 0                             */
-  PININT1_IRQn                  = 25,       /*!< External Interrupt 1                             */
-  PININT2_IRQn                  = 26,       /*!< External Interrupt 2                             */
-  PININT3_IRQn                  = 27,       /*!< External Interrupt 3                             */
-  PININT4_IRQn                  = 28,       /*!< External Interrupt 4                             */
-  PININT5_IRQn                  = 29,       /*!< External Interrupt 5                             */
-  PININT6_IRQn                  = 30,       /*!< External Interrupt 6                             */
-  PININT7_IRQn                  = 31,       /*!< External Interrupt 7                             */
-} IRQn_Type;
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
-#define __MPU_PRESENT             0         /*!< MPU present or not                               */
-#define __VTOR_PRESENT            1         /**< Defines if an VTOR is present or not */
-#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-/*@}*/ /* end of group LPC8xx_CMSIS */
-
-
-#include "core_cm0plus.h"                  /* Cortex-M0+ processor and core peripherals          */
-#include "system_LPC8xx.h"                 /* System Header                                      */
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral Registers structures             */
-/******************************************************************************/
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#endif
-
-/*------------- System Control (SYSCON) --------------------------------------*/
-/** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t SYSMEMREMAP;            /*!< Offset: 0x000 System memory remap (R/W) */
-  __IO uint32_t PRESETCTRL;             /*!< Offset: 0x004 Peripheral reset control (R/W) */
-  __IO uint32_t SYSPLLCTRL;             /*!< Offset: 0x008 System PLL control (R/W) */
-  __IO uint32_t SYSPLLSTAT;             /*!< Offset: 0x00C System PLL status (R/W ) */
-       uint32_t RESERVED0[4];
-
-  __IO uint32_t SYSOSCCTRL;             /*!< Offset: 0x020 System oscillator control (R/W) */
-  __IO uint32_t WDTOSCCTRL;             /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
-       uint32_t RESERVED1[2];
-  __IO uint32_t SYSRSTSTAT;             /*!< Offset: 0x030 System reset status Register (R/W ) */
-       uint32_t RESERVED2[3];
-  __IO uint32_t SYSPLLCLKSEL;           /*!< Offset: 0x040 System PLL clock source select (R/W) */
-  __IO uint32_t SYSPLLCLKUEN;           /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
-       uint32_t RESERVED3[10];
-
-  __IO uint32_t MAINCLKSEL;             /*!< Offset: 0x070 Main clock source select (R/W) */
-  __IO uint32_t MAINCLKUEN;             /*!< Offset: 0x074 Main clock source update enable (R/W) */
-  __IO uint32_t SYSAHBCLKDIV;           /*!< Offset: 0x078 System AHB clock divider (R/W) */
-       uint32_t RESERVED4[1];
-
-  __IO uint32_t SYSAHBCLKCTRL;          /*!< Offset: 0x080 System AHB clock control (R/W) */
-       uint32_t RESERVED5[4];
-  __IO uint32_t UARTCLKDIV;             /*!< Offset: 0x094 UART clock divider (R/W) */
-       uint32_t RESERVED6[18];
-
-  __IO uint32_t CLKOUTSEL;              /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
-  __IO uint32_t CLKOUTUEN;              /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
-  __IO uint32_t CLKOUTDIV;              /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
-       uint32_t RESERVED7;
-  __IO uint32_t UARTFRGDIV;             /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
-  __IO uint32_t UARTFRGMULT;             /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
-       uint32_t RESERVED8[1];
-  __IO uint32_t EXTTRACECMD;            /*!< (@ 0x400480FC) External trace buffer command register  */
-  __IO uint32_t PIOPORCAP0;             /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
-       uint32_t RESERVED9[12];
-  __IO uint32_t IOCONCLKDIV[7];       /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
-  __IO uint32_t BODCTRL;                /*!< Offset: 0x150 BOD control (R/W) */
-  __IO uint32_t SYSTCKCAL;              /*!< Offset: 0x154 System tick counter calibration (R/W) */
-       uint32_t RESERVED10[6];
-  __IO uint32_t IRQLATENCY;             /*!< (@ 0x40048170) IRQ delay */
-  __IO uint32_t NMISRC;                 /*!< (@ 0x40048174) NMI Source Control     */
-  __IO uint32_t PINTSEL[8];             /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
-       uint32_t RESERVED11[27];
-  __IO uint32_t STARTERP0;              /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
-       uint32_t RESERVED12[3];
-  __IO uint32_t STARTERP1;              /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
-       uint32_t RESERVED13[6];
-  __IO uint32_t PDSLEEPCFG;             /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
-  __IO uint32_t PDAWAKECFG;             /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
-  __IO uint32_t PDRUNCFG;               /*!< Offset: 0x238 Power-down configuration Register (R/W) */
-       uint32_t RESERVED14[110];
-  __I  uint32_t DEVICE_ID;              /*!< Offset: 0x3F4 Device ID (R/ ) */
-} LPC_SYSCON_TypeDef;
-/*@}*/ /* end of group LPC8xx_SYSCON */
-
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3  (IOCONFIG)
-  */
-
-typedef struct {                            /*!< (@ 0x40044000) IOCONFIG Structure     */
-  __IO uint32_t PIO0_17;                    /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
-  __IO uint32_t PIO0_13;                    /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
-  __IO uint32_t PIO0_12;                    /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
-  __IO uint32_t PIO0_5;                     /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
-  __IO uint32_t PIO0_4;                     /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
-  __IO uint32_t PIO0_3;                     /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
-  __IO uint32_t PIO0_2;                     /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
-  __IO uint32_t PIO0_11;                    /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
-  __IO uint32_t PIO0_10;                    /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
-  __IO uint32_t PIO0_16;                    /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
-  __IO uint32_t PIO0_15;                    /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
-  __IO uint32_t PIO0_1;                     /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
-  __IO uint32_t Reserved;                   /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
-  __IO uint32_t PIO0_9;                     /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
-  __IO uint32_t PIO0_8;                     /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
-  __IO uint32_t PIO0_7;                     /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
-  __IO uint32_t PIO0_6;                     /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
-  __IO uint32_t PIO0_0;                     /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
-  __IO uint32_t PIO0_14;                    /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
-} LPC_IOCON_TypeDef;
-/*@}*/ /* end of group LPC8xx_IOCON */
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3  (FLASHCTRL)
-  */
-typedef struct {                            /*!< (@ 0x40040000) FLASHCTRL Structure    */
-  __I  uint32_t  RESERVED0[4];
-  __IO uint32_t  FLASHCFG;                          /*!< (@ 0x40040010) Flash configuration register                           */
-  __I  uint32_t  RESERVED1[3];
-  __IO uint32_t  FMSSTART;                          /*!< (@ 0x40040020) Signature start address register                       */
-  __IO uint32_t  FMSSTOP;                           /*!< (@ 0x40040024) Signature stop-address register                        */
-  __I  uint32_t  RESERVED2;
-  __I  uint32_t  FMSW0;
-} LPC_FLASHCTRL_TypeDef;
-/*@}*/ /* end of group LPC8xx_FLASHCTRL */
-
-
-/*------------- Power Management Unit (PMU) --------------------------*/
-/** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t PCON;                   /*!< Offset: 0x000 Power control Register (R/W) */
-  __IO uint32_t GPREG0;                 /*!< Offset: 0x004 General purpose Register 0 (R/W) */
-  __IO uint32_t GPREG1;                 /*!< Offset: 0x008 General purpose Register 1 (R/W) */
-  __IO uint32_t GPREG2;                 /*!< Offset: 0x00C General purpose Register 2 (R/W) */
-  __IO uint32_t GPREG3;                 /*!< Offset: 0x010 General purpose Register 3 (R/W) */
-  __IO uint32_t DPDCTRL;                /*!< Offset: 0x014 Deep power-down control register (R/W) */
-} LPC_PMU_TypeDef;
-/*@}*/ /* end of group LPC8xx_PMU */
-
-
-/*------------- Switch Matrix Port --------------------------*/
-/** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
-  @{
-*/
-typedef struct
-{
-  union {
-    __IO uint32_t PINASSIGN[9];
-    struct {
-      __IO uint32_t PINASSIGN0;
-      __IO uint32_t PINASSIGN1;
-      __IO uint32_t PINASSIGN2;
-      __IO uint32_t PINASSIGN3;
-      __IO uint32_t PINASSIGN4;
-      __IO uint32_t PINASSIGN5;
-      __IO uint32_t PINASSIGN6;
-      __IO uint32_t PINASSIGN7;
-      __IO uint32_t PINASSIGN8;
-    };
-  };
-  __I  uint32_t  RESERVED0[103];
-  __IO uint32_t  PINENABLE0;
-} LPC_SWM_TypeDef;
-/*@}*/ /* end of group LPC8xx_SWM */
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                       GPIO_PORT                                      -----
-// ------------------------------------------------------------------------------------------------
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (GPIO_PORT)
-  */
-
-typedef struct {
-  __IO uint8_t B0[18];                   /*!< (@ 0xA0000000) Byte pin registers port 0 */
-  __I  uint16_t RESERVED0[2039];
-  __IO uint32_t W0[18];                  /*!< (@ 0xA0001000) Word pin registers port 0 */
-       uint32_t RESERVED1[1006];
-  __IO uint32_t DIR0;                          /* 0x2000 */
-       uint32_t RESERVED2[31];
-  __IO uint32_t MASK0;                                  /* 0x2080 */
-       uint32_t RESERVED3[31];
-  __IO uint32_t PIN0;                          /* 0x2100 */
-       uint32_t RESERVED4[31];
-  __IO uint32_t MPIN0;                                   /* 0x2180 */
-       uint32_t RESERVED5[31];
-  __IO uint32_t SET0;                         /* 0x2200 */
-       uint32_t RESERVED6[31];
-  __O  uint32_t CLR0;                         /* 0x2280 */
-       uint32_t RESERVED7[31];
-  __O  uint32_t NOT0;                                    /* 0x2300 */
-
-} LPC_GPIO_PORT_TypeDef;
-
-
-// ------------------------------------------------------------------------------------------------
-// -----                                     PIN_INT                                     -----
-// ------------------------------------------------------------------------------------------------
-
-/**
-  * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3  (PIN_INT)
-  */
-
-typedef struct {                            /*!< (@ 0xA0004000) PIN_INT Structure */
-  __IO uint32_t ISEL;                       /*!< (@ 0xA0004000) Pin Interrupt Mode register */
-  __IO uint32_t IENR;                       /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
-  __IO uint32_t SIENR;                      /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
-  __IO uint32_t CIENR;                      /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
-  __IO uint32_t IENF;                       /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
-  __IO uint32_t SIENF;                      /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
-  __IO uint32_t CIENF;                      /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
-  __IO uint32_t RISE;                       /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
-  __IO uint32_t FALL;                       /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
-  __IO uint32_t IST;                        /*!< (@ 0xA0004024) Pin Interrupt Status register */
-  __IO uint32_t PMCTRL;                     /*!< (@ 0xA0004028) GPIO pattern match interrupt control register          */
-  __IO uint32_t PMSRC;                      /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
-  __IO uint32_t PMCFG;                      /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
-} LPC_PIN_INT_TypeDef;
-
-
-/*------------- CRC Engine (CRC) -----------------------------------------*/
-/** @addtogroup LPC8xx_CRC
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t MODE;
-  __IO uint32_t SEED;
-  union {
-  __I  uint32_t SUM;
-  __O  uint32_t WR_DATA_DWORD;
-  __O  uint16_t WR_DATA_WORD;
-       uint16_t RESERVED_WORD;
-  __O  uint8_t WR_DATA_BYTE;
-       uint8_t RESERVED_BYTE[3];
-  };
-} LPC_CRC_TypeDef;
-/*@}*/ /* end of group LPC8xx_CRC */
-
-/*------------- Comparator (CMP) --------------------------------------------------*/
-/** @addtogroup LPC8xx_CMP LPC8xx Comparator
-  @{
-*/
-typedef struct {                            /*!< (@ 0x40024000) CMP Structure          */
-  __IO uint32_t  CTRL;                      /*!< (@ 0x40024000) Comparator control register */
-  __IO uint32_t  LAD;                       /*!< (@ 0x40024004) Voltage ladder register */
-} LPC_CMP_TypeDef;
-/*@}*/ /* end of group LPC8xx_CMP */
-
-
-/*------------- Wakeup Timer (WKT) --------------------------------------------------*/
-/** @addtogroup LPC8xx_WKT
-  @{
-*/
-typedef struct {                            /*!< (@ 0x40028000) WKT Structure          */
-  __IO uint32_t  CTRL;                      /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
-       uint32_t  Reserved[2];
-  __IO uint32_t  COUNT;                     /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
-} LPC_WKT_TypeDef;
-/*@}*/ /* end of group LPC8xx_WKT */
-
-
-/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
-typedef struct {
-__IO uint32_t INTVAL;
-__IO uint32_t TIMER;
-__IO uint32_t CTRL;
-__IO uint32_t STAT;
-} MRT_Channel_cfg_Type;
-
-typedef struct {
-  MRT_Channel_cfg_Type Channel[4];
-   uint32_t Reserved0[1];
-  __IO uint32_t IDLE_CH;
-  __IO uint32_t IRQ_FLAG;
-} LPC_MRT_TypeDef;
-
-
-/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
-/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
-  @{
-*/
-/**
-  * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9  (USART)
-  */
-typedef struct
-{
-  __IO uint32_t  CFG;								/* 0x00 */
-  __IO uint32_t  CTRL;
-  __IO uint32_t  STAT;
-  __IO uint32_t  INTENSET;
-  __O  uint32_t  INTENCLR;					/* 0x10 */
-  __I  uint32_t  RXDATA;
-  __I  uint32_t  RXDATA_STAT;
-  __IO uint32_t  TXDATA;
-  __IO uint32_t  BRG;								/* 0x20 */
-  __IO uint32_t  INTSTAT;
-} LPC_USART_TypeDef;
-
-/*@}*/ /* end of group LPC8xx_USART */
-
-
-/*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
-/** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t  CFG;			    /* 0x00 */
-  __IO uint32_t  DLY;
-  __IO uint32_t  STAT;
-  __IO uint32_t  INTENSET;
-  __O  uint32_t  INTENCLR;		/* 0x10 */
-  __I  uint32_t  RXDAT;
-  __IO uint32_t  TXDATCTL;
-  __IO uint32_t  TXDAT;
-  __IO uint32_t  TXCTRL;		  /* 0x20 */
-  __IO uint32_t  DIV;
-  __I  uint32_t  INTSTAT;
-} LPC_SPI_TypeDef;
-/*@}*/ /* end of group LPC8xx_SPI */
-
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-/** @addtogroup LPC8xx_I2C I2C-Bus Interface
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t  CFG;			  /* 0x00 */
-  __IO uint32_t  STAT;
-  __IO uint32_t  INTENSET;
-  __O  uint32_t  INTENCLR;
-  __IO uint32_t  TIMEOUT;		/* 0x10 */
-  __IO uint32_t  DIV;
-  __IO uint32_t  INTSTAT;
-       uint32_t  Reserved0[1];
-  __IO uint32_t  MSTCTL;			  /* 0x20 */
-  __IO uint32_t  MSTTIME;
-  __IO uint32_t  MSTDAT;
-       uint32_t  Reserved1[5];
-  __IO uint32_t  SLVCTL;			  /* 0x40 */
-  __IO uint32_t  SLVDAT;
-  __IO uint32_t  SLVADR0;
-  __IO uint32_t  SLVADR1;
-  __IO uint32_t  SLVADR2;			  /* 0x50 */
-  __IO uint32_t  SLVADR3;
-  __IO uint32_t  SLVQUAL0;
-       uint32_t  Reserved2[9];
-  __I  uint32_t  MONRXDAT;			/* 0x80 */
-} LPC_I2C_TypeDef;
-
-/*@}*/ /* end of group LPC8xx_I2C */
-
-/**
-  * @brief State Configurable Timer (SCT) (SCT)
-  */
-
-/**
-  * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7  (SCT)
-  */
-
-#define CONFIG_SCT_nEV   (6)             /* Number of events */
-#define CONFIG_SCT_nRG   (5)             /* Number of match/compare registers */
-#define CONFIG_SCT_nOU   (4)             /* Number of outputs */
-
-typedef struct
-{
-    __IO  uint32_t CONFIG;              /* 0x000 Configuration Register */
-    union {
-        __IO uint32_t CTRL_U;           /* 0x004 Control Register */
-        struct {
-            __IO uint16_t CTRL_L;       /* 0x004 low control register */
-            __IO uint16_t CTRL_H;       /* 0x006 high control register */
-        };
-    };
-    __IO uint16_t LIMIT_L;              /* 0x008 limit register for counter L */
-    __IO uint16_t LIMIT_H;              /* 0x00A limit register for counter H */
-    __IO uint16_t HALT_L;               /* 0x00C halt register for counter L */
-    __IO uint16_t HALT_H;               /* 0x00E halt register for counter H */
-    __IO uint16_t STOP_L;               /* 0x010 stop register for counter L */
-    __IO uint16_t STOP_H;               /* 0x012 stop register for counter H */
-    __IO uint16_t START_L;              /* 0x014 start register for counter L */
-    __IO uint16_t START_H;              /* 0x016 start register for counter H */
-         uint32_t RESERVED1[10];        /* 0x018-0x03C reserved */
-    union {
-        __IO uint32_t COUNT_U;          /* 0x040 counter register */
-        struct {
-            __IO uint16_t COUNT_L;      /* 0x040 counter register for counter L */
-            __IO uint16_t COUNT_H;      /* 0x042 counter register for counter H */
-        };
-    };
-    __IO uint16_t STATE_L;              /* 0x044 state register for counter L */
-    __IO uint16_t STATE_H;              /* 0x046 state register for counter H */
-    __I  uint32_t INPUT;                /* 0x048 input register */
-    __IO uint16_t REGMODE_L;            /* 0x04C match - capture registers mode register L */
-    __IO uint16_t REGMODE_H;            /* 0x04E match - capture registers mode register H */
-    __IO uint32_t OUTPUT;               /* 0x050 output register */
-    __IO uint32_t OUTPUTDIRCTRL;        /* 0x054 Output counter direction Control Register */
-    __IO uint32_t RES;                  /* 0x058 conflict resolution register */
-         uint32_t RESERVED2[37];        /* 0x05C-0x0EC reserved */
-    __IO uint32_t EVEN;                 /* 0x0F0 event enable register */
-    __IO uint32_t EVFLAG;               /* 0x0F4 event flag register */
-    __IO uint32_t CONEN;                /* 0x0F8 conflict enable register */
-    __IO uint32_t CONFLAG;              /* 0x0FC conflict flag register */
-
-    union {
-        __IO union {                    /* 0x100-... Match / Capture value */
-            uint32_t U;                 /*       SCTMATCH[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTMATCH[i].L  Access to L value */
-                uint16_t H;             /*       SCTMATCH[i].H  Access to H value */
-            };
-        } MATCH[CONFIG_SCT_nRG];
-        __I union {
-            uint32_t U;                 /*       SCTCAP[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTCAP[i].L  Access to H value */
-                uint16_t H;             /*       SCTCAP[i].H  Access to H value */
-            };
-        } CAP[CONFIG_SCT_nRG];
-    };
-
-
-         uint32_t RESERVED3[32-CONFIG_SCT_nRG];      /* ...-0x17C reserved */
-
-    union {
-        __IO uint16_t MATCH_L[CONFIG_SCT_nRG];       /* 0x180-... Match Value L counter */
-        __I  uint16_t CAP_L[CONFIG_SCT_nRG];         /* 0x180-... Capture Value L counter */
-    };
-         uint16_t RESERVED4[32-CONFIG_SCT_nRG];      /* ...-0x1BE reserved */
-    union {
-        __IO uint16_t MATCH_H[CONFIG_SCT_nRG];       /* 0x1C0-... Match Value H counter */
-        __I  uint16_t CAP_H[CONFIG_SCT_nRG];         /* 0x1C0-... Capture Value H counter */
-    };
-
-         uint16_t RESERVED5[32-CONFIG_SCT_nRG];      /* ...-0x1FE reserved */
-
-
-    union {
-        __IO union {                    /* 0x200-... Match Reload / Capture Control value */
-            uint32_t U;                 /*       SCTMATCHREL[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTMATCHREL[i].L  Access to L value */
-                uint16_t H;             /*       SCTMATCHREL[i].H  Access to H value */
-            };
-        } MATCHREL[CONFIG_SCT_nRG];
-        __IO union {
-            uint32_t U;                 /*       SCTCAPCTRL[i].U  Unified 32-bit register */
-            struct {
-                uint16_t L;             /*       SCTCAPCTRL[i].L  Access to H value */
-                uint16_t H;             /*       SCTCAPCTRL[i].H  Access to H value */
-            };
-        } CAPCTRL[CONFIG_SCT_nRG];
-    };
-
-         uint32_t RESERVED6[32-CONFIG_SCT_nRG];      /* ...-0x27C reserved */
-
-    union {
-        __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG];    /* 0x280-... Match Reload value L counter */
-        __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG];     /* 0x280-... Capture Control value L counter */
-    };
-         uint16_t RESERVED7[32-CONFIG_SCT_nRG];      /* ...-0x2BE reserved */
-    union {
-        __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG];    /* 0x2C0-... Match Reload value H counter */
-        __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG];     /* 0x2C0-... Capture Control value H counter */
-    };
-         uint16_t RESERVED8[32-CONFIG_SCT_nRG];      /* ...-0x2FE reserved */
-
-    __IO struct {                       /* 0x300-0x3FC  SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
-        uint32_t STATE;                 /* Event State Register */
-        uint32_t CTRL;                  /* Event Control Register */
-    } EVENT[CONFIG_SCT_nEV];
-
-         uint32_t RESERVED9[128-2*CONFIG_SCT_nEV];   /* ...-0x4FC reserved */
-
-    __IO struct {                       /* 0x500-0x57C  SCTOUT[i].SET / SCTOUT[i].CLR */
-        uint32_t SET;                   /* Output n Set Register */
-        uint32_t CLR;                   /* Output n Clear Register */
-    } OUT[CONFIG_SCT_nOU];
-
-         uint32_t RESERVED10[191-2*CONFIG_SCT_nOU];  /* ...-0x7F8 reserved */
-
-    __I  uint32_t MODULECONTENT;        /* 0x7FC Module Content */
-
-} LPC_SCT_TypeDef;
-/*@}*/ /* end of group LPC8xx_SCT */
-
-
-/*------------- Watchdog Timer (WWDT) -----------------------------------------*/
-/** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
-  @{
-*/
-typedef struct
-{
-  __IO uint32_t MOD;                    /*!< Offset: 0x000 Watchdog mode register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
-  __O  uint32_t FEED;                   /*!< Offset: 0x008 Watchdog feed sequence register (W) */
-  __I  uint32_t TV;                     /*!< Offset: 0x00C Watchdog timer value register (R) */
-       uint32_t RESERVED;               /*!< Offset: 0x010 RESERVED                          */
-  __IO uint32_t WARNINT;                /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
-  __IO uint32_t WINDOW;                 /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
-} LPC_WWDT_TypeDef;
-/*@}*/ /* end of group LPC8xx_WDT */
-
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#endif
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-#define LPC_FLASH_BASE        (0x00000000UL)
-#define LPC_RAM_BASE          (0x10000000UL)
-#define LPC_ROM_BASE          (0x1FFF0000UL)
-#define LPC_APB0_BASE         (0x40000000UL)
-#define LPC_AHB_BASE          (0x50000000UL)
-
-/* APB0 peripherals */
-#define LPC_WWDT_BASE         (LPC_APB0_BASE + 0x00000)
-#define LPC_MRT_BASE          (LPC_APB0_BASE + 0x04000)
-#define LPC_WKT_BASE          (LPC_APB0_BASE + 0x08000)
-#define LPC_SWM_BASE          (LPC_APB0_BASE + 0x0C000)
-#define LPC_PMU_BASE          (LPC_APB0_BASE + 0x20000)
-#define LPC_CMP_BASE          (LPC_APB0_BASE + 0x24000)
-
-#define LPC_FLASHCTRL_BASE    (LPC_APB0_BASE + 0x40000)
-#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x44000)
-#define LPC_SYSCON_BASE       (LPC_APB0_BASE + 0x48000)
-#define LPC_I2C_BASE          (LPC_APB0_BASE + 0x50000)
-#define LPC_SPI0_BASE         (LPC_APB0_BASE + 0x58000)
-#define LPC_SPI1_BASE         (LPC_APB0_BASE + 0x5C000)
-#define LPC_USART0_BASE       (LPC_APB0_BASE + 0x64000)
-#define LPC_USART1_BASE       (LPC_APB0_BASE + 0x68000)
-#define LPC_USART2_BASE       (LPC_APB0_BASE + 0x6C000)
-
-/* AHB peripherals                                                            */
-#define LPC_CRC_BASE         (LPC_AHB_BASE + 0x00000)
-#define LPC_SCT_BASE         (LPC_AHB_BASE + 0x04000)
-
-#define LPC_GPIO_PORT_BASE    (0xA0000000)
-#define LPC_PIN_INT_BASE     (LPC_GPIO_PORT_BASE  + 0x4000)
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_WWDT              ((LPC_WWDT_TypeDef   *) LPC_WWDT_BASE  )
-#define LPC_MRT               ((LPC_MRT_TypeDef    *) LPC_MRT_BASE   )
-
-
-#define LPC_WKT               ((LPC_WKT_TypeDef    *) LPC_WKT_BASE   )
-#define LPC_SWM               ((LPC_SWM_TypeDef    *) LPC_SWM_BASE   )
-#define LPC_PMU               ((LPC_PMU_TypeDef    *) LPC_PMU_BASE   )
-#define LPC_CMP               ((LPC_CMP_TypeDef    *) LPC_CMP_BASE   )
-
-#define LPC_FLASHCTRL         ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
-#define LPC_IOCON             ((LPC_IOCON_TypeDef  *) LPC_IOCON_BASE )
-#define LPC_SYSCON            ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
-#define LPC_I2C               ((LPC_I2C_TypeDef    *) LPC_I2C_BASE   )
-#define LPC_SPI0              ((LPC_SPI_TypeDef    *) LPC_SPI0_BASE  )
-#define LPC_SPI1              ((LPC_SPI_TypeDef    *) LPC_SPI1_BASE  )
-#define LPC_USART0            ((LPC_USART_TypeDef   *) LPC_USART0_BASE )
-#define LPC_USART1            ((LPC_USART_TypeDef   *) LPC_USART1_BASE )
-#define LPC_USART2            ((LPC_USART_TypeDef   *) LPC_USART2_BASE )
-
-#define LPC_CRC               ((LPC_CRC_TypeDef    *) LPC_CRC_BASE   )
-#define LPC_SCT               ((LPC_SCT_TypeDef    *) LPC_SCT_BASE   )
-
-#define LPC_GPIO_PORT         ((LPC_GPIO_PORT_TypeDef  *) LPC_GPIO_PORT_BASE  )
-#define LPC_PIN_INT          ((LPC_PIN_INT_TypeDef   *) LPC_PIN_INT_BASE  )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* __LPC8xx_H__ */

--- a/vendor/NXP/LPC812/cmsis/cmsis.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,13 +0,0 @@
-/* mbed Microcontroller Library - CMSIS
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * A generic CMSIS include header, pulling in LPC8xx specifics
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "LPC8xx.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/vendor/NXP/LPC812/cmsis/cmsis_nvic.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
- * Copyright (c) 2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-#include "cmsis_nvic.h"
-
-#define NVIC_NUM_VECTORS (16 + 32)            // CORE + MCU Peripherals
-#define NVIC_RAM_VECTOR_ADDRESS (0x10000000)  // Vectors positioned at start of RAM
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-    static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
-    int i;
-    
-    // Copy and switch to dynamic vectors if first time called
-    if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
-        uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
-        for (i=0; i<NVIC_NUM_VECTORS; i++) {
-            vectors[i] = old_vectors[i];
-        }
-        SCB->VTOR = (uint32_t)vectors;
-    }
-    
-    vectors[IRQn + 16] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t *vectors = (uint32_t*)SCB->VTOR;
-    return vectors[IRQn + 16];
-}

--- a/vendor/NXP/LPC812/cmsis/cmsis_nvic.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,23 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */ 
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC812/cmsis/core_cm0.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,279 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.c
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Source File
- * @version  V2.00
- * @date     10. September 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-
-/* ##########################  Core Instruction Access  ######################### */
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __CLREX(void)
-{
-  clrex
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_CONTROL(void)
-{
-  mrs r0, control
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_CONTROL(uint32_t control)
-{
-  msr control, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_IPSR(void)
-{
-  mrs r0, ipsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_APSR(void)
-{
-  mrs r0, apsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_xPSR(void)
-{
-  mrs r0, xpsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_PSP(void)
-{
-  mrs r0, psp
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
-  msr psp, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_MSP(void)
-{
-  mrs r0, msp
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
-  msr msp, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_PRIMASK(void)
-{
-  mrs r0, primask
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
-  msr primask, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */ 
- 
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif

--- a/vendor/NXP/LPC812/cmsis/core_cm0plus.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,778 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0plus.h
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V3.02
- * @date     05. November 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex-M0+
-  @{
- */
-
-/*  CMSIS CM0P definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
-#define __CM0PLUS_CMSIS_VERSION_SUB  (0x01)                                /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
-                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0PLUS_REV
-    #define __CM0PLUS_REV             0x0000
-    #warning "__CM0PLUS_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-#if (__VTOR_PRESENT == 1)
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-#else
-       uint32_t RESERVED0;
-#endif
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if (__VTOR_PRESENT == 1)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0+ Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
-
-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

--- a/vendor/NXP/LPC812/cmsis/core_cmFunc.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,616 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V3.02
- * @date     24. May 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */

--- a/vendor/NXP/LPC812/cmsis/core_cmInstr.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,643 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V3.03
- * @date     29. August 2012
- *
- * @note
- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-#define __ISB()                           __isb(0xF)
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()                           __dsb(0xF)
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB()                           __dmb(0xF)
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __RBIT                            __rbit
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-
-  __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
-  return(op1);
-}
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint8_t result;
-
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint16_t result;
-
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
-  uint8_t result;
-
-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

--- a/vendor/NXP/LPC812/cmsis/system_LPC8xx.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,367 +0,0 @@
-/******************************************************************************
- * @file:    system_LPC8xx.c
- * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
- *           for the NXP LPC8xx Device Series
- * @version: V1.0
- * @date:    16. Aug. 2012
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2012 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#include <stdint.h>
-#include "LPC8xx.h"
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-
-/*--------------------- Clock Configuration ----------------------------------
-//
-// <e> Clock Configuration
-//   <h> System Oscillator Control Register (SYSOSCCTRL)
-//     <o1.0>      BYPASS: System Oscillator Bypass Enable
-//                     <i> If enabled then PLL input (sys_osc_clk) is fed
-//                     <i> directly from XTALIN and XTALOUT pins.
-//     <o1.9>      FREQRANGE: System Oscillator Frequency Range
-//                     <i> Determines frequency range for Low-power oscillator.
-//                   <0=> 1 - 20 MHz
-//                   <1=> 15 - 25 MHz
-//   </h>
-//
-//   <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
-//     <o2.0..4>   DIVSEL: Select Divider for Fclkana
-//                     <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
-//                   <0-31>
-//     <o2.5..8>   FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
-//                   <0=> Undefined
-//                   <1=> 0.5 MHz
-//                   <2=> 0.8 MHz
-//                   <3=> 1.1 MHz
-//                   <4=> 1.4 MHz
-//                   <5=> 1.6 MHz
-//                   <6=> 1.8 MHz
-//                   <7=> 2.0 MHz
-//                   <8=> 2.2 MHz
-//                   <9=> 2.4 MHz
-//                   <10=> 2.6 MHz
-//                   <11=> 2.7 MHz
-//                   <12=> 2.9 MHz
-//                   <13=> 3.1 MHz
-//                   <14=> 3.2 MHz
-//                   <15=> 3.4 MHz
-//   </h>
-//
-//   <h> System PLL Control Register (SYSPLLCTRL)
-//                   <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
-//                   <i> F_clkin must be in the range of  10 MHz to  25 MHz
-//                   <i> F_CCO   must be in the range of 156 MHz to 320 MHz
-//     <o3.0..4>   MSEL: Feedback Divider Selection
-//                     <i> M = MSEL + 1
-//                   <0-31>
-//     <o3.5..6>   PSEL: Post Divider Selection
-//                   <0=> P = 1
-//                   <1=> P = 2
-//                   <2=> P = 4
-//                   <3=> P = 8
-//   </h>
-//
-//   <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
-//     <o4.0..1>   SEL: System PLL Clock Source
-//                   <0=> IRC Oscillator
-//                   <1=> System Oscillator
-//                   <2=> Reserved
-//                   <3=> CLKIN pin
-//   </h>
-//
-//   <h> Main Clock Source Select Register (MAINCLKSEL)
-//     <o5.0..1>   SEL: Clock Source for Main Clock
-//                   <0=> IRC Oscillator
-//                   <1=> Input Clock to System PLL
-//                   <2=> WDT Oscillator
-//                   <3=> System PLL Clock Out
-//   </h>
-//
-//   <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
-//     <o6.0..7>   DIV: System AHB Clock Divider
-//                     <i> Divides main clock to provide system clock to core, memories, and peripherals.
-//                     <i> 0 = is disabled
-//                   <0-255>
-//   </h>
-// </e>
-*/
-#define CLOCK_SETUP           1
-#define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
-#define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
-#define SYSPLLCTRL_Val        0x00000041              // Reset: 0x000
-#define SYSPLLCLKSEL_Val      0x00000000              // Reset: 0x000
-#define MAINCLKSEL_Val        0x00000000              // Reset: 0x000
-#define SYSAHBCLKDIV_Val      0x00000001              // Reset: 0x001
-
-/*
-//-------- <<< end of configuration section >>> ------------------------------
-*/
-
-/*----------------------------------------------------------------------------
-  Check the register settings
- *----------------------------------------------------------------------------*/
-#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
-#define CHECK_RSVD(val, mask)                     (val & mask)
-
-/* Clock Configuration -------------------------------------------------------*/
-#if (CHECK_RSVD((SYSOSCCTRL_Val),  ~0x00000003))
-   #error "SYSOSCCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((WDTOSCCTRL_Val),  ~0x000001FF))
-   #error "WDTOSCCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
-   #error "SYSPLLCLKSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((SYSPLLCTRL_Val),  ~0x000001FF))
-   #error "SYSPLLCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((MAINCLKSEL_Val),  ~0x00000003))
-   #error "MAINCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
-   #error "SYSAHBCLKDIV: Value out of range!"
-#endif
-
-
-/*----------------------------------------------------------------------------
-  DEFINES
- *----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define __XTAL            (12000000UL)    /* Oscillator frequency             */
-#define __SYS_OSC_CLK     (    __XTAL)    /* Main oscillator frequency        */
-#define __IRC_OSC_CLK     (12000000UL)    /* Internal RC oscillator frequency */
-#define __CLKIN_CLK       (12000000UL)    /* CLKIN pin frequency              */
-
-
-#define __FREQSEL   ((WDTOSCCTRL_Val >> 5) & 0x0F)
-#define __DIVSEL   (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
-
-#if (CLOCK_SETUP)                         /* Clock Setup              */
-  #if  (__FREQSEL ==  0)
-    #define __WDT_OSC_CLK        ( 0)                  /* undefined */
-  #elif (__FREQSEL ==  1)
-    #define __WDT_OSC_CLK        ( 500000 / __DIVSEL)
-  #elif (__FREQSEL ==  2)
-    #define __WDT_OSC_CLK        ( 800000 / __DIVSEL)
-  #elif (__FREQSEL ==  3)
-    #define __WDT_OSC_CLK        (1100000 / __DIVSEL)
-  #elif (__FREQSEL ==  4)
-    #define __WDT_OSC_CLK        (1400000 / __DIVSEL)
-  #elif (__FREQSEL ==  5)
-    #define __WDT_OSC_CLK        (1600000 / __DIVSEL)
-  #elif (__FREQSEL ==  6)
-    #define __WDT_OSC_CLK        (1800000 / __DIVSEL)
-  #elif (__FREQSEL ==  7)
-    #define __WDT_OSC_CLK        (2000000 / __DIVSEL)
-  #elif (__FREQSEL ==  8)
-    #define __WDT_OSC_CLK        (2200000 / __DIVSEL)
-  #elif (__FREQSEL ==  9)
-    #define __WDT_OSC_CLK        (2400000 / __DIVSEL)
-  #elif (__FREQSEL == 10)
-    #define __WDT_OSC_CLK        (2600000 / __DIVSEL)
-  #elif (__FREQSEL == 11)
-    #define __WDT_OSC_CLK        (2700000 / __DIVSEL)
-  #elif (__FREQSEL == 12)
-    #define __WDT_OSC_CLK        (2900000 / __DIVSEL)
-  #elif (__FREQSEL == 13)
-    #define __WDT_OSC_CLK        (3100000 / __DIVSEL)
-  #elif (__FREQSEL == 14)
-    #define __WDT_OSC_CLK        (3200000 / __DIVSEL)
-  #else
-    #define __WDT_OSC_CLK        (3400000 / __DIVSEL)
-  #endif
-
-  /* sys_pllclkin calculation */
-  #if   ((SYSPLLCLKSEL_Val & 0x03) == 0)
-    #define __SYS_PLLCLKIN           (__IRC_OSC_CLK)
-  #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
-    #define __SYS_PLLCLKIN           (__SYS_OSC_CLK)
-  #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
-    #define __SYS_PLLCLKIN           (__CLKIN_CLK)
-  #else
-    #define __SYS_PLLCLKIN           (0)
-  #endif
-
-  #define  __SYS_PLLCLKOUT         (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
-
-  /* main clock calculation */
-  #if   ((MAINCLKSEL_Val & 0x03) == 0)
-    #define __MAIN_CLOCK             (__IRC_OSC_CLK)
-  #elif ((MAINCLKSEL_Val & 0x03) == 1)
-    #define __MAIN_CLOCK             (__SYS_PLLCLKIN)
-  #elif ((MAINCLKSEL_Val & 0x03) == 2)
-    #if (__FREQSEL ==  0)
-      #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
-    #else
-      #define __MAIN_CLOCK           (__WDT_OSC_CLK)
-    #endif
-  #elif ((MAINCLKSEL_Val & 0x03) == 3)
-    #define __MAIN_CLOCK             (__SYS_PLLCLKOUT)
-  #else
-    #define __MAIN_CLOCK             (0)
-  #endif
-
-  #define __SYSTEM_CLOCK             (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
-
-#else
-  #define __SYSTEM_CLOCK             (__IRC_OSC_CLK)
-#endif  // CLOCK_SETUP
-
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
-
-
-/*----------------------------------------------------------------------------
-  Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
-{
-  uint32_t wdt_osc = 0;
-
-  /* Determine clock frequency according to clock register values             */
-  switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
-    case 0:  wdt_osc =       0; break;
-    case 1:  wdt_osc =  500000; break;
-    case 2:  wdt_osc =  800000; break;
-    case 3:  wdt_osc = 1100000; break;
-    case 4:  wdt_osc = 1400000; break;
-    case 5:  wdt_osc = 1600000; break;
-    case 6:  wdt_osc = 1800000; break;
-    case 7:  wdt_osc = 2000000; break;
-    case 8:  wdt_osc = 2200000; break;
-    case 9:  wdt_osc = 2400000; break;
-    case 10: wdt_osc = 2600000; break;
-    case 11: wdt_osc = 2700000; break;
-    case 12: wdt_osc = 2900000; break;
-    case 13: wdt_osc = 3100000; break;
-    case 14: wdt_osc = 3200000; break;
-    case 15: wdt_osc = 3400000; break;
-  }
-  wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
-
-  switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
-    case 0:                             /* Internal RC oscillator             */
-      SystemCoreClock = __IRC_OSC_CLK;
-      break;
-    case 1:                             /* Input Clock to System PLL          */
-      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
-          case 0:                       /* Internal RC oscillator             */
-            SystemCoreClock = __IRC_OSC_CLK;
-            break;
-          case 1:                       /* System oscillator                  */
-            SystemCoreClock = __SYS_OSC_CLK;
-            break;
-          case 2:                       /* Reserved                           */
-            SystemCoreClock = 0;
-            break;
-          case 3:                       /* CLKIN pin                          */
-            SystemCoreClock = __CLKIN_CLK;
-            break;
-      }
-      break;
-    case 2:                             /* WDT Oscillator                     */
-      SystemCoreClock = wdt_osc;
-      break;
-    case 3:                             /* System PLL Clock Out               */
-      switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
-          case 0:                       /* Internal RC oscillator             */
-            SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
-            break;
-          case 1:                       /* System oscillator                  */
-            SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
-            break;
-          case 2:                       /* Reserved                           */
-            SystemCoreClock = 0;
-            break;
-          case 3:                       /* CLKIN pin                          */
-            SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
-            break;
-      }
-      break;
-  }
-
-  SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
-
-}
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void) {
-  volatile uint32_t i;
-
-  /* System clock to the IOCON & the SWM need to be enabled or
-  most of the I/O related peripherals won't work. */
-  LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
-
-#if (CLOCK_SETUP)                                 /* Clock Setup              */
-
-#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
-  LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
-  LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
-  LPC_SWM->PINENABLE0 &= ~(0x3 << 4);
-  LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 5);        /* Power-up System Osc      */
-  LPC_SYSCON->SYSOSCCTRL    = SYSOSCCTRL_Val;
-  for (i = 0; i < 200; i++) __NOP();
-#endif
-#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
-  LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
-  LPC_SWM->PINENABLE0 &= ~(0x1 << 7);
-  for (i = 0; i < 200; i++) __NOP();
-#endif
-
-  LPC_SYSCON->SYSPLLCLKSEL  = SYSPLLCLKSEL_Val;   /* Select PLL Input         */
-  LPC_SYSCON->SYSPLLCLKUEN  = 0x01;               /* Update Clock Source      */
-  while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01));     /* Wait Until Updated       */
-#if ((MAINCLKSEL_Val & 0x03) == 3)                /* Main Clock is PLL Out    */
-  LPC_SYSCON->SYSPLLCTRL    = SYSPLLCTRL_Val;
-  LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 7);        /* Power-up SYSPLL          */
-  while (!(LPC_SYSCON->SYSPLLSTAT & 0x01));	      /* Wait Until PLL Locked    */
-#endif
-
-#if (((MAINCLKSEL_Val & 0x03) == 2) )
-  LPC_SYSCON->WDTOSCCTRL    = WDTOSCCTRL_Val;
-  LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 6);        /* Power-up WDT Clock       */
-  for (i = 0; i < 200; i++) __NOP();
-#endif
-
-  LPC_SYSCON->MAINCLKSEL    = MAINCLKSEL_Val;     /* Select PLL Clock Output  */
-  LPC_SYSCON->MAINCLKUEN    = 0x01;               /* Update MCLK Clock Source */
-  while (!(LPC_SYSCON->MAINCLKUEN & 0x01));       /* Wait Until Updated       */
-
-  LPC_SYSCON->SYSAHBCLKDIV  = SYSAHBCLKDIV_Val;
-#endif
-}

--- a/vendor/NXP/LPC812/cmsis/system_LPC8xx.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,62 +0,0 @@
-/******************************************************************************
- * @file:    system_LPC8xx.h
- * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File
- *           for the NXP LPC8xx Device Series
- * @version: V1.0
- * @date:    16. Aug. 2012
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2012 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC8xx_H
-#define __SYSTEM_LPC8xx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC8xx_H */

--- a/vendor/NXP/LPC812/cmsis/uARM/LPC812.sct	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,14 +0,0 @@
-
-LR_IROM1 0x00000000 0x4000  {    ; load region size_region (32k)
-  ER_IROM1 0x00000000 0x4000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; 8_byte_aligned(48 vect * 4 bytes) =  8_byte_aligned(0xC0) = 0xC0
-  ; 8KB - 0xC0 = 0xF40
-  RW_IRAM1 0x100000C0 0xF40  {
-   .ANY (+RW +ZI)
-  }
-}
-

--- a/vendor/NXP/LPC812/cmsis/uARM/startup_LPC8xx.s	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,211 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC8xx.s
-; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
-; *           for the NXP LPC8xx Device Series
-; * @version: V1.0
-; * @date:    16. Aug. 2012
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2012 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
-; * processor based microcontrollers.  This file can be freely distributed
-; * within development tools that are supporting such ARM based processors.
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000200
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __initial_sp
-
-Stack_Mem       SPACE   Stack_Size
-__initial_sp            EQU     0x10001000
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     SPI0_IRQHandler             ; SPI0 controller
-                DCD     SPI1_IRQHandler             ; SPI1 controller
-                DCD     0                           ; Reserved
-                DCD     UART0_IRQHandler            ; UART0
-                DCD     UART1_IRQHandler            ; UART1
-                DCD     UART2_IRQHandler            ; UART2
-                DCD     0                           ; Reserved
-                DCD     0                           ; Reserved
-                DCD     I2C_IRQHandler              ; I2C controller
-                DCD     SCT_IRQHandler              ; Smart Counter Timer
-                DCD     MRT_IRQHandler              ; Multi-Rate Timer
-                DCD     CMP_IRQHandler              ; Comparator
-                DCD     WDT_IRQHandler              ; PIO1 (0:11)
-                DCD     BOD_IRQHandler              ; Brown Out Detect
-                DCD     0                           ; Reserved
-                DCD     WKT_IRQHandler              ; Wakeup timer
-                DCD     0                           ; Reserved
-                DCD     0                           ; Reserved
-                DCD     0                           ; Reserved
-                DCD     0                           ; Reserved
-                DCD     0                           ; Reserved
-                DCD     0                           ; Reserved
-                DCD     0                           ; Reserved
-                DCD     0                           ; Reserved
-                DCD     PININT0_IRQHandler          ; PIO INT0
-                DCD     PININT1_IRQHandler         ; PIO INT1
-                DCD     PININT2_IRQHandler         ; PIO INT2
-                DCD     PININT3_IRQHandler         ; PIO INT3
-                DCD     PININT4_IRQHandler         ; PIO INT4
-                DCD     PININT5_IRQHandler         ; PIO INT5
-                DCD     PININT6_IRQHandler         ; PIO INT6
-                DCD     PININT7_IRQHandler         ; PIO INT7
-
-
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled
-; for particular peripheral.
-;NMI_Handler     PROC
-;                EXPORT  NMI_Handler               [WEAK]
-;                B       .
-;                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  NMI_Handler               [WEAK]
-                EXPORT  SPI0_IRQHandler           [WEAK]
-                EXPORT  SPI1_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  SCT_IRQHandler            [WEAK]
-                EXPORT  MRT_IRQHandler            [WEAK]
-                EXPORT  CMP_IRQHandler            [WEAK]
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  BOD_IRQHandler            [WEAK]
-
-                EXPORT  WKT_IRQHandler            [WEAK]
-
-                EXPORT  PININT0_IRQHandler      [WEAK]
-                EXPORT  PININT1_IRQHandler      [WEAK]
-                EXPORT  PININT2_IRQHandler      [WEAK]
-                EXPORT  PININT3_IRQHandler      [WEAK]
-                EXPORT  PININT4_IRQHandler      [WEAK]
-                EXPORT  PININT5_IRQHandler      [WEAK]
-                EXPORT  PININT6_IRQHandler      [WEAK]
-                EXPORT  PININT7_IRQHandler      [WEAK]
-
-NMI_Handler
-SPI0_IRQHandler
-SPI1_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-I2C_IRQHandler
-SCT_IRQHandler
-MRT_IRQHandler
-CMP_IRQHandler
-WDT_IRQHandler
-BOD_IRQHandler
-WKT_IRQHandler
-PININT0_IRQHandler
-PININT1_IRQHandler
-PININT2_IRQHandler
-PININT3_IRQHandler
-PININT4_IRQHandler
-PININT5_IRQHandler
-PININT6_IRQHandler
-PININT7_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- a/vendor/NXP/LPC812/cmsis/uARM/sys.cpp	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- * 
- * Setup a fixed single stack/heap memory model, 
- *  between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/vendor/NXP/LPC812/hal/PeripheralNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC812/hal/PinNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,106 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-typedef enum {
-    P0_0 = 0,
-    P0_1 = 1,
-    P0_2 = 2,
-    P0_3 = 3,
-    P0_4 = 4,
-    P0_5 = 5,
-    P0_6 = 6,
-    P0_7 = 7,
-    P0_8 = 8,
-    P0_9 = 9,
-    P0_10 = 10,
-    P0_11 = 11,
-    P0_12 = 12,
-    P0_13 = 13,
-    P0_14 = 14,
-    P0_15 = 15,
-    P0_16 = 16,
-    P0_17 = 17,
-    
-    D0 = P0_0,
-    D1 = P0_4,
-    D2 = P0_6,
-    D3 = P0_8,
-    D4 = P0_9,
-    
-    D7 = P0_7,
-    D8 = P0_17,
-    D9 = P0_16,
-    D10 = P0_13,
-    D11 = P0_14,
-    D12 = P0_15,
-    D13 = P0_12,
-    
-    A4 = P0_10,
-    A5 = P0_11,
-    
-    // LPC800-MAX board
-    LED_RED = P0_7,
-    LED_GREEN = P0_17,
-    LED_BLUE = P0_16,
-    
-    // mbed original LED naming
-    LED1 = LED_BLUE,
-    LED2 = LED_GREEN,
-    LED3 = LED_RED,
-    LED4 = LED_RED,
-    
-    // Serial to USB pins
-    USBTX = P0_6,
-    USBRX = P0_1,
-    
-    // Not connected
-    NC = (int)0xFFFFFFFF,
-} PinName;
-
-typedef enum {
-    PullUp = 2,
-    PullDown = 1,
-    PullNone = 0,
-    Repeater = 3,
-    OpenDrain = 4
-} PinMode;
-
-#define STDIO_UART_TX     USBTX
-#define STDIO_UART_RX     USBRX
-
-typedef struct {
-    unsigned char n;
-    unsigned char offset;
-} SWM_Map;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC812/hal/PortNames.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    Port0 = 0,
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif

--- a/vendor/NXP/LPC812/hal/device.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,57 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-#define DEVICE_PORTIN           0
-#define DEVICE_PORTOUT          0
-#define DEVICE_PORTINOUT        0
-
-#define DEVICE_INTERRUPTIN      1
-
-#define DEVICE_ANALOGIN         0
-#define DEVICE_ANALOGOUT        0
-
-#define DEVICE_SERIAL           1
-
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         0
-
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         0
-
-#define DEVICE_CAN              0
-
-#define DEVICE_RTC              0
-
-#define DEVICE_ETHERNET         0
-
-#define DEVICE_PWMOUT           0
-
-#define DEVICE_SEMIHOST         0
-#define DEVICE_LOCALFILESYSTEM  0
-
-#define DEVICE_SLEEP            0
-
-#define DEVICE_DEBUG_AWARENESS  0
-
-#define DEVICE_STDIO_MESSAGES   1
-
-#define DEVICE_ERROR_RED        1
-
-#include "objects.h"
-
-#endif

--- a/vendor/NXP/LPC812/hal/gpio_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,69 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "gpio_api.h"
-#include "pinmap.h"
-
-static int  gpio_enabled = 0;
-static void gpio_enable(void) {
-    gpio_enabled = 1;
-    
-    /* Enable AHB clock to the GPIO domain. */
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
-    
-    /* Peripheral reset control to GPIO and GPIO INT, a "1" bring it out of reset. */
-    LPC_SYSCON->PRESETCTRL &= ~(0x1<<10);
-    LPC_SYSCON->PRESETCTRL |=  (0x1<<10);
-}
-
-uint32_t gpio_set(PinName pin) {
-    int f = 0;
-    
-    if (!gpio_enabled)
-         gpio_enable();
-    
-    pin_function(pin, f);
-    
-    return (1 << ((int)pin & 0x1F));
-}
-
-void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
-    if(pin == NC) return;
-    
-    obj->pin = pin;
-    obj->mask = gpio_set(pin);
-    
-    obj->reg_set = &LPC_GPIO_PORT->SET0;
-    obj->reg_clr = &LPC_GPIO_PORT->CLR0;
-    obj->reg_in  = &LPC_GPIO_PORT->PIN0;
-    obj->reg_dir = &LPC_GPIO_PORT->DIR0;
-    
-    gpio_dir(obj, direction);
-    switch (direction) {
-        case PIN_OUTPUT: pin_mode(pin, PullNone); break;
-        case PIN_INPUT : pin_mode(pin, PullDown); break;
-    }
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode) {
-    pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction) {
-    switch (direction) {
-        case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
-        case PIN_OUTPUT: *obj->reg_dir |=  obj->mask; break;
-    }
-}

--- a/vendor/NXP/LPC812/hal/gpio_irq_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,127 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stddef.h>
-
-#include "cmsis.h"
-#include "gpio_irq_api.h"
-#include "error.h"
-
-#define CHANNEL_NUM    8
-#define LPC_GPIO_X LPC_PIN_INT
-#define PININT_IRQ PININT0_IRQn
-
-static uint32_t channel_ids[CHANNEL_NUM] = {0};
-static gpio_irq_handler irq_handler;
-
-static inline void handle_interrupt_in(uint32_t channel) {
-    uint32_t ch_bit = (1 << channel);
-    // Return immediately if:
-    //   * The interrupt was already served
-    //   * There is no user handler
-    //   * It is a level interrupt, not an edge interrupt
-    if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
-         (channel_ids[channel] == 0      ) ||
-         (LPC_GPIO_X->ISEL & ch_bit      ) ) return;
-
-    if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
-        irq_handler(channel_ids[channel], IRQ_RISE);
-        LPC_GPIO_X->RISE = ch_bit;
-    }
-    if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
-        irq_handler(channel_ids[channel], IRQ_FALL);
-    }
-    LPC_GPIO_X->IST = ch_bit;
-}
-
-void gpio_irq0(void) {handle_interrupt_in(0);}
-void gpio_irq1(void) {handle_interrupt_in(1);}
-void gpio_irq2(void) {handle_interrupt_in(2);}
-void gpio_irq3(void) {handle_interrupt_in(3);}
-void gpio_irq4(void) {handle_interrupt_in(4);}
-void gpio_irq5(void) {handle_interrupt_in(5);}
-void gpio_irq6(void) {handle_interrupt_in(6);}
-void gpio_irq7(void) {handle_interrupt_in(7);}
-
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
-    if (pin == NC) return -1;
-    
-    irq_handler = handler;
-    
-    int found_free_channel = 0;
-    int i = 0;
-    for (i=0; i<CHANNEL_NUM; i++) {
-        if (channel_ids[i] == 0) {
-            channel_ids[i] = id;
-            obj->ch = i;
-            found_free_channel = 1;
-            break;
-        }
-    }
-    if (!found_free_channel) return -1;
-
-    /* Enable AHB clock to the GPIO domain. */
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
-    
-    LPC_SYSCON->PINTSEL[obj->ch] = pin;
-    
-    // Interrupt Wake-Up Enable
-    LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
-    
-    void (*channels_irq)(void) = NULL;
-    switch (obj->ch) {
-        case 0: channels_irq = &gpio_irq0; break;
-        case 1: channels_irq = &gpio_irq1; break;
-        case 2: channels_irq = &gpio_irq2; break;
-        case 3: channels_irq = &gpio_irq3; break;
-        case 4: channels_irq = &gpio_irq4; break;
-        case 5: channels_irq = &gpio_irq5; break;
-        case 6: channels_irq = &gpio_irq6; break;
-        case 7: channels_irq = &gpio_irq7; break;
-    }
-    NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
-    NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
-    
-    return 0;
-}
-
-void gpio_irq_free(gpio_irq_t *obj) {
-    channel_ids[obj->ch] = 0;
-    LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
-}
-
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
-    unsigned int ch_bit = (1 << obj->ch);
-    
-    // Clear interrupt
-    if (!(LPC_GPIO_X->ISEL & ch_bit))
-        LPC_GPIO_X->IST = ch_bit;
-    
-    // Edge trigger
-    LPC_GPIO_X->ISEL &= ~ch_bit;
-    if (event == IRQ_RISE) {
-        if (enable) {
-            LPC_GPIO_X->IENR |= ch_bit;
-        } else {
-            LPC_GPIO_X->IENR &= ~ch_bit;
-        }
-    } else {
-        if (enable) {
-            LPC_GPIO_X->IENF |= ch_bit;
-        } else {
-            LPC_GPIO_X->IENF &= ~ch_bit;
-        }
-    }
-}

--- a/vendor/NXP/LPC812/hal/gpio_object.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    PinName  pin;
-    uint32_t mask;
-
-    __IO uint32_t *reg_dir;
-    __IO uint32_t *reg_set;
-    __IO uint32_t *reg_clr;
-    __I  uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
-    if (value)
-        *obj->reg_set = obj->mask;
-    else
-        *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
-    return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC812/hal/i2c_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,235 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "i2c_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const SWM_Map SWM_I2C_SDA[] = {
-    {7, 24},
-};
-
-static const SWM_Map SWM_I2C_SCL[] = {
-    {8, 0},
-};
-
-static uint8_t repeated_start = 0;
-
-#define I2C_DAT(x)          (x->i2c->MSTDAT)
-#define I2C_STAT(x)         ((x->i2c->STAT >> 1) & (0x07))
-
-static inline int i2c_status(i2c_t *obj) {
-    return I2C_STAT(obj);
-}
-
-// Wait until the Serial Interrupt (SI) is set
-static int i2c_wait_SI(i2c_t *obj) {
-    int timeout = 0;
-    while (!(obj->i2c->STAT & (1 << 0))) {
-        timeout++;
-        if (timeout > 100000) return -1;
-    }
-    return 0;
-}
-
-static inline void i2c_interface_enable(i2c_t *obj) {
-    obj->i2c->CFG |= (1 << 0);
-}
-
-static inline void i2c_power_enable(i2c_t *obj) {
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1<<5);	
-    LPC_SYSCON->PRESETCTRL &= ~(0x1<<6);
-    LPC_SYSCON->PRESETCTRL |= (0x1<<6);
-}
-
-void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
-    obj->i2c = (LPC_I2C_TypeDef *)LPC_I2C;
-    
-    const SWM_Map *swm;
-    uint32_t regVal;
-    
-    swm = &SWM_I2C_SDA[0];
-    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
-    LPC_SWM->PINASSIGN[swm->n] = regVal |  (sda   << swm->offset);
-    
-    swm = &SWM_I2C_SCL[0];
-    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
-    LPC_SWM->PINASSIGN[swm->n] = regVal |  (scl   << swm->offset);
-    
-    // enable power
-    i2c_power_enable(obj);
-    // set default frequency at 100k
-    i2c_frequency(obj, 100000);
-    i2c_interface_enable(obj);
-}
-
-inline int i2c_start(i2c_t *obj) {
-    int status = 0;
-    if (repeated_start) {
-        obj->i2c->MSTCTL = (1 << 1) | (1 << 0);
-        repeated_start = 0;
-    } else {
-        obj->i2c->MSTCTL = (1 << 1);
-    }
-    return status;
-}
-
-inline void i2c_stop(i2c_t *obj) {
-    obj->i2c->MSTCTL = (1 << 2) | (1 << 0);
-    while ((obj->i2c->STAT & ((1 << 0) | (7 << 1))) != ((1 << 0) | (0 << 1)));
-}
-
-
-static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
-    // write the data
-    I2C_DAT(obj) = value;
-    
-    if (!addr)
-        obj->i2c->MSTCTL = (1 << 0);
-    
-    // wait and return status
-    i2c_wait_SI(obj);
-    return i2c_status(obj);
-}
-
-static inline int i2c_do_read(i2c_t *obj, int last) {
-    // wait for it to arrive
-    i2c_wait_SI(obj);
-    if (!last)
-        obj->i2c->MSTCTL = (1 << 0);
-    
-    // return the data
-    return (I2C_DAT(obj) & 0xFF);
-}
-
-void i2c_frequency(i2c_t *obj, int hz) {
-    // No peripheral clock divider on the M0
-    uint32_t PCLK = SystemCoreClock;
-    
-    uint32_t clkdiv = PCLK / (hz * 4) - 1;
-    
-    obj->i2c->DIV = clkdiv;
-    obj->i2c->MSTTIME = 0;
-}
-
-// The I2C does a read or a write as a whole operation
-// There are two types of error conditions it can encounter
-//  1) it can not obtain the bus
-//  2) it gets error responses at part of the transmission
-//
-// We tackle them as follows:
-//  1) we retry until we get the bus. we could have a "timeout" if we can not get it
-//      which basically turns it in to a 2)
-//  2) on error, we use the standard error mechanisms to report/debug
-//
-// Therefore an I2C transaction should always complete. If it doesn't it is usually
-// because something is setup wrong (e.g. wiring), and we don't need to programatically
-// check for that
-
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
-    int count, status;
-    
-    i2c_start(obj);
-    
-    status = i2c_do_write(obj, (address | 0x01), 1);
-    if (status != 0x01) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    // Read in all except last byte
-    for (count = 0; count < (length - 1); count++) {
-        int value = i2c_do_read(obj, 0);
-        status = i2c_status(obj);
-        if (status != 0x00) {
-            i2c_stop(obj);
-            return status;
-        }
-        data[count] = (char) value;
-    }
-    
-    // read in last byte
-    int value = i2c_do_read(obj, 1);
-    status = i2c_status(obj);
-    if (status != 0x01) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    data[count] = (char) value;
-    
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-    } else {
-        repeated_start = 1;
-    }
-    
-    return 0;
-}
-
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
-    int i, status;
-    
-    i2c_start(obj);
-    
-    status = i2c_do_write(obj, (address & 0xFE), 1);
-    if (status != 0x02) {
-        i2c_stop(obj);
-        return status;
-    }
-    
-    for (i=0; i<length; i++) {
-        status = i2c_do_write(obj, data[i], 0);
-        if (status != 0x02) {
-            i2c_stop(obj);
-            return status;
-        }
-    }
-    
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-    } else {
-        repeated_start = 1;
-    }
-    
-    return 0;
-}
-
-void i2c_reset(i2c_t *obj) {
-    i2c_stop(obj);
-}
-
-int i2c_byte_read(i2c_t *obj, int last) {
-    return (i2c_do_read(obj, last) & 0xFF);
-}
-
-int i2c_byte_write(i2c_t *obj, int data) {
-    int ack;
-    int status = i2c_do_write(obj, (data & 0xFF), 0);
-    
-    switch(status) {
-        case 2:
-            ack = 1;
-            break;
-        default:
-            ack = 0;
-            break;
-    }
-
-    return ack;
-}

--- a/vendor/NXP/LPC812/hal/objects.h	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,52 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    uint32_t ch;
-};
-
-struct serial_s {
-    LPC_USART_TypeDef *uart;
-    unsigned char index;
-};
-
-struct i2c_s {
-    LPC_I2C_TypeDef *i2c;
-};
-
-struct spi_s {
-    LPC_SPI_TypeDef *spi;
-    unsigned char spi_n;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/vendor/NXP/LPC812/hal/pinmap.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,50 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "pinmap.h"
-#include "error.h"
-
-__IO uint32_t* IOCON_REGISTERS[18] = {
-        &LPC_IOCON->PIO0_0 , &LPC_IOCON->PIO0_1 , &LPC_IOCON->PIO0_2 ,
-        &LPC_IOCON->PIO0_3 , &LPC_IOCON->PIO0_4 , &LPC_IOCON->PIO0_5 ,
-        &LPC_IOCON->PIO0_6 , &LPC_IOCON->PIO0_7 , &LPC_IOCON->PIO0_8 ,
-        &LPC_IOCON->PIO0_9 , &LPC_IOCON->PIO0_10, &LPC_IOCON->PIO0_11,
-        &LPC_IOCON->PIO0_12, &LPC_IOCON->PIO0_13, &LPC_IOCON->PIO0_14,
-        &LPC_IOCON->PIO0_15, &LPC_IOCON->PIO0_16, &LPC_IOCON->PIO0_17,
-};
-
-void pin_function(PinName pin, int function) {
-    
-}
-
-void pin_mode(PinName pin, PinMode mode) {
-    if (pin == (uint32_t)NC) { return; }
-    
-    if ((pin == 10) || (pin == 11)) {
-        // True open-drain pins can be configured for different I2C-bus speeds
-        return;
-    }
-    
-    __IO uint32_t *reg = IOCON_REGISTERS[pin];
-    
-    if (mode == OpenDrain) {
-        *reg |= (1 << 10);
-    } else {
-        uint32_t tmp = *reg;
-        tmp &= ~(0x3 << 3);
-        tmp |= (mode & 0x3) << 3;
-        *reg = tmp;
-    }
-}

--- a/vendor/NXP/LPC812/hal/serial_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,269 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// math.h required for floating point operations for baud rate calculation
-#include <math.h>
-#include <string.h>
-
-#include "serial_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-/******************************************************************************
- * INITIALIZATION
- ******************************************************************************/
-#define UART_NUM    3
-
-static const SWM_Map SWM_UART_TX[] = {
-    {0, 0},
-    {1, 8},
-    {2, 16},
-};
-
-static const SWM_Map SWM_UART_RX[] = {
-    {0, 8},
-    {1, 16},
-    {2, 24},
-};
-
-// bit flags for used UARTs
-static unsigned char uart_used = 0;
-static int get_available_uart(void) {
-    int i;
-    for (i=0; i<3; i++) {
-        if ((uart_used & (1 << i)) == 0)
-            return i;
-    }
-    return -1;
-}
-
-#define UART_EN       (0x01<<0)
-
-#define CTS_DELTA     (0x01<<5)
-#define RXBRK         (0x01<<10)
-#define DELTA_RXBRK   (0x01<<11)
-
-#define RXRDY         (0x01<<0)
-#define TXRDY         (0x01<<2)
-
-static uint32_t UARTSysClk;
-
-static uint32_t serial_irq_ids[UART_NUM] = {0};
-static uart_irq_handler irq_handler;
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-void serial_init(serial_t *obj, PinName tx, PinName rx) {
-    int is_stdio_uart = 0;
-    
-    int uart_n = get_available_uart();
-    if (uart_n == -1) {
-        error("No available UART");
-    }
-    obj->index = uart_n;
-    obj->uart = (LPC_USART_TypeDef *)(LPC_USART0_BASE + (0x4000 * uart_n));
-    uart_used |= (1 << uart_n);
-    
-    const SWM_Map *swm;
-    uint32_t regVal;
-    
-    swm = &SWM_UART_TX[uart_n];
-    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
-    LPC_SWM->PINASSIGN[swm->n] = regVal |  (tx   << swm->offset);
-    
-    swm = &SWM_UART_RX[uart_n];
-    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
-    LPC_SWM->PINASSIGN[swm->n] = regVal |  (rx   << swm->offset);
-    
-    /* uart clock divided by 1 */
-    LPC_SYSCON->UARTCLKDIV = 1;
-    
-    /* disable uart interrupts */
-    NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
-    
-    /* Enable UART clock */
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (14 + uart_n));
-    
-    /* Peripheral reset control to UART, a "1" bring it out of reset. */
-    LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n));
-    LPC_SYSCON->PRESETCTRL |=  (0x1 << (3 + uart_n));
-    
-    UARTSysClk = SystemCoreClock / LPC_SYSCON->UARTCLKDIV;
-    
-    // set default baud rate and format
-    serial_baud  (obj, 9600);
-    serial_format(obj, 8, ParityNone, 1);
-    
-    /* Clear all status bits. */
-    obj->uart->STAT = CTS_DELTA | DELTA_RXBRK;
-    
-    /* enable uart interrupts */
-    NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
-    
-    /* Enable UART interrupt */
-    // obj->uart->INTENSET = RXRDY | TXRDY | DELTA_RXBRK;
-    
-    /* Enable UART */
-    obj->uart->CFG |= UART_EN;
-    
-    is_stdio_uart = ((tx == USBTX) && (rx == USBRX));
-    
-    if (is_stdio_uart) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj) {
-    uart_used &= ~(1 << obj->index);
-    serial_irq_ids[obj->index] = 0;
-}
-
-// serial_baud
-// set the baud rate, taking in to account the current SystemFrequency
-void serial_baud(serial_t *obj, int baudrate) {
-    /* Integer divider:
-         BRG = UARTSysClk/(Baudrate * 16) - 1
-       
-       Frational divider:
-         FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1)
-       
-       where
-         FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1)
-       
-       (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB
-           register is 0xFF.
-       (2) In ADD register value, depending on the value of UartSysClk,
-           baudrate, BRG register value, and SUB register value, be careful
-           about the order of multiplier and divider and make sure any
-           multiplier doesn't exceed 32-bit boundary and any divider doesn't get
-           down below one(integer 0).
-       (3) ADD should be always less than SUB.
-    */
-    obj->uart->BRG = UARTSysClk / 16 / baudrate - 1;
-    
-    LPC_SYSCON->UARTFRGDIV = 0xFF;
-    LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) /
-                                (baudrate * (obj->uart->BRG + 1))
-                              ) - (LPC_SYSCON->UARTFRGDIV + 1);
-
-}
-
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
-    // 0: 1 stop bits, 1: 2 stop bits
-    if (stop_bits != 1 && stop_bits != 2) {
-        error("Invalid stop bits specified");
-    }
-    stop_bits -= 1;
-    
-    // 0: 7 data bits ... 2: 9 data bits
-    if (data_bits < 7 || data_bits > 9) {
-        error("Invalid number of bits (%d) in serial format, should be 7..9", data_bits);
-    }
-    data_bits -= 7;
-    
-    int paritysel;
-    switch (parity) {
-        case ParityNone: paritysel = 0; break;
-        case ParityEven: paritysel = 2; break;
-        case ParityOdd : paritysel = 3; break;
-        default:
-            error("Invalid serial parity setting");
-            return;
-    }
-    
-    obj->uart->CFG = (data_bits << 2)
-                   | (paritysel << 4)
-                   | (stop_bits << 6);
-}
-
-/******************************************************************************
- * INTERRUPTS HANDLING
- ******************************************************************************/
-static inline void uart_irq(uint32_t iir, uint32_t index) {
-    // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
-    SerialIrq irq_type;
-    switch (iir) {
-        case 1: irq_type = TxIrq; break;
-        case 2: irq_type = RxIrq; break;
-        default: return;
-    }
-    
-    if (serial_irq_ids[index] != 0)
-        irq_handler(serial_irq_ids[index], irq_type);
-}
-
-void uart0_irq() {uart_irq((LPC_USART0->STAT & (1 << 2)) ? 2 : 1, 0);}
-void uart1_irq() {uart_irq((LPC_USART1->STAT & (1 << 2)) ? 2 : 1, 1);}
-void uart2_irq() {uart_irq((LPC_USART2->STAT & (1 << 2)) ? 2 : 1, 2);}
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
-    irq_handler = handler;
-    serial_irq_ids[obj->index] = id;
-}
-
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
-    IRQn_Type irq_n = (IRQn_Type)0;
-    uint32_t vector = 0;
-    switch ((int)obj->uart) {
-        case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
-        case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
-        case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
-    }
-    
-    if (enable) {
-        obj->uart->INTENSET = (1 << ((irq == RxIrq) ? 0 : 2));
-        NVIC_SetVector(irq_n, vector);
-        NVIC_EnableIRQ(irq_n);
-    } else { // disable
-        int all_disabled = 0;
-        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
-        obj->uart->INTENSET &= ~(1 << ((irq == RxIrq) ? 0 : 2));
-        all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0;
-        if (all_disabled)
-            NVIC_DisableIRQ(irq_n);
-    }
-}
-
-/******************************************************************************
- * READ/WRITE
- ******************************************************************************/
-int serial_getc(serial_t *obj) {
-    while (!serial_readable(obj));
-    return obj->uart->RXDATA;
-}
-
-void serial_putc(serial_t *obj, int c) {
-    while (!serial_writable(obj));
-    obj->uart->TXDATA = c;
-}
-
-int serial_readable(serial_t *obj) {
-    return obj->uart->STAT & RXRDY;
-}
-
-int serial_writable(serial_t *obj) {
-    return obj->uart->STAT & TXRDY;
-}
-
-void serial_clear(serial_t *obj) {
-    // [TODO]
-}
-
-void serial_pinout_tx(PinName tx) {
-    
-}

--- a/vendor/NXP/LPC812/hal/spi_api.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,210 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <math.h>
-
-#include "spi_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "error.h"
-
-static const SWM_Map SWM_SPI_SSEL[] = {
-    {4, 16},
-    {5, 16},
-};
-
-static const SWM_Map SWM_SPI_SCLK[] = {
-    {3, 24},
-    {4, 24},
-};
-
-static const SWM_Map SWM_SPI_MOSI[] = {
-    {4, 0},
-    {5, 0},
-};
-
-static const SWM_Map SWM_SPI_MISO[] = {
-    {4, 8},
-    {5, 16},
-};
-
-// bit flags for used SPIs
-static unsigned char spi_used = 0;
-static int get_available_spi(void) {
-    int i;
-    for (i=0; i<2; i++) {
-        if ((spi_used & (1 << i)) == 0)
-            return i;
-    }
-    return -1;
-}
-
-static inline int ssp_disable(spi_t *obj);
-static inline int ssp_enable(spi_t *obj);
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
-    int spi_n = get_available_spi();
-    if (spi_n == -1) {
-        error("No available SPI");
-    }
-    obj->spi_n = spi_n;
-    spi_used |= (1 << spi_n);
-    
-    obj->spi = (spi_n) ? (LPC_SPI_TypeDef *)(LPC_SPI1_BASE) : (LPC_SPI_TypeDef *)(LPC_SPI0_BASE);
-    
-    const SWM_Map *swm;
-    uint32_t regVal;
-    
-    swm = &SWM_SPI_SCLK[obj->spi_n];
-    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
-    LPC_SWM->PINASSIGN[swm->n] = regVal |  (sclk   << swm->offset);
-    
-    swm = &SWM_SPI_MOSI[obj->spi_n];
-    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
-    LPC_SWM->PINASSIGN[swm->n] = regVal |  (mosi   << swm->offset);
-    
-    swm = &SWM_SPI_MISO[obj->spi_n];
-    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
-    LPC_SWM->PINASSIGN[swm->n] = regVal |  (miso   << swm->offset);
-    
-    swm = &SWM_SPI_SSEL[obj->spi_n];
-    regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
-    LPC_SWM->PINASSIGN[swm->n] = regVal |  (ssel   << swm->offset);
-    
-    // clear interrupts
-    obj->spi->INTENCLR = 0x3f;
-    
-    // enable power and clocking
-    switch (obj->spi_n) {
-        case 0:
-            LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11);
-            LPC_SYSCON->PRESETCTRL &= ~(0x1<<0);
-            LPC_SYSCON->PRESETCTRL |= (0x1<<0);
-            break;
-        case 1:
-            LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
-            LPC_SYSCON->PRESETCTRL &= ~(0x1<<1);
-            LPC_SYSCON->PRESETCTRL |= (0x1<<1);
-            break;
-    }
-    
-    // set default format and frequency
-    if (ssel == NC) {
-        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
-    } else {
-        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
-    }
-    spi_frequency(obj, 1000000);
-    
-    // enable the ssp channel
-    ssp_enable(obj);
-}
-
-void spi_free(spi_t *obj) {}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave) {
-    ssp_disable(obj);
-    
-    if (!(bits >= 1 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
-        error("SPI format error");
-    }
-    
-    
-    int polarity = (mode & 0x2) ? 1 : 0;
-    int phase = (mode & 0x1) ? 1 : 0;
-    
-    // set it up
-    int DSS = bits - 1;            // DSS (data select size)
-    int SPO = (polarity) ? 1 : 0;  // SPO - clock out polarity
-    int SPH = (phase) ? 1 : 0;     // SPH - clock out phase
-    
-    uint32_t tmp = obj->spi->CFG;
-    tmp &= ~((1 << 2) | (1 << 4) | (1 << 5));
-    tmp |= (SPH << 4) | (SPO << 5) | ((slave ? 0 : 1) << 2);
-    obj->spi->CFG = tmp;
-    
-    // select frame length
-    tmp = obj->spi->TXDATCTL;
-    tmp &= ~(0xf << 24);
-    tmp |= (DSS << 24);
-    obj->spi->TXDATCTL = tmp;
-    
-    ssp_enable(obj);
-}
-
-void spi_frequency(spi_t *obj, int hz) {
-    ssp_disable(obj);
-    
-    uint32_t PCLK = SystemCoreClock;
-    
-    obj->spi->DIV = PCLK/hz - 1;
-    obj->spi->DLY = 0;
-    ssp_enable(obj);
-}
-
-static inline int ssp_disable(spi_t *obj) {
-    return obj->spi->CFG &= ~(1 << 0);
-}
-
-static inline int ssp_enable(spi_t *obj) {
-    return obj->spi->CFG |= (1 << 0);
-}
-
-static inline int ssp_readable(spi_t *obj) {
-    return obj->spi->STAT & (1 << 0);
-}
-
-static inline int ssp_writeable(spi_t *obj) {
-    return obj->spi->STAT & (1 << 1);
-}
-
-static inline void ssp_write(spi_t *obj, int value) {
-    while (!ssp_writeable(obj));
-    // end of transfer
-    obj->spi->TXDATCTL |= (1 << 20);
-    obj->spi->TXDAT = value;
-}
-
-static inline int ssp_read(spi_t *obj) {
-    while (!ssp_readable(obj));
-    return obj->spi->RXDAT;
-}
-
-static inline int ssp_busy(spi_t *obj) {
-    // TODO
-    return 0;
-}
-
-int spi_master_write(spi_t *obj, int value) {
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj) {
-    return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
-};
-
-int spi_slave_read(spi_t *obj) {
-    return obj->spi->RXDAT;
-}
-
-void spi_slave_write(spi_t *obj, int value) {
-    while (ssp_writeable(obj) == 0) ;
-    obj->spi->TXDAT = value;
-}
-
-int spi_busy(spi_t *obj) {
-    return ssp_busy(obj);
-}

--- a/vendor/NXP/LPC812/hal/us_ticker.c	Wed Jul 24 11:11:21 2013 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,93 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stddef.h>
-#include "us_ticker_api.h"
-#include "PeripheralNames.h"
-
-#define US_TICKER_TIMER_IRQn     SCT_IRQn
-
-int us_ticker_inited = 0;
-
-void us_ticker_init(void) {
-    if (us_ticker_inited) return;
-    us_ticker_inited = 1;
-    
-    // Enable the SCT clock
-    LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
-    
-    // Clear peripheral reset the SCT:
-    LPC_SYSCON->PRESETCTRL |= (1 << 8);
-    
-    // Unified counter (32 bits)
-    LPC_SCT->CONFIG |= 1;
-    
-    // halt and clear the counter
-    LPC_SCT->CTRL_L |= (1 << 2) | (1 << 3);
-    
-    // System Clock (12)MHz -> us_ticker (1)MHz
-    LPC_SCT->CTRL_L |= ((SystemCoreClock/1000000 - 1) << 5);
-    
-    // unhalt the counter:
-    //    - clearing bit 2 of the CTRL register
-    LPC_SCT->CTRL_L &= ~(1 << 2);
-    
-    NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
-    NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
-}
-
-uint32_t us_ticker_read() {
-    if (!us_ticker_inited)
-        us_ticker_init();
-    
-    return LPC_SCT->COUNT_U;
-}
-
-void us_ticker_set_interrupt(unsigned int timestamp) {
-    // halt the counter: 
-    //    - setting bit 2 of the CTRL register
-    LPC_SCT->CTRL_L |= (1 << 2);
-    
-    // set timestamp in compare register
-    LPC_SCT->MATCH[0].U = timestamp;
-    
-    // unhalt the counter:
-    //    - clearing bit 2 of the CTRL register
-    LPC_SCT->CTRL_L &= ~(1 << 2);
-    
-    // if events are not enabled, enable them
-    if (!(LPC_SCT->EVEN & 0x01)) {
-        
-        // comb mode = match only
-        LPC_SCT->EVENT[0].CTRL = (1 << 12);
-        
-        // ref manual:
-        //   In simple applications that do not 
-        //   use states, write 0x01 to this 
-        //   register to enable an event
-        LPC_SCT->EVENT[0].STATE |= 0x1;
-        
-        // enable events
-        LPC_SCT->EVEN |= 0x1;
-    }
-}
-
-void us_ticker_disable_interrupt(void) {
-    LPC_SCT->EVEN &= ~1;
-}
-
-void us_ticker_clear_interrupt(void) {
-    LPC_SCT->EVFLAG = 1;
-}