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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.c@13:0645d8841f51, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 14:12:34 2013 +0300
Revision:
13:0645d8841f51
Parent:
vendor/NXP/LPC812/cmsis/system_LPC8xx.c@10:3bc89ef62ce7
Child:
17:151ab7482c89
Update mbed sources to revision 64

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /******************************************************************************
emilmont 10:3bc89ef62ce7 2 * @file: system_LPC8xx.c
emilmont 10:3bc89ef62ce7 3 * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
emilmont 10:3bc89ef62ce7 4 * for the NXP LPC8xx Device Series
emilmont 10:3bc89ef62ce7 5 * @version: V1.0
emilmont 10:3bc89ef62ce7 6 * @date: 16. Aug. 2012
emilmont 10:3bc89ef62ce7 7 *----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 8 *
emilmont 10:3bc89ef62ce7 9 * Copyright (C) 2012 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 10 *
emilmont 10:3bc89ef62ce7 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
emilmont 10:3bc89ef62ce7 12 * processor based microcontrollers. This file can be freely distributed
emilmont 10:3bc89ef62ce7 13 * within development tools that are supporting such ARM based processors.
emilmont 10:3bc89ef62ce7 14 *
emilmont 10:3bc89ef62ce7 15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 10:3bc89ef62ce7 16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 10:3bc89ef62ce7 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 10:3bc89ef62ce7 18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 10:3bc89ef62ce7 19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 10:3bc89ef62ce7 20 *
emilmont 10:3bc89ef62ce7 21 ******************************************************************************/
emilmont 10:3bc89ef62ce7 22 #include <stdint.h>
emilmont 10:3bc89ef62ce7 23 #include "LPC8xx.h"
emilmont 10:3bc89ef62ce7 24
emilmont 10:3bc89ef62ce7 25 /*
emilmont 10:3bc89ef62ce7 26 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
emilmont 10:3bc89ef62ce7 27 */
emilmont 10:3bc89ef62ce7 28
emilmont 10:3bc89ef62ce7 29 /*--------------------- Clock Configuration ----------------------------------
emilmont 10:3bc89ef62ce7 30 //
emilmont 10:3bc89ef62ce7 31 // <e> Clock Configuration
emilmont 10:3bc89ef62ce7 32 // <h> System Oscillator Control Register (SYSOSCCTRL)
emilmont 10:3bc89ef62ce7 33 // <o1.0> BYPASS: System Oscillator Bypass Enable
emilmont 10:3bc89ef62ce7 34 // <i> If enabled then PLL input (sys_osc_clk) is fed
emilmont 10:3bc89ef62ce7 35 // <i> directly from XTALIN and XTALOUT pins.
emilmont 10:3bc89ef62ce7 36 // <o1.9> FREQRANGE: System Oscillator Frequency Range
emilmont 10:3bc89ef62ce7 37 // <i> Determines frequency range for Low-power oscillator.
emilmont 10:3bc89ef62ce7 38 // <0=> 1 - 20 MHz
emilmont 10:3bc89ef62ce7 39 // <1=> 15 - 25 MHz
emilmont 10:3bc89ef62ce7 40 // </h>
emilmont 10:3bc89ef62ce7 41 //
emilmont 10:3bc89ef62ce7 42 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
emilmont 10:3bc89ef62ce7 43 // <o2.0..4> DIVSEL: Select Divider for Fclkana
emilmont 10:3bc89ef62ce7 44 // <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
emilmont 10:3bc89ef62ce7 45 // <0-31>
emilmont 10:3bc89ef62ce7 46 // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
emilmont 10:3bc89ef62ce7 47 // <0=> Undefined
emilmont 10:3bc89ef62ce7 48 // <1=> 0.5 MHz
emilmont 10:3bc89ef62ce7 49 // <2=> 0.8 MHz
emilmont 10:3bc89ef62ce7 50 // <3=> 1.1 MHz
emilmont 10:3bc89ef62ce7 51 // <4=> 1.4 MHz
emilmont 10:3bc89ef62ce7 52 // <5=> 1.6 MHz
emilmont 10:3bc89ef62ce7 53 // <6=> 1.8 MHz
emilmont 10:3bc89ef62ce7 54 // <7=> 2.0 MHz
emilmont 10:3bc89ef62ce7 55 // <8=> 2.2 MHz
emilmont 10:3bc89ef62ce7 56 // <9=> 2.4 MHz
emilmont 10:3bc89ef62ce7 57 // <10=> 2.6 MHz
emilmont 10:3bc89ef62ce7 58 // <11=> 2.7 MHz
emilmont 10:3bc89ef62ce7 59 // <12=> 2.9 MHz
emilmont 10:3bc89ef62ce7 60 // <13=> 3.1 MHz
emilmont 10:3bc89ef62ce7 61 // <14=> 3.2 MHz
emilmont 10:3bc89ef62ce7 62 // <15=> 3.4 MHz
emilmont 10:3bc89ef62ce7 63 // </h>
emilmont 10:3bc89ef62ce7 64 //
emilmont 10:3bc89ef62ce7 65 // <h> System PLL Control Register (SYSPLLCTRL)
emilmont 10:3bc89ef62ce7 66 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
emilmont 10:3bc89ef62ce7 67 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
emilmont 10:3bc89ef62ce7 68 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
emilmont 10:3bc89ef62ce7 69 // <o3.0..4> MSEL: Feedback Divider Selection
emilmont 10:3bc89ef62ce7 70 // <i> M = MSEL + 1
emilmont 10:3bc89ef62ce7 71 // <0-31>
emilmont 10:3bc89ef62ce7 72 // <o3.5..6> PSEL: Post Divider Selection
emilmont 10:3bc89ef62ce7 73 // <0=> P = 1
emilmont 10:3bc89ef62ce7 74 // <1=> P = 2
emilmont 10:3bc89ef62ce7 75 // <2=> P = 4
emilmont 10:3bc89ef62ce7 76 // <3=> P = 8
emilmont 10:3bc89ef62ce7 77 // </h>
emilmont 10:3bc89ef62ce7 78 //
emilmont 10:3bc89ef62ce7 79 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
emilmont 10:3bc89ef62ce7 80 // <o4.0..1> SEL: System PLL Clock Source
emilmont 10:3bc89ef62ce7 81 // <0=> IRC Oscillator
emilmont 10:3bc89ef62ce7 82 // <1=> System Oscillator
emilmont 10:3bc89ef62ce7 83 // <2=> Reserved
emilmont 10:3bc89ef62ce7 84 // <3=> CLKIN pin
emilmont 10:3bc89ef62ce7 85 // </h>
emilmont 10:3bc89ef62ce7 86 //
emilmont 10:3bc89ef62ce7 87 // <h> Main Clock Source Select Register (MAINCLKSEL)
emilmont 10:3bc89ef62ce7 88 // <o5.0..1> SEL: Clock Source for Main Clock
emilmont 10:3bc89ef62ce7 89 // <0=> IRC Oscillator
emilmont 10:3bc89ef62ce7 90 // <1=> Input Clock to System PLL
emilmont 10:3bc89ef62ce7 91 // <2=> WDT Oscillator
emilmont 10:3bc89ef62ce7 92 // <3=> System PLL Clock Out
emilmont 10:3bc89ef62ce7 93 // </h>
emilmont 10:3bc89ef62ce7 94 //
emilmont 10:3bc89ef62ce7 95 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
emilmont 10:3bc89ef62ce7 96 // <o6.0..7> DIV: System AHB Clock Divider
emilmont 10:3bc89ef62ce7 97 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
emilmont 10:3bc89ef62ce7 98 // <i> 0 = is disabled
emilmont 10:3bc89ef62ce7 99 // <0-255>
emilmont 10:3bc89ef62ce7 100 // </h>
emilmont 10:3bc89ef62ce7 101 // </e>
emilmont 10:3bc89ef62ce7 102 */
emilmont 10:3bc89ef62ce7 103 #define CLOCK_SETUP 1
emilmont 10:3bc89ef62ce7 104 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
emilmont 10:3bc89ef62ce7 105 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
emilmont 10:3bc89ef62ce7 106 #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
emilmont 10:3bc89ef62ce7 107 #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
emilmont 10:3bc89ef62ce7 108 #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
emilmont 10:3bc89ef62ce7 109 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
emilmont 10:3bc89ef62ce7 110
emilmont 10:3bc89ef62ce7 111 /*
emilmont 10:3bc89ef62ce7 112 //-------- <<< end of configuration section >>> ------------------------------
emilmont 10:3bc89ef62ce7 113 */
emilmont 10:3bc89ef62ce7 114
emilmont 10:3bc89ef62ce7 115 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 116 Check the register settings
emilmont 10:3bc89ef62ce7 117 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 118 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
emilmont 10:3bc89ef62ce7 119 #define CHECK_RSVD(val, mask) (val & mask)
emilmont 10:3bc89ef62ce7 120
emilmont 10:3bc89ef62ce7 121 /* Clock Configuration -------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 122 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
emilmont 10:3bc89ef62ce7 123 #error "SYSOSCCTRL: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 124 #endif
emilmont 10:3bc89ef62ce7 125
emilmont 10:3bc89ef62ce7 126 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
emilmont 10:3bc89ef62ce7 127 #error "WDTOSCCTRL: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 128 #endif
emilmont 10:3bc89ef62ce7 129
emilmont 10:3bc89ef62ce7 130 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
emilmont 10:3bc89ef62ce7 131 #error "SYSPLLCLKSEL: Value out of range!"
emilmont 10:3bc89ef62ce7 132 #endif
emilmont 10:3bc89ef62ce7 133
emilmont 10:3bc89ef62ce7 134 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
emilmont 10:3bc89ef62ce7 135 #error "SYSPLLCTRL: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 136 #endif
emilmont 10:3bc89ef62ce7 137
emilmont 10:3bc89ef62ce7 138 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
emilmont 10:3bc89ef62ce7 139 #error "MAINCLKSEL: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 140 #endif
emilmont 10:3bc89ef62ce7 141
emilmont 10:3bc89ef62ce7 142 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
emilmont 10:3bc89ef62ce7 143 #error "SYSAHBCLKDIV: Value out of range!"
emilmont 10:3bc89ef62ce7 144 #endif
emilmont 10:3bc89ef62ce7 145
emilmont 10:3bc89ef62ce7 146
emilmont 10:3bc89ef62ce7 147 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 148 DEFINES
emilmont 10:3bc89ef62ce7 149 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 150
emilmont 10:3bc89ef62ce7 151 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 152 Define clocks
emilmont 10:3bc89ef62ce7 153 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 154 #define __XTAL (12000000UL) /* Oscillator frequency */
emilmont 10:3bc89ef62ce7 155 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
emilmont 10:3bc89ef62ce7 156 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
emilmont 10:3bc89ef62ce7 157 #define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
emilmont 10:3bc89ef62ce7 158
emilmont 10:3bc89ef62ce7 159
emilmont 10:3bc89ef62ce7 160 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
emilmont 10:3bc89ef62ce7 161 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
emilmont 10:3bc89ef62ce7 162
emilmont 10:3bc89ef62ce7 163 #if (CLOCK_SETUP) /* Clock Setup */
emilmont 10:3bc89ef62ce7 164 #if (__FREQSEL == 0)
emilmont 10:3bc89ef62ce7 165 #define __WDT_OSC_CLK ( 0) /* undefined */
emilmont 10:3bc89ef62ce7 166 #elif (__FREQSEL == 1)
emilmont 10:3bc89ef62ce7 167 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 168 #elif (__FREQSEL == 2)
emilmont 10:3bc89ef62ce7 169 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 170 #elif (__FREQSEL == 3)
emilmont 10:3bc89ef62ce7 171 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 172 #elif (__FREQSEL == 4)
emilmont 10:3bc89ef62ce7 173 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 174 #elif (__FREQSEL == 5)
emilmont 10:3bc89ef62ce7 175 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 176 #elif (__FREQSEL == 6)
emilmont 10:3bc89ef62ce7 177 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 178 #elif (__FREQSEL == 7)
emilmont 10:3bc89ef62ce7 179 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 180 #elif (__FREQSEL == 8)
emilmont 10:3bc89ef62ce7 181 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 182 #elif (__FREQSEL == 9)
emilmont 10:3bc89ef62ce7 183 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 184 #elif (__FREQSEL == 10)
emilmont 10:3bc89ef62ce7 185 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 186 #elif (__FREQSEL == 11)
emilmont 10:3bc89ef62ce7 187 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 188 #elif (__FREQSEL == 12)
emilmont 10:3bc89ef62ce7 189 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 190 #elif (__FREQSEL == 13)
emilmont 10:3bc89ef62ce7 191 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 192 #elif (__FREQSEL == 14)
emilmont 10:3bc89ef62ce7 193 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 194 #else
emilmont 10:3bc89ef62ce7 195 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 196 #endif
emilmont 10:3bc89ef62ce7 197
emilmont 10:3bc89ef62ce7 198 /* sys_pllclkin calculation */
emilmont 10:3bc89ef62ce7 199 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
emilmont 10:3bc89ef62ce7 200 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
emilmont 10:3bc89ef62ce7 201 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
emilmont 10:3bc89ef62ce7 202 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
emilmont 10:3bc89ef62ce7 203 #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
emilmont 10:3bc89ef62ce7 204 #define __SYS_PLLCLKIN (__CLKIN_CLK)
emilmont 10:3bc89ef62ce7 205 #else
emilmont 10:3bc89ef62ce7 206 #define __SYS_PLLCLKIN (0)
emilmont 10:3bc89ef62ce7 207 #endif
emilmont 10:3bc89ef62ce7 208
emilmont 10:3bc89ef62ce7 209 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
emilmont 10:3bc89ef62ce7 210
emilmont 10:3bc89ef62ce7 211 /* main clock calculation */
emilmont 10:3bc89ef62ce7 212 #if ((MAINCLKSEL_Val & 0x03) == 0)
emilmont 10:3bc89ef62ce7 213 #define __MAIN_CLOCK (__IRC_OSC_CLK)
emilmont 10:3bc89ef62ce7 214 #elif ((MAINCLKSEL_Val & 0x03) == 1)
emilmont 10:3bc89ef62ce7 215 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
emilmont 10:3bc89ef62ce7 216 #elif ((MAINCLKSEL_Val & 0x03) == 2)
emilmont 10:3bc89ef62ce7 217 #if (__FREQSEL == 0)
emilmont 10:3bc89ef62ce7 218 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
emilmont 10:3bc89ef62ce7 219 #else
emilmont 10:3bc89ef62ce7 220 #define __MAIN_CLOCK (__WDT_OSC_CLK)
emilmont 10:3bc89ef62ce7 221 #endif
emilmont 10:3bc89ef62ce7 222 #elif ((MAINCLKSEL_Val & 0x03) == 3)
emilmont 10:3bc89ef62ce7 223 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
emilmont 10:3bc89ef62ce7 224 #else
emilmont 10:3bc89ef62ce7 225 #define __MAIN_CLOCK (0)
emilmont 10:3bc89ef62ce7 226 #endif
emilmont 10:3bc89ef62ce7 227
emilmont 10:3bc89ef62ce7 228 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
emilmont 10:3bc89ef62ce7 229
emilmont 10:3bc89ef62ce7 230 #else
emilmont 10:3bc89ef62ce7 231 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
emilmont 10:3bc89ef62ce7 232 #endif // CLOCK_SETUP
emilmont 10:3bc89ef62ce7 233
emilmont 10:3bc89ef62ce7 234
emilmont 10:3bc89ef62ce7 235 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 236 Clock Variable definitions
emilmont 10:3bc89ef62ce7 237 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 238 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
emilmont 10:3bc89ef62ce7 239
emilmont 10:3bc89ef62ce7 240
emilmont 10:3bc89ef62ce7 241 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 242 Clock functions
emilmont 10:3bc89ef62ce7 243 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 244 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
emilmont 10:3bc89ef62ce7 245 {
emilmont 10:3bc89ef62ce7 246 uint32_t wdt_osc = 0;
emilmont 10:3bc89ef62ce7 247
emilmont 10:3bc89ef62ce7 248 /* Determine clock frequency according to clock register values */
emilmont 10:3bc89ef62ce7 249 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
emilmont 10:3bc89ef62ce7 250 case 0: wdt_osc = 0; break;
emilmont 10:3bc89ef62ce7 251 case 1: wdt_osc = 500000; break;
emilmont 10:3bc89ef62ce7 252 case 2: wdt_osc = 800000; break;
emilmont 10:3bc89ef62ce7 253 case 3: wdt_osc = 1100000; break;
emilmont 10:3bc89ef62ce7 254 case 4: wdt_osc = 1400000; break;
emilmont 10:3bc89ef62ce7 255 case 5: wdt_osc = 1600000; break;
emilmont 10:3bc89ef62ce7 256 case 6: wdt_osc = 1800000; break;
emilmont 10:3bc89ef62ce7 257 case 7: wdt_osc = 2000000; break;
emilmont 10:3bc89ef62ce7 258 case 8: wdt_osc = 2200000; break;
emilmont 10:3bc89ef62ce7 259 case 9: wdt_osc = 2400000; break;
emilmont 10:3bc89ef62ce7 260 case 10: wdt_osc = 2600000; break;
emilmont 10:3bc89ef62ce7 261 case 11: wdt_osc = 2700000; break;
emilmont 10:3bc89ef62ce7 262 case 12: wdt_osc = 2900000; break;
emilmont 10:3bc89ef62ce7 263 case 13: wdt_osc = 3100000; break;
emilmont 10:3bc89ef62ce7 264 case 14: wdt_osc = 3200000; break;
emilmont 10:3bc89ef62ce7 265 case 15: wdt_osc = 3400000; break;
emilmont 10:3bc89ef62ce7 266 }
emilmont 10:3bc89ef62ce7 267 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
emilmont 10:3bc89ef62ce7 268
emilmont 10:3bc89ef62ce7 269 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
emilmont 10:3bc89ef62ce7 270 case 0: /* Internal RC oscillator */
emilmont 10:3bc89ef62ce7 271 SystemCoreClock = __IRC_OSC_CLK;
emilmont 10:3bc89ef62ce7 272 break;
emilmont 10:3bc89ef62ce7 273 case 1: /* Input Clock to System PLL */
emilmont 10:3bc89ef62ce7 274 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
emilmont 10:3bc89ef62ce7 275 case 0: /* Internal RC oscillator */
emilmont 10:3bc89ef62ce7 276 SystemCoreClock = __IRC_OSC_CLK;
emilmont 10:3bc89ef62ce7 277 break;
emilmont 10:3bc89ef62ce7 278 case 1: /* System oscillator */
emilmont 10:3bc89ef62ce7 279 SystemCoreClock = __SYS_OSC_CLK;
emilmont 10:3bc89ef62ce7 280 break;
emilmont 10:3bc89ef62ce7 281 case 2: /* Reserved */
emilmont 10:3bc89ef62ce7 282 SystemCoreClock = 0;
emilmont 10:3bc89ef62ce7 283 break;
emilmont 10:3bc89ef62ce7 284 case 3: /* CLKIN pin */
emilmont 10:3bc89ef62ce7 285 SystemCoreClock = __CLKIN_CLK;
emilmont 10:3bc89ef62ce7 286 break;
emilmont 10:3bc89ef62ce7 287 }
emilmont 10:3bc89ef62ce7 288 break;
emilmont 10:3bc89ef62ce7 289 case 2: /* WDT Oscillator */
emilmont 10:3bc89ef62ce7 290 SystemCoreClock = wdt_osc;
emilmont 10:3bc89ef62ce7 291 break;
emilmont 10:3bc89ef62ce7 292 case 3: /* System PLL Clock Out */
emilmont 10:3bc89ef62ce7 293 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
emilmont 10:3bc89ef62ce7 294 case 0: /* Internal RC oscillator */
emilmont 10:3bc89ef62ce7 295 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
emilmont 10:3bc89ef62ce7 296 break;
emilmont 10:3bc89ef62ce7 297 case 1: /* System oscillator */
emilmont 10:3bc89ef62ce7 298 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
emilmont 10:3bc89ef62ce7 299 break;
emilmont 10:3bc89ef62ce7 300 case 2: /* Reserved */
emilmont 10:3bc89ef62ce7 301 SystemCoreClock = 0;
emilmont 10:3bc89ef62ce7 302 break;
emilmont 10:3bc89ef62ce7 303 case 3: /* CLKIN pin */
emilmont 10:3bc89ef62ce7 304 SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
emilmont 10:3bc89ef62ce7 305 break;
emilmont 10:3bc89ef62ce7 306 }
emilmont 10:3bc89ef62ce7 307 break;
emilmont 10:3bc89ef62ce7 308 }
emilmont 10:3bc89ef62ce7 309
emilmont 10:3bc89ef62ce7 310 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
emilmont 10:3bc89ef62ce7 311
emilmont 10:3bc89ef62ce7 312 }
emilmont 10:3bc89ef62ce7 313
emilmont 10:3bc89ef62ce7 314 /**
emilmont 10:3bc89ef62ce7 315 * Initialize the system
emilmont 10:3bc89ef62ce7 316 *
emilmont 10:3bc89ef62ce7 317 * @param none
emilmont 10:3bc89ef62ce7 318 * @return none
emilmont 10:3bc89ef62ce7 319 *
emilmont 10:3bc89ef62ce7 320 * @brief Setup the microcontroller system.
emilmont 10:3bc89ef62ce7 321 * Initialize the System.
emilmont 10:3bc89ef62ce7 322 */
emilmont 10:3bc89ef62ce7 323 void SystemInit (void) {
emilmont 10:3bc89ef62ce7 324 volatile uint32_t i;
emilmont 10:3bc89ef62ce7 325
emilmont 10:3bc89ef62ce7 326 /* System clock to the IOCON & the SWM need to be enabled or
emilmont 10:3bc89ef62ce7 327 most of the I/O related peripherals won't work. */
emilmont 10:3bc89ef62ce7 328 LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
emilmont 10:3bc89ef62ce7 329
emilmont 10:3bc89ef62ce7 330 #if (CLOCK_SETUP) /* Clock Setup */
emilmont 10:3bc89ef62ce7 331
emilmont 10:3bc89ef62ce7 332 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
emilmont 10:3bc89ef62ce7 333 LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
emilmont 10:3bc89ef62ce7 334 LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
emilmont 10:3bc89ef62ce7 335 LPC_SWM->PINENABLE0 &= ~(0x3 << 4);
emilmont 10:3bc89ef62ce7 336 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
emilmont 10:3bc89ef62ce7 337 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
emilmont 10:3bc89ef62ce7 338 for (i = 0; i < 200; i++) __NOP();
emilmont 10:3bc89ef62ce7 339 #endif
emilmont 10:3bc89ef62ce7 340 #if ((SYSPLLCLKSEL_Val & 0x03) == 3)
emilmont 10:3bc89ef62ce7 341 LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
emilmont 10:3bc89ef62ce7 342 LPC_SWM->PINENABLE0 &= ~(0x1 << 7);
emilmont 10:3bc89ef62ce7 343 for (i = 0; i < 200; i++) __NOP();
emilmont 10:3bc89ef62ce7 344 #endif
emilmont 10:3bc89ef62ce7 345
emilmont 10:3bc89ef62ce7 346 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
emilmont 10:3bc89ef62ce7 347 LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
emilmont 10:3bc89ef62ce7 348 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
emilmont 10:3bc89ef62ce7 349 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
emilmont 10:3bc89ef62ce7 350 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
emilmont 10:3bc89ef62ce7 351 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
emilmont 10:3bc89ef62ce7 352 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
emilmont 10:3bc89ef62ce7 353 #endif
emilmont 10:3bc89ef62ce7 354
emilmont 10:3bc89ef62ce7 355 #if (((MAINCLKSEL_Val & 0x03) == 2) )
emilmont 10:3bc89ef62ce7 356 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
emilmont 10:3bc89ef62ce7 357 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
emilmont 10:3bc89ef62ce7 358 for (i = 0; i < 200; i++) __NOP();
emilmont 10:3bc89ef62ce7 359 #endif
emilmont 10:3bc89ef62ce7 360
emilmont 10:3bc89ef62ce7 361 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
emilmont 10:3bc89ef62ce7 362 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
emilmont 10:3bc89ef62ce7 363 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
emilmont 10:3bc89ef62ce7 364
emilmont 10:3bc89ef62ce7 365 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
emilmont 10:3bc89ef62ce7 366 #endif
emilmont 10:3bc89ef62ce7 367 }