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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC176X/system_LPC17xx.c@13:0645d8841f51, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 14:12:34 2013 +0300
Revision:
13:0645d8841f51
Parent:
vendor/NXP/LPC1768/cmsis/system_LPC17xx.c@10:3bc89ef62ce7 
Update mbed sources to revision 64

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /**************************************************************************//**
emilmont 10:3bc89ef62ce7 2 * @file system_LPC17xx.c
emilmont 10:3bc89ef62ce7 3 * @brief CMSIS Cortex-M3 Device System Source File for
emilmont 10:3bc89ef62ce7 4 * NXP LPC17xx Device Series
emilmont 10:3bc89ef62ce7 5 * @version V1.11
emilmont 10:3bc89ef62ce7 6 * @date 21. June 2011
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * @note
emilmont 10:3bc89ef62ce7 9 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 10 *
emilmont 10:3bc89ef62ce7 11 * @par
emilmont 10:3bc89ef62ce7 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 10:3bc89ef62ce7 13 * processor based microcontrollers. This file can be freely distributed
emilmont 10:3bc89ef62ce7 14 * within development tools that are supporting such ARM based processors.
emilmont 10:3bc89ef62ce7 15 *
emilmont 10:3bc89ef62ce7 16 * @par
emilmont 10:3bc89ef62ce7 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 10:3bc89ef62ce7 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 10:3bc89ef62ce7 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 10:3bc89ef62ce7 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 10:3bc89ef62ce7 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 10:3bc89ef62ce7 22 *
emilmont 10:3bc89ef62ce7 23 ******************************************************************************/
emilmont 10:3bc89ef62ce7 24
emilmont 10:3bc89ef62ce7 25
emilmont 10:3bc89ef62ce7 26 #include <stdint.h>
emilmont 10:3bc89ef62ce7 27 #include "LPC17xx.h"
emilmont 10:3bc89ef62ce7 28
emilmont 10:3bc89ef62ce7 29
emilmont 10:3bc89ef62ce7 30 /** @addtogroup LPC17xx_System
emilmont 10:3bc89ef62ce7 31 * @{
emilmont 10:3bc89ef62ce7 32 */
emilmont 10:3bc89ef62ce7 33
emilmont 10:3bc89ef62ce7 34 /*
emilmont 10:3bc89ef62ce7 35 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
emilmont 10:3bc89ef62ce7 36 */
emilmont 10:3bc89ef62ce7 37
emilmont 10:3bc89ef62ce7 38 /*--------------------- Clock Configuration ----------------------------------
emilmont 10:3bc89ef62ce7 39 //
emilmont 10:3bc89ef62ce7 40 // <e> Clock Configuration
emilmont 10:3bc89ef62ce7 41 // <h> System Controls and Status Register (SCS)
emilmont 10:3bc89ef62ce7 42 // <o1.4> OSCRANGE: Main Oscillator Range Select
emilmont 10:3bc89ef62ce7 43 // <0=> 1 MHz to 20 MHz
emilmont 10:3bc89ef62ce7 44 // <1=> 15 MHz to 25 MHz
emilmont 10:3bc89ef62ce7 45 // <e1.5> OSCEN: Main Oscillator Enable
emilmont 10:3bc89ef62ce7 46 // </e>
emilmont 10:3bc89ef62ce7 47 // </h>
emilmont 10:3bc89ef62ce7 48 //
emilmont 10:3bc89ef62ce7 49 // <h> Clock Source Select Register (CLKSRCSEL)
emilmont 10:3bc89ef62ce7 50 // <o2.0..1> CLKSRC: PLL Clock Source Selection
emilmont 10:3bc89ef62ce7 51 // <0=> Internal RC oscillator
emilmont 10:3bc89ef62ce7 52 // <1=> Main oscillator
emilmont 10:3bc89ef62ce7 53 // <2=> RTC oscillator
emilmont 10:3bc89ef62ce7 54 // </h>
emilmont 10:3bc89ef62ce7 55 //
emilmont 10:3bc89ef62ce7 56 // <e3> PLL0 Configuration (Main PLL)
emilmont 10:3bc89ef62ce7 57 // <h> PLL0 Configuration Register (PLL0CFG)
emilmont 10:3bc89ef62ce7 58 // <i> F_cco0 = (2 * M * F_in) / N
emilmont 10:3bc89ef62ce7 59 // <i> F_in must be in the range of 32 kHz to 50 MHz
emilmont 10:3bc89ef62ce7 60 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz
emilmont 10:3bc89ef62ce7 61 // <o4.0..14> MSEL: PLL Multiplier Selection
emilmont 10:3bc89ef62ce7 62 // <6-32768><#-1>
emilmont 10:3bc89ef62ce7 63 // <i> M Value
emilmont 10:3bc89ef62ce7 64 // <o4.16..23> NSEL: PLL Divider Selection
emilmont 10:3bc89ef62ce7 65 // <1-256><#-1>
emilmont 10:3bc89ef62ce7 66 // <i> N Value
emilmont 10:3bc89ef62ce7 67 // </h>
emilmont 10:3bc89ef62ce7 68 // </e>
emilmont 10:3bc89ef62ce7 69 //
emilmont 10:3bc89ef62ce7 70 // <e5> PLL1 Configuration (USB PLL)
emilmont 10:3bc89ef62ce7 71 // <h> PLL1 Configuration Register (PLL1CFG)
emilmont 10:3bc89ef62ce7 72 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
emilmont 10:3bc89ef62ce7 73 // <i> F_cco1 = F_osc * M * 2 * P
emilmont 10:3bc89ef62ce7 74 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz
emilmont 10:3bc89ef62ce7 75 // <o6.0..4> MSEL: PLL Multiplier Selection
emilmont 10:3bc89ef62ce7 76 // <1-32><#-1>
emilmont 10:3bc89ef62ce7 77 // <i> M Value (for USB maximum value is 4)
emilmont 10:3bc89ef62ce7 78 // <o6.5..6> PSEL: PLL Divider Selection
emilmont 10:3bc89ef62ce7 79 // <0=> 1
emilmont 10:3bc89ef62ce7 80 // <1=> 2
emilmont 10:3bc89ef62ce7 81 // <2=> 4
emilmont 10:3bc89ef62ce7 82 // <3=> 8
emilmont 10:3bc89ef62ce7 83 // <i> P Value
emilmont 10:3bc89ef62ce7 84 // </h>
emilmont 10:3bc89ef62ce7 85 // </e>
emilmont 10:3bc89ef62ce7 86 //
emilmont 10:3bc89ef62ce7 87 // <h> CPU Clock Configuration Register (CCLKCFG)
emilmont 10:3bc89ef62ce7 88 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
emilmont 10:3bc89ef62ce7 89 // <1-256><#-1>
emilmont 10:3bc89ef62ce7 90 // </h>
emilmont 10:3bc89ef62ce7 91 //
emilmont 10:3bc89ef62ce7 92 // <h> USB Clock Configuration Register (USBCLKCFG)
emilmont 10:3bc89ef62ce7 93 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
emilmont 10:3bc89ef62ce7 94 // <0-15>
emilmont 10:3bc89ef62ce7 95 // <i> Divide is USBSEL + 1
emilmont 10:3bc89ef62ce7 96 // </h>
emilmont 10:3bc89ef62ce7 97 //
emilmont 10:3bc89ef62ce7 98 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
emilmont 10:3bc89ef62ce7 99 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
emilmont 10:3bc89ef62ce7 100 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 101 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 102 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 103 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 104 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
emilmont 10:3bc89ef62ce7 105 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 106 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 107 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 108 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 109 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
emilmont 10:3bc89ef62ce7 110 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 111 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 112 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 113 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 114 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
emilmont 10:3bc89ef62ce7 115 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 116 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 117 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 118 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 119 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
emilmont 10:3bc89ef62ce7 120 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 121 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 122 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 123 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 124 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
emilmont 10:3bc89ef62ce7 125 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 126 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 127 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 128 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 129 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
emilmont 10:3bc89ef62ce7 130 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 131 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 132 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 133 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 134 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
emilmont 10:3bc89ef62ce7 135 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 136 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 137 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 138 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 139 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
emilmont 10:3bc89ef62ce7 140 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 141 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 142 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 143 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 144 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
emilmont 10:3bc89ef62ce7 145 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 146 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 147 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 148 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 149 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
emilmont 10:3bc89ef62ce7 150 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 151 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 152 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 153 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 154 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
emilmont 10:3bc89ef62ce7 155 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 156 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 157 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 158 // <3=> Pclk = Hclk / 6
emilmont 10:3bc89ef62ce7 159 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
emilmont 10:3bc89ef62ce7 160 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 161 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 162 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 163 // <3=> Pclk = Hclk / 6
emilmont 10:3bc89ef62ce7 164 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
emilmont 10:3bc89ef62ce7 165 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 166 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 167 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 168 // <3=> Pclk = Hclk / 6
emilmont 10:3bc89ef62ce7 169 // </h>
emilmont 10:3bc89ef62ce7 170 //
emilmont 10:3bc89ef62ce7 171 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
emilmont 10:3bc89ef62ce7 172 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
emilmont 10:3bc89ef62ce7 173 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 174 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 175 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 176 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 177 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
emilmont 10:3bc89ef62ce7 178 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 179 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 180 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 181 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 182 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
emilmont 10:3bc89ef62ce7 183 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 184 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 185 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 186 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 187 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
emilmont 10:3bc89ef62ce7 188 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 189 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 190 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 191 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 192 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
emilmont 10:3bc89ef62ce7 193 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 194 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 195 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 196 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 197 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
emilmont 10:3bc89ef62ce7 198 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 199 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 200 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 201 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 202 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
emilmont 10:3bc89ef62ce7 203 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 204 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 205 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 206 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 207 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
emilmont 10:3bc89ef62ce7 208 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 209 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 210 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 211 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 212 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
emilmont 10:3bc89ef62ce7 213 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 214 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 215 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 216 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 217 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
emilmont 10:3bc89ef62ce7 218 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 219 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 220 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 221 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 222 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
emilmont 10:3bc89ef62ce7 223 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 224 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 225 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 226 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 227 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
emilmont 10:3bc89ef62ce7 228 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 229 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 230 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 231 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 232 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
emilmont 10:3bc89ef62ce7 233 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 234 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 235 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 236 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 237 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
emilmont 10:3bc89ef62ce7 238 // <0=> Pclk = Cclk / 4
emilmont 10:3bc89ef62ce7 239 // <1=> Pclk = Cclk
emilmont 10:3bc89ef62ce7 240 // <2=> Pclk = Cclk / 2
emilmont 10:3bc89ef62ce7 241 // <3=> Pclk = Hclk / 8
emilmont 10:3bc89ef62ce7 242 // </h>
emilmont 10:3bc89ef62ce7 243 //
emilmont 10:3bc89ef62ce7 244 // <h> Power Control for Peripherals Register (PCONP)
emilmont 10:3bc89ef62ce7 245 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
emilmont 10:3bc89ef62ce7 246 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
emilmont 10:3bc89ef62ce7 247 // <o11.3> PCUART0: UART 0 power/clock enable
emilmont 10:3bc89ef62ce7 248 // <o11.4> PCUART1: UART 1 power/clock enable
emilmont 10:3bc89ef62ce7 249 // <o11.6> PCPWM1: PWM 1 power/clock enable
emilmont 10:3bc89ef62ce7 250 // <o11.7> PCI2C0: I2C interface 0 power/clock enable
emilmont 10:3bc89ef62ce7 251 // <o11.8> PCSPI: SPI interface power/clock enable
emilmont 10:3bc89ef62ce7 252 // <o11.9> PCRTC: RTC power/clock enable
emilmont 10:3bc89ef62ce7 253 // <o11.10> PCSSP1: SSP interface 1 power/clock enable
emilmont 10:3bc89ef62ce7 254 // <o11.12> PCAD: A/D converter power/clock enable
emilmont 10:3bc89ef62ce7 255 // <o11.13> PCCAN1: CAN controller 1 power/clock enable
emilmont 10:3bc89ef62ce7 256 // <o11.14> PCCAN2: CAN controller 2 power/clock enable
emilmont 10:3bc89ef62ce7 257 // <o11.15> PCGPIO: GPIOs power/clock enable
emilmont 10:3bc89ef62ce7 258 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
emilmont 10:3bc89ef62ce7 259 // <o11.17> PCMC: Motor control PWM power/clock enable
emilmont 10:3bc89ef62ce7 260 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable
emilmont 10:3bc89ef62ce7 261 // <o11.19> PCI2C1: I2C interface 1 power/clock enable
emilmont 10:3bc89ef62ce7 262 // <o11.21> PCSSP0: SSP interface 0 power/clock enable
emilmont 10:3bc89ef62ce7 263 // <o11.22> PCTIM2: Timer 2 power/clock enable
emilmont 10:3bc89ef62ce7 264 // <o11.23> PCTIM3: Timer 3 power/clock enable
emilmont 10:3bc89ef62ce7 265 // <o11.24> PCUART2: UART 2 power/clock enable
emilmont 10:3bc89ef62ce7 266 // <o11.25> PCUART3: UART 3 power/clock enable
emilmont 10:3bc89ef62ce7 267 // <o11.26> PCI2C2: I2C interface 2 power/clock enable
emilmont 10:3bc89ef62ce7 268 // <o11.27> PCI2S: I2S interface power/clock enable
emilmont 10:3bc89ef62ce7 269 // <o11.29> PCGPDMA: GP DMA function power/clock enable
emilmont 10:3bc89ef62ce7 270 // <o11.30> PCENET: Ethernet block power/clock enable
emilmont 10:3bc89ef62ce7 271 // <o11.31> PCUSB: USB interface power/clock enable
emilmont 10:3bc89ef62ce7 272 // </h>
emilmont 10:3bc89ef62ce7 273 //
emilmont 10:3bc89ef62ce7 274 // <h> Clock Output Configuration Register (CLKOUTCFG)
emilmont 10:3bc89ef62ce7 275 // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
emilmont 10:3bc89ef62ce7 276 // <0=> CPU clock
emilmont 10:3bc89ef62ce7 277 // <1=> Main oscillator
emilmont 10:3bc89ef62ce7 278 // <2=> Internal RC oscillator
emilmont 10:3bc89ef62ce7 279 // <3=> USB clock
emilmont 10:3bc89ef62ce7 280 // <4=> RTC oscillator
emilmont 10:3bc89ef62ce7 281 // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
emilmont 10:3bc89ef62ce7 282 // <1-16><#-1>
emilmont 10:3bc89ef62ce7 283 // <o12.8> CLKOUT_EN: CLKOUT enable control
emilmont 10:3bc89ef62ce7 284 // </h>
emilmont 10:3bc89ef62ce7 285 //
emilmont 10:3bc89ef62ce7 286 // </e>
emilmont 10:3bc89ef62ce7 287 */
emilmont 10:3bc89ef62ce7 288
emilmont 10:3bc89ef62ce7 289
emilmont 10:3bc89ef62ce7 290
emilmont 10:3bc89ef62ce7 291 /** @addtogroup LPC17xx_System_Defines LPC17xx System Defines
emilmont 10:3bc89ef62ce7 292 @{
emilmont 10:3bc89ef62ce7 293 */
emilmont 10:3bc89ef62ce7 294
emilmont 10:3bc89ef62ce7 295 #define CLOCK_SETUP 1
emilmont 10:3bc89ef62ce7 296 #define SCS_Val 0x00000020
emilmont 10:3bc89ef62ce7 297 #define CLKSRCSEL_Val 0x00000001
emilmont 10:3bc89ef62ce7 298 #define PLL0_SETUP 1
emilmont 10:3bc89ef62ce7 299
emilmont 10:3bc89ef62ce7 300 #ifdef MCB1700
emilmont 10:3bc89ef62ce7 301 # define PLL0CFG_Val 0x00050063
emilmont 10:3bc89ef62ce7 302 # define PLL1_SETUP 1
emilmont 10:3bc89ef62ce7 303 # define PLL1CFG_Val 0x00000023
emilmont 10:3bc89ef62ce7 304 # define CCLKCFG_Val 0x00000003
emilmont 10:3bc89ef62ce7 305 # define USBCLKCFG_Val 0x00000000
emilmont 10:3bc89ef62ce7 306 #else
emilmont 10:3bc89ef62ce7 307 # define PLL0CFG_Val 0x0000000B
emilmont 10:3bc89ef62ce7 308 # define PLL1_SETUP 0
emilmont 10:3bc89ef62ce7 309 # define PLL1CFG_Val 0x00000000
emilmont 10:3bc89ef62ce7 310 # define CCLKCFG_Val 0x00000002
emilmont 10:3bc89ef62ce7 311 # define USBCLKCFG_Val 0x00000005
emilmont 10:3bc89ef62ce7 312 #endif
emilmont 10:3bc89ef62ce7 313
emilmont 10:3bc89ef62ce7 314 #define PCLKSEL0_Val 0x00000000
emilmont 10:3bc89ef62ce7 315 #define PCLKSEL1_Val 0x00000000
emilmont 10:3bc89ef62ce7 316 #define PCONP_Val 0x042887DE
emilmont 10:3bc89ef62ce7 317 #define CLKOUTCFG_Val 0x00000000
emilmont 10:3bc89ef62ce7 318
emilmont 10:3bc89ef62ce7 319
emilmont 10:3bc89ef62ce7 320 /*--------------------- Flash Accelerator Configuration ----------------------
emilmont 10:3bc89ef62ce7 321 //
emilmont 10:3bc89ef62ce7 322 // <e> Flash Accelerator Configuration
emilmont 10:3bc89ef62ce7 323 // <o1.12..15> FLASHTIM: Flash Access Time
emilmont 10:3bc89ef62ce7 324 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
emilmont 10:3bc89ef62ce7 325 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
emilmont 10:3bc89ef62ce7 326 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
emilmont 10:3bc89ef62ce7 327 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
emilmont 10:3bc89ef62ce7 328 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
emilmont 10:3bc89ef62ce7 329 // <5=> 6 CPU clocks (for any CPU clock)
emilmont 10:3bc89ef62ce7 330 // </e>
emilmont 10:3bc89ef62ce7 331 */
emilmont 10:3bc89ef62ce7 332 #define FLASH_SETUP 1
emilmont 10:3bc89ef62ce7 333 #define FLASHCFG_Val 0x0000303A
emilmont 10:3bc89ef62ce7 334
emilmont 10:3bc89ef62ce7 335 /*
emilmont 10:3bc89ef62ce7 336 //-------- <<< end of configuration section >>> ------------------------------
emilmont 10:3bc89ef62ce7 337 */
emilmont 10:3bc89ef62ce7 338
emilmont 10:3bc89ef62ce7 339 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 340 Check the register settings
emilmont 10:3bc89ef62ce7 341 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 342 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
emilmont 10:3bc89ef62ce7 343 #define CHECK_RSVD(val, mask) (val & mask)
emilmont 10:3bc89ef62ce7 344
emilmont 10:3bc89ef62ce7 345 /* Clock Configuration -------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 346 #if (CHECK_RSVD((SCS_Val), ~0x00000030))
emilmont 10:3bc89ef62ce7 347 #error "SCS: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 348 #endif
emilmont 10:3bc89ef62ce7 349
emilmont 10:3bc89ef62ce7 350 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
emilmont 10:3bc89ef62ce7 351 #error "CLKSRCSEL: Value out of range!"
emilmont 10:3bc89ef62ce7 352 #endif
emilmont 10:3bc89ef62ce7 353
emilmont 10:3bc89ef62ce7 354 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
emilmont 10:3bc89ef62ce7 355 #error "PLL0CFG: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 356 #endif
emilmont 10:3bc89ef62ce7 357
emilmont 10:3bc89ef62ce7 358 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
emilmont 10:3bc89ef62ce7 359 #error "PLL1CFG: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 360 #endif
emilmont 10:3bc89ef62ce7 361
emilmont 10:3bc89ef62ce7 362 #if (PLL0_SETUP) /* if PLL0 is used */
emilmont 10:3bc89ef62ce7 363 #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */
emilmont 10:3bc89ef62ce7 364 #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
emilmont 10:3bc89ef62ce7 365 #endif
emilmont 10:3bc89ef62ce7 366 #endif
emilmont 10:3bc89ef62ce7 367
emilmont 10:3bc89ef62ce7 368 #if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
emilmont 10:3bc89ef62ce7 369 #error "CCLKCFG: Value out of range!"
emilmont 10:3bc89ef62ce7 370 #endif
emilmont 10:3bc89ef62ce7 371
emilmont 10:3bc89ef62ce7 372 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
emilmont 10:3bc89ef62ce7 373 #error "USBCLKCFG: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 374 #endif
emilmont 10:3bc89ef62ce7 375
emilmont 10:3bc89ef62ce7 376 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
emilmont 10:3bc89ef62ce7 377 #error "PCLKSEL0: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 378 #endif
emilmont 10:3bc89ef62ce7 379
emilmont 10:3bc89ef62ce7 380 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
emilmont 10:3bc89ef62ce7 381 #error "PCLKSEL1: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 382 #endif
emilmont 10:3bc89ef62ce7 383
emilmont 10:3bc89ef62ce7 384 #if (CHECK_RSVD((PCONP_Val), 0x10100821))
emilmont 10:3bc89ef62ce7 385 #error "PCONP: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 386 #endif
emilmont 10:3bc89ef62ce7 387
emilmont 10:3bc89ef62ce7 388 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
emilmont 10:3bc89ef62ce7 389 #error "CLKOUTCFG: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 390 #endif
emilmont 10:3bc89ef62ce7 391
emilmont 10:3bc89ef62ce7 392 /* Flash Accelerator Configuration -------------------------------------------*/
emilmont 10:3bc89ef62ce7 393 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
emilmont 10:3bc89ef62ce7 394 #error "FLASHCFG: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 395 #endif
emilmont 10:3bc89ef62ce7 396
emilmont 10:3bc89ef62ce7 397
emilmont 10:3bc89ef62ce7 398 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 399 DEFINES
emilmont 10:3bc89ef62ce7 400 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 401
emilmont 10:3bc89ef62ce7 402 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 403 Define clocks
emilmont 10:3bc89ef62ce7 404 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 405 #define XTAL (12000000UL) /* Oscillator frequency */
emilmont 10:3bc89ef62ce7 406 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
emilmont 10:3bc89ef62ce7 407 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
emilmont 10:3bc89ef62ce7 408 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
emilmont 10:3bc89ef62ce7 409
emilmont 10:3bc89ef62ce7 410
emilmont 10:3bc89ef62ce7 411 /* F_cco0 = (2 * M * F_in) / N */
emilmont 10:3bc89ef62ce7 412 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
emilmont 10:3bc89ef62ce7 413 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
emilmont 10:3bc89ef62ce7 414 #define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
emilmont 10:3bc89ef62ce7 415 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
emilmont 10:3bc89ef62ce7 416
emilmont 10:3bc89ef62ce7 417 /* Determine core clock frequency according to settings */
emilmont 10:3bc89ef62ce7 418 #if (PLL0_SETUP)
emilmont 10:3bc89ef62ce7 419 #if ((CLKSRCSEL_Val & 0x03) == 1)
emilmont 10:3bc89ef62ce7 420 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
emilmont 10:3bc89ef62ce7 421 #elif ((CLKSRCSEL_Val & 0x03) == 2)
emilmont 10:3bc89ef62ce7 422 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
emilmont 10:3bc89ef62ce7 423 #else
emilmont 10:3bc89ef62ce7 424 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
emilmont 10:3bc89ef62ce7 425 #endif
emilmont 10:3bc89ef62ce7 426 #else
emilmont 10:3bc89ef62ce7 427 #if ((CLKSRCSEL_Val & 0x03) == 1)
emilmont 10:3bc89ef62ce7 428 #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
emilmont 10:3bc89ef62ce7 429 #elif ((CLKSRCSEL_Val & 0x03) == 2)
emilmont 10:3bc89ef62ce7 430 #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
emilmont 10:3bc89ef62ce7 431 #else
emilmont 10:3bc89ef62ce7 432 #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
emilmont 10:3bc89ef62ce7 433 #endif
emilmont 10:3bc89ef62ce7 434 #endif
emilmont 10:3bc89ef62ce7 435
emilmont 10:3bc89ef62ce7 436 /**
emilmont 10:3bc89ef62ce7 437 * @}
emilmont 10:3bc89ef62ce7 438 */
emilmont 10:3bc89ef62ce7 439
emilmont 10:3bc89ef62ce7 440
emilmont 10:3bc89ef62ce7 441 /** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables
emilmont 10:3bc89ef62ce7 442 @{
emilmont 10:3bc89ef62ce7 443 */
emilmont 10:3bc89ef62ce7 444 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 445 Clock Variable definitions
emilmont 10:3bc89ef62ce7 446 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 447 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
emilmont 10:3bc89ef62ce7 448
emilmont 10:3bc89ef62ce7 449 /**
emilmont 10:3bc89ef62ce7 450 * @}
emilmont 10:3bc89ef62ce7 451 */
emilmont 10:3bc89ef62ce7 452
emilmont 10:3bc89ef62ce7 453
emilmont 10:3bc89ef62ce7 454 /** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions
emilmont 10:3bc89ef62ce7 455 @{
emilmont 10:3bc89ef62ce7 456 */
emilmont 10:3bc89ef62ce7 457
emilmont 10:3bc89ef62ce7 458 /**
emilmont 10:3bc89ef62ce7 459 * Update SystemCoreClock variable
emilmont 10:3bc89ef62ce7 460 *
emilmont 10:3bc89ef62ce7 461 * @param none
emilmont 10:3bc89ef62ce7 462 * @return none
emilmont 10:3bc89ef62ce7 463 *
emilmont 10:3bc89ef62ce7 464 * @brief Updates the SystemCoreClock with current core Clock
emilmont 10:3bc89ef62ce7 465 * retrieved from cpu registers.
emilmont 10:3bc89ef62ce7 466 */void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
emilmont 10:3bc89ef62ce7 467 {
emilmont 10:3bc89ef62ce7 468 /* Determine clock frequency according to clock register values */
emilmont 10:3bc89ef62ce7 469 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
emilmont 10:3bc89ef62ce7 470 switch (LPC_SC->CLKSRCSEL & 0x03) {
emilmont 10:3bc89ef62ce7 471 case 0: /* Int. RC oscillator => PLL0 */
emilmont 10:3bc89ef62ce7 472 case 3: /* Reserved, default to Int. RC */
emilmont 10:3bc89ef62ce7 473 SystemCoreClock = (IRC_OSC *
emilmont 10:3bc89ef62ce7 474 ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
emilmont 10:3bc89ef62ce7 475 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
emilmont 10:3bc89ef62ce7 476 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
emilmont 10:3bc89ef62ce7 477 break;
emilmont 10:3bc89ef62ce7 478 case 1: /* Main oscillator => PLL0 */
emilmont 10:3bc89ef62ce7 479 SystemCoreClock = (OSC_CLK *
emilmont 10:3bc89ef62ce7 480 ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
emilmont 10:3bc89ef62ce7 481 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
emilmont 10:3bc89ef62ce7 482 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
emilmont 10:3bc89ef62ce7 483 break;
emilmont 10:3bc89ef62ce7 484 case 2: /* RTC oscillator => PLL0 */
emilmont 10:3bc89ef62ce7 485 SystemCoreClock = (RTC_CLK *
emilmont 10:3bc89ef62ce7 486 ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
emilmont 10:3bc89ef62ce7 487 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
emilmont 10:3bc89ef62ce7 488 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
emilmont 10:3bc89ef62ce7 489 break;
emilmont 10:3bc89ef62ce7 490 }
emilmont 10:3bc89ef62ce7 491 } else {
emilmont 10:3bc89ef62ce7 492 switch (LPC_SC->CLKSRCSEL & 0x03) {
emilmont 10:3bc89ef62ce7 493 case 0: /* Int. RC oscillator => PLL0 */
emilmont 10:3bc89ef62ce7 494 case 3: /* Reserved, default to Int. RC */
emilmont 10:3bc89ef62ce7 495 SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
emilmont 10:3bc89ef62ce7 496 break;
emilmont 10:3bc89ef62ce7 497 case 1: /* Main oscillator => PLL0 */
emilmont 10:3bc89ef62ce7 498 SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
emilmont 10:3bc89ef62ce7 499 break;
emilmont 10:3bc89ef62ce7 500 case 2: /* RTC oscillator => PLL0 */
emilmont 10:3bc89ef62ce7 501 SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
emilmont 10:3bc89ef62ce7 502 break;
emilmont 10:3bc89ef62ce7 503 }
emilmont 10:3bc89ef62ce7 504 }
emilmont 10:3bc89ef62ce7 505
emilmont 10:3bc89ef62ce7 506 }
emilmont 10:3bc89ef62ce7 507
emilmont 10:3bc89ef62ce7 508 /**
emilmont 10:3bc89ef62ce7 509 * Initialize the system
emilmont 10:3bc89ef62ce7 510 *
emilmont 10:3bc89ef62ce7 511 * @param none
emilmont 10:3bc89ef62ce7 512 * @return none
emilmont 10:3bc89ef62ce7 513 *
emilmont 10:3bc89ef62ce7 514 * @brief Setup the microcontroller system.
emilmont 10:3bc89ef62ce7 515 * Initialize the System.
emilmont 10:3bc89ef62ce7 516 */
emilmont 10:3bc89ef62ce7 517 void SystemInit (void)
emilmont 10:3bc89ef62ce7 518 {
emilmont 10:3bc89ef62ce7 519 #if (CLOCK_SETUP) /* Clock Setup */
emilmont 10:3bc89ef62ce7 520 LPC_SC->SCS = SCS_Val;
emilmont 10:3bc89ef62ce7 521 if (LPC_SC->SCS & (1 << 5)) { /* If Main Oscillator is enabled */
emilmont 10:3bc89ef62ce7 522 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
emilmont 10:3bc89ef62ce7 523 }
emilmont 10:3bc89ef62ce7 524
emilmont 10:3bc89ef62ce7 525 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
emilmont 10:3bc89ef62ce7 526 /* Periphral clock must be selected before PLL0 enabling and connecting
emilmont 10:3bc89ef62ce7 527 * - according errata.lpc1768-16.March.2010 -
emilmont 10:3bc89ef62ce7 528 */
emilmont 10:3bc89ef62ce7 529 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
emilmont 10:3bc89ef62ce7 530 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
emilmont 10:3bc89ef62ce7 531
emilmont 10:3bc89ef62ce7 532 #if (PLL0_SETUP)
emilmont 10:3bc89ef62ce7 533 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
emilmont 10:3bc89ef62ce7 534
emilmont 10:3bc89ef62ce7 535 LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
emilmont 10:3bc89ef62ce7 536 LPC_SC->PLL0FEED = 0xAA;
emilmont 10:3bc89ef62ce7 537 LPC_SC->PLL0FEED = 0x55;
emilmont 10:3bc89ef62ce7 538
emilmont 10:3bc89ef62ce7 539 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
emilmont 10:3bc89ef62ce7 540 LPC_SC->PLL0FEED = 0xAA;
emilmont 10:3bc89ef62ce7 541 LPC_SC->PLL0FEED = 0x55;
emilmont 10:3bc89ef62ce7 542 while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
emilmont 10:3bc89ef62ce7 543
emilmont 10:3bc89ef62ce7 544 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
emilmont 10:3bc89ef62ce7 545 LPC_SC->PLL0FEED = 0xAA;
emilmont 10:3bc89ef62ce7 546 LPC_SC->PLL0FEED = 0x55;
emilmont 10:3bc89ef62ce7 547 while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
emilmont 10:3bc89ef62ce7 548 #endif
emilmont 10:3bc89ef62ce7 549
emilmont 10:3bc89ef62ce7 550 #if (PLL1_SETUP)
emilmont 10:3bc89ef62ce7 551 LPC_SC->PLL1CFG = PLL1CFG_Val;
emilmont 10:3bc89ef62ce7 552 LPC_SC->PLL1FEED = 0xAA;
emilmont 10:3bc89ef62ce7 553 LPC_SC->PLL1FEED = 0x55;
emilmont 10:3bc89ef62ce7 554
emilmont 10:3bc89ef62ce7 555 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
emilmont 10:3bc89ef62ce7 556 LPC_SC->PLL1FEED = 0xAA;
emilmont 10:3bc89ef62ce7 557 LPC_SC->PLL1FEED = 0x55;
emilmont 10:3bc89ef62ce7 558 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
emilmont 10:3bc89ef62ce7 559
emilmont 10:3bc89ef62ce7 560 LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
emilmont 10:3bc89ef62ce7 561 LPC_SC->PLL1FEED = 0xAA;
emilmont 10:3bc89ef62ce7 562 LPC_SC->PLL1FEED = 0x55;
emilmont 10:3bc89ef62ce7 563 while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
emilmont 10:3bc89ef62ce7 564 #else
emilmont 10:3bc89ef62ce7 565 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
emilmont 10:3bc89ef62ce7 566 #endif
emilmont 10:3bc89ef62ce7 567
emilmont 10:3bc89ef62ce7 568 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
emilmont 10:3bc89ef62ce7 569
emilmont 10:3bc89ef62ce7 570 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
emilmont 10:3bc89ef62ce7 571 #endif
emilmont 10:3bc89ef62ce7 572
emilmont 10:3bc89ef62ce7 573 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
emilmont 10:3bc89ef62ce7 574 LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
emilmont 10:3bc89ef62ce7 575 #endif
emilmont 10:3bc89ef62ce7 576 }
emilmont 10:3bc89ef62ce7 577
emilmont 10:3bc89ef62ce7 578 /**
emilmont 10:3bc89ef62ce7 579 * @}
emilmont 10:3bc89ef62ce7 580 */
emilmont 10:3bc89ef62ce7 581
emilmont 10:3bc89ef62ce7 582 /**
emilmont 10:3bc89ef62ce7 583 * @}
emilmont 10:3bc89ef62ce7 584 */