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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h@13:0645d8841f51, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 14:12:34 2013 +0300
Revision:
13:0645d8841f51
Parent:
vendor/NXP/LPC812/cmsis/LPC8xx.h@10:3bc89ef62ce7 
Update mbed sources to revision 64

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /****************************************************************************
emilmont 10:3bc89ef62ce7 2 * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
emilmont 10:3bc89ef62ce7 3 * Project: NXP LPC8xx software example
emilmont 10:3bc89ef62ce7 4 *
emilmont 10:3bc89ef62ce7 5 * Description:
emilmont 10:3bc89ef62ce7 6 * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
emilmont 10:3bc89ef62ce7 7 * NXP LPC800 Device Series
emilmont 10:3bc89ef62ce7 8 *
emilmont 10:3bc89ef62ce7 9 ****************************************************************************
emilmont 10:3bc89ef62ce7 10 * Software that is described herein is for illustrative purposes only
emilmont 10:3bc89ef62ce7 11 * which provides customers with programming information regarding the
emilmont 10:3bc89ef62ce7 12 * products. This software is supplied "AS IS" without any warranties.
emilmont 10:3bc89ef62ce7 13 * NXP Semiconductors assumes no responsibility or liability for the
emilmont 10:3bc89ef62ce7 14 * use of the software, conveys no license or title under any patent,
emilmont 10:3bc89ef62ce7 15 * copyright, or mask work right to the product. NXP Semiconductors
emilmont 10:3bc89ef62ce7 16 * reserves the right to make changes in the software without
emilmont 10:3bc89ef62ce7 17 * notification. NXP Semiconductors also make no representation or
emilmont 10:3bc89ef62ce7 18 * warranty that such application will be suitable for the specified
emilmont 10:3bc89ef62ce7 19 * use without further testing or modification.
emilmont 10:3bc89ef62ce7 20
emilmont 10:3bc89ef62ce7 21 * Permission to use, copy, modify, and distribute this software and its
emilmont 10:3bc89ef62ce7 22 * documentation is hereby granted, under NXP Semiconductors'
emilmont 10:3bc89ef62ce7 23 * relevant copyright in the software, without fee, provided that it
emilmont 10:3bc89ef62ce7 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
emilmont 10:3bc89ef62ce7 25 * copyright, permission, and disclaimer notice must appear in all copies of
emilmont 10:3bc89ef62ce7 26 * this code.
emilmont 10:3bc89ef62ce7 27 ****************************************************************************/
emilmont 10:3bc89ef62ce7 28 #ifndef __LPC8xx_H__
emilmont 10:3bc89ef62ce7 29 #define __LPC8xx_H__
emilmont 10:3bc89ef62ce7 30
emilmont 10:3bc89ef62ce7 31 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 32 extern "C" {
emilmont 10:3bc89ef62ce7 33 #endif
emilmont 10:3bc89ef62ce7 34
emilmont 10:3bc89ef62ce7 35 /** @addtogroup LPC8xx_Definitions LPC8xx Definitions
emilmont 10:3bc89ef62ce7 36 This file defines all structures and symbols for LPC8xx:
emilmont 10:3bc89ef62ce7 37 - Registers and bitfields
emilmont 10:3bc89ef62ce7 38 - peripheral base address
emilmont 10:3bc89ef62ce7 39 - PIO definitions
emilmont 10:3bc89ef62ce7 40 @{
emilmont 10:3bc89ef62ce7 41 */
emilmont 10:3bc89ef62ce7 42
emilmont 10:3bc89ef62ce7 43
emilmont 10:3bc89ef62ce7 44 /******************************************************************************/
emilmont 10:3bc89ef62ce7 45 /* Processor and Core Peripherals */
emilmont 10:3bc89ef62ce7 46 /******************************************************************************/
emilmont 10:3bc89ef62ce7 47 /** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
emilmont 10:3bc89ef62ce7 48 Configuration of the Cortex-M0+ Processor and Core Peripherals
emilmont 10:3bc89ef62ce7 49 @{
emilmont 10:3bc89ef62ce7 50 */
emilmont 10:3bc89ef62ce7 51
emilmont 10:3bc89ef62ce7 52 /*
emilmont 10:3bc89ef62ce7 53 * ==========================================================================
emilmont 10:3bc89ef62ce7 54 * ---------- Interrupt Number Definition -----------------------------------
emilmont 10:3bc89ef62ce7 55 * ==========================================================================
emilmont 10:3bc89ef62ce7 56 */
emilmont 10:3bc89ef62ce7 57 typedef enum IRQn
emilmont 10:3bc89ef62ce7 58 {
emilmont 10:3bc89ef62ce7 59 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
emilmont 10:3bc89ef62ce7 60 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
emilmont 10:3bc89ef62ce7 61 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
emilmont 10:3bc89ef62ce7 62 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
emilmont 10:3bc89ef62ce7 63 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
emilmont 10:3bc89ef62ce7 64 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
emilmont 10:3bc89ef62ce7 65 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
emilmont 10:3bc89ef62ce7 66
emilmont 10:3bc89ef62ce7 67 /****** LPC8xx Specific Interrupt Numbers ********************************************************/
emilmont 10:3bc89ef62ce7 68 SPI0_IRQn = 0, /*!< SPI0 */
emilmont 10:3bc89ef62ce7 69 SPI1_IRQn = 1, /*!< SPI1 */
emilmont 10:3bc89ef62ce7 70 Reserved0_IRQn = 2, /*!< Reserved Interrupt */
emilmont 10:3bc89ef62ce7 71 UART0_IRQn = 3, /*!< USART0 */
emilmont 10:3bc89ef62ce7 72 UART1_IRQn = 4, /*!< USART1 */
emilmont 10:3bc89ef62ce7 73 UART2_IRQn = 5, /*!< USART2 */
emilmont 10:3bc89ef62ce7 74 Reserved1_IRQn = 6, /*!< Reserved Interrupt */
emilmont 10:3bc89ef62ce7 75 Reserved2_IRQn = 7, /*!< Reserved Interrupt */
emilmont 10:3bc89ef62ce7 76 I2C_IRQn = 8, /*!< I2C */
emilmont 10:3bc89ef62ce7 77 SCT_IRQn = 9, /*!< SCT */
emilmont 10:3bc89ef62ce7 78 MRT_IRQn = 10, /*!< MRT */
emilmont 10:3bc89ef62ce7 79 CMP_IRQn = 11, /*!< CMP */
emilmont 10:3bc89ef62ce7 80 WDT_IRQn = 12, /*!< WDT */
emilmont 10:3bc89ef62ce7 81 BOD_IRQn = 13, /*!< BOD */
emilmont 10:3bc89ef62ce7 82 Reserved3_IRQn = 14, /*!< Reserved Interrupt */
emilmont 10:3bc89ef62ce7 83 WKT_IRQn = 15, /*!< WKT Interrupt */
emilmont 10:3bc89ef62ce7 84 Reserved4_IRQn = 16, /*!< Reserved Interrupt */
emilmont 10:3bc89ef62ce7 85 Reserved5_IRQn = 17, /*!< Reserved Interrupt */
emilmont 10:3bc89ef62ce7 86 Reserved6_IRQn = 18, /*!< Reserved Interrupt */
emilmont 10:3bc89ef62ce7 87 Reserved7_IRQn = 19, /*!< Reserved Interrupt */
emilmont 10:3bc89ef62ce7 88 Reserved8_IRQn = 20, /*!< Reserved Interrupt */
emilmont 10:3bc89ef62ce7 89 Reserved9_IRQn = 21, /*!< Reserved Interrupt */
emilmont 10:3bc89ef62ce7 90 Reserved10_IRQn = 22, /*!< Reserved Interrupt */
emilmont 10:3bc89ef62ce7 91 Reserved11_IRQn = 23, /*!< Reserved Interrupt */
emilmont 10:3bc89ef62ce7 92 PININT0_IRQn = 24, /*!< External Interrupt 0 */
emilmont 10:3bc89ef62ce7 93 PININT1_IRQn = 25, /*!< External Interrupt 1 */
emilmont 10:3bc89ef62ce7 94 PININT2_IRQn = 26, /*!< External Interrupt 2 */
emilmont 10:3bc89ef62ce7 95 PININT3_IRQn = 27, /*!< External Interrupt 3 */
emilmont 10:3bc89ef62ce7 96 PININT4_IRQn = 28, /*!< External Interrupt 4 */
emilmont 10:3bc89ef62ce7 97 PININT5_IRQn = 29, /*!< External Interrupt 5 */
emilmont 10:3bc89ef62ce7 98 PININT6_IRQn = 30, /*!< External Interrupt 6 */
emilmont 10:3bc89ef62ce7 99 PININT7_IRQn = 31, /*!< External Interrupt 7 */
emilmont 10:3bc89ef62ce7 100 } IRQn_Type;
emilmont 10:3bc89ef62ce7 101
emilmont 10:3bc89ef62ce7 102 /*
emilmont 10:3bc89ef62ce7 103 * ==========================================================================
emilmont 10:3bc89ef62ce7 104 * ----------- Processor and Core Peripheral Section ------------------------
emilmont 10:3bc89ef62ce7 105 * ==========================================================================
emilmont 10:3bc89ef62ce7 106 */
emilmont 10:3bc89ef62ce7 107
emilmont 10:3bc89ef62ce7 108 /* Configuration of the Cortex-M0+ Processor and Core Peripherals */
emilmont 10:3bc89ef62ce7 109 #define __MPU_PRESENT 0 /*!< MPU present or not */
emilmont 10:3bc89ef62ce7 110 #define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */
emilmont 10:3bc89ef62ce7 111 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
emilmont 10:3bc89ef62ce7 112 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
emilmont 10:3bc89ef62ce7 113
emilmont 10:3bc89ef62ce7 114 /*@}*/ /* end of group LPC8xx_CMSIS */
emilmont 10:3bc89ef62ce7 115
emilmont 10:3bc89ef62ce7 116
emilmont 10:3bc89ef62ce7 117 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
emilmont 10:3bc89ef62ce7 118 #include "system_LPC8xx.h" /* System Header */
emilmont 10:3bc89ef62ce7 119
emilmont 10:3bc89ef62ce7 120
emilmont 10:3bc89ef62ce7 121 /******************************************************************************/
emilmont 10:3bc89ef62ce7 122 /* Device Specific Peripheral Registers structures */
emilmont 10:3bc89ef62ce7 123 /******************************************************************************/
emilmont 10:3bc89ef62ce7 124
emilmont 10:3bc89ef62ce7 125 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 126 #pragma anon_unions
emilmont 10:3bc89ef62ce7 127 #endif
emilmont 10:3bc89ef62ce7 128
emilmont 10:3bc89ef62ce7 129 /*------------- System Control (SYSCON) --------------------------------------*/
emilmont 10:3bc89ef62ce7 130 /** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
emilmont 10:3bc89ef62ce7 131 @{
emilmont 10:3bc89ef62ce7 132 */
emilmont 10:3bc89ef62ce7 133 typedef struct
emilmont 10:3bc89ef62ce7 134 {
emilmont 10:3bc89ef62ce7 135 __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
emilmont 10:3bc89ef62ce7 136 __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
emilmont 10:3bc89ef62ce7 137 __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
emilmont 10:3bc89ef62ce7 138 __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */
emilmont 10:3bc89ef62ce7 139 uint32_t RESERVED0[4];
emilmont 10:3bc89ef62ce7 140
emilmont 10:3bc89ef62ce7 141 __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
emilmont 10:3bc89ef62ce7 142 __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
emilmont 10:3bc89ef62ce7 143 uint32_t RESERVED1[2];
emilmont 10:3bc89ef62ce7 144 __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */
emilmont 10:3bc89ef62ce7 145 uint32_t RESERVED2[3];
emilmont 10:3bc89ef62ce7 146 __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
emilmont 10:3bc89ef62ce7 147 __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
emilmont 10:3bc89ef62ce7 148 uint32_t RESERVED3[10];
emilmont 10:3bc89ef62ce7 149
emilmont 10:3bc89ef62ce7 150 __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
emilmont 10:3bc89ef62ce7 151 __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
emilmont 10:3bc89ef62ce7 152 __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
emilmont 10:3bc89ef62ce7 153 uint32_t RESERVED4[1];
emilmont 10:3bc89ef62ce7 154
emilmont 10:3bc89ef62ce7 155 __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
emilmont 10:3bc89ef62ce7 156 uint32_t RESERVED5[4];
emilmont 10:3bc89ef62ce7 157 __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */
emilmont 10:3bc89ef62ce7 158 uint32_t RESERVED6[18];
emilmont 10:3bc89ef62ce7 159
emilmont 10:3bc89ef62ce7 160 __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
emilmont 10:3bc89ef62ce7 161 __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
emilmont 10:3bc89ef62ce7 162 __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
emilmont 10:3bc89ef62ce7 163 uint32_t RESERVED7;
emilmont 10:3bc89ef62ce7 164 __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
emilmont 10:3bc89ef62ce7 165 __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
emilmont 10:3bc89ef62ce7 166 uint32_t RESERVED8[1];
emilmont 10:3bc89ef62ce7 167 __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
emilmont 10:3bc89ef62ce7 168 __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
emilmont 10:3bc89ef62ce7 169 uint32_t RESERVED9[12];
emilmont 10:3bc89ef62ce7 170 __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
emilmont 10:3bc89ef62ce7 171 __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
emilmont 10:3bc89ef62ce7 172 __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
emilmont 10:3bc89ef62ce7 173 uint32_t RESERVED10[6];
emilmont 10:3bc89ef62ce7 174 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */
emilmont 10:3bc89ef62ce7 175 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
emilmont 10:3bc89ef62ce7 176 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
emilmont 10:3bc89ef62ce7 177 uint32_t RESERVED11[27];
emilmont 10:3bc89ef62ce7 178 __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
emilmont 10:3bc89ef62ce7 179 uint32_t RESERVED12[3];
emilmont 10:3bc89ef62ce7 180 __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
emilmont 10:3bc89ef62ce7 181 uint32_t RESERVED13[6];
emilmont 10:3bc89ef62ce7 182 __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
emilmont 10:3bc89ef62ce7 183 __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
emilmont 10:3bc89ef62ce7 184 __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
emilmont 10:3bc89ef62ce7 185 uint32_t RESERVED14[110];
emilmont 10:3bc89ef62ce7 186 __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
emilmont 10:3bc89ef62ce7 187 } LPC_SYSCON_TypeDef;
emilmont 10:3bc89ef62ce7 188 /*@}*/ /* end of group LPC8xx_SYSCON */
emilmont 10:3bc89ef62ce7 189
emilmont 10:3bc89ef62ce7 190
emilmont 10:3bc89ef62ce7 191 /**
emilmont 10:3bc89ef62ce7 192 * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
emilmont 10:3bc89ef62ce7 193 */
emilmont 10:3bc89ef62ce7 194
emilmont 10:3bc89ef62ce7 195 typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
emilmont 10:3bc89ef62ce7 196 __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
emilmont 10:3bc89ef62ce7 197 __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
emilmont 10:3bc89ef62ce7 198 __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
emilmont 10:3bc89ef62ce7 199 __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
emilmont 10:3bc89ef62ce7 200 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
emilmont 10:3bc89ef62ce7 201 __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
emilmont 10:3bc89ef62ce7 202 __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
emilmont 10:3bc89ef62ce7 203 __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
emilmont 10:3bc89ef62ce7 204 __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
emilmont 10:3bc89ef62ce7 205 __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
emilmont 10:3bc89ef62ce7 206 __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
emilmont 10:3bc89ef62ce7 207 __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
emilmont 10:3bc89ef62ce7 208 __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
emilmont 10:3bc89ef62ce7 209 __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
emilmont 10:3bc89ef62ce7 210 __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
emilmont 10:3bc89ef62ce7 211 __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
emilmont 10:3bc89ef62ce7 212 __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
emilmont 10:3bc89ef62ce7 213 __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
emilmont 10:3bc89ef62ce7 214 __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
emilmont 10:3bc89ef62ce7 215 } LPC_IOCON_TypeDef;
emilmont 10:3bc89ef62ce7 216 /*@}*/ /* end of group LPC8xx_IOCON */
emilmont 10:3bc89ef62ce7 217
emilmont 10:3bc89ef62ce7 218 /**
emilmont 10:3bc89ef62ce7 219 * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL)
emilmont 10:3bc89ef62ce7 220 */
emilmont 10:3bc89ef62ce7 221 typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
emilmont 10:3bc89ef62ce7 222 __I uint32_t RESERVED0[4];
emilmont 10:3bc89ef62ce7 223 __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
emilmont 10:3bc89ef62ce7 224 __I uint32_t RESERVED1[3];
emilmont 10:3bc89ef62ce7 225 __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
emilmont 10:3bc89ef62ce7 226 __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
emilmont 10:3bc89ef62ce7 227 __I uint32_t RESERVED2;
emilmont 10:3bc89ef62ce7 228 __I uint32_t FMSW0;
emilmont 10:3bc89ef62ce7 229 } LPC_FLASHCTRL_TypeDef;
emilmont 10:3bc89ef62ce7 230 /*@}*/ /* end of group LPC8xx_FLASHCTRL */
emilmont 10:3bc89ef62ce7 231
emilmont 10:3bc89ef62ce7 232
emilmont 10:3bc89ef62ce7 233 /*------------- Power Management Unit (PMU) --------------------------*/
emilmont 10:3bc89ef62ce7 234 /** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
emilmont 10:3bc89ef62ce7 235 @{
emilmont 10:3bc89ef62ce7 236 */
emilmont 10:3bc89ef62ce7 237 typedef struct
emilmont 10:3bc89ef62ce7 238 {
emilmont 10:3bc89ef62ce7 239 __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
emilmont 10:3bc89ef62ce7 240 __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
emilmont 10:3bc89ef62ce7 241 __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
emilmont 10:3bc89ef62ce7 242 __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
emilmont 10:3bc89ef62ce7 243 __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
emilmont 10:3bc89ef62ce7 244 __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
emilmont 10:3bc89ef62ce7 245 } LPC_PMU_TypeDef;
emilmont 10:3bc89ef62ce7 246 /*@}*/ /* end of group LPC8xx_PMU */
emilmont 10:3bc89ef62ce7 247
emilmont 10:3bc89ef62ce7 248
emilmont 10:3bc89ef62ce7 249 /*------------- Switch Matrix Port --------------------------*/
emilmont 10:3bc89ef62ce7 250 /** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
emilmont 10:3bc89ef62ce7 251 @{
emilmont 10:3bc89ef62ce7 252 */
emilmont 10:3bc89ef62ce7 253 typedef struct
emilmont 10:3bc89ef62ce7 254 {
emilmont 10:3bc89ef62ce7 255 union {
emilmont 10:3bc89ef62ce7 256 __IO uint32_t PINASSIGN[9];
emilmont 10:3bc89ef62ce7 257 struct {
emilmont 10:3bc89ef62ce7 258 __IO uint32_t PINASSIGN0;
emilmont 10:3bc89ef62ce7 259 __IO uint32_t PINASSIGN1;
emilmont 10:3bc89ef62ce7 260 __IO uint32_t PINASSIGN2;
emilmont 10:3bc89ef62ce7 261 __IO uint32_t PINASSIGN3;
emilmont 10:3bc89ef62ce7 262 __IO uint32_t PINASSIGN4;
emilmont 10:3bc89ef62ce7 263 __IO uint32_t PINASSIGN5;
emilmont 10:3bc89ef62ce7 264 __IO uint32_t PINASSIGN6;
emilmont 10:3bc89ef62ce7 265 __IO uint32_t PINASSIGN7;
emilmont 10:3bc89ef62ce7 266 __IO uint32_t PINASSIGN8;
emilmont 10:3bc89ef62ce7 267 };
emilmont 10:3bc89ef62ce7 268 };
emilmont 10:3bc89ef62ce7 269 __I uint32_t RESERVED0[103];
emilmont 10:3bc89ef62ce7 270 __IO uint32_t PINENABLE0;
emilmont 10:3bc89ef62ce7 271 } LPC_SWM_TypeDef;
emilmont 10:3bc89ef62ce7 272 /*@}*/ /* end of group LPC8xx_SWM */
emilmont 10:3bc89ef62ce7 273
emilmont 10:3bc89ef62ce7 274
emilmont 10:3bc89ef62ce7 275 // ------------------------------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 276 // ----- GPIO_PORT -----
emilmont 10:3bc89ef62ce7 277 // ------------------------------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 278
emilmont 10:3bc89ef62ce7 279 /**
emilmont 10:3bc89ef62ce7 280 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
emilmont 10:3bc89ef62ce7 281 */
emilmont 10:3bc89ef62ce7 282
emilmont 10:3bc89ef62ce7 283 typedef struct {
emilmont 10:3bc89ef62ce7 284 __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */
emilmont 10:3bc89ef62ce7 285 __I uint16_t RESERVED0[2039];
emilmont 10:3bc89ef62ce7 286 __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */
emilmont 10:3bc89ef62ce7 287 uint32_t RESERVED1[1006];
emilmont 10:3bc89ef62ce7 288 __IO uint32_t DIR0; /* 0x2000 */
emilmont 10:3bc89ef62ce7 289 uint32_t RESERVED2[31];
emilmont 10:3bc89ef62ce7 290 __IO uint32_t MASK0; /* 0x2080 */
emilmont 10:3bc89ef62ce7 291 uint32_t RESERVED3[31];
emilmont 10:3bc89ef62ce7 292 __IO uint32_t PIN0; /* 0x2100 */
emilmont 10:3bc89ef62ce7 293 uint32_t RESERVED4[31];
emilmont 10:3bc89ef62ce7 294 __IO uint32_t MPIN0; /* 0x2180 */
emilmont 10:3bc89ef62ce7 295 uint32_t RESERVED5[31];
emilmont 10:3bc89ef62ce7 296 __IO uint32_t SET0; /* 0x2200 */
emilmont 10:3bc89ef62ce7 297 uint32_t RESERVED6[31];
emilmont 10:3bc89ef62ce7 298 __O uint32_t CLR0; /* 0x2280 */
emilmont 10:3bc89ef62ce7 299 uint32_t RESERVED7[31];
emilmont 10:3bc89ef62ce7 300 __O uint32_t NOT0; /* 0x2300 */
emilmont 10:3bc89ef62ce7 301
emilmont 10:3bc89ef62ce7 302 } LPC_GPIO_PORT_TypeDef;
emilmont 10:3bc89ef62ce7 303
emilmont 10:3bc89ef62ce7 304
emilmont 10:3bc89ef62ce7 305 // ------------------------------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 306 // ----- PIN_INT -----
emilmont 10:3bc89ef62ce7 307 // ------------------------------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 308
emilmont 10:3bc89ef62ce7 309 /**
emilmont 10:3bc89ef62ce7 310 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT)
emilmont 10:3bc89ef62ce7 311 */
emilmont 10:3bc89ef62ce7 312
emilmont 10:3bc89ef62ce7 313 typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
emilmont 10:3bc89ef62ce7 314 __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
emilmont 10:3bc89ef62ce7 315 __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
emilmont 10:3bc89ef62ce7 316 __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
emilmont 10:3bc89ef62ce7 317 __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
emilmont 10:3bc89ef62ce7 318 __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
emilmont 10:3bc89ef62ce7 319 __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
emilmont 10:3bc89ef62ce7 320 __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
emilmont 10:3bc89ef62ce7 321 __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
emilmont 10:3bc89ef62ce7 322 __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
emilmont 10:3bc89ef62ce7 323 __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
emilmont 10:3bc89ef62ce7 324 __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
emilmont 10:3bc89ef62ce7 325 __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
emilmont 10:3bc89ef62ce7 326 __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
emilmont 10:3bc89ef62ce7 327 } LPC_PIN_INT_TypeDef;
emilmont 10:3bc89ef62ce7 328
emilmont 10:3bc89ef62ce7 329
emilmont 10:3bc89ef62ce7 330 /*------------- CRC Engine (CRC) -----------------------------------------*/
emilmont 10:3bc89ef62ce7 331 /** @addtogroup LPC8xx_CRC
emilmont 10:3bc89ef62ce7 332 @{
emilmont 10:3bc89ef62ce7 333 */
emilmont 10:3bc89ef62ce7 334 typedef struct
emilmont 10:3bc89ef62ce7 335 {
emilmont 10:3bc89ef62ce7 336 __IO uint32_t MODE;
emilmont 10:3bc89ef62ce7 337 __IO uint32_t SEED;
emilmont 10:3bc89ef62ce7 338 union {
emilmont 10:3bc89ef62ce7 339 __I uint32_t SUM;
emilmont 10:3bc89ef62ce7 340 __O uint32_t WR_DATA_DWORD;
emilmont 10:3bc89ef62ce7 341 __O uint16_t WR_DATA_WORD;
emilmont 10:3bc89ef62ce7 342 uint16_t RESERVED_WORD;
emilmont 10:3bc89ef62ce7 343 __O uint8_t WR_DATA_BYTE;
emilmont 10:3bc89ef62ce7 344 uint8_t RESERVED_BYTE[3];
emilmont 10:3bc89ef62ce7 345 };
emilmont 10:3bc89ef62ce7 346 } LPC_CRC_TypeDef;
emilmont 10:3bc89ef62ce7 347 /*@}*/ /* end of group LPC8xx_CRC */
emilmont 10:3bc89ef62ce7 348
emilmont 10:3bc89ef62ce7 349 /*------------- Comparator (CMP) --------------------------------------------------*/
emilmont 10:3bc89ef62ce7 350 /** @addtogroup LPC8xx_CMP LPC8xx Comparator
emilmont 10:3bc89ef62ce7 351 @{
emilmont 10:3bc89ef62ce7 352 */
emilmont 10:3bc89ef62ce7 353 typedef struct { /*!< (@ 0x40024000) CMP Structure */
emilmont 10:3bc89ef62ce7 354 __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
emilmont 10:3bc89ef62ce7 355 __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
emilmont 10:3bc89ef62ce7 356 } LPC_CMP_TypeDef;
emilmont 10:3bc89ef62ce7 357 /*@}*/ /* end of group LPC8xx_CMP */
emilmont 10:3bc89ef62ce7 358
emilmont 10:3bc89ef62ce7 359
emilmont 10:3bc89ef62ce7 360 /*------------- Wakeup Timer (WKT) --------------------------------------------------*/
emilmont 10:3bc89ef62ce7 361 /** @addtogroup LPC8xx_WKT
emilmont 10:3bc89ef62ce7 362 @{
emilmont 10:3bc89ef62ce7 363 */
emilmont 10:3bc89ef62ce7 364 typedef struct { /*!< (@ 0x40028000) WKT Structure */
emilmont 10:3bc89ef62ce7 365 __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
emilmont 10:3bc89ef62ce7 366 uint32_t Reserved[2];
emilmont 10:3bc89ef62ce7 367 __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
emilmont 10:3bc89ef62ce7 368 } LPC_WKT_TypeDef;
emilmont 10:3bc89ef62ce7 369 /*@}*/ /* end of group LPC8xx_WKT */
emilmont 10:3bc89ef62ce7 370
emilmont 10:3bc89ef62ce7 371
emilmont 10:3bc89ef62ce7 372 /*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
emilmont 10:3bc89ef62ce7 373 typedef struct {
emilmont 10:3bc89ef62ce7 374 __IO uint32_t INTVAL;
emilmont 10:3bc89ef62ce7 375 __IO uint32_t TIMER;
emilmont 10:3bc89ef62ce7 376 __IO uint32_t CTRL;
emilmont 10:3bc89ef62ce7 377 __IO uint32_t STAT;
emilmont 10:3bc89ef62ce7 378 } MRT_Channel_cfg_Type;
emilmont 10:3bc89ef62ce7 379
emilmont 10:3bc89ef62ce7 380 typedef struct {
emilmont 10:3bc89ef62ce7 381 MRT_Channel_cfg_Type Channel[4];
emilmont 10:3bc89ef62ce7 382 uint32_t Reserved0[1];
emilmont 10:3bc89ef62ce7 383 __IO uint32_t IDLE_CH;
emilmont 10:3bc89ef62ce7 384 __IO uint32_t IRQ_FLAG;
emilmont 10:3bc89ef62ce7 385 } LPC_MRT_TypeDef;
emilmont 10:3bc89ef62ce7 386
emilmont 10:3bc89ef62ce7 387
emilmont 10:3bc89ef62ce7 388 /*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
emilmont 10:3bc89ef62ce7 389 /** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
emilmont 10:3bc89ef62ce7 390 @{
emilmont 10:3bc89ef62ce7 391 */
emilmont 10:3bc89ef62ce7 392 /**
emilmont 10:3bc89ef62ce7 393 * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART)
emilmont 10:3bc89ef62ce7 394 */
emilmont 10:3bc89ef62ce7 395 typedef struct
emilmont 10:3bc89ef62ce7 396 {
emilmont 10:3bc89ef62ce7 397 __IO uint32_t CFG; /* 0x00 */
emilmont 10:3bc89ef62ce7 398 __IO uint32_t CTRL;
emilmont 10:3bc89ef62ce7 399 __IO uint32_t STAT;
emilmont 10:3bc89ef62ce7 400 __IO uint32_t INTENSET;
emilmont 10:3bc89ef62ce7 401 __O uint32_t INTENCLR; /* 0x10 */
emilmont 10:3bc89ef62ce7 402 __I uint32_t RXDATA;
emilmont 10:3bc89ef62ce7 403 __I uint32_t RXDATA_STAT;
emilmont 10:3bc89ef62ce7 404 __IO uint32_t TXDATA;
emilmont 10:3bc89ef62ce7 405 __IO uint32_t BRG; /* 0x20 */
emilmont 10:3bc89ef62ce7 406 __IO uint32_t INTSTAT;
emilmont 10:3bc89ef62ce7 407 } LPC_USART_TypeDef;
emilmont 10:3bc89ef62ce7 408
emilmont 10:3bc89ef62ce7 409 /*@}*/ /* end of group LPC8xx_USART */
emilmont 10:3bc89ef62ce7 410
emilmont 10:3bc89ef62ce7 411
emilmont 10:3bc89ef62ce7 412 /*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
emilmont 10:3bc89ef62ce7 413 /** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
emilmont 10:3bc89ef62ce7 414 @{
emilmont 10:3bc89ef62ce7 415 */
emilmont 10:3bc89ef62ce7 416 typedef struct
emilmont 10:3bc89ef62ce7 417 {
emilmont 10:3bc89ef62ce7 418 __IO uint32_t CFG; /* 0x00 */
emilmont 10:3bc89ef62ce7 419 __IO uint32_t DLY;
emilmont 10:3bc89ef62ce7 420 __IO uint32_t STAT;
emilmont 10:3bc89ef62ce7 421 __IO uint32_t INTENSET;
emilmont 10:3bc89ef62ce7 422 __O uint32_t INTENCLR; /* 0x10 */
emilmont 10:3bc89ef62ce7 423 __I uint32_t RXDAT;
emilmont 10:3bc89ef62ce7 424 __IO uint32_t TXDATCTL;
emilmont 10:3bc89ef62ce7 425 __IO uint32_t TXDAT;
emilmont 10:3bc89ef62ce7 426 __IO uint32_t TXCTRL; /* 0x20 */
emilmont 10:3bc89ef62ce7 427 __IO uint32_t DIV;
emilmont 10:3bc89ef62ce7 428 __I uint32_t INTSTAT;
emilmont 10:3bc89ef62ce7 429 } LPC_SPI_TypeDef;
emilmont 10:3bc89ef62ce7 430 /*@}*/ /* end of group LPC8xx_SPI */
emilmont 10:3bc89ef62ce7 431
emilmont 10:3bc89ef62ce7 432
emilmont 10:3bc89ef62ce7 433 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
emilmont 10:3bc89ef62ce7 434 /** @addtogroup LPC8xx_I2C I2C-Bus Interface
emilmont 10:3bc89ef62ce7 435 @{
emilmont 10:3bc89ef62ce7 436 */
emilmont 10:3bc89ef62ce7 437 typedef struct
emilmont 10:3bc89ef62ce7 438 {
emilmont 10:3bc89ef62ce7 439 __IO uint32_t CFG; /* 0x00 */
emilmont 10:3bc89ef62ce7 440 __IO uint32_t STAT;
emilmont 10:3bc89ef62ce7 441 __IO uint32_t INTENSET;
emilmont 10:3bc89ef62ce7 442 __O uint32_t INTENCLR;
emilmont 10:3bc89ef62ce7 443 __IO uint32_t TIMEOUT; /* 0x10 */
emilmont 10:3bc89ef62ce7 444 __IO uint32_t DIV;
emilmont 10:3bc89ef62ce7 445 __IO uint32_t INTSTAT;
emilmont 10:3bc89ef62ce7 446 uint32_t Reserved0[1];
emilmont 10:3bc89ef62ce7 447 __IO uint32_t MSTCTL; /* 0x20 */
emilmont 10:3bc89ef62ce7 448 __IO uint32_t MSTTIME;
emilmont 10:3bc89ef62ce7 449 __IO uint32_t MSTDAT;
emilmont 10:3bc89ef62ce7 450 uint32_t Reserved1[5];
emilmont 10:3bc89ef62ce7 451 __IO uint32_t SLVCTL; /* 0x40 */
emilmont 10:3bc89ef62ce7 452 __IO uint32_t SLVDAT;
emilmont 10:3bc89ef62ce7 453 __IO uint32_t SLVADR0;
emilmont 10:3bc89ef62ce7 454 __IO uint32_t SLVADR1;
emilmont 10:3bc89ef62ce7 455 __IO uint32_t SLVADR2; /* 0x50 */
emilmont 10:3bc89ef62ce7 456 __IO uint32_t SLVADR3;
emilmont 10:3bc89ef62ce7 457 __IO uint32_t SLVQUAL0;
emilmont 10:3bc89ef62ce7 458 uint32_t Reserved2[9];
emilmont 10:3bc89ef62ce7 459 __I uint32_t MONRXDAT; /* 0x80 */
emilmont 10:3bc89ef62ce7 460 } LPC_I2C_TypeDef;
emilmont 10:3bc89ef62ce7 461
emilmont 10:3bc89ef62ce7 462 /*@}*/ /* end of group LPC8xx_I2C */
emilmont 10:3bc89ef62ce7 463
emilmont 10:3bc89ef62ce7 464 /**
emilmont 10:3bc89ef62ce7 465 * @brief State Configurable Timer (SCT) (SCT)
emilmont 10:3bc89ef62ce7 466 */
emilmont 10:3bc89ef62ce7 467
emilmont 10:3bc89ef62ce7 468 /**
emilmont 10:3bc89ef62ce7 469 * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
emilmont 10:3bc89ef62ce7 470 */
emilmont 10:3bc89ef62ce7 471
emilmont 10:3bc89ef62ce7 472 #define CONFIG_SCT_nEV (6) /* Number of events */
emilmont 10:3bc89ef62ce7 473 #define CONFIG_SCT_nRG (5) /* Number of match/compare registers */
emilmont 10:3bc89ef62ce7 474 #define CONFIG_SCT_nOU (4) /* Number of outputs */
emilmont 10:3bc89ef62ce7 475
emilmont 10:3bc89ef62ce7 476 typedef struct
emilmont 10:3bc89ef62ce7 477 {
emilmont 10:3bc89ef62ce7 478 __IO uint32_t CONFIG; /* 0x000 Configuration Register */
emilmont 10:3bc89ef62ce7 479 union {
emilmont 10:3bc89ef62ce7 480 __IO uint32_t CTRL_U; /* 0x004 Control Register */
emilmont 10:3bc89ef62ce7 481 struct {
emilmont 10:3bc89ef62ce7 482 __IO uint16_t CTRL_L; /* 0x004 low control register */
emilmont 10:3bc89ef62ce7 483 __IO uint16_t CTRL_H; /* 0x006 high control register */
emilmont 10:3bc89ef62ce7 484 };
emilmont 10:3bc89ef62ce7 485 };
emilmont 10:3bc89ef62ce7 486 __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
emilmont 10:3bc89ef62ce7 487 __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
emilmont 10:3bc89ef62ce7 488 __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
emilmont 10:3bc89ef62ce7 489 __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
emilmont 10:3bc89ef62ce7 490 __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
emilmont 10:3bc89ef62ce7 491 __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
emilmont 10:3bc89ef62ce7 492 __IO uint16_t START_L; /* 0x014 start register for counter L */
emilmont 10:3bc89ef62ce7 493 __IO uint16_t START_H; /* 0x016 start register for counter H */
emilmont 10:3bc89ef62ce7 494 uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
emilmont 10:3bc89ef62ce7 495 union {
emilmont 10:3bc89ef62ce7 496 __IO uint32_t COUNT_U; /* 0x040 counter register */
emilmont 10:3bc89ef62ce7 497 struct {
emilmont 10:3bc89ef62ce7 498 __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
emilmont 10:3bc89ef62ce7 499 __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
emilmont 10:3bc89ef62ce7 500 };
emilmont 10:3bc89ef62ce7 501 };
emilmont 10:3bc89ef62ce7 502 __IO uint16_t STATE_L; /* 0x044 state register for counter L */
emilmont 10:3bc89ef62ce7 503 __IO uint16_t STATE_H; /* 0x046 state register for counter H */
emilmont 10:3bc89ef62ce7 504 __I uint32_t INPUT; /* 0x048 input register */
emilmont 10:3bc89ef62ce7 505 __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
emilmont 10:3bc89ef62ce7 506 __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
emilmont 10:3bc89ef62ce7 507 __IO uint32_t OUTPUT; /* 0x050 output register */
emilmont 10:3bc89ef62ce7 508 __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
emilmont 10:3bc89ef62ce7 509 __IO uint32_t RES; /* 0x058 conflict resolution register */
emilmont 10:3bc89ef62ce7 510 uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */
emilmont 10:3bc89ef62ce7 511 __IO uint32_t EVEN; /* 0x0F0 event enable register */
emilmont 10:3bc89ef62ce7 512 __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
emilmont 10:3bc89ef62ce7 513 __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
emilmont 10:3bc89ef62ce7 514 __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
emilmont 10:3bc89ef62ce7 515
emilmont 10:3bc89ef62ce7 516 union {
emilmont 10:3bc89ef62ce7 517 __IO union { /* 0x100-... Match / Capture value */
emilmont 10:3bc89ef62ce7 518 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
emilmont 10:3bc89ef62ce7 519 struct {
emilmont 10:3bc89ef62ce7 520 uint16_t L; /* SCTMATCH[i].L Access to L value */
emilmont 10:3bc89ef62ce7 521 uint16_t H; /* SCTMATCH[i].H Access to H value */
emilmont 10:3bc89ef62ce7 522 };
emilmont 10:3bc89ef62ce7 523 } MATCH[CONFIG_SCT_nRG];
emilmont 10:3bc89ef62ce7 524 __I union {
emilmont 10:3bc89ef62ce7 525 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
emilmont 10:3bc89ef62ce7 526 struct {
emilmont 10:3bc89ef62ce7 527 uint16_t L; /* SCTCAP[i].L Access to H value */
emilmont 10:3bc89ef62ce7 528 uint16_t H; /* SCTCAP[i].H Access to H value */
emilmont 10:3bc89ef62ce7 529 };
emilmont 10:3bc89ef62ce7 530 } CAP[CONFIG_SCT_nRG];
emilmont 10:3bc89ef62ce7 531 };
emilmont 10:3bc89ef62ce7 532
emilmont 10:3bc89ef62ce7 533
emilmont 10:3bc89ef62ce7 534 uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
emilmont 10:3bc89ef62ce7 535
emilmont 10:3bc89ef62ce7 536 union {
emilmont 10:3bc89ef62ce7 537 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
emilmont 10:3bc89ef62ce7 538 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
emilmont 10:3bc89ef62ce7 539 };
emilmont 10:3bc89ef62ce7 540 uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
emilmont 10:3bc89ef62ce7 541 union {
emilmont 10:3bc89ef62ce7 542 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
emilmont 10:3bc89ef62ce7 543 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
emilmont 10:3bc89ef62ce7 544 };
emilmont 10:3bc89ef62ce7 545
emilmont 10:3bc89ef62ce7 546 uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
emilmont 10:3bc89ef62ce7 547
emilmont 10:3bc89ef62ce7 548
emilmont 10:3bc89ef62ce7 549 union {
emilmont 10:3bc89ef62ce7 550 __IO union { /* 0x200-... Match Reload / Capture Control value */
emilmont 10:3bc89ef62ce7 551 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
emilmont 10:3bc89ef62ce7 552 struct {
emilmont 10:3bc89ef62ce7 553 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
emilmont 10:3bc89ef62ce7 554 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
emilmont 10:3bc89ef62ce7 555 };
emilmont 10:3bc89ef62ce7 556 } MATCHREL[CONFIG_SCT_nRG];
emilmont 10:3bc89ef62ce7 557 __IO union {
emilmont 10:3bc89ef62ce7 558 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
emilmont 10:3bc89ef62ce7 559 struct {
emilmont 10:3bc89ef62ce7 560 uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
emilmont 10:3bc89ef62ce7 561 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
emilmont 10:3bc89ef62ce7 562 };
emilmont 10:3bc89ef62ce7 563 } CAPCTRL[CONFIG_SCT_nRG];
emilmont 10:3bc89ef62ce7 564 };
emilmont 10:3bc89ef62ce7 565
emilmont 10:3bc89ef62ce7 566 uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
emilmont 10:3bc89ef62ce7 567
emilmont 10:3bc89ef62ce7 568 union {
emilmont 10:3bc89ef62ce7 569 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
emilmont 10:3bc89ef62ce7 570 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
emilmont 10:3bc89ef62ce7 571 };
emilmont 10:3bc89ef62ce7 572 uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
emilmont 10:3bc89ef62ce7 573 union {
emilmont 10:3bc89ef62ce7 574 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
emilmont 10:3bc89ef62ce7 575 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
emilmont 10:3bc89ef62ce7 576 };
emilmont 10:3bc89ef62ce7 577 uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
emilmont 10:3bc89ef62ce7 578
emilmont 10:3bc89ef62ce7 579 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
emilmont 10:3bc89ef62ce7 580 uint32_t STATE; /* Event State Register */
emilmont 10:3bc89ef62ce7 581 uint32_t CTRL; /* Event Control Register */
emilmont 10:3bc89ef62ce7 582 } EVENT[CONFIG_SCT_nEV];
emilmont 10:3bc89ef62ce7 583
emilmont 10:3bc89ef62ce7 584 uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
emilmont 10:3bc89ef62ce7 585
emilmont 10:3bc89ef62ce7 586 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
emilmont 10:3bc89ef62ce7 587 uint32_t SET; /* Output n Set Register */
emilmont 10:3bc89ef62ce7 588 uint32_t CLR; /* Output n Clear Register */
emilmont 10:3bc89ef62ce7 589 } OUT[CONFIG_SCT_nOU];
emilmont 10:3bc89ef62ce7 590
emilmont 10:3bc89ef62ce7 591 uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
emilmont 10:3bc89ef62ce7 592
emilmont 10:3bc89ef62ce7 593 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
emilmont 10:3bc89ef62ce7 594
emilmont 10:3bc89ef62ce7 595 } LPC_SCT_TypeDef;
emilmont 10:3bc89ef62ce7 596 /*@}*/ /* end of group LPC8xx_SCT */
emilmont 10:3bc89ef62ce7 597
emilmont 10:3bc89ef62ce7 598
emilmont 10:3bc89ef62ce7 599 /*------------- Watchdog Timer (WWDT) -----------------------------------------*/
emilmont 10:3bc89ef62ce7 600 /** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
emilmont 10:3bc89ef62ce7 601 @{
emilmont 10:3bc89ef62ce7 602 */
emilmont 10:3bc89ef62ce7 603 typedef struct
emilmont 10:3bc89ef62ce7 604 {
emilmont 10:3bc89ef62ce7 605 __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
emilmont 10:3bc89ef62ce7 606 __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
emilmont 10:3bc89ef62ce7 607 __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
emilmont 10:3bc89ef62ce7 608 __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
emilmont 10:3bc89ef62ce7 609 uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
emilmont 10:3bc89ef62ce7 610 __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
emilmont 10:3bc89ef62ce7 611 __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
emilmont 10:3bc89ef62ce7 612 } LPC_WWDT_TypeDef;
emilmont 10:3bc89ef62ce7 613 /*@}*/ /* end of group LPC8xx_WDT */
emilmont 10:3bc89ef62ce7 614
emilmont 10:3bc89ef62ce7 615
emilmont 10:3bc89ef62ce7 616 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 617 #pragma no_anon_unions
emilmont 10:3bc89ef62ce7 618 #endif
emilmont 10:3bc89ef62ce7 619
emilmont 10:3bc89ef62ce7 620 /******************************************************************************/
emilmont 10:3bc89ef62ce7 621 /* Peripheral memory map */
emilmont 10:3bc89ef62ce7 622 /******************************************************************************/
emilmont 10:3bc89ef62ce7 623 /* Base addresses */
emilmont 10:3bc89ef62ce7 624 #define LPC_FLASH_BASE (0x00000000UL)
emilmont 10:3bc89ef62ce7 625 #define LPC_RAM_BASE (0x10000000UL)
emilmont 10:3bc89ef62ce7 626 #define LPC_ROM_BASE (0x1FFF0000UL)
emilmont 10:3bc89ef62ce7 627 #define LPC_APB0_BASE (0x40000000UL)
emilmont 10:3bc89ef62ce7 628 #define LPC_AHB_BASE (0x50000000UL)
emilmont 10:3bc89ef62ce7 629
emilmont 10:3bc89ef62ce7 630 /* APB0 peripherals */
emilmont 10:3bc89ef62ce7 631 #define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
emilmont 10:3bc89ef62ce7 632 #define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
emilmont 10:3bc89ef62ce7 633 #define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
emilmont 10:3bc89ef62ce7 634 #define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
emilmont 10:3bc89ef62ce7 635 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
emilmont 10:3bc89ef62ce7 636 #define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
emilmont 10:3bc89ef62ce7 637
emilmont 10:3bc89ef62ce7 638 #define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
emilmont 10:3bc89ef62ce7 639 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
emilmont 10:3bc89ef62ce7 640 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
emilmont 10:3bc89ef62ce7 641 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000)
emilmont 10:3bc89ef62ce7 642 #define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
emilmont 10:3bc89ef62ce7 643 #define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
emilmont 10:3bc89ef62ce7 644 #define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
emilmont 10:3bc89ef62ce7 645 #define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
emilmont 10:3bc89ef62ce7 646 #define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
emilmont 10:3bc89ef62ce7 647
emilmont 10:3bc89ef62ce7 648 /* AHB peripherals */
emilmont 10:3bc89ef62ce7 649 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
emilmont 10:3bc89ef62ce7 650 #define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
emilmont 10:3bc89ef62ce7 651
emilmont 10:3bc89ef62ce7 652 #define LPC_GPIO_PORT_BASE (0xA0000000)
emilmont 10:3bc89ef62ce7 653 #define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
emilmont 10:3bc89ef62ce7 654
emilmont 10:3bc89ef62ce7 655 /******************************************************************************/
emilmont 10:3bc89ef62ce7 656 /* Peripheral declaration */
emilmont 10:3bc89ef62ce7 657 /******************************************************************************/
emilmont 10:3bc89ef62ce7 658 #define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
emilmont 10:3bc89ef62ce7 659 #define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
emilmont 10:3bc89ef62ce7 660
emilmont 10:3bc89ef62ce7 661
emilmont 10:3bc89ef62ce7 662 #define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
emilmont 10:3bc89ef62ce7 663 #define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
emilmont 10:3bc89ef62ce7 664 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
emilmont 10:3bc89ef62ce7 665 #define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
emilmont 10:3bc89ef62ce7 666
emilmont 10:3bc89ef62ce7 667 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
emilmont 10:3bc89ef62ce7 668 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
emilmont 10:3bc89ef62ce7 669 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
emilmont 10:3bc89ef62ce7 670 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
emilmont 10:3bc89ef62ce7 671 #define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
emilmont 10:3bc89ef62ce7 672 #define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
emilmont 10:3bc89ef62ce7 673 #define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
emilmont 10:3bc89ef62ce7 674 #define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
emilmont 10:3bc89ef62ce7 675 #define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
emilmont 10:3bc89ef62ce7 676
emilmont 10:3bc89ef62ce7 677 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
emilmont 10:3bc89ef62ce7 678 #define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
emilmont 10:3bc89ef62ce7 679
emilmont 10:3bc89ef62ce7 680 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
emilmont 10:3bc89ef62ce7 681 #define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
emilmont 10:3bc89ef62ce7 682
emilmont 10:3bc89ef62ce7 683 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 684 }
emilmont 10:3bc89ef62ce7 685 #endif
emilmont 10:3bc89ef62ce7 686
emilmont 10:3bc89ef62ce7 687 #endif /* __LPC8xx_H__ */