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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s@13:0645d8841f51, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 14:12:34 2013 +0300
Revision:
13:0645d8841f51
Child:
19:398f4c622e1b
Update mbed sources to revision 64

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 13:0645d8841f51 1 /* File: startup_ARMCM0.S
bogdanm 13:0645d8841f51 2 * Purpose: startup file for Cortex-M0 devices. Should use with
bogdanm 13:0645d8841f51 3 * GCC for ARM Embedded Processors
bogdanm 13:0645d8841f51 4 * Version: V1.2
bogdanm 13:0645d8841f51 5 * Date: 15 Nov 2011
bogdanm 13:0645d8841f51 6 *
bogdanm 13:0645d8841f51 7 * Copyright (c) 2011, ARM Limited
bogdanm 13:0645d8841f51 8 * All rights reserved.
bogdanm 13:0645d8841f51 9 *
bogdanm 13:0645d8841f51 10 * Redistribution and use in source and binary forms, with or without
bogdanm 13:0645d8841f51 11 * modification, are permitted provided that the following conditions are met:
bogdanm 13:0645d8841f51 12 * Redistributions of source code must retain the above copyright
bogdanm 13:0645d8841f51 13 notice, this list of conditions and the following disclaimer.
bogdanm 13:0645d8841f51 14 * Redistributions in binary form must reproduce the above copyright
bogdanm 13:0645d8841f51 15 notice, this list of conditions and the following disclaimer in the
bogdanm 13:0645d8841f51 16 documentation and/or other materials provided with the distribution.
bogdanm 13:0645d8841f51 17 * Neither the name of the ARM Limited nor the
bogdanm 13:0645d8841f51 18 names of its contributors may be used to endorse or promote products
bogdanm 13:0645d8841f51 19 derived from this software without specific prior written permission.
bogdanm 13:0645d8841f51 20 *
bogdanm 13:0645d8841f51 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 13:0645d8841f51 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 13:0645d8841f51 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 13:0645d8841f51 24 * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
bogdanm 13:0645d8841f51 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 13:0645d8841f51 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 13:0645d8841f51 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
bogdanm 13:0645d8841f51 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 13:0645d8841f51 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 13:0645d8841f51 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 13:0645d8841f51 31 */
bogdanm 13:0645d8841f51 32 .syntax unified
bogdanm 13:0645d8841f51 33 .arch armv6-m
bogdanm 13:0645d8841f51 34
bogdanm 13:0645d8841f51 35 /* Memory Model
bogdanm 13:0645d8841f51 36 The HEAP starts at the end of the DATA section and grows upward.
bogdanm 13:0645d8841f51 37
bogdanm 13:0645d8841f51 38 The STACK starts at the end of the RAM and grows downward.
bogdanm 13:0645d8841f51 39
bogdanm 13:0645d8841f51 40 The HEAP and stack STACK are only checked at compile time:
bogdanm 13:0645d8841f51 41 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
bogdanm 13:0645d8841f51 42
bogdanm 13:0645d8841f51 43 This is just a check for the bare minimum for the Heap+Stack area before
bogdanm 13:0645d8841f51 44 aborting compilation, it is not the run time limit:
bogdanm 13:0645d8841f51 45 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
bogdanm 13:0645d8841f51 46 */
bogdanm 13:0645d8841f51 47 .section .stack
bogdanm 13:0645d8841f51 48 .align 3
bogdanm 13:0645d8841f51 49 #ifdef __STACK_SIZE
bogdanm 13:0645d8841f51 50 .equ Stack_Size, __STACK_SIZE
bogdanm 13:0645d8841f51 51 #else
bogdanm 13:0645d8841f51 52 .equ Stack_Size, 0x80
bogdanm 13:0645d8841f51 53 #endif
bogdanm 13:0645d8841f51 54 .globl __StackTop
bogdanm 13:0645d8841f51 55 .globl __StackLimit
bogdanm 13:0645d8841f51 56 __StackLimit:
bogdanm 13:0645d8841f51 57 .space Stack_Size
bogdanm 13:0645d8841f51 58 .size __StackLimit, . - __StackLimit
bogdanm 13:0645d8841f51 59 __StackTop:
bogdanm 13:0645d8841f51 60 .size __StackTop, . - __StackTop
bogdanm 13:0645d8841f51 61
bogdanm 13:0645d8841f51 62 .section .heap
bogdanm 13:0645d8841f51 63 .align 3
bogdanm 13:0645d8841f51 64 #ifdef __HEAP_SIZE
bogdanm 13:0645d8841f51 65 .equ Heap_Size, __HEAP_SIZE
bogdanm 13:0645d8841f51 66 #else
bogdanm 13:0645d8841f51 67 .equ Heap_Size, 0x80
bogdanm 13:0645d8841f51 68 #endif
bogdanm 13:0645d8841f51 69 .globl __HeapBase
bogdanm 13:0645d8841f51 70 .globl __HeapLimit
bogdanm 13:0645d8841f51 71 __HeapBase:
bogdanm 13:0645d8841f51 72 .space Heap_Size
bogdanm 13:0645d8841f51 73 .size __HeapBase, . - __HeapBase
bogdanm 13:0645d8841f51 74 __HeapLimit:
bogdanm 13:0645d8841f51 75 .size __HeapLimit, . - __HeapLimit
bogdanm 13:0645d8841f51 76
bogdanm 13:0645d8841f51 77 .section .isr_vector
bogdanm 13:0645d8841f51 78 .align 2
bogdanm 13:0645d8841f51 79 .globl __isr_vector
bogdanm 13:0645d8841f51 80 __isr_vector:
bogdanm 13:0645d8841f51 81 .long __StackTop /* Top of Stack */
bogdanm 13:0645d8841f51 82 .long Reset_Handler /* Reset Handler */
bogdanm 13:0645d8841f51 83 .long NMI_Handler /* NMI Handler */
bogdanm 13:0645d8841f51 84 .long HardFault_Handler /* Hard Fault Handler */
bogdanm 13:0645d8841f51 85 .long 0 /* Reserved */
bogdanm 13:0645d8841f51 86 .long 0 /* Reserved */
bogdanm 13:0645d8841f51 87 .long 0 /* Reserved */
bogdanm 13:0645d8841f51 88 .long 0 /* Reserved */
bogdanm 13:0645d8841f51 89 .long 0 /* Reserved */
bogdanm 13:0645d8841f51 90 .long 0 /* Reserved */
bogdanm 13:0645d8841f51 91 .long 0 /* Reserved */
bogdanm 13:0645d8841f51 92 .long SVC_Handler /* SVCall Handler */
bogdanm 13:0645d8841f51 93 .long 0 /* Reserved */
bogdanm 13:0645d8841f51 94 .long 0 /* Reserved */
bogdanm 13:0645d8841f51 95 .long PendSV_Handler /* PendSV Handler */
bogdanm 13:0645d8841f51 96 .long SysTick_Handler /* SysTick Handler */
bogdanm 13:0645d8841f51 97
bogdanm 13:0645d8841f51 98 /* LPC11xx interrupts */
bogdanm 13:0645d8841f51 99 .long WAKEUP_IRQHandler /* 16 0 Wake-up on pin PIO0_0 */
bogdanm 13:0645d8841f51 100 .long WAKEUP_IRQHandler /* 17 1 Wake-up on pin PIO0_1 */
bogdanm 13:0645d8841f51 101 .long WAKEUP_IRQHandler /* 18 2 Wake-up on pin PIO0_2 */
bogdanm 13:0645d8841f51 102 .long WAKEUP_IRQHandler /* 19 3 Wake-up on pin PIO0_3 */
bogdanm 13:0645d8841f51 103 .long WAKEUP_IRQHandler /* 20 4 Wake-up on pin PIO0_4 */
bogdanm 13:0645d8841f51 104 .long WAKEUP_IRQHandler /* 21 5 Wake-up on pin PIO0_5 */
bogdanm 13:0645d8841f51 105 .long WAKEUP_IRQHandler /* 22 6 Wake-up on pin PIO0_6 */
bogdanm 13:0645d8841f51 106 .long WAKEUP_IRQHandler /* 23 7 Wake-up on pin PIO0_7 */
bogdanm 13:0645d8841f51 107 .long WAKEUP_IRQHandler /* 24 8 Wake-up on pin PIO0_8 */
bogdanm 13:0645d8841f51 108 .long WAKEUP_IRQHandler /* 25 9 Wake-up on pin PIO0_9 */
bogdanm 13:0645d8841f51 109 .long WAKEUP_IRQHandler /* 26 10 Wake-up on pin PIO0_10 */
bogdanm 13:0645d8841f51 110 .long WAKEUP_IRQHandler /* 27 11 Wake-up on pin PIO0_11 */
bogdanm 13:0645d8841f51 111 .long WAKEUP_IRQHandler /* 28 12 Wake-up on pin PIO1_0 */
bogdanm 13:0645d8841f51 112 .long Default_Handler /* 29 13 */
bogdanm 13:0645d8841f51 113 .long SSP1_IRQHandler /* 30 14 SSP1 */
bogdanm 13:0645d8841f51 114 .long I2C_IRQHandler /* 31 15 I2C0 SI (state change) */
bogdanm 13:0645d8841f51 115 .long TIMER16_0_IRQHandler /* 32 16 CT16B0 16 bit timer 0 */
bogdanm 13:0645d8841f51 116 .long TIMER16_1_IRQHandler /* 33 17 CT16B1 16 bit timer 1 */
bogdanm 13:0645d8841f51 117 .long TIMER32_0_IRQHandler /* 34 18 CT32B0 32 bit timer 0 */
bogdanm 13:0645d8841f51 118 .long TIMER32_1_IRQHandler /* 35 19 CT32B1 32 bit timer 1 */
bogdanm 13:0645d8841f51 119 .long SSP0_IRQHandler /* 36 20 SSP */
bogdanm 13:0645d8841f51 120 .long UART_IRQHandler /* 37 21 UART */
bogdanm 13:0645d8841f51 121 .long Default_Handler /* 38 22 */
bogdanm 13:0645d8841f51 122 .long Default_Handler /* 39 23 */
bogdanm 13:0645d8841f51 123 .long ADC_IRQHandler /* 40 24 ADC end of conversion */
bogdanm 13:0645d8841f51 124 .long WDT_IRQHandler /* 41 25 Watchdog interrupt (WDINT) */
bogdanm 13:0645d8841f51 125 .long BOD_IRQHandler /* 42 26 BOD Brown-out detect */
bogdanm 13:0645d8841f51 126 .long Default_Handler /* 43 27 */
bogdanm 13:0645d8841f51 127 .long PIOINT3_IRQHandler /* 44 28 PIO_3 GPIO interrupt status of port 3 */
bogdanm 13:0645d8841f51 128 .long PIOINT2_IRQHandler /* 45 29 PIO_2 GPIO interrupt status of port 2 */
bogdanm 13:0645d8841f51 129 .long PIOINT1_IRQHandler /* 46 30 PIO_1 GPIO interrupt status of port 1 */
bogdanm 13:0645d8841f51 130 .long PIOINT0_IRQHandler /* 47 31 PIO_0 GPIO interrupt status of port 0 */
bogdanm 13:0645d8841f51 131
bogdanm 13:0645d8841f51 132 .size __isr_vector, . - __isr_vector
bogdanm 13:0645d8841f51 133
bogdanm 13:0645d8841f51 134 .section .text.Reset_Handler
bogdanm 13:0645d8841f51 135 .thumb
bogdanm 13:0645d8841f51 136 .thumb_func
bogdanm 13:0645d8841f51 137 .align 2
bogdanm 13:0645d8841f51 138 .globl Reset_Handler
bogdanm 13:0645d8841f51 139 .type Reset_Handler, %function
bogdanm 13:0645d8841f51 140 Reset_Handler:
bogdanm 13:0645d8841f51 141 /* Loop to copy data from read only memory to RAM. The ranges
bogdanm 13:0645d8841f51 142 * of copy from/to are specified by following symbols evaluated in
bogdanm 13:0645d8841f51 143 * linker script.
bogdanm 13:0645d8841f51 144 * __etext: End of code section, i.e., begin of data sections to copy from.
bogdanm 13:0645d8841f51 145 * __data_start__/__data_end__: RAM address range that data should be
bogdanm 13:0645d8841f51 146 * copied to. Both must be aligned to 4 bytes boundary. */
bogdanm 13:0645d8841f51 147
bogdanm 13:0645d8841f51 148 ldr r1, =__etext
bogdanm 13:0645d8841f51 149 ldr r2, =__data_start__
bogdanm 13:0645d8841f51 150 ldr r3, =__data_end__
bogdanm 13:0645d8841f51 151
bogdanm 13:0645d8841f51 152 subs r3, r2
bogdanm 13:0645d8841f51 153 ble .flash_to_ram_loop_end
bogdanm 13:0645d8841f51 154
bogdanm 13:0645d8841f51 155 movs r4, 0
bogdanm 13:0645d8841f51 156 .flash_to_ram_loop:
bogdanm 13:0645d8841f51 157 ldr r0, [r1,r4]
bogdanm 13:0645d8841f51 158 str r0, [r2,r4]
bogdanm 13:0645d8841f51 159 adds r4, 4
bogdanm 13:0645d8841f51 160 cmp r4, r3
bogdanm 13:0645d8841f51 161 blt .flash_to_ram_loop
bogdanm 13:0645d8841f51 162 .flash_to_ram_loop_end:
bogdanm 13:0645d8841f51 163
bogdanm 13:0645d8841f51 164 ldr r0, =SystemInit
bogdanm 13:0645d8841f51 165 blx r0
bogdanm 13:0645d8841f51 166 ldr r0, =_start
bogdanm 13:0645d8841f51 167 bx r0
bogdanm 13:0645d8841f51 168 .pool
bogdanm 13:0645d8841f51 169 .size Reset_Handler, . - Reset_Handler
bogdanm 13:0645d8841f51 170
bogdanm 13:0645d8841f51 171 .text
bogdanm 13:0645d8841f51 172 /* Macro to define default handlers. Default handler
bogdanm 13:0645d8841f51 173 * will be weak symbol and just dead loops. They can be
bogdanm 13:0645d8841f51 174 * overwritten by other handlers */
bogdanm 13:0645d8841f51 175 .macro def_default_handler handler_name
bogdanm 13:0645d8841f51 176 .align 1
bogdanm 13:0645d8841f51 177 .thumb_func
bogdanm 13:0645d8841f51 178 .weak \handler_name
bogdanm 13:0645d8841f51 179 .type \handler_name, %function
bogdanm 13:0645d8841f51 180 \handler_name :
bogdanm 13:0645d8841f51 181 b .
bogdanm 13:0645d8841f51 182 .size \handler_name, . - \handler_name
bogdanm 13:0645d8841f51 183 .endm
bogdanm 13:0645d8841f51 184
bogdanm 13:0645d8841f51 185 def_default_handler NMI_Handler
bogdanm 13:0645d8841f51 186 def_default_handler HardFault_Handler
bogdanm 13:0645d8841f51 187 def_default_handler SVC_Handler
bogdanm 13:0645d8841f51 188 def_default_handler PendSV_Handler
bogdanm 13:0645d8841f51 189 def_default_handler SysTick_Handler
bogdanm 13:0645d8841f51 190 def_default_handler Default_Handler
bogdanm 13:0645d8841f51 191
bogdanm 13:0645d8841f51 192 def_default_handler WAKEUP_IRQHandler
bogdanm 13:0645d8841f51 193 def_default_handler SSP1_IRQHandler
bogdanm 13:0645d8841f51 194 def_default_handler I2C_IRQHandler
bogdanm 13:0645d8841f51 195 def_default_handler TIMER16_0_IRQHandler
bogdanm 13:0645d8841f51 196 def_default_handler TIMER16_1_IRQHandler
bogdanm 13:0645d8841f51 197 def_default_handler TIMER32_0_IRQHandler
bogdanm 13:0645d8841f51 198 def_default_handler TIMER32_1_IRQHandler
bogdanm 13:0645d8841f51 199 def_default_handler SSP0_IRQHandler
bogdanm 13:0645d8841f51 200 def_default_handler UART_IRQHandler
bogdanm 13:0645d8841f51 201 def_default_handler ADC_IRQHandler
bogdanm 13:0645d8841f51 202 def_default_handler WDT_IRQHandler
bogdanm 13:0645d8841f51 203 def_default_handler BOD_IRQHandler
bogdanm 13:0645d8841f51 204 def_default_handler PIOINT3_IRQHandler
bogdanm 13:0645d8841f51 205 def_default_handler PIOINT2_IRQHandler
bogdanm 13:0645d8841f51 206 def_default_handler PIOINT1_IRQHandler
bogdanm 13:0645d8841f51 207 def_default_handler PIOINT0_IRQHandler
bogdanm 13:0645d8841f51 208
bogdanm 13:0645d8841f51 209 .weak DEF_IRQHandler
bogdanm 13:0645d8841f51 210 .set DEF_IRQHandler, Default_Handler
bogdanm 13:0645d8841f51 211
bogdanm 13:0645d8841f51 212 .end