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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_NXP/TARGET_LPC13XX/gpio_irq_api.c@13:0645d8841f51, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 14:12:34 2013 +0300
Revision:
13:0645d8841f51
Child:
35:371630885ad6
Update mbed sources to revision 64

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 13:0645d8841f51 1 /* mbed Microcontroller Library
bogdanm 13:0645d8841f51 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 13:0645d8841f51 3 *
bogdanm 13:0645d8841f51 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 13:0645d8841f51 5 * you may not use this file except in compliance with the License.
bogdanm 13:0645d8841f51 6 * You may obtain a copy of the License at
bogdanm 13:0645d8841f51 7 *
bogdanm 13:0645d8841f51 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 13:0645d8841f51 9 *
bogdanm 13:0645d8841f51 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 13:0645d8841f51 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 13:0645d8841f51 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 13:0645d8841f51 13 * See the License for the specific language governing permissions and
bogdanm 13:0645d8841f51 14 * limitations under the License.
bogdanm 13:0645d8841f51 15 */
bogdanm 13:0645d8841f51 16 #include <stddef.h>
bogdanm 13:0645d8841f51 17 #include "cmsis.h"
bogdanm 13:0645d8841f51 18 #include "gpio_irq_api.h"
bogdanm 13:0645d8841f51 19 #include "error.h"
bogdanm 13:0645d8841f51 20
bogdanm 13:0645d8841f51 21 #define CHANNEL_NUM 8
bogdanm 13:0645d8841f51 22 #define LPC_GPIO_X LPC_GPIO_PIN_INT
bogdanm 13:0645d8841f51 23 #define PININT_IRQ 0
bogdanm 13:0645d8841f51 24
bogdanm 13:0645d8841f51 25 static uint32_t channel_ids[CHANNEL_NUM] = {0};
bogdanm 13:0645d8841f51 26 static gpio_irq_handler irq_handler;
bogdanm 13:0645d8841f51 27
bogdanm 13:0645d8841f51 28 static inline void handle_interrupt_in(uint32_t channel) {
bogdanm 13:0645d8841f51 29 uint32_t ch_bit = (1 << channel);
bogdanm 13:0645d8841f51 30 // Return immediately if:
bogdanm 13:0645d8841f51 31 // * The interrupt was already served
bogdanm 13:0645d8841f51 32 // * There is no user handler
bogdanm 13:0645d8841f51 33 // * It is a level interrupt, not an edge interrupt
bogdanm 13:0645d8841f51 34 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
bogdanm 13:0645d8841f51 35 (channel_ids[channel] == 0 ) ||
bogdanm 13:0645d8841f51 36 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
bogdanm 13:0645d8841f51 37
bogdanm 13:0645d8841f51 38 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
bogdanm 13:0645d8841f51 39 irq_handler(channel_ids[channel], IRQ_RISE);
bogdanm 13:0645d8841f51 40 LPC_GPIO_X->RISE = ch_bit;
bogdanm 13:0645d8841f51 41 }
bogdanm 13:0645d8841f51 42 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
bogdanm 13:0645d8841f51 43 irq_handler(channel_ids[channel], IRQ_FALL);
bogdanm 13:0645d8841f51 44 }
bogdanm 13:0645d8841f51 45 LPC_GPIO_X->IST = ch_bit;
bogdanm 13:0645d8841f51 46 }
bogdanm 13:0645d8841f51 47
bogdanm 13:0645d8841f51 48 void gpio_irq0(void) {handle_interrupt_in(0);}
bogdanm 13:0645d8841f51 49 void gpio_irq1(void) {handle_interrupt_in(1);}
bogdanm 13:0645d8841f51 50 void gpio_irq2(void) {handle_interrupt_in(2);}
bogdanm 13:0645d8841f51 51 void gpio_irq3(void) {handle_interrupt_in(3);}
bogdanm 13:0645d8841f51 52 void gpio_irq4(void) {handle_interrupt_in(4);}
bogdanm 13:0645d8841f51 53 void gpio_irq5(void) {handle_interrupt_in(5);}
bogdanm 13:0645d8841f51 54 void gpio_irq6(void) {handle_interrupt_in(6);}
bogdanm 13:0645d8841f51 55 void gpio_irq7(void) {handle_interrupt_in(7);}
bogdanm 13:0645d8841f51 56
bogdanm 13:0645d8841f51 57 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
bogdanm 13:0645d8841f51 58 if (pin == NC) return -1;
bogdanm 13:0645d8841f51 59
bogdanm 13:0645d8841f51 60 irq_handler = handler;
bogdanm 13:0645d8841f51 61
bogdanm 13:0645d8841f51 62 int found_free_channel = 0;
bogdanm 13:0645d8841f51 63 int i = 0;
bogdanm 13:0645d8841f51 64 for (i=0; i<CHANNEL_NUM; i++) {
bogdanm 13:0645d8841f51 65 if (channel_ids[i] == 0) {
bogdanm 13:0645d8841f51 66 channel_ids[i] = id;
bogdanm 13:0645d8841f51 67 obj->ch = i;
bogdanm 13:0645d8841f51 68 found_free_channel = 1;
bogdanm 13:0645d8841f51 69 break;
bogdanm 13:0645d8841f51 70 }
bogdanm 13:0645d8841f51 71 }
bogdanm 13:0645d8841f51 72 if (!found_free_channel) return -1;
bogdanm 13:0645d8841f51 73
bogdanm 13:0645d8841f51 74 /* Enable AHB clock to the GPIO domain. */
bogdanm 13:0645d8841f51 75 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
bogdanm 13:0645d8841f51 76
bogdanm 13:0645d8841f51 77 /* Enable AHB clock to the FlexInt, GroupedInt domain. */
bogdanm 13:0645d8841f51 78 LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24));
bogdanm 13:0645d8841f51 79
bogdanm 13:0645d8841f51 80 /* To select a pin for any of the eight pin interrupts, write the pin number
bogdanm 13:0645d8841f51 81 * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
bogdanm 13:0645d8841f51 82 * @see: mbed_capi/PinNames.h
bogdanm 13:0645d8841f51 83 */
bogdanm 13:0645d8841f51 84 LPC_SYSCON->PINSEL[obj->ch] = (pin >> 5) ? (pin - 8) : (pin);
bogdanm 13:0645d8841f51 85
bogdanm 13:0645d8841f51 86 // Interrupt Wake-Up Enable
bogdanm 13:0645d8841f51 87 LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
bogdanm 13:0645d8841f51 88
bogdanm 13:0645d8841f51 89 void (*channels_irq)(void) = NULL;
bogdanm 13:0645d8841f51 90 switch (obj->ch) {
bogdanm 13:0645d8841f51 91 case 0: channels_irq = &gpio_irq0; break;
bogdanm 13:0645d8841f51 92 case 1: channels_irq = &gpio_irq1; break;
bogdanm 13:0645d8841f51 93 case 2: channels_irq = &gpio_irq2; break;
bogdanm 13:0645d8841f51 94 case 3: channels_irq = &gpio_irq3; break;
bogdanm 13:0645d8841f51 95 case 4: channels_irq = &gpio_irq4; break;
bogdanm 13:0645d8841f51 96 case 5: channels_irq = &gpio_irq5; break;
bogdanm 13:0645d8841f51 97 case 6: channels_irq = &gpio_irq6; break;
bogdanm 13:0645d8841f51 98 case 7: channels_irq = &gpio_irq7; break;
bogdanm 13:0645d8841f51 99 }
bogdanm 13:0645d8841f51 100 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
bogdanm 13:0645d8841f51 101 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
bogdanm 13:0645d8841f51 102
bogdanm 13:0645d8841f51 103 return 0;
bogdanm 13:0645d8841f51 104 }
bogdanm 13:0645d8841f51 105
bogdanm 13:0645d8841f51 106 void gpio_irq_free(gpio_irq_t *obj) {
bogdanm 13:0645d8841f51 107 channel_ids[obj->ch] = 0;
bogdanm 13:0645d8841f51 108 LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
bogdanm 13:0645d8841f51 109 }
bogdanm 13:0645d8841f51 110
bogdanm 13:0645d8841f51 111 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
bogdanm 13:0645d8841f51 112 unsigned int ch_bit = (1 << obj->ch);
bogdanm 13:0645d8841f51 113
bogdanm 13:0645d8841f51 114 // Clear interrupt
bogdanm 13:0645d8841f51 115 if (!(LPC_GPIO_X->ISEL & ch_bit))
bogdanm 13:0645d8841f51 116 LPC_GPIO_X->IST = ch_bit;
bogdanm 13:0645d8841f51 117
bogdanm 13:0645d8841f51 118 // Edge trigger
bogdanm 13:0645d8841f51 119 LPC_GPIO_X->ISEL &= ~ch_bit;
bogdanm 13:0645d8841f51 120 if (event == IRQ_RISE) {
bogdanm 13:0645d8841f51 121 if (enable) {
bogdanm 13:0645d8841f51 122 LPC_GPIO_X->IENR |= ch_bit;
bogdanm 13:0645d8841f51 123 } else {
bogdanm 13:0645d8841f51 124 LPC_GPIO_X->IENR &= ~ch_bit;
bogdanm 13:0645d8841f51 125 }
bogdanm 13:0645d8841f51 126 } else {
bogdanm 13:0645d8841f51 127 if (enable) {
bogdanm 13:0645d8841f51 128 LPC_GPIO_X->IENF |= ch_bit;
bogdanm 13:0645d8841f51 129 } else {
bogdanm 13:0645d8841f51 130 LPC_GPIO_X->IENF &= ~ch_bit;
bogdanm 13:0645d8841f51 131 }
bogdanm 13:0645d8841f51 132 }
bogdanm 13:0645d8841f51 133 }