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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_NXP/TARGET_LPC81X/spi_api.c@13:0645d8841f51, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 14:12:34 2013 +0300
Revision:
13:0645d8841f51
Parent:
vendor/NXP/LPC812/hal/spi_api.c@10:3bc89ef62ce7 
Update mbed sources to revision 64

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #include <math.h>
emilmont 10:3bc89ef62ce7 17
emilmont 10:3bc89ef62ce7 18 #include "spi_api.h"
emilmont 10:3bc89ef62ce7 19 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 20 #include "pinmap.h"
emilmont 10:3bc89ef62ce7 21 #include "error.h"
emilmont 10:3bc89ef62ce7 22
emilmont 10:3bc89ef62ce7 23 static const SWM_Map SWM_SPI_SSEL[] = {
emilmont 10:3bc89ef62ce7 24 {4, 16},
emilmont 10:3bc89ef62ce7 25 {5, 16},
emilmont 10:3bc89ef62ce7 26 };
emilmont 10:3bc89ef62ce7 27
emilmont 10:3bc89ef62ce7 28 static const SWM_Map SWM_SPI_SCLK[] = {
emilmont 10:3bc89ef62ce7 29 {3, 24},
emilmont 10:3bc89ef62ce7 30 {4, 24},
emilmont 10:3bc89ef62ce7 31 };
emilmont 10:3bc89ef62ce7 32
emilmont 10:3bc89ef62ce7 33 static const SWM_Map SWM_SPI_MOSI[] = {
emilmont 10:3bc89ef62ce7 34 {4, 0},
emilmont 10:3bc89ef62ce7 35 {5, 0},
emilmont 10:3bc89ef62ce7 36 };
emilmont 10:3bc89ef62ce7 37
emilmont 10:3bc89ef62ce7 38 static const SWM_Map SWM_SPI_MISO[] = {
emilmont 10:3bc89ef62ce7 39 {4, 8},
emilmont 10:3bc89ef62ce7 40 {5, 16},
emilmont 10:3bc89ef62ce7 41 };
emilmont 10:3bc89ef62ce7 42
emilmont 10:3bc89ef62ce7 43 // bit flags for used SPIs
emilmont 10:3bc89ef62ce7 44 static unsigned char spi_used = 0;
emilmont 10:3bc89ef62ce7 45 static int get_available_spi(void) {
emilmont 10:3bc89ef62ce7 46 int i;
emilmont 10:3bc89ef62ce7 47 for (i=0; i<2; i++) {
emilmont 10:3bc89ef62ce7 48 if ((spi_used & (1 << i)) == 0)
emilmont 10:3bc89ef62ce7 49 return i;
emilmont 10:3bc89ef62ce7 50 }
emilmont 10:3bc89ef62ce7 51 return -1;
emilmont 10:3bc89ef62ce7 52 }
emilmont 10:3bc89ef62ce7 53
emilmont 10:3bc89ef62ce7 54 static inline int ssp_disable(spi_t *obj);
emilmont 10:3bc89ef62ce7 55 static inline int ssp_enable(spi_t *obj);
emilmont 10:3bc89ef62ce7 56
emilmont 10:3bc89ef62ce7 57 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
emilmont 10:3bc89ef62ce7 58 int spi_n = get_available_spi();
emilmont 10:3bc89ef62ce7 59 if (spi_n == -1) {
emilmont 10:3bc89ef62ce7 60 error("No available SPI");
emilmont 10:3bc89ef62ce7 61 }
emilmont 10:3bc89ef62ce7 62 obj->spi_n = spi_n;
emilmont 10:3bc89ef62ce7 63 spi_used |= (1 << spi_n);
emilmont 10:3bc89ef62ce7 64
emilmont 10:3bc89ef62ce7 65 obj->spi = (spi_n) ? (LPC_SPI_TypeDef *)(LPC_SPI1_BASE) : (LPC_SPI_TypeDef *)(LPC_SPI0_BASE);
emilmont 10:3bc89ef62ce7 66
emilmont 10:3bc89ef62ce7 67 const SWM_Map *swm;
emilmont 10:3bc89ef62ce7 68 uint32_t regVal;
emilmont 10:3bc89ef62ce7 69
emilmont 10:3bc89ef62ce7 70 swm = &SWM_SPI_SCLK[obj->spi_n];
emilmont 10:3bc89ef62ce7 71 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
emilmont 10:3bc89ef62ce7 72 LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset);
emilmont 10:3bc89ef62ce7 73
emilmont 10:3bc89ef62ce7 74 swm = &SWM_SPI_MOSI[obj->spi_n];
emilmont 10:3bc89ef62ce7 75 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
emilmont 10:3bc89ef62ce7 76 LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset);
emilmont 10:3bc89ef62ce7 77
emilmont 10:3bc89ef62ce7 78 swm = &SWM_SPI_MISO[obj->spi_n];
emilmont 10:3bc89ef62ce7 79 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
emilmont 10:3bc89ef62ce7 80 LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset);
emilmont 10:3bc89ef62ce7 81
emilmont 10:3bc89ef62ce7 82 swm = &SWM_SPI_SSEL[obj->spi_n];
emilmont 10:3bc89ef62ce7 83 regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
emilmont 10:3bc89ef62ce7 84 LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset);
emilmont 10:3bc89ef62ce7 85
emilmont 10:3bc89ef62ce7 86 // clear interrupts
emilmont 10:3bc89ef62ce7 87 obj->spi->INTENCLR = 0x3f;
emilmont 10:3bc89ef62ce7 88
emilmont 10:3bc89ef62ce7 89 // enable power and clocking
emilmont 10:3bc89ef62ce7 90 switch (obj->spi_n) {
emilmont 10:3bc89ef62ce7 91 case 0:
emilmont 10:3bc89ef62ce7 92 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11);
emilmont 10:3bc89ef62ce7 93 LPC_SYSCON->PRESETCTRL &= ~(0x1<<0);
emilmont 10:3bc89ef62ce7 94 LPC_SYSCON->PRESETCTRL |= (0x1<<0);
emilmont 10:3bc89ef62ce7 95 break;
emilmont 10:3bc89ef62ce7 96 case 1:
emilmont 10:3bc89ef62ce7 97 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
emilmont 10:3bc89ef62ce7 98 LPC_SYSCON->PRESETCTRL &= ~(0x1<<1);
emilmont 10:3bc89ef62ce7 99 LPC_SYSCON->PRESETCTRL |= (0x1<<1);
emilmont 10:3bc89ef62ce7 100 break;
emilmont 10:3bc89ef62ce7 101 }
emilmont 10:3bc89ef62ce7 102
emilmont 10:3bc89ef62ce7 103 // set default format and frequency
emilmont 10:3bc89ef62ce7 104 if (ssel == NC) {
emilmont 10:3bc89ef62ce7 105 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
emilmont 10:3bc89ef62ce7 106 } else {
emilmont 10:3bc89ef62ce7 107 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
emilmont 10:3bc89ef62ce7 108 }
emilmont 10:3bc89ef62ce7 109 spi_frequency(obj, 1000000);
emilmont 10:3bc89ef62ce7 110
emilmont 10:3bc89ef62ce7 111 // enable the ssp channel
emilmont 10:3bc89ef62ce7 112 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 113 }
emilmont 10:3bc89ef62ce7 114
emilmont 10:3bc89ef62ce7 115 void spi_free(spi_t *obj) {}
emilmont 10:3bc89ef62ce7 116
emilmont 10:3bc89ef62ce7 117 void spi_format(spi_t *obj, int bits, int mode, int slave) {
emilmont 10:3bc89ef62ce7 118 ssp_disable(obj);
emilmont 10:3bc89ef62ce7 119
emilmont 10:3bc89ef62ce7 120 if (!(bits >= 1 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
emilmont 10:3bc89ef62ce7 121 error("SPI format error");
emilmont 10:3bc89ef62ce7 122 }
emilmont 10:3bc89ef62ce7 123
emilmont 10:3bc89ef62ce7 124
emilmont 10:3bc89ef62ce7 125 int polarity = (mode & 0x2) ? 1 : 0;
emilmont 10:3bc89ef62ce7 126 int phase = (mode & 0x1) ? 1 : 0;
emilmont 10:3bc89ef62ce7 127
emilmont 10:3bc89ef62ce7 128 // set it up
emilmont 10:3bc89ef62ce7 129 int DSS = bits - 1; // DSS (data select size)
emilmont 10:3bc89ef62ce7 130 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
emilmont 10:3bc89ef62ce7 131 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
emilmont 10:3bc89ef62ce7 132
emilmont 10:3bc89ef62ce7 133 uint32_t tmp = obj->spi->CFG;
emilmont 10:3bc89ef62ce7 134 tmp &= ~((1 << 2) | (1 << 4) | (1 << 5));
emilmont 10:3bc89ef62ce7 135 tmp |= (SPH << 4) | (SPO << 5) | ((slave ? 0 : 1) << 2);
emilmont 10:3bc89ef62ce7 136 obj->spi->CFG = tmp;
emilmont 10:3bc89ef62ce7 137
emilmont 10:3bc89ef62ce7 138 // select frame length
emilmont 10:3bc89ef62ce7 139 tmp = obj->spi->TXDATCTL;
emilmont 10:3bc89ef62ce7 140 tmp &= ~(0xf << 24);
emilmont 10:3bc89ef62ce7 141 tmp |= (DSS << 24);
emilmont 10:3bc89ef62ce7 142 obj->spi->TXDATCTL = tmp;
emilmont 10:3bc89ef62ce7 143
emilmont 10:3bc89ef62ce7 144 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 145 }
emilmont 10:3bc89ef62ce7 146
emilmont 10:3bc89ef62ce7 147 void spi_frequency(spi_t *obj, int hz) {
emilmont 10:3bc89ef62ce7 148 ssp_disable(obj);
emilmont 10:3bc89ef62ce7 149
emilmont 10:3bc89ef62ce7 150 uint32_t PCLK = SystemCoreClock;
emilmont 10:3bc89ef62ce7 151
emilmont 10:3bc89ef62ce7 152 obj->spi->DIV = PCLK/hz - 1;
emilmont 10:3bc89ef62ce7 153 obj->spi->DLY = 0;
emilmont 10:3bc89ef62ce7 154 ssp_enable(obj);
emilmont 10:3bc89ef62ce7 155 }
emilmont 10:3bc89ef62ce7 156
emilmont 10:3bc89ef62ce7 157 static inline int ssp_disable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 158 return obj->spi->CFG &= ~(1 << 0);
emilmont 10:3bc89ef62ce7 159 }
emilmont 10:3bc89ef62ce7 160
emilmont 10:3bc89ef62ce7 161 static inline int ssp_enable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 162 return obj->spi->CFG |= (1 << 0);
emilmont 10:3bc89ef62ce7 163 }
emilmont 10:3bc89ef62ce7 164
emilmont 10:3bc89ef62ce7 165 static inline int ssp_readable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 166 return obj->spi->STAT & (1 << 0);
emilmont 10:3bc89ef62ce7 167 }
emilmont 10:3bc89ef62ce7 168
emilmont 10:3bc89ef62ce7 169 static inline int ssp_writeable(spi_t *obj) {
emilmont 10:3bc89ef62ce7 170 return obj->spi->STAT & (1 << 1);
emilmont 10:3bc89ef62ce7 171 }
emilmont 10:3bc89ef62ce7 172
emilmont 10:3bc89ef62ce7 173 static inline void ssp_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 174 while (!ssp_writeable(obj));
emilmont 10:3bc89ef62ce7 175 // end of transfer
emilmont 10:3bc89ef62ce7 176 obj->spi->TXDATCTL |= (1 << 20);
emilmont 10:3bc89ef62ce7 177 obj->spi->TXDAT = value;
emilmont 10:3bc89ef62ce7 178 }
emilmont 10:3bc89ef62ce7 179
emilmont 10:3bc89ef62ce7 180 static inline int ssp_read(spi_t *obj) {
emilmont 10:3bc89ef62ce7 181 while (!ssp_readable(obj));
emilmont 10:3bc89ef62ce7 182 return obj->spi->RXDAT;
emilmont 10:3bc89ef62ce7 183 }
emilmont 10:3bc89ef62ce7 184
emilmont 10:3bc89ef62ce7 185 static inline int ssp_busy(spi_t *obj) {
emilmont 10:3bc89ef62ce7 186 // TODO
emilmont 10:3bc89ef62ce7 187 return 0;
emilmont 10:3bc89ef62ce7 188 }
emilmont 10:3bc89ef62ce7 189
emilmont 10:3bc89ef62ce7 190 int spi_master_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 191 ssp_write(obj, value);
emilmont 10:3bc89ef62ce7 192 return ssp_read(obj);
emilmont 10:3bc89ef62ce7 193 }
emilmont 10:3bc89ef62ce7 194
emilmont 10:3bc89ef62ce7 195 int spi_slave_receive(spi_t *obj) {
emilmont 10:3bc89ef62ce7 196 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
emilmont 10:3bc89ef62ce7 197 };
emilmont 10:3bc89ef62ce7 198
emilmont 10:3bc89ef62ce7 199 int spi_slave_read(spi_t *obj) {
emilmont 10:3bc89ef62ce7 200 return obj->spi->RXDAT;
emilmont 10:3bc89ef62ce7 201 }
emilmont 10:3bc89ef62ce7 202
emilmont 10:3bc89ef62ce7 203 void spi_slave_write(spi_t *obj, int value) {
emilmont 10:3bc89ef62ce7 204 while (ssp_writeable(obj) == 0) ;
emilmont 10:3bc89ef62ce7 205 obj->spi->TXDAT = value;
emilmont 10:3bc89ef62ce7 206 }
emilmont 10:3bc89ef62ce7 207
emilmont 10:3bc89ef62ce7 208 int spi_busy(spi_t *obj) {
emilmont 10:3bc89ef62ce7 209 return ssp_busy(obj);
emilmont 10:3bc89ef62ce7 210 }