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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c@13:0645d8841f51, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 14:12:34 2013 +0300
Revision:
13:0645d8841f51
Parent:
vendor/NXP/LPC812/hal/gpio_irq_api.c@10:3bc89ef62ce7 
Update mbed sources to revision 64

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #include <stddef.h>
emilmont 10:3bc89ef62ce7 17
emilmont 10:3bc89ef62ce7 18 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 19 #include "gpio_irq_api.h"
emilmont 10:3bc89ef62ce7 20 #include "error.h"
emilmont 10:3bc89ef62ce7 21
emilmont 10:3bc89ef62ce7 22 #define CHANNEL_NUM 8
emilmont 10:3bc89ef62ce7 23 #define LPC_GPIO_X LPC_PIN_INT
emilmont 10:3bc89ef62ce7 24 #define PININT_IRQ PININT0_IRQn
emilmont 10:3bc89ef62ce7 25
emilmont 10:3bc89ef62ce7 26 static uint32_t channel_ids[CHANNEL_NUM] = {0};
emilmont 10:3bc89ef62ce7 27 static gpio_irq_handler irq_handler;
emilmont 10:3bc89ef62ce7 28
emilmont 10:3bc89ef62ce7 29 static inline void handle_interrupt_in(uint32_t channel) {
emilmont 10:3bc89ef62ce7 30 uint32_t ch_bit = (1 << channel);
emilmont 10:3bc89ef62ce7 31 // Return immediately if:
emilmont 10:3bc89ef62ce7 32 // * The interrupt was already served
emilmont 10:3bc89ef62ce7 33 // * There is no user handler
emilmont 10:3bc89ef62ce7 34 // * It is a level interrupt, not an edge interrupt
emilmont 10:3bc89ef62ce7 35 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
emilmont 10:3bc89ef62ce7 36 (channel_ids[channel] == 0 ) ||
emilmont 10:3bc89ef62ce7 37 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
emilmont 10:3bc89ef62ce7 38
emilmont 10:3bc89ef62ce7 39 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
emilmont 10:3bc89ef62ce7 40 irq_handler(channel_ids[channel], IRQ_RISE);
emilmont 10:3bc89ef62ce7 41 LPC_GPIO_X->RISE = ch_bit;
emilmont 10:3bc89ef62ce7 42 }
emilmont 10:3bc89ef62ce7 43 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
emilmont 10:3bc89ef62ce7 44 irq_handler(channel_ids[channel], IRQ_FALL);
emilmont 10:3bc89ef62ce7 45 }
emilmont 10:3bc89ef62ce7 46 LPC_GPIO_X->IST = ch_bit;
emilmont 10:3bc89ef62ce7 47 }
emilmont 10:3bc89ef62ce7 48
emilmont 10:3bc89ef62ce7 49 void gpio_irq0(void) {handle_interrupt_in(0);}
emilmont 10:3bc89ef62ce7 50 void gpio_irq1(void) {handle_interrupt_in(1);}
emilmont 10:3bc89ef62ce7 51 void gpio_irq2(void) {handle_interrupt_in(2);}
emilmont 10:3bc89ef62ce7 52 void gpio_irq3(void) {handle_interrupt_in(3);}
emilmont 10:3bc89ef62ce7 53 void gpio_irq4(void) {handle_interrupt_in(4);}
emilmont 10:3bc89ef62ce7 54 void gpio_irq5(void) {handle_interrupt_in(5);}
emilmont 10:3bc89ef62ce7 55 void gpio_irq6(void) {handle_interrupt_in(6);}
emilmont 10:3bc89ef62ce7 56 void gpio_irq7(void) {handle_interrupt_in(7);}
emilmont 10:3bc89ef62ce7 57
emilmont 10:3bc89ef62ce7 58 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
emilmont 10:3bc89ef62ce7 59 if (pin == NC) return -1;
emilmont 10:3bc89ef62ce7 60
emilmont 10:3bc89ef62ce7 61 irq_handler = handler;
emilmont 10:3bc89ef62ce7 62
emilmont 10:3bc89ef62ce7 63 int found_free_channel = 0;
emilmont 10:3bc89ef62ce7 64 int i = 0;
emilmont 10:3bc89ef62ce7 65 for (i=0; i<CHANNEL_NUM; i++) {
emilmont 10:3bc89ef62ce7 66 if (channel_ids[i] == 0) {
emilmont 10:3bc89ef62ce7 67 channel_ids[i] = id;
emilmont 10:3bc89ef62ce7 68 obj->ch = i;
emilmont 10:3bc89ef62ce7 69 found_free_channel = 1;
emilmont 10:3bc89ef62ce7 70 break;
emilmont 10:3bc89ef62ce7 71 }
emilmont 10:3bc89ef62ce7 72 }
emilmont 10:3bc89ef62ce7 73 if (!found_free_channel) return -1;
emilmont 10:3bc89ef62ce7 74
emilmont 10:3bc89ef62ce7 75 /* Enable AHB clock to the GPIO domain. */
emilmont 10:3bc89ef62ce7 76 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
emilmont 10:3bc89ef62ce7 77
emilmont 10:3bc89ef62ce7 78 LPC_SYSCON->PINTSEL[obj->ch] = pin;
emilmont 10:3bc89ef62ce7 79
emilmont 10:3bc89ef62ce7 80 // Interrupt Wake-Up Enable
emilmont 10:3bc89ef62ce7 81 LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
emilmont 10:3bc89ef62ce7 82
emilmont 10:3bc89ef62ce7 83 void (*channels_irq)(void) = NULL;
emilmont 10:3bc89ef62ce7 84 switch (obj->ch) {
emilmont 10:3bc89ef62ce7 85 case 0: channels_irq = &gpio_irq0; break;
emilmont 10:3bc89ef62ce7 86 case 1: channels_irq = &gpio_irq1; break;
emilmont 10:3bc89ef62ce7 87 case 2: channels_irq = &gpio_irq2; break;
emilmont 10:3bc89ef62ce7 88 case 3: channels_irq = &gpio_irq3; break;
emilmont 10:3bc89ef62ce7 89 case 4: channels_irq = &gpio_irq4; break;
emilmont 10:3bc89ef62ce7 90 case 5: channels_irq = &gpio_irq5; break;
emilmont 10:3bc89ef62ce7 91 case 6: channels_irq = &gpio_irq6; break;
emilmont 10:3bc89ef62ce7 92 case 7: channels_irq = &gpio_irq7; break;
emilmont 10:3bc89ef62ce7 93 }
emilmont 10:3bc89ef62ce7 94 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
emilmont 10:3bc89ef62ce7 95 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
emilmont 10:3bc89ef62ce7 96
emilmont 10:3bc89ef62ce7 97 return 0;
emilmont 10:3bc89ef62ce7 98 }
emilmont 10:3bc89ef62ce7 99
emilmont 10:3bc89ef62ce7 100 void gpio_irq_free(gpio_irq_t *obj) {
emilmont 10:3bc89ef62ce7 101 channel_ids[obj->ch] = 0;
emilmont 10:3bc89ef62ce7 102 LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
emilmont 10:3bc89ef62ce7 103 }
emilmont 10:3bc89ef62ce7 104
emilmont 10:3bc89ef62ce7 105 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
emilmont 10:3bc89ef62ce7 106 unsigned int ch_bit = (1 << obj->ch);
emilmont 10:3bc89ef62ce7 107
emilmont 10:3bc89ef62ce7 108 // Clear interrupt
emilmont 10:3bc89ef62ce7 109 if (!(LPC_GPIO_X->ISEL & ch_bit))
emilmont 10:3bc89ef62ce7 110 LPC_GPIO_X->IST = ch_bit;
emilmont 10:3bc89ef62ce7 111
emilmont 10:3bc89ef62ce7 112 // Edge trigger
emilmont 10:3bc89ef62ce7 113 LPC_GPIO_X->ISEL &= ~ch_bit;
emilmont 10:3bc89ef62ce7 114 if (event == IRQ_RISE) {
emilmont 10:3bc89ef62ce7 115 if (enable) {
emilmont 10:3bc89ef62ce7 116 LPC_GPIO_X->IENR |= ch_bit;
emilmont 10:3bc89ef62ce7 117 } else {
emilmont 10:3bc89ef62ce7 118 LPC_GPIO_X->IENR &= ~ch_bit;
emilmont 10:3bc89ef62ce7 119 }
emilmont 10:3bc89ef62ce7 120 } else {
emilmont 10:3bc89ef62ce7 121 if (enable) {
emilmont 10:3bc89ef62ce7 122 LPC_GPIO_X->IENF |= ch_bit;
emilmont 10:3bc89ef62ce7 123 } else {
emilmont 10:3bc89ef62ce7 124 LPC_GPIO_X->IENF &= ~ch_bit;
emilmont 10:3bc89ef62ce7 125 }
emilmont 10:3bc89ef62ce7 126 }
emilmont 10:3bc89ef62ce7 127 }