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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.
Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.
If you are looking for a stable and tested release, please import one of the official mbed library releases:
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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Last commit 20 Feb 2019 by 
mbed official
Revision 630:825f75ca301e, committed 2015-09-28
- Comitter:
- mbed_official
- Date:
- Mon Sep 28 10:45:10 2015 +0100
- Parent:
- 629:1806c2edb763
- Child:
- 631:ff681937ffd8
- Commit message:
- Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10
Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/
NUCLEO_F031K6 : Add new target
Changed in this revision
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis.h Mon Sep 28 10:45:10 2015 +0100 @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * A generic CMSIS include header ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.c Mon Sep 28 10:45:10 2015 +0100
@@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -33,10 +33,10 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
-static unsigned char vtor_remap = 0; // To keep track that the vectors remap is done
-
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
int i;
+ // To keep track that the vectors remap is done
+ static volatile uint32_t vtor_remap = 0;
// Space for dynamic vectors, initialised to allocate in R/W
static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.h Mon Sep 28 10:45:10 2015 +0100 @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f051x8.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 03-Oct-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS STM32F051x4/STM32F051x6/STM32F051x8 devices Peripheral Access
* Layer Header File.
*
@@ -15,7 +15,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -60,7 +60,6 @@
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
-
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
@@ -284,14 +283,12 @@
*/
typedef struct
{
- __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
- __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
- __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
- __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
- __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
- __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
- __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
- __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
+ __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
+ __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
+ __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
+ __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
}OB_TypeDef;
/**
@@ -369,6 +366,7 @@
/**
* @brief Reset and Clock Control
*/
+
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
@@ -390,7 +388,6 @@
/**
* @brief Real-Time Clock
*/
-
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
@@ -426,24 +423,15 @@
typedef struct
{
- __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
}SPI_TypeDef;
/**
@@ -535,6 +523,7 @@
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0800FFFF) /*!< FLASH END address of bank1 */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
@@ -556,6 +545,7 @@
#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
+
#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
@@ -642,7 +632,6 @@
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-
/**
* @}
*/
@@ -782,7 +771,6 @@
#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
-
/******************************************************************************/
/* */
/* HDMI-CEC (CEC) */
@@ -841,7 +829,6 @@
#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
-
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
@@ -889,24 +876,24 @@
#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
/* COMPx bits definition */
-#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
-#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
-#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
-#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
-#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
-#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
-#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
-#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
-#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
-#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
-#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
-#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
-#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
-#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
-#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
-#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
-#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
+#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
+#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
+#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
+#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
+#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
+#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
+#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
+#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
/******************************************************************************/
/* */
@@ -929,7 +916,6 @@
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
-
/******************************************************************************/
/* */
/* Digital to Analog Converter (DAC) */
@@ -1266,8 +1252,8 @@
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
/****************** FLASH Keys **********************************************/
-#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
-#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
to unlock the write access to the FPEC. */
#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
@@ -1302,12 +1288,13 @@
#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
-#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
+#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
+#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
/* Old BOOT1 bit definition, maintained for legacy purpose */
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
@@ -2181,16 +2168,6 @@
#define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
#define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
-/*!< USART2 Clock source selection */
-#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
-#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
-#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
-#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
-#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
-
/******************* Bit definition for RCC_CR2 register *******************/
#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
@@ -2566,6 +2543,7 @@
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
@@ -2578,173 +2556,174 @@
#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+
/***************** Bit definition for SYSCFG_EXTICR1 register **************/
-#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
/**
* @brief EXTI1 configuration
*/
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
/**
* @brief EXTI2 configuration
*/
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
/**
* @brief EXTI3 configuration
*/
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register **************/
-#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
/**
* @brief EXTI5 configuration
*/
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
/**
* @brief EXTI6 configuration
*/
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
/**
* @brief EXTI7 configuration
*/
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register **************/
-#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
/**
* @brief EXTI9 configuration
*/
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
/**
* @brief EXTI10 configuration
*/
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
/**
* @brief EXTI11 configuration
*/
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register **************/
-#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
/**
* @brief EXTI13 configuration
*/
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
/**
* @brief EXTI14 configuration
*/
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
/**
* @brief EXTI15 configuration
*/
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
@@ -3497,13 +3476,15 @@
((INSTANCE) == DMA1_Channel5))
/****************************** GPIO Instances ********************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOF))
-
-/****************************** GPIO Lock Instances ****************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB))
+
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB))
@@ -3767,7 +3748,6 @@
/****************** UART Instances : Driver enable detection ********************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
-
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,10 +2,10 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
- * @version V2.1.0
- * @date 03-Oct-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
- *
+ *
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
@@ -14,11 +14,11 @@
* code will be based on direct access to peripherals registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
- *
+ *
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -59,21 +59,28 @@
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
-
+
/** @addtogroup Library_configuration_section
* @{
*/
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F0)
+#define STM32F0
+#endif /* STM32F0 */
+
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
!defined (STM32F031x6) && !defined (STM32F038xx) && \
- !defined (STM32F042x6) && !defined (STM32F048xx) && \
+ !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
!defined (STM32F051x8) && !defined (STM32F058xx) && \
- !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && \
- !defined (STM32F091xC) && !defined (STM32F098xx)
+ !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
+ !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
/* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
/* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
/* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
@@ -82,13 +89,16 @@
/* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
#define STM32F051x8 /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
/* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
/* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
/* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
/* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
+ /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
/* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
/* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
#endif
-
+
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
@@ -102,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.1.0
- */
+ * @brief CMSIS Device version number V2.2.2
+ */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
-#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
@@ -137,6 +147,10 @@
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
+#elif defined(STM32F070x6)
+ #include "stm32f070x6.h"
+#elif defined(STM32F070xB)
+ #include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
@@ -146,7 +160,9 @@
#elif defined(STM32F091xC)
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
- #include "stm32f098xx.h"
+ #include "stm32f098xx.h"
+#elif defined(STM32F030xC)
+ #include "stm32f030xc.h"
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
@@ -157,7 +173,7 @@
/** @addtogroup Exported_types
* @{
- */
+ */
typedef enum
{
RESET = 0,
@@ -177,7 +193,7 @@
SUCCESS = !ERROR
} ErrorStatus;
-/**
+/**
* @}
*/
@@ -186,13 +202,13 @@
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
-
+
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
-
+
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
@@ -203,7 +219,7 @@
/**
* @}
*/
-
+
#if defined (USE_HAL_DRIVER)
#include "stm32f0xx_hal.h"
#endif /* USE_HAL_DRIVER */
@@ -217,11 +233,11 @@
/**
* @}
*/
-
+
/**
* @}
*/
-
+
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,18 +2,18 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
- * @version V2.1.0
- * @date 03-Oct-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
- * 1. This file provides two functions and one global variable to be called from
- * user application:
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f0xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
+ * by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
@@ -42,7 +42,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -75,8 +75,8 @@
/** @addtogroup stm32f0xx_system
* @{
- */
-
+ */
+
/** @addtogroup STM32F0xx_System_Private_Includes
* @{
*/
@@ -107,6 +107,7 @@
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
+
/**
* @}
*/
@@ -134,7 +135,8 @@
call the 2 first functions listed above, since SystemCoreClock variable is
updated automatically.
*/
-uint32_t SystemCoreClock = 48000000;
+uint32_t SystemCoreClock = 48000000;
+
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
@@ -166,7 +168,7 @@
* @retval None
*/
void SystemInit(void)
-{
+{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
@@ -191,15 +193,31 @@
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB)
- /* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+#if defined (STM32F072xB) || defined (STM32F078xx)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
+#elif defined (STM32F071xB)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
#elif defined (STM32F091xC) || defined (STM32F098xx)
- /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
+ /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+ /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+ /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
+ /* Set default USB clock to PLLCLK, since there is no HSI48 */
+ RCC->CFGR3 |= (uint32_t)0x00000080;
#else
- /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
+ #warning "No target selected"
#endif
/* Reset HSI14 bit */
@@ -207,14 +225,6 @@
/* Disable all interrupts */
RCC->CIR = 0x00000000;
-
- /* Configure the Cube driver */
- SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
- HAL_Init();
-
- /* Configure the System clock source, PLL Multiplier and Divider factors,
- AHB/APBx prescalers and Flash settings */
- SetSysClock();
}
/**
@@ -225,16 +235,16 @@
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
+ * based on this variable will be incorrect.
*
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
+ *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
+ *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
@@ -259,7 +269,7 @@
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
-
+
switch (tmp)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
@@ -274,7 +284,7 @@
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
pllmull = ( pllmull >> 18) + 2;
predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-
+
if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
{
/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
@@ -289,14 +299,18 @@
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
else
{
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
+ || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
+ || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
#else
/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
- }
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
+ STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
+ STM32F091xC || STM32F098xx || STM32F030xC */
+ }
break;
default: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
@@ -306,7 +320,7 @@
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
- SystemCoreClock >>= tmp;
+ SystemCoreClock >>= tmp;
}
/**
@@ -339,7 +353,7 @@
}
}
}
-
+
// Output clock on MCO pin(PA8) for debugging purpose
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
}
@@ -350,25 +364,32 @@
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ //Select HSI as system clock source to allow modification of the PLL configuration
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
// Select HSE oscillator as PLL source
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
}
- RCC_OscInitStruct.HSI48State = 0; // not used
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
- }
-
+ }
+
// Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
@@ -376,9 +397,11 @@
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
return 0; // FAIL
- }
-
- return 1; // OK
+ }
+
+// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
+
+ return 1; // OK
}
#endif
@@ -389,10 +412,10 @@
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
-
+
// Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
@@ -400,7 +423,7 @@
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
-
+
// Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
@@ -410,6 +433,8 @@
return 0; // FAIL
}
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
+
return 1; // OK
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h Mon Sep 28 10:45:10 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.1.0 - * @date 03-Oct-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f030x8.icf Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f030x8.icf Mon Sep 28 10:45:10 2015 +0100
@@ -1,31 +1,34 @@
-/* [ROM = 64kb = 0x10000] */
-define symbol __intvec_start__ = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__ = 0x0800FFFF;
-
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
/* [RAM = 8kb = 0x2000] Vector table dynamic copy: 45 vectors = 180 bytes (0xB4) to be reserved in RAM */
-define symbol __NVIC_start__ = 0x20000000;
-define symbol __NVIC_end__ = 0x200000B7; /* Add 4 more bytes to be aligned on 8 bytes */
-define symbol __region_RAM_start__ = 0x200000B8;
-define symbol __region_RAM_end__ = 0x20001FFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x200000B8; /* Add 4 more bytes after NVIC section to be aligned on 8 bytes */
+define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x800;
+/**** End of ICF editor section. ###ICF###*/
-/* Memory regions */
define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-/* Stack and Heap */
-/*Heap 1/4 of ram and stack 1/8*/
-define symbol __size_cstack__ = 0x400;
-define symbol __size_heap__ = 0x800;
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-initialize by copy with packing = zeros { readwrite };
+initialize by copy { readwrite };
do not initialize { section .noinit };
-place at address mem:__intvec_start__ { readonly section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, block STACKHEAP };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f030x8.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 05-December-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS STM32F030x8 devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -59,7 +59,6 @@
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
-
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
@@ -236,14 +235,12 @@
*/
typedef struct
{
- __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
- __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
- __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
- __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
- __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
- __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
- __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
- __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
+ __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
+ __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
+ __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
+ __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
}OB_TypeDef;
/**
@@ -321,6 +318,7 @@
/**
* @brief Reset and Clock Control
*/
+
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
@@ -342,7 +340,6 @@
/**
* @brief Real-Time Clock
*/
-
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
@@ -410,7 +407,6 @@
__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
}TIM_TypeDef;
-
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
@@ -451,6 +447,7 @@
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0800FFFF) /*!< FLASH END address of bank1 */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
@@ -545,7 +542,6 @@
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-
/**
* @}
*/
@@ -681,7 +677,6 @@
#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
/******************* Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
@@ -994,8 +989,8 @@
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
/****************** FLASH Keys **********************************************/
-#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
-#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
to unlock the write access to the FPEC. */
#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
@@ -1030,12 +1025,13 @@
#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
-#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
+#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
+#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
/* Old BOOT1 bit definition, maintained for legacy purpose */
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
@@ -1560,6 +1556,7 @@
/******************* Bit definition for PWR_CSR register *******************/
#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+
#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
@@ -1873,16 +1870,6 @@
#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
-/*!< USART2 Clock source selection */
-#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
-#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
-#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
-#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
-#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
-
/******************* Bit definition for RCC_CR2 register *******************/
#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
@@ -2240,6 +2227,7 @@
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
@@ -2252,173 +2240,174 @@
#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+
/***************** Bit definition for SYSCFG_EXTICR1 register **************/
-#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
/**
* @brief EXTI1 configuration
*/
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
/**
* @brief EXTI2 configuration
*/
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
/**
* @brief EXTI3 configuration
*/
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register **************/
-#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
/**
* @brief EXTI5 configuration
*/
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
/**
* @brief EXTI6 configuration
*/
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
/**
* @brief EXTI7 configuration
*/
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register **************/
-#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
/**
* @brief EXTI9 configuration
*/
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
/**
* @brief EXTI10 configuration
*/
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
/**
* @brief EXTI11 configuration
*/
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register **************/
-#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
/**
* @brief EXTI13 configuration
*/
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
/**
* @brief EXTI14 configuration
*/
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
/**
* @brief EXTI15 configuration
*/
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
@@ -2724,7 +2713,6 @@
#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
@@ -2958,6 +2946,7 @@
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -3168,7 +3157,6 @@
/****************** UART Instances : Driver enable detection ********************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
-
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f0xx.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f0xx.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 05-December-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,6 +63,13 @@
/** @addtogroup Library_configuration_section
* @{
*/
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F0)
+#define STM32F0
+#endif /* STM32F0 */
/* Uncomment the line below according to the target STM32 device used in your
application
@@ -105,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.2.0
+ * @brief CMSIS Device version number V2.2.2
*/
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
- * @version V2.2.0
- * @date 05-December-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@@ -42,7 +42,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -107,6 +107,7 @@
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
+
/**
* @}
*/
@@ -192,7 +193,7 @@
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-#if defined (STM32F072xB) || defined (STM32F078xB)
+#if defined (STM32F072xB) || defined (STM32F078xx)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
#elif defined (STM32F071xB)
@@ -224,14 +225,6 @@
/* Disable all interrupts */
RCC->CIR = 0x00000000;
-
- /* Configure the Cube driver */
- SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
- HAL_Init();
-
- /* Configure the System clock source, PLL Multiplier and Divider factors,
- AHB/APBx prescalers and Flash settings */
- SetSysClock();
}
/**
@@ -306,9 +299,9 @@
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
else
{
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
+ || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
+ || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
#else
@@ -362,7 +355,7 @@
}
// Output clock on MCO pin(PA8) for debugging purpose
- //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
+ // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
}
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
@@ -371,17 +364,24 @@
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ //Select HSI as system clock source to allow modification of the PLL configuration
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
// Select HSE oscillator as PLL source
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
}
- RCC_OscInitStruct.HSI48State = 0; // not used
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
@@ -399,6 +399,8 @@
return 0; // FAIL
}
+// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
+
return 1; // OK
}
#endif
@@ -413,7 +415,7 @@
// Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
@@ -431,6 +433,8 @@
return 0; // FAIL
}
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
+
return 1; // OK
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h Mon Sep 28 10:45:10 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.s Mon Sep 28 10:45:10 2015 +0100 @@ -0,0 +1,226 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f031x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20001000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 32KB FLASH (0x8000) + 4KB RAM (0x1000)
+
+ LR_IROM1 0x08000000 0x8000 { ; load region size_region
+ ER_IROM1 0x08000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+; 44 vectors = 176 bytes (0xB0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xB0) (0x1000-0xB0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/sys.cpp Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/startup_stm32f031x6.s Mon Sep 28 10:45:10 2015 +0100 @@ -0,0 +1,199 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f031x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20001000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/stm32f0xx.sct Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2014, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 32KB FLASH (0x8000) + 4KB RAM (0x1000)
+
+ LR_IROM1 0x08000000 0x8000 { ; load region size_region
+ ER_IROM1 0x08000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+; 44 vectors = 176 bytes (0xB0) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0xB0) (0x1000-0xB0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/sys.cpp Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_GCC_ARM/STM32F031X6.ld Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32k
+ RAM (xrw) : ORIGIN = 0x200000B0, LENGTH = 4k - 0x0B0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.s Mon Sep 28 10:45:10 2015 +0100 @@ -0,0 +1,279 @@ +/** + ****************************************************************************** + * @file startup_stm32f031x6.s + * @author MCD Application Team + * @version V2.2.2 + * @date 26-June-2015 + * @brief STM32F031x4/STM32F031x6 devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ +// bl main + bl _start + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* Reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* Reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word 0 /* Reserved */ + .word SPI1_IRQHandler /* SPI1 */ + .word 0 /* Reserved */ + .word USART1_IRQHandler /* USART1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_IAR/startup_stm32f031x6.s Mon Sep 28 10:45:10 2015 +0100 @@ -0,0 +1,272 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f031x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F031x4/STM32F031x6 devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address, +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* +;* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Channel4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_IRQHandler + B DMA1_Channel4_5_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_IAR/stm32f031x6.icf Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x08007FFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x200000B0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/cmsis.h Mon Sep 28 10:45:10 2015 +0100 @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32f0xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/cmsis_nvic.c Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ int i;
+ // To keep track that the vectors remap is done
+ static volatile uint32_t vtor_remap = 0;
+ // Space for dynamic vectors, initialised to allocate in R/W
+ static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
+
+ // Copy and switch to dynamic vectors if first time called
+ if (vtor_remap == 0) {
+ uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
+ for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
+ vtor_remap = 1; // The vectors remap is done
+ }
+
+ // Set the vector
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ // Return the vector
+ return vectors[IRQn + 16];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/cmsis_nvic.h Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F031K6
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 28 vectors = 112 bytes from 0x40 to 0xAF
+// Total: 44 vectors = 176 bytes (0xB0) to be reserved in RAM
+#define NVIC_NUM_VECTORS 44
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/hal_tick.c Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,122 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.c
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#include "hal_tick.h"
+
+TIM_HandleTypeDef TimMasterHandle;
+uint32_t PreviousVal = 0;
+
+void us_ticker_irq_handler(void);
+
+void timer_irq_handler(void) {
+ // Channel 1 for mbed timeout
+ if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
+ us_ticker_irq_handler();
+ }
+
+ // Channel 2 for HAL tick
+ if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
+ __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
+ uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
+ if ((val - PreviousVal) >= HAL_TICK_DELAY) {
+ // Increment HAL variable
+ HAL_IncTick();
+ // Prepare next interrupt
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
+ PreviousVal = val;
+#if 0 // For DEBUG only
+ HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
+#endif
+ }
+ }
+}
+
+// Reconfigure the HAL tick using a standard timer instead of systick.
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
+ // Enable timer clock
+ TIM_MST_RCC;
+
+ // Reset timer
+ TIM_MST_RESET_ON;
+ TIM_MST_RESET_OFF;
+
+ // Update the SystemCoreClock variable
+ SystemCoreClockUpdate();
+
+ // Configure time base
+ TimMasterHandle.Instance = TIM_MST;
+ TimMasterHandle.Init.Period = 0xFFFFFFFF;
+ TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
+ TimMasterHandle.Init.ClockDivision = 0;
+ TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ TimMasterHandle.Init.RepetitionCounter = 0;
+ HAL_TIM_OC_Init(&TimMasterHandle);
+
+ NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
+ NVIC_EnableIRQ(TIM_MST_IRQ);
+
+ // Channel 1 for mbed timeout
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
+
+ // Channel 2 for HAL tick
+ HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
+ PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
+ __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
+ __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
+
+#if 0 // For DEBUG only
+ __GPIOB_CLK_ENABLE();
+ GPIO_InitTypeDef GPIO_InitStruct;
+ GPIO_InitStruct.Pin = GPIO_PIN_6;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+#endif
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/hal_tick.h Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,60 @@
+/**
+ ******************************************************************************
+ * @file hal_tick.h
+ * @author MCD Application Team
+ * @brief Initialization of HAL tick
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "stm32f0xx.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST TIM2
+#define TIM_MST_IRQ TIM2_IRQn
+#define TIM_MST_RCC __TIM2_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON __TIM2_FORCE_RESET()
+#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET()
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/stm32f031x6.h Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,3248 @@
+/**
+ ******************************************************************************
+ * @file stm32f031x6.h
+ * @author MCD Application Team
+ * @version V2.2.2
+ * @date 26-June-2015
+ * @brief CMSIS STM32F031x4/STM32F031x6 devices Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripherals registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f031x6
+ * @{
+ */
+
+#ifndef __STM32F031x6_H
+#define __STM32F031x6_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
+ */
+#define __CM0_REV 0 /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
+#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F031x4/STM32F031x6 device Interrupt Number Definition
+ */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** STM32F031x4/STM32F031x6 specific Interrupt Numbers **************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD Interrupts through EXTI Lines 16 */
+ RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
+ FLASH_IRQn = 3, /*!< FLASH global Interrupt */
+ RCC_IRQn = 4, /*!< RCC global Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
+ ADC1_IRQn = 12, /*!< ADC1 global Interrupt */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
+ TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 27 /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#include "system_stm32f0xx.h" /* STM32F0xx System Header */
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+}ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+}ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+}CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+}DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+}DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
+ __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
+ __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
+ __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
+}FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
+ __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
+ __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
+ __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
+}OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED; /*!< Reserved, 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+}SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+}IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+}PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
+ __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
+}RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */
+ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+}RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+}SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED1; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED2; /*!< Reserved, 0x2A */
+}USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+}WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
+#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
+#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
+#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
+
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
+#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
+#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
+#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
+#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
+#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
+#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
+#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
+#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
+#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+
+/* Old bit definition, maintained for legacy purpose */
+#define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
+#define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
+#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
+#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
+
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/****************** FLASH Keys **********************************************/
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
+ to unlock the write access to the FPEC. */
+
+#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
+#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
+ unlock the write access to the option byte block */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
+#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
+
+#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
+#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
+#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
+
+/* Old OBR_VDDA bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OB_RDP register **********************/
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OB_USER register *********************/
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for OB_WRP0 register *********************/
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register ****************/
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register ****************/
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register ********************/
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register ********************/
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *******************/
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *******************/
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+/*****************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register *******************/
+#define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register ******************/
+#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register *******************/
+#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register *******************/
+#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
+
+/*****************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for PWR_CR register *******************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+/******************* Bit definition for PWR_CSR register *******************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
+
+/*****************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/*****************************************************************************/
+
+/******************** Bit definition for RCC_CR register *******************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+/******************** Bit definition for RCC_CFGR register *****************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE configuration */
+#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
+#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
+#define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
+#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
+#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
+
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
+
+/*!<****************** Bit definition for RCC_CIR register *****************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2RSTR register ****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
+#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
+
+/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
+
+/***************** Bit definition for RCC_APB1RSTR register ****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
+
+/****************** Bit definition for RCC_AHBENR register *****************/
+#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
+#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
+#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register *****************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
+
+/******************* Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/* Old Bit definition maintained for legacy purpose */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ***************/
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
+
+/******************* Bit definition for RCC_CFGR2 register *****************/
+/*!< PREDIV configuration */
+#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
+#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
+#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
+#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
+#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
+#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
+#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
+#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
+#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
+#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
+#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
+#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
+#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
+#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
+#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
+#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
+#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
+
+/******************* Bit definition for RCC_CFGR3 register *****************/
+/*!< USART1 Clock source selection */
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
+#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
+
+#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
+#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
+
+/******************* Bit definition for RCC_CR2 register *******************/
+#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
+#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
+#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
+#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
+#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
+
+/*****************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/*****************************************************************************/
+/******************** Bits definition for RTC_TR register ******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register ******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register ******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ISR register *****************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register ****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMAR register **************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register *****************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register *****************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register **************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register ****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register ****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ***************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALR register ****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ***************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register ************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ***************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ***************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ***************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ***************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ***************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER ((uint32_t)0x00000005)
+
+/*****************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for SPI_CR1 register *******************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register *******************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register *******************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+
+/******************** Bit definition for SPI_DR register *******************/
+#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register *****************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register *****************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register *****************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register ****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register ******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/*****************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/*****************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+
+
+#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
+#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+
+#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
+#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 */
+#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10 */
+
+
+/***************** Bit definition for SYSCFG_EXTICR1 register **************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register **************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register **************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register **************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM14_OR register ********************/
+#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
+#define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
+#define USART_CR1_M ((uint32_t)0x00001000) /*!< SmartCard Length */
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances ******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5))
+
+/****************************** GPIO Instances ********************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB))
+
+/****************************** I2C Instances *********************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************************** I2S Instances *********************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/****************************** SMBUS Instances *********************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************************** SPI Instances *********************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM2)
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM14)
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
+
+/******************** USART Instances : auto Baud rate detection **************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
+
+/****************** UART Instances : LIN mode ********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/****************** UART Instances : wakeup from stop mode ********************/
+#define IS_UART_WAKEUP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+
+/****************** UART Instances : Auto Baud Rate detection ********************/
+#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
+
+/****************** UART Instances : Driver enable detection ********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define PVD_VDDIO2_IRQn PVD_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
+#define ADC1_COMP_IRQn ADC1_IRQn
+
+/* Aliases for __IRQHandler */
+#define PVD_VDDIO2_IRQHandler PVD_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
+#define ADC1_COMP_IRQHandler ADC1_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F031x6_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/stm32f0xx.h Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,244 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.2.2
+ * @date 26-June-2015
+ * @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F0xx device used in the target application
+ * - To use or not the peripherals drivers in application code(i.e.
+ * code will be based on direct access to peripherals registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx
+ * @{
+ */
+
+#ifndef __STM32F0xx_H
+#define __STM32F0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F0)
+#define STM32F0
+#endif /* STM32F0 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
+ !defined (STM32F031x6) && !defined (STM32F038xx) && \
+ !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
+ !defined (STM32F051x8) && !defined (STM32F058xx) && \
+ !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
+ !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
+ /* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
+ #define STM32F031x6 /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
+ /* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
+ /* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
+ /* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
+ /* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
+ /* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
+ /* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
+ /* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
+ /* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number V2.2.2
+ */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F030x6)
+ #include "stm32f030x6.h"
+#elif defined(STM32F030x8)
+ #include "stm32f030x8.h"
+#elif defined(STM32F031x6)
+ #include "stm32f031x6.h"
+#elif defined(STM32F038xx)
+ #include "stm32f038xx.h"
+#elif defined(STM32F042x6)
+ #include "stm32f042x6.h"
+#elif defined(STM32F048xx)
+ #include "stm32f048xx.h"
+#elif defined(STM32F051x8)
+ #include "stm32f051x8.h"
+#elif defined(STM32F058xx)
+ #include "stm32f058xx.h"
+#elif defined(STM32F070x6)
+ #include "stm32f070x6.h"
+#elif defined(STM32F070xB)
+ #include "stm32f070xb.h"
+#elif defined(STM32F071xB)
+ #include "stm32f071xb.h"
+#elif defined(STM32F072xB)
+ #include "stm32f072xb.h"
+#elif defined(STM32F078xx)
+ #include "stm32f078xx.h"
+#elif defined(STM32F091xC)
+ #include "stm32f091xc.h"
+#elif defined(STM32F098xx)
+ #include "stm32f098xx.h"
+#elif defined(STM32F030xC)
+ #include "stm32f030xc.h"
+#else
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f0xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F0xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.c Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,454 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.c
+ * @author MCD Application Team
+ * @version V2.2.2
+ * @date 26-June-2015
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f0xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. This file configures the system clock as follows:
+ *=============================================================================
+ * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * | (external 8 MHz clock) | (internal 48 MHz)
+ * | 2- PLL_HSE_XTAL |
+ * | (external 8 MHz xtal) |
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * AHBCLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * APB1CLK (MHz) | 48 | 48
+ *-----------------------------------------------------------------------------
+ * USB capable (48 MHz precise clock) | YES | YES
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f0xx.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Defines
+ * @{
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Macros
+ * @{
+ */
+
+/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
+#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock there is no need to
+ call the 2 first functions listed above, since SystemCoreClock variable is
+ updated automatically.
+ */
+uint32_t SystemCoreClock = 48000000;
+
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+ RCC->CFGR &= (uint32_t)0xF8FFB80C;
+#else
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+ RCC->CFGR &= (uint32_t)0x08FFB80C;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+ RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+
+ /* Reset PREDIV[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+#if defined (STM32F072xB) || defined (STM32F078xx)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
+#elif defined (STM32F071xB)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+ /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+ /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+ /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
+ /* Set default USB clock to PLLCLK, since there is no HSI48 */
+ RCC->CFGR3 |= (uint32_t)0x00000080;
+#else
+ #warning "No target selected"
+#endif
+
+ /* Reset HSI14 bit */
+ RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
+ SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
+ }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+ else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
+ {
+ /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
+ }
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
+ else
+ {
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
+ || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
+ || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
+#else
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
+ STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
+ STM32F091xC || STM32F098xx || STM32F030xC */
+ }
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ /* 1- Try to start with HSE and external clock */
+#if USE_PLL_HSE_EXTC != 0
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+ /* 2- If fail try to start with HSE and external xtal */
+ #if USE_PLL_HSE_XTAL != 0
+ if (SetSysClock_PLL_HSE(0) == 0)
+ #endif
+ {
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+ {
+ while(1)
+ {
+ // [TODO] Put something here to tell the user that a problem occured...
+ }
+ }
+ }
+ }
+
+ // Output clock on MCO pin(PA8) for debugging purpose
+ // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
+}
+
+#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ //Select HSI as system clock source to allow modification of the PLL configuration
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
+
+ // Select HSE oscillator as PLL source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
+ }
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
+
+ return 1; // OK
+}
+#endif
+
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
+
+ return 1; // OK
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.h Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,123 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f0xx.h
+ * @author MCD Application Team
+ * @version V2.2.2
+ * @date 26-June-2015
+ * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f0xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F0XX_H
+#define __SYSTEM_STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F0xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F0xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 3) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) by calling HAL API function HAL_RCC_ClockConfig()
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F0xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F0XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/stm32f070xb.icf Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/TOOLCHAIN_IAR/stm32f070xb.icf Mon Sep 28 10:45:10 2015 +0100
@@ -1,31 +1,33 @@
-/* [ROM = 128kb = 0x20000] */
-define symbol __intvec_start__ = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__ = 0x0801FFFF;
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x200000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
-/* [RAM = 16kb = 0x4000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
-define symbol __NVIC_start__ = 0x20000000;
-define symbol __NVIC_end__ = 0x200000BF; /* Aligned on 8 bytes */
-define symbol __region_RAM_start__ = 0x200000C0;
-define symbol __region_RAM_end__ = 0x20003FFF;
-
-/* Memory regions */
define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-/* Stack and Heap */
-/*Heap 1/4 of ram and stack 1/8*/
-define symbol __size_cstack__ = 0x800;
-define symbol __size_heap__ = 0x1000;
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-initialize by copy with packing = zeros { readwrite };
+initialize by copy { readwrite };
do not initialize { section .noinit };
-place at address mem:__intvec_start__ { readonly section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, block STACKHEAP };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis.h Mon Sep 28 10:45:10 2015 +0100 @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * A generic CMSIS include header ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.c Mon Sep 28 10:45:10 2015 +0100
@@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -33,21 +33,21 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
-int NVIC_vtor_remap = 0; // To keep track that the vectors remap is done
-
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
int i;
+ // To keep track that the vectors remap is done
+ static volatile uint32_t vtor_remap = 0;
// Space for dynamic vectors, initialised to allocate in R/W
- uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
+ static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
// Copy and switch to dynamic vectors if first time called
- if (NVIC_vtor_remap == 0) {
+ if (vtor_remap == 0) {
uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
- NVIC_vtor_remap = 1; // The vectors remap is done
+ vtor_remap = 1; // The vectors remap is done
}
// Set the vector
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.h Mon Sep 28 10:45:10 2015 +0100 @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f070xb.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 05-December-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS STM32F070xB devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -59,7 +59,6 @@
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
-
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
@@ -324,6 +323,7 @@
/**
* @brief Reset and Clock Control
*/
+
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
@@ -345,7 +345,6 @@
/**
* @brief Real-Time Clock
*/
-
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
@@ -353,10 +352,10 @@
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
__IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
- uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
@@ -492,6 +491,7 @@
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
@@ -730,7 +730,6 @@
#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
/******************* Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
@@ -1050,8 +1049,8 @@
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
/****************** FLASH Keys **********************************************/
-#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
-#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
to unlock the write access to the FPEC. */
#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
@@ -1086,12 +1085,13 @@
#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
-#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
+#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
+#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
/* Old BOOT1 bit definition, maintained for legacy purpose */
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
@@ -2053,11 +2053,16 @@
#define RTC_CR_TSIE ((uint32_t)0x00008000)
#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
#define RTC_CR_ALRAE ((uint32_t)0x00000100)
#define RTC_CR_FMT ((uint32_t)0x00000040)
#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
#define RTC_CR_REFCKON ((uint32_t)0x00000010)
#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
/******************** Bits definition for RTC_ISR register *****************/
#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
@@ -2065,18 +2070,23 @@
#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
#define RTC_ISR_INIT ((uint32_t)0x00000080)
#define RTC_ISR_INITF ((uint32_t)0x00000040)
#define RTC_ISR_RSF ((uint32_t)0x00000020)
#define RTC_ISR_INITS ((uint32_t)0x00000010)
#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
/******************** Bits definition for RTC_PRER register ****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+/******************** Bits definition for RTC_WUTR register ****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
/******************** Bits definition for RTC_ALRMAR register **************/
#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
@@ -2306,187 +2316,189 @@
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
-#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
+
+#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x04001F00) /*!< DMA remap mask */
#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */
#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
-#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */
+
/***************** Bit definition for SYSCFG_EXTICR1 register **************/
-#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
/**
* @brief EXTI1 configuration
*/
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
/**
* @brief EXTI2 configuration
*/
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
/**
* @brief EXTI3 configuration
*/
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register **************/
-#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
/**
* @brief EXTI5 configuration
*/
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
/**
* @brief EXTI6 configuration
*/
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
/**
* @brief EXTI7 configuration
*/
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register **************/
-#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
/**
* @brief EXTI9 configuration
*/
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
/**
* @brief EXTI10 configuration
*/
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
/**
* @brief EXTI11 configuration
*/
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register **************/
-#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
/**
* @brief EXTI13 configuration
*/
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
/**
* @brief EXTI14 configuration
*/
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
/**
* @brief EXTI15 configuration
*/
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
@@ -3140,6 +3152,7 @@
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -3361,6 +3374,11 @@
#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
+/****************** UART Instances : Driver enable detection ********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART4))
/****************************** USB Instances ********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f0xx.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f0xx.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 05-December-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,6 +63,13 @@
/** @addtogroup Library_configuration_section
* @{
*/
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F0)
+#define STM32F0
+#endif /* STM32F0 */
/* Uncomment the line below according to the target STM32 device used in your
application
@@ -105,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.2.0
+ * @brief CMSIS Device version number V2.2.2
*/
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
- * @version V2.2.0
- * @date 05-December-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@@ -42,7 +42,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -82,7 +82,6 @@
*/
#include "stm32f0xx.h"
-#include "hal_tick.h"
/**
* @}
@@ -108,6 +107,7 @@
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
+
/**
* @}
*/
@@ -161,8 +161,6 @@
* @{
*/
-extern int NVIC_vtor_remap;
-
/**
* @brief Setup the microcontroller system.
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
@@ -195,7 +193,7 @@
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-#if defined (STM32F072xB) || defined (STM32F078xB)
+#if defined (STM32F072xB) || defined (STM32F078xx)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
#elif defined (STM32F071xB)
@@ -227,19 +225,6 @@
/* Disable all interrupts */
RCC->CIR = 0x00000000;
-
- /* Configure the Cube driver */
- SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
- NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector()
- HAL_Init();
-
- /* Configure the System clock source, PLL Multiplier and Divider factors,
- AHB/APBx prescalers and Flash settings */
- SetSysClock();
-
- /* Reset the timer to avoid issues after the RAM initialization */
- TIM_MST_RESET_ON;
- TIM_MST_RESET_OFF;
}
/**
@@ -314,9 +299,9 @@
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
else
{
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
+ || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
+ || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
#else
@@ -379,17 +364,24 @@
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ //Select HSI as system clock source to allow modification of the PLL configuration
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
// Select HSE oscillator as PLL source
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
}
- RCC_OscInitStruct.HSI48State = 0; // not used
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.h Mon Sep 28 10:45:10 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/stm32f072xb.icf Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/stm32f072xb.icf Mon Sep 28 10:45:10 2015 +0100
@@ -1,30 +1,34 @@
-/* [ROM = 128kb = 0x20000] */
-define symbol __intvec_start__ = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__ = 0x0801FFFF;
-
-/* [RAM = 16kb = 0x4000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
-define symbol __NVIC_start__ = 0x20000000;
-define symbol __NVIC_end__ = 0x200000BF; /* Aligned on 8 bytes */
-define symbol __region_RAM_start__ = 0x200000C0;
-define symbol __region_RAM_end__ = 0x20003FFF;
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x200000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
-/* Memory regions */
define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-/* Stack and Heap */
-define symbol __size_cstack__ = 0x800;
-define symbol __size_heap__ = 0x1000;
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-initialize by copy with packing = zeros { readwrite };
+initialize by copy { readwrite };
do not initialize { section .noinit };
-place at address mem:__intvec_start__ { readonly section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, block STACKHEAP };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis.h Mon Sep 28 10:45:10 2015 +0100 @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * A generic CMSIS include header ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.c Mon Sep 28 10:45:10 2015 +0100
@@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -33,21 +33,21 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
-int NVIC_vtor_remap = 0; // To keep track that the vectors remap is done
-
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
int i;
+ // To keep track that the vectors remap is done
+ static volatile uint32_t vtor_remap = 0;
// Space for dynamic vectors, initialised to allocate in R/W
- uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
+ static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
// Copy and switch to dynamic vectors if first time called
- if (NVIC_vtor_remap == 0) {
+ if (vtor_remap == 0) {
uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
- NVIC_vtor_remap = 1; // The vectors remap is done
+ vtor_remap = 1; // The vectors remap is done
}
// Set the vector
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.h Mon Sep 28 10:45:10 2015 +0100 @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f072xb.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 05-December-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS STM32F072x8/STM32F072xB devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -59,7 +59,6 @@
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
-
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
@@ -449,6 +448,7 @@
/**
* @brief Reset and Clock Control
*/
+
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
@@ -470,7 +470,6 @@
/**
* @brief Real-Time Clock
*/
-
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
@@ -644,6 +643,7 @@
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
@@ -672,6 +672,7 @@
#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
+
#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
@@ -1145,9 +1146,10 @@
/*!<CAN filter registers */
/******************* Bit definition for CAN_FMR register ********************/
#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
@@ -1162,9 +1164,23 @@
#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
@@ -1179,40 +1195,82 @@
#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
+#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
+#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@@ -2224,7 +2282,6 @@
#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
-
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
@@ -2272,24 +2329,24 @@
#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
/* COMPx bits definition */
-#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
-#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
-#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
-#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
-#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
-#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
-#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
-#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
-#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
-#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
-#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
-#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
-#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
-#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
-#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
-#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
-#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
+#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
+#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
+#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
+#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
+#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
+#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
+#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
+#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
/******************************************************************************/
/* */
@@ -2630,12 +2687,20 @@
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 - reserved */
#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 - reserved */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 - reserved */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 - reserved */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
/****************** Bit definition for EXTI_EMR register ********************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@@ -2656,12 +2721,20 @@
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 - reserved */
#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 - reserved */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 - reserved */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 - reserved */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
/******************* Bit definition for EXTI_RTSR register ******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@@ -2683,6 +2756,9 @@
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/******************* Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -2704,6 +2780,9 @@
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/******************* Bit definition for EXTI_SWIER register *******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -2725,6 +2804,9 @@
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/****************** Bit definition for EXTI_PR register *********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
@@ -2746,6 +2828,9 @@
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
/******************************************************************************/
/* */
@@ -2766,8 +2851,8 @@
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
/****************** FLASH Keys **********************************************/
-#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
-#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
to unlock the write access to the FPEC. */
#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
@@ -2802,12 +2887,13 @@
#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
-#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
+#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
+#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
/* Old BOOT1 bit definition, maintained for legacy purpose */
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
@@ -3834,6 +3920,7 @@
#define RTC_CR_SUB1H ((uint32_t)0x00020000)
#define RTC_CR_ADD1H ((uint32_t)0x00010000)
#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
#define RTC_CR_TSE ((uint32_t)0x00000800)
#define RTC_CR_WUTE ((uint32_t)0x00000400)
@@ -4140,6 +4227,7 @@
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x7F007F00) /*!< DMA remap mask */
#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
@@ -4161,185 +4249,186 @@
#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
+
#define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus */
/***************** Bit definition for SYSCFG_EXTICR1 register **************/
-#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
/**
* @brief EXTI1 configuration
*/
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
/**
* @brief EXTI2 configuration
*/
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
/**
* @brief EXTI3 configuration
*/
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register **************/
-#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
/**
* @brief EXTI5 configuration
*/
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
/**
* @brief EXTI6 configuration
*/
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
/**
* @brief EXTI7 configuration
*/
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register **************/
-#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
/**
* @brief EXTI9 configuration
*/
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
/**
* @brief EXTI10 configuration
*/
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
/**
* @brief EXTI11 configuration
*/
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register **************/
-#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
/**
* @brief EXTI13 configuration
*/
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
/**
* @brief EXTI14 configuration
*/
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
/**
* @brief EXTI15 configuration
*/
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f0xx.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f0xx.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 05-December-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,6 +63,13 @@
/** @addtogroup Library_configuration_section
* @{
*/
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F0)
+#define STM32F0
+#endif /* STM32F0 */
/* Uncomment the line below according to the target STM32 device used in your
application
@@ -105,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.2.0
+ * @brief CMSIS Device version number V2.2.2
*/
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
- * @version V2.2.0
- * @date 05-December-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@@ -42,7 +42,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -82,7 +82,6 @@
*/
#include "stm32f0xx.h"
-#include "hal_tick.h"
/**
* @}
@@ -108,6 +107,7 @@
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
+
/**
* @}
*/
@@ -161,8 +161,6 @@
* @{
*/
-extern int NVIC_vtor_remap;
-
/**
* @brief Setup the microcontroller system.
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
@@ -195,7 +193,7 @@
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-#if defined (STM32F072xB) || defined (STM32F078xB)
+#if defined (STM32F072xB) || defined (STM32F078xx)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
#elif defined (STM32F071xB)
@@ -227,19 +225,6 @@
/* Disable all interrupts */
RCC->CIR = 0x00000000;
-
- /* Configure the Cube driver */
- SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
- NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector()
- HAL_Init();
-
- /* Configure the System clock source, PLL Multiplier and Divider factors,
- AHB/APBx prescalers and Flash settings */
- SetSysClock();
-
- /* Reset the timer to avoid issues after the RAM initialization */
- TIM_MST_RESET_ON;
- TIM_MST_RESET_OFF;
}
/**
@@ -314,9 +299,9 @@
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
else
{
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
+ || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
+ || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
#else
@@ -370,7 +355,7 @@
}
// Output clock on MCO pin(PA8) for debugging purpose
- //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
+ // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
}
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
@@ -379,17 +364,24 @@
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ //Select HSI as system clock source to allow modification of the PLL configuration
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
// Select HSE oscillator as PLL source
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
}
- RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
@@ -425,13 +417,13 @@
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
- // Select HSI48 oscillator as PLL source
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
- RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI48;
- RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
- RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
@@ -446,7 +438,7 @@
}
// Output clock on MCO1 pin(PA8) for debugging purpose
- //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 48 MHz
return 1; // OK
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.h Mon Sep 28 10:45:10 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/stm32f091xc.icf Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/stm32f091xc.icf Mon Sep 28 10:45:10 2015 +0100
@@ -1,31 +1,33 @@
-/* [ROM = 256kb = 0x40000] */
-define symbol __intvec_start__ = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__ = 0x0803FFFF;
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x200000C0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
-/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
-define symbol __NVIC_start__ = 0x20000000;
-define symbol __NVIC_end__ = 0x200000BF; /* Aligned on 8 bytes */
-define symbol __region_RAM_start__ = 0x200000C0;
-define symbol __region_RAM_end__ = 0x20007FFF;
-
-/* Memory regions */
define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-/* Stack and Heap */
-/*Heap 1/4 of ram and stack 1/8*/
-define symbol __size_cstack__ = 0x1000;
-define symbol __size_heap__ = 0x2000;
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-initialize by copy with packing = zeros { readwrite };
+initialize by copy { readwrite };
do not initialize { section .noinit };
-place at address mem:__intvec_start__ { readonly section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
-place in RAM_region { readwrite, block STACKHEAP };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis.h Mon Sep 28 10:45:10 2015 +0100 @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * A generic CMSIS include header ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.c Mon Sep 28 10:45:10 2015 +0100
@@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -33,21 +33,21 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
-int NVIC_vtor_remap = 0; // To keep track that the vectors remap is done
-
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
int i;
+ // To keep track that the vectors remap is done
+ static volatile uint32_t vtor_remap = 0;
// Space for dynamic vectors, initialised to allocate in R/W
- uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
+ static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
// Copy and switch to dynamic vectors if first time called
- if (NVIC_vtor_remap == 0) {
+ if (vtor_remap == 0) {
uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
- NVIC_vtor_remap = 1; // The vectors remap is done
+ vtor_remap = 1; // The vectors remap is done
}
// Set the vector
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.h Mon Sep 28 10:45:10 2015 +0100 @@ -1,7 +1,7 @@ /* mbed Microcontroller Library * CMSIS-style functionality to support dynamic vectors ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics + * Copyright (c) 2015, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.h Mon Sep 28 10:45:10 2015 +0100 @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f091xc.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 05-December-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS STM32F091xC devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -59,7 +59,6 @@
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
-
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
@@ -453,6 +452,7 @@
/**
* @brief Reset and Clock Control
*/
+
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
@@ -474,7 +474,6 @@
/**
* @brief Real-Time Clock
*/
-
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
@@ -610,6 +609,7 @@
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /*!< FLASH END address of bank1 */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
@@ -637,6 +637,7 @@
#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
+
#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
@@ -754,7 +755,6 @@
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-
/**
* @}
*/
@@ -1130,9 +1130,10 @@
/*!<CAN filter registers */
/******************* Bit definition for CAN_FMR register ********************/
#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
@@ -1147,9 +1148,23 @@
#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
@@ -1164,40 +1179,82 @@
#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
+#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
+#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@@ -2209,7 +2266,6 @@
#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
-
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
@@ -2257,24 +2313,24 @@
#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
/* COMPx bits definition */
-#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
-#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
-#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
-#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
-#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
-#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
-#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
-#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
-#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
-#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
-#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
-#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
-#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
-#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
-#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
-#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
-#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
+#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
+#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
+#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
+#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
+#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
+#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
+#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
+#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
/******************************************************************************/
/* */
@@ -2770,15 +2826,19 @@
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 - reserved */
#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
-#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 - reserved */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 - reserved */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 - reserved */
#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
/****************** Bit definition for EXTI_EMR register ********************/
@@ -2800,15 +2860,19 @@
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 - reserved */
#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
-#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 - reserved */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 - reserved */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 - reserved */
#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
/******************* Bit definition for EXTI_RTSR register ******************/
@@ -2926,8 +2990,8 @@
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
/****************** FLASH Keys **********************************************/
-#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
-#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
to unlock the write access to the FPEC. */
#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
@@ -2962,12 +3026,15 @@
#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
-#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
+#define FLASH_OBR_USER ((uint32_t)0x0000FF00) /*!< User Option Bytes */
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT0 ((uint32_t)0x00001000) /*!< nBOOT0 */
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
+#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
+#define FLASH_OBR_BOOT_SEL ((uint32_t)0x00008000) /*!< BOOT selection */
/* Old BOOT1 bit definition, maintained for legacy purpose */
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
@@ -4002,6 +4069,7 @@
#define RTC_CR_SUB1H ((uint32_t)0x00020000)
#define RTC_CR_ADD1H ((uint32_t)0x00010000)
#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
#define RTC_CR_TSE ((uint32_t)0x00000800)
#define RTC_CR_WUTE ((uint32_t)0x00000400)
@@ -4320,182 +4388,182 @@
#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10 */
/***************** Bit definition for SYSCFG_EXTICR1 register **************/
-#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
/**
* @brief EXTI1 configuration
*/
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
/**
* @brief EXTI2 configuration
*/
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
/**
* @brief EXTI3 configuration
*/
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register **************/
-#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
/**
* @brief EXTI5 configuration
*/
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
/**
* @brief EXTI6 configuration
*/
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
/**
* @brief EXTI7 configuration
*/
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register **************/
-#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
/**
* @brief EXTI9 configuration
*/
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
/**
* @brief EXTI10 configuration
*/
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
/**
* @brief EXTI11 configuration
*/
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register **************/
-#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
/**
* @brief EXTI13 configuration
*/
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
/**
* @brief EXTI14 configuration
*/
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
/**
* @brief EXTI15 configuration
*/
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
@@ -5661,6 +5729,7 @@
* @}
*/
+
/******************************************************************************/
/* For a painless codes migration between the STM32F3xx device product */
/* lines, the aliases defined below are put in place to overcome the */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f0xx.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f0xx.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
- * @version V2.2.0
- * @date 05-December-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,6 +63,13 @@
/** @addtogroup Library_configuration_section
* @{
*/
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F0)
+#define STM32F0
+#endif /* STM32F0 */
/* Uncomment the line below according to the target STM32 device used in your
application
@@ -105,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.2.0
+ * @brief CMSIS Device version number V2.2.2
*/
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
- * @version V2.2.0
- * @date 05-December-2014
+ * @version V2.2.2
+ * @date 26-June-2015
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@@ -42,7 +42,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -82,7 +82,6 @@
*/
#include "stm32f0xx.h"
-#include "hal_tick.h"
/**
* @}
@@ -108,6 +107,7 @@
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
+
/**
* @}
*/
@@ -161,8 +161,6 @@
* @{
*/
-extern int NVIC_vtor_remap;
-
/**
* @brief Setup the microcontroller system.
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
@@ -195,7 +193,7 @@
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-#if defined (STM32F072xB) || defined (STM32F078xB)
+#if defined (STM32F072xB) || defined (STM32F078xx)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
#elif defined (STM32F071xB)
@@ -227,19 +225,6 @@
/* Disable all interrupts */
RCC->CIR = 0x00000000;
-
- /* Configure the Cube driver */
- SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
- NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector()
- HAL_Init();
-
- /* Configure the System clock source, PLL Multiplier and Divider factors,
- AHB/APBx prescalers and Flash settings */
- SetSysClock();
-
- /* Reset the timer to avoid issues after the RAM initialization */
- TIM_MST_RESET_ON;
- TIM_MST_RESET_OFF;
}
/**
@@ -314,9 +299,9 @@
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
else
{
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
+ || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
+ || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
#else
@@ -370,7 +355,7 @@
}
// Output clock on MCO pin(PA8) for debugging purpose
- //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
}
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
@@ -379,17 +364,24 @@
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ //Select HSI as system clock source to allow modification of the PLL configuration
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
// Select HSE oscillator as PLL source
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
}
- RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
@@ -425,13 +417,13 @@
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
- // Select HSI48 oscillator as PLL source
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
- RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI48;
- RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
- RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
+ RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
@@ -446,7 +438,7 @@
}
// Output clock on MCO1 pin(PA8) for debugging purpose
- //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz
+ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 48 MHz
return 1; // OK
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.h Mon Sep 28 10:45:10 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f0xx.h * @author MCD Application Team - * @version V2.2.0 - * @date 05-December-2014 + * @version V2.2.2 + * @date 26-June-2015 * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32_hal_legacy.h Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,2500 @@
+/**
+ ******************************************************************************
+ * @file stm32_hal_legacy.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 26-June-2015
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * macros and functions maintained for legacy purpose.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_HAL_LEGACY
+#define __STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP ADC_REGULAR_GROUP
+#define INJECTED_GROUP ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT ADC_AWD_EVENT
+#define AWD1_EVENT ADC_AWD1_EVENT
+#define AWD2_EVENT ADC_AWD2_EVENT
+#define AWD3_EVENT ADC_AWD3_EVENT
+#define OVR_EVENT ADC_OVR_EVENT
+#define JQOVF_EVENT ADC_JQOVF_EVENT
+#define ALL_CHANNELS ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+#define DAC_WAVE_NONE ((uint32_t)0x00000000)
+#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
+#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW OB_IWDG_SW
+#define OB_WDG_HW OB_IWDG_HW
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+
+/**
+ * @}
+ */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F7)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
+#else
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define GET_GPIO_SOURCE GPIO_GET_INDEX
+#define GET_GPIO_INDEX GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSISTIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSISTIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSISTIONS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NAND_AddressTypedef NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE NOR_WRITE
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FORMAT_BIN RTC_FORMAT_BIN
+#define FORMAT_BCD RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
+/**
+ * @}
+ */
+
+
+ /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
+/**
+ * @}
+ */
+
+ /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER TIM_DMABASE_DIER
+#define TIM_DMABase_SR TIM_DMABASE_SR
+#define TIM_DMABase_EGR TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER TIM_DMABASE_CCER
+#define TIM_DMABase_CNT TIM_DMABASE_CNT
+#define TIM_DMABase_PSC TIM_DMABASE_PSC
+#define TIM_DMABase_ARR TIM_DMABASE_ARR
+#define TIM_DMABase_RCR TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
+
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED USART_NACK_ENABLE
+#define USARTNACK_DISABLED USART_NACK_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CFR_BASE WWDG_CFR_BASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define VLAN_TAG ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR ((uint32_t)0x00000100)
+#define ETH_MMCRIR ((uint32_t)0x00000104)
+#define ETH_MMCTIR ((uint32_t)0x00000108)
+#define ETH_MMCRIMR ((uint32_t)0x0000010C)
+#define ETH_MMCTIMR ((uint32_t)0x00000110)
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
+#define ETH_MMCTGFCR ((uint32_t)0x00000168)
+#define ETH_MMCRFCECR ((uint32_t)0x00000194)
+#define ETH_MMCRFAECR ((uint32_t)0x00000198)
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+ * @{
+ */
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+
+#define DBP_BitNumber DBP_BIT_NUMBER
+#define PVDE_BitNumber PVDE_BIT_NUMBER
+#define PMODE_BitNumber PMODE_BIT_NUMBER
+#define EWUP_BitNumber EWUP_BIT_NUMBER
+#define FPDS_BitNumber FPDS_BIT_NUMBER
+#define ODEN_BitNumber ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
+#define BRE_BitNumber BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError TIM_DMAError
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+/**
+ * @}
+ */
+
+
+ /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define AES_IT_CC CRYP_IT_CC
+#define AES_IT_ERR CRYP_IT_ERR
+#define AES_FLAG_CCF CRYP_FLAG_CCF
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __ADC_ENABLE __HAL_ADC_ENABLE
+#define __ADC_DISABLE __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
+#define __ADC_IS_ENABLED ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1 ADC_SQR1
+#define __HAL_ADC_SMPR1 ADC_SMPR1
+#define __HAL_ADC_SMPR2 ADC_SMPR2
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_WRPAREA IS_OB_WRPAREA
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE IS_FLASH_TYPEERASE
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
+#define __HAL_I2C_SPEED I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
+#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+ * @{
+ */
+
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define Sdmmc1ClockSelection SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
+#define SdioClockSelection Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
+
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB RCC_CR_HSION_BB
+#define CR_CSSON_BB RCC_CR_CSSON_BB
+#define CR_PLLON_BB RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB RCC_CR_MSION_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
+
+#define IS_ALARM IS_RTC_ALARM
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK
+#define IS_TAMPER IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+
+#if defined(STM32F4)
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define SDMMC1_IRQn SDIO_IRQn
+#define SDMMC1_IRQHandler SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define SDIO_IRQn SDMMC1_IRQn
+#define SDIO_IRQHandler SDMMC1_IRQHandler
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
+#define __USART_ENABLE __HAL_USART_ENABLE
+#define __USART_DISABLE __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
+
+#define TIM_TS_ITR0 ((uint32_t)0x0000)
+#define TIM_TS_ITR1 ((uint32_t)0x0010)
+#define TIM_TS_ITR2 ((uint32_t)0x0020)
+#define TIM_TS_ITR3 ((uint32_t)0x0030)
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+
+#define TIM_CHANNEL_1 ((uint32_t)0x0000)
+#define TIM_CHANNEL_2 ((uint32_t)0x0004)
+#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
+
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
+
+#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
+
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
+ ((STATE) == TIM_OUTPUTSTATE_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -57,7 +57,7 @@
* @{
*/
-/** @defgroup HAL HAL module driver
+/** @defgroup HAL HAL
* @brief HAL module driver.
* @{
*/
@@ -66,14 +66,14 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup HAL_Private Constants
+/** @defgroup HAL_Private_Constants HAL Private Constants
* @{
*/
/**
- * @brief STM32F0xx HAL Driver version number V1.2.0
+ * @brief STM32F0xx HAL Driver version number V1.3.0
*/
#define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F0xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F0xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24)\
@@ -87,6 +87,13 @@
*/
/* Private macro -------------------------------------------------------------*/
+/** @defgroup HAL_Private_Macros HAL Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
/* Private variables ---------------------------------------------------------*/
/** @defgroup HAL_Private_Variables HAL Private Variables
* @{
@@ -174,14 +181,14 @@
HAL_StatusTypeDef HAL_DeInit(void)
{
/* Reset of all peripherals */
- __APB1_FORCE_RESET();
- __APB1_RELEASE_RESET();
+ __HAL_RCC_APB1_FORCE_RESET();
+ __HAL_RCC_APB1_RELEASE_RESET();
- __APB2_FORCE_RESET();
- __APB2_RELEASE_RESET();
+ __HAL_RCC_APB2_FORCE_RESET();
+ __HAL_RCC_APB2_RELEASE_RESET();
- __AHB_FORCE_RESET();
- __AHB_RELEASE_RESET();
+ __HAL_RCC_AHB_FORCE_RESET();
+ __HAL_RCC_AHB_RELEASE_RESET();
/* De-Init the low level hardware */
HAL_MspDeInit();
@@ -282,8 +289,8 @@
}
/**
- * @brief Povides a tick value in millisecond.
- * @note The function is declared as __Weak to be overwritten in case of other
+ * @brief Provides a tick value in millisecond.
+ * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
@@ -293,41 +300,6 @@
}
/**
- * @brief Suspend Tick increment.
- * @note In the default implementation , SysTick timer is the source of time base. It is
- * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
- * is called, the the SysTick interrupt will be disabled and so Tick increment
- * is suspended.
- * @note This function is declared as __weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_SuspendTick(void)
-
-{
- /* Disable SysTick Interrupt */
- SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
-
-}
-
-/**
- * @brief Resume Tick increment.
- * @note In the default implementation , SysTick timer is the source of time base. It is
- * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
- * is called, the the SysTick interrupt will be enabled and so Tick increment
- * is resumed.
- * The function is declared as __Weak to be overwritten in case of other
- * implementations in user file.
- * @retval None
- */
-__weak void HAL_ResumeTick(void)
-{
- /* Enable SysTick Interrupt */
- SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
-
-}
-
-/**
* @brief This function provides accurate delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
@@ -348,6 +320,39 @@
}
/**
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ * is called, the the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void)
+
+{
+ /* Disable SysTick Interrupt */
+ CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ * is called, the the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void)
+{
+ /* Enable SysTick Interrupt */
+ SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
* @brief This method returns the HAL revision
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
*/
@@ -378,7 +383,7 @@
* @brief Enable the Debug Module during STOP mode
* @retval None
*/
-void HAL_EnableDBGStopMode(void)
+void HAL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
@@ -387,7 +392,7 @@
* @brief Disable the Debug Module during STOP mode
* @retval None
*/
-void HAL_DisableDBGStopMode(void)
+void HAL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
@@ -396,7 +401,7 @@
* @brief Enable the Debug Module during STANDBY mode
* @retval None
*/
-void HAL_EnableDBGStandbyMode(void)
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
@@ -405,7 +410,7 @@
* @brief Disable the Debug Module during STANDBY mode
* @retval None
*/
-void HAL_DisableDBGStandbyMode(void)
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f0xx_hal.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,91 +55,43 @@
* @{
*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup HAL_Private_Macros
+ * @{
+ */
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
+ defined(STM32F070xB) || defined(STM32F030x6)
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+#else
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+#endif
+#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
+#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
+#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
+#if defined(STM32F091xC) || defined(STM32F098xx)
+#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
+ ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
+ ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
+#endif /* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
+
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
- * @{
+ * @{
*/
-#if defined(SYSCFG_CFGR1_DMA_RMP)
-/** @defgroup HAL_DMA_remapping HAL DMA remapping
- * Elements values convention: 0xYYYYYYYY
- * - YYYYYYYY : Position in the SYSCFG register CFGR1
- * @{
- */
-#define HAL_REMAPDMA_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
- 0: No remap (ADC DMA requests mapped on DMA channel 1
- 1: Remap (ADC DMA requests mapped on DMA channel 2 */
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
- 0: No remap (USART1_TX DMA request mapped on DMA channel 2
- 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
- 0: No remap (USART1_RX DMA request mapped on DMA channel 3
- 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
-#define HAL_REMAPDMA_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
- 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
- 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
-#define HAL_REMAPDMA_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
- 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
- 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
-
-#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
-#define HAL_REMAPDMA_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
- 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
- 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
-#define HAL_REMAPDMA_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
- 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
- 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
-#define HAL_REMAPDMA_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
- 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
- 1: 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
-#define HAL_REMAPDMA_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
- 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
- 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
-#define HAL_REMAPDMA_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
- 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
- 1: 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
-#define HAL_REMAPDMA_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
- 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
- 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
-#define HAL_REMAPDMA_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
- 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
- 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
-#define HAL_REMAPDMA_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
- 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
- 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
-#define HAL_REMAPDMA_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
- 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
- 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
-#endif
-
-#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
-#define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \
- ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \
- ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \
- ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \
- ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2) || \
- ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH6) || \
- ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH7) || \
- ((RMP) == HAL_REMAPDMA_SPI2_DMA_CH67) || \
- ((RMP) == HAL_REMAPDMA_USART2_DMA_CH67) || \
- ((RMP) == HAL_REMAPDMA_USART3_DMA_CH32) || \
- ((RMP) == HAL_REMAPDMA_I2C1_DMA_CH76) || \
- ((RMP) == HAL_REMAPDMA_TIM1_DMA_CH6) || \
- ((RMP) == HAL_REMAPDMA_TIM2_DMA_CH7) || \
- ((RMP) == HAL_REMAPDMA_TIM3_DMA_CH6))
-#else
-#define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \
- ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \
- ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \
- ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \
- ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2))
-#endif
-/**
- * @}
- */
-#endif /* SYSCFG_CFGR1_DMA_RMP */
-
#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
/** @defgroup HAL_Pin_remapping HAL Pin remapping
* @{
@@ -148,7 +100,6 @@
0: No remap (pin pair PA9/10 mapped on the pins)
1: Remap (pin pair PA11/12 mapped instead of PA9/10) */
-#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
/**
* @}
*/
@@ -163,100 +114,33 @@
#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */
#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */
-#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
- ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
- ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
/**
* @}
*/
#endif /* STM32F091xC || STM32F098xx */
-/** @defgroup HAL_FastModePlus_I2C HAL FastModePlus I2C
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/
-#if defined(SYSCFG_CFGR1_I2C_FMP_PB6)
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 (SYSCFG_CFGR1_I2C_FMP_PB6) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
- 0: PB6 pin operates in standard mode
- 1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */
-#endif /* SYSCFG_CFGR1_I2C_FMP_PB6 */
-#if defined(SYSCFG_CFGR1_I2C_FMP_PB7)
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 (SYSCFG_CFGR1_I2C_FMP_PB7) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
- 0: PB7 pin operates in standard mode
- 1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */
-#endif /* SYSCFG_CFGR1_I2C_FMP_PB7 */
-
-#if defined(SYSCFG_CFGR1_I2C_FMP_PB8)
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 (SYSCFG_CFGR1_I2C_FMP_PB8) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
- 0: PB8 pin operates in standard mode
- 1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */
-#endif /* SYSCFG_CFGR1_I2C_FMP_PB8 */
-
-#if defined(SYSCFG_CFGR1_I2C_FMP_PB9)
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 (SYSCFG_CFGR1_I2C_FMP_PB9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
- 0: PB9 pin operates in standard mode
- 1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */
-#endif /* SYSCFG_CFGR1_I2C_FMP_PB9 */
-
-#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1)
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1 (SYSCFG_CFGR1_I2C_FMP_I2C1) /*!< I2C1 fast mode Plus driving capability activation
- 0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits
- 1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */
-#endif /* SYSCFG_CFGR1_I2C_FMP_I2C1 */
-
-#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2)
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2 (SYSCFG_CFGR1_I2C_FMP_I2C2) /*!< I2C2 fast mode Plus driving capability activation
- 0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits
- 1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */
-#endif /* SYSCFG_CFGR1_I2C_FMP_I2C2 */
-
-#if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 (SYSCFG_CFGR1_I2C_FMP_PA9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
- 0: PA9 pin operates in standard mode
- 1: FM+ mode is enabled on PA9 pin, and the Speed control is bypassed */
-#endif /* SYSCFG_CFGR1_I2C_FMP_PA9 */
-
-#if defined(SYSCFG_CFGR1_I2C_FMP_PA10)
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 (SYSCFG_CFGR1_I2C_FMP_PA10) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
- 0: PA10 pin operates in standard mode
- 1: FM+ mode is enabled on PA10 pin, and the Speed control is bypassed */
-#endif /* SYSCFG_CFGR1_I2C_FMP_PA10 */
-
-#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx)
-#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA9) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA10) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
-#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
-#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
-#elif defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F030x6)
-#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA9) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA10) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
-#else
-#define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
- ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
+/** @brief Fast-mode Plus driving capability on a specific GPIO
+ */
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
+ defined(STM32F070xB) || defined(STM32F030x6)
+#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */
+#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */
#endif
+#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */
+#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */
+#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */
/**
- * @}
- */
+ * @}
+ */
+
#if defined(STM32F091xC) || defined (STM32F098xx)
/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
@@ -394,68 +278,68 @@
#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
-#define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
-#define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
-#define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
-#define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
-#define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
-#define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
-#define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
-#define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
-#define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
-#define __HAL_FREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
-#define __HAL_UNFREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
-#define __HAL_FREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
-#define __HAL_UNFREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
-#define __HAL_FREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
-#define __HAL_UNFREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
/**
@@ -468,13 +352,13 @@
#if defined(SYSCFG_CFGR1_MEM_MODE)
/** @brief Main Flash memory mapped at 0x00000000
*/
-#define __HAL_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
#endif /* SYSCFG_CFGR1_MEM_MODE */
#if defined(SYSCFG_CFGR1_MEM_MODE_0)
/** @brief System Flash memory mapped at 0x00000000
*/
-#define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
}while(0)
#endif /* SYSCFG_CFGR1_MEM_MODE_0 */
@@ -482,7 +366,7 @@
#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
/** @brief Embedded SRAM mapped at 0x00000000
*/
-#define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
}while(0)
#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
@@ -490,22 +374,6 @@
* @}
*/
-#if defined(SYSCFG_CFGR1_DMA_RMP)
-/** @defgroup HAL_DMA_remap HAL DMA remap
- * @brief DMA remapping enable/disable macros
- * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
- * @{
- */
-#define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
- SYSCFG->CFGR1 |= (__DMA_REMAP__); \
- }while(0)
-#define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
- SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
- }while(0)
-/**
- * @}
- */
-#endif /* SYSCFG_CFGR1_DMA_RMP */
#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
/** @defgroup HAL_Pin_remap HAL Pin remap
@@ -524,22 +392,17 @@
*/
#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
-/** @defgroup HAL_Fast_mode_plus_driving_cap HAL Fast mode plus driving cap
- * @brief Fast mode Plus driving capability enable/disable macros
- * @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C
- * @{
+/** @brief Fast-mode Plus driving capability enable/disable macros
+ * @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
+ * That you can find above these macros.
*/
-#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
- SYSCFG->CFGR1 |= (__FASTMODEPLUS__); \
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+ SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0)
-#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
- SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__); \
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+ CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0)
-/**
- * @}
- */
-
#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
* @{
@@ -635,14 +498,15 @@
/**
* @}
- */
+ */
+
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Functions HAL Exported Functions
+
+/** @addtogroup HAL_Exported_Functions
* @{
*/
-/** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
- * @brief Initialization and de-initialization functions
+/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ******************************/
@@ -655,11 +519,11 @@
* @}
*/
-/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
- * @brief HAL Control functions
+/** @addtogroup HAL_Exported_Functions_Group2
* @{
*/
-/* Peripheral Control functions **********************************************/
+
+/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(__IO uint32_t Delay);
uint32_t HAL_GetTick(void);
@@ -668,26 +532,26 @@
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
-void HAL_EnableDBGStopMode(void);
-void HAL_DisableDBGStopMode(void);
-void HAL_EnableDBGStandbyMode(void);
-void HAL_DisableDBGStandbyMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/
/**
* @}
+ */
+
+/**
+ * @}
*/
/**
* @}
- */
+ */
-/**
- * @}
- */
-
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,53 +2,55 @@
******************************************************************************
* @file stm32f0xx_hal_adc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
* + Initialization and de-initialization functions
* ++ Initialization and Configuration of ADC
* + Operation functions
- * ++ Start, stop, get result of conversions of regular group,
- * using 3 possible modes: polling, interruption or DMA.
+ * ++ Start, stop, get result of conversions of regular
+ * group, using 3 possible modes: polling, interruption or DMA.
* + Control functions
+ * ++ Channels configuration on regular group
* ++ Analog Watchdog configuration
- * ++ Channels configuration on regular group
* + State functions
* ++ ADC state machine management
* ++ Interrupts and flags management
- *
+ * Other functions (extended functions) are available in file
+ * "stm32f0xx_hal_adc_ex.c".
+ *
@verbatim
==============================================================================
- ##### ADC specific features #####
+ ##### ADC peripheral features #####
==============================================================================
- [..]
- (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
+ [..]
+ (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
- (#) Interrupt generation at the end of regular conversion and in case of
+ (+) Interrupt generation at the end of regular conversion and in case of
analog watchdog or overrun events.
- (#) Single and continuous conversion modes.
+ (+) Single and continuous conversion modes.
- (#) Scan mode for automatic conversion of channel 0 to channel 'n'.
+ (+) Scan mode for conversion of several channels sequentially.
- (#) Data alignment with in-built data coherency.
+ (+) Data alignment with in-built data coherency.
- (#) Programmable sampling time.
+ (+) Programmable sampling time (common for all channels)
- (#) ADC conversion group Regular.
+ (+) ADC conversion of regular group.
- (#) External trigger (timer or EXTI) with configurable polarity.
+ (+) External trigger (timer or EXTI) with configurable polarity
- (#) DMA request generation for transfer of conversions data of regular group.
+ (+) DMA request generation for transfer of conversions data of regular group.
- (#) ADC calibration
+ (+) ADC calibration
- (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
+ (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
slower speed.
- (#) ADC input range: from Vref minus (connected to Vssa) to Vref plus (connected to
+ (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
Vdda or to an external voltage reference).
@@ -56,64 +58,176 @@
==============================================================================
[..]
- (#) Enable the ADC interface
- (++) As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured
- at RCC top level: clock source and clock prescaler.
- (++)Two possible clock sources: synchronous clock derived from APB clock
- or asynchronous clock derived from ADC dedicated HSI RC oscillator
- 14MHz.
- (++)Example:
- __ADC1_CLK_ENABLE(); (mandatory)
-
- HI14 enable or let under control of ADC: (optional)
+ *** Configuration of top level parameters related to ADC ***
+ ============================================================
+ [..]
+
+ (#) Enable the ADC interface
+ (++) As prerequisite, ADC clock must be configured at RCC top level.
+ Caution: On STM32F0, ADC clock frequency max is 14MHz (refer
+ to device datasheet).
+ Therefore, ADC clock prescaler must be configured in
+ function of ADC clock source frequency to remain below
+ this maximum frequency.
+
+ (++) Two clock settings are mandatory:
+ (+++) ADC clock (core clock, also possibly conversion clock).
- RCC_OscInitTypeDef RCC_OscInitStructure;
- RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
- RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
- RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL;
- RCC_OscInitStructure.PLL... (optional if used for system clock)
- HAL_RCC_OscConfig(&RCC_OscInitStructure);
-
- Parameter "HSI14State" must be set either:
- - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control
- the HSI14 oscillator enable/disable (if not used to supply the main
- system clock): feature used if ADC mode LowPowerAutoPowerOff is
- enabled.
- - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator
- always enabled: can be used to supply the main system clock.
+ (+++) ADC clock (conversions clock).
+ Two possible clock sources: synchronous clock derived from APB clock
+ or asynchronous clock derived from ADC dedicated HSI RC oscillator
+ 14MHz.
+ If asynchronous clock is selected, parameter "HSI14State" must be set either:
+ - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control
+ the HSI14 oscillator enable/disable (if not used to supply the main
+ system clock): feature used if ADC mode LowPowerAutoPowerOff is
+ enabled.
+ - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator
+ always enabled: can be used to supply the main system clock.
+
+ (+++) Example:
+ Into HAL_ADC_MspInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory)
+
+ HI14 enable or let under control of ADC: (optional: if asynchronous clock selected)
+ (+++) RCC_OscInitTypeDef RCC_OscInitStructure;
+ (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
+ (+++) RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
+ (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL;
+ (+++) RCC_OscInitStructure.PLL... (optional if used for system clock)
+ (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+ (++) ADC clock source and clock prescaler are configured at ADC level with
+ parameter "ClockPrescaler" using function HAL_ADC_Init().
(#) ADC pins configuration
- (++) Enable the clock for the ADC GPIOs using the following function:
- __GPIOx_CLK_ENABLE();
- (++) Configure these ADC pins in analog mode using HAL_GPIO_Init();
-
- (#) Configure the ADC parameters (conversion resolution, data alignment,
- continuous mode, ...) using the HAL_ADC_Init() function.
+ (++) Enable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+ (++) Configure these ADC pins in analog mode
+ using function HAL_GPIO_Init()
- (#) Activate the ADC peripheral using one of the start functions:
- HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA().
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Configure the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding ADC interruption vector
+ ADCx_IRQHandler().
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+ using function HAL_DMA_Init().
+ (++) Configure the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding DMA interruption vector
+ DMAx_Channelx_IRQHandler().
- *** Channels configuration to regular group ***
- ================================================
- [..]
- (+) To configure the ADC regular group features, use
- HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
- (+) To activate the continuous mode, use the HAL_ADC_Init() function.
- (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
-
- *** DMA for regular configuration ***
- =============================================================
+ *** Configuration of ADC, group regular, channels parameters ***
+ ================================================================
+ [..]
+
+ (#) Configure the ADC parameters (resolution, data alignment, ...)
+ and regular group parameters (conversion trigger, sequencer, ...)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...)
+ using function HAL_ADC_AnalogWDGConfig().
+
+ *** Execution of ADC conversions ***
+ ====================================
[..]
- (+) To enable the DMA mode for regular group, use the
- HAL_ADC_Start_DMA() function.
- (+) To enable the generation of DMA requests continuously at the end of
- the last DMA transfer, use the HAL_ADC_Init() function.
+
+ (#) Optionally, perform an automatic ADC calibration to improve the
+ conversion accuracy
+ using function HAL_ADCEx_Calibration_Start().
+
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
+ (++) ADC conversion by polling:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start()
+ (+++) Wait for ADC conversion completion
+ using function HAL_ADC_PollForConversion()
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop()
+
+ (++) ADC conversion by interruption:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_IT()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback()
+ (this function must be implemented in user program)
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_IT()
+
+ (++) ADC conversion with transfer by DMA:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_DMA()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ (these functions must be implemented in user program)
+ (+++) Conversion results are automatically transferred by DMA into
+ destination variable address.
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_DMA()
+
+ [..]
+
+ (@) Callback functions must be implemented in user program:
+ (+@) HAL_ADC_ErrorCallback()
+ (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+ (+@) HAL_ADC_ConvCpltCallback()
+ (+@) HAL_ADC_ConvHalfCpltCallback
+
+ *** Deinitialization of ADC ***
+ ============================================================
+ [..]
+
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+ (++) ADC clock disable
+ using the equivalent macro/functions as configuration step.
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
+ (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
+ (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA
+ using function HAL_DMA_Init().
+ (++) Disable the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+ [..]
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -147,7 +261,7 @@
* @{
*/
-/** @defgroup ADC ADC HAL module driver
+/** @defgroup ADC ADC
* @brief ADC HAL module driver
* @{
*/
@@ -171,17 +285,16 @@
#define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
#define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 2)
+ /* Delay for ADC stabilization time. */
+ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
+ /* Unit: us */
+ #define ADC_STAB_DELAY_US ((uint32_t) 1)
+
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
- /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 48MHz to */
- /* have the minimum number of CPU cycles to fulfill this delay. */
- #define ADC_TEMPSENSOR_DELAY_CPU_CYCLES ((uint32_t) 480)
+ /* Unit: us */
+ #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
- /* Delay for ADC stabilization time. */
- /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
- /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 48MHz to */
- /* have the minimum number of CPU cycles to fulfill this delay. */
- #define ADC_STAB_DELAY_CPU_CYCLES ((uint32_t)48)
/**
* @}
*/
@@ -247,7 +360,7 @@
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpCFGR1 = 0;
/* Check ADC handle */
@@ -282,9 +395,14 @@
/* - ADC voltage regulator enable */
if (hadc->State == HAL_ADC_STATE_RESET)
{
+ /* Initialize ADC error code */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Allocate lock resource and initialize it */
+ hadc->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
-
}
/* Configuration of ADC parameters if previous preliminary actions are */
@@ -292,17 +410,21 @@
/* and if there is no conversion on going on regular group (ADC can be */
/* enabled anyway, in case of call of this function to update a parameter */
/* on the fly). */
- if ((hadc->State != HAL_ADC_STATE_ERROR) &&
- (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
+ (tmp_hal_status == HAL_OK) &&
+ (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
{
- /* Initialize the ADC state */
- hadc->State = HAL_ADC_STATE_BUSY;
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - ADC clock mode */
/* - ADC clock prescaler */
- if (__HAL_ADC_IS_ENABLED(hadc) == RESET)
+ /* - ADC resolution */
+ if (ADC_IS_ENABLE(hadc) == RESET)
{
/* Some parameters of this register are not reset, since they are set */
/* by other functions and must be kept in case of usage of this */
@@ -312,13 +434,16 @@
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() ) */
- /* Reset configuration of ADC configuration register CFGR2: */
- /* - ADC clock mode: CKMODE */
- hadc->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE);
+ /* Configuration of ADC resolution */
+ MODIFY_REG(hadc->Instance->CFGR1,
+ ADC_CFGR1_RES ,
+ hadc->Init.Resolution );
/* Configuration of ADC clock mode: clock source AHB or HSI with */
/* selectable prescaler */
- hadc->Instance->CFGR2 |= hadc->Init.ClockPrescaler;
+ MODIFY_REG(hadc->Instance->CFGR2 ,
+ ADC_CFGR2_CKMODE ,
+ hadc->Init.ClockPrescaler );
}
/* Configuration of ADC: */
@@ -341,18 +466,16 @@
ADC_CFGR1_EXTSEL |
ADC_CFGR1_EXTEN |
ADC_CFGR1_ALIGN |
- ADC_CFGR1_RES |
ADC_CFGR1_SCANDIR |
ADC_CFGR1_DMACFG );
- tmpCFGR1 |= (__HAL_ADC_CFGR1_AUTOWAIT(hadc->Init.LowPowerAutoWait) |
- __HAL_ADC_CFGR1_AUTOOFF(hadc->Init.LowPowerAutoPowerOff) |
- __HAL_ADC_CFGR1_CONTINUOUS(hadc->Init.ContinuousConvMode) |
- __HAL_ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
- hadc->Init.DataAlign |
- hadc->Init.Resolution |
- __HAL_ADC_CFGR1_SCANDIR(hadc->Init.ScanConvMode) |
- __HAL_ADC_CFGR1_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
+ tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT(hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR1_AUTOOFF(hadc->Init.LowPowerAutoPowerOff) |
+ ADC_CFGR1_CONTINUOUS(hadc->Init.ContinuousConvMode) |
+ ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
+ hadc->Init.DataAlign |
+ ADC_SCANDIR(hadc->Init.ScanConvMode) |
+ ADC_CFGR1_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
/* Enable discontinuous mode only if continuous mode is disabled */
if ((hadc->Init.DiscontinuousConvMode == ENABLE) &&
@@ -364,7 +487,7 @@
/* Enable external trigger if trigger selection is different of software */
/* start. */
- /* @Note: This configuration keeps the hardware feature of parameter */
+ /* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
@@ -376,41 +499,62 @@
/* Update ADC configuration register with previous settings */
hadc->Instance->CFGR1 |= tmpCFGR1;
+ /* Channel sampling time configuration */
+ /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
+ /* (obsolete): sampling time set in this function if parameter */
+ /* "SamplingTimeCommon" has been set to a valid sampling time. */
+ /* Otherwise, sampling time is set into ADC channel initialization */
+ /* structure with parameter "SamplingTime" (obsolete). */
+ if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
+ {
+ /* Channel sampling time configuration */
+ /* Clear the old sample time */
+ hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
+
+ /* Set the new sample time */
+ hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon);
+ }
+
/* Check back that ADC registers have effectively been configured to */
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CFGR1 (excluding analog watchdog configuration: */
- /* set into separate dedicated function). */
- if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL))
+ /* set into separate dedicated function, and bits of ADC resolution set */
+ /* out of temporary variable 'tmpCFGR1'). */
+ if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES))
== tmpCFGR1)
{
/* Set ADC error code to none */
- __HAL_ADC_CLEAR_ERRORCODE(hadc);
+ ADC_CLEAR_ERRORCODE(hadc);
- /* Initialize the ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Set the ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
- hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
- tmpHALStatus = HAL_ERROR;
+ tmp_hal_status = HAL_ERROR;
}
}
else
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- tmpHALStatus = HAL_ERROR;
+ tmp_hal_status = HAL_ERROR;
}
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
@@ -428,7 +572,7 @@
*/
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check ADC handle */
if(hadc == NULL)
@@ -439,20 +583,20 @@
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
/* Stop potential conversion on going, on regular group */
- tmpHALStatus = ADC_ConversionStop(hadc);
+ tmp_hal_status = ADC_ConversionStop(hadc);
/* Disable ADC peripheral if conversions are effectively stopped */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status == HAL_OK)
{
/* Disable the ADC peripheral */
- tmpHALStatus = ADC_Disable(hadc);
+ tmp_hal_status = ADC_Disable(hadc);
/* Check if ADC is effectively disabled */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status != HAL_ERROR)
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_READY;
@@ -462,7 +606,7 @@
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status != HAL_ERROR)
{
/* ========== Reset ADC registers ========== */
@@ -487,7 +631,7 @@
ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN );
/* Reset register CFGR2 */
- /* @Note: Update of ADC clock mode is conditioned to ADC state disabled: */
+ /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
/* already done above. */
hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
@@ -508,9 +652,7 @@
/* bits in access mode read only, no direct reset applicable*/
/* Reset register CCR */
- ADC->CCR &= ~( ADC_CCR_VBATEN |
- ADC_CCR_TSEN |
- ADC_CCR_VREFEN );
+ ADC->CCR &= ~(ADC_CCR_ALL);
/* ========== Hard reset ADC peripheral ========== */
/* Performs a global reset of the entire ADC peripheral: ADC state is */
@@ -518,16 +660,16 @@
/* If needed, copy-paste and uncomment the following reset code into */
/* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
/* */
- /* __ADC1_FORCE_RESET() */
- /* __ADC1_RELEASE_RESET() */
+ /* __HAL_RCC_ADC1_FORCE_RESET() */
+ /* __HAL_RCC_ADC1_RELEASE_RESET() */
/* DeInit the low level hardware */
HAL_ADC_MspDeInit(hadc);
/* Set ADC error code to none */
- __HAL_ADC_CLEAR_ERRORCODE(hadc);
+ ADC_CLEAR_ERRORCODE(hadc);
- /* Change ADC state */
+ /* Set ADC state */
hadc->State = HAL_ADC_STATE_RESET;
}
@@ -535,7 +677,7 @@
__HAL_UNLOCK(hadc);
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
@@ -597,13 +739,13 @@
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
- if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
{
/* Process locked */
__HAL_LOCK(hadc);
@@ -613,17 +755,26 @@
/* performed automatically by hardware. */
if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
{
- tmpHALStatus = ADC_Enable(hadc);
+ tmp_hal_status = ADC_Enable(hadc);
}
/* Start conversion if ADC is effectively enabled */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status == HAL_OK)
{
- /* State machine update: Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
-
- /* Set ADC error code to none */
- __HAL_ADC_CLEAR_ERRORCODE(hadc);
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC */
@@ -636,17 +787,14 @@
/* trigger event. */
hadc->Instance->CR |= ADC_CR_ADSTART;
}
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
}
else
{
- tmpHALStatus = HAL_BUSY;
+ tmp_hal_status = HAL_BUSY;
}
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
/**
@@ -656,7 +804,7 @@
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -665,19 +813,21 @@
__HAL_LOCK(hadc);
/* 1. Stop potential conversion on going, on regular group */
- tmpHALStatus = ADC_ConversionStop(hadc);
+ tmp_hal_status = ADC_ConversionStop(hadc);
/* Disable ADC peripheral if conversions are effectively stopped */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status == HAL_OK)
{
/* 2. Disable the ADC peripheral */
- tmpHALStatus = ADC_Disable(hadc);
+ tmp_hal_status = ADC_Disable(hadc);
/* Check if ADC is effectively disabled */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status == HAL_OK)
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
}
}
@@ -685,11 +835,23 @@
__HAL_UNLOCK(hadc);
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
/**
* @brief Wait for regular group conversion to be completed.
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of
+ * conversion) are cleared by this function, with an exception:
+ * if low power feature "LowPowerAutoWait" is enabled, flags are
+ * not cleared to not interfere with this feature until data register
+ * is read using function HAL_ADC_GetValue().
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode and polling for end of each conversion (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion. Nevertheless, polling can still
+ * be performed on the complete sequence (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
* @param hadc: ADC handle
* @param Timeout: Timeout value in millisecond.
* @retval HAL status
@@ -703,19 +865,38 @@
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* If end of conversion selected to end of sequence */
- if (hadc->Init.EOCSelection == EOC_SEQ_CONV)
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
{
tmp_Flag_EOC = ADC_FLAG_EOS;
}
/* If end of conversion selected to end of each conversion */
- else /* EOC_SINGLE_CONV */
+ else /* ADC_EOC_SINGLE_CONV */
{
- tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */
+ /* several ranks and polling for end of each conversion. */
+ /* For code simplicity sake, this particular case is generalized to */
+ /* ADC configured in DMA mode and and polling for end of each conversion. */
+ if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
+ }
}
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
/* Wait until End of Conversion flag is raised */
while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
{
@@ -725,12 +906,49 @@
if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Update ADC state machine to timeout */
- hadc->State = HAL_ADC_STATE_TIMEOUT;
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
/* Process unlocked */
__HAL_UNLOCK(hadc);
- return HAL_ERROR;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
}
}
@@ -744,13 +962,6 @@
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
}
- /* Update state machine on conversion status if not in error state */
- if(hadc->State != HAL_ADC_STATE_ERROR)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_REG;
- }
-
/* Return ADC state */
return HAL_OK;
}
@@ -760,8 +971,8 @@
* @param hadc: ADC handle
* @param EventType: the ADC event type.
* This parameter can be one of the following values:
- * @arg AWD_EVENT: ADC Analog watchdog event
- * @arg OVR_EVENT: ADC Overrun event
+ * @arg ADC_AWD_EVENT: ADC Analog watchdog event
+ * @arg ADC_OVR_EVENT: ADC Overrun event
* @param Timeout: Timeout value in millisecond.
* @retval HAL status
*/
@@ -773,6 +984,7 @@
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_EVENT_TYPE(EventType));
+ /* Get tick count */
tickstart = HAL_GetTick();
/* Check selected event flag */
@@ -784,7 +996,7 @@
if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Update ADC state machine to timeout */
- hadc->State = HAL_ADC_STATE_TIMEOUT;
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
/* Process unlocked */
__HAL_UNLOCK(hadc);
@@ -797,27 +1009,27 @@
switch(EventType)
{
/* Analog watchdog (level out of window) event */
- case AWD_EVENT:
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_AWD;
+ case ADC_AWD_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
break;
/* Overrun event */
- default: /* Case OVR_EVENT */
+ default: /* Case ADC_OVR_EVENT */
/* If overrun is set to overwrite previous data, overrun event is not */
/* considered as an error. */
/* (cf ref manual "Managing conversions without using the DMA and without */
/* overrun ") */
- if (hadc->Init.Overrun == OVR_DATA_PRESERVED)
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_ERROR;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
/* Set ADC error code to overrun */
- hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
}
/* Clear ADC Overrun flag */
@@ -842,13 +1054,13 @@
*/
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
- if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
{
/* Process locked */
__HAL_LOCK(hadc);
@@ -858,17 +1070,26 @@
/* performed automatically by hardware. */
if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
{
- tmpHALStatus = ADC_Enable(hadc);
+ tmp_hal_status = ADC_Enable(hadc);
}
/* Start conversion if ADC is effectively enabled */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status == HAL_OK)
{
- /* State machine update: Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
- /* Set ADC error code to none */
- __HAL_ADC_CLEAR_ERRORCODE(hadc);
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC */
@@ -879,11 +1100,11 @@
/* Enable ADC overrun interrupt */
switch(hadc->Init.EOCSelection)
{
- case EOC_SEQ_CONV:
+ case ADC_EOC_SEQ_CONV:
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR));
break;
- /* case EOC_SINGLE_CONV */
+ /* case ADC_EOC_SINGLE_CONV */
default:
__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
break;
@@ -895,17 +1116,14 @@
/* trigger event. */
hadc->Instance->CR |= ADC_CR_ADSTART;
}
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
}
else
{
- tmpHALStatus = HAL_BUSY;
+ tmp_hal_status = HAL_BUSY;
}
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
@@ -917,7 +1135,7 @@
*/
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -926,23 +1144,25 @@
__HAL_LOCK(hadc);
/* 1. Stop potential conversion on going, on regular group */
- tmpHALStatus = ADC_ConversionStop(hadc);
-
+ tmp_hal_status = ADC_ConversionStop(hadc);
+
/* Disable ADC peripheral if conversions are effectively stopped */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status == HAL_OK)
{
/* Disable ADC end of conversion interrupt for regular group */
/* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
/* 2. Disable the ADC peripheral */
- tmpHALStatus = ADC_Disable(hadc);
+ tmp_hal_status = ADC_Disable(hadc);
/* Check if ADC is effectively disabled */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status == HAL_OK)
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
}
}
@@ -950,7 +1170,7 @@
__HAL_UNLOCK(hadc);
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
/**
@@ -968,13 +1188,13 @@
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
- if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
{
/* Process locked */
__HAL_LOCK(hadc);
@@ -984,19 +1204,27 @@
/* performed automatically by hardware. */
if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
{
- tmpHALStatus = ADC_Enable(hadc);
+ tmp_hal_status = ADC_Enable(hadc);
}
/* Start conversion if ADC is effectively enabled */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status == HAL_OK)
{
- /* State machine update: Change ADC state */
- hadc->State = HAL_ADC_STATE_BUSY_REG;
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
- /* Set ADC error code to none */
- __HAL_ADC_CLEAR_ERRORCODE(hadc);
-
+ /* Reset ADC all error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
@@ -1030,17 +1258,14 @@
/* trigger event. */
hadc->Instance->CR |= ADC_CR_ADSTART;
}
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
}
else
{
- tmpHALStatus = HAL_BUSY;
+ tmp_hal_status = HAL_BUSY;
}
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
/**
@@ -1052,7 +1277,7 @@
*/
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -1061,34 +1286,34 @@
__HAL_LOCK(hadc);
/* 1. Stop potential conversion on going, on regular group */
- tmpHALStatus = ADC_ConversionStop(hadc);
+ tmp_hal_status = ADC_ConversionStop(hadc);
/* Disable ADC peripheral if conversions are effectively stopped */
- if (tmpHALStatus != HAL_ERROR)
+ if (tmp_hal_status == HAL_OK)
{
/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN;
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* while DMA transfer is on going) */
- tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle);
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
/* Check if DMA channel effectively disabled */
- if (tmpHALStatus != HAL_OK)
+ if (tmp_hal_status != HAL_OK)
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
}
/* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
/* 2. Disable the ADC peripheral */
- /* Update "tmpHALStatus" only if DMA channel disabling passed, to keep in */
- /* memory a potential failing status. */
- if (tmpHALStatus == HAL_OK)
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */
+ /* in memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
{
- tmpHALStatus = ADC_Disable(hadc);
+ tmp_hal_status = ADC_Disable(hadc);
}
else
{
@@ -1096,10 +1321,12 @@
}
/* Check if ADC is effectively disabled */
- if (tmpHALStatus == HAL_OK)
+ if (tmp_hal_status == HAL_OK)
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
}
}
@@ -1108,7 +1335,7 @@
__HAL_UNLOCK(hadc);
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
/**
@@ -1125,7 +1352,7 @@
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
- /* @Note: EOC flag is not cleared here by software because automatically */
+ /* Note: EOC flag is not cleared here by software because automatically */
/* cleared by hardware when reading register DR. */
/* Clear regular group end of sequence flag */
@@ -1136,61 +1363,6 @@
}
/**
- * @brief DMA transfer complete callback.
- * @param hdma: pointer to DMA handle.
- * @retval None
- */
-static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Update state machine on conversion status if not in error state */
- if(hadc->State != HAL_ADC_STATE_ERROR)
- {
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_REG;
- }
-
- /* Conversion complete callback */
- HAL_ADC_ConvCpltCallback(hadc);
-}
-
-/**
- * @brief DMA half transfer complete callback.
- * @param hdma: pointer to DMA handle.
- * @retval None
- */
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
-{
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Half conversion callback */
- HAL_ADC_ConvHalfCpltCallback(hadc);
-}
-
-/**
- * @brief DMA error callback
- * @param hdma: pointer to DMA handle.
- * @retval None
- */
-static void ADC_DMAError(DMA_HandleTypeDef *hdma)
-{
- /* Retrieve ADC handle corresponding to current DMA handle */
- ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_ERROR;
-
- /* Set ADC error code to DMA error */
- hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
-
- /* Error callback */
- HAL_ADC_ErrorCallback(hadc);
-}
-
-/**
* @brief Handles ADC interrupt request.
* @param hadc: ADC handle
* @retval None
@@ -1207,52 +1379,56 @@
(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) )
{
/* Update state machine on conversion status if not in error state */
- if(hadc->State != HAL_ADC_STATE_ERROR)
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_EOC_REG;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
}
- /* Disable interruption if no further conversion upcoming by regular */
- /* external trigger or by continuous mode, */
- /* and if scan sequence if completed. */
- if(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
- (hadc->Init.ContinuousConvMode == DISABLE) )
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
{
/* If End of Sequence is reached, disable interrupts */
if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
{
/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
/* ADSTART==0 (no conversion on going) */
- if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
{
- /* Disable ADC end of sequence conversion interrupt */
- /* @Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
}
else
{
/* Change ADC state to error state */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Set ADC error code to ADC IP internal error */
- hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
}
}
/* Conversion complete callback */
- /* @Note: into callback, to determine if conversion has been triggered */
+ /* Note: into callback, to determine if conversion has been triggered */
/* from EOC or EOS, possibility to use: */
/* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
HAL_ADC_ConvCpltCallback(hadc);
/* Clear regular group conversion flag */
- /* @Note: in case of overrun set to OVR_DATA_PRESERVED, end of conversion */
- /* flags clear induces the release of the preserved data. */
+ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
+ /* conversion flags clear induces the release of the preserved data.*/
/* Therefore, if the preserved data value is needed, it must be */
/* read preliminarily into HAL_ADC_ConvCpltCallback(). */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
@@ -1261,8 +1437,8 @@
/* ========== Check Analog watchdog flags ========== */
if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_AWD;
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
/* Level out of window callback */
HAL_ADC_LevelOutOfWindowCallback(hadc);
@@ -1282,14 +1458,14 @@
/* overrun ") */
/* Exception for usage with DMA overrun event always considered as an */
/* error. */
- if ((hadc->Init.Overrun == OVR_DATA_PRESERVED) ||
+ if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) ||
HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) )
{
- /* Change ADC state to error state */
- hadc->State = HAL_ADC_STATE_ERROR;
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
- /* Set ADC error code to overrun */
- hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
+ /* Clear ADC overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
/* Error callback */
HAL_ADC_ErrorCallback(hadc);
@@ -1397,15 +1573,19 @@
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
__IO uint32_t wait_loop_index = 0;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_RANK(sConfig->Rank));
- assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
-
+
+ if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
+ {
+ assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+ }
+
/* Process locked */
__HAL_LOCK(hadc);
@@ -1414,8 +1594,8 @@
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel sampling time */
- /* - Management of internal measurement channels: Vbat/VrefInt/TempSensor */
- if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
{
/* Configure channel: depending on rank setting, add it or remove it from */
/* ADC conversion sequencer. */
@@ -1423,97 +1603,90 @@
{
/* Regular sequence configuration */
/* Set the channel selection register from the selected channel */
- hadc->Instance->CHSELR |= __HAL_ADC_CHSELR_CHANNEL(sConfig->Channel);
+ hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel);
/* Channel sampling time configuration */
- /* Modify sampling time if needed (not needed in case of reoccurrence */
- /* for several channels programmed consecutively into the sequencer) */
- if (sConfig->SamplingTime != __HAL_ADC_GET_SAMPLINGTIME(hadc))
+ /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */
+ /* (obsolete): sampling time set in this function with */
+ /* parameter "SamplingTime" (obsolete) only if not already set into */
+ /* ADC initialization structure with parameter "SamplingTimeCommon". */
+ if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon))
{
- /* Channel sampling time configuration */
- /* Clear the old sample time */
- hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
-
- /* Set the new sample time */
- hadc->Instance->SMPR |= (sConfig->SamplingTime);
+ /* Modify sampling time if needed (not needed in case of reoccurrence */
+ /* for several channels programmed consecutively into the sequencer) */
+ if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc))
+ {
+ /* Channel sampling time configuration */
+ /* Clear the old sample time */
+ hadc->Instance->SMPR &= ~(ADC_SMPR_SMP);
+
+ /* Set the new sample time */
+ hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime);
+ }
}
-
- /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
+
+ /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
/* internal measurement paths enable: If internal channel selected, */
/* enable dedicated internal buffers and path. */
- /* @Note: these internal measurement paths can be disabled using */
- /* HAL_ADC_DeInit() or removing the channel from sequencer with */
- /* channel configuration parameter "Rank". */
-
- /* If Channel_16 is selected, enable Temp. sensor measurement path. */
- if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit() or removing the channel from sequencer with */
+ /* channel configuration parameter "Rank". */
+ if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
{
- ADC->CCR |= ADC_CCR_TSEN;
+ /* If Channel_16 is selected, enable Temp. sensor measurement path. */
+ /* If Channel_17 is selected, enable VREFINT measurement path. */
+ /* If Channel_18 is selected, enable VBAT measurement path. */
+ ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
- /* Delay for temperature sensor stabilization time */
- while(wait_loop_index < ADC_TEMPSENSOR_DELAY_CPU_CYCLES)
+ /* If Temp. sensor is selected, wait for stabilization delay */
+ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
{
- wait_loop_index++;
+ /* Delay for temperature sensor stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
+ while(wait_loop_index != 0)
+ {
+ wait_loop_index--;
+ }
}
}
- /* If Channel_17 is selected, enable VBAT measurement path. */
- else if (sConfig->Channel == ADC_CHANNEL_VBAT)
- {
- ADC->CCR |= ADC_CCR_VBATEN;
- }
- /* If Channel_18 is selected, enable VREFINT measurement path. */
- else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
- {
- ADC->CCR |= ADC_CCR_VREFEN;
- }
-
}
else
{
/* Regular sequence configuration */
/* Reset the channel selection register from the selected channel */
- hadc->Instance->CHSELR &= ~__HAL_ADC_CHSELR_CHANNEL(sConfig->Channel);
+ hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel);
- /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
+ /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
/* internal measurement paths disable: If internal channel selected, */
/* disable dedicated internal buffers and path. */
-
- /* If Channel_16 is selected, disable Temp. sensor measurement path. */
- if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
{
- ADC->CCR &= ~ADC_CCR_TSEN;
- }
- /* If Channel_17 is selected, disable VBAT measurement path. */
- else if (sConfig->Channel == ADC_CHANNEL_VBAT)
- {
- ADC->CCR &= ~ADC_CCR_VBATEN;
- }
- /* If Channel_18 is selected, disable VREFINT measurement path. */
- else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
- {
- ADC->CCR &= ~ADC_CCR_VREFEN;
+ /* If Channel_16 is selected, disable Temp. sensor measurement path. */
+ /* If Channel_17 is selected, disable VREFINT measurement path. */
+ /* If Channel_18 is selected, disable VBAT measurement path. */
+ ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel);
}
}
-
+
}
-
/* If a conversion is on going on regular group, no update on regular */
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- tmpHALStatus = HAL_ERROR;
+ tmp_hal_status = HAL_ERROR;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
@@ -1533,18 +1706,19 @@
*/
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpAWDHighThresholdShifted;
uint32_t tmpAWDLowThresholdShifted;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
/* Verify if threshold is within the selected ADC resolution */
- assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
- assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
{
@@ -1559,7 +1733,7 @@
/* conversion on going on regular group: */
/* - Analog watchdog channels */
/* - Analog watchdog thresholds */
- if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
{
/* Configuration of analog watchdog: */
/* - Set the analog watchdog enable mode: one or overall group of */
@@ -1570,18 +1744,18 @@
ADC_CFGR1_AWDEN |
ADC_CFGR1_AWDCH );
- hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode |
- __HAL_ADC_CFGR_AWDCH(AnalogWDGConfig->Channel) );
+ hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode |
+ ADC_CFGR_AWDCH(AnalogWDGConfig->Channel) );
/* Shift the offset in function of the selected ADC resolution: Thresholds*/
/* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
- tmpAWDHighThresholdShifted = __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
- tmpAWDLowThresholdShifted = __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+ tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+ tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
/* Set the high and low thresholds */
hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT);
- hadc->Instance->TR |= ( __HAL_ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) |
- tmpAWDLowThresholdShifted );
+ hadc->Instance->TR |= ( ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) |
+ tmpAWDLowThresholdShifted );
/* Clear the ADC Analog watchdog flag (in case of left enabled by */
/* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
@@ -1606,9 +1780,9 @@
else
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
- tmpHALStatus = HAL_ERROR;
+ tmp_hal_status = HAL_ERROR;
}
@@ -1616,7 +1790,7 @@
__HAL_UNLOCK(hadc);
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
@@ -1647,7 +1821,7 @@
* @param hadc: ADC handle
* @retval HAL state
*/
-HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -1682,6 +1856,12 @@
* @brief Enable the selected ADC.
* @note Prerequisite condition to use this function: ADC must be disabled
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
+ * @note If low power mode AutoPowerOff is enabled, power-on/off phases are
+ * performed automatically by hardware.
+ * In this mode, this function is useless and must not be called because
+ * flag ADC_FLAG_RDY is not usable.
+ * Therefore, this function must be called under condition of
+ * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
* @param hadc: ADC handle
* @retval HAL status.
*/
@@ -1694,16 +1874,16 @@
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
- if (__HAL_ADC_IS_ENABLED(hadc) == RESET)
+ if (ADC_IS_ENABLE(hadc) == RESET)
{
/* Check if conditions to enable the ADC are fulfilled */
- if (__HAL_ADC_ENABLING_CONDITIONS(hadc) == RESET)
+ if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
-
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
/* Set ADC error code to ADC IP internal error */
- hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
@@ -1711,14 +1891,15 @@
/* Enable the ADC peripheral */
__HAL_ADC_ENABLE(hadc);
- /* Delay for ADC stabilization time. */
- /* Delay fixed to worst case: maximum CPU frequency */
- while(wait_loop_index < ADC_STAB_DELAY_CPU_CYCLES)
+ /* Delay for ADC stabilization time */
+ /* Compute number of CPU cycles to wait for */
+ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
+ while(wait_loop_index != 0)
{
- wait_loop_index++;
- }
+ wait_loop_index--;
+ }
- /* Get timeout */
+ /* Get tick count */
tickstart = HAL_GetTick();
/* Wait for ADC effectively enabled */
@@ -1727,10 +1908,10 @@
if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
-
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
/* Set ADC error code to ADC IP internal error */
- hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
@@ -1754,12 +1935,12 @@
uint32_t tickstart = 0;
/* Verification if ADC is not already disabled: */
- /* @Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
- /* disabled. */
- if (__HAL_ADC_IS_ENABLED(hadc) != RESET )
+ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
+ /* disabled. */
+ if (ADC_IS_ENABLE(hadc) != RESET)
{
/* Check if conditions to disable the ADC are fulfilled */
- if (__HAL_ADC_DISABLING_CONDITIONS(hadc) != RESET)
+ if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
{
/* Disable the ADC peripheral */
__HAL_ADC_DISABLE(hadc);
@@ -1767,26 +1948,27 @@
else
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
-
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
/* Set ADC error code to ADC IP internal error */
- hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
/* Wait for ADC effectively disabled */
+ /* Get tick count */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
{
- if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
-
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
/* Set ADC error code to ADC IP internal error */
- hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
@@ -1814,7 +1996,7 @@
/* Verification if ADC is not already stopped on regular group to bypass */
/* this function if not needed. */
- if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
{
/* Stop potential conversion on going on regular group */
@@ -1827,6 +2009,7 @@
}
/* Wait for conversion effectively stopped */
+ /* Get tick count */
tickstart = HAL_GetTick();
while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET)
@@ -1834,10 +2017,10 @@
if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
-
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
/* Set ADC error code to ADC IP internal error */
- hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
@@ -1849,6 +2032,102 @@
return HAL_OK;
}
+
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Update state machine on conversion status if not in error state */
+ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
+ (hadc->Init.ContinuousConvMode == DISABLE) )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC IP internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+ HAL_ADC_ConvCpltCallback(hadc);
+ }
+ else
+ {
+ /* Call DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
+
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Half conversion callback */
+ HAL_ADC_ConvHalfCpltCallback(hadc);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma: pointer to DMA handle.
+ * @retval None
+ */
+static void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+ /* Set ADC error code to DMA error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+
+ /* Error callback */
+ HAL_ADC_ErrorCallback(hadc);
+}
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_adc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -64,7 +64,7 @@
* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler')
- * - For all parameters except 'ClockPrescaler': ADC enabled without conversion on going on regular group.
+ * - For all parameters except 'ClockPrescaler' and 'resolution': ADC enabled without conversion on going on regular group.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
*/
@@ -88,8 +88,8 @@
uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
This parameter can be a value of @ref ADC_EOCSelection. */
uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
- conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
- This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
+ conversion (for regular group) has been treated by user software, using function HAL_ADC_GetValue().
+ This feature automatically adapts the ADC conversions trigs to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
@@ -119,6 +119,14 @@
uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten
This parameter has an effect on regular group only, including in DMA mode.
This parameter can be a value of @ref ADC_Overrun */
+ uint32_t SamplingTimeCommon; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ Note: On STM32F0 devices, the sampling time setting is common to all channels. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
+ This parameter can be a value of @ref ADC_sampling_times
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */
}ADC_InitTypeDef;
/**
@@ -135,7 +143,7 @@
This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
- On STM32F0 devices, rank is defined by each channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ On STM32F0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...)..
Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
This parameter can be a value of @ref ADC_rank */
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
@@ -143,6 +151,8 @@
Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
This parameter can be a value of @ref ADC_sampling_times
Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set.
+ Caution: Obsolete parameter. Use parameter "SamplingTimeCommon" in ADC initialization structure.
+ If parameter "SamplingTimeCommon" is set to a valid sampling time, parameter "SamplingTime" is discarded.
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */
@@ -169,26 +179,40 @@
}ADC_AnalogWDGConfTypeDef;
/**
- * @brief HAL ADC state machine: ADC States structure definition
+ * @brief HAL ADC state machine: ADC states definition (bitfields)
*/
-typedef enum
-{
- HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
- HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
- HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
- HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
- HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */
- HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */
- HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
- HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
- HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */
- HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */
- HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */
- HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */
- HAL_ADC_STATE_AWD2 = 0x07, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring several AWD) */
- HAL_ADC_STATE_AWD3 = 0x08, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring several AWD) */
-}HAL_ADC_StateTypeDef;
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+ external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F0 device: End Of Sampling flag raised */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+ external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Not available on STM32F0 device: Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */
+
/**
* @brief ADC handle Structure definition
@@ -199,13 +223,11 @@
ADC_InitTypeDef Init; /*!< ADC required parameters */
- __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */
-
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
HAL_LockTypeDef Lock; /*!< ADC locking object */
- __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
+ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
}ADC_HandleTypeDef;
@@ -237,18 +259,11 @@
/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
* @{
*/
-#define ADC_CLOCK_ASYNC ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI */
+#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI */
#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */
-#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /* Obsolete naming, kept for compatibility with some other devices */
-#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /* Obsolete naming, kept for compatibility with some other devices */
-
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC) || \
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) )
-
/**
* @}
*/
@@ -256,15 +271,10 @@
/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
-#define ADC_RESOLUTION12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
-#define ADC_RESOLUTION10b ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */
-#define ADC_RESOLUTION8b ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */
-#define ADC_RESOLUTION6b ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */
-
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
- ((RESOLUTION) == ADC_RESOLUTION10b) || \
- ((RESOLUTION) == ADC_RESOLUTION8b) || \
- ((RESOLUTION) == ADC_RESOLUTION6b) )
+#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
+#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */
+#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */
+#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */
/**
* @}
*/
@@ -274,9 +284,6 @@
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
- ((ALIGN) == ADC_DATAALIGN_LEFT) )
/**
* @}
*/
@@ -300,8 +307,6 @@
#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
- ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) )
/**
* @}
*/
@@ -313,51 +318,6 @@
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
-
-#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
-/**
- * @}
- */
-
-/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
- * @{
- */
-/* List of external triggers with generic trigger name, sorted by trigger */
-/* name: */
-
-/* External triggers of regular group for ADC1 */
-#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
-#define ADC_EXTERNALTRIGCONV_T1_CC4 ADC1_2_EXTERNALTRIG_T1_CC4
-#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
-#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
-#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
-#define ADC_SOFTWARE_START ((uint32_t)0x00000010)
-
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
- ((REGTRIG) == ADC_SOFTWARE_START) )
-/**
- * @}
- */
-
-/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular
- * @{
- */
-
-/* List of external triggers of regular group for ADC1: */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)0x00000000)
-#define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0)
-#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1)
-#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2)
-
/**
* @}
*/
@@ -365,13 +325,9 @@
/** @defgroup ADC_EOCSelection ADC EOCSelection
* @{
*/
-#define EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
-#define EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
-#define EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
-
-#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV) || \
- ((EOC_SELECTION) == EOC_SEQ_CONV) || \
- ((EOC_SELECTION) == EOC_SINGLE_SEQ_CONV) )
+#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
+#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
+#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
/**
* @}
*/
@@ -379,68 +335,8 @@
/** @defgroup ADC_Overrun ADC Overrun
* @{
*/
-#define OVR_DATA_OVERWRITTEN ((uint32_t)0x00000000)
-#define OVR_DATA_PRESERVED ((uint32_t)0x00000001)
-
-#define IS_ADC_OVERRUN(OVR) (((OVR) == OVR_DATA_PRESERVED) || \
- ((OVR) == OVR_DATA_OVERWRITTEN) )
-/**
- * @}
- */
-
-/** @defgroup ADC_channels ADC channels
- * @{
- */
-/* Note: Depending on devices, some channels may not be available on package */
-/* pins. Refer to device datasheet for channels availability. */
-/* Note: Channels are used by bitfields for setting of channel selection */
-/* (register ADC_CHSELR) and used by number for setting of analog watchdog */
-/* channel (bits AWDCH in register ADC_CFGR1). */
-/* Channels are defined with decimal numbers and converted them to bitfields */
-/* when needed. */
-#define ADC_CHANNEL_0 ((uint32_t) 0x00000000)
-#define ADC_CHANNEL_1 ((uint32_t) 0x00000001)
-#define ADC_CHANNEL_2 ((uint32_t) 0x00000002)
-#define ADC_CHANNEL_3 ((uint32_t) 0x00000003)
-#define ADC_CHANNEL_4 ((uint32_t) 0x00000004)
-#define ADC_CHANNEL_5 ((uint32_t) 0x00000005)
-#define ADC_CHANNEL_6 ((uint32_t) 0x00000006)
-#define ADC_CHANNEL_7 ((uint32_t) 0x00000007)
-#define ADC_CHANNEL_8 ((uint32_t) 0x00000008)
-#define ADC_CHANNEL_9 ((uint32_t) 0x00000009)
-#define ADC_CHANNEL_10 ((uint32_t) 0x0000000A)
-#define ADC_CHANNEL_11 ((uint32_t) 0x0000000B)
-#define ADC_CHANNEL_12 ((uint32_t) 0x0000000C)
-#define ADC_CHANNEL_13 ((uint32_t) 0x0000000D)
-#define ADC_CHANNEL_14 ((uint32_t) 0x0000000E)
-#define ADC_CHANNEL_15 ((uint32_t) 0x0000000F)
-#define ADC_CHANNEL_16 ((uint32_t) 0x00000010)
-#define ADC_CHANNEL_17 ((uint32_t) 0x00000011)
-#define ADC_CHANNEL_18 ((uint32_t) 0x00000012)
-
-#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
-#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
-#define ADC_CHANNEL_VBAT ADC_CHANNEL_18
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
- ((CHANNEL) == ADC_CHANNEL_1) || \
- ((CHANNEL) == ADC_CHANNEL_2) || \
- ((CHANNEL) == ADC_CHANNEL_3) || \
- ((CHANNEL) == ADC_CHANNEL_4) || \
- ((CHANNEL) == ADC_CHANNEL_5) || \
- ((CHANNEL) == ADC_CHANNEL_6) || \
- ((CHANNEL) == ADC_CHANNEL_7) || \
- ((CHANNEL) == ADC_CHANNEL_8) || \
- ((CHANNEL) == ADC_CHANNEL_9) || \
- ((CHANNEL) == ADC_CHANNEL_10) || \
- ((CHANNEL) == ADC_CHANNEL_11) || \
- ((CHANNEL) == ADC_CHANNEL_12) || \
- ((CHANNEL) == ADC_CHANNEL_13) || \
- ((CHANNEL) == ADC_CHANNEL_14) || \
- ((CHANNEL) == ADC_CHANNEL_15) || \
- ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
- ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
- ((CHANNEL) == ADC_CHANNEL_VBAT) )
+#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)0x00000000)
+#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000001)
/**
* @}
*/
@@ -448,19 +344,20 @@
/** @defgroup ADC_rank ADC rank
* @{
*/
-#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /*!< Enable the rank of the selected channels. Rank is defined by each channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
+#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
#define ADC_RANK_NONE ((uint32_t)0x00001001) /*!< Disable the selected rank (selected channel) from sequencer */
-
-#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
- ((WATCHDOG) == ADC_RANK_NONE) )
/**
* @}
*/
/** @defgroup ADC_sampling_times ADC sampling times
* @{
- */
-#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */
+ */
+/* Note: Parameter "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit */
+/* to distinguish this parameter versus reset value 0x00000000, */
+/* in the context of management of parameters "SamplingTimeCommon" */
+/* and "SamplingTime" (obsolete)). */
+#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x10000000) /*!< Sampling time 1.5 ADC clock cycle */
#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */
#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */
#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */
@@ -468,15 +365,6 @@
#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */
#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */
#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR_SMP) /*!< Sampling time 239.5 ADC clock cycles */
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
- ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
/**
* @}
*/
@@ -487,11 +375,6 @@
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
-
-
-#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) )
/**
* @}
*/
@@ -499,11 +382,8 @@
/** @defgroup ADC_Event_type ADC Event type
* @{
*/
-#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */
-#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
-
-#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \
- ((EVENT) == OVR_EVENT) )
+#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */
+#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
/**
* @}
*/
@@ -530,54 +410,192 @@
#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
-
-#define ADC_FLAG_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC | \
- ADC_FLAG_EOSMP | ADC_FLAG_RDY )
-
-/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
-#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
/**
* @}
*/
-/** @defgroup ADC_range_verification ADC range verification
- * in function of ADC resolution selected (12, 10, 8 or 6 bits)
- * @{
+/**
+ * @}
*/
-#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
- ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
- (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
- (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
- (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F))) )
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @addtogroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular
+ * @{
+ */
+
+/* List of external triggers of regular group for ADC1: */
+/* (used internally by HAL driver. To not use into HAL structure parameters) */
+#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0)
+#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1)
+#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0))
+#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2)
/**
* @}
*/
-/** @defgroup ADC_regular_rank_verification ADC regular rank verification
- * @{
- */
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
-/**
- * @}
- */
+/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
+#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
/**
* @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Macros ADC Exported Macros
* @{
*/
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user. */
+
+/**
+ * @brief Enable the ADC peripheral
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE(__HANDLE__) \
+ ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
+
+/**
+ * @brief Disable the ADC peripheral
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \
+ __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
+ } while(0)
+
+/**
+ * @brief Enable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+ * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @arg ADC_IT_OVR: ADC overrun interrupt source
+ * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+ * @arg ADC_IT_RDY: ADC Ready interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the ADC end of conversion interrupt.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC Interrupt
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+ * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @arg ADC_IT_OVR: ADC overrun interrupt source
+ * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+ * @arg ADC_IT_RDY: ADC Ready interrupt source
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
+ * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
+ * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
+ * @arg ADC_IT_OVR: ADC overrun interrupt source
+ * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
+ * @arg ADC_IT_RDY: ADC Ready interrupt source
+ * @retval State ofinterruption (SET or RESET)
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Get the selected ADC's flag status.
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+ * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
+ * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+ * @arg ADC_FLAG_OVR: ADC overrun flag
+ * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
+ * @arg ADC_FLAG_RDY: ADC Ready flag
+ * @retval None
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the ADC's pending flags
+ * @param __HANDLE__: ADC handle
+ * @param __FLAG__: ADC flag
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
+ * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
+ * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
+ * @arg ADC_FLAG_OVR: ADC overrun flag
+ * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
+ * @arg ADC_FLAG_RDY: ADC Ready flag
+ * @retval None
+ */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+
/** @brief Reset ADC handle state
* @param __HANDLE__: ADC handle
* @retval None
*/
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+
+/**
+ * @}
+ */
+
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
-/* Macro for internal HAL driver usage, and possibly can be used into code of */
-/* final user. */
+/**
+ * @brief Verification of hardware constraints before ADC can be enabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
+ */
+#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
+ (( ( ((__HANDLE__)->Instance->CR) & \
+ (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) \
+ ) == RESET \
+ ) ? SET : RESET)
+
+/**
+ * @brief Verification of hardware constraints before ADC can be disabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
+ */
+#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
+ (( ( ((__HANDLE__)->Instance->CR) & \
+ (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
+ ) ? SET : RESET)
/**
* @brief Verification of ADC state: enabled or disabled
@@ -587,11 +605,11 @@
/* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */
/* performed automatically by hardware and flag ADC_FLAG_RDY is not */
/* set. */
-#define __HAL_ADC_IS_ENABLED(__HANDLE__) \
- (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
- (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \
- ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \
- ) ? SET : RESET)
+#define ADC_IS_ENABLE(__HANDLE__) \
+ (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
+ (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \
+ ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \
+ ) ? SET : RESET)
/**
* @brief Test if conversion trigger of regular group is software start
@@ -599,17 +617,17 @@
* @param __HANDLE__: ADC handle
* @retval SET (software start) or RESET (external trigger)
*/
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
- (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
+ (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
/**
* @brief Check if no conversion on going on regular group
* @param __HANDLE__: ADC handle
* @retval SET (conversion is on going) or RESET (no conversion is on going)
*/
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
- (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
- ) ? RESET : SET)
+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
+ ) ? RESET : SET)
/**
* @brief Returns resolution bits in CFGR1 register: RES[1:0].
@@ -617,7 +635,8 @@
* @param __HANDLE__: ADC handle
* @retval None
*/
-#define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
+#define ADC_GET_RESOLUTION(__HANDLE__) \
+ (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
/**
* @brief Returns ADC sample time bits in SMPR register: SMP[2:0].
@@ -625,57 +644,25 @@
* @param __HANDLE__: ADC handle
* @retval None
*/
-#define __HAL_ADC_GET_SAMPLINGTIME(__HANDLE__) (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP)
-
-/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
- * @param __HANDLE__: ADC handle
- * @param __INTERRUPT__: ADC interrupt source to check
- * @retval State ofinterruption (SET or RESET)
- */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__) \
- )? SET : RESET \
- )
-
-/**
- * @brief Enable the ADC end of conversion interrupt.
- * @param __HANDLE__: ADC handle
- * @param __INTERRUPT__: ADC Interrupt
- * @retval None
- */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+#define ADC_GET_SAMPLINGTIME(__HANDLE__) \
+ (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP)
/**
- * @brief Disable the ADC end of conversion interrupt.
- * @param __HANDLE__: ADC handle
- * @param __INTERRUPT__: ADC Interrupt
+ * @brief Simultaneously clears and sets specific bits of the handle State
+ * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ * the first parameter is the ADC handle State, the second parameter is the
+ * bit field to clear, the third and last parameter is the bit field to set.
* @retval None
*/
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/**
- * @brief Get the selected ADC's flag status.
- * @param __HANDLE__: ADC handle
- * @param __FLAG__: ADC flag
- * @retval None
- */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear the ADC's pending flags
- * @param __HANDLE__: ADC handle
- * @param __FLAG__: ADC flag
- * @retval None
- */
-/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+#define ADC_STATE_CLR_SET MODIFY_REG
/**
* @brief Clear ADC error code (set it to error code: "no error")
* @param __HANDLE__: ADC handle
* @retval None
*/
-#define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
+ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
/**
@@ -705,52 +692,61 @@
ADC_CHANNEL_17 ((uint32_t) ADC_CHSELR_CHSEL17)
ADC_CHANNEL_18 ((uint32_t) ADC_CHSELR_CHSEL18)
*/
-#define __HAL_ADC_CHSELR_CHANNEL(_CHANNEL_) ( 1U << (_CHANNEL_))
-
-/**
- * @}
- */
+#define ADC_CHSELR_CHANNEL(_CHANNEL_) \
+ ( 1U << (_CHANNEL_))
-/** @defgroup ADC_Exported_Macro_internal_HAL_driver ADC Exported Macro internal HAL driver
- * @{
+/**
+ * @brief Set the ADC's sample time
+ * @param _SAMPLETIME_: Sample time parameter.
+ * @retval None
*/
-/* Macro reserved for internal HAL driver usage, not intended to be used in */
-/* code of final user. */
+/* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */
+/* "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit (bit used to */
+/* distinguish this parameter versus reset value 0x00000000, */
+/* in the context of management of parameters "SamplingTimeCommon" */
+/* and "SamplingTime" (obsolete)). */
+#define ADC_SMPR_SET(_SAMPLETIME_) \
+ ((_SAMPLETIME_) & (ADC_SMPR_SMP))
/**
* @brief Set the Analog Watchdog 1 channel.
* @param _CHANNEL_: channel to be monitored by Analog Watchdog 1.
* @retval None
*/
-#define __HAL_ADC_CFGR_AWDCH(_CHANNEL_) ((_CHANNEL_) << 26)
+#define ADC_CFGR_AWDCH(_CHANNEL_) \
+ ((_CHANNEL_) << 26)
/**
* @brief Enable ADC discontinuous conversion mode for regular group
* @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
* @retval None
*/
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16)
+#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \
+ ((_REG_DISCONTINUOUS_MODE_) << 16)
/**
* @brief Enable the ADC auto off mode.
* @param _AUTOOFF_: Auto off bit enable or disable.
* @retval None
*/
-#define __HAL_ADC_CFGR1_AUTOOFF(_AUTOOFF_) ((_AUTOOFF_) << 15)
+#define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \
+ ((_AUTOOFF_) << 15)
/**
* @brief Enable the ADC auto delay mode.
* @param _AUTOWAIT_: Auto delay bit enable or disable.
* @retval None
*/
-#define __HAL_ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14)
+#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \
+ ((_AUTOWAIT_) << 14)
/**
* @brief Enable ADC continuous conversion mode.
* @param _CONTINUOUS_MODE_: Continuous mode.
* @retval None
*/
-#define __HAL_ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13)
+#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \
+ ((_CONTINUOUS_MODE_) << 13)
/**
* @brief Enable ADC overrun mode.
@@ -758,10 +754,10 @@
* @retval Overun bit setting to be programmed into CFGR register
*/
/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */
-/* "OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it as the */
-/* default case to be compliant with other STM32 devices. */
-#define __HAL_ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \
- ( ( (_OVERRUN_MODE_) != (OVR_DATA_PRESERVED) \
+/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */
+/* as the default case to be compliant with other STM32 devices. */
+#define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \
+ ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
)? (ADC_CFGR1_OVRMOD) : (0x00000000) \
)
@@ -770,65 +766,31 @@
* @param _SCAN_MODE_: Scan conversion mode.
* @retval None
*/
-#define __HAL_ADC_CFGR1_SCANDIR(_SCAN_MODE_) \
+/* Note: Scan mode set using this macro (instead of parameter direct set) */
+/* due to different modes on other STM32 devices: to avoid any */
+/* unwanted setting, the exact parameter corresponding to the device */
+/* must be passed to this macro. */
+#define ADC_SCANDIR(_SCAN_MODE_) \
( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \
)? (ADC_CFGR1_SCANDIR) : (0x00000000) \
)
-
+
/**
* @brief Enable the ADC DMA continuous request.
* @param _DMACONTREQ_MODE_: DMA continuous request mode.
* @retval None
*/
-#define __HAL_ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1)
+#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \
+ ((_DMACONTREQ_MODE_) << 1)
/**
* @brief Configure the analog watchdog high threshold into register TR.
* @param _Threshold_: Threshold value
* @retval None
*/
-#define __HAL_ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
-
-/**
- * @brief Enable the ADC peripheral
- * @param __HANDLE__: ADC handle
- * @retval None
- */
-#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
-
-/**
- * @brief Verification of hardware constraints before ADC can be enabled
- * @param __HANDLE__: ADC handle
- * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
- */
-#define __HAL_ADC_ENABLING_CONDITIONS(__HANDLE__) \
- (( ( ((__HANDLE__)->Instance->CR) & \
- (ADC_CR_ADCAL | ADC_CR_ADSTP | \
- ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \
- ) == RESET \
- ) ? SET : RESET)
-
-/**
- * @brief Disable the ADC peripheral
- * @param __HANDLE__: ADC handle
- * @retval None
- */
-#define __HAL_ADC_DISABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \
- __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
- } while(0)
-
-/**
- * @brief Verification of hardware constraints before ADC can be disabled
- * @param __HANDLE__: ADC handle
- * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
- */
-#define __HAL_ADC_DISABLING_CONDITIONS(__HANDLE__) \
- (( ( ((__HANDLE__)->Instance->CR) & \
- (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
- ) ? SET : RESET)
-
+#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \
+ ((_Threshold_) << 16)
+
/**
* @brief Shift the AWD threshold in function of the selected ADC resolution.
* Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
@@ -841,8 +803,76 @@
* @param _Threshold_: Value to be shifted
* @retval None
*/
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
- ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2))
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
+ ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2))
+
+
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) )
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_10B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_8B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_6B) )
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT) )
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
+ ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) )
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
+
+#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
+ ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \
+ ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV) )
+
+#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
+ ((OVR) == ADC_OVR_DATA_OVERWRITTEN) )
+
+#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
+ ((WATCHDOG) == ADC_RANK_NONE) )
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
+ ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
+ ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) )
+
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
+ ((EVENT) == ADC_OVR_EVENT) )
+
+/** @defgroup ADC_range_verification ADC range verification
+ * in function of ADC resolution selected (12, 10, 8 or 6 bits)
+ * @{
+ */
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
+ ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))) )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_rank_verification ADC regular rank verification
+ * @{
+ */
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
+/**
+ * @}
+ */
/**
* @}
@@ -920,7 +950,7 @@
/** @addtogroup ADC_Exported_Functions_Group4
* @{
*/
-HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,109 +2,26 @@
******************************************************************************
* @file stm32f0xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
* + Operation functions
* ++ Calibration (ADC automatic self-calibration)
- *
+ * Other functions (generic functions) are available in file
+ * "stm32l1xx_hal_adc.c".
+ *
@verbatim
- ==============================================================================
- ##### ADC specific features #####
- ==============================================================================
[..]
- (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
-
- (#) Interrupt generation at the end of regular conversion and in case of
- analog watchdog or overrun events.
-
- (#) Single and continuous conversion modes.
-
- (#) Scan mode for automatic conversion of channel 0 to channel 'n'.
-
- (#) Data alignment with in-built data coherency.
-
- (#) Programmable sampling time.
-
- (#) ADC conversion group Regular.
-
- (#) External trigger (timer or EXTI) with configurable polarity.
-
- (#) DMA request generation for transfer of conversions data of regular group.
-
- (#) ADC calibration
-
- (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
- slower speed.
-
- (#) ADC input range: from Vref minud (connected to Vssa) to Vref plus(connected to
- Vdda or to an external voltage reference).
-
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
-
- (#) Enable the ADC interface
- As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured
- at RCC top level: clock source and clock prescaler.
- Two possible clock sources: synchronous clock derived from APB clock
- or asynchronous clock derived from ADC dedicated HSI RC oscillator
- 14MHz.
- Example:
- __ADC1_CLK_ENABLE(); (mandatory)
-
- HI14 enable or let under control of ADC: (optional)
-
- RCC_OscInitTypeDef RCC_OscInitStructure;
- RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
- RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
- RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL;
- RCC_OscInitStructure.PLL... (optional if used for system clock)
- HAL_RCC_OscConfig(&RCC_OscInitStructure);
-
- Parameter "HSI14State" must be set either:
- - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control
- the HSI14 oscillator enable/disable (if not used to supply the main
- system clock): feature used if ADC mode LowPowerAutoPowerOff is
- enabled.
- - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator
- always enabled: can be used to supply the main system clock.
-
- (#) ADC pins configuration
- (++) Enable the clock for the ADC GPIOs using the following function:
- __GPIOx_CLK_ENABLE();
- (++) Configure these ADC pins in analog mode using HAL_GPIO_Init();
-
- (#) Configure the ADC parameters (conversion resolution, data alignment,
- continuous mode, ...) using the HAL_ADC_Init() function.
-
- (#) Activate the ADC peripheral using one of the start functions:
- HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA().
-
- *** Regular channels group configuration ***
- ============================================
- [..]
- (+) To configure the ADC regular channels group features, use
- HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
- (+) To activate the continuous mode, use the HAL_ADC_Init() function.
- (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
-
- *** DMA for Regular channels group features configuration ***
- =============================================================
- [..]
- (+) To enable the DMA mode for regular channels group, use the
- HAL_ADC_Start_DMA() function.
- (+) To enable the generation of DMA requests continuously at the end of
- the last DMA transfer, use the HAL_ADC_Init() function.
-
- @endverbatim
+ (@) Sections "ADC peripheral features" and "How to use this driver" are
+ available in file of generic functions "stm32l1xx_hal_adc.c".
+ [..]
+ @endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -138,7 +55,7 @@
* @{
*/
-/** @defgroup ADCEx ADCEx Extended HAL Module Driver
+/** @defgroup ADCEx ADCEx
* @brief ADC HAL module driver
* @{
*/
@@ -163,8 +80,8 @@
/**
* @}
*/
-
-/* Private macro -------------------------------------------------------------*/
+
+/* Private macros -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
@@ -174,9 +91,9 @@
*/
/** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
- * @brief Extended Initialization and Configuration functions
+ * @brief Extended Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@@ -197,7 +114,7 @@
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
{
- HAL_StatusTypeDef tmpHALStatus = HAL_OK;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tickstart=0;
/* Check the parameters */
@@ -205,12 +122,14 @@
/* Process locked */
__HAL_LOCK(hadc);
-
- /* Calibration prerequisite: ADC must be disabled. */
- if (__HAL_ADC_IS_ENABLED(hadc) == RESET )
+
+ /* Calibration prerequisite: ADC must be disabled. */
+ if (ADC_IS_ENABLE(hadc) == RESET)
{
- /* Change ADC state */
- hadc->State = HAL_ADC_STATE_READY;
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
/* Start ADC calibration */
hadc->Instance->CR |= ADC_CR_ADCAL;
@@ -223,7 +142,9 @@
if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
/* Process unlocked */
__HAL_UNLOCK(hadc);
@@ -231,18 +152,25 @@
return HAL_ERROR;
}
}
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
- hadc->State = HAL_ADC_STATE_ERROR;
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
- return tmpHALStatus;
+ return tmp_hal_status;
}
/**
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_adc_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of ADC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -56,7 +56,226 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define ADC_CCR_ALL (ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN)
+#else
+#define ADC_CCR_ALL (ADC_CCR_TSEN | ADC_CCR_VREFEN)
+#endif
+
+/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
+ * @{
+ */
+/* List of external triggers with generic trigger name, sorted by trigger */
+/* name: */
+
+/* External triggers of regular group for ADC1 */
+#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
+#define ADC_EXTERNALTRIGCONV_T1_CC4 ADC1_2_EXTERNALTRIG_T1_CC4
+#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
+#define ADC_SOFTWARE_START (ADC_CFGR1_EXTSEL + (uint32_t)1)
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
+#endif
+
+#if !defined(STM32F030x6) && !defined(STM32F070x6) && !defined(STM32F042x6)
+#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
+#endif
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_channels ADC channels
+ * @{
+ */
+/* Note: Depending on devices, some channels may not be available on package */
+/* pins. Refer to device datasheet for channels availability. */
+/* Note: Channels are used by bitfields for setting of channel selection */
+/* (register ADC_CHSELR) and used by number for setting of analog */
+/* watchdog channel (bits AWDCH in register ADC_CFGR1). */
+/* Channels are defined with decimal numbers and converted them to */
+/* bitfields when needed. */
+#define ADC_CHANNEL_0 ((uint32_t) 0x00000000)
+#define ADC_CHANNEL_1 ((uint32_t) 0x00000001)
+#define ADC_CHANNEL_2 ((uint32_t) 0x00000002)
+#define ADC_CHANNEL_3 ((uint32_t) 0x00000003)
+#define ADC_CHANNEL_4 ((uint32_t) 0x00000004)
+#define ADC_CHANNEL_5 ((uint32_t) 0x00000005)
+#define ADC_CHANNEL_6 ((uint32_t) 0x00000006)
+#define ADC_CHANNEL_7 ((uint32_t) 0x00000007)
+#define ADC_CHANNEL_8 ((uint32_t) 0x00000008)
+#define ADC_CHANNEL_9 ((uint32_t) 0x00000009)
+#define ADC_CHANNEL_10 ((uint32_t) 0x0000000A)
+#define ADC_CHANNEL_11 ((uint32_t) 0x0000000B)
+#define ADC_CHANNEL_12 ((uint32_t) 0x0000000C)
+#define ADC_CHANNEL_13 ((uint32_t) 0x0000000D)
+#define ADC_CHANNEL_14 ((uint32_t) 0x0000000E)
+#define ADC_CHANNEL_15 ((uint32_t) 0x0000000F)
+#define ADC_CHANNEL_16 ((uint32_t) 0x00000010)
+#define ADC_CHANNEL_17 ((uint32_t) 0x00000011)
+
+#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
+#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define ADC_CHANNEL_18 ((uint32_t) 0x00000012)
+#define ADC_CHANNEL_VBAT ADC_CHANNEL_18
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
/* Exported macro ------------------------------------------------------------*/
+
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macros ADCEx Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+/**
+ * @brief Test if the selected ADC channel is an internal channel
+ * VrefInt/TempSensor/Vbat
+ * Note: On STM32F0, availability of internal channel Vbat depends on
+ * devices lines.
+ * @param __CHANNEL__: ADC channel
+ * @retval None
+ */
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ (((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) \
+ )
+#else
+#define ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ (((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT) \
+ )
+#endif
+
+/**
+ * @brief Select the internal measurement path to be enabled/disabled
+ * corresponding to the selected ADC internal channel
+ * VrefInt/TempSensor/Vbat.
+ * Note: On STM32F0, availability of internal channel Vbat depends on
+ * devices lines.
+ * @param __CHANNEL__: ADC channel
+ * @retval Bit of register ADC_CCR
+ */
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define ADC_CHANNEL_INTERNAL_PATH(__CHANNEL__) \
+ (( (__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR \
+ )? \
+ (ADC_CCR_TSEN) \
+ : \
+ ( \
+ ( (__CHANNEL__) == ADC_CHANNEL_VREFINT \
+ )? \
+ (ADC_CCR_VREFEN) \
+ : \
+ (ADC_CCR_VBATEN) \
+ ) \
+ )
+#else
+#define ADC_CHANNEL_INTERNAL_PATH(__CHANNEL__) \
+ (( (__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR \
+ )? \
+ (ADC_CCR_TSEN) \
+ : \
+ (ADC_CHANNEL_VREFINT) \
+ )
+#endif
+
+
+#if defined (STM32F030x6) || defined (STM32F070x6)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_SOFTWARE_START))
+#elif defined (STM32F042x6)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_SOFTWARE_START))
+
+#elif defined (STM32F030xC) || defined (STM32F070xB) || defined (STM32F030x8)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ ((REGTRIG) == ADC_SOFTWARE_START))
+#else
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
+ ((REGTRIG) == ADC_SOFTWARE_START))
+#endif
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
+ ((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
+ ((CHANNEL) == ADC_CHANNEL_VBAT) )
+#else
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
+ ((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((CHANNEL) == ADC_CHANNEL_VREFINT) )
+#endif
+
+/**
+ * @}
+ */
+
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADCEx_Exported_Functions
* @{
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_can.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
@@ -17,11 +17,11 @@
##### How to use this driver #####
==============================================================================
[..]
- (#) Enable the CAN controller interface clock using __CAN_CLK_ENABLE();
+ (#) Enable the CAN controller interface clock using __HAL_RCC_CAN1_CLK_ENABLE();
(#) CAN pins configuration
(++) Enable the clock for the CAN GPIOs using the following function:
- __GPIOx_CLK_ENABLE();
+ __HAL_RCC_GPIOx_CLK_ENABLE();
(++) Connect and configure the involved CAN pins to AF9 using the
following function HAL_GPIO_Init();
@@ -71,7 +71,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -109,7 +109,7 @@
* @{
*/
-/** @defgroup CAN CAN HAL Module Driver
+/** @defgroup CAN CAN
* @brief CAN driver modules
* @{
*/
@@ -119,7 +119,7 @@
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
-#define HAL_CAN_DEFAULT_TIMEOUT 10
+#define CAN_TIMEOUT_VALUE 10
/**
* @}
*/
@@ -190,6 +190,8 @@
if(hcan->State == HAL_CAN_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hcan->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CAN_MspInit(hcan);
}
@@ -203,15 +205,17 @@
/* Request initialisation */
hcan->Instance->MCR |= CAN_MCR_INRQ ;
- /* Get tickstart */
+ /* Get tick */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
{
- if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
return HAL_TIMEOUT;
}
}
@@ -289,15 +293,17 @@
/* Request leave initialisation */
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
- /* Get timeout */
+ /* Get tick */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
- if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
return HAL_TIMEOUT;
}
}
@@ -355,6 +361,10 @@
/* Initialisation mode for the filter */
hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT;
+
+ /* Select the start slave bank */
+ hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
+ hcan->Instance->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
/* Filter Deactivation */
hcan->Instance->FA1R &= ~(uint32_t)filternbrbitpos;
@@ -493,8 +503,8 @@
* @}
*/
-/** @defgroup CAN_Exported_Functions_Group2 I/O operation functions
- * @brief I/O operation functions
+/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
+ * @brief IO operation functions
*
@verbatim
==============================================================================
@@ -590,7 +600,7 @@
/* Request transmission */
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
- /* Get timeout */
+ /* Get tick */
tickstart = HAL_GetTick();
/* Check End of transmission flag */
@@ -782,7 +792,7 @@
hcan->State = HAL_CAN_STATE_BUSY_RX;
}
- /* Get timeout */
+ /* Get tick */
tickstart = HAL_GetTick();
/* Check pending message */
@@ -957,13 +967,13 @@
return HAL_ERROR;
}
- /* Get timeout */
+ /* Get tick */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
{
- if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
@@ -1002,13 +1012,13 @@
/* Wake up request */
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
- /* Get timeout */
+ /* Get tick */
tickstart = HAL_GetTick();
/* Sleep mode status */
while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
{
- if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
@@ -1245,7 +1255,6 @@
*
* @{
*/
-
/**
* @brief Initiates and transmits a CAN frame message.
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
@@ -1380,7 +1389,6 @@
/* Return function status */
return HAL_OK;
}
-
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_can.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -52,7 +52,7 @@
* @{
*/
-/** @addtogroup CAN CAN HAL Module Driver
+/** @addtogroup CAN
* @{
*/
@@ -180,7 +180,7 @@
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
- uint32_t Data[8]; /*!< Contains the data to be transmitted.
+ uint8_t Data[8]; /*!< Contains the data to be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
}CanTxMsgTypeDef;
@@ -205,7 +205,7 @@
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
- uint32_t Data[8]; /*!< Contains the data to be received.
+ uint8_t Data[8]; /*!< Contains the data to be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
@@ -234,7 +234,7 @@
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
__IO uint32_t ErrorCode; /*!< CAN Error code
- This parameter can be a value of @ref CAN_Error */
+ This parameter can be a value of @ref HAL_CAN_Error_Code */
}CAN_HandleTypeDef;
/**
@@ -247,7 +247,7 @@
* @{
*/
-/** @defgroup CAN_Error CAN Error
+/** @defgroup HAL_CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
@@ -280,11 +280,6 @@
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
- ((MODE) == CAN_MODE_LOOPBACK)|| \
- ((MODE) == CAN_MODE_SILENT) || \
- ((MODE) == CAN_MODE_SILENT_LOOPBACK))
/**
* @}
*/
@@ -297,9 +292,6 @@
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
- ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
/**
* @}
*/
@@ -324,7 +316,6 @@
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
/**
* @}
*/
@@ -341,23 +332,6 @@
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-/**
- * @}
- */
-
-/** @defgroup CAN_clock_prescaler CAN clock prescaler
- * @{
- */
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_number CAN filter number
- * @{
- */
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
/**
* @}
*/
@@ -368,8 +342,6 @@
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
- ((MODE) == CAN_FILTERMODE_IDLIST))
/**
* @}
*/
@@ -380,8 +352,6 @@
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
- ((SCALE) == CAN_FILTERSCALE_32BIT))
/**
* @}
*/
@@ -392,31 +362,6 @@
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
- ((FIFO) == CAN_FILTER_FIFO1))
-
-/* Legacy defines */
-#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
-/**
- * @}
- */
-
-/** @defgroup CAN_Start_bank_filter_for_slave_CAN CAN Start bank filter for slave CAN
- * @{
- */
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
-/**
- * @}
- */
-
-/** @defgroup CAN_Tx CAN Tx
- * @{
- */
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
/**
* @}
*/
@@ -426,8 +371,7 @@
*/
#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
- ((IDTYPE) == CAN_ID_EXT))
+
/**
* @}
*/
@@ -437,19 +381,6 @@
*/
#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-
-/**
- * @}
- */
-
-/** @defgroup CAN_transmit_constants CAN transmit constants
- * @{
- */
-#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) /*!< CAN transmission failed */
-#define CAN_TXSTATUS_OK ((uint8_t)0x01) /*!< CAN transmission succeeded */
-#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /*!< CAN transmission pending */
-#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
/**
* @}
@@ -461,7 +392,6 @@
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
/**
* @}
*/
@@ -532,26 +462,10 @@
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
-/* Flags named as Interrupts : kept only for FW compatibility */
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
/**
* @}
*/
-/** @defgroup CAN_Timeouts CAN Timeouts
-* @{
-*/
-
-/* Time out for INAK bit */
-#define INAK_TIMEOUT ((uint32_t)0x00FFFFFF)
-/* Time out for SLAK bit */
-#define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF)
-/**
- * @}
- */
-
/** @defgroup CAN_Mailboxes CAN Mailboxes
* @{
*/
@@ -630,7 +544,6 @@
* @arg CAN_FLAG_BOF: Bus-Off Flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
@@ -751,7 +664,7 @@
* @}
*/
-/** @addtogroup CAN_Exported_Functions_Group2 I/O operation functions
+/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
* @brief I/O operation functions
* @{
*/
@@ -789,6 +702,79 @@
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CAN_Private_Types CAN Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Variables CAN Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_cec.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief CEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface
@@ -47,7 +47,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -88,7 +88,7 @@
* @{
*/
-/** @defgroup CEC CEC HAL Module Driver
+/** @defgroup CEC CEC
* @brief HAL CEC module driver
* @{
*/
@@ -161,7 +161,8 @@
return HAL_ERROR;
}
- /* Check the parameters */
+ /* Check the parameters */
+ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
@@ -172,12 +173,13 @@
assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress));
assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress));
-
-
+
if(hcec->State == HAL_CEC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hcec->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK */
- HAL_CEC_MspInit(hcec);
+ HAL_CEC_MspInit(hcec);
}
hcec->State = HAL_CEC_STATE_BUSY;
@@ -365,7 +367,7 @@
hcec->TxXferCount--;
tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_TXBR))
+ while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR))
{
if(Timeout != HAL_MAX_DELAY)
{
@@ -384,19 +386,19 @@
* has Tx Missing Acknowledge error occurred ?
* has Arbitration Loss error occurred ? */
tempisr = hcec->Instance->ISR;
- if ((tempisr & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST)) != 0)
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
{
/* copy ISR for error handling purposes */
hcec->ErrorCode = tempisr;
/* clear all error flags by default */
- __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST));
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
hcec->State = HAL_CEC_STATE_ERROR;
__HAL_UNLOCK(hcec);
return HAL_ERROR;
}
}
/* TXBR to clear BEFORE writing TXDR register */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR);
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
if (hcec->TxXferCount == 0)
{
/* if last byte transmission, set TX End of Message (TXEOM) bit */
@@ -406,12 +408,12 @@
/* error check after TX byte write up */
tempisr = hcec->Instance->ISR;
- if ((tempisr & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST)) != 0)
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
{
/* copy ISR for error handling purposes */
hcec->ErrorCode = tempisr;
/* clear all error flags by default */
- __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE|CEC_ISR_ARBLST));
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
hcec->State = HAL_CEC_STATE_ERROR;
__HAL_UNLOCK(hcec);
return HAL_ERROR;
@@ -438,12 +440,12 @@
/* Final error check once all bytes have been transmitted */
tempisr = hcec->Instance->ISR;
- if ((tempisr & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0)
+ if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0)
{
/* copy ISR for error handling purposes */
hcec->ErrorCode = tempisr;
/* clear all error flags by default */
- __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE));
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE));
hcec->State = HAL_CEC_STATE_ERROR;
__HAL_UNLOCK(hcec);
return HAL_ERROR;
@@ -490,12 +492,12 @@
__HAL_LOCK(hcec);
- /* Rx loop until CEC_ISR_RXEND is set */
- while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))
+ /* Rx loop until CEC_FLAG_RXEND is set */
+ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))
{
tickstart = HAL_GetTick();
/* Wait for next byte to be received */
- while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR))
+ while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR))
{
if(Timeout != HAL_MAX_DELAY)
{
@@ -513,46 +515,46 @@
* has Rx Bit Rising error occurred ?
* has Rx Overrun error occurred ? */
temp = (uint32_t) (hcec->Instance->ISR);
- if ((temp & (CEC_ISR_RXACKE|CEC_ISR_LBPE|CEC_ISR_SBPE|CEC_ISR_BRE|CEC_ISR_RXOVR)) != 0)
+ if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0)
{
/* copy ISR for error handling purposes */
hcec->ErrorCode = temp;
/* clear all error flags by default */
- __HAL_CEC_CLEAR_FLAG(hcec, (CEC_ISR_RXACKE|CEC_ISR_LBPE|CEC_ISR_SBPE|CEC_ISR_BRE|CEC_ISR_RXOVR));
+ __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR));
hcec->State = HAL_CEC_STATE_ERROR;
__HAL_UNLOCK(hcec);
return HAL_ERROR;
}
- } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */
+ } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR)) */
/* read received data */
*pData++ = hcec->Instance->RXDR;
temp = (uint32_t) (hcec->Instance->ISR);
/* end of message ? */
- if ((temp & CEC_ISR_RXEND) != 0)
+ if ((temp & CEC_FLAG_RXEND) != 0)
{
assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize));
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXEND);
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);
hcec->State = HAL_CEC_STATE_READY;
__HAL_UNLOCK(hcec);
return HAL_OK;
}
/* clear Rx-Byte Received flag */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXBR);
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR);
/* increment payload byte counter */
hcec->RxXferSize++;
- } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */
+ } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND)) */
/* if the instructions below are executed, it means RXEND was set when RXBR was
* set for the first time:
- * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))"
+ * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))"
* loop has not been executed and this means a single byte has been sent */
*pData++ = hcec->Instance->RXDR;
/* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */
hcec->RxXferSize = 0;
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXEND);
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);
hcec->State = HAL_CEC_STATE_READY;
__HAL_UNLOCK(hcec);
@@ -609,7 +611,7 @@
* Tx-Error IT
* Tx-Buffer Underrun IT
* Tx arbitration lost */
- __HAL_CEC_ENABLE_IT(hcec, CEC_IER_TXBRIE|CEC_IER_TXENDIE|CEC_IER_TX_ALL_ERR);
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
@@ -656,14 +658,14 @@
__HAL_CEC_DISABLE(hcec);
/* Disable the CEC Transmission Interrupts */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TXBRIE|CEC_IER_TXENDIE);
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
/* Disable the CEC Transmission Error Interrupts */
__HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR|CEC_ISR_TXEND);
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
hcec->State = HAL_CEC_STATE_READY;
/* Call the Process Unlocked before calling the Tx call back API to give the possibility to
@@ -682,7 +684,7 @@
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* clear Tx-Byte request flag */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR);
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
hcec->TxXferCount--;
@@ -744,7 +746,7 @@
/* Enable the following two CEC Reception interrupts:
* Rx Byte Received IT
* End of Reception IT */
- __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RXBRIE|CEC_IER_RXENDIE);
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND);
__HAL_CEC_ENABLE(hcec);
@@ -756,7 +758,15 @@
}
}
-
+/**
+ * @brief Get size of the received frame.
+ * @param hcec: CEC handle
+ * @retval Frame size
+ */
+uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec)
+{
+ return hcec->RxXferSize;
+}
/**
* @brief This function handles CEC interrupt requests.
@@ -768,65 +778,65 @@
/* save interrupts register for further error or interrupts handling purposes */
hcec->ErrorCode = hcec->Instance->ISR;
/* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/
- if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXACKEIE) != RESET))
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET))
{
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_TXACKE);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE);
hcec->State = HAL_CEC_STATE_ERROR;
}
/* CEC transmit error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXERRIE) != RESET))
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET))
{
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_TXERR);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR);
hcec->State = HAL_CEC_STATE_ERROR;
}
/* CEC TX underrun error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXUDRIE) != RESET))
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET))
{
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_TXUDR);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR);
hcec->State = HAL_CEC_STATE_ERROR;
}
/* CEC TX arbitration error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_IT(hcec, CEC_ISR_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_ARBLSTIE) != RESET))
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET))
{
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_ARBLST);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
hcec->State = HAL_CEC_STATE_ERROR;
}
/* CEC RX overrun error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXOVRIE) != RESET))
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET))
{
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_RXOVR);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR);
hcec->State = HAL_CEC_STATE_ERROR;
}
/* CEC RX bit rising error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_IT(hcec, CEC_ISR_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_BREIE) != RESET))
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET))
{
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_BRE);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE);
hcec->State = HAL_CEC_STATE_ERROR;
}
/* CEC RX short bit period error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_IT(hcec, CEC_ISR_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_SBPEIE) != RESET))
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET))
{
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_SBPE);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE);
hcec->State = HAL_CEC_STATE_ERROR;
}
/* CEC RX long bit period error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_IT(hcec, CEC_ISR_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_LBPEIE) != RESET))
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET))
{
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_LBPE);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE);
hcec->State = HAL_CEC_STATE_ERROR;
}
/* CEC RX missing acknowledge error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXACKEIE) != RESET))
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET))
{
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_RXACKE);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE);
hcec->State = HAL_CEC_STATE_ERROR;
}
@@ -836,14 +846,14 @@
}
/* CEC RX byte received interrupt ---------------------------------------------------*/
- if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXBRIE) != RESET))
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET))
{
/* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
CEC_Receive_IT(hcec);
}
/* CEC RX end received interrupt ---------------------------------------------------*/
- if((__HAL_CEC_GET_IT(hcec, CEC_ISR_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_RXENDIE) != RESET))
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET))
{
/* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
CEC_Receive_IT(hcec);
@@ -851,14 +861,14 @@
/* CEC TX byte request interrupt ------------------------------------------------*/
- if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXBRIE) != RESET))
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET))
{
/* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */
CEC_Transmit_IT(hcec);
}
/* CEC TX end interrupt ------------------------------------------------*/
- if((__HAL_CEC_GET_IT(hcec, CEC_ISR_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IER_TXENDIE) != RESET))
+ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET))
{
/* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */
CEC_Transmit_IT(hcec);
@@ -983,17 +993,17 @@
__HAL_CEC_DISABLE(hcec);
/* Disable the CEC Transmission Interrupts */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TXBRIE|CEC_IER_TXENDIE);
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
/* Disable the CEC Transmission Error Interrupts */
__HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR|CEC_ISR_TXEND);
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
/* If RX interruptions are enabled, return to HAL_CEC_STATE_STANDBY_RX state */
- if (__HAL_CEC_GET_IT_SOURCE(hcec, (CEC_IER_RXBRIE|CEC_IER_RXENDIE) ) != RESET)
+ if (__HAL_CEC_GET_IT_SOURCE(hcec, (CEC_IT_RXBR|CEC_IT_RXEND) ) != RESET)
{
hcec->State = HAL_CEC_STATE_STANDBY_RX;
}
@@ -1014,7 +1024,7 @@
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* clear Tx-Byte request flag */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_TXBR);
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
hcec->TxXferCount--;
@@ -1055,15 +1065,15 @@
/* reception is starting */
hcec->State = HAL_CEC_STATE_BUSY_RX;
tempisr = (uint32_t) (hcec->Instance->ISR);
- if ((tempisr & CEC_ISR_RXBR) != 0)
+ if ((tempisr & CEC_FLAG_RXBR) != 0)
{
/* read received byte */
*hcec->pRxBuffPtr++ = hcec->Instance->RXDR;
/* if last byte has been received */
- if ((tempisr & CEC_ISR_RXEND) != 0)
+ if ((tempisr & CEC_FLAG_RXEND) != 0)
{
/* clear IT */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_ISR_RXBR|CEC_ISR_RXEND);
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR|CEC_FLAG_RXEND);
/* RX interrupts are not disabled at this point.
* Indeed, to disable the IT, the IP must be disabled first
* which resets the TXSOM flag. In case of arbitration loss,
@@ -1081,7 +1091,7 @@
return HAL_OK;
}
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_ISR_RXBR);
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
hcec->RxXferSize++;
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cec.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_cec.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +54,7 @@
* @{
*/
-/** @addtogroup CEC CEC HAL Module Driver
+/** @addtogroup CEC CEC
* @{
*/
@@ -144,24 +144,6 @@
}HAL_CEC_StateTypeDef;
/**
- * @brief HAL Error structures definition
- */
-typedef enum
-{
- HAL_CEC_ERROR_NONE = (uint32_t) 0x0, /*!< no error */
- HAL_CEC_ERROR_RXOVR = CEC_ISR_RXOVR, /*!< CEC Rx-Overrun */
- HAL_CEC_ERROR_BRE = CEC_ISR_BRE, /*!< CEC Rx Bit Rising Error */
- HAL_CEC_ERROR_SBPE = CEC_ISR_SBPE, /*!< CEC Rx Short Bit period Error */
- HAL_CEC_ERROR_LBPE = CEC_ISR_LBPE, /*!< CEC Rx Long Bit period Error */
- HAL_CEC_ERROR_RXACKE = CEC_ISR_RXACKE, /*!< CEC Rx Missing Acknowledge */
- HAL_CEC_ERROR_ARBLST = CEC_ISR_ARBLST, /*!< CEC Arbitration Lost */
- HAL_CEC_ERROR_TXUDR = CEC_ISR_TXUDR, /*!< CEC Tx-Buffer Underrun */
- HAL_CEC_ERROR_TXERR = CEC_ISR_TXERR, /*!< CEC Tx-Error */
- HAL_CEC_ERROR_TXACKE = CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
-}
-HAL_CEC_ErrorTypeDef;
-
-/**
* @brief CEC handle Structure definition
*/
typedef struct
@@ -178,7 +160,7 @@
uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */
- __IO uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register
+ uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register
in case error is reported */
HAL_LockTypeDef Lock; /* Locking object */
@@ -194,7 +176,24 @@
/** @defgroup CEC_Exported_Constants CEC Exported Constants
* @{
*/
-
+
+/** @defgroup CEC_Error_Code CEC Error Code
+ * @{
+ */
+#define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< no error */
+#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
+#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
+#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
+#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
+#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
+#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
+#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
+#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
+#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
+/**
+ * @}
+ */
+
/** @defgroup CEC_Signal_Free_Time Signal Free Time setting parameter
* @{
*/
@@ -206,7 +205,6 @@
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)
-#define IS_CEC_SIGNALFREETIME(SFT) ((SFT) <= CEC_CFGR_SFT)
/**
* @}
*/
@@ -216,8 +214,6 @@
*/
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
-#define IS_CEC_TOLERANCE(RXTOL) (((RXTOL) == CEC_STANDARD_TOLERANCE) || \
- ((RXTOL) == CEC_EXTENDED_TOLERANCE))
/**
* @}
*/
@@ -227,8 +223,6 @@
*/
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
-#define IS_CEC_BRERXSTOP(BRERXSTOP) (((BRERXSTOP) == CEC_NO_RX_STOP_ON_BRE) || \
- ((BRERXSTOP) == CEC_RX_STOP_ON_BRE))
/**
* @}
*/
@@ -238,8 +232,6 @@
*/
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
-#define IS_CEC_BREERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
- ((ERRORBITGEN) == CEC_BRE_ERRORBIT_GENERATION))
/**
* @}
*/
@@ -249,8 +241,6 @@
*/
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
-#define IS_CEC_LBPEERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
- ((ERRORBITGEN) == CEC_LBPE_ERRORBIT_GENERATION))
/**
* @}
*/
@@ -260,8 +250,6 @@
*/
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
-#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(ERRORBITGEN) (((ERRORBITGEN) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
- ((ERRORBITGEN) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
/**
* @}
*/
@@ -271,8 +259,6 @@
*/
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
-#define IS_CEC_SFTOP(SFTOP) (((SFTOP) == CEC_SFT_START_ON_TXSOM) || \
- ((SFTOP) == CEC_SFT_START_ON_TX_RX_END))
/**
* @}
*/
@@ -282,11 +268,66 @@
*/
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
-#define IS_CEC_LISTENING_MODE(MODE) (((MODE) == CEC_REDUCED_LISTENING_MODE) || \
- ((MODE) == CEC_FULL_LISTENING_MODE))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_OAR_Position Device Own Address position in CEC CFGR register
+ * @{
+ */
+#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Initiator_Position Initiator logical address position in message header
+ * @{
+ */
+#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)
/**
* @}
*/
+
+/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
+ * @{
+ */
+#define CEC_IT_TXACKE CEC_IER_TXACKEIE
+#define CEC_IT_TXERR CEC_IER_TXERRIE
+#define CEC_IT_TXUDR CEC_IER_TXUDRIE
+#define CEC_IT_TXEND CEC_IER_TXENDIE
+#define CEC_IT_TXBR CEC_IER_TXBRIE
+#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
+#define CEC_IT_RXACKE CEC_IER_RXACKEIE
+#define CEC_IT_LBPE CEC_IER_LBPEIE
+#define CEC_IT_SBPE CEC_IER_SBPEIE
+#define CEC_IT_BRE CEC_IER_BREIE
+#define CEC_IT_RXOVR CEC_IER_RXOVRIE
+#define CEC_IT_RXEND CEC_IER_RXENDIE
+#define CEC_IT_RXBR CEC_IER_RXBRIE
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Flags_Definitions CEC Flags definition
+ * @{
+ */
+#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
+#define CEC_FLAG_TXERR CEC_ISR_TXERR
+#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
+#define CEC_FLAG_TXEND CEC_ISR_TXEND
+#define CEC_FLAG_TXBR CEC_ISR_TXBR
+#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
+#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
+#define CEC_FLAG_LBPE CEC_ISR_LBPE
+#define CEC_FLAG_SBPE CEC_ISR_SBPE
+#define CEC_FLAG_BRE CEC_ISR_BRE
+#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
+#define CEC_FLAG_RXEND CEC_ISR_RXEND
+#define CEC_FLAG_RXBR CEC_ISR_RXBR
+/**
+ * @}
+ */
+
/** @defgroup CEC_ALL_ERROR all RX or TX errors flags in CEC ISR register
* @{
@@ -311,23 +352,7 @@
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
/**
* @}
- */
-
-/** @defgroup CEC_OAR_Position Device Own Address position in CEC CFGR register
- * @{
- */
-#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)
-/**
- * @}
- */
-
-/** @defgroup CEC_Initiator_Position Initiator logical address position in message header
- * @{
- */
-#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)
-/**
- * @}
- */
+ */
/**
* @}
@@ -346,63 +371,62 @@
/** @brief Checks whether or not the specified CEC interrupt flag is set.
* @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the interrupt to check.
- * This parameter can be one of the following values:
- * @arg CEC_ISR_RXBR : Rx-Byte Received
- * @arg CEC_ISR_RXEND : End of Reception
- * @arg CEC_ISR_RXOVR : Rx Overrun
- * @arg CEC_ISR_BRE : Rx Bit Rising Error
- * @arg CEC_ISR_SBPE : Rx Short Bit Period Error
- * @arg CEC_ISR_LBPE : Rx Long Bit Period Error
- * @arg CEC_ISR_RXACKE : Rx Missing Acknowledge
- * @arg CEC_ISR_ARBLST : Arbitration lost
- * @arg CEC_ISR_TXBR : Tx-Byte Request
- * @arg CEC_ISR_TXEND : End of Transmission
- * @arg CEC_ISR_TXUDR : Tx-buffer Underrun
- * @arg CEC_ISR_TXERR : Tx Error
- * @arg CEC_ISR_TXACKE : Tx Missing Acknowledge
- * @retval ITStatus
+ * @param __FLAG__: specifies the interrupt to check.
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+ * @arg CEC_FLAG_TXERR: Tx Error.
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_LBPE: Rx Long period Error
+ * @arg CEC_FLAG_SBPE: Rx Short period Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.
+ * @arg CEC_FLAG_RXEND: End Of Reception.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @retval None
*/
-#define __HAL_CEC_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
+#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/** @brief Clears the interrupt or status flag when raised (write at 1)
* @param __HANDLE__: specifies the CEC Handle.
* @param __FLAG__: specifies the interrupt/status flag to clear.
* This parameter can be one of the following values:
- * @arg CEC_ISR_RXBR : Rx-Byte Received
- * @arg CEC_ISR_RXEND : End of Reception
- * @arg CEC_ISR_RXOVR : Rx Overrun
- * @arg CEC_ISR_BRE : Rx Bit Rising Error
- * @arg CEC_ISR_SBPE : Rx Short Bit Period Error
- * @arg CEC_ISR_LBPE : Rx Long Bit Period Error
- * @arg CEC_ISR_RXACKE : Rx Missing Acknowledge
- * @arg CEC_ISR_ARBLST : Arbitration lost
- * @arg CEC_ISR_TXBR : Tx-Byte Request
- * @arg CEC_ISR_TXEND : End of Transmission
- * @arg CEC_ISR_TXUDR : Tx-buffer Underrun
- * @arg CEC_ISR_TXERR : Tx Error
- * @arg CEC_ISR_TXACKE : Tx Missing Acknowledge
+ * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
+ * @arg CEC_FLAG_TXERR: Tx Error.
+ * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
+ * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
+ * @arg CEC_FLAG_TXBR: Tx-Byte Request.
+ * @arg CEC_FLAG_ARBLST: Arbitration Lost
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_LBPE: Rx Long period Error
+ * @arg CEC_FLAG_SBPE: Rx Short period Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+ * @arg CEC_FLAG_RXOVR: Rx Overrun.
+ * @arg CEC_FLAG_RXEND: End Of Reception.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
* @retval none
*/
-#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR = (__FLAG__))
+#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
/** @brief Enables the specified CEC interrupt.
* @param __HANDLE__: specifies the CEC Handle.
* @param __INTERRUPT__: specifies the CEC interrupt to enable.
* This parameter can be one of the following values:
- * @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable
- * @arg CEC_IER_RXENDIE : End Of Reception IT Enable
- * @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable
- * @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable
- * @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable
- * @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable
- * @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable
- * @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable
- * @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable
- * @arg CEC_IER_TXENDIE : End of Transmission IT Enable
- * @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable
- * @arg CEC_IER_TXERRIE : Tx-Error IT Enable
- * @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval none
*/
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
@@ -411,19 +435,19 @@
* @param __HANDLE__: specifies the CEC Handle.
* @param __INTERRUPT__: specifies the CEC interrupt to disable.
* This parameter can be one of the following values:
- * @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable
- * @arg CEC_IER_RXENDIE : End Of Reception IT Enable
- * @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable
- * @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable
- * @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable
- * @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable
- * @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable
- * @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable
- * @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable
- * @arg CEC_IER_TXENDIE : End of Transmission IT Enable
- * @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable
- * @arg CEC_IER_TXERRIE : Tx-Error IT Enable
- * @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval none
*/
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
@@ -432,19 +456,19 @@
* @param __HANDLE__: specifies the CEC Handle.
* @param __INTERRUPT__: specifies the CEC interrupt to check.
* This parameter can be one of the following values:
- * @arg CEC_IER_RXBRIE : Rx-Byte Received IT Enable
- * @arg CEC_IER_RXENDIE : End Of Reception IT Enable
- * @arg CEC_IER_RXOVRIE : Rx-Overrun IT Enable
- * @arg CEC_IER_BREIE : Rx Bit Rising Error IT Enable
- * @arg CEC_IER_SBPEIE : Rx Short Bit period Error IT Enable
- * @arg CEC_IER_LBPEIE : Rx Long Bit period Error IT Enable
- * @arg CEC_IER_RXACKEIE : Rx Missing Acknowledge IT Enable
- * @arg CEC_IER_ARBLSTIE : Arbitration Lost IT Enable
- * @arg CEC_IER_TXBRIE : Tx Byte Request IT Enable
- * @arg CEC_IER_TXENDIE : End of Transmission IT Enable
- * @arg CEC_IER_TXUDRIE : Tx-Buffer Underrun IT Enable
- * @arg CEC_IER_TXERRIE : Tx-Error IT Enable
- * @arg CEC_IER_TXACKEIE : Tx Missing Acknowledge IT Enable
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval FlagStatus
*/
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
@@ -499,7 +523,112 @@
* @retval none
*/
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CEC_Exported_Functions
+ * @{
+ */
+/** @addtogroup CEC_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
+void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
+uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
+void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/** @addtogroup CEC_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CEC_Private_Types CEC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Variables CEC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Macros CEC Private Macros
+ * @{
+ */
+
+#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
+
+#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
+ ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
+
+#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
+ ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
+
+#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
+
+#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
+
+#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
+
+#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
+ ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
+
+#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
+ ((__MODE__) == CEC_FULL_LISTENING_MODE))
+
/** @brief Check CEC device Own Address Register (OAR) setting.
* OAR address is written in a 15-bit field within CEC_CFGR register.
* @param __ADDRESS__: CEC own address.
@@ -521,57 +650,17 @@
* @param __SIZE__: CEC message size.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CEC_Exported_Functions CEC Exported Functions
- * @{
- */
-/** @addtogroup CEC_Exported_Functions_Group1 Initialization/de-initialization function
- * @brief Initialization and Configuration functions
- * @{
- */
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
-HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
-void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
-void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
+
/**
* @}
- */
+ */
-/** @addtogroup CEC_Exported_Functions_Group2 IO operation function
- * @brief CEC Transmit/Receive functions
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
* @{
- */
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
-HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
-void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
-void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
-void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
-void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
-/**
- * @}
*/
-
-/** @addtogroup CEC_Exported_Functions_Group3 Peripheral Control function
- * @brief CEC control functions
- * @{
- */
-/* Peripheral State functions ************************************************/
-HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
-uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
-/**
- * @}
- */
-
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_comp.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief COMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
@@ -19,25 +19,24 @@
[..]
The STM32F0xx device family integrates up to 2 analog comparators COMP1 and COMP2:
- (#) The non inverting input and inverting input can be set to GPIO pins
+ (+) The non inverting input and inverting input can be set to GPIO pins
as shown in table1. COMP Inputs below.
- (#) The COMP output is available using HAL_COMP_GetOutputLevel()
+ (+) The COMP output is available using HAL_COMP_GetOutputLevel()
and can be set on GPIO pins. Refer to table 2. COMP Outputs below.
- (#) The COMP output can be redirected to embedded timers (TIM1, TIM2 and TIM3)
+ (+) The COMP output can be redirected to embedded timers (TIM1, TIM2 and TIM3)
Refer to table 3. COMP Outputs redirection to embedded timers below.
- (#) The comparators COMP1 and COMP2 can be combined in window mode.
+ (+) The comparators COMP1 and COMP2 can be combined in window mode.
- (#) The comparators have interrupt capability with wake-up
+ (+) The comparators have interrupt capability with wake-up
from Sleep and Stop modes (through the EXTI controller):
(++) COMP1 is internally connected to EXTI Line 21
(++) COMP2 is internally connected to EXTI Line 22
- From the corresponding IRQ handler, the right interrupt source can be retrieved with the
- macro __HAL_COMP_EXTI_GET_FLAG(). Possible values are:
- (++) COMP_EXTI_LINE_COMP1_EVENT
- (++) COMP_EXTI_LINE_COMP2_EVENT
+
+ (+) From the corresponding IRQ handler, the right interrupt source can be retrieved with the
+ macros __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
[..] Table 1. COMP Inputs for the STM32F05x, STM32F07x and STM32F09x devices
@@ -100,23 +99,36 @@
interrupt vector using HAL_NVIC_EnableIRQ() function.
(#) Configure the comparator using HAL_COMP_Init() function:
- (++) Select the inverting input
- (++) Select the non inverting input
+ (++) Select the inverting input (input minus)
+ (++) Select the non inverting input (input plus)
(++) Select the output polarity
(++) Select the output redirection
(++) Select the hysteresis level
(++) Select the power mode
(++) Select the event/interrupt mode
+ (++) Select the window mode
- (#) Enable the comparator using HAL_COMP_Start() function or HAL_COMP_Start_IT() function for interrupt mode
+ -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() in order
+ to access the comparator(s) registers.
+
+ (#) Enable the comparator using HAL_COMP_Start() function or HAL_COMP_Start_IT() function for interrupt mode.
- (#) Read the comparator output level with HAL_COMP_GetOutputLevel()
-
+ (#) Use HAL_COMP_TriggerCallback() and/or HAL_COMP_GetOutputLevel() functions
+ to manage comparator outputs (event/interrupt triggered and output level).
+
+ (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
+ function.
+
+ (#) De-initialize the comparator using HAL_COMP_DeInit() function.
+
+ (#) For safety purposes comparator(s) can be locked using HAL_COMP_Lock() function.
+ Only a MCU reset can reset that protection.
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -156,7 +168,7 @@
* @{
*/
-/** @defgroup COMP COMP HAL Module Driver
+/** @defgroup COMP COMP
* @brief COMP HAL module driver
* @{
*/
@@ -235,19 +247,26 @@
assert_param(IS_COMP_DAC1SWITCH_INSTANCE(hcomp->Instance));
}
- if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLED)
+ if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
{
assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance));
}
-
+
+ /* Init SYSCFG and the low level hardware to access comparators */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Init the low level hardware : SYSCFG to access comparators */
+ HAL_COMP_MspInit(hcomp);
+
if(hcomp->State == HAL_COMP_STATE_RESET)
{
- /* Init SYSCFG and the low level hardware to access comparators */
- __SYSCFG_CLK_ENABLE();
+ /* Allocate lock resource and initialize it */
+ hcomp->Lock = HAL_UNLOCKED;
+ }
- HAL_COMP_MspInit(hcomp);
- }
-
+ /* Change COMP peripheral state */
+ hcomp->State = HAL_COMP_STATE_BUSY;
+
/* Set COMP parameters */
/* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */
/* Set COMPxOUTSEL bits according to hcomp->Init.Output value */
@@ -259,7 +278,7 @@
regshift = COMP_CSR_COMP2_SHIFT;
}
MODIFY_REG(COMP->CSR,
- (uint32_t)(COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL_MASK | \
+ (COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL_MASK | \
COMP_CSR_COMPxOUTSEL | COMP_CSR_COMPxPOL | \
COMP_CSR_COMPxHYST | COMP_CSR_COMPxMODE) << regshift,
(hcomp->Init.InvertingInput | \
@@ -269,16 +288,13 @@
hcomp->Init.Hysteresis | \
hcomp->Init.Mode) << regshift);
- if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLED)
+ if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
{
COMP->CSR |= COMP_CSR_WNDWEN;
}
/* Initialize the COMP state*/
- if(hcomp->State == HAL_COMP_STATE_RESET)
- {
- hcomp->State = HAL_COMP_STATE_READY;
- }
+ hcomp->State = HAL_COMP_STATE_READY;
}
return status;
@@ -319,6 +335,9 @@
HAL_COMP_MspDeInit(hcomp);
hcomp->State = HAL_COMP_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcomp);
}
return status;
@@ -394,7 +413,7 @@
{
regshift = COMP_CSR_COMP2_SHIFT;
}
- SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift);
+ SET_BIT(COMP->CSR, COMP_CSR_COMPxEN << regshift);
hcomp->State = HAL_COMP_STATE_BUSY;
}
@@ -434,7 +453,7 @@
{
regshift = COMP_CSR_COMP2_SHIFT;
}
- CLEAR_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift);
+ CLEAR_BIT(COMP->CSR, COMP_CSR_COMPxEN << regshift);
hcomp->State = HAL_COMP_STATE_READY;
}
@@ -464,29 +483,31 @@
if(status == HAL_OK)
{
/* Check the Exti Line output configuration */
- extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance);
+ extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
/* Configure the rising edge */
if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET)
{
- __HAL_COMP_EXTI_RISING_IT_ENABLE(extiline);
+ SET_BIT(EXTI->RTSR, extiline);
}
else
{
- __HAL_COMP_EXTI_RISING_IT_DISABLE(extiline);
+ CLEAR_BIT(EXTI->RTSR, extiline);
}
/* Configure the falling edge */
if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET)
{
- __HAL_COMP_EXTI_FALLING_IT_ENABLE(extiline);
+ SET_BIT(EXTI->FTSR, extiline);
}
else
{
- __HAL_COMP_EXTI_FALLING_IT_DISABLE(extiline);
+ CLEAR_BIT(EXTI->FTSR, extiline);
}
+
+ /* Clear COMP EXTI pending bit */
+ WRITE_REG(EXTI->PR, extiline);
+
/* Enable Exti interrupt mode */
- __HAL_COMP_EXTI_ENABLE_IT(extiline);
- /* Clear COMP Exti pending bit */
- __HAL_COMP_EXTI_CLEAR_FLAG(extiline);
+ SET_BIT(EXTI->IMR, extiline);
}
return status;
@@ -502,7 +523,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Disable the Exti Line interrupt mode */
- __HAL_COMP_EXTI_DISABLE_IT(__HAL_COMP_GET_EXTI_LINE(hcomp->Instance));
+ CLEAR_BIT(EXTI->IMR, COMP_GET_EXTI_LINE(hcomp->Instance));
status = HAL_COMP_Stop(hcomp);
@@ -516,17 +537,17 @@
*/
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
{
- uint32_t extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance);
+ uint32_t extiline = COMP_GET_EXTI_LINE(hcomp->Instance);
/* Check COMP Exti flag */
- if(__HAL_COMP_EXTI_GET_FLAG(extiline) != RESET)
+ if(READ_BIT(EXTI->PR, extiline) != RESET)
{
/* Clear COMP Exti pending bit */
- __HAL_COMP_EXTI_CLEAR_FLAG(extiline);
+ WRITE_REG(EXTI->PR, extiline);
/* COMP trigger user callback */
HAL_COMP_TriggerCallback(hcomp);
- }
+ }
}
/**
@@ -576,7 +597,7 @@
{
regshift = COMP_CSR_COMP2_SHIFT;
}
- SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxLOCK << regshift);
+ SET_BIT(COMP->CSR, COMP_CSR_COMPxLOCK << regshift);
}
return status;
@@ -611,7 +632,7 @@
{
regshift = COMP_CSR_COMP2_SHIFT;
}
- level = READ_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxOUT << regshift);
+ level = READ_BIT(COMP->CSR, COMP_CSR_COMPxOUT << regshift);
if(level != 0)
{
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_comp.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_comp.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +54,7 @@
* @{
*/
-/** @addtogroup COMP COMP HAL Module Driver
+/** @addtogroup COMP COMP
* @{
*/
@@ -134,9 +134,6 @@
*/
#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */
-
-#define IS_COMP_OUTPUTPOL(POL) (((POL) == COMP_OUTPUTPOL_NONINVERTED) || \
- ((POL) == COMP_OUTPUTPOL_INVERTED))
/**
* @}
*/
@@ -148,11 +145,6 @@
#define COMP_HYSTERESIS_LOW COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */
#define COMP_HYSTERESIS_MEDIUM COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */
#define COMP_HYSTERESIS_HIGH COMP_CSR_COMP1HYST /*!< Hysteresis level high */
-
-#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_HYSTERESIS_NONE) || \
- ((HYSTERESIS) == COMP_HYSTERESIS_LOW) || \
- ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \
- ((HYSTERESIS) == COMP_HYSTERESIS_HIGH))
/**
* @}
*/
@@ -166,12 +158,6 @@
#define COMP_MODE_MEDIUMSPEED COMP_CSR_COMP1MODE_0 /*!< Medium Speed */
#define COMP_MODE_LOWPOWER COMP_CSR_COMP1MODE_1 /*!< Low power mode */
#define COMP_MODE_ULTRALOWPOWER COMP_CSR_COMP1MODE /*!< Ultra-low power mode */
-
-#define IS_COMP_MODE(MODE) (((MODE) == COMP_MODE_HIGHSPEED) || \
- ((MODE) == COMP_MODE_MEDIUMSPEED) || \
- ((MODE) == COMP_MODE_LOWPOWER) || \
- ((MODE) == COMP_MODE_ULTRALOWPOWER))
-
/**
* @}
*/
@@ -189,15 +175,6 @@
and close switch (PA0 for COMP1 only) */
#define COMP_INVERTINGINPUT_DAC2 (COMP_CSR_COMP1INSEL_2|COMP_CSR_COMP1INSEL_0) /*!< DAC_OUT2 (PA5) connected to comparator inverting input */
#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMP1INSEL_2|COMP_CSR_COMP1INSEL_1) /*!< IO (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */
-
-#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC1) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC1SWITCHCLOSED) || \
- ((INPUT) == COMP_INVERTINGINPUT_DAC2) || \
- ((INPUT) == COMP_INVERTINGINPUT_IO1))
/**
* @}
*/
@@ -208,9 +185,6 @@
#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA3 for COMP2)
connected to comparator non inverting input */
#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
-
-#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
- ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
/**
* @}
*/
@@ -228,16 +202,6 @@
#define COMP_OUTPUT_TIM2OCREFCLR (COMP_CSR_COMP1OUTSEL_2|COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM2 OCREF Clear */
#define COMP_OUTPUT_TIM3IC1 (COMP_CSR_COMP1OUTSEL_2|COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM3 Input Capture 1 */
#define COMP_OUTPUT_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
- ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
- ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))
-
/**
* @}
*/
@@ -262,11 +226,9 @@
#define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
#define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
#define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-
-#define IS_COMP_TRIGGERMODE(MODE) (((MODE) == COMP_TRIGGERMODE_NONE) || \
- ((MODE) == COMP_TRIGGERMODE_IT_RISING) || \
- ((MODE) == COMP_TRIGGERMODE_IT_FALLING) || \
- ((MODE) == COMP_TRIGGERMODE_IT_RISING_FALLING))
+#define COMP_TRIGGERMODE_EVENT_RISING ((uint32_t)0x00000010) /*!< Event Mode with Rising edge trigger detection */
+#define COMP_TRIGGERMODE_EVENT_FALLING ((uint32_t)0x00000020) /*!< Event Mode with Falling edge trigger detection */
+#define COMP_TRIGGERMODE_EVENT_RISING_FALLING ((uint32_t)0x00000030) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@@ -274,40 +236,22 @@
/** @defgroup COMP_WindowMode COMP WindowMode
* @{
*/
-#define COMP_WINDOWMODE_DISABLED ((uint32_t)0x00000000) /*!< Window mode disabled */
-#define COMP_WINDOWMODE_ENABLED COMP_CSR_WNDWEN /*!< Window mode enabled: non inverting input of comparator 2
+#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled */
+#define COMP_WINDOWMODE_ENABLE COMP_CSR_WNDWEN /*!< Window mode enabled: non inverting input of comparator 2
is connected to the non inverting input of comparator 1 (PA1) */
-
-#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLED) || \
- ((WINDOWMODE) == COMP_WINDOWMODE_ENABLED))
/**
* @}
*/
-/** @defgroup COMP_ExtiLineEvent COMP ExtiLineEvent
- * Elements values convention: XXXX0000
- * - XXXX : Interrupt mask in the EMR/IMR/RTSR/FTSR register
- * @{
- */
-#define COMP_EXTI_LINE_COMP1_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to COMP1 */
-#define COMP_EXTI_LINE_COMP2_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to COMP2 */
+/** @defgroup COMP_Flag COMP Flag
+ * @{
+ */
+#define COMP_FLAG_LOCK ((uint32_t)COMP_CSR_COMPxLOCK) /*!< Lock flag */
/**
* @}
*/
-/** @defgroup COMP_Lock COMP Lock
- * @{
- */
-#define COMP_LOCK_DISABLE ((uint32_t)0x00000000)
-#define COMP_LOCK_ENABLE COMP_CSR_COMP1LOCK
-
-#define COMP_STATE_BIT_LOCK ((uint32_t)0x10)
-/**
- * @}
- */
-
-
/**
* @}
*/
@@ -324,76 +268,209 @@
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
/**
- * @brief Checks whether the specified EXTI line flag is set or not.
- * @param __FLAG__: specifies the COMP Exti sources to be checked.
- * This parameter can be a value of @ref COMP_ExtiLineEvent
- * @retval The state of __FLAG__ (SET or RESET).
+ * @brief Enable the specified comparator.
+ * @param __HANDLE__: COMP handle.
+ * @retval None
+ */
+#define __HAL_COMP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \
+ SET_BIT(COMP->CSR, COMP_CSR_COMP1EN) : \
+ SET_BIT(COMP->CSR, COMP_CSR_COMP2EN))
+
+/**
+ * @brief Disable the specified comparator.
+ * @param __HANDLE__: COMP handle.
+ * @retval None
+ */
+#define __HAL_COMP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \
+ CLEAR_BIT(COMP->CSR, COMP_CSR_COMP1EN) : \
+ CLEAR_BIT(COMP->CSR, COMP_CSR_COMP2EN))
+
+/**
+ * @brief Lock the specified comparator configuration.
+ * @param __HANDLE__: COMP handle.
+ * @retval None
*/
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (EXTI->PR & (__FLAG__))
-
+#define __HAL_COMP_LOCK(__HANDLE__) (((__HANDLE__)->Instance == COMP1) ? \
+ SET_BIT(COMP->CSR, COMP_CSR_COMP1LOCK) : \
+ SET_BIT(COMP->CSR, COMP_CSR_COMP2LOCK))
+
+/**
+ * @brief Enable the COMP1 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
+
/**
- * @brief Clear the COMP Exti flags.
- * @param __FLAG__: specifies the COMP Exti sources to be cleared.
- * This parameter can be a value of @ref COMP_ExtiLineEvent
- * @retval None.
- */
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__))
+ * @brief Disable the COMP1 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Enable the COMP1 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
/**
- * @brief Enable the COMP Exti Line.
- * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
- * This parameter can be a value of @ref COMP_ExtiLineEvent
- * @retval None.
+ * @brief Disable the COMP1 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Enable the COMP1 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Disable the COMP1 EXTI line rising & falling edge trigger.
+ * @retval None
*/
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
-
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Enable the COMP1 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
+
/**
- * @brief Disable the COMP Exti Line.
- * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
- * This parameter can be a value of @ref COMP_ExtiLineEvent
- * @retval None.
+ * @brief Disable the COMP1 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Generate a software interrupt on the COMP1 EXTI line.
+ * @retval None
*/
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
+#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Enable the COMP1 EXTI Line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Disable the COMP1 EXTI Line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1)
/**
- * @brief Enable the Exti Line rising edge trigger.
- * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
- * This parameter can be a value of @ref COMP_ExtiLineEvent
- * @retval None.
+ * @brief Check whether the COMP1 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Clear the COMP1 EXTI flag.
+ * @retval None
+ */
+#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1)
+
+/**
+ * @brief Enable the COMP2 EXTI line rising edge trigger.
+ * @retval None
*/
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (EXTI->RTSR |= (__EXTILINE__))
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
/**
- * @brief Disable the Exti Line rising edge trigger.
- * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
- * This parameter can be a value of @ref COMP_ExtiLineEvent
- * @retval None.
+ * @brief Disable the COMP2 EXTI line rising edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Enable the COMP2 EXTI line falling edge trigger.
+ * @retval None
*/
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (EXTI->RTSR &= ~(__EXTILINE__))
+#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI line falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Enable the COMP2 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0)
/**
- * @brief Enable the Exti Line falling edge trigger.
- * @param __EXTILINE__: specifies the COMP Exti sources to be enabled.
- * This parameter can be a value of @ref COMP_ExtiLineEvent
- * @retval None.
+ * @brief Disable the COMP2 EXTI line rising & falling edge trigger.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
+
+/**
+ * @brief Enable the COMP2 EXTI line in interrupt mode.
+ * @retval None
*/
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (EXTI->FTSR |= (__EXTILINE__))
+#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI line in interrupt mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Generate a software interrupt on the COMP2 EXTI line.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2)
/**
- * @brief Disable the Exti Line falling edge trigger.
- * @param __EXTILINE__: specifies the COMP Exti sources to be disabled.
- * This parameter can be a value of @ref COMP_ExtiLineEvent
- * @retval None.
- */
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (EXTI->FTSR &= ~(__EXTILINE__))
+ * @brief Enable the COMP2 EXTI Line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Disable the COMP2 EXTI Line in event mode.
+ * @retval None
+ */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2)
/**
- * @brief Get the specified EXTI line for a comparator instance
- * @param __INSTANCE__: specifies the COMP instance.
- * @retval value of @ref COMP_ExtiLineEvent
+ * @brief Check whether the COMP2 EXTI line flag is set or not.
+ * @retval RESET or SET
+ */
+#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2)
+
+/**
+ * @brief Clear the COMP2 EXTI flag.
+ * @retval None
*/
-#define __HAL_COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1_EVENT : \
- COMP_EXTI_LINE_COMP2_EVENT)
+#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2)
+
+/** @brief Check whether the specified COMP flag is set or not.
+ * @param __HANDLE__: specifies the COMP Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg COMP_FLAG_LOCK: lock flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__))
+
/**
* @}
*/
@@ -457,6 +534,114 @@
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_Private_Constants COMP Private Constants
+ * @{
+ */
+/** @defgroup COMP_ExtiLine COMP EXTI Lines
+ * Elements values convention: XXXX0000
+ * - XXXX : Interrupt mask in the EMR/IMR/RTSR/FTSR register
+ * @{
+ */
+#define COMP_EXTI_LINE_COMP1 ((uint32_t)EXTI_IMR_MR21) /*!< EXTI line 21 connected to COMP1 output */
+#define COMP_EXTI_LINE_COMP2 ((uint32_t)EXTI_IMR_MR22) /*!< EXTI line 22 connected to COMP2 output */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_Private_Macros COMP Private Macros
+ * @{
+ */
+/** @defgroup COMP_GET_EXTI_LINE COMP Private macros to get EXTI line associated with Comparators
+ * @{
+ */
+/**
+ * @brief Get the specified EXTI line for a comparator instance.
+ * @param __INSTANCE__: specifies the COMP instance.
+ * @retval value of @ref COMP_ExtiLine
+ */
+#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
+ COMP_EXTI_LINE_COMP2)
+/**
+ * @}
+ */
+
+/** @defgroup COMP_IS_COMP_Definitions COMP Private macros to check input parameters
+ * @{
+ */
+
+#define IS_COMP_OUTPUTPOL(POL) (((POL) == COMP_OUTPUTPOL_NONINVERTED) || \
+ ((POL) == COMP_OUTPUTPOL_INVERTED))
+
+#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_HYSTERESIS_NONE) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_LOW) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_MEDIUM) || \
+ ((HYSTERESIS) == COMP_HYSTERESIS_HIGH))
+
+#define IS_COMP_MODE(MODE) (((MODE) == COMP_MODE_HIGHSPEED) || \
+ ((MODE) == COMP_MODE_MEDIUMSPEED) || \
+ ((MODE) == COMP_MODE_LOWPOWER) || \
+ ((MODE) == COMP_MODE_ULTRALOWPOWER))
+
+#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_VREFINT) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC1SWITCHCLOSED) || \
+ ((INPUT) == COMP_INVERTINGINPUT_DAC2) || \
+ ((INPUT) == COMP_INVERTINGINPUT_IO1))
+
+#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_IO1) || \
+ ((INPUT) == COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED))
+
+#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_NONE) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1BKIN) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM1OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2IC4) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3IC1) || \
+ ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR))
+
+#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \
+ ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE))
+
+#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
+ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
+ ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
+/**
+ * @}
+ */
+
+/** @defgroup COMP_Lock COMP Lock
+ * @{
+ */
+#define COMP_LOCK_DISABLE ((uint32_t)0x00000000)
+#define COMP_LOCK_ENABLE COMP_CSR_COMP1LOCK
+
+#define COMP_STATE_BIT_LOCK ((uint32_t)0x10)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_conf.h Mon Sep 28 10:45:10 2015 +0100
@@ -1,14 +1,14 @@
/**
******************************************************************************
- * @file stm32f0xx_hal_conf_template.h
+ * @file stm32f0xx_hal_conf.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief HAL configuration file.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -146,6 +146,10 @@
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@@ -32,13 +32,15 @@
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
+
+ -@- Negative value of IRQn_Type are not allowed.
[..]
*** How to configure Systick using CORTEX HAL driver ***
========================================================
[..]
- Setup SysTick Timer for time base
+ Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
is a CMSIS function that:
@@ -68,7 +70,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,7 +104,7 @@
* @{
*/
-/** @defgroup CORTEX CORTEX HAL module driver
+/** @defgroup CORTEX CORTEX
* @brief CORTEX CORTEX HAL module driver
* @{
*/
@@ -141,10 +143,10 @@
* @param IRQn: External interrupt number .
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
- * @param PreemptPriority: The pre-emption priority for the IRQn channel.
+ * @param PreemptPriority: The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 3.
* A lower priority value indicates a higher priority
- * @param SubPriority: The subpriority level for the IRQ channel.
+ * @param SubPriority: the subpriority level for the IRQ channel.
* with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0 based products.
* @retval None
@@ -160,26 +162,32 @@
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
- * @param IRQn External interrupt number
+ * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
- * @param IRQn External interrupt number
+ * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
@@ -228,7 +236,7 @@
/**
* @brief Gets the priority of an interrupt.
- * @param IRQn: External interrupt number
+ * @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
* @retval None
@@ -248,6 +256,9 @@
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
@@ -255,7 +266,7 @@
/**
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt).
- * @param IRQn External interrupt number
+ * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
@@ -263,19 +274,25 @@
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Clears the pending bit of an external interrupt.
- * @param IRQn External interrupt number
+ * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_cortex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,30 +50,22 @@
* @{
*/
-/** @addtogroup CORTEX CORTEX HAL module driver
+/** @addtogroup CORTEX CORTEX
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
-/** @defgroup CORTEX_Priority CORTEX Priority
- * @{
- */
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4)
-/**
- * @}
- */
-
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
- ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
/**
* @}
*/
@@ -147,6 +139,23 @@
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+/**
+ * @}
+ */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_crc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@@ -16,7 +16,7 @@
##### How to use this driver #####
===============================================================================
[..]
- (#) Enable CRC AHB clock using __CRC_CLK_ENABLE();
+ (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
(#) Initialize CRC calculator
(++)specify generating polynomial (IP default or non-default one)
(++)specify initialization value (IP default or non-default one)
@@ -33,7 +33,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -67,7 +67,7 @@
* @{
*/
-/** @defgroup CRC CRC HAL module driver
+/** @defgroup CRC CRC
* @brief CRC HAL module driver.
* @{
*/
@@ -130,6 +130,8 @@
if(hcrc->State == HAL_CRC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hcrc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_crc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @addtogroup CRC CRC HAL module driver
+/** @addtogroup CRC CRC
* @{
*/
@@ -111,8 +111,8 @@
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
Can be either
- CRC_OUTPUTDATA_INVERSION_DISABLED no CRC inversion, or
- CRC_OUTPUTDATA_INVERSION_ENABLED CRC 0x11223344 is converted into 0x22CC4488 */
+ CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, or
+ CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
}CRC_InitTypeDef;
@@ -239,6 +239,20 @@
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
/**
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @param __HANDLE__: CRC handle
+ * @param __VALUE__: 8-bit value to be stored in the ID register
+ * @retval None
+ */
+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
+
+/**
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
+ * @param __HANDLE__: CRC handle
+ * @retval 8-bit value of the ID register
+ */
+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
+/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_crc_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Extended CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CRC peripheral:
@@ -25,7 +25,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -59,7 +59,7 @@
* @{
*/
-/** @defgroup CRCEx CRCEx Extended HAL Module Driver
+/** @defgroup CRCEx CRCEx
* @brief CRC Extended HAL module driver
* @{
*/
@@ -160,8 +160,8 @@
* @param hcrc: CRC handle
* @param OutputReverseMode: Output Data inversion mode
* This parameter can be one of the following values:
- * @arg CRC_OUTPUTDATA_INVERSION_DISABLED: no CRC inversion (default value)
- * @arg CRC_OUTPUTDATA_INVERSION_ENABLED: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
+ * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
+ * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_crc_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_crc_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @addtogroup CRCEx CRCEx Extended HAL Module Driver
+/** @addtogroup CRCEx CRCEx
* @{
*/
@@ -78,11 +78,11 @@
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
* @{
*/
-#define CRC_OUTPUTDATA_INVERSION_DISABLED ((uint32_t)0x00000000)
-#define CRC_OUTPUTDATA_INVERSION_ENABLED ((uint32_t)CRC_CR_REV_OUT)
+#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000)
+#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
-#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLED) || \
- ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLED))
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+ ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dac.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -33,17 +33,17 @@
*** DAC Triggers ***
====================
[..]
- Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+ Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
[..]
Digital to Analog conversion can be triggered by:
- (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
- The used pin (GPIOx_Pin9) must be configured in input mode.
+ (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
+ The used pin (GPIOx_PIN_9) must be configured in input mode.
(#) Timers TRGO: TIM2, TIM3, TIM6, and TIM15
- (DAC_Trigger_T2_TRGO, DAC_Trigger_T3_TRGO...)
+ (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...)
- (#) Software using DAC_Trigger_Software
+ (#) Software using DAC_TRIGGER_SOFTWARE
*** DAC Buffer mode feature ***
===============================
@@ -52,10 +52,21 @@
reduce the output impedance, and to drive external loads directly
without having to add an external operational amplifier.
To enable, the output buffer use
- sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+ sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
[..]
(@) Refer to the device datasheet for more details about output
impedance value with and without output buffer.
+
+ *** GPIO configurations guidelines ***
+ =====================
+ [..]
+ When a DAC channel is used (ex channel1 on PA4) and the other is not
+ (ex channel1 on PA5 is configured in Analog and disabled).
+ Channel1 may disturb channel2 as coupling effect.
+ Note that there is no coupling on channel2 as soon as channel2 is turned on.
+ Coupling on adjacent channel could be avoided as follows:
+ when unused PA5 is configured as INPUT PULL-UP or DOWN.
+ PA5 is configured in ANALOG just before it is turned on.
*** DAC wave generation feature ***
===================================
@@ -72,16 +83,19 @@
(#) 12-bit left alignment using DAC_ALIGN_12B_L
(#) 12-bit right alignment using DAC_ALIGN_12B_R
- *** DAC data value to voltage correspondence ***
+ *** DAC data value to voltage correspondance ***
================================================
[..]
The analog output voltage on each DAC channel pin is determined
by the following equation:
+ [..]
DAC_OUTx = VREF+ * DOR / 4095
- with DOR is the Data Output Register
+ (+) with DOR is the Data Output Register
+ [..]
VEF+ is the input voltage reference (refer to the device datasheet)
+ [..]
e.g. To set DAC_OUT1 to 0.7V, use
- Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+ (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
*** DMA requests ***
=====================
@@ -96,8 +110,8 @@
(#) DAC channel2 : mapped on DMA1 channel4 which must be
already configured
- -@- For Dual mode and specific signal (Triangle and noise) generation please
- refer to Extension Features Driver description
+ (@) For Dual mode and specific signal (Triangle and noise) generation please
+ refer to Extended Features Driver description
STM32F0 devices with one channel (one converting capability) does not
support Dual mode and specific signal (Triangle and noise) generation.
@@ -108,25 +122,33 @@
registers using HAL_DAC_Init()
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
(+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
- (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
+ (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
*** Polling mode IO operation ***
=================================
[..]
(+) Start the DAC peripheral using HAL_DAC_Start()
- (+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function.
+ (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
(+) Stop the DAC peripheral using HAL_DAC_Stop()
*** DMA mode IO operation ***
==============================
[..]
(+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
- of data to be transfered at each end of conversion
- (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
+ of data to be transferred at each end of conversion
+ (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
function is executed and user can add his own code by customization of function pointer
- HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
+ HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
(+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
+ (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
+ HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
+ add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
*** DAC HAL driver macros list ***
@@ -146,7 +168,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -177,17 +199,17 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
#ifdef HAL_DAC_MODULE_ENABLED
#if defined(STM32F051x8) || defined(STM32F058xx) || \
defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
defined(STM32F091xC) || defined (STM32F098xx)
-/** @addtogroup STM32F0xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DAC DAC HAL module driver
+/** @defgroup DAC DAC
* @brief DAC driver modules
* @{
*/
@@ -195,10 +217,23 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
+/** @defgroup DAC_Private_Macros DAC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DAC_Private_Functions DAC Private Functions
+ * @{
+ */
+/**
+ * @}
+ */
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions -------------------------------------------------------*/
/** @defgroup DAC_Exported_Functions DAC Exported Functions
* @{
@@ -220,8 +255,8 @@
*/
/**
- * @brief Initializes the DAC peripheral according to the specified parameters
- * in the DAC_InitStruct.
+ * @brief Initialize the DAC peripheral according to the specified parameters
+ * in the DAC_InitStruct and initialize the associated handle.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
@@ -238,6 +273,9 @@
if(hdac->State == HAL_DAC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hdac->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
}
@@ -256,7 +294,7 @@
}
/**
- * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ * @brief Deinitialize the DAC peripheral registers to their default reset values.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
@@ -292,27 +330,27 @@
}
/**
- * @brief Initializes the DAC MSP.
+ * @brief Initialize the DAC MSP.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_MspInit could be implemented in the user file
*/
}
/**
- * @brief DeInitializes the DAC MSP.
+ * @brief DeInitialize the DAC MSP.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_MspDeInit could be implemented in the user file
*/
}
@@ -333,7 +371,7 @@
(+) Stop conversion.
(+) Start conversion and enable DMA transfer.
(+) Stop conversion and disable DMA transfer.
- (+) Get result of conversion.
+ (+) Set the specified data holding register value for DAC channel.
@endverbatim
* @{
@@ -429,20 +467,35 @@
/* Disable the selected DAC channel DMA request */
hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
- /* Disable the Peripharal */
+ /* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
- /* Disable the DMA Channel */
+ /* Disable the DMA channel */
/* Channel1 is used */
if (Channel == DAC_CHANNEL_1)
{
+ /* Disable the DMA channel */
status = HAL_DMA_Abort(hdac->DMA_Handle1);
+
+ /* Disable the DAC DMA underrun interrupt */
+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
}
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined (STM32F098xx)
+ /* Does not apply to STM32F051x8 & STM32F058xx */
+
else /* Channel2 is used for */
{
+ /* Disable the DMA channel */
status = HAL_DMA_Abort(hdac->DMA_Handle2);
+
+ /* Disable the DAC DMA underrun interrupt */
+ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
}
-
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
/* Check if DMA Channel effectively disabled */
if (status != HAL_OK)
{
@@ -460,94 +513,15 @@
}
/**
- * @brief Conversion complete callback in non blocking mode for Channel1
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_ConvCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @brief Error DAC callback for Channel1.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_ErrorCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief DMA underrun DAC callback for channel1.
+ * @brief Handles DAC interrupt request
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
-__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
- */
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral Control functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Configure channels.
- (+) Set the specified data holding register value for DAC channel.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @param sConfig: DAC configuration structure.
- * @param Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_CHANNEL_1: DAC Channel1 selected
- * @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+__weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
{
/* Note : This function is defined into this file for library reference. */
/* Function content is located into file stm32f0xx_hal_dac_ex.c */
-
- /* Return error status as not implemented here */
- return HAL_ERROR;
}
/**
@@ -578,11 +552,11 @@
tmp = (uint32_t)hdac->Instance;
if(Channel == DAC_CHANNEL_1)
{
- tmp += __HAL_DHR12R1_ALIGNEMENT(Alignment);
+ tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
}
else
{
- tmp += __HAL_DHR12R2_ALIGNEMENT(Alignment);
+ tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
}
/* Set the DAC channel1 selected data holding register */
@@ -593,6 +567,77 @@
}
/**
+ * @brief Conversion complete callback in non blocking mode for Channel1
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error DAC callback for Channel1.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DMA underrun DAC callback for channel1.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @retval None
+ */
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels.
+ (+) Get result of conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
* @brief Returns the last data output value of the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
@@ -612,6 +657,26 @@
}
/**
+ * @brief Configures the selected DAC channel.
+ * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * the configuration information for the specified DAC.
+ * @param sConfig: DAC configuration structure.
+ * @param Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_CHANNEL_1: DAC Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC Channel2 selected
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+ /* Note : This function is defined into this file for library reference. */
+ /* Function content is located into file stm32f0xx_hal_dac_ex.c */
+
+ /* Return error status as not implemented here */
+ return HAL_ERROR;
+}
+
+/**
* @}
*/
@@ -632,14 +697,14 @@
*/
/**
- * @brief return the DAC state
+ * @brief return the DAC handle state
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL state
*/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
{
- /* Return DAC state */
+ /* Return DAC handle state */
return hdac->State;
}
@@ -656,18 +721,6 @@
}
/**
- * @brief Handles DAC interrupt request
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
- * @retval None
- */
-__weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
-{
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f0xx_hal_dac_ex.c */
-}
-
-/**
* @}
*/
@@ -679,15 +732,15 @@
/**
* @}
*/
-
-/**
- * @}
- */
-
#endif /* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
#endif /* HAL_DAC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_dac.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,6 +43,10 @@
extern "C" {
#endif
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
#if defined(STM32F051x8) || defined(STM32F058xx) || \
defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
defined(STM32F091xC) || defined(STM32F098xx)
@@ -50,10 +54,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
-/** @addtogroup STM32F0xx_HAL_Driver
- * @{
- */
-
/** @addtogroup DAC
* @{
*/
@@ -123,8 +123,8 @@
* @{
*/
#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */
#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
/**
* @}
@@ -136,30 +136,17 @@
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
- ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
/**
* @}
*/
-/** @defgroup DAC_data_alignement DAC data alignement
+/** @defgroup DAC_data_alignment DAC data alignment
* @{
*/
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
- ((ALIGN) == DAC_ALIGN_12B_L) || \
- ((ALIGN) == DAC_ALIGN_8B_R))
-/**
- * @}
- */
-
-/** @defgroup DAC_data DAC data
- * @{
- */
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
@@ -214,27 +201,12 @@
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
-/** @brief Set DHR12R1 alignment
- * @param __ALIGNEMENT__: specifies the DAC alignement
- * @retval None
- */
-#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
-
-/** @brief Set DHR12R2 alignment
- * @param __ALIGNEMENT__: specifies the DAC alignement
- * @retval None
- */
-#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
-
-/** @brief Set DHR12RD alignment
- * @param __ALIGNEMENT__: specifies the DAC alignement
- * @retval None
- */
-#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
-
/** @brief Enable the DAC interrupt
* @param __HANDLE__: specifies the DAC handle
* @param __INTERRUPT__: specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
@@ -242,20 +214,36 @@
/** @brief Disable the DAC interrupt
* @param __HANDLE__: specifies the DAC handle
* @param __INTERRUPT__: specifies the DAC interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-/** @brief Get the selected DAC's flag status.
+/** @brief Check whether the specified DAC interrupt source is enabled or not
+ * @param __HANDLE__: DAC handle
+ * @param __INTERRUPT__: DAC interrupt source to check
+ * This parameter can be any combination of the following values:
+ * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+ * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Get the selected DAC's flag status
* @param __HANDLE__: specifies the DAC handle.
- * @param __FLAG__: specifies the FLAG.
+ * @param __FLAG__: specifies the DAC flag to get.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-/** @brief Clear the DAC's flag.
+/** @brief Clear the DAC's flag
* @param __HANDLE__: specifies the DAC handle.
- * @param __FLAG__: specifies the FLAG.
+ * @param __FLAG__: specifies the DAC flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
@@ -264,6 +252,58 @@
* @}
*/
+/* Private macro -------------------------------------------------------------*/
+
+/** @addtogroup DAC_Private_Macros
+ * @{
+ */
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+ ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F051x8) || defined(STM32F058xx)
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1))
+
+#endif /* STM32F051x8 || STM32F058xx */
+
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+ ((ALIGN) == DAC_ALIGN_12B_L) || \
+ ((ALIGN) == DAC_ALIGN_8B_R))
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+
+/** @brief Set DHR12R1 alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
+
+/** @brief Set DHR12R2 alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
+
+/** @brief Set DHR12RD alignment
+ * @param __ALIGNMENT__: specifies the DAC alignment
+ * @retval None
+ */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
+
+/**
+ * @}
+ */
/* Include DAC HAL Extension module */
#include "stm32f0xx_hal_dac_ex.h"
@@ -296,6 +336,10 @@
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
@@ -308,9 +352,9 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
/**
* @}
*/
@@ -320,7 +364,6 @@
*/
/* Peripheral State and Error functions ***************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
/**
@@ -335,14 +378,14 @@
* @}
*/
+#endif /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
/**
* @}
*/
-#endif /* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
-
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,12 +2,11 @@
******************************************************************************
* @file stm32f0xx_hal_dac_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief DAC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of DAC extension peripheral:
- * + Extended features functions
+ * This file provides firmware functions to manage the extended
+ * functionalities of the DAC peripheral.
*
*
@verbatim
@@ -15,7 +14,7 @@
##### How to use this driver #####
==============================================================================
[..]
- (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
+ (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
@@ -25,7 +24,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -56,28 +55,21 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
#ifdef HAL_DAC_MODULE_ENABLED
+/** @addtogroup DAC
+ * @{
+ */
+
#if defined(STM32F051x8) || defined(STM32F058xx) || \
defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
defined(STM32F091xC) || defined(STM32F098xx)
-/** @addtogroup STM32F0xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DACEx DACEx Extended HAL module driver
- * @brief DACEx driver module
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DACEx_Private_Functions DACEx Private Functions
+/** @addtogroup DAC_Private_Functions
* @{
*/
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
@@ -87,32 +79,37 @@
* @}
*/
-/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+#endif /* STM32F051x8 STM32F058xx */
+ /* STM32F071xB STM32F072xB STM32F078xx */
+ /* STM32F091xC STM32F098xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @addtogroup DAC_Private_Functions
* @{
*/
-/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- *
-@verbatim
- ==============================================================================
- ##### Extended features functions #####
- ==============================================================================
- [..] This section provides functions allowing to:
- (+) Start conversion.
- (+) Stop conversion.
- (+) Start conversion and enable DMA transfer.
- (+) Stop conversion and disable DMA transfer.
- (+) Get result of conversion.
- (+) Get result of dual mode conversion.
-
-@endverbatim
+/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
+/* are set by HAL_DAC_Start_DMA */
+
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+#endif /* STM32F071xB STM32F072xB STM32F078xx */
+ /* STM32F091xC STM32F098xx */
+
+/** @addtogroup DAC_Exported_Functions
* @{
*/
-#endif /* STM32F051x8 STM32F058xx */
- /* STM32F071xB STM32F072xB STM32F078xx */
- /* STM32F091xC STM32F098xx */
+/** @addtogroup DAC_Exported_Functions_Group3
+ * @{
+ */
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
defined(STM32F091xC) || defined(STM32F098xx)
@@ -145,7 +142,7 @@
hdac->State = HAL_DAC_STATE_BUSY;
/* Get the DAC CR value */
- tmpreg1 = DAC->CR;
+ tmpreg1 = hdac->Instance->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
/* Configure for the selected DAC channel: buffer output, trigger */
@@ -155,9 +152,7 @@
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC CR */
- DAC->CR = tmpreg1;
- /* Disable wave generation */
- DAC->CR &= ~(DAC_CR_WAVE1 << Channel);
+ hdac->Instance->CR = tmpreg1;
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -201,9 +196,8 @@
hdac->State = HAL_DAC_STATE_BUSY;
/* Get the DAC CR value */
- tmpreg1 = DAC->CR;
+ tmpreg1 = hdac->Instance->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
- // tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
tmpreg1 &= ~(((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
/* Configure for the selected DAC channel: buffer output, trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
@@ -212,9 +206,7 @@
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC CR */
- DAC->CR = tmpreg1;
- /* Disable wave generation */
- // DAC->CR &= ~(DAC_CR_WAVE1 << Channel);
+ hdac->Instance->CR = tmpreg1;
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -287,6 +279,14 @@
#endif /* STM32F051x8 STM32F058xx */
+/**
+ * @}
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group2
+ * @{
+ */
+
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
defined(STM32F091xC) || defined(STM32F098xx)
@@ -302,8 +302,6 @@
*/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
- uint32_t tmp1 = 0, tmp2 = 0;
-
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -318,24 +316,20 @@
if(Channel == DAC_CHANNEL_1)
{
- tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
- tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
/* Check if software trigger enabled */
- if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
+ if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
{
/* Enable the selected DAC software conversion */
- hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
+ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
}
}
else
{
- tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
- tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
/* Check if software trigger enabled */
- if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
+ if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
{
/* Enable the selected DAC software conversion*/
- hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
+ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
}
}
@@ -392,7 +386,7 @@
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
/* Enable the selected DAC channel1 DMA request */
- hdac->Instance->CR |= DAC_CR_DMAEN1;
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
/* Case of use of channel 1 */
switch(Alignment)
@@ -425,7 +419,7 @@
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
/* Enable the selected DAC channel2 DMA request */
- hdac->Instance->CR |= DAC_CR_DMAEN2;
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
/* Case of use of channel 2 */
switch(Alignment)
@@ -484,8 +478,6 @@
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
- uint32_t tmp1 = 0, tmp2 = 0;
-
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -500,13 +492,11 @@
if(Channel == DAC_CHANNEL_1)
{
- tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
- tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
/* Check if software trigger enabled */
- if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
+ if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
{
/* Enable the selected DAC software conversion */
- hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
+ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
}
}
@@ -560,7 +550,7 @@
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
/* Enable the selected DAC channel1 DMA request */
- hdac->Instance->CR |= DAC_CR_DMAEN1;
+ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
/* Case of use of channel 1 */
switch(Alignment)
@@ -618,40 +608,47 @@
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
{
- /* Check Overrun flag */
- if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
- {
- /* Change DAC state to error state */
- hdac->State = HAL_DAC_STATE_ERROR;
+ if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
+ {
+ /* Check underrun channel 1 flag */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
- /* Set DAC error code to chanel1 DMA underrun error */
- hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
+ /* Set DAC error code to channel1 DMA underrun error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
- /* Clear the underrun flag */
- __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
- /* Disable the selected DAC channel1 DMA request */
- hdac->Instance->CR &= ~DAC_CR_DMAEN1;
+ /* Disable the selected DAC channel1 DMA request */
+ hdac->Instance->CR &= ~DAC_CR_DMAEN1;
- /* Error callback */
- HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+ /* Error callback */
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+ }
}
- else
+ if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
{
- /* Change DAC state to error state */
- hdac->State = HAL_DAC_STATE_ERROR;
+ /* Check underrun channel 2 flag */
+ if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
- /* Set DAC error code to channel2 DMA underrun error */
- hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
+ /* Set DAC error code to channel2 DMA underrun error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
- /* Clear the underrun flag */
- __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
- /* Disable the selected DAC channel1 DMA request */
- hdac->Instance->CR &= ~DAC_CR_DMAEN2;
+ /* Disable the selected DAC channel1 DMA request */
+ hdac->Instance->CR &= ~DAC_CR_DMAEN2;
- /* Error callback */
- HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+ /* Error callback */
+ HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+ }
}
}
@@ -669,28 +666,205 @@
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
{
+ if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
+ {
/* Check Overrun flag */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
- {
- /* Change DAC state to error state */
- hdac->State = HAL_DAC_STATE_ERROR;
+ {
+ /* Change DAC state to error state */
+ hdac->State = HAL_DAC_STATE_ERROR;
- /* Set DAC error code to chanel1 DMA underrun error */
- hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
+ /* Set DAC error code to chanel1 DMA underrun error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
- /* Clear the underrun flag */
- __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
+ /* Clear the underrun flag */
+ __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
- /* Disable the selected DAC channel1 DMA request */
- hdac->Instance->CR &= ~DAC_CR_DMAEN1;
+ /* Disable the selected DAC channel1 DMA request */
+ hdac->Instance->CR &= ~DAC_CR_DMAEN1;
- /* Error callback */
- HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+ /* Error callback */
+ HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+ }
}
}
#endif /* STM32F051x8 STM32F058xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined(STM32F051x8) || defined(STM32F058xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_DAC_ConvCpltCallbackCh1(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+ HAL_DAC_ErrorCallbackCh1(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+/**
+ * @}
+ */
+#endif /* STM32F051x8 STM32F058xx */
+ /* STM32F071xB STM32F072xB STM32F078xx */
+ /* STM32F091xC STM32F098xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @addtogroup DAC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA conversion complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_DACEx_ConvCpltCallbackCh2(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ /* Conversion complete callback */
+ HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
+}
+
+/**
+ * @brief DMA error callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
+{
+ DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Set DAC error code to DMA error */
+ hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+ HAL_DACEx_ErrorCallbackCh2(hdac);
+
+ hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+ * @}
+ */
+
+#endif /* STM32F071xB STM32F072xB STM32F078xx */
+ /* STM32F091xC STM32F098xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup DACEx DACEx
+ * @brief DACEx driver module
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup DACEx_Private_Macros DACEx Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+ * @{
+ */
+
+/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended features functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion.
+ (+) Stop conversion.
+ (+) Start conversion and enable DMA transfer.
+ (+) Stop conversion and disable DMA transfer.
+ (+) Get result of conversion.
+ (+) Get result of dual mode conversion.
+
+@endverbatim
+ * @{
+ */
+
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
defined(STM32F091xC) || defined(STM32F098xx)
@@ -775,7 +949,7 @@
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the selected wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_WAVE_TRIANGLE | Amplitude) << Channel);
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -823,7 +997,7 @@
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the selected wave generation for the selected DAC channel */
- MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_WAVE_NOISE | Amplitude) << Channel);
+ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
@@ -838,10 +1012,27 @@
#endif /* STM32F071xB STM32F072xB STM32F078xx */
/* STM32F091xC STM32F098xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#if defined(STM32F051x8) || defined(STM32F058xx) || \
defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
defined(STM32F091xC) || defined(STM32F098xx)
+/** @addtogroup DACEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DACEx_Exported_Functions_Group1
+ * @brief Extended features functions
+ * @{
+ */
+
/**
* @brief Set the specified data holding register value for dual DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
@@ -877,7 +1068,7 @@
}
tmp = (uint32_t)hdac->Instance;
- tmp += __HAL_DHR12RD_ALIGNEMENT(Alignment);
+ tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
@@ -894,58 +1085,6 @@
* @}
*/
-/** @addtogroup DACEx_Private_Functions
- * @{
- */
-
-/**
- * @brief DMA conversion complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_DAC_ConvCpltCallbackCh1(hdac);
-
- hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
- * @brief DMA half transfer complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Conversion complete callback */
- HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
-}
-
-/**
- * @brief DMA error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Set DAC error code to DMA error */
- hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
- HAL_DAC_ErrorCallbackCh1(hdac);
-
- hdac->State= HAL_DAC_STATE_READY;
-}
-/**
- * @}
- */
#endif /* STM32F051x8 STM32F058xx */
/* STM32F071xB STM32F072xB STM32F078xx */
/* STM32F091xC STM32F098xx */
@@ -961,6 +1100,7 @@
* @brief Extended features functions
* @{
*/
+
/**
* @brief Conversion complete callback in non blocking mode for Channel2
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
@@ -1014,60 +1154,6 @@
}
/**
- * @brief DMA conversion complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_DACEx_ConvCpltCallbackCh2(hdac);
-
- hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
- * @brief DMA half transfer complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- /* Conversion complete callback */
- HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
-}
-
-/**
- * @brief DMA error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
-{
- DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Set DAC error code to DMA error */
- hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-
- HAL_DACEx_ErrorCallbackCh2(hdac);
-
- hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
* @}
*/
@@ -1078,6 +1164,14 @@
#endif /* STM32F071xB STM32F072xB STM32F078xx */
/* STM32F091xC STM32F098xx */
+/**
+ * @}
+ */
+
#endif /* HAL_DAC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dac_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_dac_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -43,6 +43,10 @@
extern "C" {
#endif
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
#if defined(STM32F051x8) || defined(STM32F058xx) || \
defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
defined(STM32F091xC) || defined(STM32F098xx)
@@ -50,37 +54,17 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
-/** @addtogroup STM32F0xx_HAL_Driver
- * @{
- */
-
/** @addtogroup DACEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
-/**
- * @brief HAL State structures definition
- */
+/* Exported constants --------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
* @{
*/
-/** @defgroup DACEx_wave_generation DACEx wave generation
- * @{
- */
-#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000)
-#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
-
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \
- ((WAVE) == DAC_WAVEGENERATION_NOISE) || \
- ((WAVE) == DAC_WAVEGENERATION_TRIANGLE))
-/**
- * @}
- */
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
* @{
@@ -110,6 +94,133 @@
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+
+/** @defgroup DACEx_Exported_Macros DACEx Exported Macros
+ * @{
+ */
+
+/** @defgroup DAC_trigger_selection DAC trigger selection
+ * @{
+ */
+#if defined(STM32F051x8) || defined(STM32F058xx)
+
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#endif /* STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection DAC Channel selection
+ * @{
+ */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
+#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F051x8) || defined(STM32F058xx)
+
+#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
+
+#endif /* STM32F051x8 || STM32F058xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @addtogroup DACEx_Private_Macros
+ * @{
+ */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F051x8) || defined(STM32F058xx)
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+#endif /* STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+ ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
@@ -134,19 +245,42 @@
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+
/**
* @}
*/
-/** @defgroup DACEx_wave_generationbis DACEx wave generation bis
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DACEx_Exported_Functions
* @{
*/
-#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+
+/** @addtogroup DACEx_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \
- ((WAVE) == DAC_WAVE_TRIANGLE))
-
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+
+/**
+ * @}
+ */
+
+/** @addtogroup DACEx_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+
/**
* @}
*/
@@ -155,143 +289,22 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Macros DACEx Exported Macros
- * @{
- */
-
-/** @defgroup DAC_trigger_selection DAC trigger selection
- * @{
- */
-#if defined(STM32F051x8) || defined(STM32F058xx)
-
-#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-#endif /* STM32F051x8 || STM32F058xx */
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
-
-#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
/**
* @}
*/
-/** @defgroup DAC_Channel_selection DAC Channel selection
- * @{
- */
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
-
-#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
-#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2))
-
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
-
-#if defined(STM32F051x8) || defined(STM32F058xx)
-
-#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1))
-
-#endif /* STM32F051x8 || STM32F058xx */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/* Extension features functions ***********************************************/
-
-/** @addtogroup DACEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup DACEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
- * @{
- */
-
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
-
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
- /**
- * @}
- */
-#endif /* */
+#endif /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
/**
* @}
*/
-/**
- * @}
- */
-
#ifdef __cplusplus
}
-#endif /* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
-
+#endif
+
#endif /*__STM32F0xx_HAL_DAC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_def.h Mon Sep 28 10:45:10 2015 +0100 @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32f0xx_hal_def.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -46,6 +46,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx.h" +#include "stm32_hal_legacy.h" +#include <stdio.h> /* Exported types ------------------------------------------------------------*/ @@ -70,9 +72,6 @@ } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ -#ifndef NULL - #define NULL 0 -#endif #define HAL_MAX_DELAY 0xFFFFFFFF
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_dma.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -73,7 +73,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -107,12 +107,13 @@
* @{
*/
+#ifdef HAL_DMA_MODULE_ENABLED
+
/** @defgroup DMA DMA
* @brief DMA HAL module driver
* @{
*/
-#ifdef HAL_DMA_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -125,6 +126,13 @@
*/
/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup DMA_Private_Functions DMA Private Functions
@@ -141,7 +149,7 @@
* @{
*/
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
@@ -186,6 +194,12 @@
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
assert_param(IS_DMA_MODE(hdma->Init.Mode));
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+ if(hdma->State == HAL_DMA_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hdma->Lock = HAL_UNLOCKED;
+ }
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
@@ -259,7 +273,7 @@
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
- /* Initialise the error code */
+ /* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state */
@@ -386,7 +400,7 @@
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
- /* Get timeout */
+ /* Get tick */
tickstart = HAL_GetTick();
/* Check if the DMA Channel is effectively disabled */
@@ -441,7 +455,7 @@
temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
}
- /* Get timeout */
+ /* Get tick */
tickstart = HAL_GetTick();
while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
@@ -649,7 +663,7 @@
* @}
*/
-/** @addtogroup DMA_Private_Functions DMA Private Functions
+/** @addtogroup DMA_Private_Functions
* @{
*/
@@ -691,10 +705,10 @@
* @}
*/
-#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
+#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_dma.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,6 +55,7 @@
*/
/* Exported types ------------------------------------------------------------*/
+
/** @defgroup DMA_Exported_Types DMA Exported Types
* @{
*/
@@ -87,7 +88,6 @@
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_Priority_level */
-
} DMA_InitTypeDef;
/**
@@ -106,12 +106,11 @@
typedef enum
{
HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
- HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
+ HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
- HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
-
+ HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
}HAL_DMA_StateTypeDef;
/**
@@ -121,9 +120,7 @@
{
HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
-
-}HAL_DMA_LevelCompleteTypeDef;
-
+}HAL_DMA_LevelCompleteTypeDef;
/**
* @brief DMA handle Structure definition
@@ -136,7 +133,7 @@
HAL_LockTypeDef Lock; /*!< DMA locking object */
- HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
@@ -147,13 +144,14 @@
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
-
} DMA_HandleTypeDef;
+
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup DMA_Exported_Constants DMA Exported Constants
* @{
*/
@@ -175,29 +173,15 @@
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
- ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
- ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
/**
* @}
*/
-
-/** @defgroup DMA_Data_buffer_size DMA Data buffer size
- * @{
- */
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-/**
- * @}
- */
-
+
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
- ((STATE) == DMA_PINC_DISABLE))
/**
* @}
*/
@@ -207,9 +191,6 @@
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
- ((STATE) == DMA_MINC_DISABLE))
/**
* @}
*/
@@ -220,25 +201,16 @@
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
- ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_PDATAALIGN_WORD))
/**
* @}
*/
-
/** @defgroup DMA_Memory_data_size DMA Memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
- ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_MDATAALIGN_WORD ))
/**
* @}
*/
@@ -248,9 +220,6 @@
*/
#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
- ((MODE) == DMA_CIRCULAR))
/**
* @}
*/
@@ -262,11 +231,6 @@
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
- ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
- ((PRIORITY) == DMA_PRIORITY_HIGH) || \
- ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/**
* @}
*/
@@ -275,11 +239,9 @@
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{
*/
-
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
-
/**
* @}
*/
@@ -317,16 +279,78 @@
#define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */
#define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_CFGR1_DMA_RMP)
+/** @defgroup HAL_DMA_remapping HAL DMA remapping
+ * Elements values convention: 0xYYYYYYYY
+ * - YYYYYYYY : Position in the SYSCFG register CFGR1
+ * @{
+ */
+#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
+ 0: No remap (ADC DMA requests mapped on DMA channel 1
+ 1: Remap (ADC DMA requests mapped on DMA channel 2 */
+#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
+ 0: No remap (USART1_TX DMA request mapped on DMA channel 2
+ 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
+#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
+ 0: No remap (USART1_RX DMA request mapped on DMA channel 3
+ 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
+#define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
+ 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
+ 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
+#define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
+ 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
+ 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
+#if defined (STM32F070xB)
+#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only.
+ 0: Disabled, need to remap before use
+ 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
+
+#endif
+
+#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
+#define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
+ 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
+ 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
+#define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
+ 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
+ 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
+#define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
+ 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
+#define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
+ 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
+#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
+ 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
+#define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
+ 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
+#define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
+ 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
+#define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
+ 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
+#define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
+ 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
+ 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
+#endif
/**
* @}
*/
+#endif /* SYSCFG_CFGR1_DMA_RMP */
/**
* @}
*/
-/* Exported macros -----------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{
*/
@@ -340,14 +364,14 @@
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__: DMA handle
- * @retval None.
+ * @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__: DMA handle
- * @retval None.
+ * @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
@@ -379,7 +403,7 @@
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
/**
- * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
+ * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
* @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
@@ -390,6 +414,18 @@
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#if defined(SYSCFG_CFGR1_DMA_RMP)
+/** @brief DMA remapping enable/disable macros
+ * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
+ */
+#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
+ SYSCFG->CFGR1 |= (__DMA_REMAP__); \
+ }while(0)
+#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
+ SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
+ }while(0)
+#endif /* SYSCFG_CFGR1_DMA_RMP */
+
/**
* @}
*/
@@ -398,11 +434,11 @@
#include "stm32f0xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_Exported_Functions DMA Exported Functions
+/** @addtogroup DMA_Exported_Functions
* @{
*/
+
/** @addtogroup DMA_Exported_Functions_Group1
- * @brief Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
@@ -413,10 +449,9 @@
*/
/** @addtogroup DMA_Exported_Functions_Group2
- * @brief I/O operation functions
* @{
*/
-/* IO operation functions *****************************************************/
+/* Input and Output operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
@@ -426,16 +461,86 @@
* @}
*/
-/* Peripheral State and Error functions ***************************************/
/** @addtogroup DMA_Exported_Functions_Group3
- * @brief Peripheral State functions
* @{
*/
+/* Peripheral State and Error functions ***************************************/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/**
* @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Macros
+ * @{
*/
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+ ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
+ ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
+ ((MODE) == DMA_CIRCULAR))
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+#if defined(SYSCFG_CFGR1_DMA_RMP)
+
+#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
+#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
+ ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
+ ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
+ ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
+ ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \
+ ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \
+ ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \
+ ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \
+ ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \
+ ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
+ ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \
+ ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \
+ ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \
+ ((RMP) == DMA_REMAP_TIM3_DMA_CH6))
+#elif defined (STM32F070xB)
+#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
+ ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
+ ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
+ ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
+ ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
+ ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
+#else
+#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
+ ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
+ ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
+ ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
+ ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
+#endif
+
+#endif /* SYSCFG_CFGR1_DMA_RMP */
+
+
+/**
+ * @}
+ */
/**
* @}
@@ -443,10 +548,6 @@
/**
* @}
- */
-
-/**
- * @}
*/
#ifdef __cplusplus
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_dma_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of DMA HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,9 +50,10 @@
* @{
*/
-/** @addtogroup DMAEx
+/** @defgroup DMAEx DMAEx
+ * @brief DMA HAL module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_flash.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -14,11 +14,11 @@
@verbatim
==============================================================================
##### FLASH peripheral features #####
- ==============================================================================
+ ==============================================================================
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
to the Flash memory. It implements the erase and program Flash memory operations
and the read and write protection mechanisms.
-
+
[..] The Flash memory interface accelerates code execution with a system of instruction
prefetch.
@@ -28,12 +28,13 @@
(+) Read / write protections
(+) Prefetch on I-Code
(+) Option Bytes programming
-
+
+
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions and macros to configure and program the FLASH
- memory of all STM32F0xx devices. These functions are split in 3 groups:
+ memory of all STM32F0xx devices.
(#) FLASH Memory I/O Programming functions: this group includes all needed
functions to erase and program the main memory:
@@ -41,15 +42,17 @@
(++) Erase function: Erase page, erase all pages
(++) Program functions: half word, word and doubleword
- (#) Option Bytes Programming functions: this group includes all needed
+ (#) FLASH Option Bytes Programming functions: this group includes all needed
functions to manage the Option Bytes:
(++) Lock and Unlock the Option Bytes
- (++) Erase Option Bytes
(++) Set/Reset the write protection
(++) Set the Read protection Level
(++) Program the user Option Bytes
+ (++) Launch the Option Bytes loader
+ (++) Erase Option Bytes
(++) Program the data Option Bytes
- (++) Launch the Option Bytes loader
+ (++) Get the Write protection.
+ (++) Get the user option bytes.
(#) Interrupts and flags management functions : this group
includes all needed functions to:
@@ -69,7 +72,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -103,23 +106,23 @@
* @{
*/
-/** @defgroup FLASH FLASH HAL module driver
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/** @defgroup FLASH FLASH
* @brief FLASH HAL module driver
* @{
*/
-#ifdef HAL_FLASH_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Defines FLASH Private Define
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
* @{
*/
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macro ---------------------------- ---------------------------------*/
/** @defgroup FLASH_Private_Macros FLASH Private Macros
* @{
*/
@@ -130,27 +133,20 @@
/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
- * @{
- */
+ * @{
+ */
/* Variables used for Erase pages under interruption*/
FLASH_ProcessTypeDef pFlash;
/**
* @}
*/
-
+
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASH_Private_Functions FLASH Private Functions
- * @{
- */
-/* Erase operations */
-void FLASH_PageErase(uint32_t PageAddress);
-
-/* Program operations */
-static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
-
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-static void FLASH_SetErrorCode(void);
-
+ * @{
+ */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
+static void FLASH_SetErrorCode(void);
/**
* @}
*/
@@ -160,17 +156,10 @@
* @{
*/
-/** @defgroup FLASH_Exported_Functions_Group1 I/O operation functions
- * @brief Data transfers functions
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+ * @brief Programming operation functions
*
@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the FLASH
- program operations (write/erase).
-
@endverbatim
* @{
*/
@@ -203,20 +192,20 @@
__HAL_LOCK(&pFlash);
/* Check the parameters */
- assert_param(IS_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
- if(TypeProgram == TYPEPROGRAM_HALFWORD)
+ if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
/* Program halfword (16-bit) at a specified address. */
nbiterations = 1;
}
- else if(TypeProgram == TYPEPROGRAM_WORD)
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
/* Program word (32-bit = 2*16-bit) at a specified address. */
nbiterations = 2;
@@ -231,12 +220,11 @@
{
FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index)));
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- /* If the program operation is completed, disable the PG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
-
+ /* If the program operation is completed, disable the PG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
/* In case of error, stop programation procedure */
if (status != HAL_OK)
{
@@ -274,22 +262,22 @@
__HAL_LOCK(&pFlash);
/* Check the parameters */
- assert_param(IS_TYPEPROGRAM(TypeProgram));
+ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
/* Enable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
pFlash.Address = Address;
pFlash.Data = Data;
- if(TypeProgram == TYPEPROGRAM_HALFWORD)
+ if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
/*Program halfword (16-bit) at a specified address.*/
pFlash.DataRemaining = 1;
}
- else if(TypeProgram == TYPEPROGRAM_WORD)
+ else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
/*Program word (32-bit : 2*16-bit) at a specified address.*/
@@ -315,7 +303,7 @@
void HAL_FLASH_IRQHandler(void)
{
uint32_t addresstmp = 0;
-
+
/* Check FLASH operation error flags */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
{
@@ -339,92 +327,93 @@
/* Process can continue only if no error detected */
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
{
- if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
- {
- /* Nb of pages to erased can be decreased */
- pFlash.DataRemaining--;
+ if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
+ {
+ /* Nb of pages to erased can be decreased */
+ pFlash.DataRemaining--;
- /* Indicate user which page address has been erased*/
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ /* Indicate user which page address has been erased*/
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
- /* Check if there are still pages to erase*/
- if(pFlash.DataRemaining != 0)
- {
- /* Increment page address to next page */
- pFlash.Address += FLASH_PAGE_SIZE;
- addresstmp = pFlash.Address;
+ /* Check if there are still pages to erase*/
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Increment page address to next page */
+ pFlash.Address += FLASH_PAGE_SIZE;
+ addresstmp = pFlash.Address;
/* Operation is completed, disable the PER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
- FLASH_PageErase(addresstmp);
- }
- else
- {
- /*No more pages to Erase*/
+ FLASH_PageErase(addresstmp);
+ }
+ else
+ {
+ /*No more pages to Erase*/
- /*Reset Address and stop Erase pages procedure*/
- pFlash.Address = 0xFFFFFFFF;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ /*Reset Address and stop Erase pages procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
}
- }
- else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
- {
+ else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+ {
/* Operation is completed, disable the MER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
- /*MassErase ended. Return the selected bank*/
- /* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(0);
+ /* MassErase ended. Return the selected bank*/
+ /* FLASH EOP interrupt user callback */
+ HAL_FLASH_EndOfOperationCallback(0);
- /* Stop Mass Erase procedure*/
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- }
- else
- {
- /* Nb of 16-bit data to program can be decreased */
- pFlash.DataRemaining--;
-
- /* Check if there are still 16-bit data to program */
- if(pFlash.DataRemaining != 0)
+ /* Stop Mass Erase procedure*/
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+ }
+ else
{
- /* Increment address to 16-bit */
- pFlash.Address += 2;
- addresstmp = pFlash.Address;
-
- /* Shift to have next 16-bit data */
- pFlash.Data = (pFlash.Data >> 16);
-
+ /* Nb of 16-bit data to program can be decreased */
+ pFlash.DataRemaining--;
+
+ /* Check if there are still 16-bit data to program */
+ if(pFlash.DataRemaining != 0)
+ {
+ /* Increment address to 16-bit */
+ pFlash.Address += 2;
+ addresstmp = pFlash.Address;
+
+ /* Shift to have next 16-bit data */
+ pFlash.Data = (pFlash.Data >> 16);
+
/* Operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
- /*Program halfword (16-bit) at a specified address.*/
- FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
- }
- else
- {
- /*Program ended. Return the selected address*/
- /* FLASH EOP interrupt user callback */
- if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ /*Program halfword (16-bit) at a specified address.*/
+ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
}
- else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
- {
- HAL_FLASH_EndOfOperationCallback(pFlash.Address-2);
- }
- else
+ else
{
- HAL_FLASH_EndOfOperationCallback(pFlash.Address-6);
+ /*Program ended. Return the selected address*/
+ /* FLASH EOP interrupt user callback */
+ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+ }
+ else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2);
+ }
+ else
+ {
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6);
+ }
+
+ /* Reset Address and stop Program procedure*/
+ pFlash.Address = 0xFFFFFFFF;
+ pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
-
- /* Reset Address and stop Program procedure*/
- pFlash.Address = 0xFFFFFFFF;
- pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
}
- }
}
+
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
@@ -432,7 +421,7 @@
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
/* Disable End of FLASH Operation and Error source interrupts */
- __HAL_FLASH_DISABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
@@ -495,17 +484,17 @@
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
- if((READ_BIT(FLASH->CR, FLASH_CR_LOCK)) != RESET)
+ if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK))
{
/* Authorize the FLASH Registers access */
- WRITE_REG(FLASH->KEYR, FLASH_FKEY1);
- WRITE_REG(FLASH->KEYR, FLASH_FKEY2);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);
}
else
{
return HAL_ERROR;
}
-
+
return HAL_OK;
}
@@ -518,6 +507,7 @@
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+
return HAL_OK;
}
@@ -528,7 +518,7 @@
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
- if((READ_BIT(FLASH->CR, FLASH_CR_OPTWRE)) == RESET)
+ if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
{
/* Authorizes the Option Byte register programming */
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
@@ -553,36 +543,34 @@
return HAL_OK;
}
-
+
/**
* @brief Launch the option byte loading.
- * @retval HAL status
+ * @note This function will reset automatically the MCU.
+ * @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
- /* Clean the error context */
- pFlash.ErrorCode = FLASH_ERROR_NONE;
-
- /* Set the bit to force the option byte reloading */
- SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
-
+ /* Set the OBL_Launch bit to lauch the option byte loading */
+ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
+
/* Wait for last operation to be completed */
- return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));
+ return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
}
/**
* @}
- */
+ */
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral Errors functions
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
*
@verbatim
===============================================================================
- ##### Peripheral Errors functions #####
+ ##### Peripheral State functions #####
===============================================================================
[..]
- This subsection permit to get in run-time Errors of the FLASH peripheral.
+ This subsection permit to get in run-time the status of the FLASH peripheral.
@endverbatim
* @{
@@ -591,42 +579,23 @@
/**
* @brief Get the specific FLASH error flag.
* @retval FLASH_ErrorCode: The returned value can be:
- * @arg FLASH_ERROR_PG: FLASH Programming error flag
- * @arg FLASH_ERROR_WRP: FLASH Write protected error flag
+ * @ref FLASH_Error_Codes
*/
uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
-}
+}
/**
* @}
*/
/**
* @}
- */
+ */
/** @addtogroup FLASH_Private_Functions
- * @{
- */
-/**
- * @brief Erase the specified FLASH memory page
- * @param PageAddress: FLASH page to erase
- * The value of this parameter depend on device used within the same series
- *
- * @retval None
- */
-void FLASH_PageErase(uint32_t PageAddress)
-{
- /* Clean the error context */
- pFlash.ErrorCode = FLASH_ERROR_NONE;
-
- /* Proceed to erase the page */
- SET_BIT(FLASH->CR, FLASH_CR_PER);
- WRITE_REG(FLASH->AR, PageAddress);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
-}
-
+ * @{
+ */
/**
* @brief Program a half-word (16-bit) at a specified address.
* @param Address: specifies the address to be programmed.
@@ -636,11 +605,12 @@
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
{
/* Clean the error context */
- pFlash.ErrorCode = FLASH_ERROR_NONE;
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Proceed to program the new data */
+ SET_BIT(FLASH->CR, FLASH_CR_PG);
- /* Proceed to program the new data */
- SET_BIT(FLASH->CR, FLASH_CR_PG);
-
+ /* Write data in the address */
*(__IO uint16_t*)Address = Data;
}
@@ -650,7 +620,7 @@
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
-{
+{
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
@@ -659,9 +629,9 @@
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
{
return HAL_TIMEOUT;
}
@@ -674,7 +644,7 @@
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
-
+
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
{
/*Save the error code*/
@@ -687,27 +657,32 @@
}
+
/**
* @brief Set the specific FLASH error flag.
* @retval None
*/
static void FLASH_SetErrorCode(void)
-{
+{
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
{
- pFlash.ErrorCode |= FLASH_ERROR_WRP;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
{
- pFlash.ErrorCode |= FLASH_ERROR_PG;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
}
+ /* Clear FLASH error pending bits */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
-}
+}
+/**
+ * @}
+ */
/**
* @}
- */
+ */
#endif /* HAL_FLASH_MODULE_ENABLED */
@@ -715,8 +690,4 @@
* @}
*/
-/**
- * @}
- */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_flash.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -45,67 +45,43 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
-
+
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
/** @addtogroup FLASH
* @{
- */
+ */
+
+/** @addtogroup FLASH_Private_Constants
+ * @{
+ */
+#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Private_Macros
+ * @{
+ */
+
+#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
+ ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
+
+#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
+ ((__LATENCY__) == FLASH_LATENCY_1))
+
+/**
+ * @}
+ */
/* Exported types ------------------------------------------------------------*/
-
/** @defgroup FLASH_Exported_Types FLASH Exported Types
* @{
*/
-/**
- * @brief FLASH Erase structure definition
- */
-typedef struct
-{
- uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
- This parameter can be a value of @ref FLASH_Type_Erase */
-
- uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
- This parameter must be a value of @ref FLASHEx_Address */
-
- uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
- This parameter must be a value between 1 and (max number of pages - value of initial page)*/
-
-} FLASH_EraseInitTypeDef;
-
-/**
- * @brief FLASH Options bytes program structure definition
- */
-typedef struct
-{
- uint32_t OptionType; /*!< OptionType: Option byte to be configured.
- This parameter can be a value of @ref FLASH_OB_Type */
-
- uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
- This parameter can be a value of @ref FLASH_OB_WRP_State */
-
- uint32_t WRPPage; /*!< WRPSector: specifies the page(s) to be write protected
- This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
-
- uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
- This parameter can be a value of @ref FLASH_OB_Read_Protection */
-
- uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
- IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY
- This parameter can be a combination of @ref FLASH_OB_Watchdog, @ref FLASH_OB_nRST_STOP,
- @ref FLASH_OB_nRST_STDBY, @ref FLASH_OB_BOOT1, @ref FLASH_OB_VDDA_Analog_Monitoring and
- @ref FLASH_OB_RAM_Parity_Check_Enable */
-
- uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be prgrammed
- This parameter can be a value of @ref FLASH_OB_Data_Address */
-
- uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
- This parameter can have any value */
-
-} FLASH_OBProgramInitTypeDef;
/**
* @brief FLASH Procedure structure definition
@@ -136,8 +112,7 @@
HAL_LockTypeDef Lock; /*!< FLASH locking object */
__IO uint32_t ErrorCode; /*!< FLASH error code
- This parameter can be a value of @ref FLASH_Error */
-
+ This parameter can be a value of @ref FLASH_Error_Codes */
} FLASH_ProcessTypeDef;
/**
@@ -145,29 +120,18 @@
*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{
*/
-/** @defgroup FLASH_Error FLASH Error
+/** @defgroup FLASH_Error_Codes FLASH Error Codes
* @{
- */
-#define FLASH_ERROR_NONE ((uint32_t)0x00000000)
-#define FLASH_ERROR_PG ((uint32_t)0x00000001)
-#define FLASH_ERROR_WRP ((uint32_t)0x00000002)
-/**
- * @}
*/
+
+#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00)
+#define HAL_FLASH_ERROR_PROG ((uint32_t)0x01)
+#define HAL_FLASH_ERROR_WRP ((uint32_t)0x02)
-/** @defgroup FLASH_Type_Erase FLASH Type Erase
- * @{
- */
-#define TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
-#define TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/
-
-#define IS_TYPEERASE(VALUE) (((VALUE) == TYPEERASE_PAGES) || \
- ((VALUE) == TYPEERASE_MASSERASE))
/**
* @}
*/
@@ -175,38 +139,10 @@
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
-#define TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!<Program a half-word (16-bit) at a specified address.*/
-#define TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
-#define TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!<Program a double word (64-bit) at a specified address*/
-
-#define IS_TYPEPROGRAM(VALUE) (((VALUE) == TYPEPROGRAM_HALFWORD) || \
- ((VALUE) == TYPEPROGRAM_WORD) || \
- ((VALUE) == TYPEPROGRAM_DOUBLEWORD))
-/**
- * @}
- */
+#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!<Program a half-word (16-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!<Program a double word (64-bit) at a specified address*/
-/** @defgroup FLASH_OB_WRP_State FLASH WRP State
- * @{
- */
-#define WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired pages*/
-#define WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired pagess*/
-
-#define IS_WRPSTATE(VALUE) (((VALUE) == WRPSTATE_DISABLE) || \
- ((VALUE) == WRPSTATE_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
- * @{
- */
-#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!<WRP option byte configuration*/
-#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!<RDP option byte configuration*/
-#define OPTIONBYTE_USER ((uint32_t)0x04) /*!<USER option byte configuration*/
-#define OPTIONBYTE_DATA ((uint32_t)0x08) /*!<DATA option byte configuration*/
-
-#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
/**
* @}
*/
@@ -217,93 +153,10 @@
#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
- ((LATENCY) == FLASH_LATENCY_1))
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_Data_Address FLASH OB Data Address
- * @{
- */
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_Read_Protection FLASH OB Read Protection
- * @{
- */
-#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
-#define OB_RDP_LEVEL_1 ((uint8_t)0xBB)
-#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
- it's no more possible to go back to level 1 or 0 */
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
- ((LEVEL) == OB_RDP_LEVEL_1))/*||\
- ((LEVEL) == OB_RDP_LEVEL_2))*/
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_Watchdog FLASH OB Watchdog
- * @{
- */
-#define OB_WDG_SW ((uint8_t)0x01) /*!< Software WDG selected */
-#define OB_WDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */
-#define IS_OB_WDG_SOURCE(SOURCE) (((SOURCE) == OB_WDG_SW) || ((SOURCE) == OB_WDG_HW))
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_nRST_STOP FLASH OB nRST STOP
- * @{
- */
-#define OB_STOP_NO_RST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
/**
* @}
*/
-/** @defgroup FLASH_OB_nRST_STDBY FLASH OB nRST STDBY
- * @{
- */
-#define OB_STDBY_NO_RST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_BOOT1 FLASH OB BOOT1
- * @{
- */
-#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
-#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
-#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_VDDA_Analog_Monitoring FLASH OB VDDA Analog Monitoring
- * @{
- */
-#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
-#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
-#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_RAM_Parity_Check_Enable FLASH OB RAM Parity Check Enable
- * @{
- */
-#define OB_RAM_PARITY_CHECK_SET ((uint8_t)0x00) /*!< RAM parity check enable set */
-#define OB_RAM_PARITY_CHECK_RESET ((uint8_t)0x40) /*!< RAM parity check enable reset */
-#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_RAM_PARITY_CHECK_SET) || ((PARITY) == OB_RAM_PARITY_CHECK_RESET))
-/**
- * @}
- */
/** @defgroup FLASH_Flag_definition FLASH Flag definition
* @{
@@ -325,15 +178,6 @@
* @}
*/
-/** @defgroup FLASH_Timeout_definition FLASH Timeout definition
- * @brief FLASH Timeout definition
- * @{
- */
-#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
-/**
- * @}
- */
-
/**
* @}
*/
@@ -344,7 +188,7 @@
* @brief macros to control FLASH features
* @{
*/
-
+
/** @defgroup FLASH_Latency FLASH Latency
* @brief macros to handle FLASH Latency
* @{
@@ -357,6 +201,15 @@
* @retval None
*/
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
+
+
+/**
+ * @brief Get the FLASH Latency.
+ * @retval FLASH Latency
+ * The value of this parameter depend on device used within the same series
+ */
+#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
/**
* @}
*/
@@ -380,8 +233,8 @@
/**
* @}
*/
-
-/** @defgroup FLASH_Interrupt FLASH Interrupt
+
+/** @defgroup FLASH_Interrupt FLASH Interrupts
* @brief macros to handle FLASH interrupts
* @{
*/
@@ -394,7 +247,7 @@
* @arg FLASH_IT_ERR: Error Interrupt
* @retval none
*/
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__))
/**
* @brief Disable the specified FLASH interrupt.
@@ -404,30 +257,31 @@
* @arg FLASH_IT_ERR: Error Interrupt
* @retval none
*/
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__))
/**
* @brief Get the specified FLASH flag status.
* @param __FLAG__: specifies the FLASH flag to check.
* This parameter can be one of the following values:
- * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGERR : FLASH Programming error flag
- * @arg FLASH_FLAG_BSY : FLASH Busy flag
+ * @arg FLASH_FLAG_BSY : FLASH Busy flag
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGERR : FLASH Programming error flag
* @retval The new state of __FLAG__ (SET or RESET).
*/
-#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)) == (__FLAG__))
+#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
/**
* @brief Clear the specified FLASH flag.
* @param __FLAG__: specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_PGERR : FLASH Programming error flag
+ * @arg FLASH_FLAG_BSY : FLASH Busy flag
+ * @arg FLASH_FLAG_EOP : FLASH End of Operation flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_PGERR : FLASH Programming error flag
* @retval none
*/
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))
/**
* @}
@@ -436,56 +290,49 @@
/**
* @}
*/
-
-/* Include FLASH HAL Extension module */
+
+/* Include FLASH HAL Extended module */
#include "stm32f0xx_hal_flash_ex.h"
/* Exported functions --------------------------------------------------------*/
-
/** @addtogroup FLASH_Exported_Functions
* @{
- */
-
-/** @addtogroup FLASH_Exported_Functions_Group1
- * @brief Data transfers functions
- * @{
- */
+ */
+/** @addtogroup FLASH_Exported_Functions_Group1
+ * @{
+ */
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
/* FLASH IRQ handler method */
-void HAL_FLASH_IRQHandler(void);
+void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */
-void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Exported_Functions_Group2
- * @brief management functions
- * @{
- */
-
-/* FLASH Memory Programming functions *****************************************/
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-
-/* Option Bytes Programming functions *****************************************/
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
/**
* @}
*/
-/** @addtogroup FLASH_Exported_Functions_Group3
- * @{
- */
+/** @addtogroup FLASH_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+ * @{
+ */
/* Peripheral State and Error functions ***************************************/
uint32_t HAL_FLASH_GetError(void);
@@ -497,6 +344,17 @@
* @}
*/
+/* Private function -------------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+void FLASH_PageErase(uint32_t PageAddress);
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/**
+ * @}
+ */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,15 +2,15 @@
******************************************************************************
* @file stm32f0xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Extended FLASH HAL module driver.
+ *
* This file provides firmware functions to manage the following
* functionalities of the FLASH peripheral:
* + Extended Initialization/de-initialization functions
* + Extended I/O operation functions
* + Extended Peripheral Control functions
- * + Extended Peripheral State functions
*
@verbatim
==============================================================================
@@ -22,15 +22,15 @@
[..] This driver provides functions to configure and program the FLASH memory
of all STM32F0xxx devices. It includes
- (+) Set/Reset the write protection
- (+) Program the user Option Bytes
- (+) Get the Read protection Level
+ (++) Set/Reset the write protection
+ (++) Program the user Option Bytes
+ (++) Get the Read protection Level
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,46 +63,53 @@
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
-
-/** @defgroup FLASHEx FLASHEx Extended HAL module driver
- * @brief FLASH Extended HAL module driver
- * @{
- */
-
#ifdef HAL_FLASH_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @addtogroup FLASHEx_Private_Constants FLASHEx Private Constants
+/** @addtogroup FLASH
* @{
- */
-#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+ */
+/** @addtogroup FLASH_Private_Variables
+ * @{
+ */
+/* Variables used for Erase pages under interruption*/
+extern FLASH_ProcessTypeDef pFlash;
+/**
+ * @}
+ */
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup FLASHEx_Private_Variables FLASHEx Private Variables
+/** @defgroup FLASHEx FLASHEx
+ * @brief FLASH Extended HAL module driver
* @{
- */
-
-/* Variables used for Erase pages under interruption*/
-extern FLASH_ProcessTypeDef pFlash;
+ */
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
+ * @{
+ */
+#define FLASH_POSITION_IWDGSW_BIT (uint32_t)8
/**
* @}
*/
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
* @{
*/
-
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
/* Erase operations */
-extern void FLASH_PageErase(uint32_t PageAddress);
static void FLASH_MassErase(void);
/* Option bytes control */
@@ -112,29 +119,20 @@
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
static uint32_t FLASH_OB_GetWRP(void);
-static FlagStatus FLASH_OB_GetRDP(void);
+static uint8_t FLASH_OB_GetRDP(void);
static uint8_t FLASH_OB_GetUser(void);
/**
* @}
*/
-/** @defgroup FLASHEx_Extern_Functions FLASHEx Extern Functions
- * @{
- */
-/* Private functions ---------------------------------------------------------*/
-extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-
-/**
- * @}
- */
-
+/* Exported functions ---------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
* @{
*/
-
-/** @defgroup FLASHEx_Exported_Functions_Group2 Extended I/O operation functions
- * @brief Extended I/O operation functions
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended Input and Output operation functions
+ * @brief I/O operation functions
*
@verbatim
===============================================================================
@@ -144,76 +142,83 @@
@endverbatim
* @{
*/
+
+
/**
- * @brief Perform a mass erase or erase the specified FLASH memory pages
+ * @brief Perform a mass erase or erase the specified FLASH memory pages
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
* @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
* contains the configuration information for the erasing.
- *
+ *
* @param[out] PageError: pointer to variable that
- * contains the configuration information on faulty page in case of error
+ * contains the configuration information on faulty page in case of error
* (0xFFFFFFFF means that all the pages have been correctly erased)
- *
+ *
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
{
HAL_StatusTypeDef status = HAL_ERROR;
uint32_t address = 0;
-
+
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Check the parameters */
- assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
- if (status == HAL_OK)
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
{
- if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
- {
- /*Mass erase to be done*/
- FLASH_MassErase();
-
+ /* Mass Erase requested for Bank1 */
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the MER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
- }
- else
- {
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
- assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
-
- /*Initialization of PageError variable*/
- *PageError = 0xFFFFFFFF;
+ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
+ {
+ /*Mass erase to be done*/
+ FLASH_MassErase();
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the MER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
+ }
+ }
+ else
+ {
+ /* Page Erase is requested */
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
+ assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
- /* Erase by page by page to be done*/
- for(address = pEraseInit->PageAddress;
- address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE);
- address += FLASH_PAGE_SIZE)
+ /* Page Erase requested on address located on bank1 */
+ /* Wait for last operation to be completed */
+ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
{
- FLASH_PageErase(address);
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
-
- /* If the erase operation is completed, disable the PER Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
-
- if (status != HAL_OK)
+ /*Initialization of PageError variable*/
+ *PageError = 0xFFFFFFFF;
+
+ /* Erase by page by page to be done*/
+ for(address = pEraseInit->PageAddress;
+ address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE);
+ address += FLASH_PAGE_SIZE)
{
- /* In case of error, stop erase procedure and return the faulty address */
- *PageError = address;
- break;
+ FLASH_PageErase(address);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the PER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
+
+ if (status != HAL_OK)
+ {
+ /* In case of error, stop erase procedure and return the faulty address */
+ *PageError = address;
+ break;
+ }
}
}
- }
}
/* Process Unlocked */
@@ -228,7 +233,7 @@
* The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
* @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
* contains the configuration information for the erasing.
- *
+ *
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
@@ -245,16 +250,16 @@
}
/* Check the parameters */
- assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
+ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
/* Enable End of FLASH Operation and Error source interrupts */
__HAL_FLASH_ENABLE_IT((FLASH_IT_EOP | FLASH_IT_ERR));
-
- if (pEraseInit->TypeErase == TYPEERASE_MASSERASE)
+
+ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
{
/*Mass erase to be done*/
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
- FLASH_MassErase();
+ FLASH_MassErase();
}
else
{
@@ -279,8 +284,8 @@
* @}
*/
-/** @defgroup FLASHEx_Exported_Functions_Group3 Extended Peripheral Control functions
- * @brief Extended Peripheral Control functions
+/** @defgroup FLASHEx_Exported_Functions_Group2 Extended Peripheral Control functions
+ * @brief Peripheral Control functions
*
@verbatim
===============================================================================
@@ -293,12 +298,13 @@
@endverbatim
* @{
*/
+
/**
* @brief Erases the FLASH option bytes.
- * @note This functions erases all option bytes except the Read protection (RDP).
+ * @note This functions erases all option bytes except the Read protection (RDP).
* The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
* The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
- * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
* (system reset will occur)
* @retval HAL status
*/
@@ -307,39 +313,32 @@
{
uint8_t rdptmp = OB_RDP_LEVEL_0;
HAL_StatusTypeDef status = HAL_ERROR;
- FLASH_OBProgramInitTypeDef optionsbytes;
/* Get the actual read protection Option Byte value */
- HAL_FLASHEx_OBGetConfig(&optionsbytes);
- if(optionsbytes.RDPLevel != RESET)
- {
- rdptmp = OB_RDP_LEVEL_1;
- }
+ rdptmp = FLASH_OB_GetRDP();
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Clean the error context */
- pFlash.ErrorCode = FLASH_ERROR_NONE;
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* If the previous operation is completed, proceed to erase the option bytes */
SET_BIT(FLASH->CR, FLASH_CR_OPTER);
SET_BIT(FLASH->CR, FLASH_CR_STRT);
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
-
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
/* If the erase operation is completed, disable the OPTER Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
if(status == HAL_OK)
{
/* Restore the last read protection Option Byte value */
- optionsbytes.OptionType = OPTIONBYTE_RDP;
- optionsbytes.RDPLevel = rdptmp;
- status = HAL_FLASHEx_OBProgram(&optionsbytes);
+ status = FLASH_OB_RDP_LevelConfig(rdptmp);
}
}
@@ -351,18 +350,18 @@
* @brief Program option bytes
* @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
* The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
- * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
+ * The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
* (system reset will occur)
*
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
- *
+ *
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
{
HAL_StatusTypeDef status = HAL_ERROR;
-
+
/* Check the parameters */
assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
@@ -370,7 +369,7 @@
if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
{
assert_param(IS_WRPSTATE(pOBInit->WRPState));
- if (pOBInit->WRPState == WRPSTATE_ENABLE)
+ if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
{
/* Enable of Write protection on the selected page */
status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
@@ -407,7 +406,7 @@
* @brief Get the Option byte configuration
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
- *
+ *
* @retval None
*/
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
@@ -432,29 +431,30 @@
* @}
*/
-/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
- * @{
- */
+/** @addtogroup FLASHEx_Private_Functions
+ * @{
+ */
/**
- * @brief Mass erase of FLASH memory
- * @retval None
+ * @brief Full erase of FLASH memory Bank
+ *
+ * @retval HAL Status
*/
static void FLASH_MassErase(void)
{
-
/* Clean the error context */
- pFlash.ErrorCode = FLASH_ERROR_NONE;
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
- /* Proceed to erase all sectors */
- SET_BIT(FLASH->CR, FLASH_CR_MER);
- SET_BIT(FLASH->CR, FLASH_CR_STRT);
+ /* Only bank1 will be erased*/
+ SET_BIT(FLASH->CR, FLASH_CR_MER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
}
/**
* @brief Enable the write protection of the desired pages
+ * @note An option byte erase is done automatically in this function.
* @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase the flash page i if CortexM4
+ * it is not possible to program or erase the flash page i if
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
*
* @param WriteProtectPage: specifies the page(s) to be write protected.
@@ -464,96 +464,103 @@
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
{
HAL_StatusTypeDef status = HAL_OK;
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
- defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
uint16_t WRP0_Data = 0xFFFF;
-#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+#if defined(OB_WRP1_WRP1)
uint16_t WRP1_Data = 0xFFFF;
-#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
- uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
+#endif /* OB_WRP1_WRP1 */
+#if defined(OB_WRP2_WRP2)
+ uint16_t WRP2_Data = 0xFFFF;
+#endif /* OB_WRP2_WRP2 */
+#if defined(OB_WRP3_WRP3)
+ uint16_t WRP3_Data = 0xFFFF;
+#endif /* OB_WRP3_WRP3 */
/* Check the parameters */
assert_param(IS_OB_WRP(WriteProtectPage));
- WriteProtectPage = (uint32_t)(~WriteProtectPage);
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
- defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
+ /* Get current write protected pages and the new pages to be protected ******/
+ WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
+
+#if defined(OB_WRP_PAGES0TO31MASK)
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
-#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8);
-#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx)|| defined(STM32F030xC)
+#elif defined(OB_WRP_PAGES0TO15MASK)
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
+#endif /* OB_WRP_PAGES0TO31MASK */
+
+#if defined(OB_WRP_PAGES32TO63MASK)
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8);
+#elif defined(OB_WRP_PAGES16TO31MASK)
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+#endif /* OB_WRP_PAGES32TO63MASK */
+
+#if defined(OB_WRP_PAGES32TO47MASK)
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#endif /* OB_WRP_PAGES32TO47MASK */
+
+#if defined(OB_WRP_PAGES48TO63MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24);
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx */
-#if defined(STM32F091xC) || defined(STM32F098xx)
+#elif defined(OB_WRP_PAGES48TO127MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
-#endif /* STM32F091xC || STM32F098xx */
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
-
+#endif /* OB_WRP_PAGES48TO63MASK */
+
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
- {
+ {
/* Clean the error context */
- pFlash.ErrorCode = FLASH_ERROR_NONE;
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
- if(WRP0_Data != 0xFF)
+ /* To be able to write again option byte, need to perform a option byte erase */
+ status = HAL_FLASHEx_OBErase();
+ if (status == HAL_OK)
{
- OB->WRP0 &= WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
- }
+ /* Enable write protection */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+#if defined(OB_WRP0_WRP0)
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 &= WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP0_WRP0 */
+
+#if defined(OB_WRP1_WRP1)
+ if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 &= WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP1_WRP1 */
-#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
- if((status == HAL_OK) && (WRP1_Data != 0xFF))
- {
- OB->WRP1 &= WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+#if defined(OB_WRP2_WRP2)
+ if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 &= WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP2_WRP2 */
+
+#if defined(OB_WRP3_WRP3)
+ if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 &= WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP3_WRP3 */
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
}
-#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx || STM32F071xB || STM32F070xB ||
- STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)|| defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
- if((status == HAL_OK) && (WRP2_Data != 0xFF))
- {
- OB->WRP2 &= WRP2_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
- }
-
- if((status == HAL_OK) && (WRP3_Data != 0xFF))
- {
- OB->WRP3 &= WRP3_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
- }
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC*/
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
}
return status;
@@ -561,8 +568,9 @@
/**
* @brief Disable the write protection of the desired pages
+ * @note An option byte erase is done automatically in this function.
* @note When the memory read protection level is selected (RDP level = 1),
- * it is not possible to program or erase the flash page i if CortexM4
+ * it is not possible to program or erase the flash page i if
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
*
* @param WriteProtectPage: specifies the page(s) to be write unprotected.
@@ -572,96 +580,103 @@
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
{
HAL_StatusTypeDef status = HAL_OK;
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
- defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
uint16_t WRP0_Data = 0xFFFF;
-#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+#if defined(OB_WRP1_WRP1)
uint16_t WRP1_Data = 0xFFFF;
-#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
- uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
+#endif /* OB_WRP1_WRP1 */
+#if defined(OB_WRP2_WRP2)
+ uint16_t WRP2_Data = 0xFFFF;
+#endif /* OB_WRP2_WRP2 */
+#if defined(OB_WRP3_WRP3)
+ uint16_t WRP3_Data = 0xFFFF;
+#endif /* OB_WRP3_WRP3 */
/* Check the parameters */
assert_param(IS_OB_WRP(WriteProtectPage));
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || STM32F070x6 || \
- defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx)
+ /* Get current write protected pages and the new pages to be unprotected ******/
+ WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);
+
+#if defined(OB_WRP_PAGES0TO31MASK)
WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
-#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+#elif defined(OB_WRP_PAGES0TO15MASK)
+ WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
+#endif /* OB_WRP_PAGES0TO31MASK */
+
+#if defined(OB_WRP_PAGES32TO63MASK)
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8);
-#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
- WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
+#elif defined(OB_WRP_PAGES16TO31MASK)
WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+#endif /* OB_WRP_PAGES32TO63MASK */
+
+#if defined(OB_WRP_PAGES32TO47MASK)
WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#endif /* OB_WRP_PAGES32TO47MASK */
+
+#if defined(OB_WRP_PAGES48TO63MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO63MASK) >> 24);
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx */
-#if defined(STM32F091xC) || defined(STM32F098xx)
+#elif defined(OB_WRP_PAGES48TO127MASK)
WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
-#endif /* STM32F091xC || STM32F098xx */
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070xB */
-
+#endif /* OB_WRP_PAGES48TO63MASK */
+
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
- {
+ {
/* Clean the error context */
- pFlash.ErrorCode = FLASH_ERROR_NONE;
-
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
- if(WRP0_Data != 0xFF)
+ /* To be able to write again option byte, need to perform a option byte erase */
+ status = HAL_FLASHEx_OBErase();
+ if (status == HAL_OK)
{
- OB->WRP0 |= WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
- }
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+#if defined(OB_WRP0_WRP0)
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 |= WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP0_WRP0 */
+
+#if defined(OB_WRP1_WRP1)
+ if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 |= WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP1_WRP1 */
-#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
- if((status == HAL_OK) && (WRP1_Data != 0xFF))
- {
- OB->WRP1 |= WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+#if defined(OB_WRP2_WRP2)
+ if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 |= WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP2_WRP2 */
+
+#if defined(OB_WRP3_WRP3)
+ if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 |= WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ }
+#endif /* OB_WRP3_WRP3 */
+
+ /* if the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
}
-#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx || STM32F071xB || STM32F070xB ||
- STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
- if((status == HAL_OK) && (WRP2_Data != 0xFF))
- {
- OB->WRP2 |= WRP2_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
- }
-
- if((status == HAL_OK) && (WRP3_Data != 0xFF))
- {
- OB->WRP3 |= WRP3_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
- }
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
-
- /* if the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
+ }
return status;
}
@@ -672,9 +687,7 @@
* @arg OB_RDP_LEVEL_0: No protection
* @arg OB_RDP_LEVEL_1: Read protection of the memory
* @arg OB_RDP_LEVEL_2: Full chip protection
- *
* @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
- *
* @retval HAL status
*/
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
@@ -683,26 +696,39 @@
/* Check the parameters */
assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
-
+
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
-
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
if(status == HAL_OK)
{
/* Clean the error context */
- pFlash.ErrorCode = FLASH_ERROR_NONE;
-
- /* Enable the Option Bytes Programming operation */
- SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
- WRITE_REG(OB->RDP, ReadProtectLevel);
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* If the previous operation is completed, proceed to erase the option bytes */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTER);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+ /* If the erase operation is completed, disable the OPTER Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
+ if(status == HAL_OK)
+ {
+ /* Enable the Option Bytes Programming operation */
+ SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
+ WRITE_REG(OB->RDP, ReadProtectLevel);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
/* if the program operation is completed, disable the OPTPG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
}
+ }
return status;
}
@@ -710,8 +736,9 @@
/**
* @brief Program the FLASH User Option Byte.
* @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
- * @param UserConfig: The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), BOOT1(Bit4),
+ * @param UserConfig: The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
* VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
+ * For few devices, following option bytes are available: nBOOT0(Bit3) & BOOT_SEL(Bit7).
* @retval HAL status
*/
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
@@ -719,36 +746,36 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_OB_WDG_SOURCE((UserConfig&OB_WDG_SW)));
+ assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON)));
assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_RAM_PARITY_CHECK_RESET)));
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)|| defined(STM32F070x6)
+#if defined(FLASH_OBR_BOOT_SEL)
assert_param(IS_OB_BOOT_SEL((UserConfig&OB_BOOT_SEL_SET)));
assert_param(IS_OB_BOOT0((UserConfig&OB_BOOT0_SET)));
-#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070x6 */
+#endif /* FLASH_OBR_BOOT_SEL */
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Clean the error context */
- pFlash.ErrorCode = FLASH_ERROR_NONE;
-
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
/* Enable the Option Bytes Programming operation */
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)|| defined(STM32F070x6)
+
+#if defined(FLASH_OBR_BOOT_SEL)
OB->USER = UserConfig;
#else
OB->USER = (UserConfig | 0x88);
-#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070x6 */
-
+#endif /* FLASH_OBR_BOOT_SEL */
+
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* if the program operation is completed, disable the OPTPG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
@@ -772,28 +799,28 @@
static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
{
HAL_StatusTypeDef status = HAL_ERROR;
-
+
/* Check the parameters */
assert_param(IS_OB_DATA_ADDRESS(Address));
-
+
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
-
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
if(status == HAL_OK)
{
/* Clean the error context */
- pFlash.ErrorCode = FLASH_ERROR_NONE;
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Enables the Option Bytes Programming operation */
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
*(__IO uint16_t*)Address = Data;
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
- /* If the program operation is completed, disable the OPTPG Bit */
- CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
- }
+ /* If the program operation is completed, disable the OPTPG Bit */
+ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
+ }
/* Return the Option Byte Data Program Status */
return status;
}
@@ -811,16 +838,26 @@
/**
* @brief Returns the FLASH Read Protection level.
* @retval FLASH ReadOut Protection Status:
- * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
- * - RESET, when OB_RDP_Level_0 is set
+ * This parameter can be one of the following values:
+ * @arg OB_RDP_LEVEL_0: No protection
+ * @arg OB_RDP_LEVEL_1: Read protection of the memory
+ * @arg OB_RDP_LEVEL_2: Full chip protection
*/
-static FlagStatus FLASH_OB_GetRDP(void)
+static uint8_t FLASH_OB_GetRDP(void)
{
- FlagStatus readstatus = RESET;
+ uint8_t readstatus = OB_RDP_LEVEL_0;
- if ((uint8_t)READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT1) != RESET)
+ if (HAL_IS_BIT_SET(FLASH->OBR, FLASH_OBR_RDPRT1))
+ {
+ readstatus = OB_RDP_LEVEL_1;
+ }
+ else if (HAL_IS_BIT_SET(FLASH->OBR, FLASH_OBR_RDPRT2))
{
- readstatus = SET;
+ readstatus = OB_RDP_LEVEL_2;
+ }
+ else
+ {
+ readstatus = OB_RDP_LEVEL_0;
}
return readstatus;
@@ -828,27 +865,67 @@
/**
* @brief Return the FLASH User Option Byte value.
- * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), BOOT1(Bit4),
- * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
+ * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit0), FLASH_OBR_nRST_STOP(Bit1),
+ * FLASH_OBR_nRST_STDBY(Bit2), FLASH_OBR_nBOOT1(Bit4),
+ * FLASH_OBR_VDDA_MONITOR(Bit5), FLASH_OBR_RAM_PARITY_CHECK(Bit6) and FLASH_OBR_BOOT_SEL(Bit7) (*).
+ * @note (*) not present on all the devices.
*/
static uint8_t FLASH_OB_GetUser(void)
{
/* Return the User Option Byte */
- return (uint8_t)(READ_REG(FLASH->OBR) >> 8);
+ return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
}
/**
* @}
*/
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
- * @}
- */
-
/**
* @}
*/
+/** @addtogroup FLASH
+ * @{
+ */
+
+
+/** @addtogroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Erase the specified FLASH memory page
+ * @param PageAddress: FLASH page to erase
+ * The value of this parameter depend on device used within the same series
+ *
+ * @retval None
+ */
+void FLASH_PageErase(uint32_t PageAddress)
+{
+ /* Clean the error context */
+ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+ /* Proceed to erase the page */
+ SET_BIT(FLASH->CR, FLASH_CR_PER);
+ WRITE_REG(FLASH->AR, PageAddress);
+ SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_flash_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_flash_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
- * @brief Header file of FLASH HAL Extension module.
+ * @version V1.3.0
+ * @date 26-June-2015
+ * @brief Header file of Flash HAL Extended module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,68 +54,152 @@
* @{
*/
+/** @addtogroup FLASHEx_Private_Macros
+ * @{
+ */
+#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
+ ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+
+#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
+
+#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
+ ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
+ ((LEVEL) == OB_RDP_LEVEL_1))/*||\
+ ((LEVEL) == OB_RDP_LEVEL_2))*/
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+
+#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
+
+#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_RAM_PARITY_CHECK_SET) || ((PARITY) == OB_RAM_PARITY_CHECK_RESET))
+
+#if defined(FLASH_OBR_BOOT_SEL)
+#define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET))
+#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET))
+#endif /* FLASH_OBR_BOOT_SEL */
+
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= FLASH_BANK1_END)
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BANK1_END))
+
+/**
+ * @}
+ */
/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
+ * @{
+ */
+/**
+ * @brief FLASH Erase structure definition
+ */
+typedef struct
+{
+ uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
+ This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+ uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
+ This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */
+
+ uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
+ This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
+
+} FLASH_EraseInitTypeDef;
+
+/**
+ * @brief FLASH Options bytes program structure definition
+ */
+typedef struct
+{
+ uint32_t OptionType; /*!< OptionType: Option byte to be configured.
+ This parameter can be a value of @ref FLASHEx_OB_Type */
+
+ uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
+ This parameter can be a value of @ref FLASHEx_OB_WRP_State */
+
+ uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
+ This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
+
+ uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
+ This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
+
+ uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
+ IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY
+ This parameter can be a combination of @ref FLASHEx_OB_Watchdog, @ref FLASHEx_OB_nRST_STOP,
+ @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring and
+ @ref FLASHEx_OB_RAM_Parity_Check_Enable */
+
+ uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
+ This parameter can be a value of @ref FLASHEx_OB_Data_Address */
+
+ uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+} FLASH_OBProgramInitTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
* @{
*/
-/** @defgroup FLASHEx_Address FLASHEx Address
- * @{
- */
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx) || defined(STM32F070x6)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x08007FFF))
-#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */
-
-#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF))
-#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF))
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB*/
-
-#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
-#endif /* STM32F091xC || STM32F098xx || STM32F030xC*/
-/**
- * @}
- */
-
/** @defgroup FLASHEx_Page_Size FLASHEx Page Size
* @{
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
+ || defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
#define FLASH_PAGE_SIZE 0x400
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define FLASH_PAGE_SIZE 0x800
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */
/**
* @}
*/
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+ * @{
+ */
+#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
+#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/
-/** @defgroup FLASHEx_Nb_Pages FLASHEx Nb Pages
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_Type FLASH Option Bytes Type
* @{
*/
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx)|| defined(STM32F070x6)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF)
-#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */
-
-#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF)
-#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!<WRP option byte configuration*/
+#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!<RDP option byte configuration*/
+#define OPTIONBYTE_USER ((uint32_t)0x04) /*!<USER option byte configuration*/
+#define OPTIONBYTE_DATA ((uint32_t)0x08) /*!<DATA option byte configuration*/
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF)
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
-
-#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF)
-#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+/**
+ * @}
+ */
+
+
+/** @defgroup FLASHEx_OB_WRP_State FLASH WRP State
+ * @{
+ */
+#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired pages*/
+#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired pagess*/
+
/**
* @}
*/
@@ -123,8 +207,8 @@
/** @defgroup FLASHEx_OB_Write_Protection FLASHEx OB Write Protection
* @{
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
+ || defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
#define OB_WRP_PAGES0TO3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
#define OB_WRP_PAGES4TO7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
#define OB_WRP_PAGES8TO11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
@@ -144,7 +228,11 @@
#define OB_WRP_PAGES60TO63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
+ || defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
#define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF)
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx || STM32F070x6 */
+
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
#define OB_WRP_PAGES32TO63MASK ((uint32_t)0x0000FF00)
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
@@ -158,8 +246,8 @@
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx || STM32F070x6 */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define OB_WRP_PAGES0TO1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
#define OB_WRP_PAGES2TO3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
#define OB_WRP_PAGES4TO5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
@@ -198,9 +286,13 @@
#define OB_WRP_PAGES62TO127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
+ || defined(STM32F091xC) || defined(STM32F098xx)|| defined(STM32F030xC)
#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */
+
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
#define OB_WRP_PAGES48TO63MASK ((uint32_t)0xFF000000)
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
@@ -211,18 +303,80 @@
#define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all pages */
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070xB */
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
/**
* @}
*/
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)|| defined(STM32F070x6)
+/** @defgroup FLASHEx_OB_Read_Protection FLASH OB Read Protection
+ * @{
+ */
+#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
+#define OB_RDP_LEVEL_1 ((uint8_t)0xBB)
+#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
+ it's no more possible to go back to level 1 or 0 */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_Watchdog FLASH OB Watchdog
+ * @{
+ */
+#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software WDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_nRST_STOP FLASH OB nRST STOP
+ * @{
+ */
+#define OB_STOP_NO_RST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_nRST_STDBY FLASH OB nRST STDBY
+ * @{
+ */
+#define OB_STDBY_NO_RST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_BOOT1 FLASH OB BOOT1
+ * @{
+ */
+#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_VDDA_Analog_Monitoring FLASH OB VDDA Analog Monitoring
+ * @{
+ */
+#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
+#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
+/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_OB_RAM_Parity_Check_Enable FLASH OB RAM Parity Check Enable
+ * @{
+ */
+#define OB_RAM_PARITY_CHECK_SET ((uint8_t)0x00) /*!< RAM parity check enable set */
+#define OB_RAM_PARITY_CHECK_RESET ((uint8_t)0x40) /*!< RAM parity check enable reset */
+/**
+ * @}
+ */
+#if defined(FLASH_OBR_BOOT_SEL)
/** @defgroup FLASHEx_OB_BOOT_SEL FLASHEx OB BOOT SEL
* @{
*/
#define OB_BOOT_SEL_RESET ((uint8_t)0x00) /*!< BOOT_SEL Reset */
#define OB_BOOT_SEL_SET ((uint8_t)0x80) /*!< BOOT_SEL Set */
-#define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET))
/**
* @}
*/
@@ -232,11 +386,19 @@
*/
#define OB_BOOT0_RESET ((uint8_t)0x00) /*!< BOOT0 Reset */
#define OB_BOOT0_SET ((uint8_t)0x08) /*!< BOOT0 Set */
-#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET))
/**
* @}
*/
-#endif /* STM32F042x6 || STM32F048xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070x6 */
+#endif /* FLASH_OBR_BOOT_SEL */
+
+/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
+ * @{
+ */
+#define OB_DATA_ADDRESS_DATA0 ((uint32_t)0x1FFFF804)
+#define OB_DATA_ADDRESS_DATA1 ((uint32_t)0x1FFFF806)
+/**
+ * @}
+ */
/**
* @}
@@ -245,12 +407,11 @@
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+/** @addtogroup FLASHEx_Exported_Functions
* @{
*/
-/** @addtogroup FLASHEx_Exported_Functions_Group2 Extended I/O operation functions
- * @brief Extended I/O operation functions
+/** @addtogroup FLASHEx_Exported_Functions_Group1
* @{
*/
/* IO operation functions *****************************************************/
@@ -261,8 +422,7 @@
* @}
*/
-/** @addtogroup FLASHEx_Exported_Functions_Group3 Extended Peripheral Control functions
- * @brief Extended Peripheral Control functions
+/** @addtogroup FLASHEx_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -15,58 +15,51 @@
##### GPIO Peripheral features #####
==============================================================================
[..]
- Each port bit of the general-purpose I/O (GPIO) ports can be individually
+ (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
configured by software in several modes:
- (+) Input mode
- (+) Analog mode
- (+) Output mode
- (+) Alternate function mode
- (+) External interrupt/event lines
+ (++) Input mode
+ (++) Analog mode
+ (++) Output mode
+ (++) Alternate function mode
+ (++) External interrupt/event lines
- [..]
- During and just after reset, the alternate functions and external interrupt
+ (+) During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
- [..]
- All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+ (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.
- [..]
- In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+ (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
- [..]
- The microcontroller IO pins are connected to onboard peripherals/modules through a
- multiplexer that allows only one peripheral s alternate function (AF) connected
+ (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+ multiplexer that allows only one peripheral alternate function (AF) connected
to an IO pin at a time. In this way, there can be no conflict between peripherals
sharing the same IO pin.
- [..]
- All ports have external interrupt/event capability. To use external interrupt
+ (+) All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
- [..]
- The external interrupt/event controller consists of up to 28 edge detectors
- (depending on products 16 lines are connected to GPIO) for generating event/interrupt
- requests (each input line can be independently configured to select the type
- (interrupt or event) and the corresponding trigger event (rising or falling or both).
- Each line can also be masked independently.
+ (+) The external interrupt/event controller consists of up to 28 edge detectors
+ (16 lines are connected to GPIO) for generating event/interrupt requests (each
+ input line can be independently configured to select the type (interrupt or event)
+ and the corresponding trigger event (rising or falling or both). Each line can
+ also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
- (#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE().
+ (#) Enable the GPIO AHB clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
structure.
(++) In case of Output or alternate function mode selection: the speed is
- configured through "Speed" member from GPIO_InitTypeDef structure,
- the speed is configurable: Low, Medium and High.
- (++) If alternate mode is selected, the alternate function connected to the IO
- is configured through "Alternate" member from GPIO_InitTypeDef structure
+ configured through "Speed" member from GPIO_InitTypeDef structure.
+ (++) In alternate mode is selection, the alternate function connected to the IO
+ is configured through "Alternate" member from GPIO_InitTypeDef structure.
(++) Analog mode is required when a pin is to be used as ADC channel
or DAC output.
(++) In case of external interrupt/event selection the "Mode" member from
@@ -98,14 +91,14 @@
priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
- general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
+ general purpose PF0 and PF1, respectively, when the HSE oscillator is off.
The HSE has priority over the GPIO function.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -139,7 +132,7 @@
* @{
*/
-/** @defgroup GPIO GPIO HAL module driver
+/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
@@ -147,8 +140,8 @@
#ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Define GPIO Private Define
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup GPIO_Private_Defines GPIO Private Defines
* @{
*/
#define GPIO_MODE ((uint32_t)0x00000003)
@@ -160,15 +153,14 @@
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
#define GPIO_NUMBER ((uint32_t)16)
-
/**
* @}
*/
-
-/* Private macro -------------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Exporte functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @{
@@ -187,10 +179,8 @@
*/
/**
- * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
- * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx
- * @note GPIOE is only available on STM32F07xx and STM32F09xx
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
@@ -225,15 +215,15 @@
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
- temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+ CLEAR_BIT(temp, (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+ SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
GPIOx->AFR[position >> 3] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
- temp &= ~(GPIO_MODER_MODER0 << (position * 2));
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
+ SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */
@@ -244,21 +234,21 @@
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
- temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- temp |= (GPIO_Init->Speed << (position * 2));
+ CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+ SET_BIT(temp, GPIO_Init->Speed << (position * 2));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
- temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+ CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
+ SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
GPIOx->OTYPER = temp;
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
- temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
- temp |= ((GPIO_Init->Pull) << (position * 2));
+ CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
+ SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
GPIOx->PUPDR = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
@@ -266,44 +256,44 @@
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
{
/* Enable SYSCFG Clock */
- __SYSCFG_CLK_ENABLE();
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2];
- temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
- temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)));
+ CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03)));
+ SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
SYSCFG->EXTICR[position >> 2] = temp;
/* Clear EXTI line configuration */
temp = EXTI->IMR;
- temp &= ~((uint32_t)iocurrent);
+ CLEAR_BIT(temp, (uint32_t)iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
- temp |= iocurrent;
+ SET_BIT(temp, iocurrent);
}
EXTI->IMR = temp;
temp = EXTI->EMR;
- temp &= ~((uint32_t)iocurrent);
+ CLEAR_BIT(temp, (uint32_t)iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{
- temp |= iocurrent;
+ SET_BIT(temp, iocurrent);
}
EXTI->EMR = temp;
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
- temp &= ~((uint32_t)iocurrent);
+ CLEAR_BIT(temp, (uint32_t)iocurrent);
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
{
- temp |= iocurrent;
+ SET_BIT(temp, iocurrent);
}
EXTI->RTSR = temp;
temp = EXTI->FTSR;
- temp &= ~((uint32_t)iocurrent);
+ CLEAR_BIT(temp, (uint32_t)iocurrent);
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
{
- temp |= iocurrent;
+ SET_BIT(temp, iocurrent);
}
EXTI->FTSR = temp;
}
@@ -314,10 +304,8 @@
}
/**
- * @brief De-initializes the GPIOx peripheral registers to their default reset values.
+ * @brief De-initialize the GPIOx peripheral registers to their default reset values.
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
- * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx
- * @note GPIOE is only available on STM32F07xx and STM32F09xx
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @retval None
@@ -342,19 +330,19 @@
{
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO Direction in Input Floting Mode */
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
+ CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2));
/* Configure the default Alternate Function in current IO */
- GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+ CLEAR_BIT(GPIOx->AFR[position >> 3], (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
/* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+ CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
/* Configure the default value IO Output Type */
- GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
+ CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ;
/* Deactivate the Pull-up oand Pull-down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2));
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
@@ -364,15 +352,15 @@
if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
{
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
- SYSCFG->EXTICR[position >> 2] &= ~tmp;
+ CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp);
/* Clear EXTI line configuration */
- EXTI->IMR &= ~((uint32_t)iocurrent);
- EXTI->EMR &= ~((uint32_t)iocurrent);
+ CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
+ CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
/* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~((uint32_t)iocurrent);
- EXTI->FTSR &= ~((uint32_t)iocurrent);
+ CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
+ CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
}
}
@@ -397,10 +385,8 @@
*/
/**
- * @brief Reads the specified input port pin.
+ * @brief Read the specified input port pin.
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
- * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx
- * @note GPIOE is only available on STM32F07xx and STM32F09xx
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
@@ -424,13 +410,12 @@
}
/**
- * @brief Sets or clears the selected data port bit.
- * @note This function uses GPIOx_BSRR register to allow atomic read/modify
+ * @brief Set or clear the selected data port bit.
+ * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
- * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
- * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx
- * @note GPIOE is only available on STM32F07xx and STM32F09xx
+ *
+ * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32F0 family
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinState: specifies the value to be written to the selected bit.
@@ -451,16 +436,14 @@
}
else
{
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
+ GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
/**
- * @brief Toggles the specified GPIO pin
+ * @brief Toggle the specified GPIO pin.
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
- * @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx
- * @note GPIOE is only available on STM32F07xx and STM32F09xx
- * @param GPIO_Pin: specifies the pins to be toggled.
+ * @param GPIO_Pin: specifies the pin to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
@@ -477,10 +460,8 @@
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
-* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
-* @note GPIOD is only available on STM32F05xx, STM32F07xx and STM32F09xx
-* @note GPIOE is only available on STM32F07xx and STM32F09xx
-* @param GPIO_Pin: specifies the port bit to be locked.
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F0 family
+ * @param GPIO_Pin: specifies the port bits to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
@@ -493,7 +474,7 @@
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Apply lock key write sequence */
- tmp |= GPIO_Pin;
+ SET_BIT(tmp, GPIO_Pin);
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
@@ -514,7 +495,7 @@
}
/**
- * @brief This function handles EXTI interrupt request.
+ * @brief Handle EXTI interrupt request.
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
@@ -529,13 +510,13 @@
}
/**
- * @brief EXTI line detection callbacks.
+ * @brief EXTI line detection callback.
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_gpio.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -93,19 +93,9 @@
*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
-
-/** @defgroup GPIO_pin_actions GPIO pin actions
- * @{
- */
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-/**
- * @}
- */
-
/** @defgroup GPIO_pins GPIO pins
* @{
*/
@@ -128,8 +118,6 @@
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
-
-#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK) != (uint32_t)0x00)
/**
* @}
*/
@@ -149,30 +137,13 @@
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
-
-#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
-
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
- ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
- ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
- ((MODE) == GPIO_MODE_AF_PP) ||\
- ((MODE) == GPIO_MODE_AF_OD) ||\
- ((MODE) == GPIO_MODE_IT_RISING) ||\
- ((MODE) == GPIO_MODE_IT_FALLING) ||\
- ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING) ||\
- ((MODE) == GPIO_MODE_EVT_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_ANALOG))
-
/**
* @}
*/
@@ -185,8 +156,6 @@
#define GPIO_SPEED_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */
#define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \
- ((SPEED) == GPIO_SPEED_HIGH))
/**
* @}
*/
@@ -198,9 +167,6 @@
#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
-
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
- ((PULL) == GPIO_PULLDOWN))
/**
* @}
*/
@@ -210,13 +176,12 @@
*/
/* Exported macro ------------------------------------------------------------*/
-
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/
/**
- * @brief Checks whether the specified EXTI line flag is set or not.
+ * @brief Check whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__: specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
@@ -224,7 +189,7 @@
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
/**
- * @brief Clears the EXTI's line pending flags.
+ * @brief Clear the EXTI's line pending flags.
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
@@ -232,7 +197,7 @@
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
/**
- * @brief Checks whether the specified EXTI line is asserted or not.
+ * @brief Check whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
@@ -240,7 +205,7 @@
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
/**
- * @brief Clears the EXTI's line pending bits.
+ * @brief Clear the EXTI's line pending bits.
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
@@ -248,7 +213,7 @@
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
/**
- * @brief Generates a Software interrupt on selected EXTI line.
+ * @brief Generate a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None
@@ -259,7 +224,39 @@
* @}
*/
-/* Include GPIO HAL Extension module */
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)
+
+#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
+ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
+ ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
+ ((__MODE__) == GPIO_MODE_AF_PP) ||\
+ ((__MODE__) == GPIO_MODE_AF_OD) ||\
+ ((__MODE__) == GPIO_MODE_IT_RISING) ||\
+ ((__MODE__) == GPIO_MODE_IT_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_EVT_RISING) ||\
+ ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((__MODE__) == GPIO_MODE_ANALOG))
+
+#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_LOW) ||\
+ ((__SPEED__) == GPIO_SPEED_MEDIUM) ||\
+ ((__SPEED__) == GPIO_SPEED_HIGH))
+
+#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
+ ((__PULL__) == GPIO_PULLUP) || \
+ ((__PULL__) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/* Include GPIO HAL Extended module */
#include "stm32f0xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/
@@ -315,4 +312,3 @@
#endif /* __STM32F0xx_HAL_GPIO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_gpio_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_gpio_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @defgroup GPIOEx GPIOEx Extended HAL module driver
+/** @defgroup GPIOEx GPIOEx
* @{
*/
@@ -82,6 +82,7 @@
#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< AF1: USART1 Alternate Function mapping */
#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< AF1: EVENTOUT Alternate Function mapping */
#define GPIO_AF1_I2C1 ((uint8_t)0x01) /*!< AF1: I2C1 Alternate Function mapping */
+#define GPIO_AF1_IR ((uint8_t)0x01) /*!< AF1: IR Alternate Function mapping */
/* AF 2 */
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< AF2: TIM1 Alternate Function mapping */
@@ -613,6 +614,7 @@
/* AF 3 */
#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /*!< AF3: EVENTOUT Alternate Function mapping */
+#define GPIO_AF3_I2C1 ((uint8_t)0x03) /*!< AF3: I2C1 Alternate Function mapping */
#define GPIO_AF3_TIM15 ((uint8_t)0x03) /*!< AF3: TIM15 Alternate Function mapping */
/* AF 4 */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f0xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral State functions
+ * + Peripheral State and Errors functions
*
@verbatim
==============================================================================
@@ -21,32 +21,32 @@
(#) Declare a I2C_HandleTypeDef handle structure, for example:
I2C_HandleTypeDef hi2c;
- (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit ()API:
- (++) Enable the I2Cx interface clock
- (++) I2C pins configuration
+ (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+ (##) Enable the I2Cx interface clock
+ (##) I2C pins configuration
(+++) Enable the clock for the I2C GPIOs
(+++) Configure I2C pins as alternate function open-drain
- (++) NVIC configuration if you need to use interrupt process
+ (##) NVIC configuration if you need to use interrupt process
(+++) Configure the I2Cx interrupt priority
(+++) Enable the NVIC I2C IRQ Channel
- (++) DMA Configuration if you need to use DMA process
+ (##) DMA Configuration if you need to use DMA process
(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
(+++) Enable the DMAx interface clock using
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx channel
- (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
-
- (#) Configure the Communication Clock Timing, Own Address1, Master Adressing Mode, Dual Addressing mode,
+ (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+ the DMA Tx or Rx channel
+
+ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing Mode, Dual Addressing mode,
Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
- (#) Initialize the I2C registers by calling the HAL_I2C_Init() API:
- (++) These API s configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_I2C_MspInit(&hi2c) API.
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
- (#) For I2C IO and IO MEM operations, three modes of operations are available within this driver :
+ (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -66,70 +66,70 @@
*** Interrupt mode IO operation ***
===================================
[..]
- (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
- (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
- (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
- (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
- (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
- (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
- (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
- (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
+ (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
*** Interrupt mode IO MEM operation ***
=======================================
[..]
- (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
+ (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
HAL_I2C_Mem_Write_IT()
- (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
- (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
HAL_I2C_Mem_Read_IT()
- (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
*** DMA mode IO operation ***
==============================
[..]
- (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
+ (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
HAL_I2C_Master_Transmit_DMA()
- (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
- (+) Receive in master mode an amount of data in non blocking mode (DMA) using
+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
HAL_I2C_Master_Receive_DMA()
- (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
- (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
HAL_I2C_Slave_Transmit_DMA()
- (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
- (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
HAL_I2C_Slave_Receive_DMA()
- (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
*** DMA mode IO MEM operation ***
=================================
[..]
- (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
+ (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
HAL_I2C_Mem_Write_DMA()
- (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
- (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
HAL_I2C_Mem_Read_DMA()
- (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback()
*** I2C HAL driver macros list ***
@@ -137,12 +137,12 @@
[..]
Below the list of most used macros in I2C HAL driver.
- (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
- (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
- (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
- (+) __HAL_I2C_CLEAR_FLAG : Clears the specified I2C pending flag
- (+) __HAL_I2C_ENABLE_IT: Enables the specified I2C interrupt
- (+) __HAL_I2C_DISABLE_IT: Disables the specified I2C interrupt
+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not
+ (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
[..]
(@) You can refer to the I2C HAL driver header file for more useful macros
@@ -151,7 +151,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -185,7 +185,7 @@
* @{
*/
-/** @defgroup I2C I2C HAL module driver
+/** @defgroup I2C I2C
* @brief I2C HAL module driver
* @{
*/
@@ -230,9 +230,9 @@
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c);
@@ -246,7 +246,7 @@
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup I2C_Exported_Functions I2C Exported Functions
* @{
@@ -257,10 +257,10 @@
*
@verbatim
===============================================================================
- ##### Initialization and Configuration functions #####
+ ##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the I2Cx peripheral:
+ deinitialize the I2Cx peripheral:
(+) User must Implement HAL_I2C_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
@@ -277,7 +277,7 @@
(++) Nostretch mode
(+) Call the function HAL_I2C_DeInit() to restore the default configuration
- of the selected I2Cx periperal.
+ of the selected I2Cx peripheral.
@endverbatim
* @{
@@ -285,7 +285,7 @@
/**
* @brief Initializes the I2C according to the specified parameters
- * in the I2C_InitTypeDef and create the associated handle.
+ * in the I2C_InitTypeDef and initialize the associated handle.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
@@ -310,6 +310,9 @@
if(hi2c->State == HAL_I2C_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hi2c->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
}
@@ -365,7 +368,7 @@
}
/**
- * @brief DeInitializes the I2C peripheral.
+ * @brief DeInitialize the I2C peripheral.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
@@ -390,6 +393,7 @@
HAL_I2C_MspDeInit(hi2c);
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
hi2c->State = HAL_I2C_STATE_RESET;
/* Release Lock */
@@ -399,27 +403,27 @@
}
/**
- * @brief I2C MSP Init.
+ * @brief Initialize the I2C MSP.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspInit could be implemented in the user file
*/
}
/**
- * @brief I2C MSP DeInit
+ * @brief DeInitialize the I2C MSP.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspDeInit could be implemented in the user file
*/
}
@@ -439,7 +443,7 @@
This subsection provides a set of functions allowing to manage the I2C data
transfers.
- (#) There is two mode of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
after finishing transfer.
@@ -474,7 +478,7 @@
(++) HAL_I2C_Mem_Write_DMA()
(++) HAL_I2C_Mem_Read_DMA()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_I2C_MemTxCpltCallback()
(++) HAL_I2C_MemRxCpltCallback()
(++) HAL_I2C_MasterTxCpltCallback()
@@ -592,7 +596,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
@@ -706,7 +710,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
@@ -963,7 +967,7 @@
}
/**
- * @brief Transmit in master mode an amount of data in no-blocking mode with Interrupt
+ * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress: Target device address
@@ -1035,7 +1039,7 @@
}
/**
- * @brief Receive in master mode an amount of data in no-blocking mode with Interrupt
+ * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress: Target device address
@@ -1106,7 +1110,7 @@
}
/**
- * @brief Transmit in slave mode an amount of data in no-blocking mode with Interrupt
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData: Pointer to data buffer
@@ -1156,7 +1160,7 @@
}
/**
- * @brief Receive in slave mode an amount of data in no-blocking mode with Interrupt
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData: Pointer to data buffer
@@ -1206,7 +1210,7 @@
}
/**
- * @brief Transmit in master mode an amount of data in no-blocking mode with DMA
+ * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress: Target device address
@@ -1297,7 +1301,7 @@
}
/**
- * @brief Receive in master mode an amount of data in no-blocking mode with DMA
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress: Target device address
@@ -1378,7 +1382,7 @@
}
/**
- * @brief Transmit in slave mode an amount of data in no-blocking mode with DMA
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData: Pointer to data buffer
@@ -1464,7 +1468,7 @@
}
/**
- * @brief Receive in slave mode an amount of data in no-blocking mode with DMA
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData: Pointer to data buffer
@@ -1533,7 +1537,6 @@
return HAL_BUSY;
}
}
-
/**
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
@@ -1662,7 +1665,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
@@ -1800,7 +1803,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
@@ -1814,9 +1817,8 @@
return HAL_BUSY;
}
}
-
/**
- * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address
+ * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress: Target device address
@@ -1909,7 +1911,7 @@
}
/**
- * @brief Read an amount of data in no-blocking mode with Interrupt from a specific memory address
+ * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress: Target device address
@@ -1999,9 +2001,8 @@
return HAL_BUSY;
}
}
-
/**
- * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address
+ * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress: Target device address
@@ -2110,7 +2111,7 @@
}
/**
- * @brief Reads an amount of data in no-blocking mode with DMA from a specific memory address.
+ * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
* @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress: Target device address
@@ -2241,7 +2242,7 @@
do
{
/* Generate Start */
- hi2c->Instance->CR2 = __HAL_I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
+ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set or a NACK flag is set*/
@@ -2325,6 +2326,13 @@
return HAL_BUSY;
}
}
+/**
+ * @}
+ */
+
+/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
/**
* @brief This function handles I2C event interrupt request.
@@ -2408,7 +2416,7 @@
}
/* Call the Error Callback in case of Error detected */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
{
hi2c->State = HAL_I2C_STATE_READY;
@@ -2424,7 +2432,7 @@
*/
__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_TxCpltCallback could be implemented in the user file
*/
}
@@ -2437,7 +2445,7 @@
*/
__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_TxCpltCallback could be implemented in the user file
*/
}
@@ -2449,7 +2457,7 @@
*/
__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_TxCpltCallback could be implemented in the user file
*/
}
@@ -2462,7 +2470,7 @@
*/
__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_TxCpltCallback could be implemented in the user file
*/
}
@@ -2475,7 +2483,7 @@
*/
__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_TxCpltCallback could be implemented in the user file
*/
}
@@ -2488,7 +2496,7 @@
*/
__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_TxCpltCallback could be implemented in the user file
*/
}
@@ -2501,7 +2509,7 @@
*/
__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_ErrorCallback could be implemented in the user file
*/
}
@@ -2518,7 +2526,7 @@
##### Peripheral State and Errors functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -2526,20 +2534,22 @@
*/
/**
- * @brief Returns the I2C state.
- * @param hi2c : I2C handle
+ * @brief Return the I2C handle state.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @retval HAL state
*/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
{
+ /* Return I2C handle state */
return hi2c->State;
}
/**
-* @brief Return the I2C error code
-* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
+* @brief Return the I2C error code.
+ * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
-* @retval I2C Error Code
+ * @retval I2C Error Code
*/
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
{
@@ -2631,7 +2641,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
@@ -2738,7 +2748,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
@@ -2949,13 +2959,13 @@
if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
- hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
- hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_MSB(MemAddress);
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXIS flag is set */
if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
@@ -2971,7 +2981,7 @@
}
/* Send LSB of Memory Address */
- hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
}
/* Wait until TCR flag is set */
@@ -3014,13 +3024,13 @@
if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
- hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
}
- /* If Mememory address size is 16Bit */
+ /* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
- hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_MSB(MemAddress);
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXIS flag is set */
if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
@@ -3036,7 +3046,7 @@
}
/* Send LSB of Memory Address */
- hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress);
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
}
/* Wait until TC flag is set */
@@ -3092,7 +3102,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
@@ -3149,7 +3159,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
@@ -3183,7 +3193,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
@@ -3299,7 +3309,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
@@ -3362,7 +3372,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
@@ -3397,7 +3407,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
@@ -3514,7 +3524,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
@@ -3571,7 +3581,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
@@ -3605,7 +3615,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
@@ -3670,7 +3680,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
@@ -3733,7 +3743,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->XferCount = 0;
@@ -3767,7 +3777,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
@@ -3953,7 +3963,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State= HAL_I2C_STATE_READY;
@@ -4030,7 +4040,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_I2C_RESET_CR2(hi2c);
+ I2C_RESET_CR2(hi2c);
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
hi2c->State= HAL_I2C_STATE_READY;
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -81,11 +81,11 @@
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
- uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
- This parameter can be a value of @ref I2C_own_address2_masks. */
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+ This parameter can be a value of @ref I2C_own_address2_masks */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref I2C_general_call_addressing_mode. */
+ This parameter can be a value of @ref I2C_general_call_addressing_mode */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_nostretch_mode */
@@ -114,18 +114,32 @@
HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */
HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
-
}HAL_I2C_StateTypeDef;
/**
* @}
*/
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+ * @brief I2C Error Code definition
+ * @{
+ */
+#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
+#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
+#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< ACKF error */
+#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
+#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040) /*!< Size Management error */
+/**
+ * @}
+ */
+
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
-
typedef struct
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
@@ -146,8 +160,7 @@
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
- __IO uint32_t ErrorCode; /*!< I2C Error code
- This parameter can be a value of @ref I2C_Error */
+ __IO uint32_t ErrorCode; /*!< I2C Error code */
}I2C_HandleTypeDef;
/**
@@ -163,33 +176,11 @@
* @{
*/
-/** @defgroup I2C_Error I2C Error
- * @brief I2C Error
- * @{
- */
-
-#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
-#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
-#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< AF error */
-#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
-#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
-#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
-#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040) /*!< Size Management error */
-
-/**
- * @}
- */
-
-
/** @defgroup I2C_addressing_mode I2C addressing mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
-
-#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
- ((MODE) == I2C_ADDRESSINGMODE_10BIT))
/**
* @}
*/
@@ -197,12 +188,8 @@
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
* @{
*/
-
-#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
-#define I2C_DUALADDRESS_ENABLED I2C_OAR2_OA2EN
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \
- ((ADDRESS) == I2C_DUALADDRESS_ENABLED))
+#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
@@ -210,7 +197,6 @@
/** @defgroup I2C_own_address2_masks I2C own address2 masks
* @{
*/
-
#define I2C_OA2_NOMASK ((uint8_t)0x00)
#define I2C_OA2_MASK01 ((uint8_t)0x01)
#define I2C_OA2_MASK02 ((uint8_t)0x02)
@@ -219,15 +205,6 @@
#define I2C_OA2_MASK05 ((uint8_t)0x05)
#define I2C_OA2_MASK06 ((uint8_t)0x06)
#define I2C_OA2_MASK07 ((uint8_t)0x07)
-
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
- ((MASK) == I2C_OA2_MASK01) || \
- ((MASK) == I2C_OA2_MASK02) || \
- ((MASK) == I2C_OA2_MASK03) || \
- ((MASK) == I2C_OA2_MASK04) || \
- ((MASK) == I2C_OA2_MASK05) || \
- ((MASK) == I2C_OA2_MASK06) || \
- ((MASK) == I2C_OA2_MASK07))
/**
* @}
*/
@@ -235,11 +212,8 @@
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
* @{
*/
-#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000)
-#define I2C_GENERALCALL_ENABLED I2C_CR1_GCEN
-
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \
- ((CALL) == I2C_GENERALCALL_ENABLED))
+#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
+#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
@@ -247,11 +221,8 @@
/** @defgroup I2C_nostretch_mode I2C nostretch mode
* @{
*/
-#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
-#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
-
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \
- ((STRETCH) == I2C_NOSTRETCH_ENABLED))
+#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
@@ -261,9 +232,6 @@
*/
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)
-
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
- ((SIZE) == I2C_MEMADD_SIZE_16BIT))
/**
* @}
*/
@@ -271,14 +239,9 @@
/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition
* @{
*/
-
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE ((uint32_t)0x00000000)
-
-#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
- ((MODE) == I2C_AUTOEND_MODE) || \
- ((MODE) == I2C_SOFTEND_MODE))
/**
* @}
*/
@@ -286,17 +249,10 @@
/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition
* @{
*/
-
#define I2C_NO_STARTSTOP ((uint32_t)0x00000000)
#define I2C_GENERATE_STOP I2C_CR2_STOP
#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE I2C_CR2_START
-
-#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
- ((REQUEST) == I2C_GENERATE_START_READ) || \
- ((REQUEST) == I2C_GENERATE_START_WRITE) || \
- ((REQUEST) == I2C_NO_STARTSTOP))
-
/**
* @}
*/
@@ -323,7 +279,6 @@
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
-
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
@@ -354,107 +309,117 @@
* @{
*/
-/** @brief Reset I2C handle state
- * @param __HANDLE__: I2C handle.
+/** @brief Reset I2C handle state.
+ * @param __HANDLE__: specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-/** @brief Enables or disables the specified I2C interrupts.
+/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__: specifies the I2C Handle.
- * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * @param __INTERRUPT__: specifies the interrupt source to enable.
* This parameter can be one of the following values:
- * @arg I2C_IT_ERRI: Errors interrupt enable
- * @arg I2C_IT_TCI: Transfer complete interrupt enable
+ * @arg I2C_IT_ERRI: Errors interrupt enable
+ * @arg I2C_IT_TCI: Transfer complete interrupt enable
* @arg I2C_IT_STOPI: STOP detection interrupt enable
* @arg I2C_IT_NACKI: NACK received interrupt enable
* @arg I2C_IT_ADDRI: Address match interrupt enable
- * @arg I2C_IT_RXI: RX interrupt enable
- * @arg I2C_IT_TXI: TX interrupt enable
+ * @arg I2C_IT_RXI: RX interrupt enable
+ * @arg I2C_IT_TXI: TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-
-/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
+
+/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__: specifies the I2C Handle.
- * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
- * @param __INTERRUPT__: specifies the I2C interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2C_IT_ERRI: Errors interrupt enable
- * @arg I2C_IT_TCI: Transfer complete interrupt enable
+ * @param __INTERRUPT__: specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_ERRI: Errors interrupt enable
+ * @arg I2C_IT_TCI: Transfer complete interrupt enable
* @arg I2C_IT_STOPI: STOP detection interrupt enable
* @arg I2C_IT_NACKI: NACK received interrupt enable
* @arg I2C_IT_ADDRI: Address match interrupt enable
- * @arg I2C_IT_RXI: RX interrupt enable
- * @arg I2C_IT_TXI: TX interrupt enable
+ * @arg I2C_IT_RXI: RX interrupt enable
+ * @arg I2C_IT_TXI: TX interrupt enable
*
- * @retval The new state of __IT__ (TRUE or FALSE).
+ * @retval None
+ */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified I2C interrupt source is enabled or not.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * @param __INTERRUPT__: specifies the I2C interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_ERRI: Errors interrupt enable
+ * @arg I2C_IT_TCI: Transfer complete interrupt enable
+ * @arg I2C_IT_STOPI: STOP detection interrupt enable
+ * @arg I2C_IT_NACKI: NACK received interrupt enable
+ * @arg I2C_IT_ADDRI: Address match interrupt enable
+ * @arg I2C_IT_RXI: RX interrupt enable
+ * @arg I2C_IT_TXI: TX interrupt enable
+ *
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-/** @brief Checks whether the specified I2C flag is set or not.
+/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__: specifies the I2C Handle.
- * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
- * @arg I2C_FLAG_TXE: Transmit data register empty
- * @arg I2C_FLAG_TXIS: Transmit interrupt status
- * @arg I2C_FLAG_RXNE: Receive data register not empty
- * @arg I2C_FLAG_ADDR: Address matched (slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure received flag
- * @arg I2C_FLAG_STOPF: STOP detection flag
- * @arg I2C_FLAG_TC: Transfer complete (master mode)
- * @arg I2C_FLAG_TCR: Transfer complete reload
- * @arg I2C_FLAG_BERR: Bus error
- * @arg I2C_FLAG_ARLO: Arbitration lost
- * @arg I2C_FLAG_OVR: Overrun/Underrun
- * @arg I2C_FLAG_PECERR: PEC error in reception
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_FLAG_ALERT: SMBus alert
- * @arg I2C_FLAG_BUSY: Bus busy
- * @arg I2C_FLAG_DIR: Transfer direction (slave mode)
+ * @arg I2C_FLAG_TXE: Transmit data register empty
+ * @arg I2C_FLAG_TXIS: Transmit interrupt status
+ * @arg I2C_FLAG_RXNE: Receive data register not empty
+ * @arg I2C_FLAG_ADDR: Address matched (slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure received flag
+ * @arg I2C_FLAG_STOPF: STOP detection flag
+ * @arg I2C_FLAG_TC: Transfer complete (master mode)
+ * @arg I2C_FLAG_TCR: Transfer complete reload
+ * @arg I2C_FLAG_BERR: Bus error
+ * @arg I2C_FLAG_ARLO: Arbitration lost
+ * @arg I2C_FLAG_OVR: Overrun/Underrun
+ * @arg I2C_FLAG_PECERR: PEC error in reception
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+ * @arg I2C_FLAG_ALERT: SMBus alert
+ * @arg I2C_FLAG_BUSY: Bus busy
+ * @arg I2C_FLAG_DIR: Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+#define I2C_FLAG_MASK ((uint32_t)0x0001FFFF)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
-/** @brief Clears the I2C pending flags which are cleared by writing 1 in a specific bit.
+/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__: specifies the I2C Handle.
- * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
- * @arg I2C_FLAG_ADDR: Address matched (slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_STOPF: STOP detection flag
- * @arg I2C_FLAG_BERR: Bus error
- * @arg I2C_FLAG_ARLO: Arbitration lost
- * @arg I2C_FLAG_OVR: Overrun/Underrun
- * @arg I2C_FLAG_PECERR: PEC error in reception
+ * @arg I2C_FLAG_ADDR: Address matched (slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure received flag
+ * @arg I2C_FLAG_STOPF: STOP detection flag
+ * @arg I2C_FLAG_BERR: Bus error
+ * @arg I2C_FLAG_ARLO: Arbitration lost
+ * @arg I2C_FLAG_OVR: Overrun/Underrun
+ * @arg I2C_FLAG_PECERR: PEC error in reception
* @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_FLAG_ALERT: SMBus alert
+ * @arg I2C_FLAG_ALERT: SMBus alert
*
* @retval None
*/
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK))
-
-#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
-#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
-
-#define __HAL_I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+/** @brief Enable the specified I2C peripheral.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-#define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
-#define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+/** @brief Disable the specified I2C peripheral.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * @retval None
+ */
+#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-#define __HAL_I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
/**
* @}
*/
@@ -470,13 +435,11 @@
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-
-/* Initialization/de-initialization functions **********************************/
+/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-
/**
* @}
*/
@@ -484,9 +447,7 @@
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
-
-/* IO operation functions *****************************************************/
-
+/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -511,7 +472,13 @@
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+/**
+ * @}
+ */
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
@@ -522,7 +489,6 @@
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-
/**
* @}
*/
@@ -530,8 +496,7 @@
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
* @{
*/
-
-/* Peripheral State and Errors functions **************************************/
+/* Peripheral State and Errors functions *************************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
@@ -543,6 +508,76 @@
* @}
*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+ * @{
+ */
+
+#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
+ ((MASK) == I2C_OA2_MASK01) || \
+ ((MASK) == I2C_OA2_MASK02) || \
+ ((MASK) == I2C_OA2_MASK03) || \
+ ((MASK) == I2C_OA2_MASK04) || \
+ ((MASK) == I2C_OA2_MASK05) || \
+ ((MASK) == I2C_OA2_MASK06) || \
+ ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
+ ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
+ ((MODE) == I2C_AUTOEND_MODE) || \
+ ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
+ ((REQUEST) == I2C_GENERATE_START_READ) || \
+ ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+ ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32l4xx_hal_i2c.c file */
+/**
+ * @}
+ */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,19 +2,19 @@
******************************************************************************
* @file stm32f0xx_hal_i2c_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
- * @brief I2C Extension HAL module driver.
+ * @version V1.3.0
+ * @date 26-June-2015
+ * @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of I2C extension peripheral:
- * + Extension features functions
+ * functionalities of I2C Extended peripheral:
+ * + Extended features functions
*
@verbatim
==============================================================================
- ##### I2C peripheral extension features #####
+ ##### I2C peripheral Extended features #####
==============================================================================
- [..] Comparing to other previous devices, the I2C interface for STM32F0XX
+ [..] Comparing to other previous devices, the I2C interface for STM32F0xx
devices contains the following additional features
(+) Possibility to disable or enable Analog Noise Filter
@@ -24,17 +24,19 @@
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure Noise Filter
- (#) Configure I2C Analog noise filter using the function HAL_I2CEx_AnalogFilter_Config()
- (#) Configure I2C Digital noise filter using the function HAL_I2CEx_DigitalFilter_Config()
- (#) Configure the enabling or disabling of I2C Wake Up Mode using the functions :
+ (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+ (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+ (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
(++) HAL_I2CEx_EnableWakeUp()
(++) HAL_I2CEx_DisableWakeUp()
-
+ (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+ (++) HAL_I2CEx_EnableFastModePlus()
+ (++) HAL_I2CEx_DisbleFastModePlus()
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -68,7 +70,7 @@
* @{
*/
-/** @defgroup I2CEx I2CEx Extended HAL module driver
+/** @defgroup I2CEx I2CEx
* @brief I2C Extended HAL module driver
* @{
*/
@@ -82,7 +84,7 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup I2CEx_Exported_Functions I2CEx Exported Functions
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
@@ -91,7 +93,7 @@
*
@verbatim
===============================================================================
- ##### Extension features functions #####
+ ##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
@@ -107,7 +109,7 @@
* @param AnalogFilter : new state of the Analog filter.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
@@ -150,7 +152,7 @@
* @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg = 0;
@@ -272,6 +274,43 @@
return HAL_OK;
}
#endif /* !(STM32F030x6) && !(STM32F030x8) && !(STM32F070x6) && !(STM32F070xB) && !(STM32F030xC) */
+
+/**
+ * @brief Enable the I2C fast mode plus driving capability.
+ * @param ConfigFastModePlus: selects the pin.
+ * This parameter can be one of the @ref I2CEx_FastModePlus values
+ * @retval None
+ */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Enable fast mode plus driving capability for selected pin */
+ SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the I2C fast mode plus driving capability.
+ * @param ConfigFastModePlus: selects the pin.
+ * This parameter can be one of the @ref I2CEx_FastModePlus values
+ * @retval None
+ */
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ /* Check the parameter */
+ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+ /* Enable SYSCFG clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* Disable fast mode plus driving capability for selected pin */
+ CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2c_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_i2c_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
- * @brief Header file of I2C HAL Extension module.
+ * @version V1.3.0
+ * @date 26-June-2015
+ * @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @addtogroup I2CEx I2CEx Extended HAL module driver
+/** @addtogroup I2CEx I2CEx
* @{
*/
@@ -64,23 +64,55 @@
/** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter
* @{
*/
-#define I2C_ANALOGFILTER_ENABLED ((uint32_t)0x00000000)
-#define I2C_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF
-
-#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLED) || \
- ((FILTER) == I2C_ANALOGFILTER_DISABLED))
+#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
+#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
-/** @defgroup I2CEx_Digital_Filter I2CEx Digital Filter
+/** @defgroup I2CEx_FastModePlus I2CEx Fast Mode Plus
* @{
*/
-#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx)
+#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */
+#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */
+#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */
+#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */
+#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */
+#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */
+#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */
+#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable Fast Mode Plus on I2C2 pins */
+#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */
+#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */
+#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */
+#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */
+#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */
+#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable Fast Mode Plus on I2C2 pins */
+#elif defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F030xC)
+#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */
+#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */
+#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */
+#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */
+#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */
+#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */
+#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */
+#elif defined(STM32F070xB)
+#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */
+#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */
+#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */
+#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */
+#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */
+#else /* defined(STM32F030x8) || defined(STM32F051xx) || defined(STM32F058xx) */
+#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */
+#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */
+#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */
+#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */
+#endif
/**
* @}
*/
-
+
/**
* @}
*/
@@ -98,17 +130,78 @@
*/
/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
-HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c);
#endif /* !(STM32F030x6) && !(STM32F030x8) && !(STM32F070x6) && !(STM32F070xB) && !(STM32F030xC) */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+ * @{
+ */
/**
* @}
*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+ * @{
+ */
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2))
+#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2))
+#elif defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F030xC)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1))
+#elif defined(STM32F070xB)
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1))
+#else /* defined(STM32F030x8) || defined(STM32F051xx) || defined(STM32F058xx) */
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9))
+#endif
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f0xx_hal_i2c_ex.c file */
/**
* @}
*/
@@ -120,7 +213,16 @@
/**
* @}
*/
-
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -108,7 +108,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -150,7 +150,7 @@
* @{
*/
-/** @defgroup I2S I2S HAL module driver
+/** @defgroup I2S I2S
* @brief I2S HAL module driver
* @{
*/
@@ -238,6 +238,9 @@
if(hi2s->State == HAL_I2S_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hi2s->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2S_MspInit(hi2s);
}
@@ -982,18 +985,18 @@
hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
- /* Disable the I2S DMA channel */
- __HAL_DMA_DISABLE(hi2s->hdmatx);
- __HAL_DMA_DISABLE(hi2s->hdmarx);
-
/* Abort the I2S DMA tx channel */
if(hi2s->hdmatx != NULL)
{
+ /* Disable the I2S DMA channel */
+ __HAL_DMA_DISABLE(hi2s->hdmatx);
HAL_DMA_Abort(hi2s->hdmatx);
}
/* Abort the I2S DMA rx channel */
if(hi2s->hdmarx != NULL)
{
+ /* Disable the I2S DMA channel */
+ __HAL_DMA_DISABLE(hi2s->hdmarx);
HAL_DMA_Abort(hi2s->hdmarx);
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h Mon Sep 28 10:30:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.h Mon Sep 28 10:45:10 2015 +0100 @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f0xx_hal_i2s.h * @author MCD Application Team - * @version V1.2.0 - * @date 11-December-2014 + * @version V1.3.0 + * @date 26-June-2015 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,106 +2,116 @@
******************************************************************************
* @file stm32f0xx_hal_irda.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief IRDA HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the IrDA (Infrared Data Association) Peripheral
+ * This file provides firmware functions to manage the following
+ * functionalities of the IrDA (Infrared Data Association) Peripheral
* (IRDA)
- * + Initialization and de-initialization function
- * + IO operation function
- * + Peripheral Control function
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ * + Peripheral Control functions
*
- *
- @verbatim
- ===============================================================================
+ @verbatim
+ ==============================================================================
##### How to use this driver #####
- ===============================================================================
- [..]
+ ==============================================================================
+ [..]
The IRDA HAL driver can be used as follows:
-
- (#) Declare a IRDA_HandleTypeDef handle structure.
- (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
- (##) Enable the USARTx interface clock.
- (##) IRDA pins configuration:
- (+++) Enable the clock for the IRDA GPIOs.
- (+++) Configure these IRDA pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
- and HAL_IRDA_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
+
+ (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
+ (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
+ in setting the associated USART or UART in IRDA mode:
+ (++) Enable the USARTx/UARTx interface clock.
+ (++) USARTx/UARTx pins configuration:
+ (+++) Enable the clock for the USARTx/UARTx GPIOs.
+ (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
+ (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
+ and HAL_IRDA_Receive_IT() APIs):
+ (+++) Configure the USARTx/UARTx interrupt priority.
+ (+++) Enable the NVIC USARTx/UARTx IRQ handle.
+ (+++) The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+ (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
and HAL_IRDA_Receive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx channel.
(+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
- the normal or low power mode and the clock prescaler in the hirda Init structure.
+ the normal or low power mode and the clock prescaler in the hirda handle Init structure.
(#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
- (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_IRDA_MspInit() API.
-
- -@@- The specific IRDA interrupts (Transmission complete interrupt,
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_IRDA_MspInit() API.
+
+ -@@- The specific IRDA interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
(#) Three operation modes are available within this driver :
-
+
*** Polling mode IO operation ***
=================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
(+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
-
- *** Interrupt mode IO operation ***
+
+ *** Interrupt mode IO operation ***
===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
- (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
- (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
- (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_IRDA_ErrorCallback
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
- *** DMA mode IO operation ***
+ *** DMA mode IO operation ***
==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
- (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
- (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
- (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_IRDA_ErrorCallback
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+ (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
+ (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+ (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
+ (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
+ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
*** IRDA HAL driver macros list ***
====================================
[..]
Below the list of most used macros in IRDA HAL driver.
-
- (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
- (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+
+ (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
+ (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
(+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
(+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
(+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
(+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
-
- [..]
+ (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
+
+ [..]
(@) You can refer to the IRDA HAL driver header file for more useful macros
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -125,7 +135,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -133,107 +143,122 @@
#ifdef HAL_IRDA_MODULE_ENABLED
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
-/** @defgroup IRDA IRDA HAL module driver
+/** @defgroup IRDA IRDA
* @brief HAL IRDA module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup IRDA_Private_Constants IRDA Private Constants
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
* @{
*/
-#define TEACK_REACK_TIMEOUT 1000
+#define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */
#define IRDA_TXDMA_TIMEOUTVALUE 22000
#define IRDA_TIMEOUT_VALUE 22000
#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
- | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))
+ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @defgroup IRDA_Private_Functions IRDA Private Functions
+/** @addtogroup IRDA_Private_Functions IRDA Private Functions
* @{
*/
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
/**
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
* @{
*/
-/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
==============================================================================
- ##### Initialization and Configuration functions #####
+ ##### Initialization and Configuration functions #####
==============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USARTx
- in IRDA mode.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits)
- or by the M1 and M0 bits (7-bit, 8-bit or 9-bit),
- the possible IRDA frame formats are as listed in the following table:
- +---------------------------------------------------------------+
- | M bit | PCE bit | IRDA frame |
- |-----------|-----------|---------------------------------------|
- | 0 | 0 | | SB | 8-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7-bit data | PB | STB | |
- |-----------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8-bit data | PB | STB | |
- +---------------------------------------------------------------+
- | M1M0 bits | PCE bit | IRDA frame |
- |-----------------------|---------------------------------------|
- | 10 | 0 | | SB | 7-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 10 | 1 | | SB | 6-bit data | PB | STB | |
- +---------------------------------------------------------------+
-
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx
+ in asynchronous IRDA mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ According to device capability (support or not of 7-bit word length),
+ frame length is either defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
+ Possible IRDA frame formats are as listed in the following table:
+
+ (+++) Table 1. IRDA frame format.
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M bit | PCE bit | IRDA frame |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | | SB | 8-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | | SB | 9-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M1 bit | M0 bit | PCE bit | IRDA frame |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
+
(++) Power mode
- (++) Prescaler setting
+ (++) Prescaler setting
(++) Receiver/transmitter modes
- [..]
- The HAL_IRDA_Init() function follows IRDA configuration procedures
- (details for the procedures are available in reference manual).
+ [..]
+ The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
+ (details for the procedures are available in reference manual).
@endverbatim
* @{
*/
/**
- * @brief Initializes the IRDA mode according to the specified
- * parameters in the IRDA_InitTypeDef and creates the associated handle .
- * @param hirda: IRDA handle
+ * @brief Initialize the IRDA mode according to the specified
+ * parameters in the IRDA_InitTypeDef and initialize the associated handle.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
@@ -243,46 +268,50 @@
{
return HAL_ERROR;
}
-
+
/* Check the USART/UART associated to the IRDA handle */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-
+
if(hirda->State == HAL_IRDA_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ hirda->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK */
HAL_IRDA_MspInit(hirda);
}
-
+
hirda->State = HAL_IRDA_STATE_BUSY;
-
+
/* Disable the Peripheral to update the configuration registers */
__HAL_IRDA_DISABLE(hirda);
-
+
/* Set the IRDA Communication parameters */
if (IRDA_SetConfig(hirda) == HAL_ERROR)
{
return HAL_ERROR;
- }
-
- /* In IRDA mode, the following bits must be kept cleared:
+ }
+
+ /* In IRDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- SCEN and HDSEL bits in the USART_CR3 register.*/
- hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP);
- hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
-
+ hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP);
+ hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
+
/* set the UART/USART in IRDA mode */
- hirda->Instance->CR3 |= USART_CR3_IREN;
-
+ hirda->Instance->CR3 |= USART_CR3_IREN;
+
/* Enable the Peripheral */
__HAL_IRDA_ENABLE(hirda);
-
+
/* TEACK and/or REACK to check before moving hirda->State to Ready */
return (IRDA_CheckIdleState(hirda));
}
/**
- * @brief DeInitializes the IRDA peripheral
- * @param hirda: IRDA handle
+ * @brief DeInitialize the IRDA peripheral.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
@@ -292,140 +321,147 @@
{
return HAL_ERROR;
}
-
+
/* Check the USART/UART associated to the IRDA handle */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
hirda->State = HAL_IRDA_STATE_BUSY;
-
+
/* DeInit the low level hardware */
HAL_IRDA_MspDeInit(hirda);
/* Disable the Peripheral */
__HAL_IRDA_DISABLE(hirda);
-
+
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->State = HAL_IRDA_STATE_RESET;
-
+
/* Process Unlock */
__HAL_UNLOCK(hirda);
-
+
return HAL_OK;
}
/**
- * @brief IRDA MSP Init
- * @param hirda: IRDA handle
+ * @brief Initialize the IRDA MSP.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
{
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_MspInit can be implemented in the user file
- */
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspInit can be implemented in the user file
+ */
}
/**
- * @brief IRDA MSP DeInit
- * @param hirda: IRDA handle
+ * @brief DeInitialize the IRDA MSP.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
{
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_MspDeInit can be implemented in the user file
- */
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspDeInit can be implemented in the user file
+ */
}
/**
* @}
*/
-/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
- * @brief IRDA Transmit and Receive functions
+/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
+ * @brief IRDA Transmit and Receive functions
*
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
[..]
This subsection provides a set of functions allowing to manage the IRDA data transfers.
[..]
IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
- on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
+ on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
(#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) Non Blocking mode: The communication is performed using Interrupts
- or DMA, these API s return the HAL status.
- The end of the data processing will be indicated through the
- dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the Transmit or Receive process
- The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
+ (++) Blocking mode: the communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: the communication is performed using Interrupts
+ or DMA, these API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
- (#) Blocking mode API s are :
+ (#) Blocking mode APIs are :
(++) HAL_IRDA_Transmit()
- (++) HAL_IRDA_Receive()
-
- (#) Non Blocking mode API s with Interrupt are :
+ (++) HAL_IRDA_Receive()
+
+ (#) Non Blocking mode APIs with Interrupt are :
(++) HAL_IRDA_Transmit_IT()
(++) HAL_IRDA_Receive_IT()
(++) HAL_IRDA_IRQHandler()
- (++) IRDA_Transmit_IT()
- (++) IRDA_Receive_IT()
(#) Non Blocking mode functions with DMA are :
(++) HAL_IRDA_Transmit_DMA()
(++) HAL_IRDA_Receive_DMA()
+ (++) HAL_IRDA_DMAPause()
+ (++) HAL_IRDA_DMAResume()
+ (++) HAL_IRDA_DMAStop()
(#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
+ (++) HAL_IRDA_TxHalfCpltCallback()
(++) HAL_IRDA_TxCpltCallback()
+ (++) HAL_IRDA_RxHalfCpltCallback()
(++) HAL_IRDA_RxCpltCallback()
(++) HAL_IRDA_ErrorCallback()
-
+
@endverbatim
* @{
*/
/**
- * @brief Send an amount of data in blocking mode
- * @param hirda: IRDA handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout: Duration of the timeout
+ * @brief Send an amount of data in blocking mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer.
+ * @param Size: Amount of data to be sent.
+ * @param Timeout: Specify timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
-
- if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
+ uint16_t* tmp;
+
+ if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hirda);
+
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
}
else
{
hirda->State = HAL_IRDA_STATE_BUSY_TX;
- }
-
+ }
+
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
while(hirda->TxXferCount > 0)
@@ -439,79 +475,81 @@
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
tmp = (uint16_t*) pData;
- hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- pData += 2;
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ pData +=2;
}
else
{
- hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
}
}
if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
- {
+ {
return HAL_TIMEOUT;
- }
+ }
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_RX;
}
else
{
hirda->State = HAL_IRDA_STATE_READY;
- }
-
+ }
+
/* Process Unlocked */
__HAL_UNLOCK(hirda);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Receive an amount of data in blocking mode
- * @param hirda: IRDA handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout: Duration of the timeout
+ * @brief Receive an amount of data in blocking mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer.
+ * @param Size: Amount of data to be received.
+ * @param Timeout: Specify timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
+{
uint16_t* tmp;
uint16_t uhMask;
-
- if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
- {
- if((pData == NULL) || (Size == 0))
+
+ if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hirda);
+
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
}
else
{
hirda->State = HAL_IRDA_STATE_BUSY_RX;
- }
-
- hirda->RxXferSize = Size;
+ }
+
+ hirda->RxXferSize = Size;
hirda->RxXferCount = Size;
- /* Computation of the mask to apply to the RDR register
+ /* Computation of the mask to apply to the RDR register
of the UART associated to the IRDA */
- __HAL_IRDA_MASK_COMPUTATION(hirda);
+ IRDA_MASK_COMPUTATION(hirda);
uhMask = hirda->Mask;
/* Check data remaining to be received */
@@ -520,7 +558,7 @@
hirda->RxXferCount--;
if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
+ {
return HAL_TIMEOUT;
}
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
@@ -531,11 +569,11 @@
}
else
{
- *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
}
}
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
@@ -543,43 +581,157 @@
{
hirda->State = HAL_IRDA_STATE_READY;
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(hirda);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Send an amount of data in interrupt mode
- * @param hirda: IRDA handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @brief Send an amount of data in interrupt mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer.
+ * @param Size: Amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
- if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
+ if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hirda);
-
+
hirda->pTxBuffPtr = pData;
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+ /* Enable the IRDA Transmit Data Register Empty Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer.
+ * @param Size: Amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ /* Computation of the mask to apply to the RDR register
+ of the UART associated to the IRDA */
+ IRDA_MASK_COMPUTATION(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Data Register not empty Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
+
+ /* Enable the IRDA Parity Error Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
}
@@ -588,52 +740,67 @@
hirda->State = HAL_IRDA_STATE_BUSY_TX;
}
- /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
-
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+
+ /* Enable the IRDA transmit DMA channel */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ hirda->Instance->CR3 |= USART_CR3_DMAT;
+
/* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Transmit Data Register Empty Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
-
+ __HAL_UNLOCK(hirda);
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Receive an amount of data in interrupt mode
- * @param hirda: IRDA handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
+ * @brief Receive an amount of data in DMA mode.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData: Pointer to data buffer.
+ * @param Size: Amount of data to be received.
+ * @note When the IRDA parity is enabled (PCE = 1) the received data contains
+ * the parity bit (MSB position).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
- __HAL_LOCK(hirda);
-
+ __HAL_LOCK(hirda);
+
hirda->pRxBuffPtr = pData;
hirda->RxXferSize = Size;
- hirda->RxXferCount = Size;
- /* Computation of the mask to apply to the RDR register
- of the UART associated to the IRDA */
- __HAL_IRDA_MASK_COMPUTATION(hirda);
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
{
hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
}
@@ -641,127 +808,13 @@
{
hirda->State = HAL_IRDA_STATE_BUSY_RX;
}
-
- /* Enable the IRDA Parity Error Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
-
- /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Data Register not empty Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @brief Send an amount of data in DMA mode
- * @param hirda: IRDA handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- uint32_t *tmp;
-
- if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX))
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pTxBuffPtr = pData;
- hirda->TxXferSize = Size;
- hirda->TxXferCount = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX;
- }
-
- /* Set the IRDA DMA transfer complete callback */
- hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
-
- /* Set the DMA error callback */
- hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
-
- /* Enable the IRDA transmit DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the IRDA CR3 register */
- hirda->Instance->CR3 |= USART_CR3_DMAT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in DMA mode
- * @param hirda: IRDA handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @note When the IRDA parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- uint32_t *tmp;
-
- if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX))
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pRxBuffPtr = pData;
- hirda->RxXferSize = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_BUSY_RX;
- }
-
/* Set the IRDA DMA transfer complete callback */
hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
-
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
+
/* Set the DMA error callback */
hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
@@ -769,400 +822,326 @@
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the IRDA CR3 register */
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
hirda->Instance->CR3 |= USART_CR3_DMAR;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hirda);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
-
+
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ /* Disable the IRDA DMA Tx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ /* Disable the IRDA DMA Rx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+ else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ /* Disable the IRDA DMA Tx & Rx requests */
+ CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
/**
- * @brief This function handles IRDA interrupt request.
- * @param hirda: IRDA handle
+ * @brief Resume the DMA Transfer.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ {
+ /* Enable the IRDA DMA Tx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+ /* Enable the IRDA DMA Rx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+ else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
+ /* Enable the IRDA DMA Tx & Rx request */
+ SET_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_ERROR;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
+ HAL_IRDA_TxHalfCpltCallback() / HAL_IRDA_RxHalfCpltCallback():
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
+ generated if the DMA transfer interruption occurs at the middle or at the end of the stream
+ and the corresponding call back is executed.
+ */
+
+ /* Disable the IRDA Tx/Rx DMA requests */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA tx channel */
+ if(hirda->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ /* Abort the IRDA DMA rx channel */
+ if(hirda->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+
+ hirda->State = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Handle IRDA interrupt request.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
{
/* IRDA parity error interrupt occurred -------------------------------------*/
if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET))
- {
+ {
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
/* Set the IRDA state ready to be able to start again the process */
hirda->State = HAL_IRDA_STATE_READY;
}
-
- /* IRDA frame error interrupt occured --------------------------------------*/
+
+ /* IRDA frame error interrupt occurred --------------------------------------*/
if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
- {
+ {
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
/* Set the IRDA state ready to be able to start again the process */
hirda->State = HAL_IRDA_STATE_READY;
}
-
- /* IRDA noise error interrupt occured --------------------------------------*/
+
+ /* IRDA noise error interrupt occurred --------------------------------------*/
if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
- {
+ {
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
- hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+ hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
/* Set the IRDA state ready to be able to start again the process */
hirda->State = HAL_IRDA_STATE_READY;
}
-
- /* IRDA Over-Run interrupt occured -----------------------------------------*/
+
+ /* IRDA Over-Run interrupt occurred -----------------------------------------*/
if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
- {
+ {
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
- hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+ hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
/* Set the IRDA state ready to be able to start again the process */
hirda->State = HAL_IRDA_STATE_READY;
}
-
+
/* Call IRDA Error Call back function if need be --------------------------*/
if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
{
HAL_IRDA_ErrorCallback(hirda);
- }
+ }
/* IRDA in mode Receiver ---------------------------------------------------*/
if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET))
- {
+ {
IRDA_Receive_IT(hirda);
/* Clear RXNE interrupt flag */
__HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
}
-
+
/* IRDA in mode Transmitter ------------------------------------------------*/
if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET))
{
IRDA_Transmit_IT(hirda);
- }
-
+ }
+
/* IRDA in mode Transmitter (transmission end) -----------------------------*/
if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET))
{
IRDA_EndTransmit_IT(hirda);
- }
-
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
+ }
-/** @addtogroup IRDA_Private_Functions IRDA Private Functions
- * @{
- */
-
-/**
- * @brief DMA IRDA Tx transfer completed callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hirda->TxXferCount = 0;
-
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the IRDA CR3 register */
- hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);
-
- /* Enable the IRDA Transmit Complete Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
}
/**
- * @brief DMA IRDA Rx Transfer completed callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hirda->RxXferCount = 0;
-
- /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
- in the IRDA CR3 register */
- hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
-
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_READY;
- }
-
- HAL_IRDA_RxCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA communication error callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hirda->RxXferCount = 0;
- hirda->TxXferCount = 0;
- hirda->State= HAL_IRDA_STATE_READY;
- hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
- HAL_IRDA_ErrorCallback(hirda);
-}
-/**
- * @}
- */
-
-/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
- * @{
- */
-
-/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
-/**
- * @brief Tx Transfer completed callback
- * @param hirda: irda handle
+ * @brief Tx Transfer completed callback.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
{
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_TxCpltCallback can be implemented in the user file
- */
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief Rx Transfer completed callback
- * @param hirda: irda handle
+ * @brief Tx Half Transfer completed callback.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
+ * @retval None
+ */
+ __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
{
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_TxCpltCallback can be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief IRDA error callback
- * @param hirda: IRDA handle
+ * @brief Rx Half Transfer complete callback.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA error callback.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
{
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_ErrorCallback can be implemented in the user file
- */
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_ErrorCallback can be implemented in the user file.
+ */
}
/**
* @}
*/
-/**
- * @}
- */
-
-/** @addtogroup IRDA_Private_Functions IRDA Private Functions
- * @{
- */
-
-/**
- * @brief Receive an amount of data in non blocking mode.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_IRDA_Transmit_IT()
- * @param hirda: IRDA handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
-{
- uint16_t* tmp;
-
- if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
- {
-
- if(hirda->TxXferCount == 0)
- {
- /* Disable the IRDA Transmit Data Register Empty Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
-
- /* Enable the IRDA Transmit Complete Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
-
- return HAL_OK;
- }
- else
- {
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
- {
- tmp = (uint16_t*) hirda->pTxBuffPtr;
- hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- hirda->pTxBuffPtr += 2;
- }
- else
- {
- hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
- }
- hirda->TxXferCount--;
-
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
+/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief IRDA State and Errors functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of IrDA
+ communication process and also return Peripheral Errors occurred during communication process
+ (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
+ of the IRDA peripheral handle.
+ (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
+ communication.
-/**
- * @brief Wraps up transmission in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
-{
- /* Disable the IRDA Transmit Complete Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
-
- /* Check if a receive process is ongoing or not */
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_RX;
- }
- else
- {
- /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
- hirda->State = HAL_IRDA_STATE_READY;
- }
-
- HAL_IRDA_TxCpltCallback(hirda);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Receive an amount of data in non blocking mode.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_IRDA_Receive_IT()
- * @param hirda: IRDA handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
-{
- uint16_t* tmp;
- uint16_t uhMask = hirda->Mask;
-
- if ((hirda->State == HAL_IRDA_STATE_BUSY_RX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
- {
-
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
- {
- tmp = (uint16_t*) hirda->pRxBuffPtr ;
- *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
- hirda->pRxBuffPtr +=2;
- }
- else
- {
- *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
- }
-
- if(--hirda->RxXferCount == 0)
- {
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
-
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX;
- }
- else
- {
- /* Disable the IRDA Parity Error Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-
- /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
- hirda->State = HAL_IRDA_STATE_READY;
- }
-
- HAL_IRDA_RxCpltCallback(hirda);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
- * @{
- */
-
-/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief IRDA control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the IRDA.
- (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral.
- (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters.
@endverbatim
* @{
*/
/**
- * @brief return the IRDA state
- * @param hirda: irda handle
+ * @brief Return the IRDA handle state.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL state
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
{
+ /* Return IRDA handle state */
return hirda->State;
}
/**
-* @brief Return the IRDA error code
-* @param hirda : pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA.
-* @retval IRDA Error Code
-*/
+ * @brief Return the IRDA handle error code.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval IRDA Error Code
+ */
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
{
return hirda->ErrorCode;
@@ -1174,74 +1153,77 @@
/**
* @}
- */
+ */
/** @addtogroup IRDA_Private_Functions IRDA Private Functions
* @{
*/
-
+
+
/**
- * @brief Configure the IRDA peripheral
- * @param hirda: irda handle
+ * @brief Configure the IRDA peripheral.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
{
uint32_t tmpreg = 0x00000000;
IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
- HAL_StatusTypeDef ret = HAL_OK;
-
- /* Check the communication parameters */
- assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the communication parameters */
+ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
- assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
- assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
+ assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
+ assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* Configure the IRDA Word Length, Parity and transfer Mode:
- Set the M bits according to hirda->Init.WordLength value
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Configure the IRDA Word Length, Parity and transfer Mode:
+ Set the M bits according to hirda->Init.WordLength value
Set PCE and PS bits according to hirda->Init.Parity value
Set TE and RE bits according to hirda->Init.Mode value */
tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
-
+
MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
-
+
/*-------------------------- USART CR3 Configuration -----------------------*/
MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
-
- /*-------------------------- USART GTPR Configuration ----------------------*/
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- __HAL_IRDA_GETCLOCKSOURCE(hirda, clocksource);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ IRDA_GETCLOCKSOURCE(hirda, clocksource);
switch (clocksource)
{
- case IRDA_CLOCKSOURCE_PCLK1:
+ case IRDA_CLOCKSOURCE_PCLK1:
hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hirda->Init.BaudRate);
break;
- case IRDA_CLOCKSOURCE_HSI:
- hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_SYSCLK:
+ case IRDA_CLOCKSOURCE_HSI:
+ hirda->Instance->BRR = (uint16_t)(HSI_VALUE / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_SYSCLK:
hirda->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_LSE:
- hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_LSE:
+ hirda->Instance->BRR = (uint16_t)(LSE_VALUE / hirda->Init.BaudRate);
break;
- case IRDA_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
+ case IRDA_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
}
-
- return ret;
+
+ return ret;
}
/**
- * @brief Check the IRDA Idle State
- * @param hirda: IRDA handle
+ * @brief Check the IRDA Idle State.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
@@ -1250,67 +1232,79 @@
/* Initialize the IRDA ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- /* Check if the Transmitter is enabled */
- if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
+ Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
+ */
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+ if (IS_UART_WAKEUP_INSTANCE(hirda->Instance))
{
- /* Wait until TEACK flag is set */
- if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout Occured */
- return HAL_TIMEOUT;
- }
- }
+ /* Check if the Transmitter is enabled */
+ if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
/* Check if the Receiver is enabled */
- if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout Occured */
- return HAL_TIMEOUT;
- }
+ if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
}
-
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+
/* Initialize the IRDA state*/
- hirda->State= HAL_IRDA_STATE_READY;
+ hirda->State= HAL_IRDA_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hirda);
-
+
return HAL_OK;
}
/**
* @brief Handle IRDA Communication Timeout.
- * @param hirda: IRDA handle
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @param Flag: specifies the IRDA flag to check.
- * @param Status: the flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
+ * @param Status: the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
* @param Timeout: Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
-
+
/* Wait until flag is set */
if(Status == RESET)
- {
+ {
while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
+
hirda->State= HAL_IRDA_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hirda);
-
+
return HAL_TIMEOUT;
}
}
@@ -1322,26 +1316,268 @@
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
+
hirda->State= HAL_IRDA_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hirda);
-
+
return HAL_TIMEOUT;
}
}
}
}
- return HAL_OK;
+ return HAL_OK;
+}
+
+/**
+ * @brief DMA IRDA transmit process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ hirda->TxXferCount = 0;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the IRDA CR3 register */
+ hirda->Instance->CR3 &= ~(USART_CR3_DMAT);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+ }
+ /* DMA Circular mode */
+ else
+ {
+ HAL_IRDA_TxCpltCallback(hirda);
+ }
+}
+
+/**
+ * @brief DMA IRDA transmit process half complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_IRDA_TxHalfCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA receive process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ hirda->RxXferCount = 0;
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the IRDA CR3 register */
+ hirda->Instance->CR3 &= ~(USART_CR3_DMAR);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+ else
+ {
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+ }
+
+ HAL_IRDA_RxCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA receive process half complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_IRDA_RxHalfCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA communication error callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->RxXferCount = 0;
+ hirda->TxXferCount = 0;
+ hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+ hirda->State= HAL_IRDA_STATE_READY;
+
+ HAL_IRDA_ErrorCallback(hirda);
+}
+
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Transmit_IT().
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp;
+
+ if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
+ {
+ if(hirda->TxXferCount == 0)
+ {
+ /* Disable the IRDA Transmit Data Register Empty Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) hirda->pTxBuffPtr;
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ hirda->pTxBuffPtr += 2;
+ }
+ else
+ {
+ hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
+ }
+ hirda->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable the IRDA Transmit Complete Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ HAL_IRDA_TxCpltCallback(hirda);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * Function is called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Receive_IT().
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp;
+ uint16_t uhMask = hirda->Mask;
+
+ if ((hirda->State == HAL_IRDA_STATE_BUSY_RX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX))
+ {
+
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) hirda->pRxBuffPtr ;
+ *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
+ hirda->pRxBuffPtr +=2;
+ }
+ else
+ {
+ *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ }
+
+ if(--hirda->RxXferCount == 0)
+ {
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+
+ if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
+ {
+ hirda->State = HAL_IRDA_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Disable the IRDA Parity Error Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ hirda->State = HAL_IRDA_STATE_READY;
+ }
+
+ HAL_IRDA_RxCpltCallback(hirda);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
}
/**
@@ -1356,7 +1592,7 @@
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#endif /* HAL_IRDA_MODULE_ENABLED */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f0xx_hal_irda.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief This file contains all the functions prototypes for the IRDA
* firmware library.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -55,16 +55,16 @@
/** @addtogroup IRDA
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup IRDA_Exported_Types IRDA Exported Types
* @{
- */
+ */
-/**
- * @brief IRDA Init Structure definition
- */
+/**
+ * @brief IRDA Init Structure definition
+ */
typedef struct
{
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
@@ -74,32 +74,32 @@
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref IRDAEx_Word_Length */
- uint16_t Parity; /*!< Specifies the parity mode.
+ uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref IRDA_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
-
- uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref IRDA_Mode */
-
+
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
to achieve low-power frequency.
@note Prescaler value 0 is forbidden */
-
+
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
This parameter can be a value of @ref IRDA_Low_Power */
}IRDA_InitTypeDef;
-/**
- * @brief HAL IRDA State structures definition
- */
+/**
+ * @brief HAL IRDA State structures definition
+ */
typedef enum
{
- HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
- HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
+ HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
@@ -116,56 +116,56 @@
IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
IRDA_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
- IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
+ IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
}IRDA_ClockSourceTypeDef;
-/**
- * @brief IRDA handle Structure definition
- */
+/**
+ * @brief IRDA handle Structure definition
+ */
typedef struct
{
USART_TypeDef *Instance; /*!< USART registers base address */
-
+
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
-
+
uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
-
+
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
-
+
uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
-
+
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
-
+
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
-
+
uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
-
- uint16_t Mask; /*!< USART RX RDR register mask */
-
+
+ uint16_t Mask; /*!< USART RX RDR register mask */
+
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
-
+
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
-
+
HAL_LockTypeDef Lock; /*!< Locking object */
- HAL_IRDA_StateTypeDef State; /*!< IRDA communication state */
-
+ __IO HAL_IRDA_StateTypeDef State; /*!< IRDA communication state */
+
__IO uint32_t ErrorCode; /*!< IRDA Error code
This parameter can be a value of @ref IRDA_Error */
}IRDA_HandleTypeDef;
-/**
- * @brief IRDA Configuration enumeration values definition
+/**
+ * @brief IRDA Configuration enumeration values definition
*/
-typedef enum
+typedef enum
{
- IRDA_BAUDRATE = 0x00,
- IRDA_PARITY = 0x01,
- IRDA_WORDLENGTH = 0x02,
- IRDA_MODE = 0x03,
- IRDA_PRESCALER = 0x04,
- IRDA_POWERMODE = 0x05
+ IRDA_BAUDRATE = 0x00, /*!< IRDA Baud rate */
+ IRDA_PARITY = 0x01, /*!< IRDA frame parity */
+ IRDA_WORDLENGTH = 0x02, /*!< IRDA frame length */
+ IRDA_MODE = 0x03, /*!< IRDA communication mode */
+ IRDA_PRESCALER = 0x04, /*!< IRDA prescaling */
+ IRDA_POWERMODE = 0x05 /*!< IRDA power mode */
}IRDA_ControlTypeDef;
/**
@@ -173,13 +173,13 @@
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Constants IRDA Exported constants
+/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
* @{
*/
/** @defgroup IRDA_Error IRDA Error
* @{
- */
+ */
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
@@ -188,62 +188,51 @@
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
/**
* @}
- */
+ */
-/** @defgroup IRDA_Parity IRDA Parity
+/** @defgroup IRDA_Parity IRDA Parity
* @{
- */
-#define IRDA_PARITY_NONE ((uint16_t)0x0000)
-#define IRDA_PARITY_EVEN ((uint16_t)USART_CR1_PCE)
-#define IRDA_PARITY_ODD ((uint16_t)(USART_CR1_PCE | USART_CR1_PS))
-#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
- ((PARITY) == IRDA_PARITY_EVEN) || \
- ((PARITY) == IRDA_PARITY_ODD))
-/**
- * @}
- */
-
-
-/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
- * @{
- */
-#define IRDA_MODE_RX ((uint16_t)USART_CR1_RE)
-#define IRDA_MODE_TX ((uint16_t)USART_CR1_TE)
-#define IRDA_MODE_TX_RX ((uint16_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_IRDA_TX_RX_MODE(MODE) ((((MODE) & ((uint16_t)(~((uint16_t)(IRDA_MODE_TX_RX))))) == (uint16_t)0x00) && ((MODE) != (uint16_t)0x00))
+ */
+#define IRDA_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */
+#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
+#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
/**
* @}
*/
-/** @defgroup IRDA_Low_Power IRDA Low Power
+/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
* @{
*/
-#define IRDA_POWERMODE_NORMAL ((uint16_t)0x0000)
-#define IRDA_POWERMODE_LOWPOWER ((uint16_t)USART_CR3_IRLP)
-#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
- ((MODE) == IRDA_POWERMODE_NORMAL))
+#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
+#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
+#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
/**
* @}
*/
-
- /** @defgroup IRDA_State IRDA State
+
+/** @defgroup IRDA_Low_Power IRDA Low Power
* @{
- */
-#define IRDA_STATE_DISABLE ((uint16_t)0x0000)
-#define IRDA_STATE_ENABLE ((uint16_t)USART_CR1_UE)
-#define IS_IRDA_STATE(STATE) (((STATE) == IRDA_STATE_DISABLE) || \
- ((STATE) == IRDA_STATE_ENABLE))
+ */
+#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000) /*!< IRDA normal power mode */
+#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) /*!< IRDA low power mode */
+/**
+ * @}
+ */
+
+ /** @defgroup IRDA_State IRDA State
+ * @{
+ */
+#define IRDA_STATE_DISABLE ((uint32_t)0x00000000) /*!< IRDA disabled */
+#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< IRDA enabled */
/**
* @}
*/
/** @defgroup IRDA_Mode IRDA Mode
* @{
- */
-#define IRDA_MODE_DISABLE ((uint16_t)0x0000)
-#define IRDA_MODE_ENABLE ((uint16_t)USART_CR3_IREN)
-#define IS_IRDA_MODE(STATE) (((STATE) == IRDA_MODE_DISABLE) || \
- ((STATE) == IRDA_MODE_ENABLE))
+ */
+#define IRDA_MODE_DISABLE ((uint32_t)0x00000000) /*!< Associated UART disabled in IRDA mode */
+#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) /*!< Associated UART enabled in IRDA mode */
/**
* @}
*/
@@ -251,58 +240,62 @@
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
* @{
*/
-#define IRDA_ONE_BIT_SAMPLE_DISABLED ((uint16_t)0x00000000)
-#define IRDA_ONE_BIT_SAMPLE_ENABLED ((uint16_t)USART_CR3_ONEBIT)
-#define IS_IRDA_ONEBIT_SAMPLE(ONEBIT) (((ONEBIT) == IRDA_ONE_BIT_SAMPLE_DISABLED) || \
- ((ONEBIT) == IRDA_ONE_BIT_SAMPLE_ENABLED))
+#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disabled */
+#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled */
/**
* @}
- */
-
+ */
+
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
* @{
*/
-#define IRDA_DMA_TX_DISABLE ((uint16_t)0x00000000)
-#define IRDA_DMA_TX_ENABLE ((uint16_t)USART_CR3_DMAT)
-#define IS_IRDA_DMA_TX(DMATX) (((DMATX) == IRDA_DMA_TX_DISABLE) || \
- ((DMATX) == IRDA_DMA_TX_ENABLE))
+#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA TX disabled */
+#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< IRDA DMA TX enabled */
/**
* @}
- */
-
+ */
+
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
* @{
*/
-#define IRDA_DMA_RX_DISABLE ((uint16_t)0x0000)
-#define IRDA_DMA_RX_ENABLE ((uint16_t)USART_CR3_DMAR)
-#define IS_IRDA_DMA_RX(DMARX) (((DMARX) == IRDA_DMA_RX_DISABLE) || \
- ((DMARX) == IRDA_DMA_RX_ENABLE))
+#define IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA RX disabled */
+#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< IRDA DMA RX enabled */
/**
* @}
*/
-
+
+/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
+ * @{
+ */
+#define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
+#define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#define IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+/**
+ * @}
+ */
+
/** @defgroup IRDA_Flags IRDA Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define IRDA_FLAG_REACK ((uint32_t)0x00400000)
-#define IRDA_FLAG_TEACK ((uint32_t)0x00200000)
-#define IRDA_FLAG_BUSY ((uint32_t)0x00010000)
-#define IRDA_FLAG_ABRF ((uint32_t)0x00008000)
-#define IRDA_FLAG_ABRE ((uint32_t)0x00004000)
-#define IRDA_FLAG_TXE ((uint32_t)0x00000080)
-#define IRDA_FLAG_TC ((uint32_t)0x00000040)
-#define IRDA_FLAG_RXNE ((uint32_t)0x00000020)
-#define IRDA_FLAG_ORE ((uint32_t)0x00000008)
-#define IRDA_FLAG_NE ((uint32_t)0x00000004)
-#define IRDA_FLAG_FE ((uint32_t)0x00000002)
-#define IRDA_FLAG_PE ((uint32_t)0x00000001)
+#define IRDA_FLAG_REACK ((uint32_t)0x00400000) /*!< IRDA Receive enable acknowledge flag */
+#define IRDA_FLAG_TEACK ((uint32_t)0x00200000) /*!< IRDA Transmit enable acknowledge flag */
+#define IRDA_FLAG_BUSY ((uint32_t)0x00010000) /*!< IRDA Busy flag */
+#define IRDA_FLAG_ABRF ((uint32_t)0x00008000) /*!< IRDA Auto baud rate flag */
+#define IRDA_FLAG_ABRE ((uint32_t)0x00004000) /*!< IRDA Auto baud rate error */
+#define IRDA_FLAG_TXE ((uint32_t)0x00000080) /*!< IRDA Transmit data register empty */
+#define IRDA_FLAG_TC ((uint32_t)0x00000040) /*!< IRDA Transmission complete */
+#define IRDA_FLAG_RXNE ((uint32_t)0x00000020) /*!< IRDA Read data register not empty */
+#define IRDA_FLAG_ORE ((uint32_t)0x00000008) /*!< IRDA Overrun error */
+#define IRDA_FLAG_NE ((uint32_t)0x00000004) /*!< IRDA Noise error */
+#define IRDA_FLAG_FE ((uint32_t)0x00000002) /*!< IRDA Noise error */
+#define IRDA_FLAG_PE ((uint32_t)0x00000001) /*!< IRDA Parity error */
/**
* @}
- */
+ */
-/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definition
+/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
* Elements values convention: 0000ZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
@@ -310,16 +303,14 @@
* - 10: CR2 register
* - 11: CR3 register
* - ZZZZ : Flag position in the ISR register(4bits)
- * @{
- */
-#define IRDA_IT_PE ((uint16_t)0x0028)
-#define IRDA_IT_TXE ((uint16_t)0x0727)
-#define IRDA_IT_TC ((uint16_t)0x0626)
-#define IRDA_IT_RXNE ((uint16_t)0x0525)
-#define IRDA_IT_IDLE ((uint16_t)0x0424)
+ * @{
+ */
+#define IRDA_IT_PE ((uint16_t)0x0028) /*!< IRDA Parity error interruption */
+#define IRDA_IT_TXE ((uint16_t)0x0727) /*!< IRDA Transmit data register empty interruption */
+#define IRDA_IT_TC ((uint16_t)0x0626) /*!< IRDA Transmission complete interruption */
+#define IRDA_IT_RXNE ((uint16_t)0x0525) /*!< IRDA Read data register not empty interruption */
+#define IRDA_IT_IDLE ((uint16_t)0x0424) /*!< IRDA Idle interruption */
-
-
/** Elements values convention: 000000000XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
@@ -327,18 +318,18 @@
* - 10: CR2 register
* - 11: CR3 register
*/
-#define IRDA_IT_ERR ((uint16_t)0x0060)
+#define IRDA_IT_ERR ((uint16_t)0x0060) /*!< IRDA Error interruption */
/** Elements values convention: 0000ZZZZ00000000b
* - ZZZZ : Flag position in the ISR register(4bits)
*/
-#define IRDA_IT_ORE ((uint16_t)0x0300)
-#define IRDA_IT_NE ((uint16_t)0x0200)
-#define IRDA_IT_FE ((uint16_t)0x0100)
+#define IRDA_IT_ORE ((uint16_t)0x0300) /*!< IRDA Overrun error interruption */
+#define IRDA_IT_NE ((uint16_t)0x0200) /*!< IRDA Noise error interruption */
+#define IRDA_IT_FE ((uint16_t)0x0100) /*!< IRDA Frame error interruption */
/**
* @}
*/
-
+
/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
* @{
*/
@@ -349,54 +340,96 @@
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
/**
* @}
- */
-
+ */
-
-/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
+/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
* @{
*/
-#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
-#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
-#define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \
- ((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \
- ((PARAM) == IRDA_TXDATA_FLUSH_REQUEST))
+#define IRDA_IT_MASK ((uint16_t)0x001F) /*!< IRDA Interruptions flags mask */
/**
* @}
*/
-
-/** @defgroup IRDA_Interruption_Mask IRDA interruptions flag mask
- * @{
- */
-#define IRDA_IT_MASK ((uint16_t)0x001F)
-/**
- * @}
- */
-
+
/**
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
* @{
*/
-
-/** @brief Reset IRDA handle state
+
+/** @brief Reset IRDA handle state.
* @param __HANDLE__: IRDA handle.
* @retval None
*/
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
-/** @brief Checks whether the specified IRDA flag is set or not.
+/** @brief Flush the IRDA DR register.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
+ } while(0)
+
+
+/** @brief Clear the specified IRDA pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg IRDA_CLEAR_PEF
+ * @arg IRDA_CLEAR_FEF
+ * @arg IRDA_CLEAR_NEF
+ * @arg IRDA_CLEAR_OREF
+ * @arg IRDA_CLEAR_TCF
+ * @arg IRDA_CLEAR_IDLEF
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the IRDA PE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
+
+
+/** @brief Clear the IRDA FE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
+
+/** @brief Clear the IRDA NE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
+
+/** @brief Clear the IRDA ORE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
+
+/** @brief Clear the IRDA IDLE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
+
+/** @brief Check whether the specified IRDA flag is set or not.
* @param __HANDLE__: specifies the IRDA Handle.
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
* UART peripheral
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
- * @arg IRDA_FLAG_REACK: Receive enable ackowledge flag
- * @arg IRDA_FLAG_TEACK: Transmit enable ackowledge flag
+ * @arg IRDA_FLAG_REACK: Receive enable acknowledge flag
+ * @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag
* @arg IRDA_FLAG_BUSY: Busy flag
* @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag
* @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag
@@ -410,9 +443,10 @@
* @arg IRDA_FLAG_PE: Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-/** @brief Enables the specified IRDA interrupt.
+
+/** @brief Enable the specified IRDA interrupt.
* @param __HANDLE__: specifies the IRDA Handle.
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
* UART peripheral
@@ -430,7 +464,7 @@
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
-/** @brief Disables the specified IRDA interrupt.
+/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__: specifies the IRDA Handle.
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
* UART peripheral
@@ -447,9 +481,9 @@
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
-
-
-/** @brief Checks whether the specified IRDA interrupt has occurred or not.
+
+
+/** @brief Check whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__: specifies the IRDA Handle.
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
* UART peripheral
@@ -462,12 +496,12 @@
* @arg IRDA_IT_ORE: OverRun Error interrupt
* @arg IRDA_IT_NE: Noise Error interrupt
* @arg IRDA_IT_FE: Framing Error interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
+#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
-/** @brief Checks whether the specified IRDA interrupt source is enabled.
+/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__: specifies the IRDA Handle.
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
* UART peripheral
@@ -480,28 +514,28 @@
* @arg IRDA_IT_ORE: OverRun Error interrupt
* @arg IRDA_IT_NE: Noise Error interrupt
* @arg IRDA_IT_FE: Framing Error interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg IRDA_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
-/** @brief Clears the specified IRDA ISR flag, in setting the proper ICR register flag.
+/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__: specifies the IRDA Handle.
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
* UART peripheral
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
- * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag
- * @arg IRDA_CLEAR_FEF: Framing Error Clear Flag
- * @arg IRDA_CLEAR_NEF: Noise detected Clear Flag
- * @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag
- * @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag
+ * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag
+ * @arg IRDA_CLEAR_FEF: Framing Error Clear Flag
+ * @arg IRDA_CLEAR_NEF: Noise detected Clear Flag
+ * @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag
+ * @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag
* @retval None
*/
-#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific IRDA request flag.
@@ -510,25 +544,39 @@
* UART peripheral
* @param __REQ__: specifies the request flag to set
* This parameter can be one of the following values:
- * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request
- * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request
- * @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request
+ * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request
+ * @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request
*
* @retval None
- */
-#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+ */
+#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-
+/** @brief Enable the IRDA one bit sample method.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-/** @brief Enable UART/USART associated to IRDA Handle
+/** @brief Disable the IRDA one bit sample method.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
+ * UART peripheral
+ * @retval None
+ */
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable UART/USART associated to IRDA Handle.
* @param __HANDLE__: specifies the IRDA Handle.
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
* UART peripheral
* @retval None
- */
+ */
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-/** @brief Disable UART/USART associated to IRDA Handle
+/** @brief Disable UART/USART associated to IRDA Handle.
* @param __HANDLE__: specifies the IRDA Handle.
* The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
* UART peripheral
@@ -536,32 +584,112 @@
*/
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-/** @brief Ensure that IRDA Baud rate is less or equal to maximum value
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros IRDA Private Macros
+ * @{
+ */
+
+/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
* @param __BAUDRATE__: specifies the IRDA Baudrate set by the user.
* @retval True or False
- */
+ */
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
-/** @brief Ensure that IRDA prescaler value is strictly larger than 0
+/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
* @param __PRESCALER__: specifies the IRDA prescaler value set by the user.
* @retval True or False
- */
-#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
+ */
+#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
+
+/**
+ * @brief Ensure that IRDA frame parity is valid.
+ * @param __PARITY__: IRDA frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
+ ((__PARITY__) == IRDA_PARITY_EVEN) || \
+ ((__PARITY__) == IRDA_PARITY_ODD))
+
+/**
+ * @brief Ensure that IRDA communication mode is valid.
+ * @param __MODE__: IRDA communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
+
+/**
+ * @brief Ensure that IRDA power mode is valid.
+ * @param __MODE__: IRDA power mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
+ ((__MODE__) == IRDA_POWERMODE_NORMAL))
+
+/**
+ * @brief Ensure that IRDA state is valid.
+ * @param __STATE__: IRDA state mode.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
+ ((__STATE__) == IRDA_STATE_ENABLE))
/**
+ * @brief Ensure that IRDA associated UART/USART mode is valid.
+ * @param __MODE__: IRDA associated UART/USART mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
+ ((__MODE__) == IRDA_MODE_ENABLE))
+
+/**
+ * @brief Ensure that IRDA sampling rate is valid.
+ * @param __ONEBIT__: IRDA sampling rate.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+ * @brief Ensure that IRDA DMA TX mode is valid.
+ * @param __DMATX__: IRDA DMA TX mode.
+ * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+ */
+#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
+ ((__DMATX__) == IRDA_DMA_TX_ENABLE))
+
+/**
+ * @brief Ensure that IRDA DMA RX mode is valid.
+ * @param __DMARX__: IRDA DMA RX mode.
+ * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+ */
+#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
+ ((__DMARX__) == IRDA_DMA_RX_ENABLE))
+
+/**
+ * @brief Ensure that IRDA request is valid.
+ * @param __PARAM__: IRDA request.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
+/**
* @}
*/
/* Include IRDA HAL Extended module */
-#include "stm32f0xx_hal_irda_ex.h"
+#include "stm32f0xx_hal_irda_ex.h"
/* Exported functions --------------------------------------------------------*/
-
/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
* @{
*/
-
-/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+
+/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
@@ -575,7 +703,7 @@
* @}
*/
-/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
+/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
* @{
*/
@@ -586,41 +714,48 @@
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
-/** @addtogroup IRDA_Exported_Functions_Group3
+/* Peripheral Control functions ************************************************/
+
+/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/**
* @}
*/
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-
+
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_irda_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_irda_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of IRDA HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -32,7 +32,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -52,9 +52,9 @@
* @{
*/
-/** @addtogroup IRDAEx IRDAEx Extended HAL module driver
+/** @addtogroup IRDAEx IRDAEx
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@@ -68,43 +68,40 @@
#if defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx)
-#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
-#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
-#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
-#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_7B) || \
- ((LENGTH) == IRDA_WORDLENGTH_8B) || \
- ((LENGTH) == IRDA_WORDLENGTH_9B))
+#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long frame */
+#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long frame */
#else
-#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
-#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
- ((LENGTH) == IRDA_WORDLENGTH_9B))
+#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long frame */
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx)*/
/**
* @}
*/
-
-
+
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @defgroup IRDAEx_Exported_Macros IRDAEx Exported Macros
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
* @{
*/
-
-/** @brief Reports the IRDA clock source.
- * @param __HANDLE__: specifies the IRDA Handle
- * @param __CLOCKSOURCE__ : output variable
+
+/** @brief Report the IRDA clock source.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __CLOCKSOURCE__: output variable.
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/
#if defined(STM32F031x6) || defined(STM32F038xx)
-#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
@@ -127,7 +124,7 @@
} while(0)
#elif defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F051x8) || defined (STM32F058xx)
-#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -160,7 +157,7 @@
} \
} while(0)
#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
-#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -218,7 +215,7 @@
} \
} while(0)
#elif defined(STM32F091xC) || defined(STM32F098xx)
-#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -308,19 +305,23 @@
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0)
-
+
#endif /* defined(STM32F031x6) || defined(STM32F038xx) */
-
-
-/** @brief Computes the mask to apply to retrieve the received data
+
+
+/** @brief Compute the mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
+ * @note If PCE = 1, the parity bit is not included in the data extracted
+ * by the reception API().
+ * This masking operation is not carried out in the case of
+ * DMA transfers.
* @param __HANDLE__: specifies the IRDA Handle
- * @retval none
+ * @retval None, the mask to apply to IRDA RDR register is stored in (__HANDLE__)->Mask field.
*/
#if defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx)
-#define __HAL_IRDA_MASK_COMPUTATION(__HANDLE__) \
+#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
@@ -357,7 +358,7 @@
} \
} while(0)
#else
-#define __HAL_IRDA_MASK_COMPUTATION(__HANDLE__) \
+#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
@@ -385,23 +386,38 @@
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined(STM32F098xx) */
+
+/**
+ * @brief Ensure that IRDA frame length is valid.
+ * @param __LENGTH__: IRDA frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#if defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)
+#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
+ ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
+ ((__LENGTH__) == IRDA_WORDLENGTH_9B))
+#else
+#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
+ ((__LENGTH__) == IRDA_WORDLENGTH_9B))
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)*/
+
/**
* @}
*/
-
+
/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions ****************************/
-/* IO operation functions *****************************************************/
-/* Peripheral Control functions ***********************************************/
-/* Peripheral State and Error functions ***************************************/
/**
* @}
- */
+ */
/**
* @}
- */
+ */
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_iwdg.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
@@ -69,15 +69,15 @@
(+) __HAL_IWDG_START: Enable the IWDG peripheral
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
- (+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
- (+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
+ (+) IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
+ (+) IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
(+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -101,8 +101,8 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
- */
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@@ -111,7 +111,7 @@
* @{
*/
-/** @defgroup IWDG IWDG HAL module driver
+/** @defgroup IWDG IWDG
* @brief IWDG HAL module driver.
* @{
*/
@@ -120,7 +120,6 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
@@ -130,43 +129,42 @@
/**
* @}
*/
-
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
* @{
*/
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
+ * @brief Initialization and Configuration functions.
*
-@verbatim
+@verbatim
===============================================================================
- ##### Initialization functions #####
+ ##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) Initialize the IWDG according to the specified parameters
+ (+) Initialize the IWDG according to the specified parameters
in the IWDG_InitTypeDef and create the associated handle
(+) Manage Window option
(+) Initialize the IWDG MSP
- (+) DeInitialize IWDG MSP
-
+ (+) DeInitialize the IWDG MSP
+
@endverbatim
* @{
*/
/**
- * @brief Initializes the IWDG according to the specified
- * parameters in the IWDG_InitTypeDef and creates the associated handle.
+ * @brief Initialize the IWDG according to the specified
+ * parameters in the IWDG_InitTypeDef and initialize the associated handle.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
-{
+{
uint32_t tickstart = 0;
/* Check the IWDG handle allocation */
@@ -174,7 +172,7 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
@@ -188,24 +186,27 @@
{
return HAL_ERROR;
}
-
+
if(hiwdg->State == HAL_IWDG_STATE_RESET)
- {
- /* Init the low level hardware */
- HAL_IWDG_MspInit(hiwdg);
+ {
+ /* Allocate lock resource and initialize it */
+ hiwdg->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware */
+ HAL_IWDG_MspInit(hiwdg);
}
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
- /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */
- /* by writing 0x5555 in KR */
- __HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg);
-
+ /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */
+ /* by writing 0x5555 in KR */
+ IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
/* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
-
+
/* check if window option is enabled */
if (((hiwdg->Init.Window) != IWDG_WINDOW_DISABLE) || ((hiwdg->Instance->WINR) != IWDG_WINDOW_DISABLE))
{
@@ -214,34 +215,34 @@
/* Wait for register to be updated */
while((uint32_t)(hiwdg->Instance->SR) != RESET)
{
- if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
- {
+ if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
/* Set IWDG state */
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
return HAL_TIMEOUT;
- }
+ }
}
/* Write to IWDG WINR the IWDG_Window value to compare with */
MODIFY_REG(hiwdg->Instance->WINR, IWDG_WINR_WIN, hiwdg->Init.Window);
+ }
- }
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the IWDG MSP.
+ * @brief Initialize the IWDG MSP.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval None
*/
__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_IWDG_MspInit could be implemented in the user file
*/
}
@@ -253,10 +254,10 @@
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Start the IWDG.
(+) Refresh the IWDG.
@@ -266,82 +267,83 @@
*/
/**
- * @brief Starts the IWDG.
+ * @brief Start the IWDG.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
-{
+{
uint32_t tickstart = 0;
- /* Process Locked */
+ /* Process locked */
__HAL_LOCK(hiwdg);
-
- /* Change IWDG peripheral state */
+
+ /* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
-
+
/* Reload IWDG counter with value defined in the RLR register */
if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE)
{
- __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
}
- /* Enable the IWDG peripheral */
+ /* Start the IWDG peripheral */
__HAL_IWDG_START(hiwdg);
tickstart = HAL_GetTick();
/* Wait until PVU, RVU, WVU flag are RESET */
while( (__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET)
- &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
- &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET) )
+ &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
+ &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET) )
{
- if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
- {
+
+ if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
/* Set IWDG state */
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
-
- /* Process unlocked */
+
+ /* Process unlocked */
__HAL_UNLOCK(hiwdg);
-
+
return HAL_TIMEOUT;
- }
+ }
}
- /* Change IWDG peripheral state */
- hiwdg->State = HAL_IWDG_STATE_READY;
-
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hiwdg);
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Refreshes the IWDG.
+ * @brief Refresh the IWDG.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
- {
+{
uint32_t tickstart = 0;
/* Process Locked */
- __HAL_LOCK(hiwdg);
-
- /* Change IWDG peripheral state */
+ __HAL_LOCK(hiwdg);
+
+ /* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
-
+
tickstart = HAL_GetTick();
/* Wait until RVU flag is RESET */
while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
{
- if((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
- {
+ if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
/* Set IWDG state */
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
@@ -349,18 +351,18 @@
__HAL_UNLOCK(hiwdg);
return HAL_TIMEOUT;
- }
+ }
}
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
-
- /* Change IWDG peripheral state */
- hiwdg->State = HAL_IWDG_STATE_READY;
-
+
+ /* Change IWDG peripheral state */
+ hiwdg->State = HAL_IWDG_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hiwdg);
-
+
/* Return function status */
return HAL_OK;
}
@@ -370,28 +372,28 @@
*/
/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions.
+ * @brief Peripheral State functions.
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
+ This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
- * @brief Returns the IWDG state.
+ * @brief Return the IWDG handle state.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL state
*/
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
{
+ /* Return IWDG handle state */
return hiwdg->State;
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_iwdg.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_iwdg.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -32,7 +32,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -52,55 +52,54 @@
/** @addtogroup IWDG
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
-
+/* Exported types ------------------------------------------------------------*/
/** @defgroup IWDG_Exported_Types IWDG Exported Types
* @{
*/
/**
- * @brief IWDG HAL State Structure definition
- */
+ * @brief IWDG HAL State Structure definition
+ */
typedef enum
{
- HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
- HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
- HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
- HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
- HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
+ HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
+ HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
+ HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
+ HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
+ HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
}HAL_IWDG_StateTypeDef;
/**
- * @brief IWDG Init structure definition
+ * @brief IWDG Init structure definition
*/
typedef struct
{
- uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
- This parameter can be a value of @ref IWDG_Prescaler */
-
- uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
- uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+ uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
+ This parameter can be a value of @ref IWDG_Prescaler */
+
+ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+
+ uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
} IWDG_InitTypeDef;
/**
* @brief IWDG Handle Structure definition
- */
+ */
typedef struct
{
- IWDG_TypeDef *Instance; /*!< Register base address */
-
- IWDG_InitTypeDef Init; /*!< IWDG required parameters */
-
- HAL_LockTypeDef Lock; /*!< IWDG Locking object */
-
- __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
+ IWDG_TypeDef *Instance; /*!< Register base address */
+
+ IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+
+ HAL_LockTypeDef Lock; /*!< IWDG Locking object */
+
+ __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
}IWDG_HandleTypeDef;
@@ -109,134 +108,63 @@
*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
* @{
*/
-/** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask
- * @brief IWDG registers bit mask
- * @{
- */
-/* --- KR Register ---*/
-/* KR register bit mask */
-#define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */
-#define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */
-#define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */
-#define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */
-
-#define IS_IWDG_KR(__KR__) (((__KR__) == KR_KEY_RELOAD) || \
- ((__KR__) == KR_KEY_ENABLE))|| \
- ((__KR__) == KR_KEY_EWA)) || \
- ((__KR__) == KR_KEY_DWA))
-/**
- * @}
- */
-
-/** @defgroup IWDG_Flag_definition IWDG Flag definition
- * @{
- */
-#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update Flag */
-#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update Flag */
-#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update Flag */
-
-/**
- * @}
- */
-
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
- */
-#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
-#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
-#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
-#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
-#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
-#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
-
-#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
- ((__PRESCALER__) == IWDG_PRESCALER_8) || \
- ((__PRESCALER__) == IWDG_PRESCALER_16) || \
- ((__PRESCALER__) == IWDG_PRESCALER_32) || \
- ((__PRESCALER__) == IWDG_PRESCALER_64) || \
- ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
- ((__PRESCALER__) == IWDG_PRESCALER_256))
-
+ */
+#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
/**
* @}
*/
-/** @defgroup IWDG_Reload_Value IWDG Reload Value
+/** @defgroup IWDG_Window IWDG Window
* @{
- */
-#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
+ */
+#define IWDG_WINDOW_DISABLE ((uint32_t)0x00000FFF)
/**
* @}
*/
-/** @defgroup IWDG_CounterWindow_Value IWDG CounterWindow Value
- * @{
- */
-#define IS_IWDG_WINDOW(__VALUE__) ((__VALUE__) <= 0xFFF)
-/**
- * @}
- */
-/** @defgroup IWDG_Window_option IWDG Window option
- * @{
- */
-#define IWDG_WINDOW_DISABLE 0xFFF
-/**
- * @}
- */
-
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
+ * @{
+ */
-/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
- * @{
- */
-
-/** @brief Reset IWDG handle state
+/** @brief Reset IWDG handle state.
* @param __HANDLE__: IWDG handle.
* @retval None
*/
-#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
+#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
/**
- * @brief Enables the IWDG peripheral.
+ * @brief Enable the IWDG peripheral.
* @param __HANDLE__: IWDG handle
* @retval None
*/
-#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_ENABLE)
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/**
- * @brief Reloads IWDG counter with value defined in the reload register
- * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @brief Reload IWDG counter with value defined in the reload register.
* @param __HANDLE__: IWDG handle
* @retval None
*/
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_RELOAD)
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
/**
- * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
- * @param __HANDLE__: IWDG handle
- * @retval None
- */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_EWA)
-
-/**
- * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
- * @param __HANDLE__: IWDG handle
- * @retval None
- */
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_DWA)
-
-/**
- * @brief Gets the selected IWDG's flag status.
+ * @brief Get the selected IWDG flag status.
* @param __HANDLE__: IWDG handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
@@ -245,14 +173,13 @@
* @arg IWDG_FLAG_WVU: Watchdog counter window value flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
-
/** @addtogroup IWDG_Exported_Functions
* @{
*/
@@ -262,45 +189,115 @@
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
-void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
-
+void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
-
+
/** @addtogroup IWDG_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
-
/**
* @}
*/
-
+
/** @addtogroup IWDG_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions ************************************************/
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
/**
* @}
- */
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup IWDG_Private_Defines
+ * @{
+ */
+/**
+ * @brief IWDG Key Register BitMask
+ */
+#define IWDG_KEY_RELOAD ((uint32_t)0x0000AAAA) /*!< IWDG Reload Counter Enable */
+#define IWDG_KEY_ENABLE ((uint32_t)0x0000CCCC) /*!< IWDG Peripheral Enable */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x00005555) /*!< IWDG KR Write Access Enable */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x00000000) /*!< IWDG KR Write Access Disable */
+
+/**
+ * @brief IWDG Flag definition
+ */
+#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */
+#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */
+#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update flag */
/**
* @}
- */
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Macro IWDG Private Macros
+ * @{
+ */
+/**
+ * @brief Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+
+/**
+ * @brief Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
+ * @param __HANDLE__: IWDG handle
+ * @retval None
+ */
+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+
+/**
+ * @brief Check IWDG prescaler value.
+ * @param __PRESCALER__: IWDG prescaler value
+ * @retval None
+ */
+#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_8) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+ ((__PRESCALER__) == IWDG_PRESCALER_256))
+
+/**
+ * @brief Check IWDG reload value.
+ * @param __RELOAD__: IWDG reload value
+ * @retval None
+ */
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
+
+/**
+ * @brief Check IWDG window value.
+ * @param __WINDOW__: IWDG window value
+ * @retval None
+ */
+#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0xFFF)
/**
* @}
- */
+ */
/**
* @}
- */
-
+ */
+
+/**
+ * @}
+ */
+
+
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -28,7 +28,7 @@
(#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
(##) Enable the PCD/USB Low Level interface clock using
- (+++) __USB_CLK_ENABLE);
+ (+++) __HAL_RCC_USB_CLK_ENABLE);
(##) Initialize the related GPIO clocks
(##) Configure PCD pin-out
@@ -44,7 +44,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -74,15 +74,15 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
#ifdef HAL_PCD_MODULE_ENABLED
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
-/** @addtogroup STM32F0xx_HAL_Driver
- * @{
- */
-
-/** @defgroup PCD PCD HAL module driver
+/** @defgroup PCD PCD
* @brief PCD HAL module driver
* @{
*/
@@ -110,8 +110,8 @@
/**
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup PCD_Exported_Functions PCD Exported Functions
* @{
*/
@@ -150,11 +150,17 @@
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
- hpcd->State = PCD_BUSY;
+ if(hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hpcd->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_PCD_MspInit(hpcd);
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_PCD_MspInit(hpcd);
+ }
+ hpcd->State = HAL_PCD_STATE_BUSY;
+
/* Init endpoints structures */
for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
{
@@ -200,7 +206,7 @@
hpcd->Instance->CNTR = wInterrupt_Mask;
hpcd->USB_Address = 0;
- hpcd->State= PCD_READY;
+ hpcd->State= HAL_PCD_STATE_READY;
return HAL_OK;
}
@@ -218,7 +224,7 @@
return HAL_ERROR;
}
- hpcd->State = PCD_BUSY;
+ hpcd->State = HAL_PCD_STATE_BUSY;
/* Stop Device */
HAL_PCD_Stop(hpcd);
@@ -226,7 +232,7 @@
/* DeInit the low level hardware */
HAL_PCD_MspDeInit(hpcd);
- hpcd->State = PCD_READY;
+ hpcd->State = HAL_PCD_STATE_RESET;
return HAL_OK;
}
@@ -275,7 +281,7 @@
*/
/**
- * @brief Start The USB OTG Device.
+ * @brief Start the USB device.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -288,7 +294,7 @@
}
/**
- * @brief Stop The USB OTG Device.
+ * @brief Stop the USB device.
* @param hpcd: PCD handle
* @retval HAL status
*/
@@ -308,234 +314,7 @@
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
-/**
- * @}
- */
-
-/**
- * @}
- */
-/** @addtogroup PCD_Private_Functions PCD Private Functions
- * @{
- */
-/**
- * @brief This function handles PCD Endpoint interrupt request.
- * @param hpcd: PCD handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
-{
- PCD_EPTypeDef *ep;
- uint16_t count=0;
- uint8_t EPindex;
- __IO uint16_t wIstr;
- __IO uint16_t wEPVal = 0;
-
- /* stay in loop while pending interrupts */
- while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0)
- {
- /* extract highest priority endpoint number */
- EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
-
- if (EPindex == 0)
- {
- /* Decode and service control endpoint interrupt */
-
- /* DIR bit = origin of the interrupt */
- if ((wIstr & USB_ISTR_DIR) == 0)
- {
- /* DIR = 0 */
-
- /* DIR = 0 => IN int */
- /* DIR = 0 implies that (EP_CTR_TX = 1) always */
- PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
- ep = &hpcd->IN_ep[0];
-
- ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- ep->xfer_buff += ep->xfer_count;
-
- /* TX COMPLETE */
- HAL_PCD_DataInStageCallback(hpcd, 0);
-
-
- if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0))
- {
- hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
- hpcd->USB_Address = 0;
- }
-
- }
- else
- {
- /* DIR = 1 */
-
- /* DIR = 1 & CTR_RX => SETUP or OUT int */
- /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
- ep = &hpcd->OUT_ep[0];
- wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
-
- if ((wEPVal & USB_EP_SETUP) != 0)
- {
- /* Get SETUP Packet*/
- ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
- /* SETUP bit kept frozen while CTR_RX = 1*/
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-
- /* Process SETUP Packet*/
- HAL_PCD_SetupStageCallback(hpcd);
- }
-
- else if ((wEPVal & USB_EP_CTR_RX) != 0)
- {
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
- /* Get Control Data OUT Packet*/
- ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-
- if (ep->xfer_count != 0)
- {
- PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
- ep->xfer_buff+=ep->xfer_count;
- }
-
- /* Process Control Data OUT Packet*/
- HAL_PCD_DataOutStageCallback(hpcd, 0);
-
- PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
- PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
- }
- }
- }
- else
- {
-
- /* Decode and service non control endpoints interrupt */
-
- /* process related endpoint register */
- wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex);
- if ((wEPVal & USB_EP_CTR_RX) != 0)
- {
- /* clear int flag */
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex);
- ep = &hpcd->OUT_ep[EPindex];
-
- /* OUT double Buffering*/
- if (ep->doublebuffer == 0)
- {
- count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- if (count != 0)
- {
- PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
- }
- }
- else
- {
- if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
- {
- /*read from endpoint BUF0Addr buffer*/
- count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (count != 0)
- {
- PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
- }
- }
- else
- {
- /*read from endpoint BUF1Addr buffer*/
- count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (count != 0)
- {
- PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
- }
- }
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);
- }
- /*multi-packet on the NON control OUT endpoint*/
- ep->xfer_count+=count;
- ep->xfer_buff+=count;
-
- if ((ep->xfer_len == 0) || (count < ep->maxpacket))
- {
- /* RX COMPLETE */
- HAL_PCD_DataOutStageCallback(hpcd, ep->num);
- }
- else
- {
- HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
- }
-
- } /* if((wEPVal & EP_CTR_RX) */
-
- if ((wEPVal & USB_EP_CTR_TX) != 0)
- {
- ep = &hpcd->IN_ep[EPindex];
-
- /* clear int flag */
- PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex);
-
- /* IN double Buffering*/
- if (ep->doublebuffer == 0)
- {
- ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0)
- {
- PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
- }
- }
- else
- {
- if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
- {
- /*read from endpoint BUF0Addr buffer*/
- ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0)
- {
- PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
- }
- }
- else
- {
- /*read from endpoint BUF1Addr buffer*/
- ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0)
- {
- PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
- }
- }
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);
- }
- /*multi-packet on the NON control IN endpoint*/
- ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- ep->xfer_buff+=ep->xfer_count;
-
- /* Zero Length Packet? */
- if (ep->xfer_len == 0)
- {
- /* TX COMPLETE */
- HAL_PCD_DataInStageCallback(hpcd, ep->num);
- }
- else
- {
- HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
- }
- }
- }
- }
- return HAL_OK;
-}
-/**
- * @}
- */
-
-/** @addtogroup PCD_Exported_Functions
- * @{
- */
-
-/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
- * @{
- */
-
/**
* @brief This function handles PCD interrupt request.
* @param hpcd: PCD handle
@@ -641,7 +420,7 @@
}
/**
* @brief Setup stage callback
- * @param hpcd: ppp handle
+ * @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
@@ -739,7 +518,7 @@
/**
* @brief Disconnection event callbacks
- * @param hpcd: ppp handle
+ * @param hpcd: PCD handle
* @retval None
*/
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
@@ -851,7 +630,7 @@
__HAL_LOCK(hpcd);
-/* initialize Endpoint */
+ /* initialize Endpoint */
switch (ep->type)
{
case PCD_EP_TYPE_CTRL:
@@ -1108,18 +887,20 @@
}
else
{
- /*Set the Double buffer counter*/
- PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
-
/*Write the data to the USB endpoint*/
if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX)
{
+ /*Set the Double buffer counter for pmabuffer1*/
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
}
else
{
+ /*Set the Double buffer counter for pmabuffer0*/
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
}
+
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in);
}
@@ -1229,22 +1010,22 @@
}
/**
- * @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling
+ * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling
* @param hpcd: PCD handle
- * @retval status
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
hpcd->Instance->CNTR |= USB_CNTR_RESUME;
return HAL_OK;
}
/**
- * @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling
+ * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling
* @param hpcd: PCD handle
- * @retval status
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME);
return HAL_OK;
@@ -1253,9 +1034,37 @@
* @}
*/
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State functions #####
+ ===============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the PCD state
+ * @param hpcd : PCD handle
+ * @retval HAL state
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+{
+ return hpcd->State;
+}
/**
* @}
- */
+ */
+
+/**
+ * @}
+ */
/** @addtogroup PCD_Private_Functions
* @{
@@ -1306,49 +1115,215 @@
pbUsrBuf++;
}
}
-/**
- * @}
- */
-
-/** @addtogroup PCD_Exported_Functions
- * @{
- */
-
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permit to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
/**
- * @brief Return the PCD state
- * @param hpcd : PCD handle
- * @retval HAL state
+ * @brief This function handles PCD Endpoint interrupt request.
+ * @param hpcd: PCD handle
+ * @retval HAL status
*/
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
- return hpcd->State;
+ PCD_EPTypeDef *ep;
+ uint16_t count=0;
+ uint8_t EPindex;
+ __IO uint16_t wIstr;
+ __IO uint16_t wEPVal = 0;
+
+ /* stay in loop while pending interrupts */
+ while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0)
+ {
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
+
+ if (EPindex == 0)
+ {
+ /* Decode and service control endpoint interrupt */
+
+ /* DIR bit = origin of the interrupt */
+ if ((wIstr & USB_ISTR_DIR) == 0)
+ {
+ /* DIR = 0 */
+
+ /* DIR = 0 => IN int */
+ /* DIR = 0 implies that (EP_CTR_TX = 1) always */
+ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+ ep = &hpcd->IN_ep[0];
+
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ ep->xfer_buff += ep->xfer_count;
+
+ /* TX COMPLETE */
+ HAL_PCD_DataInStageCallback(hpcd, 0);
+
+
+ if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0))
+ {
+ hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
+ hpcd->USB_Address = 0;
+ }
+
+ }
+ else
+ {
+ /* DIR = 1 */
+
+ /* DIR = 1 & CTR_RX => SETUP or OUT int */
+ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+ ep = &hpcd->OUT_ep[0];
+ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+
+ if ((wEPVal & USB_EP_SETUP) != 0)
+ {
+ /* Get SETUP Packet*/
+ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+ PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
+ /* SETUP bit kept frozen while CTR_RX = 1*/
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+
+ /* Process SETUP Packet*/
+ HAL_PCD_SetupStageCallback(hpcd);
+ }
+
+ else if ((wEPVal & USB_EP_CTR_RX) != 0)
+ {
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+ /* Get Control Data OUT Packet*/
+ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_count != 0)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+ ep->xfer_buff+=ep->xfer_count;
+ }
+
+ /* Process Control Data OUT Packet*/
+ HAL_PCD_DataOutStageCallback(hpcd, 0);
+
+ PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ }
+ }
+ }
+ else
+ {
+
+ /* Decode and service non control endpoints interrupt */
+
+ /* process related endpoint register */
+ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex);
+ if ((wEPVal & USB_EP_CTR_RX) != 0)
+ {
+ /* clear int flag */
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex);
+ ep = &hpcd->OUT_ep[EPindex];
+
+ /* OUT double Buffering*/
+ if (ep->doublebuffer == 0)
+ {
+ count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+ if (count != 0)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
+ }
+ }
+ else
+ {
+ if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
+ {
+ /*read from endpoint BUF0Addr buffer*/
+ count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ if (count != 0)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+ }
+ }
+ else
+ {
+ /*read from endpoint BUF1Addr buffer*/
+ count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ if (count != 0)
+ {
+ PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+ }
+ }
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);
+ }
+ /*multi-packet on the NON control OUT endpoint*/
+ ep->xfer_count+=count;
+ ep->xfer_buff+=count;
+
+ if ((ep->xfer_len == 0) || (count < ep->maxpacket))
+ {
+ /* RX COMPLETE */
+ HAL_PCD_DataOutStageCallback(hpcd, ep->num);
+ }
+ else
+ {
+ HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ }
+
+ } /* if((wEPVal & EP_CTR_RX) */
+
+ if ((wEPVal & USB_EP_CTR_TX) != 0)
+ {
+ ep = &hpcd->IN_ep[EPindex];
+
+ /* clear int flag */
+ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex);
+
+ /* IN double Buffering*/
+ if (ep->doublebuffer == 0)
+ {
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
+ }
+ }
+ else
+ {
+ if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
+ {
+ /*read from endpoint BUF0Addr buffer*/
+ ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
+ }
+ }
+ else
+ {
+ /*read from endpoint BUF1Addr buffer*/
+ ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ if (ep->xfer_count != 0)
+ {
+ PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
+ }
+ }
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);
+ }
+ /*multi-packet on the NON control IN endpoint*/
+ ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ ep->xfer_buff+=ep->xfer_count;
+
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0)
+ {
+ /* TX COMPLETE */
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
+ }
+ else
+ {
+ HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ }
+ }
+ }
+ }
+ return HAL_OK;
}
/**
* @}
*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
/**
* @}
@@ -1357,4 +1332,8 @@
#endif /* HAL_PCD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -62,25 +62,30 @@
*/
/**
- * @brief PCD State structures definition
+ * @brief PCD State structure definition
*/
typedef enum
{
- PCD_READY = 0x00,
- PCD_ERROR = 0x01,
- PCD_BUSY = 0x02,
- PCD_TIMEOUT = 0x03
+ HAL_PCD_STATE_RESET = 0x00,
+ HAL_PCD_STATE_READY = 0x01,
+ HAL_PCD_STATE_ERROR = 0x02,
+ HAL_PCD_STATE_BUSY = 0x03,
+ HAL_PCD_STATE_TIMEOUT = 0x04
} PCD_StateTypeDef;
+/**
+ * @brief PCD double buffered endpoint direction
+ */
typedef enum
{
- /* double buffered endpoint direction */
PCD_EP_DBUF_OUT,
PCD_EP_DBUF_IN,
PCD_EP_DBUF_ERR,
}PCD_EP_DBUF_DIR;
-/* endpoint buffer number */
+/**
+ * @brief PCD endpoint buffer number
+ */
typedef enum
{
PCD_EP_NOBUF,
@@ -93,31 +98,31 @@
*/
typedef struct
{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
- This parameter depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref PCD_Core_Speed */
-
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
- This parameter can be any value of @ref PCD_EP0_MPS */
-
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref PCD_Core_PHY */
-
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t low_power_enable; /*!< Enable or disable Low Power mode
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t lpm_enable; /*!< Enable or disable the Link Power Management .
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.
- This parameter can be set to ENABLE or DISABLE */
-
+ uint32_t dev_endpoints; /*!< Device Endpoints number.
+ This parameter depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref PCD_Core_Speed */
+
+ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
+ This parameter can be any value of @ref PCD_EP0_MPS */
+
+ uint32_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref PCD_Core_PHY */
+
+ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t low_power_enable; /*!< Enable or disable Low Power mode
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t lpm_enable; /*!< Enable or disable the Link Power Management .
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.
+ This parameter can be set to ENABLE or DISABLE */
+
}PCD_InitTypeDef;
typedef struct
@@ -136,16 +141,13 @@
uint16_t pmaadress; /*!< PMA Address
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
-
-
+
uint16_t pmaaddr0; /*!< PMA Address0
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
-
-
+
uint16_t pmaaddr1; /*!< PMA Address1
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
-
-
+
uint8_t doublebuffer; /*!< Double buffer enable
This parameter can be 0 or 1 */
@@ -153,7 +155,6 @@
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
-
uint32_t xfer_len; /*!< Current transfer length */
@@ -168,15 +169,15 @@
*/
typedef struct
{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- __IO uint8_t USB_Address; /*!< USB Address */
- PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- void *pData; /*!< Pointer to upper stack Handler */
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ void *pData; /*!< Pointer to upper stack Handler */
} PCD_HandleTypeDef;
@@ -184,7 +185,9 @@
* @}
*/
-#include "stm32f0xx_hal_pcd_ex.h"
+/* Include PCD HAL Extension module */
+#include "stm32f0xx_hal_pcd_ex.h"
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
@@ -206,6 +209,112 @@
/**
* @}
*/
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* I/O operation functions ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PCD_Private_Constants PCD Private Constants
+ * @{
+ */
+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
+ * @{
+ */
+#define USB_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR_MR18) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+/**
+ * @}
+ */
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
* @{
@@ -226,63 +335,44 @@
/** @defgroup PCD_EP_Type PCD EP Type
* @{
*/
-#define PCD_EP_TYPE_CTRL 0
-#define PCD_EP_TYPE_ISOC 1
-#define PCD_EP_TYPE_BULK 2
-#define PCD_EP_TYPE_INTR 3
+#define PCD_EP_TYPE_CTRL 0
+#define PCD_EP_TYPE_ISOC 1
+#define PCD_EP_TYPE_BULK 2
+#define PCD_EP_TYPE_INTR 3
/**
* @}
*/
-/** @defgroup PCD_ENDP_Type PCD_ENDP_Type
+/** @defgroup PCD_ENDP PCD ENDP
* @{
*/
+#define PCD_ENDP0 ((uint8_t)0)
+#define PCD_ENDP1 ((uint8_t)1)
+#define PCD_ENDP2 ((uint8_t)2)
+#define PCD_ENDP3 ((uint8_t)3)
+#define PCD_ENDP4 ((uint8_t)4)
+#define PCD_ENDP5 ((uint8_t)5)
+#define PCD_ENDP6 ((uint8_t)6)
+#define PCD_ENDP7 ((uint8_t)7)
+/**
+ * @}
+ */
-#define PCD_ENDP0 ((uint8_t)0)
-#define PCD_ENDP1 ((uint8_t)1)
-#define PCD_ENDP2 ((uint8_t)2)
-#define PCD_ENDP3 ((uint8_t)3)
-#define PCD_ENDP4 ((uint8_t)4)
-#define PCD_ENDP5 ((uint8_t)5)
-#define PCD_ENDP6 ((uint8_t)6)
-#define PCD_ENDP7 ((uint8_t)7)
-
-/* Endpoint Kind */
-#define PCD_SNG_BUF 0
-#define PCD_DBL_BUF 1
-
-#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
+/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
+ * @{
+ */
+#define PCD_SNG_BUF 0
+#define PCD_DBL_BUF 1
/**
* @}
- */
+ */
/**
* @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup PCD_Exported_Macros PCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
*/
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
-
-#define USB_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
-#define __HAL_USB_EXTI_ENABLE_IT() EXTI->IMR |= USB_EXTI_LINE_WAKEUP
-#define __HAL_USB_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_EXTI_LINE_WAKEUP)
-#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
-
-/**
- * @}
- */
-
-/* Internal macros -----------------------------------------------------------*/
-
-/** @defgroup PCD_Private_Macros PCD Private Macros
- * @brief macros to handle interrupts and specific clock configurations
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup PCD_Private_Macros PCD Private Macros
* @{
*/
@@ -662,7 +752,7 @@
{PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));}\
else if((bDir) == PCD_EP_DBUF_IN)\
/* IN endpoint */\
- *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
+ *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
} /* SetEPDblBuf1Count */
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
@@ -679,81 +769,10 @@
#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup PCD_Exported_Functions
- * @{
- */
-
-/** @addtogroup PCD_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-
-/**
- * @}
- */
-
-/** @addtogroup PCD_Exported_Functions_Group2
+/** @defgroup PCD_Instance_definition PCD Instance definition
* @{
*/
-/* IO operation functions *****************************************************/
- /* Non Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-
-/**
- * @}
- */
-
-/** @addtogroup PCD_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/** @addtogroup PCD_Exported_Functions_Group4
- * @{
- */
-/* Peripheral State functions **************************************************/
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pcd_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Extended PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -42,36 +42,39 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
#ifdef HAL_PCD_MODULE_ENABLED
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
-/** @addtogroup STM32F0xx_HAL_Driver
+/** @defgroup PCDEx PCDEx
+ * @brief PCD Extended HAL module driver
* @{
*/
-/** @defgroup PCDEx PCDEx Extended HAL module driver
- * @brief PCDEx PCDEx Extended HAL module driver
- * @{
- */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/
-
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
-/** @defgroup PCDEx_Exported_Functions_Group2 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+ * @brief PCDEx control functions
+ *
@verbatim
===============================================================================
- ##### Peripheral extended features methods #####
+ ##### Extended Peripheral Control functions #####
===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Update PMA configuration
+
@endverbatim
* @{
*/
@@ -116,7 +119,7 @@
{
/*Single Buffer*/
ep->doublebuffer = 0;
- /*Configure te PMA*/
+ /*Configure the PMA*/
ep->pmaadress = (uint16_t)pmaadress;
}
else /*USB_DBL_BUF*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pcd_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_pcd_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of PCD HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -61,15 +61,12 @@
/* Exported macros -----------------------------------------------------------*/
/* Internal macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup PCDEx_Exported_Functions
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
-
-/** @addtogroup PCDEx_Exported_Functions_Group2
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @{
- */
-
+ */
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -48,7 +48,7 @@
* @{
*/
-/** @defgroup PWR PWR HAL module Driver
+/** @defgroup PWR PWR
* @brief PWR HAL module driver
* @{
*/
@@ -79,7 +79,7 @@
write accesses.
To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
- __PWR_CLK_ENABLE() macro.
+ __HAL_RCC_PWR_CLK_ENABLE() macro.
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
@endverbatim
@@ -92,13 +92,13 @@
*/
void HAL_PWR_DeInit(void)
{
- __PWR_FORCE_RESET();
- __PWR_RELEASE_RESET();
+ __HAL_RCC_PWR_FORCE_RESET();
+ __HAL_RCC_PWR_RELEASE_RESET();
}
/**
* @brief Enables access to the backup domain (RTC registers, RTC
- * backup data registers).
+ * backup data registers when present).
* @note If the HSE divided by 32 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
@@ -110,7 +110,7 @@
/**
* @brief Disables access to the backup domain (RTC registers, RTC
- * backup data registers).
+ * backup data registers when present).
* @note If the HSE divided by 32 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_pwr.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @addtogroup PWR PWR HAL module Driver
+/** @addtogroup PWR PWR
* @{
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -47,7 +47,7 @@
* @{
*/
-/** @defgroup PWREx PWREx Extended HAL module driver
+/** @defgroup PWREx PWREx
* @brief PWREx HAL module driver
* @{
*/
@@ -93,7 +93,7 @@
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if enabled. This is done through
- HAL_PWR_PVDConfig(), HAL_PWR_EnablePVD() functions.
+ HAL_PWR_ConfigPVD(), HAL_PWR_EnablePVD() functions.
(+) The PVD is stopped in Standby mode.
-@- PVD is not available on STM32F030x4/x6/x8
@@ -104,7 +104,7 @@
to VREFInt Voltage
(+) This monitor is internally connected to the EXTI line31
and can generate an interrupt if enabled. This is done through
- HAL_PWR_EnableVddio2Monitor() function.
+ HAL_PWREx_EnableVddio2Monitor() function.
-@- VDDIO2 is available on STM32F07x/09x/04x
@endverbatim
@@ -123,7 +123,7 @@
* detection level.
* @retval None
*/
-void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD)
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
{
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
@@ -135,7 +135,7 @@
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
__HAL_PWR_PVD_EXTI_DISABLE_IT();
- __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER();
+ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
/* Configure interrupt mode */
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
@@ -152,12 +152,12 @@
/* Configure the edge */
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
- __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER();
+ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
}
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
- __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER();
+ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
}
}
@@ -222,20 +222,20 @@
NVIS has to be enable by user.
* @retval None
*/
-void HAL_PWR_EnableVddio2Monitor(void)
+void HAL_PWREx_EnableVddio2Monitor(void)
{
__HAL_PWR_VDDIO2_EXTI_ENABLE_IT();
- __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER();
+ __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE();
}
/**
* @brief Disable the Vddio2 Monitor.
* @retval None
*/
-void HAL_PWR_DisableVddio2Monitor(void)
+void HAL_PWREx_DisableVddio2Monitor(void)
{
__HAL_PWR_VDDIO2_EXTI_DISABLE_IT();
- __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER();
+ __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE();
}
@@ -244,13 +244,13 @@
* @note This API should be called under the VDDIO2_IRQHandler() PVD_VDDIO2_IRQHandler().
* @retval None
*/
-void HAL_PWR_Vddio2Monitor_IRQHandler(void)
+void HAL_PWREx_Vddio2Monitor_IRQHandler(void)
{
/* Check PWR exti flag */
if(__HAL_PWR_VDDIO2_EXTI_GET_FLAG() != RESET)
{
/* PWR Vddio2 monitor interrupt user callback */
- HAL_PWR_Vddio2MonitorCallback();
+ HAL_PWREx_Vddio2MonitorCallback();
/* Clear PWR Exti pending bit */
__HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG();
@@ -261,10 +261,10 @@
* @brief PWR Vddio2 Monitor interrupt callback
* @retval None
*/
-__weak void HAL_PWR_Vddio2MonitorCallback(void)
+__weak void HAL_PWREx_Vddio2MonitorCallback(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_PWR_Vddio2MonitorCallback could be implemented in the user file
+ the HAL_PWREx_Vddio2MonitorCallback could be implemented in the user file
*/
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_pwr_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_pwr_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -130,7 +130,7 @@
defined (STM32F071xB) || defined (STM32F072xB) || \
defined (STM32F091xC)
-#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
/* defined (STM32F071xB) || defined (STM32F072xB) || */
@@ -140,7 +140,7 @@
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx)
-#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)0x80000000) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */
+#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */
#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
@@ -255,23 +255,41 @@
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
/**
- * @brief PVD EXTI line configuration: clear falling edge and rising edge trigger.
+ * @brief Disable the PVD Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() EXTI->FTSR &= ~(PWR_EXTI_LINE_PVD); \
- EXTI->RTSR &= ~(PWR_EXTI_LINE_PVD)
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
+
/**
* @brief PVD EXTI line configuration: set falling edge trigger.
* @retval None.
*/
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
/**
* @brief PVD EXTI line configuration: set rising edge trigger.
* @retval None.
*/
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
+
+/**
+ * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
+ * @retval None
+ */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
/**
* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
@@ -315,14 +333,14 @@
* @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger.
* @retval None.
*/
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER() EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \
+#define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \
EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2)
/**
* @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger.
* @retval None.
*/
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2)
+#define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2)
/**
* @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not.
@@ -373,8 +391,8 @@
#if defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx)
-void HAL_PWR_Vddio2Monitor_IRQHandler(void);
-void HAL_PWR_Vddio2MonitorCallback(void);
+void HAL_PWREx_Vddio2Monitor_IRQHandler(void);
+void HAL_PWREx_Vddio2MonitorCallback(void);
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx) */
@@ -383,7 +401,7 @@
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
defined (STM32F071xB) || defined (STM32F072xB) || \
defined (STM32F091xC)
-void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
@@ -393,8 +411,8 @@
#if defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx)
-void HAL_PWR_EnableVddio2Monitor(void);
-void HAL_PWR_DisableVddio2Monitor(void);
+void HAL_PWREx_EnableVddio2Monitor(void);
+void HAL_PWREx_DisableVddio2Monitor(void);
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx) */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,21 +2,21 @@
******************************************************************************
* @file stm32f0xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief RCC HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
- *
- @verbatim
+ *
+ @verbatim
==============================================================================
##### RCC specific features #####
==============================================================================
- [..]
+ [..]
After reset the device is running from Internal High Speed oscillator
- (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is disabled,
+ (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
and all peripherals are off except internal SRAM, Flash and JTAG.
(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
all peripherals mapped on these busses are running at HSI speed.
@@ -26,10 +26,10 @@
[..] Once the device started from reset, the user application has to:
(+) Configure the clock source to be used to drive the System clock
(if the application needs higher frequency/performance)
- (+) Configure the System clock frequency and Flash settings
+ (+) Configure the System clock frequency and Flash settings
(+) Configure the AHB and APB busses prescalers
(+) Enable the clock for the peripheral(s) to be used
- (+) Configure the clock source(s) for peripherals which clocks are not
+ (+) Configure the clock source(s) for peripherals whose clocks are not
derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..)
##### RCC Limitations #####
@@ -37,25 +37,20 @@
[..]
A delay between an RCC peripheral clock enable and the effective peripheral
enabling should be taken into account in order to manage the peripheral read/write
- from/to registeres.
+ from/to registers.
(+) This delay depends on the peripheral mapping.
- (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
- after the clock enable bit is set on the hardware register
- (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
- after the clock enable bit is set on the hardware register
+ (++) AHB & APB peripherals, 1 dummy read is necessary
[..]
- Possible Workarounds:
- (#) Enable the peripheral clock sometimes before the peripheral read/write
- register is required.
- (#) For AHB peripheral, insert two dummy read to the peripheral register.
- (#) For APB peripheral, insert a dummy read to the peripheral register.
-
-@endverbatim
+ Workarounds:
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+ inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+ @endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -79,8 +74,8 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
- */
+ ******************************************************************************
+*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@@ -89,8 +84,8 @@
* @{
*/
-/** @defgroup RCC RCC HAL module driver
- * @brief RCC HAL module driver
+/** @defgroup RCC RCC
+* @brief RCC HAL module driver
* @{
*/
@@ -98,22 +93,21 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup RCC_Private_Define RCC Private Define
- * @{
- */
-#define RCC_CFGR_HPRE_BITNUMBER 4
-#define RCC_CFGR_PPRE_BITNUMBER 8
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
/**
* @}
*/
-
/* Private macro -------------------------------------------------------------*/
/** @defgroup RCC_Private_Macros RCC Private Macros
* @{
*/
-#define __MCO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
-#define MCO_GPIO_PORT GPIOA
-#define MCO_PIN GPIO_PIN_8
+
+#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT GPIOA
+#define MCO1_PIN GPIO_PIN_8
+
/**
* @}
*/
@@ -122,96 +116,95 @@
/** @defgroup RCC_Private_Variables RCC Private Variables
* @{
*/
-const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
/** @defgroup RCC_Exported_Functions RCC Exported Functions
* @{
*/
-/** @defgroup RCC_Exported_Functions_Group1 Initialization/de-initialization function
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+ @verbatim
+ ===============================================================================
##### Initialization and de-initialization function #####
- ===============================================================================
+ ===============================================================================
[..]
- This section provide functions allowing to configure the internal/external oscillators
+ This section provides functions allowing to configure the internal/external oscillators
(HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK,
AHB and APB1).
[..] Internal/external clock and PLL configuration
- (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
- the PLL as System clock source.
+ (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
+ the PLL as System clock source.
The HSI clock can be used also to clock the USART and I2C peripherals.
- (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock
+ (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock
the ADC peripheral.
- (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
- clock source.
+ (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
+ clock source.
- (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
+ (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
+ through the PLL as System clock source. Can be used also as RTC clock source.
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
- (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks:
- (++) The first output is used to generate the high speed system clock (up to 48 MHz)
- (++) The second output is used to generate the clock for the USB FS (48 MHz)
- (++) The third output may be used to generate the clock for the TIM, I2C and USART
- peripherals (up to 48 MHz)
+ (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks:
+ (++) The first output is used to generate the high speed system clock (up to 48 MHz)
+ (++) The second output is used to generate the clock for the USB FS (48 MHz)
+ (++) The third output may be used to generate the clock for the TIM, I2C and USART
+ peripherals (up to 48 MHz)
- (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
- and if a HSE clock failure occurs(HSE used directly or through PLL as System
- clock source), the System clockis automatically switched to HSI and an interrupt
- is generated if enabled. The interrupt is linked to the Cortex-M0 NMI
- (Non-Maskable Interrupt) exception vector.
+ (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
+ and if a HSE clock failure occurs(HSE used directly or through PLL as System
+ clock source), the System clockis automatically switched to HSI and an interrupt
+ is generated if enabled. The interrupt is linked to the Cortex-M0 NMI
+ (Non-Maskable Interrupt) exception vector.
- (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
- clock (divided by 2) output on pin (such as PA8 pin).
+ (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
+ clock (divided by 2) output on pin (such as PA8 pin).
- [..] System, AHB and APB busses clocks configuration
- (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable
- prescaler and used to clock the CPU, memory and peripherals mapped
- on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived
- from AHB clock through configurable prescalers and used to clock
- the peripherals mapped on these busses. You can use
- "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+ [..] System, AHB and APB busses clocks configuration
+ (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+ HSE and PLL.
+ The AHB clock (HCLK) is derived from System clock through configurable
+ prescaler and used to clock the CPU, memory and peripherals mapped
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived
+ from AHB clock through configurable prescalers and used to clock
+ the peripherals mapped on these busses. You can use
+ "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
- (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
- (++) The FLASH program/erase clock which is always HSI 8MHz clock.
- (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
- (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
- (++) The I2C clock which can be derived as well from HSI 8MHz clock.
- (++) The ADC clock which is derived from PLL output.
- (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
- (HSE divided by a programmable prescaler). The System clock (SYSCLK)
- frequency must be higher or equal to the RTC clock frequency.
- (++) IWDG clock which is always the LSI clock.
+ (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
+ (++) The FLASH program/erase clock which is always HSI 8MHz clock.
+ (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
+ (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
+ (++) The I2C clock which can be derived as well from HSI 8MHz clock.
+ (++) The ADC clock which is derived from PLL output.
+ (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
+ (HSE divided by a programmable prescaler). The System clock (SYSCLK)
+ frequency must be higher or equal to the RTC clock frequency.
+ (++) IWDG clock which is always the LSI clock.
- (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz,
- Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
- +-----------------------------------------------+
- | Latency | SYSCLK clock frequency (MHz) |
- |---------------|-------------------------------|
- |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
- |---------------|-------------------------------|
- |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
- +-----------------------------------------------+
+ (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz,
+ Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
+ +-----------------------------------------------+
+ | Latency | SYSCLK clock frequency (MHz) |
+ |---------------|-------------------------------|
+ |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
+ |---------------|-------------------------------|
+ |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
+ +-----------------------------------------------+
- (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
- prefetch is disabled.
-
-@endverbatim
+ (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
+ prefetch is disabled.
+ @endverbatim
* @{
*/
@@ -221,11 +214,11 @@
* - HSI ON and used as system clock source
* - HSE and PLL OFF
* - AHB, APB1 prescaler set to 1.
- * - CSS, MCO OFF
+ * - CSS and MCO1 OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
* @retval None
*/
void HAL_RCC_DeInit(void)
@@ -252,7 +245,7 @@
CLEAR_REG(RCC->CFGR3);
/* Disable all interrupts */
- CLEAR_REG(RCC->CIR);
+ CLEAR_REG(RCC->CIR);
}
/**
@@ -263,26 +256,461 @@
* @note The PLL is not disabled when used as system clock.
* @retval HAL status
*/
-__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */
- /* handle the possible oscillators present in STM32F0xx devices */
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(RCC_OscInitStruct != NULL);
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
- /* Return error status as not implemented here */
- return HAL_ERROR;
+ /*------------------------------- HSE Configuration ------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+ /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new HSE configuration ---------------------------------------*/
+ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+ /* Check the HSE State */
+ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is bypassed or disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+ || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ /*------------------------------ LSE Configuration -------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set the new LSE configuration -----------------------------------------*/
+ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ /* Check the LSE State */
+ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /*----------------------------- HSI14 Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
+ assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
+
+ /* Check the HSI14 State */
+ if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
+ {
+ /* Disable ADC control of the Internal High Speed oscillator HSI14 */
+ __HAL_RCC_HSI14ADC_DISABLE();
+
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI14_ENABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
+ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
+ }
+ else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
+ {
+ /* Enable ADC control of the Internal High Speed oscillator HSI14 */
+ __HAL_RCC_HSI14ADC_ENABLE();
+
+ /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
+ __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
+ }
+ else
+ {
+ /* Disable ADC control of the Internal High Speed oscillator HSI14 */
+ __HAL_RCC_HSI14ADC_DISABLE();
+
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI14_DISABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+#if defined(RCC_CR2_HSI48ON)
+ /*----------------------------- HSI48 Configuration --------------------------*/
+ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
+
+ /* When the HSI48 is used as system clock it is not allowed to be disabled */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) ||
+ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))
+ {
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI48). */
+ __HAL_RCC_HSI48_ENABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI48). */
+ __HAL_RCC_HSI48_DISABLE();
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+#endif /* RCC_CR2_HSI48ON */
+
+ /*-------------------------------- PLL Configuration -----------------------*/
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+ if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not */
+ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
+ assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
+
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the main PLL clock source, predivider and multiplication factor. */
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PREDIV,
+ RCC_OscInitStruct->PLL.PLLMUL);
+ /* Enable the main PLL. */
+ __HAL_RCC_PLL_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is disabled */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ return HAL_OK;
}
/**
- * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
+ * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
* parameters in the RCC_ClkInitStruct.
* @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC peripheral.
- * @param FLatency: FLASH Latency
+ * @param FLatency: FLASH Latency
* This parameter can be one of the following values:
* @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
* @arg FLASH_LATENCY_1: FLASH 1 Latency cycle
- *
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated by HAL_RCC_GetHCLKFreq() function called within this function
*
@@ -290,82 +718,327 @@
* startup from Reset, wake-up from STOP and STANDBY mode, or in case
* of failure of the HSE used directly or indirectly as system clock
* (if the Clock Security System CSS is enabled).
- *
+ *
* @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
+ * clock source is ready (clock stable after startup delay or PLL locked).
* If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
+ * occur when the clock source will be ready.
+ * You can use HAL_RCC_GetClockConfig() function to know which clock is
+ * currently used as system clock source.
* @retval HAL status
*/
-__weak HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */
- /* handle the possible oscillators present in STM32F0xx devices */
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(RCC_ClkInitStruct != NULL);
+ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+ assert_param(IS_FLASH_LATENCY(FLatency));
+
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) of the device. */
- /* Return error status as not implemented here */
- return HAL_ERROR;
+ /* Increasing the CPU frequency */
+ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ return HAL_ERROR;
+ }
+
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+#if defined(RCC_CR2_HSI48ON)
+ /* HSI48 is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
+ {
+ /* Check the HSI48 ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+#endif /* RCC_CR2_HSI48ON */
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#if defined(RCC_CR2_HSI48ON)
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48)
+ {
+ if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif /* RCC_CR2_HSI48ON */
+ else
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /* Decreasing the CPU frequency */
+ else
+ {
+ /*-------------------------- HCLK Configuration --------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ }
+
+ /*------------------------- SYSCLK Configuration -------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ {
+ assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+ /* HSE is selected as System Clock Source */
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ /* Check the HSE ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ /* PLL is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ /* Check the PLL ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+#if defined(RCC_CR2_HSI48ON)
+ /* HSI48 is selected as System Clock Source */
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
+ {
+ /* Check the HSI48 ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+#endif /* RCC_CR2_HSI48ON */
+ /* HSI is selected as System Clock Source */
+ else
+ {
+ /* Check the HSI ready flag */
+ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ }
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#if defined(RCC_CR2_HSI48ON)
+ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48)
+ {
+ if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif /* RCC_CR2_HSI48ON */
+ else
+ {
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
+ {
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ __HAL_FLASH_SET_LATENCY(FLatency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
+ }
+
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick (TICK_INT_PRIORITY);
+
+ return HAL_OK;
}
/**
* @}
*/
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control function
- * @brief RCC clocks control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control function #####
- ===============================================================================
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief RCC clocks control functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to control the RCC Clocks
+ This subsection provides a set of functions allowing to control the RCC Clocks
frequencies.
-@endverbatim
+ @endverbatim
* @{
*/
/**
- * @brief Selects the clock source to output on MCO pin(such as PA8).
- * @note MCO pin (such as PA8) should be configured in alternate function mode.
+ * @brief Selects the clock source to output on MCO pin.
+ * @note MCO pin should be configured in alternate function mode.
* @param RCC_MCOx: specifies the output direction for the clock source.
* This parameter can be one of the following values:
- * @arg RCC_MCO: Clock source to output on MCO pin(such as PA8).
+ * @arg RCC_MCO: Clock source to output on MCO1 pin(PA8).
* @param RCC_MCOSource: specifies the clock source to output.
* This parameter can be one of the following values:
- * @arg RCC_MCOSOURCE_LSI: LSI clock selected as MCO source
- * @arg RCC_MCOSOURCE_HSI: HSI clock selected as MCO source
- * @arg RCC_MCOSOURCE_LSE: LSE clock selected as MCO source
- * @arg RCC_MCOSOURCE_HSE: HSE clock selected as MCO source
- * @arg RCC_MCOSOURCE_PLLCLK_NODIV: main PLL clock not divided selected as MCO source (not applicable to STM32F05x devices)
- * @arg RCC_MCOSOURCE_PLLCLK_DIV2: main PLL clock divided by 2 selected as MCO source
- * @arg RCC_MCOSOURCE_SYSCLK: System clock (SYSCLK) selected as MCO source
- * @param RCC_MCODiv: specifies the MCOx prescaler.
+ * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
+ * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
+ * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
+ * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
+ * @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock (not applicable to STM32F05x devices)
+ * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
+ * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
+ * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
+ * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
+ * @param RCC_MCODiv: specifies the MCO DIV.
* This parameter can be one of the following values:
- * @arg RCC_MCO_NODIV: no division applied to MCO clock
+ * @arg RCC_MCODIV_1: no division applied to MCO clock
* @retval None
*/
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
{
GPIO_InitTypeDef gpio;
+
/* Check the parameters */
assert_param(IS_RCC_MCO(RCC_MCOx));
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
- /* RCC_MCO */
- assert_param(IS_RCC_MCOSOURCE(RCC_MCOSource));
-
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
/* MCO Clock Enable */
- __MCO_CLK_ENABLE();
-
- /* Configue the MCO pin in alternate function mode */
- gpio.Pin = MCO_PIN;
+ MCO1_CLK_ENABLE();
+
+ /* Configure the MCO1 pin in alternate function mode */
+ gpio.Pin = MCO1_PIN;
gpio.Mode = GPIO_MODE_AF_PP;
gpio.Speed = GPIO_SPEED_HIGH;
gpio.Pull = GPIO_NOPULL;
gpio.Alternate = GPIO_AF0_MCO;
- HAL_GPIO_Init(MCO_GPIO_PORT, &gpio);
-
+ HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
+
/* Configure the MCO clock source */
__HAL_RCC_MCO_CONFIG(RCC_MCOSource, RCC_MCODiv);
}
@@ -375,13 +1048,13 @@
* @note If a failure is detected on the HSE oscillator clock, this oscillator
* is automatically disabled and an interrupt is generated to inform the
* software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
* @retval None
*/
void HAL_RCC_EnableCSS(void)
{
- SET_BIT(RCC->CR, RCC_CR_CSSON);
+ SET_BIT(RCC->CR, RCC_CR_CSSON) ;
}
/**
@@ -390,68 +1063,125 @@
*/
void HAL_RCC_DisableCSS(void)
{
- CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
+ CLEAR_BIT(RCC->CR, RCC_CR_CSSON) ;
}
/**
- * @brief Returns the SYSCLK frequency
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
+ * @brief Returns the SYSCLK frequency
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
- * @note If SYSCLK source is HSI, function returns a value based on HSI_VALUE(*)
- * @note If SYSCLK source is HSI48, function returns a value based on HSI48_VALUE(*)
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
* @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
* divided by PREDIV factor(**)
* @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
* divided by PREDIV factor(**) or depending on STM32F0xx devices either a value based
* on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the
* PLL factor .
- * @note (*) HSI_VALUE & HSI48_VALUE are constants defined in stm32f0xx_hal_conf.h file
- * (default values 8 MHz and 48MHz).
+ * @note (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
* @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
- *
+ *
* @note The result of this function could be not correct when using fractional
* value for HSE crystal.
- *
- * @note This function can be used by the user application to compute the
+ *
+ * @note This function can be used by the user application to compute the
* baudrate for the communication peripherals or configure other parameters.
- *
+ *
* @note Each time SYSCLK changes, this function must be called to update the
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
+ *
+ *
* @retval SYSCLK frequency
*/
-__weak uint32_t HAL_RCC_GetSysClockFreq(void)
+uint32_t HAL_RCC_GetSysClockFreq(void)
{
- /* Note : This function is defined into this file for library reference. */
- /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */
- /* handle the possible oscillators present in STM32F0xx devices */
+ const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9,
+ 10, 11, 12, 13, 14, 15, 16, 16};
+ const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8,
+ 9,10, 11, 12, 13, 14, 15, 16};
+
+ uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0;
+ uint32_t sysclockfreq = 0;
+
+ tmpreg = RCC->CFGR;
- /* Return error status as not implemented here */
- return HAL_ERROR;
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (tmpreg & RCC_CFGR_SWS)
+ {
+ case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
+ {
+ sysclockfreq = HSE_VALUE;
+ break;
+ }
+ case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
+ {
+ pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
+ prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
+ if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+ {
+ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
+ pllclk = (HSE_VALUE/prediv) * pllmul;
+ }
+#if defined(RCC_CR2_HSI48ON)
+ else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48)
+ {
+ /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */
+ pllclk = (HSI48_VALUE/prediv) * pllmul;
+ }
+#endif /* RCC_CR2_HSI48ON */
+ else
+ {
+#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
+ /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
+ pllclk = (HSI_VALUE/prediv) * pllmul;
+#else
+ /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
+ pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
+#endif
+ }
+ sysclockfreq = pllclk;
+ break;
+ }
+#if defined(RCC_CR2_HSI48ON)
+ case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */
+ {
+ sysclockfreq = HSI48_VALUE;
+ break;
+ }
+#endif /* RCC_CR2_HSI48ON */
+ case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ default: /* HSI used as system clock */
+ {
+ sysclockfreq = HSI_VALUE;
+ break;
+ }
+ }
+ return sysclockfreq;
}
/**
- * @brief Returns the HCLK frequency
+ * @brief Returns the HCLK frequency
* @note Each time HCLK changes, this function must be called to update the
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
- *
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
return SystemCoreClock;
}
/**
- * @brief Returns the PCLK1 frequency
+ * @brief Returns the PCLK1 frequency
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
@@ -459,27 +1189,34 @@
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE)>> RCC_CFGR_PPRE_BITNUMBER]);
-}
+ return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE)>> RCC_CFGR_PPRE_BITNUMBER]);
+}
/**
- * @brief Configures the RCC_OscInitStruct according to the internal
+ * @brief Configures the RCC_OscInitStruct according to the internal
* RCC configuration registers.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
* will be configured.
* @retval None
*/
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- /* Set all possible values for the Oscillator type parameter ---------------*/
- RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+ /* Check the parameters */
+ assert_param(RCC_OscInitStruct != NULL);
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
+ | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI14;
+#if defined(RCC_CR2_HSI48ON)
+ RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
+#endif /* RCC_CR2_HSI48ON */
+
/* Get the HSE configuration -----------------------------------------------*/
- if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
{
RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
}
- else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
+ else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
{
RCC_OscInitStruct->HSEState = RCC_HSE_ON;
}
@@ -487,9 +1224,9 @@
{
RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
}
-
+
/* Get the HSI configuration -----------------------------------------------*/
- if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
+ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
{
RCC_OscInitStruct->HSIState = RCC_HSI_ON;
}
@@ -497,15 +1234,15 @@
{
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
-
+
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber);
-
+
/* Get the LSE configuration -----------------------------------------------*/
- if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
{
RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
}
- else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
{
RCC_OscInitStruct->LSEState = RCC_LSE_ON;
}
@@ -513,9 +1250,9 @@
{
RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
}
-
+
/* Get the LSI configuration -----------------------------------------------*/
- if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
+ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
{
RCC_OscInitStruct->LSIState = RCC_LSI_ON;
}
@@ -523,9 +1260,9 @@
{
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
}
-
+
/* Get the PLL configuration -----------------------------------------------*/
- if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
+ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
{
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
}
@@ -536,7 +1273,7 @@
RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
-
+
/* Get the HSI14 configuration -----------------------------------------------*/
if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON)
{
@@ -548,35 +1285,40 @@
}
RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_CR2_HSI14TRIM_BitNumber);
-
+
+#if defined(RCC_CR2_HSI48ON)
/* Get the HSI48 configuration if any-----------------------------------------*/
RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE();
+#endif /* RCC_CR2_HSI48ON */
}
/**
- * @brief Get the RCC_ClkInitStruct according to the internal
+ * @brief Get the RCC_ClkInitStruct according to the internal
* RCC configuration registers.
- * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+ * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
* contains the current clock configuration.
* @param pFLatency: Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
+ /* Check the parameters */
+ assert_param(RCC_ClkInitStruct != NULL);
+ assert_param(pFLatency != NULL);
+
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1;
-
- /* Get the SYSCLK configuration --------------------------------------------*/
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-
- /* Get the HCLK configuration ----------------------------------------------*/
- RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
-
- /* Get the APB1 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE);
-
- /* Get the Flash Wait State (Latency) configuration ------------------------*/
- *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE);
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
}
/**
@@ -590,8 +1332,8 @@
if(__HAL_RCC_GET_IT(RCC_IT_CSS))
{
/* RCC Clock Security System interrupt user callback */
- HAL_RCC_CCSCallback();
-
+ HAL_RCC_CSSCallback();
+
/* Clear RCC CSS pending bit */
__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
}
@@ -601,11 +1343,11 @@
* @brief RCC Clock Security System interrupt callback
* @retval none
*/
-__weak void HAL_RCC_CCSCallback(void)
+__weak void HAL_RCC_CSSCallback(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_RCC_CCSCallback could be implemented in the user file
- */
+ the HAL_RCC_CSSCallback could be implemented in the user file
+ */
}
/**
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_RCC_H
@@ -52,53 +52,198 @@
/** @addtogroup RCC
* @{
+ */
+
+/** @addtogroup RCC_Private_Constants
+ * @{
+ */
+
+/** @defgroup RCC_Timeout RCC Timeout
+ * @{
+ */
+
+/* Disable Backup domain write protection state change timeout */
+#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+/* LSE state change timeout */
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
+#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Register_Offset Register offsets
+ * @{
+ */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+#define RCC_CR_OFFSET 0x00
+#define RCC_CFGR_OFFSET 0x04
+#define RCC_CIR_OFFSET 0x08
+#define RCC_BDCR_OFFSET 0x20
+#define RCC_CSR_OFFSET 0x24
+
+/**
+ * @}
*/
-/* Exported types ------------------------------------------------------------*/
+
+/* CR register byte 2 (Bits[23:16]) base address */
+#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
+
+/* CIR register byte 1 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
+
+/* CIR register byte 2 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
+
+/* Defines used for Flags */
+#define CR_REG_INDEX ((uint8_t)1)
+#define CR2_REG_INDEX 2
+#define BDCR_REG_INDEX 3
+#define CSR_REG_INDEX 4
+
+/* Flags in the CFGR register */
+#define RCC_CFGR_PLLMUL_BITNUMBER 18
+#define RCC_CFGR_HPRE_BITNUMBER 4
+#define RCC_CFGR_PPRE_BITNUMBER 8
+/* Flags in the CFGR2 register */
+#define RCC_CFGR2_PREDIV_BITNUMBER 0
+/* Flags in the CR register */
+#define RCC_CR_HSIRDY_BitNumber 1
+#define RCC_CR_HSERDY_BitNumber 17
+#define RCC_CR_PLLRDY_BitNumber 25
+/* Flags in the CR2 register */
+#define RCC_CR2_HSI14RDY_BitNumber 1
+#define RCC_CR2_HSI48RDY_BitNumber 16
+/* Flags in the BDCR register */
+#define RCC_BDCR_LSERDY_BitNumber 1
+/* Flags in the CSR register */
+#define RCC_CSR_LSIRDY_BitNumber 1
+#define RCC_CSR_V18PWRRSTF_BitNumber 23
+#define RCC_CSR_RMVF_BitNumber 24
+#define RCC_CSR_OBLRSTF_BitNumber 25
+#define RCC_CSR_PINRSTF_BitNumber 26
+#define RCC_CSR_PORRSTF_BitNumber 27
+#define RCC_CSR_SFTRSTF_BitNumber 28
+#define RCC_CSR_IWDGRSTF_BitNumber 29
+#define RCC_CSR_WWDGRSTF_BitNumber 30
+#define RCC_CSR_LPWRRSTF_BitNumber 31
+/* Flags in the HSITRIM register */
+#define RCC_CR_HSITRIM_BitNumber 3
+#define RCC_FLAG_MASK ((uint8_t)0x1F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+
+#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
+ ((__HSE__) == RCC_HSE_BYPASS))
+#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
+ ((__LSE__) == RCC_LSE_BYPASS))
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
+#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL))
+#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
+#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
+#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
+ ((__PLL__) == RCC_PLL_ON))
+#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \
+ ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))
+#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
+ ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
+ ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
+ ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
+ ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
+ ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
+ ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
+ ((__MUL__) == RCC_PLL_MUL16))
+#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
+ (((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
+ (((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV512))
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
+ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
+ ((__PCLK__) == RCC_HCLK_DIV16))
+#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
+#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
+#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
/** @defgroup RCC_Exported_Types RCC Exported Types
* @{
*/
-/**
- * @brief RCC PLL configuration structure definition
+/**
+ * @brief RCC PLL configuration structure definition
*/
typedef struct
{
- uint32_t PLLState; /*!< PLLState: The new state of the PLL.
- This parameter can be a value of @ref RCC_PLL_Config */
+ uint32_t PLLState; /*!< The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
- uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
+ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL_Clock_Source */
- uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
- This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
+ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
+ This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
+
+ uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
+ This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
- uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
- This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */
-
-}RCC_PLLInitTypeDef;
-
-/**
- * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+} RCC_PLLInitTypeDef;
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
*/
typedef struct
{
- uint32_t OscillatorType; /*!< The Oscillators to be configured.
- This parameter can be a value of @ref RCC_Oscillator_Type */
-
- uint32_t HSEState; /*!< The new state of the HSE.
- This parameter can be a value of @ref RCC_HSE_Config */
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
- uint32_t LSEState; /*!< The new state of the LSE.
- This parameter can be a value of @ref RCC_LSE_Config */
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
- uint32_t HSIState; /*!< The new state of the HSI.
- This parameter can be a value of @ref RCC_HSI_Config */
-
- uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-
+ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
uint32_t HSI14State; /*!< The new state of the HSI14.
This parameter can be a value of @ref RCC_HSI14_Config */
@@ -108,94 +253,53 @@
uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
This parameter can be a value of @ref RCCEx_HSI48_Config */
- uint32_t LSIState; /*!< The new state of the LSI.
- This parameter can be a value of @ref RCC_LSI_Config */
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
- RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
+ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
-}RCC_OscInitTypeDef;
+} RCC_OscInitTypeDef;
+
-/**
- * @brief RCC System, AHB and APB busses clock configuration structure definition
+/**
+ * @brief RCC System, AHB and APB busses clock configuration structure definition
*/
typedef struct
{
- uint32_t ClockType; /*!< The clock to be configured.
- This parameter can be a value of @ref RCC_System_Clock_Type */
-
- uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
- This parameter can be a value of @ref RCC_System_Clock_Source */
+ uint32_t ClockType; /*!< The clock to be configured.
+ This parameter can be a value of @ref RCC_System_Clock_Type */
+
+ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
+ This parameter can be a value of @ref RCC_System_Clock_Source */
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
- This parameter can be a value of @ref RCC_AHB_Clock_Source */
-
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_APB1_Clock_Source */
-
-}RCC_ClkInitTypeDef;
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_AHB_Clock_Source */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_APB1_Clock_Source */
+
+} RCC_ClkInitTypeDef;
/**
* @}
*/
-
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_Exported_Constants RCC Exported Constants
* @{
*/
-/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
- * @brief RCC registers bit address in the alias region
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
* @{
*/
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-/* --- CR Register ---*/
-#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
-/* --- CFGR Register ---*/
-#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
-/* --- CIR Register ---*/
-#define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
-/* --- BDCR Register ---*/
-#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
-/* --- CSR Register ---*/
-#define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
-/* --- CR2 Register ---*/
-#define RCC_CR2_OFFSET (RCC_OFFSET + 0x34)
-/* CR register byte 2 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
-
-/* CIR register byte 1 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
-
-/* CIR register byte 2 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
-
-/* CSR register byte 1 (Bits[15:8]) base address */
-#define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
-
-/* BDCR register byte 0 (Bits[7:0] base address */
-#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
-
-#define RCC_CFGR_PLLMUL_BITNUMBER 18
-#define RCC_CFGR2_PREDIV_BITNUMBER 0
+#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */
/**
* @}
- */
-
-/** @defgroup RCC_Timeout RCC Timeout
- * @{
- */
-/* LSE state change timeout */
-#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+ */
-/* Disable Backup domain write protection state change timeout */
-#define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-/**
- * @}
- */
-
-/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
+/** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
@@ -204,58 +308,43 @@
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
#define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
-#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
-
-#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \
- (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
/**
* @}
*/
-/** @defgroup RCC_HSE_Config RCC HSE Config
+/** @defgroup RCC_HSE_Config HSE Config
* @{
*/
-#define RCC_HSE_OFF ((uint8_t)0x00)
-#define RCC_HSE_ON ((uint8_t)0x01)
-#define RCC_HSE_BYPASS ((uint8_t)0x05)
-
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_BYPASS))
+#define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */
+#define RCC_HSE_ON ((uint32_t)0x00000001) /*!< HSE clock activation */
+#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for HSE clock */
/**
* @}
*/
-/** @defgroup RCC_LSE_Config RCC_LSE_Config
+/** @defgroup RCC_LSE_Config LSE Config
* @{
*/
-#define RCC_LSE_OFF ((uint8_t)0x00)
-#define RCC_LSE_ON ((uint8_t)0x01)
-#define RCC_LSE_BYPASS ((uint8_t)0x05)
+#define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */
+#define RCC_LSE_ON ((uint32_t)0x00000001) /*!< LSE clock activation */
+#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for LSE clock */
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_BYPASS))
/**
* @}
*/
-/** @defgroup RCC_HSI_Config RCC HSI Config
+/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
-#define RCC_HSI_OFF ((uint8_t)0x00)
-#define RCC_HSI_ON ((uint8_t)0x01)
+#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
+#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
-#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
+#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
-#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
/**
* @}
*/
-
+
/** @defgroup RCC_HSI14_Config RCC HSI14 Config
* @{
*/
@@ -263,35 +352,106 @@
#define RCC_HSI14_ON RCC_CR2_HSI14ON
#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
-#define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) || ((HSI14) == RCC_HSI14_ON) || ((HSI14) == RCC_HSI14_ADC_CONTROL))
+#define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LSI_Config LSI Config
+ * @{
+ */
+#define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */
+#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
+
+/**
+ * @}
+ */
-#define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
+/** @defgroup RCC_PLL_Config PLL Config
+ * @{
+ */
+#define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */
+#define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */
+#define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Type System Clock Type
+ * @{
+ */
+#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
+
/**
* @}
*/
-/** @defgroup RCC_LSI_Config RCC LSI Config
+/** @defgroup RCC_System_Clock_Source System Clock Source
* @{
*/
-#define RCC_LSI_OFF ((uint8_t)0x00)
-#define RCC_LSI_ON ((uint8_t)0x01)
+#define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI) /*!< HSI selected as system clock */
+#define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE) /*!< HSE selected as system clock */
+#define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL) /*!< PLL selected as system clock */
+
+/**
+ * @}
+ */
-#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+
/**
* @}
*/
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+ * @{
+ */
+#define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1)
+#define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2)
+#define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4)
+#define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8)
+#define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16)
+#define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64)
+#define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128)
+#define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256)
+#define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512)
-/** @defgroup RCC_PLL_Config RCC PLL Config
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
* @{
*/
-#define RCC_PLL_NONE ((uint8_t)0x00)
-#define RCC_PLL_OFF ((uint8_t)0x01)
-#define RCC_PLL_ON ((uint8_t)0x02)
+#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
+#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
+#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
-#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
/**
* @}
+ */
+
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
+ * @{
*/
+#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_BDCR_RTCSEL_LSE) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_BDCR_RTCSEL_LSI) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_HSE_DIV32 ((uint32_t)RCC_BDCR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+ * @}
+ */
/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
* @{
@@ -313,18 +473,10 @@
#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
-#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \
- ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \
- ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \
- ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \
- ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \
- ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \
- ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \
- ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16))
/**
* @}
*/
-
+
/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
* @{
*/
@@ -344,110 +496,6 @@
#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
-#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \
- ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \
- ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \
- ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \
- ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \
- ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \
- ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \
- ((MUL) == RCC_PLL_MUL16))
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
- * @{
- */
-#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Type RCC System Clock Type
- * @{
- */
-#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
-#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
-#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
-
-#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
- (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
- (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source RCC System Clock Source
- * @{
- */
-#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
-#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
-#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
- * @{
- */
-#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
-#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
- * @{
- */
-#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
-#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
-#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
-#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
-#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
-#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
-#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
-#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
-#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
-
-#define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \
- ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \
- ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \
- ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \
- ((DIV) == RCC_SYSCLK_DIV512))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
- * @{
- */
-#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
-#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
-#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
-#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
-#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
-
-#define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \
- ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \
- ((DIV) == RCC_HCLK_DIV16))
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
- * @{
- */
-#define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
-#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
-#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
-#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
-
-#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
- ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
/**
* @}
*/
@@ -460,10 +508,6 @@
#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
-#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
/**
* @}
*/
@@ -474,18 +518,15 @@
#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
-#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
- ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
/**
* @}
*/
-
-/** @defgroup RCC_MCOx_Index RCC MCOx Index
+/** @defgroup RCC_MCO_Index MCO Index
* @{
*/
-#define RCC_MCO ((uint32_t)0x00000000)
+#define RCC_MCO1 ((uint32_t)0x00000000)
+#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
-#define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
/**
* @}
*/
@@ -501,70 +542,45 @@
#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
#define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
+
/**
* @}
*/
-
-/** @defgroup RCC_Interrupt RCC Interrupt
+
+/** @defgroup RCC_Interrupt Interrupts
* @{
*/
-#define RCC_IT_LSIRDY ((uint8_t)0x01)
-#define RCC_IT_LSERDY ((uint8_t)0x02)
-#define RCC_IT_HSIRDY ((uint8_t)0x04)
-#define RCC_IT_HSERDY ((uint8_t)0x08)
-#define RCC_IT_PLLRDY ((uint8_t)0x10)
-#define RCC_IT_HSI14 ((uint8_t)0x20)
-#define RCC_IT_CSS ((uint8_t)0x80)
+#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
+#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
+#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
+#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
+#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
+#define RCC_IT_HSI14 ((uint8_t)RCC_CIR_HSI14RDYF) /*!< HSI14 Ready Interrupt flag */
+#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
/**
* @}
*/
-/** @defgroup RCC_Flag RCC Flag
- * Elements values convention: 0XXYYYYYb
+/** @defgroup RCC_Flag Flags
+ * Elements values convention: XXXYYYYYb
* - YYYYY : Flag position in the register
- * - XX : Register index
- * - 00: CR register
- * - 01: CR2 register
- * - 10: BDCR register
- * - 11: CSR register
+ * - XXX : Register index
+ * - 001: CR register
+ * - 010: CR2 register
+ * - 011: BDCR register
+ * - 0100: CSR register
* @{
*/
-#define CR_REG_INDEX 0
-#define CR2_REG_INDEX 1
-#define BDCR_REG_INDEX 2
-#define CSR_REG_INDEX 3
-
/* Flags in the CR register */
-#define RCC_CR_HSIRDY_BitNumber 1
-#define RCC_CR_HSERDY_BitNumber 17
-#define RCC_CR_PLLRDY_BitNumber 25
-
#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_BitNumber))
#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_BitNumber))
#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_BitNumber))
/* Flags in the CR2 register */
-#define RCC_CR2_HSI14RDY_BitNumber 1
-
#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI14RDY_BitNumber))
-/* Flags in the BDCR register */
-#define RCC_BDCR_LSERDY_BitNumber 1
-
-#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber))
/* Flags in the CSR register */
-#define RCC_CSR_LSIRDY_BitNumber 1
-#define RCC_CSR_V18PWRRSTF_BitNumber 23
-#define RCC_CSR_RMVF_BitNumber 24
-#define RCC_CSR_OBLRSTF_BitNumber 25
-#define RCC_CSR_PINRSTF_BitNumber 26
-#define RCC_CSR_PORRSTF_BitNumber 27
-#define RCC_CSR_SFTRSTF_BitNumber 28
-#define RCC_CSR_IWDGRSTF_BitNumber 29
-#define RCC_CSR_WWDGRSTF_BitNumber 30
-#define RCC_CSR_LPWRRSTF_BitNumber 31
-
#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber))
@@ -575,45 +591,23 @@
#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_BitNumber))
#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_BitNumber))
#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_BitNumber))
-/**
- * @}
- */
-/** @defgroup RCC_Calibration_values RCC Calibration values
- * @{
- */
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber))
/**
* @}
- */
-
-/** @addtogroup RCC_Timeout
- * @{
- */
-
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
-#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+ */
/**
* @}
- */
+ */
-/**
- * @}
- */
-
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RCC_Exported_Macros RCC Exported Macros
- * @{
- */
+ * @{
+ */
/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
* @brief Enable or disable the AHB peripheral clock.
@@ -622,27 +616,102 @@
* using it.
* @{
*/
-#define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN))
-#define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN))
-#define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN))
-#define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN))
-#define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
-#define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
-#define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN))
-#define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN))
+#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CRC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
-#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
-#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
-#define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
-#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
-#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
-#define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
-#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
+#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
+#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
+#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
/**
* @}
*/
+/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the AHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
+#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
+#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
+#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
+#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
+/**
+ * @}
+ */
+
/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
@@ -650,20 +719,72 @@
* using it.
* @{
*/
-#define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
-#define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
-#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
-#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
-#define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
+#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_PWR_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
/**
* @}
*/
+
+/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
+/**
+ * @}
+ */
+
/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
@@ -672,42 +793,117 @@
* using it.
* @{
*/
-#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
-#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
-#define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
-#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
-#define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN))
-#define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN))
-#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
-#define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN))
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
-#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
-#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
-#define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
-#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-#define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
+#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
/**
* @}
*/
+/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
+#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
+#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET)
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
+#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
+#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET)
+/**
+ * @}
+ */
+
/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
* @brief Force or release AHB peripheral reset.
* @{
*/
-#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
-#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
-#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
-#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
-#define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
+#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
-#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
-#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
-#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
-#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
-#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
+#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
/**
* @}
*/
@@ -716,19 +912,19 @@
* @brief Force or release APB1 peripheral reset.
* @{
*/
-#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
-#define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
-#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
/**
* @}
*/
@@ -737,88 +933,87 @@
* @brief Force or release APB2 peripheral reset.
* @{
*/
-#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
-#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
-#define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
-#define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
-#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-#define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
-#define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
-#define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
+#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
+#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
-#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
-#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
-#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
-#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
-#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-#define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
-#define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
-#define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
+#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
+#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
+/**
+ * @}
+ */
+/** @defgroup RCC_HSI_Configuration HSI Configuration
+ * @{
+ */
+
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
+
+/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
+ * (default is RCC_HSICALIBRATION_DEFAULT).
+ * This parameter must be a number between 0 and 0x1F.
+ */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
+ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber)
+
/**
* @}
*/
-/** @defgroup RCC_HSI_Configuration RCC HSI Configuration
+/** @defgroup RCC_LSI_Configuration LSI Configuration
* @{
*/
-
-/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * It is used (enabled by hardware) as system clock source after startup
- * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
- * of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
-#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
-/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param __HSICalibrationValue__: specifies the calibration trimming value
- * (default is RCC_HSICALIBRATION_DEFAULT).
- * This parameter must be a number between 0 and 0x1F.
- */
-#define RCC_CR_HSITRIM_BitNumber 3
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
- MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber)
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
+#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
+
/**
* @}
*/
-/** @defgroup RCC_LSI_Configuration RCC LSI Configuration
+/** @defgroup RCC_HSE_Configuration HSE Configuration
* @{
*/
-
-/** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
-#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
-/**
- * @}
- */
-/** @defgroup RCC_HSE_Configuration RCC HSE Configuration
- * @{
- */
-
/**
* @brief Macro to configure the External High Speed oscillator (HSE).
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+ * supported by this macro. User should request a transition to HSE Off
+ * first and then HSE On or HSE Bypass.
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
* software should wait on HSERDY flag to be set indicating that HSE clock
* is stable and can be used to clock the PLL and/or system clock.
@@ -836,31 +1031,55 @@
* @arg RCC_HSE_ON: turn ON the HSE oscillator
* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
*/
-#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)RCC_CR_BYTE2_ADDRESS = (__STATE__))
+#define __HAL_RCC_HSE_CONFIG(__STATE__) \
+ do{ \
+ if ((__STATE__) == RCC_HSE_ON) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else if ((__STATE__) == RCC_HSE_OFF) \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ else if ((__STATE__) == RCC_HSE_BYPASS) \
+ { \
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ SET_BIT(RCC->CR, RCC_CR_HSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
+ } \
+ }while(0)
/**
* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
* @note Predivision factor can not be changed if PLL is used as system clock
* In this case, you have to select another source of the system clock, disable the PLL and
* then change the HSE predivision factor.
- * @param __HSEPredivValue__: specifies the division value applied to HSE.
+ * @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
*/
-#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
+#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
+
/**
* @}
*/
-/** @defgroup RCC_LSE_Configuration RCC LSE Configuration
+/** @defgroup RCC_LSE_Configuration LSE Configuration
* @{
- */
+ */
+
/**
* @brief Macro to configure the External Low Speed oscillator (LSE).
+ * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
* @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
+ * this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
+ * (to be done once after reset).
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
* software should wait on LSERDY flag to be set indicating that LSE clock
* is stable and can be used to clock the RTC.
@@ -868,11 +1087,32 @@
* This parameter can be one of the following values:
* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
* 6 LSE oscillator clock cycles.
- * @arg RCC_LSE_ON: turn ON the LSE oscillator
- * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator.
+ * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
*/
-#define __HAL_RCC_LSE_CONFIG(__STATE__) \
- MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+ do{ \
+ if ((__STATE__) == RCC_LSE_ON) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else if ((__STATE__) == RCC_LSE_OFF) \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ else if ((__STATE__) == RCC_LSE_BYPASS) \
+ { \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ } \
+ else \
+ { \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+ } \
+ }while(0)
+
/**
* @}
*/
@@ -963,235 +1203,247 @@
* @}
*/
+
+/** @defgroup RCC_PLL_Configuration PLL Configuration
+ * @{
+ */
+
+/** @brief Macros to enable the main PLL.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
+
+/** @brief Macros to disable the main PLL.
+ * @note The main PLL can not be disabled if it is used as system clock source
+ */
+#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
+
+/** @brief Macro to configure the PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ *
+ * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+ * @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter can be one of the following values:
+ * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
+ * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
+ * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
+ *
+ */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \
+ do { \
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \
+ } while(0)
+
+/** @brief Get oscillator clock selected as PLL input clock
+ * @retval The clock source used for PLL entry. The returned value can be one
+ * of the following:
+ * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
+ */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Get_Clock_source Get Clock source
+ * @{
+ */
+
+/**
+ * @brief Macro to configure the system clock source.
+ * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
+ * This parameter can be one of the following values:
+ * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+ * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+ */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
+
+/** @brief Macro to get the clock source used as system clock.
+ * @retval The clock source used as system clock. The returned value can be one
+ * of the following:
+ * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
+ * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
+ * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
+
+/**
+ * @}
+ */
+
/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
* @{
*/
-/** @brief Macros to enable or disable the the RTC clock.
- * @note These macros must be used only after the RTC clock source was selected.
- */
-#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-/** @brief Macro to configure the RTC clock (RTCCLK).
+/** @brief Macro to configures the RTC clock (RTCCLK).
* @note As the RTC clock configuration bits are in the Backup domain and write
* access is denied to this domain after reset, you have to enable write
* access using the Power Backup Access macro before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the
- * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the
+ * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
* a Power On Reset (POR).
- * @param __RTCCLKSource__: specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
- * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
- * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
*
- * @note If the LSE is used as RTC clock source, the RTC continues to
+ * @param __RTC_CLKSOURCE__: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
* work in STOP and STANDBY modes, and can be used as wakeup source.
* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
* the RTC cannot be used in STOP and STANDBY modes.
* @note The system must always be configured so as to get a PCLK frequency greater than or
* equal to the RTCCLK frequency for a proper operation of the RTC.
*/
-#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
- MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
-
-/** @brief Macro to get the RTC clock source.
+#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
+
+/** @brief macros to get the RTC clock source.
* @retval The clock source can be one of the following values:
- * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock
* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
+ * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
*/
-#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
-/**
- * @}
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
+
+/** @brief Macros to enable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
*/
+#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
-/** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
- * @{
- */
-
-/** @brief Macro to force or release the Backup domain reset.
- * @note These macros reset the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_CSR register.
- * @note The BKPSRAM is not affected by this reset.
+/** @brief Macros to disable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
*/
-#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
-#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
+
+/** @brief Macros to force the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ * and the RTC clock source selection in RCC_BDCR register.
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
+/** @brief Macros to release the Backup domain reset.
+ */
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
+
/**
* @}
*/
-/** @defgroup RCC_PLL_Configuration RCC PLL Configuration
- * @{
- */
-
-/** @brief Macro to enable or disable the PLL.
- * @note After enabling the PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The PLL can not be disabled if it is used as system clock source
- * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
-#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
-
-/** @brief Macro to configure the PLL clock source, multiplication and division factors.
- * @note This macro must be used only when the PLL is disabled.
- *
- * @param __RCC_PLLSource__: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
- * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
- * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
- * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
- * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
- * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
- *
- */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
- do { \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
- } while(0)
-/**
- * @}
- */
-
-/** @defgroup RCC_Get_Clock_source RCC Get Clock source
- * @{
- */
-
-/** @brief Macro to get the clock source used as system clock.
- * @retval The clock source used as system clock.
- * The returned value can be one of the following value:
- * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
- * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
- * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
- */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
-
-/** @brief Macro to get the oscillator used as PLL clock source.
- * @retval The oscillator used as PLL clock source. The returned value can be one
- * of the following:
- * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
- */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
-/**
- * @}
- */
-
-/** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
* @brief macros to manage the specified RCC Flags and interrupts.
* @{
*/
-/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
- * the selected interrupts.).
+/** @brief Enable RCC interrupt.
* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
- * @arg RCC_IT_LSERDY: LSE ready interrupt enable
- * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
- * @arg RCC_IT_HSERDY: HSE ready interrupt enable
- * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt
* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
*/
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
-/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
- * the selected interrupts.).
+/** @brief Disable RCC interrupt.
* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
- * @arg RCC_IT_LSERDY: LSE ready interrupt enable
- * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
- * @arg RCC_IT_HSERDY: HSE ready interrupt enable
- * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: main PLL ready interrupt
+ * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
+ * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
+ */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
+
+/** @brief Clear the RCC's interrupt pending bits.
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_CSS: Clock Security System interrupt
* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
*/
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
-
-/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
- * bits to clear the selected interrupt pending bits.
- * @param __IT__: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt clear
- * @arg RCC_IT_LSERDY: LSE ready interrupt clear
- * @arg RCC_IT_HSIRDY: HSI ready interrupt clear
- * @arg RCC_IT_HSERDY: HSE ready interrupt clear
- * @arg RCC_IT_PLLRDY: PLL ready interrupt clear
- * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices)
- * @arg RCC_IT_CSS: Clock Security System interrupt clear
- */
-#define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__IT__))
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
-/** @brief Check the RCC's interrupt has occurred or not.
- * @param __IT__: specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt flag
- * @arg RCC_IT_LSERDY: LSE ready interrupt flag
- * @arg RCC_IT_HSIRDY: HSI ready interrupt flag
- * @arg RCC_IT_HSERDY: HSE ready interrupt flag
- * @arg RCC_IT_PLLRDY: PLL ready interrupt flag
- * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices)
- * @arg RCC_IT_CSS: Clock Security System interrupt flag
- * @retval The new state of __IT__ (TRUE or FALSE).
+/** @brief Check the RCC's interrupt has occurred or not.
+ * @param __INTERRUPT__: specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt.
+ * @arg RCC_IT_LSERDY: LSE ready interrupt.
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt.
+ * @arg RCC_IT_HSERDY: HSE ready interrupt.
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
+ * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
-/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
- * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+/** @brief Set RMVF bit to clear the reset flags.
+ * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
*/
-#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
/** @brief Check RCC flag is set or not.
* @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
- * @arg RCC_FLAG_PLLRDY: PLL clock ready
+ * This parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
+ * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
* @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
* @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
* @arg RCC_FLAG_OBLRST: Option Byte Load reset
- * @arg RCC_FLAG_PINRST: Pin reset
- * @arg RCC_FLAG_PORRST: POR/PDR reset
- * @arg RCC_FLAG_SFTRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPWRRST: Low Power reset
+ * @arg RCC_FLAG_PINRST: Pin reset.
+ * @arg RCC_FLAG_PORRST: POR/PDR reset.
+ * @arg RCC_FLAG_SFTRST: Software reset.
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
+ * @arg RCC_FLAG_LPWRRST: Low Power reset.
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define RCC_FLAG_MASK ((uint8_t)0x1F)
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
(((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
(((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
-
+/**
+ * @}
+ */
/**
* @}
- */
-
-/**
- * @}
- */
+ */
/* Include RCC HAL Extension module */
#include "stm32f0xx_hal_rcc_ex.h"
/* Exported functions --------------------------------------------------------*/
-
/** @addtogroup RCC_Exported_Functions
* @{
*/
@@ -1200,10 +1452,10 @@
* @{
*/
-/* Initialization and de-initialization functions ***************************/
-void HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+/* Initialization and de-initialization functions ******************************/
+void HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
/**
* @}
@@ -1212,22 +1464,22 @@
/** @addtogroup RCC_Exported_Functions_Group2
* @{
*/
-
-/* Peripheral Control functions *********************************************/
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void HAL_RCC_EnableCSS(void);
-void HAL_RCC_DisableCSS(void);
-uint32_t HAL_RCC_GetSysClockFreq(void);
-uint32_t HAL_RCC_GetHCLKFreq(void);
-uint32_t HAL_RCC_GetPCLK1Freq(void);
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/* Peripheral Control functions ************************************************/
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void HAL_RCC_EnableCSS(void);
+void HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
+void HAL_RCC_NMI_IRQHandler(void);
/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CCSCallback(void);
+void HAL_RCC_CSSCallback(void);
/**
* @}
@@ -1235,16 +1487,16 @@
/**
* @}
- */
+ */
+
+/**
+ * @}
+ */
/**
* @}
*/
-
-/**
- * @}
- */
-
+
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Extended RCC HAL module driver
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@@ -60,7 +60,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -94,20 +94,18 @@
* @{
*/
-/** @defgroup RCCEx RCCEx Extended HAL module driver
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/** @defgroup RCCEx RCCEx
* @brief RCC Extension HAL module driver.
* @{
*/
-#ifdef HAL_RCC_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Define RCCEx Private Define
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
* @{
*/
-#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-
/* Bit position in register */
#define CRS_CFGR_FELIM_BITNUMBER 16
#define CRS_CR_TRIM_BITNUMBER 8
@@ -117,17 +115,13 @@
*/
/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Variables RCCEx Private Variables
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
* @{
*/
-const uint8_t PLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9,
- 10, 11, 12, 13, 14, 15, 16, 16};
-const uint8_t PredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8,
- 9,10, 11, 12, 13, 14, 15, 16};
/**
* @}
*/
+/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/
@@ -156,834 +150,6 @@
*/
/**
- * @brief Initializes the RCC Oscillators according to the specified parameters in the
- * RCC_OscInitTypeDef.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC Oscillators.
- * @note The PLL is not disabled when used as system clock.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
- /*------------------------------- HSE Configuration ------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
- /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) ||
- ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
- {
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
- {
- return HAL_ERROR;
- }
- }
- else
- {
- /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
- __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Set the new HSE configuration ---------------------------------------*/
- __HAL_RCC_HSE_CONFIG((uint8_t)RCC_OscInitStruct->HSEState);
-
- /* Check the HSE State */
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- {
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*----------------------------- HSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) ||
- ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
- {
- /* When the HSI is used as system clock it is not allowed to be disabled */
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- {
- return HAL_ERROR;
- }
- /* Otherwise, just the calibration is allowed */
- else
- {
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- }
- else
- {
- /* Check the HSI State */
- if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
- {
- /* Enable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_ENABLE();
-
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- else
- {
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_DISABLE();
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*------------------------------ LSI Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
- /* Check the LSI State */
- if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
- {
- /* Enable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_ENABLE();
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_DISABLE();
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /*------------------------------ LSE Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Enable Power Clock */
- __PWR_CLK_ENABLE();
-
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR, PWR_CR_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while((PWR->CR & PWR_CR_DBP) == RESET)
- {
- if((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
- __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Set the new LSE configuration -----------------------------------------*/
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- /* Check the LSE State */
- if(RCC_OscInitStruct->LSEState == RCC_LSE_ON)
- {
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- /*----------------------------- HSI14 Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
-
- /* Check the HSI14 State */
- if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
- {
- /* Disable ADC control of the Internal High Speed oscillator HSI14 */
- __HAL_RCC_HSI14ADC_DISABLE();
-
- /* Enable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI14_ENABLE();
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
- {
- if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
- __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
- }
- else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
- {
- /* Enable ADC control of the Internal High Speed oscillator HSI14 */
- __HAL_RCC_HSI14ADC_ENABLE();
-
- /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
- __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
- }
- else
- {
- /* Disable ADC control of the Internal High Speed oscillator HSI14 */
- __HAL_RCC_HSI14ADC_DISABLE();
-
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI14_DISABLE();
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
- {
- if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
- /*----------------------------- HSI48 Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
-
- /* When the HSI48 is used as system clock it is not allowed to be disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) ||
- ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))
- {
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON))
- {
- return HAL_ERROR;
- }
- }
- else
- {
- /* Check the HSI State */
- if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
- {
- /* Enable the Internal High Speed oscillator (HSI48). */
- __HAL_RCC_HSI48_ENABLE();
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
- {
- if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the Internal High Speed oscillator (HSI48). */
- __HAL_RCC_HSI48_DISABLE();
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
- {
- if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
-
- /*-------------------------------- PLL Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
- if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- {
- /* Check if the PLL is used as system clock or not */
- if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
- assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
- assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
-
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the main PLL clock source, predivider and multiplication factor. */
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- RCC_OscInitStruct->PLL.PREDIV,
- RCC_OscInitStruct->PLL.PLLMUL);
-
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- return HAL_ERROR;
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
- * parameters in the RCC_ClkInitStruct.
- * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC peripheral.
- * @param FLatency: FLASH Latency
- * This parameter can be one of the following values:
- * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
- * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
- * and updated by HAL_RCC_GetHCLKFreq() function called within this function
- *
- * @note The HSI is used (enabled by hardware) as system clock source after
- * startup from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- *
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * @retval None
- */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
- assert_param(IS_FLASH_LATENCY(FLatency));
-
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) of the device. */
-
- /* Increasing the CPU frequency */
- if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
- {
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
- {
- return HAL_ERROR;
- }
-
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- {
- assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- }
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
- /* HSI48 is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
- {
- /* Check the HSI48 ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
- /* HSI is selected as System Clock Source */
- else
- {
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
- {
- if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48)
- {
- if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
- else
- {
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
- {
- if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /* Decreasing the CPU frequency */
- else
- {
- /*-------------------------- HCLK Configuration --------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- {
- assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- }
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
- assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
- /* HSE is selected as System Clock Source */
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- /* Check the HSE ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- /* PLL is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- /* Check the PLL ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
- /* HSI48 is selected as System Clock Source */
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
- {
- /* Check the HSI48 ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
- /* HSI is selected as System Clock Source */
- else
- {
- /* Check the HSI ready flag */
- if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- return HAL_ERROR;
- }
- }
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
- {
- if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48)
- {
- if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
- else
- {
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
- {
- if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
- /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
- __HAL_FLASH_SET_LATENCY(FLatency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
- {
- return HAL_ERROR;
- }
- }
-
- /*-------------------------- PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- {
- assert_param(IS_RCC_HCLK_DIV(RCC_ClkInitStruct->APB1CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
- }
-
- /* Configure the source of time base considering new system clocks settings*/
- HAL_InitTick (TICK_INT_PRIORITY);
-
- return HAL_OK;
-}
-
-/**
- * @brief Returns the SYSCLK frequency
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- * @note If SYSCLK source is HSI, function returns a value based on HSI_VALUE(*)
- * @note If SYSCLK source is HSI48, function returns a value based on HSI48_VALUE(*)
- * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
- * divided by PREDIV factor(**)
- * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
- * divided by PREDIV factor(**) or depending on STM32F0xx devices either a value based
- * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the
- * PLL factor .
- * @note (*) HSI_VALUE & HSI48_VALUE are constants defined in stm32f0xx_hal_conf.h file
- * (default values 8 MHz and 48MHz).
- * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @note This function can be used by the user application to compute the
- * baudrate for the communication peripherals or configure other parameters.
- *
- * @note Each time SYSCLK changes, this function must be called to update the
- * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- * @retval SYSCLK frequency
- */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
- uint32_t tmpreg = 0, prediv = 0, pllmul = 0, pllclk = 0;
- uint32_t sysclockfreq = 0;
-
- tmpreg = RCC->CFGR;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (tmpreg & RCC_CFGR_SWS)
- {
- case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
- sysclockfreq = HSE_VALUE;
- break;
-
- case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
- pllmul = PLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
- prediv = PredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
- if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
- {
- /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
- pllclk = (HSE_VALUE/prediv) * pllmul;
- }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
- else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48)
- {
- /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */
- pllclk = (HSI48_VALUE/prediv) * pllmul;
- }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
- else
- {
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
- /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
- pllclk = (HSI_VALUE/prediv) * pllmul;
-#else
- /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
- pllclk = (HSI_VALUE >> 1) * pllmul;
-#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
- STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB
- STM32F091xC || STM32F098xx || STM32F030xC */
- }
- sysclockfreq = pllclk;
- break;
-
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
- case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */
- sysclockfreq = HSI48_VALUE;
- break;
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
-
- case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
- default:
- sysclockfreq = HSI_VALUE;
- break;
- }
- return sysclockfreq;
-}
-
-/**
* @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef.
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
@@ -1000,7 +166,7 @@
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tickstart = 0;
- uint32_t tmpreg = 0;
+ uint32_t temp_reg = 0;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection));
@@ -1008,51 +174,51 @@
/*---------------------------- RTC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
- /* Enable Power Clock*/
- __PWR_CLK_ENABLE();
-
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR, PWR_CR_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while((PWR->CR & PWR_CR_DBP) == RESET)
- {
- if((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
/* Reset the Backup domain only if the RTC Clock source selction is modified */
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
{
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
/* Store the content of BDCR register before the reset of Backup Domain */
- tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
/* Restore the Content of BDCR register */
- RCC->BDCR = tmpreg;
- }
-
- /* If LSE is selected as RTC clock source, wait for LSE reactivation */
- if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
- {
- /* Get timeout */
- tickstart = HAL_GetTick();
+ RCC->BDCR = temp_reg;
+
+ /* Wait for LSERDY if LSE was enabled */
+ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE)
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
- return HAL_TIMEOUT;
- }
- }
+ if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
/*------------------------------- USART1 Configuration ------------------------*/
@@ -1065,8 +231,8 @@
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
}
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/*----------------------------- USART2 Configuration --------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
{
@@ -1113,10 +279,10 @@
}
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/*------------------------------ CEC clock Configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
{
@@ -1154,8 +320,8 @@
/* Get the I2C1 clock source -----------------------------------------------*/
PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2;
/* Get the USART2 clock source ---------------------------------------------*/
PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
@@ -1174,10 +340,10 @@
PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
/* Get the CEC clock source ------------------------------------------------*/
PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
@@ -1188,9 +354,271 @@
}
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+/**
+ * @brief Returns the peripheral clock frequency
+ * @note Returns 0 if peripheral clock is unknown
+ * @param PeriphClk: Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg RCC_PERIPHCLK_RTC RTC peripheral clock
+ * @arg RCC_PERIPHCLK_USART1 USART1 peripheral clock
+ * @arg RCC_PERIPHCLK_USART2 USART2 peripheral clock (*)
+ * @arg RCC_PERIPHCLK_USART3 USART3 peripheral clock (*)
+ * @arg RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
+ * @arg RCC_PERIPHCLK_USB USB peripheral clock (*)
+ * @arg RCC_PERIPHCLK_CEC CEC peripheral clock (*)
+ * @note (*) means that this peripheral is not present on all the STM32F0xx devices
+ * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ uint32_t frequency = 0;
+ uint32_t srcclk = 0;
+#if defined(USB)
+ uint32_t pllmull = 0, pllsource = 0, predivfactor = 0;
+#endif /* USB */
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLK(PeriphClk));
+
+ switch (PeriphClk)
+ {
+ case RCC_PERIPHCLK_RTC:
+ {
+ /* Get the current RTC source */
+ srcclk = __HAL_RCC_GET_RTC_SOURCE();
+
+ /* Check if LSE is ready and if RTC clock selection is LSE */
+ if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready and if RTC clock selection is LSI */
+ else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+ {
+ frequency = LSI_VALUE;
+ }
+ /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
+ else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
+ {
+ frequency = HSE_VALUE / 32;
+ }
+ /* Clock not enabled for RTC*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_USART1:
+ {
+ /* Get the current USART1 source */
+ srcclk = __HAL_RCC_GET_USART1_SOURCE();
+
+ /* Check if USART1 clock selection is PCLK1 */
+ if (srcclk == RCC_USART1CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if USART1 clock selection is HSI */
+ else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if USART1 clock selection is SYSCLK */
+ else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if USART1 clock selection is LSE */
+ else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART1*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#if defined(RCC_CFGR3_USART2SW)
+ case RCC_PERIPHCLK_USART2:
+ {
+ /* Get the current USART2 source */
+ srcclk = __HAL_RCC_GET_USART2_SOURCE();
+
+ /* Check if USART2 clock selection is PCLK1 */
+ if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if USART2 clock selection is HSI */
+ else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if USART2 clock selection is SYSCLK */
+ else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if USART2 clock selection is LSE */
+ else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART2*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_USART2SW */
+#if defined(RCC_CFGR3_USART3SW)
+ case RCC_PERIPHCLK_USART3:
+ {
+ /* Get the current USART3 source */
+ srcclk = __HAL_RCC_GET_USART3_SOURCE();
+
+ /* Check if USART3 clock selection is PCLK1 */
+ if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if USART3 clock selection is HSI */
+ else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if USART3 clock selection is SYSCLK */
+ else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if USART3 clock selection is LSE */
+ else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART3*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* RCC_CFGR3_USART3SW */
+ case RCC_PERIPHCLK_I2C1:
+ {
+ /* Get the current I2C1 source */
+ srcclk = __HAL_RCC_GET_I2C1_SOURCE();
+
+ /* Check if HSI is ready and if I2C1 clock selection is HSI */
+ if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if I2C1 clock selection is SYSCLK */
+ else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Clock not enabled for I2C1*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#if defined(USB)
+ case RCC_PERIPHCLK_USB:
+ {
+ /* Get the current USB source */
+ srcclk = __HAL_RCC_GET_USB_SOURCE();
+
+ /* Check if PLL is ready and if USB clock selection is PLL */
+ if ((srcclk == RCC_USBCLKSOURCE_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = (pllmull >> RCC_CFGR_PLLMUL_BITNUMBER) + 2;
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
+ {
+ /* HSE used as PLL clock source : frequency = HSE/PREDIV * PLLMUL */
+ frequency = (HSE_VALUE/predivfactor) * pllmull;
+ }
+#if defined(RCC_CR2_HSI48ON)
+ else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
+ {
+ /* HSI48 used as PLL clock source : frequency = HSI48/PREDIV * PLLMUL */
+ frequency = (HSI48_VALUE / predivfactor) * pllmull;
+ }
+#endif /* RCC_CR2_HSI48ON */
+ else
+ {
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F072xB) || defined(STM32F070xB)
+ /* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */
+ frequency = (HSI_VALUE / predivfactor) * pllmull;
+#else
+ /* HSI used as PLL clock source : frequency = HSI/2 * PLLMUL */
+ frequency = (HSI_VALUE >> 1) * pllmull;
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */
+ }
+ }
+#if defined(RCC_CR2_HSI48ON)
+ /* Check if HSI48 is ready and if USB clock selection is HSI48 */
+ else if ((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CR2, RCC_CR2_HSI48RDY)))
+ {
+ frequency = HSI48_VALUE;
+ }
+#endif /* RCC_CR2_HSI48ON */
+ /* Clock not enabled for USB*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* USB */
+#if defined(CEC)
+ case RCC_PERIPHCLK_CEC:
+ {
+ /* Get the current CEC source */
+ srcclk = __HAL_RCC_GET_CEC_SOURCE();
+
+ /* Check if HSI is ready and if CEC clock selection is HSI */
+ if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if LSE is ready and if CEC clock selection is LSE */
+ else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for CEC */
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* CEC */
+ default:
+ {
+ break;
+ }
+ }
+ return(frequency);
+}
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/**
* @brief Start automatic synchronization using polling mode
* @param pInit Pointer on RCC_CRSInitTypeDef structure
@@ -1210,8 +638,8 @@
/* CONFIGURATION */
/* Before configuration, reset CRS registers to their default values*/
- __CRS_FORCE_RESET();
- __CRS_RELEASE_RESET();
+ __HAL_RCC_CRS_FORCE_RESET();
+ __HAL_RCC_CRS_RELEASE_RESET();
/* Configure Synchronization input */
/* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */
@@ -1395,10 +823,11 @@
* @}
*/
-#endif /* HAL_RCC_MODULE_ENABLED */
/**
* @}
*/
+
+#endif /* HAL_RCC_MODULE_ENABLED */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -37,7 +37,7 @@
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_RCC_EX_H
-#define __STM32F0xx_HAL_RCC_EX_H
+#define __HAL_RCC_STM32F0xx_HAL_RCC_EX_H
#ifdef __cplusplus
extern "C" {
@@ -50,10 +50,363 @@
* @{
*/
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
+
+#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSI48) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
+#else
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14))
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
+
+#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+ ((SOURCE) == RCC_PLLSOURCE_HSE))
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6)\
+ || defined(STM32F070xB) || defined(STM32F030xC)
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI14))
+
+#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */
+
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI14))
+
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_LSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSE) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
+ ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI14) || \
+ ((SOURCE) == RCC_MCOSOURCE_HSI48))
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Constants
+ * @{
+ */
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @addtogroup RCC_PLL_Clock_Source
+ * @{
+ */
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
+#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Oscillator_Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Interrupt
+ * @{
+ */
+#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Flag
+ * @{
+ */
+#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber))
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_System_Clock_Source
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_System_Clock_Source_Status
+ * @{
+ */
+#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
+/**
+ * @}
+ */
+
+#else
+/** @addtogroup RCC_PLL_Clock_Source
+ * @{
+ */
+
+#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC)
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
+#else
+#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+/** @addtogroup RCC_MCO_Clock_Source
+ * @{
+ */
+
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6)\
+ || defined(STM32F070xB) || defined(STM32F030xC)
+
+#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
+
+#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
+#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
/** @addtogroup RCCEx
* @{
*/
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+ * @{
+ */
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F030xC)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_RTC))
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
+ STM32F030xC */
+
+#if defined(STM32F070x6) || defined(STM32F070xB)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
+#endif /* STM32F070x6 || STM32F070xB */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB))
+#endif /* STM32F042x6 || STM32F048xx */
+
+#if defined(STM32F051x8) || defined(STM32F058xx)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
+#endif /* STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F071xB)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
+ RCC_PERIPHCLK_RTC))
+#endif /* STM32F071xB */
+
+#if defined(STM32F072xB) || defined(STM32F078xx)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
+#endif /* STM32F072xB || STM32F078xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
+ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 ))
+#endif /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
+
+#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \
+ ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
+
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
+
+#if defined(STM32F070x6) || defined(STM32F070xB)
+
+#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
+
+#endif /* STM32F070x6 || STM32F070xB */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
+#endif /* STM32F091xC || STM32F098xx */
+
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_CECCLKSOURCE_LSE))
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
+
+#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
+
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6)\
+ || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB)\
+ || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \
+ ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \
+ ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \
+ ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
+
+#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070x6 || STM32F070xB */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
+ ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \
+ ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
+#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \
+ ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
+ ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
+ ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
+#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
+ ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
+#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
+#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
+#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
+#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
+ ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
+
/* Exported types ------------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
@@ -63,8 +416,8 @@
/**
* @brief RCC extended clocks structure definition
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F030xC)
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F030xC)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
@@ -228,9 +581,9 @@
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/**
* @brief RCC_CRS Init structure definition
@@ -294,13 +647,22 @@
* @{
*/
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
+ * @{
+ */
+#define RCC_HSI48_OFF ((uint8_t)0x00)
+#define RCC_HSI48_ON ((uint8_t)0x01)
+
+/**
+ * @}
+ */
+
/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
* @{
*/
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
-
#define RCC_CRS_NONE ((uint32_t)0x00000000)
#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
@@ -309,24 +671,33 @@
#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
#define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
-#endif /* STM32F042x6 || STM32F048xx */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
/**
* @}
*/
+#else
+
+/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
+ * @{
+ */
+#define RCC_HSI48_OFF ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+#endif /* STM32F042x6 || STM32F048xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
* @{
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F030xC)
+#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F030xC)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
- RCC_PERIPHCLK_RTC))
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
STM32F030xC */
@@ -336,8 +707,6 @@
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
#endif /* STM32F070x6 || STM32F070xB */
#if defined(STM32F042x6) || defined(STM32F048xx)
@@ -347,9 +716,6 @@
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
- RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_USB))
#endif /* STM32F042x6 || STM32F048xx */
#if defined(STM32F051x8) || defined(STM32F058xx)
@@ -358,8 +724,6 @@
#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
- RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
#endif /* STM32F051x8 || STM32F058xx */
#if defined(STM32F071xB)
@@ -369,9 +733,6 @@
#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
- RCC_PERIPHCLK_RTC))
#endif /* STM32F071xB */
#if defined(STM32F072xB) || defined(STM32F078xx)
@@ -382,9 +743,6 @@
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
#endif /* STM32F072xB || STM32F078xx */
#if defined(STM32F091xC) || defined(STM32F098xx)
@@ -395,80 +753,12 @@
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
- RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
- RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 ))
#endif /* STM32F091xC || STM32F098xx */
/**
* @}
*/
-/** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
- * @{
- */
-
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F030xC)
-
-#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
-
-#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
- ((SOURCE) == RCC_MCOSOURCE_LSI) || \
- ((SOURCE) == RCC_MCOSOURCE_LSE) || \
- ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI) || \
- ((SOURCE) == RCC_MCOSOURCE_HSE) || \
- ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
- ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI14))
-
-#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */
-
-#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
-
-#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
- ((SOURCE) == RCC_MCOSOURCE_LSI) || \
- ((SOURCE) == RCC_MCOSOURCE_LSE) || \
- ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI) || \
- ((SOURCE) == RCC_MCOSOURCE_HSE) || \
- ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI14))
-
-#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
-
-#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
-#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
-
-#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
- ((SOURCE) == RCC_MCOSOURCE_LSI) || \
- ((SOURCE) == RCC_MCOSOURCE_LSE) || \
- ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI) || \
- ((SOURCE) == RCC_MCOSOURCE_HSE) || \
- ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
- ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI14) || \
- ((SOURCE) == RCC_MCOSOURCE_HSI48))
-
-#define RCC_IT_HSI48 ((uint8_t)0x40)
-
-/* Flags in the CR2 register */
-#define RCC_CR2_HSI48RDY_BitNumber 16
-
-#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber))
-
-#endif /* STM32F042x6 || STM32F048xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
-/**
- * @}
- */
-
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
@@ -477,8 +767,6 @@
#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
-#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \
- ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
/**
* @}
*/
@@ -492,15 +780,14 @@
*/
#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
-#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
/**
* @}
*/
#endif /* STM32F070x6 || STM32F070xB */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
* @{
@@ -510,10 +797,6 @@
#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
-#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
/**
* @}
*/
@@ -531,10 +814,6 @@
#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
-#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
- ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
- ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
- ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
/**
* @}
*/
@@ -542,10 +821,10 @@
#endif /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
* @{
@@ -553,8 +832,6 @@
#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
-#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
- ((SOURCE) == RCC_CECCLKSOURCE_LSE))
/**
* @}
*/
@@ -564,115 +841,20 @@
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
-
-/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
- * @{
- */
-#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
-#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
-
-#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
- ((SOURCE) == RCC_PLLSOURCE_HSI48) || \
- ((SOURCE) == RCC_PLLSOURCE_HSE))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
- * @{
- */
-#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
-
-#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
-
-#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
-
-#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
- * @{
- */
-#define RCC_HSI48_OFF ((uint8_t)0x00)
-#define RCC_HSI48_ON ((uint8_t)0x01)
-
-#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
-/**
- * @}
- */
-#else
-/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
- * @{
- */
-
-#if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC)
-#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
-#else
-#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
-#endif
-
-#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
- ((SOURCE) == RCC_PLLSOURCE_HSE))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
- * @{
- */
-#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
-
-#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
- ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
-/**
- * @}
- */
-
-/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
- * @{
- */
-#define RCC_HSI48_OFF ((uint8_t)0x00)
-
-#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
-/**
- * @}
- */
-
-#endif /* STM32F042x6 || STM32F048xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
-
-
/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
* @{
*/
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
-#define RCC_MCO_NODIV ((uint32_t)0x00000000)
-
-#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
+#define RCC_MCODIV_1 ((uint32_t)0x00000000)
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
- defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB) || \
- defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6)\
+ || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB)\
+ || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
@@ -683,11 +865,6 @@
#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
-#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \
- ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \
- ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \
- ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
-
#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070x6 || STM32F070xB */
/* STM32F091xC || STM32F098xx || STM32F030xC */
@@ -696,9 +873,9 @@
* @}
*/
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
* @{
@@ -707,9 +884,6 @@
#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
-#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
- ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \
- ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
/**
* @}
*/
@@ -726,10 +900,6 @@
#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
-#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \
- ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
- ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
- ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
/**
* @}
*/
@@ -740,8 +910,6 @@
#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
-#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
- ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
/**
* @}
*/
@@ -752,7 +920,6 @@
#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
-#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
/**
* @}
*/
@@ -762,7 +929,6 @@
*/
#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
-#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
/**
* @}
*/
@@ -774,7 +940,6 @@
The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
corresponds to a higher output frequency */
-#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
/**
* @}
*/
@@ -785,8 +950,6 @@
#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
-#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
- ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
/**
* @}
*/
@@ -841,38 +1004,56 @@
* using it.
* @{
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || \
- defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x6) || defined(STM32F030x8)\
+ || defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
+#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
#endif /* STM32F030x6 || STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || STM32F070xB || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
+#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
+#define __HAL_RCC_TSC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
+#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
@@ -881,9 +1062,15 @@
#if defined(STM32F091xC) || defined(STM32F098xx)
-#define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
+#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
#endif /* STM32F091xC || STM32F098xx */
@@ -892,32 +1079,63 @@
* is disabled and the application software has to enable this clock before
* using it.
*/
-#if defined(STM32F030x8) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x8)\
+ || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_USART2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
-#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || STM32F070x6 || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
-#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#if defined(STM32F030x8)\
+ || defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#endif /* STM32F031x6 || STM32F038xx || */
/* STM32F042x6 || STM32F048xx || */
@@ -925,88 +1143,148 @@
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F030x8) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x8) \
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
-#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#endif /* STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
#endif /* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN))
+#define __HAL_RCC_CEC_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
-#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
-#define __USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN))
+#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART4_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
-#define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
+#define __HAL_RCC_USB_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
+#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
/* STM32F072xB || STM32F078xx || STM32F070xB */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN))
-#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
+#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
+#define __HAL_RCC_CRS_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
+#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
@@ -1014,9 +1292,15 @@
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
+#define __HAL_RCC_USART5_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
+#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
@@ -1025,14 +1309,20 @@
* is disabled and the application software has to enable this clock before
* using it.
*/
-#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN))
+#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
+#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
/* STM32F051x8 || STM32F058xx || */
@@ -1041,19 +1331,37 @@
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
+#define __HAL_RCC_USART6_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
#if defined(STM32F091xC) || defined(STM32F098xx)
-#define __USART7_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART7EN))
-#define __USART8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART8EN))
+#define __HAL_RCC_USART7_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
+ UNUSED(tmpreg); \
+ } while(0)
+#define __HAL_RCC_USART8_CLK_ENABLE() do { \
+ __IO uint32_t tmpreg; \
+ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
+ /* Delay after an RCC peripheral clock enabling */ \
+ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
+ UNUSED(tmpreg); \
+ } while(0)
-#define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
-#define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
+#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
+#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
#endif /* STM32F091xC || STM32F098xx */
@@ -1069,38 +1377,38 @@
/** @brief Force or release AHB peripheral reset.
*/
-#if defined(STM32F030x6) || defined(STM32F030x8) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x6) || defined(STM32F030x8)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
-#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
#endif /* STM32F030x6 || STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
-#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
+#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
-#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
+#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
@@ -1109,32 +1417,32 @@
/** @brief Force or release APB1 peripheral reset.
*/
-#if defined(STM32F030x8) || \
- defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x8) \
+ || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
#endif /* STM32F031x6 || STM32F038xx || */
/* STM32F042x6 || STM32F048xx || */
@@ -1142,89 +1450,89 @@
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F030x8) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) ||\
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x8) \
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
#endif /* STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
#endif /* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
-#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
-#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
-#define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
+#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
-#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
+#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
/* STM32F072xB || STM32F078xx || STM32F070xB */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
+#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
-#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
+#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
/* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
-#define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
+#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
-#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
+#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F071xB || STM32F072xB || STM32F078xx || */
@@ -1232,23 +1540,23 @@
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
+#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
-#define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
+#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
/** @brief Force or release APB2 peripheral reset.
*/
-#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
+#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
-#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
+#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
/* STM32F051x8 || STM32F058xx || */
@@ -1257,25 +1565,244 @@
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
-#define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
-#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
#if defined(STM32F091xC) || defined(STM32F098xx)
-#define __USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST))
-#define __USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST))
+#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST))
+#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST))
-#define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
-#define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
+#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
+#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
#endif /* STM32F091xC || STM32F098xx */
/**
* @}
*/
+
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
+ * @brief Get the enable or disable status of peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it.
+ * @{
+ */
+/** @brief AHB Peripheral Clock Enable Disable Status
+ */
+#if defined(STM32F030x6) || defined(STM32F030x8)\
+ || defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
+
+#endif /* STM32F030x6 || STM32F030x8 || */
+ /* STM32F051x8 || STM32F058xx || STM32F070xB || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
+#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
+
+#endif /* STM32F091xC || STM32F098xx */
+
+/** @brief APB1 Peripheral Clock Enable Disable Status
+ */
+#if defined(STM32F030x8)\
+ || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
+
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || STM32F070x6 || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F030x8)\
+ || defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
+
+#endif /* STM32F031x6 || STM32F038xx || */
+ /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F030x8) \
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+
+#endif /* STM32F030x8 || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
+#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
+
+#endif /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET)
+
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
+
+#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
+#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
+
+#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
+ /* STM32F072xB || STM32F078xx || STM32F070xB */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET)
+#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET)
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET)
+#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET)
+
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+/** @brief APB1 Peripheral Clock Enable Disable Status
+ */
+#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
+#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
+
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
+ /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+
+#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
+#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
+
+#endif /* STM32F091xC || STM32F098xx || STM32F030xC */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET)
+#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET)
+#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET)
+#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET)
+
+#endif /* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
+
/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
@@ -1289,9 +1816,9 @@
* clock cycles.
* @{
*/
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
@@ -1323,9 +1850,9 @@
/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
* @{
*/
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F070x6) || defined(STM32F070xB)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F070x6) || defined(STM32F070xB)
/** @brief Macro to configure the USB clock (USBCLK).
* @param __USBCLKSource__: specifies the USB clock source.
@@ -1338,7 +1865,7 @@
/** @brief Macro to get the USB clock source.
* @retval The clock source can be one of the following values:
- * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
+ * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
*/
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
@@ -1347,10 +1874,10 @@
/* STM32F072xB || STM32F078xx || */
/* STM32F070x6 || STM32F070xB */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F051x8) || defined(STM32F058xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/** @brief Macro to configure the CEC clock.
* @param __CECCLKSource__: specifies the CEC clock source.
@@ -1373,10 +1900,10 @@
/* STM32F071xB || STM32F072xB || STM32F078xx || */
/* STM32F091xC || defined(STM32F098xx) */
-#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
- defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)\
+ || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
+ || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/** @brief Macro to configure the MCO clock.
* @param __MCOCLKSource__: specifies the MCO clock source.
@@ -1418,7 +1945,7 @@
* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
* @param __MCODiv__: specifies the MCO clock prescaler.
* This parameter can be one of the following values:
- * @arg RCC_MCO_NODIV: No division applied on MCO clock source
+ * @arg RCC_MCODIV_1: No division applied on MCO clock source
*/
#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
@@ -1428,8 +1955,8 @@
/* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
/* STM32F091xC || STM32F098xx || STM32F030xC */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/** @brief Macro to configure the USART2 clock (USART2CLK).
* @param __USART2CLKSource__: specifies the USART2 clock source.
* This parameter can be one of the following values:
@@ -1477,9 +2004,9 @@
* @}
*/
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
* @{
@@ -1642,10 +2169,11 @@
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F042x6) || defined(STM32F048xx)\
+ || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
+ || defined(STM32F091xC) || defined(STM32F098xx)
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,68 +2,20 @@
******************************************************************************
* @file stm32f0xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the Real-Time Clock (RTC) peripheral:
- * + Initialization
+ * functionalities of the Real Time Clock (RTC) peripheral:
+ * + Initialization and de-initialization functions
* + RTC Time and Date functions
* + RTC Alarm functions
- * + Backup Data Registers configuration
- * + Interrupts and flags management
- *
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
@verbatim
-
- ===============================================================================
- ##### RTC Operating Condition #####
- ===============================================================================
- [..] The real-time clock (RTC) and the RTC backup registers can be powered
- from the VBAT voltage when the main VDD supply is powered off.
- To retain the content of the RTC backup registers and supply the RTC
- when VDD is turned off, VBAT pin can be connected to an optional
- standby voltage supplied by a battery or by another source.
-
- [..] To allow the RTC to operate even when the main digital supply (VDD)
- is turned off, the VBAT pin powers the following blocks:
- (#) The RTC
- (#) The LSE oscillator
- (#) PC13 to PC15 I/Os (when available)
-
- [..] When the backup domain is supplied by VDD (analog switch connected
- to VDD), the following pins are available:
- (#) PC14 and PC15 can be used as either GPIO or LSE pins
- (#) PC13 can be used as a GPIO or as the RTC_OUT pin
-
- [..] When the backup domain is supplied by VBAT (analog switch connected
- to VBAT because VDD is not present), the following pins are available:
- (#) PC14 and PC15 can be used as LSE pins only
- (#) PC13 can be used as the RTC_OUT pin
-
- ##### Backup Domain Reset #####
- ===============================================================================
- [..] The backup domain reset sets all RTC registers and the RCC_BDCR
- register to their reset values.
- A backup domain reset is generated when one of the following events
- occurs:
- (#) Software reset, triggered by setting the BDRST bit in the
- RCC Backup domain control register (RCC_BDCR).
- (#) VDD or VBAT power on, if both supplies have previously been powered off.
-
- ##### Backup Domain Access #####
- ===================================================================
- [..] After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted write
- accesses.
- [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
- (#) Enable the Power Controller (PWR) APB1 interface clock using the
- __PWR_CLK_ENABLE() function.
- (#) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
- (#) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
- (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
-
-
- ##### How to use this driver #####
+ ==============================================================================
+ ##### How to use RTC Driver #####
===================================================================
[..]
(+) Enable the RTC domain access (see description in the section above).
@@ -80,8 +32,9 @@
*** Alarm configuration ***
===========================
[..]
- (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
- You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
+ (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
+ You can also configure the RTC Alarm with interrupt mode using the
+ HAL_RTC_SetAlarm_IT() function.
(+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
##### RTC and low power modes #####
@@ -104,7 +57,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -138,7 +91,7 @@
* @{
*/
-/** @defgroup RTC RTC HAL module driver
+/** @addtogroup RTC
* @brief RTC HAL module driver
* @{
*/
@@ -152,11 +105,11 @@
/* Private function prototypes -----------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/
-/** @defgroup RTC_Exported_Functions RTC Exported Functions
+/** @addtogroup RTC_Exported_Functions
* @{
*/
-/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup RTC_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
@@ -191,9 +144,9 @@
*/
/**
- * @brief Initializes the RTC peripheral
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Initialize the RTC according to the specified parameters
+ * in the RTC_InitTypeDef structure and initialize the associated handle.
+ * @param hrtc: RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
@@ -215,6 +168,9 @@
if(hrtc->State == HAL_RTC_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
+
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
@@ -264,14 +220,21 @@
}
/**
- * @brief DeInitializes the RTC peripheral
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @note This function doesn't reset the RTC Backup Data registers.
+ * @brief DeInitialize the RTC peripheral.
+ * @param hrtc: RTC handle
+ * @note This function doesn't reset the RTC Backup Data registers.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
{
+#if defined (STM32F030xC) || defined (STM32F070xB) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)
+ uint32_t tickstart = 0;
+#endif /* defined (STM32F030xC) || defined (STM32F070xB) ||\
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx) ||*/
+
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
@@ -297,8 +260,42 @@
/* Reset TR, DR and CR registers */
hrtc->Instance->TR = (uint32_t)0x00000000;
hrtc->Instance->DR = (uint32_t)0x00002101;
+
+#if defined (STM32F030xC) || defined (STM32F070xB) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)
+ /* Reset All CR bits except CR[2:0] */
+ hrtc->Instance->CR &= (uint32_t)0x00000007;
+
+ tickstart = HAL_GetTick();
+
+ /* Wait till WUTWF flag is set and if Time out is reached exit */
+ while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+#endif /* defined (STM32F030xC) || defined (STM32F070xB) ||\
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx) ||*/
+
/* Reset all RTC CR register bits */
hrtc->Instance->CR &= (uint32_t)0x00000000;
+#if defined (STM32F030xC) || defined (STM32F070xB) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx)
+ hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;
+#endif /* defined (STM32F030xC) || defined (STM32F070xB) ||\
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx) ||*/
hrtc->Instance->PRER = (uint32_t)0x007F00FF;
hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
@@ -327,7 +324,7 @@
}
/* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
/* De-Initialize RTC MSP */
HAL_RTC_MspDeInit(hrtc);
@@ -341,27 +338,25 @@
}
/**
- * @brief Initializes the RTC MSP.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Initialize the RTC MSP.
+ * @param hrtc: RTC handle
* @retval None
*/
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTC_MspInit could be implemented in the user file
*/
}
/**
- * @brief DeInitializes the RTC MSP.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief DeInitialize the RTC MSP.
+ * @param hrtc: RTC handle
* @retval None
*/
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTC_MspDeInit could be implemented in the user file
*/
}
@@ -370,7 +365,7 @@
* @}
*/
-/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
+/** @addtogroup RTC_Exported_Functions_Group2
* @brief RTC Time and Date functions
*
@verbatim
@@ -378,21 +373,20 @@
##### RTC Time and Date functions #####
===============================================================================
- [..] This section provide functions allowing to configure Time and Date features
+ [..] This section provides functions allowing to configure Time and Date features
@endverbatim
* @{
*/
/**
- * @brief Sets RTC current time.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Set RTC current time.
+ * @param hrtc: RTC handle
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -409,7 +403,7 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
@@ -473,14 +467,14 @@
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
/* Clear the bits to be configured */
- hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
-
+ hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK);
+
/* Configure the RTC_CR register */
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
/* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-
+ hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
+
/* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
{
@@ -510,17 +504,17 @@
}
/**
- * @brief Gets RTC current time.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Get RTC current time.
+ * @param hrtc: RTC handle
* @param sTime: Pointer to Time structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
* in the higher-order calendar shadow registers to ensure consistency between the time and date values.
- * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
+ * Reading RTC current time locks the values in calendar shadow registers until Current date is read
+ * to ensure consistency between the time and date values.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -543,7 +537,7 @@
sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
/* Check the input parameters format */
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
/* Convert the time structure parameters to Binary format */
sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
@@ -555,14 +549,13 @@
}
/**
- * @brief Sets RTC current date.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Set RTC current date.
+ * @param hrtc: RTC handle
* @param sDate: Pointer to date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -577,14 +570,14 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- if((Format == FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
+ if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
{
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
}
assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
assert_param(IS_RTC_YEAR(sDate->Year));
assert_param(IS_RTC_MONTH(sDate->Month));
@@ -632,8 +625,8 @@
hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
/* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-
+ hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
+
/* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
{
@@ -664,14 +657,13 @@
}
/**
- * @brief Gets RTC current date.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Get RTC current date.
+ * @param hrtc: RTC handle
* @param sDate: Pointer to Date structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN : Binary data format
- * @arg FORMAT_BCD : BCD data format
+ * @arg RTC_FORMAT_BIN : Binary data format
+ * @arg RTC_FORMAT_BCD : BCD data format
* @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
* in the higher-order calendar shadow registers to ensure consistency between the time and date values.
* Reading RTC current time locks the values in calendar shadow registers until Current date is read.
@@ -694,7 +686,7 @@
sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
/* Check the input parameters format */
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
/* Convert the date structure parameters to Binary format */
sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
@@ -708,7 +700,7 @@
* @}
*/
-/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
+/** @addtogroup RTC_Exported_Functions_Group3
* @brief RTC Alarm functions
*
@verbatim
@@ -722,14 +714,13 @@
* @{
*/
/**
- * @brief Sets the specified RTC Alarm.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Set the specified RTC Alarm.
+ * @param hrtc: RTC handle
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
@@ -739,8 +730,8 @@
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_ALARM(sAlarm->Alarm));
- assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
@@ -750,7 +741,7 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
@@ -831,9 +822,7 @@
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
- /* Get tick */
tickstart = HAL_GetTick();
-
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
{
@@ -870,14 +859,13 @@
}
/**
- * @brief Sets the specified RTC Alarm with Interrupt
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Set the specified RTC Alarm with Interrupt.
+ * @param hrtc: RTC handle
* @param sAlarm: Pointer to Alarm structure
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @note The Alarm register can only be written when the corresponding Alarm
* is disabled (Use the HAL_RTC_DeactivateAlarm()).
* @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
@@ -890,8 +878,8 @@
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_ALARM(sAlarm->Alarm));
- assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
@@ -901,7 +889,7 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
@@ -1007,9 +995,9 @@
__HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
/* RTC Alarm Interrupt Configuration: EXTI configuration */
- __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT);
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
- EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1023,9 +1011,8 @@
}
/**
- * @brief Deactive the specified RTC Alarm
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Deactivate the specified RTC Alarm.
+ * @param hrtc: RTC handle
* @param Alarm: Specifies the Alarm.
* This parameter can be one of the following values:
* @arg RTC_ALARM_A: AlarmA
@@ -1036,7 +1023,7 @@
uint32_t tickstart = 0;
/* Check the parameters */
- assert_param(IS_ALARM(Alarm));
+ assert_param(IS_RTC_ALARM(Alarm));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1051,7 +1038,6 @@
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
- /* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
@@ -1082,17 +1068,16 @@
}
/**
- * @brief Gets the RTC Alarm value and masks.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Get the RTC Alarm value and masks.
+ * @param hrtc: RTC handle
* @param sAlarm: Pointer to Date structure
* @param Alarm: Specifies the Alarm.
* This parameter can be one of the following values:
* @arg RTC_ALARM_A: AlarmA
* @param Format: Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
@@ -1101,7 +1086,7 @@
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_ALARM(Alarm));
+ assert_param(IS_RTC_ALARM(Alarm));
sAlarm->Alarm = RTC_ALARM_A;
@@ -1118,7 +1103,7 @@
sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
@@ -1130,9 +1115,8 @@
}
/**
- * @brief This function handles Alarm interrupt request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Handle Alarm interrupt request.
+ * @param hrtc: RTC handle
* @retval None
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
@@ -1142,16 +1126,16 @@
/* Get the status of the Interrupt */
if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
{
- /* AlarmA callback */
+ /* AlarmA callback */
HAL_RTC_AlarmAEventCallback(hrtc);
-
- /* Clear the Alarm interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
+
+ /* Clear the AlarmA interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
}
}
/* Clear the EXTI's line Flag for RTC Alarm */
- __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT);
+ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -1159,30 +1143,26 @@
/**
* @brief Alarm A callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @param hrtc: RTC handle
* @retval None
*/
__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTC_AlarmAEventCallback could be implemented in the user file
*/
}
/**
- * @brief This function handles AlarmA Polling request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Handle AlarmA Polling request.
+ * @param hrtc: RTC handle
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
+{
- /* Get tick */
- tickstart = HAL_GetTick();
+ uint32_t tickstart = HAL_GetTick();
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
{
@@ -1209,7 +1189,7 @@
* @}
*/
-/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
+/** @addtogroup RTC_Exported_Functions_Group4
* @brief Peripheral Control functions
*
@verbatim
@@ -1225,18 +1205,17 @@
*/
/**
- * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+ * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
* synchronized with RTC APB clock.
* @note The RTC Resynchronization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
* @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wake-up from low power modes
- * the software must first clear the RSF flag.
- * The software must then wait until it is set again before reading
- * the calendar, which means that the calendar registers have been
- * correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param hrtc: RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
@@ -1245,8 +1224,7 @@
/* Clear RSF flag */
hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
-
- /* Get tick */
+
tickstart = HAL_GetTick();
/* Wait the registers to be synchronised */
@@ -1265,7 +1243,7 @@
* @}
*/
-/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
+/** @addtogroup RTC_Exported_Functions_Group5
* @brief Peripheral State functions
*
@verbatim
@@ -1280,13 +1258,13 @@
* @{
*/
/**
- * @brief Returns the RTC state.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Return the RTC handle state.
+ * @param hrtc: RTC handle
* @retval HAL state
*/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
{
+ /* Return RTC handle state */
return hrtc->State;
}
@@ -1298,19 +1276,15 @@
* @}
*/
-/** @defgroup RTC_Private_Functions RTC Private Functions
+/** @addtogroup RTC_Private_Functions
* @{
*/
-
/**
- * @brief Enters the RTC Initialization mode.
+ * @brief Enter the RTC Initialization mode.
* @note The RTC Initialization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @retval HAL status:
- * - HAL_OK : RTC is in Init mode
- * - HAL_TIMEOUT : RTC is not in Init mode and in Timeout
+ * @param hrtc: RTC handle
+ * @retval HAL status
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
{
@@ -1322,7 +1296,6 @@
/* Set the Initialization mode */
hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
- /* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC is in INIT state and if Time out is reached exit */
@@ -1340,7 +1313,7 @@
/**
- * @brief Converts a 2 digit decimal to BCD format.
+ * @brief Convert a 2 digit decimal to BCD format.
* @param Value: Byte to be converted
* @retval Converted byte
*/
@@ -1358,7 +1331,7 @@
}
/**
- * @brief Converts from 2 digit BCD to Binary.
+ * @brief Convert from 2 digit BCD to Binary.
* @param Value: BCD value to be converted
* @retval Converted word
*/
@@ -1368,16 +1341,17 @@
tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
return (tmp + (Value & (uint8_t)0x0F));
}
-
/**
* @}
*/
#endif /* HAL_RTC_MODULE_ENABLED */
+
/**
* @}
*/
-
+
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_rtc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -32,8 +32,8 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
- */
+ ******************************************************************************
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_RTC_H
@@ -50,50 +50,50 @@
* @{
*/
-/** @addtogroup RTC RTC HAL module driver
+/** @defgroup RTC RTC
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Types RTC Exported Types
* @{
*/
-
+
/**
* @brief HAL State structures definition
- */
+ */
typedef enum
{
HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */
HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */
- HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
- HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
- HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
-
+ HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
+ HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
+ HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
+
}HAL_RTCStateTypeDef;
/**
- * @brief RTC Configuration Structure definition
+ * @brief RTC Configuration Structure definition
*/
typedef struct
{
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
- This parameter can be a value of @ref RTC_Hour_Formats */
+ This parameter can be a value of @ref RTC_Hour_Formats */
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
-
- uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+
+ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
- This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
-
- uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
- This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
+ This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
+
+ uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
+ This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
}RTC_InitTypeDef;
/**
@@ -103,232 +103,163 @@
{
uint8_t Hours; /*!< Specifies the RTC Time Hour.
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
- This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
+
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
+
uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
- This parameter can be a value of @ref RTC_AM_PM_Definitions */
-
+ This parameter can be a value of @ref RTC_AM_PM_Definitions */
+
uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
-
+
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
in CR register to store the operation.
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
-}RTC_TimeTypeDef;
-
+}RTC_TimeTypeDef;
+
/**
- * @brief RTC Date structure definition
+ * @brief RTC Date structure definition
*/
typedef struct
{
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
+
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
This parameter can be a value of @ref RTC_Month_Date_Definitions */
uint8_t Date; /*!< Specifies the RTC Date.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
+
uint8_t Year; /*!< Specifies the RTC Date Year.
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-
+
}RTC_DateTypeDef;
/**
- * @brief RTC Alarm structure definition
+ * @brief RTC Alarm structure definition
*/
typedef struct
{
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
-
+
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
- This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
+ This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
- This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-
+
uint32_t Alarm; /*!< Specifies the alarm .
- This parameter can be a value of @ref RTC_Alarms_Definitions */
+ This parameter can be a value of @ref RTC_Alarms_Definitions */
}RTC_AlarmTypeDef;
/**
- * @brief Time Handle Structure definition
- */
+ * @brief RTC Handle Structure definition
+ */
typedef struct
{
- RTC_TypeDef *Instance; /*!< Register base address */
-
- RTC_InitTypeDef Init; /*!< RTC required parameters */
+ RTC_TypeDef *Instance; /*!< Register base address */
+
+ RTC_InitTypeDef Init; /*!< RTC required parameters */
+
+ HAL_LockTypeDef Lock; /*!< RTC locking object */
+
+ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
+
+}RTC_HandleTypeDef;
- HAL_LockTypeDef Lock; /*!< RTC locking object */
-
- __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
-
-}RTC_HandleTypeDef;
/**
* @}
*/
-
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
*/
-/** @defgroup RTC_Mask_Definition RTC Mask Definition
- * @{
- */
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
-#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
-#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
-
-#define RTC_TIMEOUT_VALUE 1000
-/**
- * @}
- */
-
/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
- */
+ */
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
-#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
- ((FORMAT) == RTC_HOURFORMAT_24))
/**
* @}
- */
+ */
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
- */
+ */
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
-
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
- ((POL) == RTC_OUTPUT_POLARITY_LOW))
/**
* @}
- */
+ */
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
- */
+ */
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)0x00040000)
+/**
+ * @}
+ */
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
- ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
+ * @{
+ */
+#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
+#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
+/**
+ * @}
+ */
+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
+ * @{
+ */
+#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
+#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
+#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
/**
* @}
*/
-/** @defgroup RTC_Asynchronous_Predivider RTC Asynchronous Predivider
- * @{
- */
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
-/**
- * @}
- */
-
-/** @defgroup RTC_Synchronous_Predivider RTC Synchronous Predivider
- * @{
- */
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Definitions RTC Time Definitions
+/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
* @{
- */
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
-/**
- * @}
- */
-
-/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
- * @{
- */
-#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
-#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
-
-#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
-/**
- * @}
- */
-
-/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
- * @{
- */
-#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
-#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
-#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
-
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
- ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
- ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
-/**
- * @}
- */
-
-/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
- * @{
- */
+ */
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
-
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
- ((OPERATION) == RTC_STOREOPERATION_SET))
/**
* @}
*/
/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions
* @{
- */
-#define FORMAT_BIN ((uint32_t)0x000000000)
-#define FORMAT_BCD ((uint32_t)0x000000001)
-
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD))
-/**
- * @}
- */
-
-/** @defgroup RTC_Year_Date_Definitions RTC Year Date Definitions
- * @{
- */
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
+ */
+#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
+#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
/**
* @}
*/
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
* @{
- */
-
+ */
/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
@@ -342,16 +273,13 @@
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
-
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
-#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
/**
* @}
- */
+ */
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
* @{
- */
+ */
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
@@ -359,134 +287,80 @@
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
-
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
/**
* @}
- */
+ */
-/** @defgroup RTC_Alarm_Definitions RTC Alarm Definitions
+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
* @{
- */
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
- ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+ */
+#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
/**
* @}
- */
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
- * @{
- */
-#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
+ */
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
- ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-/**
- * @}
- */
-
-/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
+/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
* @{
- */
+ */
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
-
-#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
/**
* @}
- */
+ */
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
* @{
- */
+ */
#define RTC_ALARM_A RTC_CR_ALRAE
-#define IS_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Value RTC Alarm Sub Seconds Value
- * @{
- */
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
/**
* @}
- */
+ */
- /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
- */
-#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
- There is no comparison on sub seconds
+ */
+#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
+ There is no comparison on sub seconds
for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
comparison. Only SS[0] is compared. */
-#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
comparison. Only SS[1:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
comparison. Only SS[2:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
comparison. Only SS[3:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
comparison. Only SS[4:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
comparison. Only SS[5:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
comparison. Only SS[6:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
comparison. Only SS[7:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
comparison. Only SS[8:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
comparison. Only SS[9:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
comparison.Only SS[11:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
+#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
comparison.Only SS[13:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
+#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
to activate alarm. */
-
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_None))
/**
* @}
- */
+ */
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
* @{
@@ -495,9 +369,9 @@
#define RTC_IT_WUT ((uint32_t)0x00004000)
#define RTC_IT_ALRA ((uint32_t)0x00001000)
#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
-#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
-#define RTC_IT_TAMP3 ((uint32_t)0x00080000)
+#define RTC_IT_TAMP1 ((uint32_t)0x00020000) /*only for RTC_ISR flag check*/
+#define RTC_IT_TAMP2 ((uint32_t)0x00040000) /*only for RTC_ISR flag check*/
+#define RTC_IT_TAMP3 ((uint32_t)0x00080000) /*only for RTC_ISR flag check*/
/**
* @}
*/
@@ -525,14 +399,14 @@
/**
* @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
+ */
+
+/* Exported macros ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Macros RTC Exported Macros
* @{
*/
-
-/** @brief Reset RTC handle state
+
+/** @brief Reset RTC handle state
* @param __HANDLE__: RTC handle.
* @retval None
*/
@@ -557,8 +431,8 @@
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->WPR = 0xFF; \
- } while(0)
-
+ } while(0)
+
/**
* @brief Enable the RTC ALARMA peripheral.
* @param __HANDLE__: specifies the RTC handle.
@@ -596,17 +470,27 @@
/**
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt to check.
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
+ * This parameter can be:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
/**
* @brief Get the selected RTC Alarm's flag status.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to check.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @arg RTC_FLAG_ALRAWF
@@ -617,84 +501,103 @@
/**
* @brief Clear the RTC Alarm's pending flags.
* @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * @param __FLAG__: specifies the RTC Alarm Flag sources to clear.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @retval None
*/
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-
-#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+
+/**
+ * @brief Enable interrupt on the RTC Alarm associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Enable the RTC Exti line.
- * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_EXTI_LINE_ALARM_EVENT
- * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
- * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
- * @retval None
- */
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
-
-/* alias define maintained for legacy */
-#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
-
-/**
- * @brief Disable the RTC Exti line.
- * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_EXTI_LINE_ALARM_EVENT
- * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
- * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
+ * @brief Disable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable event on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable event on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-/* alias define maintained for legacy */
-#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+/**
+ * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_EXTI_LINE_ALARM_EVENT
- * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
- * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
- * @retval None
+ * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
*/
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
/**
- * @brief Clear the RTC Exti flags.
- * @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_EXTI_LINE_ALARM_EVENT
- * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
- * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
- * @retval None
+ * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
*/
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__))
+#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
-/* alias define maintained for legacy */
-#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+/**
+ * @brief Clear the RTC Alarm associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
/**
+ * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
+/**
* @}
*/
-/* Include RTC HAL Extension module */
+/* Include RTC HAL Extended module */
#include "stm32f0xx_hal_rtc_ex.h"
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_Exported_Functions RTC Exported Functions
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
*/
-/** @addtogroup RTC_Exported_Functions_Group1
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
@@ -707,7 +610,7 @@
* @}
*/
-/** @addtogroup RTC_Exported_Functions_Group2
+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
* @{
*/
@@ -720,7 +623,7 @@
* @}
*/
-/** @addtogroup RTC_Exported_Functions_Group3
+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
* @{
*/
/* RTC Alarm functions ********************************************************/
@@ -735,7 +638,7 @@
* @}
*/
-/** @addtogroup RTC_Exported_Functions_Group4
+/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
@@ -744,7 +647,7 @@
* @}
*/
-/** @addtogroup RTC_Exported_Functions_Group5
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
* @{
*/
/* Peripheral State functions *************************************************/
@@ -757,23 +660,125 @@
* @}
*/
-/** @addtogroup RTC_Private_Functions
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Constants RTC Private Constants
+ * @{
+ */
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
+#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
+#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
+ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
+ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
+ RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
+
+#define RTC_TIMEOUT_VALUE 1000
+
+#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTC_Private_Macros RTC Private Macros
+ * @{
+ */
+
+/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
* @{
- */
+ */
+#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
+ ((FORMAT) == RTC_HOURFORMAT_24))
+
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+ ((POL) == RTC_OUTPUT_POLARITY_LOW))
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
+
+#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+ ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+ ((OPERATION) == RTC_STOREOPERATION_SET))
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
+ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Functions RTC Private Functions
+ * @{
+ */
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
/**
* @}
- */
+ */
/**
* @}
- */
-
- /**
+ */
+
+/**
* @}
- */
+ */
#ifdef __cplusplus
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,35 +2,35 @@
******************************************************************************
* @file stm32f0xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Extended RTC HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the Real Time Clock (RTC) Extension peripheral:
- * + RTC TimeStamp functions
- * + RTC Tamper functions
+ * functionalities of the Real Time Clock (RTC) Extended peripheral:
+ * + RTC Time Stamp functions
+ * + RTC Tamper functions
* + RTC Wake-up functions
- * + Extension Control functions
- * + Extension RTC features functions
+ * + Extended Control functions
+ * + Extended RTC features functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
- (+) Enable the RTC domain access (see description in the section above).
+ (+) Enable the RTC domain access.
(+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
format using the HAL_RTC_Init() function.
*** RTC Wake-up configuration ***
================================
[..]
- (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
- function. You can also configure the RTC Wake-up timer in interrupt mode
+ (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
+ function. You can also configure the RTC Wakeup timer with interrupt mode
using the HAL_RTCEx_SetWakeUpTimer_IT() function.
- (+) To read the RTC Wake-up Counter register, use the HAL_RTCEx_GetWakeUpTimer()
+ (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
function.
- (@) Not available on F030x6/x8/xC and F070x6/xB
+ (@) Not available on F030x4/x6/x8 and F070x6
*** TimeStamp configuration ***
===============================
@@ -57,14 +57,14 @@
function.
(+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
function.
- (@) Not available on F030x6/x8/xC and F070x6/xB
+ (@) Not available on F030x6/x8/xC and F070x6/xB (F0xx Value Line devices)
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -98,8 +98,10 @@
* @{
*/
-/** @defgroup RTCEx RTCEx Extended HAL module driver
- * @brief RTCEx Extended HAL module driver
+
+
+/** @addtogroup RTCEx
+ * @brief RTC Extended HAL module driver
* @{
*/
@@ -112,11 +114,12 @@
/* Private function prototypes -----------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
+/** @addtogroup RTCEx_Exported_Functions
* @{
*/
-
-/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions
+
+
+/** @addtogroup RTCEx_Exported_Functions_Group1
* @brief RTC TimeStamp and Tamper functions
*
@verbatim
@@ -131,11 +134,10 @@
*/
/**
- * @brief Sets TimeStamp.
- * @note This API must be called before enabling the TimeStamp feature.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+ * @brief Set TimeStamp.
+ * @note This API must be called before enabling the TimeStamp feature.
+ * @param hrtc: RTC handle
+ * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
* activated.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
@@ -144,7 +146,7 @@
* falling edge of the related pin.
* @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
@@ -186,9 +188,8 @@
}
/**
- * @brief Sets TimeStamp with Interrupt.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Set TimeStamp with Interrupt.
+ * @param hrtc: RTC handle
* @note This API must be called before enabling the TimeStamp feature.
* @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
* activated.
@@ -199,7 +200,7 @@
* falling edge of the related pin.
* @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
@@ -232,9 +233,9 @@
__HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
/* RTC timestamp Interrupt Configuration: EXTI configuration */
- __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
- EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -248,9 +249,8 @@
}
/**
- * @brief Deactivates TimeStamp.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Deactivate TimeStamp.
+ * @param hrtc: RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
@@ -286,15 +286,15 @@
}
/**
- * @brief Gets the RTC TimeStamp value.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Get the RTC TimeStamp value.
+ * @param hrtc: RTC handle
+
* @param sTimeStamp: Pointer to Time structure
* @param sTimeStampDate: Pointer to Date structure
* @param Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg FORMAT_BIN: Binary data format
- * @arg FORMAT_BCD: BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
@@ -322,7 +322,7 @@
sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
/* Check the input parameters format */
- if(Format == FORMAT_BIN)
+ if(Format == RTC_FORMAT_BIN)
{
/* Convert the TimeStamp structure parameters to Binary format */
sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
@@ -342,10 +342,9 @@
}
/**
- * @brief Sets Tamper
- * @note By calling this API we disable the tamper interrupt for all tampers.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Set Tamper
+ * @note By calling this API we disable the tamper interrupt for all tampers.
+ * @param hrtc: RTC handle
* @param sTamper: Pointer to Tamper Structure.
* @retval HAL status
*/
@@ -354,13 +353,13 @@
uint32_t tmpreg = 0;
/* Check the parameters */
- assert_param(IS_TAMPER(sTamper->Tamper));
- assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
- assert_param(IS_TAMPER_FILTER(sTamper->Filter));
- assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
- assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
- assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
- assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -403,13 +402,13 @@
uint32_t tmpreg = 0;
/* Check the parameters */
- assert_param(IS_TAMPER(sTamper->Tamper));
- assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
- assert_param(IS_TAMPER_FILTER(sTamper->Filter));
- assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
- assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
- assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
- assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
+ assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
+ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
+ assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
+ assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -436,9 +435,9 @@
hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
/* RTC Tamper Interrupt Configuration: EXTI configuration */
- __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
-
- EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
hrtc->State = HAL_RTC_STATE_READY;
@@ -449,16 +448,15 @@
}
/**
- * @brief Deactivates Tamper.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Deactivate Tamper.
+ * @param hrtc: RTC handle
* @param Tamper: Selected tamper pin.
* This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
{
- assert_param(IS_TAMPER(Tamper));
+ assert_param(IS_RTC_TAMPER(Tamper));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -477,9 +475,8 @@
}
/**
- * @brief This function handles TimeStamp interrupt request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Handle TimeStamp interrupt request.
+ * @param hrtc: RTC handle
* @retval None
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
@@ -491,9 +488,9 @@
{
/* TIMESTAMP callback */
HAL_RTCEx_TimeStampEventCallback(hrtc);
-
+
/* Clear the TIMESTAMP interrupt pending bit */
- __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
}
}
@@ -503,11 +500,11 @@
/* Get the TAMPER Interrupt enable bit and pending bit */
if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET)
{
- /* Tamper callback */
+ /* Tamper1 callback */
HAL_RTCEx_Tamper1EventCallback(hrtc);
-
- /* Clear the Tamper interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
+
+ /* Clear the Tamper1 interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
}
}
@@ -517,10 +514,10 @@
/* Get the TAMPER Interrupt enable bit and pending bit */
if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET)
{
- /* Tamper callback */
+ /* Tamper2 callback */
HAL_RTCEx_Tamper2EventCallback(hrtc);
-
- /* Clear the Tamper interrupt pending bit */
+
+ /* Clear the Tamper2 interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
}
}
@@ -532,17 +529,17 @@
/* Get the TAMPER Interrupt enable bit and pending bit */
if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET)
{
- /* Tamper callback */
+ /* Tamper3 callback */
HAL_RTCEx_Tamper3EventCallback(hrtc);
- /* Clear the Tamper interrupt pending bit */
+ /* Clear the Tamper3 interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
}
}
#endif
/* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
- __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -550,44 +547,41 @@
/**
* @brief TimeStamp callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @param hrtc: RTC handle
* @retval None
*/
__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
*/
}
/**
- * @brief Tamper 1 callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Tamper 1 callback.
+ * @param hrtc: RTC handle
* @retval None
*/
__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
*/
}
/**
* @brief Tamper 2 callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @param hrtc: RTC handle
* @retval None
*/
__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
*/
}
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
/**
* @brief Tamper 3 callback.
* @param hrtc: RTC handle
@@ -595,31 +589,27 @@
*/
__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
*/
}
#endif
/**
- * @brief This function handles TimeStamp polling request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Handle TimeStamp polling request.
+ * @param hrtc: RTC handle
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Get tick */
- tickstart = HAL_GetTick();
+{
+ uint32_t tickstart = HAL_GetTick();
while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
{
if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
{
- /* Clear the TIMESTAMP Overrun Flag */
+ /* Clear the TIMESTAMP OverRun Flag */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
/* Change TIMESTAMP state */
@@ -640,23 +630,19 @@
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
-
+
return HAL_OK;
}
/**
- * @brief This function handles Tamper1 Polling.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Handle Tamper 1 Polling.
+ * @param hrtc: RTC handle
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Get tick */
- tickstart = HAL_GetTick();
+{
+ uint32_t tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET)
@@ -673,26 +659,22 @@
/* Clear the Tamper Flag */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
-
+
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief This function handles Tamper2 Polling.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Handle Tamper 2 Polling.
+ * @param hrtc: RTC handle
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Get tick */
- tickstart = HAL_GetTick();
+{
+ uint32_t tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP2F) == RESET)
@@ -718,18 +700,14 @@
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
/**
- * @brief This function handles Tamper3 Polling.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Handle Tamper 3 Polling.
+ * @param hrtc: RTC handle
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t tickstart = 0;
-
- /* Get tick */
- tickstart = HAL_GetTick();
+ uint32_t tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET)
@@ -758,10 +736,10 @@
* @}
*/
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions
- * @brief RTC Wake-up functions
- *
+#if defined(STM32F070xB) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+/** @addtogroup RTCEx_Exported_Functions_Group2
+ * @brief RTC Wake-up functions
+ *
@verbatim
===============================================================================
##### RTC Wake-up functions #####
@@ -774,11 +752,10 @@
*/
/**
- * @brief Sets wake up timer.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Set wake up timer.
+ * @param hrtc: RTC handle
* @param WakeUpCounter: Wake up counter
- * @param WakeUpClock: Wake up clock
+ * @param WakeUpClock: Wake up clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
@@ -786,8 +763,8 @@
uint32_t tickstart = 0;
/* Check the parameters */
- assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
- assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -798,8 +775,7 @@
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
- /* Get tick */
+
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
@@ -819,16 +795,16 @@
}
}
- /* Clear the Wake-up Timer clock source bits in CR register */
+ /* Clear the Wakeup Timer clock source bits in CR register */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
/* Configure the clock source */
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
- /* Configure the Wake-up Timer counter */
+ /* Configure the Wakeup Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
- /* Enable the Wake-up Timer */
+ /* Enable the Wakeup Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
/* Enable the write protection for RTC registers */
@@ -843,9 +819,8 @@
}
/**
- * @brief Sets wake up timer with interrupt
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Set wake up timer with interrupt.
+ * @param hrtc: RTC handle
* @param WakeUpCounter: Wake up counter
* @param WakeUpClock: Wake up clock
* @retval HAL status
@@ -855,8 +830,8 @@
uint32_t tickstart = 0;
/* Check the parameters */
- assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
- assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
+ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
+ assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -868,7 +843,6 @@
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
- /* Get tick */
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
@@ -888,24 +862,24 @@
}
}
- /* Configure the Wake-up Timer counter */
+ /* Configure the Wakeup Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
- /* Clear the Wake-up Timer clock source bits in CR register */
+ /* Clear the Wakeup Timer clock source bits in CR register */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
/* Configure the clock source */
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
/* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
- __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
- EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
/* Configure the Interrupt in the RTC_CR register */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
-
- /* Enable the Wake-up Timer */
+
+ /* Enable the Wakeup Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
/* Enable the write protection for RTC registers */
@@ -920,9 +894,8 @@
}
/**
- * @brief Deactivates wake up timer counter.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Deactivate wake up timer counter.
+ * @param hrtc: RTC handle
* @retval HAL status
*/
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -937,15 +910,13 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Disable the Wake-up Timer */
+ /* Disable the Wakeup Timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
- /* Get tick */
tickstart = HAL_GetTick();
-
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
{
@@ -975,9 +946,8 @@
}
/**
- * @brief Gets wake up timer counter.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Get wake up timer counter.
+ * @param hrtc: RTC handle
* @retval Counter value
*/
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -987,9 +957,8 @@
}
/**
- * @brief This function handles Wake Up Timer interrupt request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Handle Wake Up Timer interrupt request.
+ * @param hrtc: RTC handle
* @retval None
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
@@ -999,53 +968,49 @@
/* Get the status of the Interrupt */
if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
{
- /* WAKEUPTIMER callback */
+ /* WAKEUPTIMER callback */
HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
-
+
/* Clear the WAKEUPTIMER interrupt pending bit */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
}
}
/* Clear the EXTI's line Flag for RTC WakeUpTimer */
- __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
-
+ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
/**
* @brief Wake Up Timer callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @param hrtc: RTC handle
* @retval None
*/
__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
*/
}
+
/**
- * @brief This function handles Wake Up Timer Polling.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Handle Wake Up Timer Polling.
+ * @param hrtc: RTC handle
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t tickstart = 0;
-
- /* Get tick */
- tickstart = HAL_GetTick();
+ uint32_t tickstart = HAL_GetTick();
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
@@ -1056,7 +1021,7 @@
/* Clear the WAKEUPTIMER Flag */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
+
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -1066,14 +1031,14 @@
/**
* @}
*/
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+#endif /* defined(STM32F070xB) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) | defined(STM32F030xC) */
-/** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions
- * @brief Extension Peripheral Control functions
- *
+/** @addtogroup RTCEx_Exported_Functions_Group3
+ * @brief Extended Peripheral Control functions
+ *
@verbatim
===============================================================================
- ##### Extension Peripheral Control functions #####
+ ##### Extended Peripheral Control functions #####
===============================================================================
[..]
This subsection provides functions allowing to
@@ -1096,9 +1061,8 @@
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/**
- * @brief Writes a data in a specified RTC Backup data register.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Write a data in a specified RTC Backup data register.
+ * @param hrtc: RTC handle
* @param BackupRegister: RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
* specify the register.
@@ -1111,7 +1075,7 @@
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
-
+
tmp = (uint32_t)&(hrtc->Instance->BKP0R);
tmp += (BackupRegister * 4);
@@ -1121,8 +1085,7 @@
/**
* @brief Reads data from the specified RTC Backup data Register.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @param hrtc: RTC handle
* @param BackupRegister: RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
* specify the register.
@@ -1137,16 +1100,15 @@
tmp = (uint32_t)&(hrtc->Instance->BKP0R);
tmp += (BackupRegister * 4);
-
+
/* Read the specified register */
return (*(__IO uint32_t *)tmp);
}
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
/**
- * @brief Sets the Smooth calibration parameters.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Set the Smooth calibration parameters.
+ * @param hrtc: RTC handle
* @param SmoothCalibPeriod: Select the Smooth Calibration Period.
* This parameter can be can be one of the following values :
* @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
@@ -1156,21 +1118,21 @@
* This parameter can be one of the following values:
* @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
* @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
- * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+ * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
* This parameter can be one any value from 0 to 0x000001FF.
* @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
- * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
- * SmouthCalibMinusPulsesValue must be equal to 0.
+ * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
+ * SmoothCalibMinusPulsesValue mut be equal to 0.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
{
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
- assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
+ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue));
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1183,7 +1145,6 @@
/* check if a calibration is pending*/
if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
{
- /* Get tick */
tickstart = HAL_GetTick();
/* check if a calibration is pending*/
@@ -1206,7 +1167,7 @@
}
/* Configure the Smooth calibration settings */
- hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);
+ hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1221,10 +1182,9 @@
}
/**
- * @brief Configures the Synchronization Shift Control Settings.
+ * @brief Configure the Synchronization Shift Control Settings.
* @note When REFCKON is set, firmware must not write to Shift control register.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @param hrtc: RTC handle
* @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
* This parameter can be one of the following values :
* @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
@@ -1249,7 +1209,6 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Get tick */
tickstart = HAL_GetTick();
/* Wait until the shift is completed*/
@@ -1319,12 +1278,11 @@
}
/**
- * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc: RTC handle
* @param CalibOutput : Select the Calibration output Selection .
* This parameter can be one of the following values:
- * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
+ * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
* @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
* @retval HAL status
*/
@@ -1362,9 +1320,8 @@
}
/**
- * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc: RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
@@ -1392,9 +1349,8 @@
}
/**
- * @brief Enables the RTC reference clock detection.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Enable the RTC reference clock detection.
+ * @param hrtc: RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
@@ -1443,8 +1399,7 @@
/**
* @brief Disable the RTC reference clock detection.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @param hrtc: RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
@@ -1456,7 +1411,7 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
+
/* Set Initialization mode */
if(RTC_EnterInitMode(hrtc) != HAL_OK)
{
@@ -1492,10 +1447,9 @@
}
/**
- * @brief Enables the Bypass Shadow feature.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
- * @note When the Bypass Shadow is enabled the calendar value are taken
+ * @brief Enable the Bypass Shadow feature.
+ * @param hrtc: RTC handle
+ * @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
* @retval HAL status
*/
@@ -1525,9 +1479,8 @@
}
/**
- * @brief Disables the Bypass Shadow feature.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
- * the configuration information for RTC.
+ * @brief Disable the Bypass Shadow feature.
+ * @param hrtc: RTC handle
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
* @retval HAL status
@@ -1543,7 +1496,7 @@
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Reset the BYPSHAD bit */
- hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;
+ hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1566,6 +1519,7 @@
*/
#endif /* HAL_RTC_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rtc_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_rtc_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
- * @brief Header file of RTC HAL Extension module.
+ * @version V1.3.0
+ * @date 26-June-2015
+ * @brief Header file of RTC HAL Extended module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -50,7 +50,7 @@
* @{
*/
-/** @addtogroup RTCEx
+/** @defgroup RTCEx RTCEx
* @{
*/
@@ -100,18 +100,10 @@
*/
#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000)
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000)
#endif
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
- ((OUTPUT) == RTC_OUTPUT_WAKEUP))
-#else
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMA))
-#endif
/**
* @}
*/
@@ -125,8 +117,6 @@
#define RTC_BKP_DR2 ((uint32_t)0x00000002)
#define RTC_BKP_DR3 ((uint32_t)0x00000003)
#define RTC_BKP_DR4 ((uint32_t)0x00000004)
-
-#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
/**
* @}
*/
@@ -138,12 +128,20 @@
#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008)
-#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
- ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
/**
* @}
*/
+/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
+ * @{
+ */
+#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+
/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definition
* @{
*/
@@ -153,27 +151,11 @@
#define RTC_TAMPER_3 RTC_TAFCR_TAMP3E
#endif
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-#define IS_TAMPER(TAMPER) (((TAMPER) == RTC_TAMPER_1) || \
- ((TAMPER) == RTC_TAMPER_2) || \
- ((TAMPER) == RTC_TAMPER_3))
-#else
-#define IS_TAMPER(TAMPER) (((TAMPER) == RTC_TAMPER_1) || \
- ((TAMPER) == RTC_TAMPER_2))
-#endif
/**
* @}
*/
-/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
- * @{
- */
-#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000)
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_PC13))
-/**
- * @}
- */
/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Trigger Definition
* @{
@@ -183,10 +165,6 @@
#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
-#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
/**
* @}
@@ -204,10 +182,6 @@
#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8
consecutive samples at the active level. */
-#define IS_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
- ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
- ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
- ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
/**
* @}
*/
@@ -232,14 +206,6 @@
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 256 */
-#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
- ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
/**
* @}
*/
@@ -256,10 +222,6 @@
#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
sampling during 8 RTCCLK cycles */
-#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
- ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
- ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
- ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
/**
* @}
*/
@@ -270,8 +232,6 @@
#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
- ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
/**
* @}
*/
@@ -279,11 +239,9 @@
/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definition
* @{
*/
-#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before sampling */
#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */
-#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
- ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
/**
* @}
*/
@@ -299,14 +257,7 @@
#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004)
#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006)
-#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
- ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-#define IS_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
/**
* @}
*/
@@ -322,9 +273,6 @@
#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
period is 8s, else 2exp18 RTCCLK seconds */
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
- ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
- ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
/**
* @}
*/
@@ -338,16 +286,15 @@
#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
during a 32-second window = CALM[8:0] */
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
- ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
/**
* @}
*/
-
-/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions RTCEx Smooth calib Minus pulses Definition
+ /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
* @{
*/
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
+#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)
+
/**
* @}
*/
@@ -358,41 +305,23 @@
#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000)
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
- ((SEL) == RTC_SHIFTADD1S_SET))
/**
* @}
*/
-
-/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value RTCEx Substract Fraction Of Second Value
- * @{
- */
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
/**
* @}
*/
- /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definition
- * @{
- */
-#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
-#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000)
-
-#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
- ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
* @{
*/
-
+
+/* ---------------------------------WAKEUPTIMER---------------------------------*/
+/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
+ * @{
+ */
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/**
* @brief Enable the RTC WakeUp Timer peripheral.
@@ -400,32 +329,499 @@
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+
+/**
+ * @brief Disable the RTC WakeUp Timer peripheral.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
+
+/**
+ * @brief Enable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC WakeUpTimer interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
+ * This parameter can be:
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC WakeUpTimer's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @arg RTC_FLAG_WUTWF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Clear the RTC Wake Up timer's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_WUTF
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/* WAKE-UP TIMER EXTI */
+/* ------------------ */
+/**
+ * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Enable the RTC TimeStamp peripheral.
+ * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable event on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable event on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Clear the RTC WakeUp Timer associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+/**
+ * @}
+ */
+
+/* ---------------------------------TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Timestamp RTC Timestamp
+ * @{
+ */
+/**
+ * @brief Enable the RTC TimeStamp peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/**
- * @brief Disable the RTC WakeUp Timer peripheral.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
-
-/**
- * @brief Disable the RTC TimeStamp peripheral.
+ * @brief Disable the RTC TimeStamp peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
/**
+ * @brief Enable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC TimeStamp interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+
+/**
+ * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TS: TimeStamp interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+ * @brief Get the selected RTC TimeStamp's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @arg RTC_FLAG_TSOVF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+/**
+ * @brief Clear the RTC Time Stamp's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Alarm Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF
+ * @retval None
+ */
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+ * @}
+ */
+
+/* ---------------------------------TAMPER------------------------------------*/
+/** @defgroup RTCEx_Tamper RTC Tamper
+ * @{
+ */
+
+/**
+ * @brief Enable the RTC Tamper1 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
+
+/**
+ * @brief Disable the RTC Tamper1 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
+
+/**
+ * @brief Enable the RTC Tamper2 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
+
+/**
+ * @brief Disable the RTC Tamper2 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/**
+ * @brief Enable the RTC Tamper3 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP3E))
+
+/**
+ * @brief Disable the RTC Tamper3 input detection.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP3E))
+
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+/**
+ * @brief Enable the RTC Tamper interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: Tamper interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Tamper interrupt.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: Tamper interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__))
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @arg RTC_IT_TAMP3: Tamper3 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+#else
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP1: Tamper1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper2 interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+
+/**
+ * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
+ * This parameter can be:
+ * @arg RTC_IT_TAMP: Tamper interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+/**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP2F
+ * @arg RTC_FLAG_TAMP3F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP2F
+ * @arg RTC_FLAG_TAMP3F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#else
+
+/**
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag is pending or not.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP2F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+
+
+/**
+ * @brief Clear the RTC Tamper's pending flags.
+ * @param __HANDLE__: specifies the RTC handle.
+ * @param __FLAG__: specifies the RTC Tamper Flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP2F
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
+/**
+ * @}
+ */
+
+/* --------------------------TAMPER/TIMESTAMP---------------------------------*/
+/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI
+ * @{
+ */
+
+/* TAMPER TIMESTAMP EXTI */
+/* --------------------- */
+/**
+ * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable event on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable event on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+
+/**
+ * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
+
+/**
+ * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * This parameter can be:
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
+
+/**
+ * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
+ * @retval Line Status.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+
+/**
+ * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
+ * @retval None.
+ */
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
+/**
+ * @}
+ */
+
+/* ------------------------------Calibration----------------------------------*/
+/** @defgroup RTCEx_Calibration RTC Calibration
+ * @{
+ */
+
+/**
* @brief Enable the RTC calibration output.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
@@ -454,170 +850,32 @@
#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
/**
- * @brief Enable the RTC TimeStamp interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
-/**
- * @brief Enable the RTC WakeUpTimer interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
-
-/**
- * @brief Disable the RTC TimeStamp interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
-/**
- * @brief Disable the RTC WakeUpTimer interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
-
-/**
- * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_TAMP1
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
-/**
- * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
-
-/**
- * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_TS: TimeStamp interrupt
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-
-/**
- * @brief Get the selected RTC TimeStamp's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
- * @arg RTC_FLAG_TSOVF
- * @retval None
- */
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
-/**
- * @brief Get the selected RTC WakeUpTimer's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @arg RTC_FLAG_WUTWF
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
-
-/**
- * @brief Get the selected RTC Tamper's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
* @brief Get the selected RTC shift operation's flag status.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC shift operation Flag is pending or not.
- * This parameter can be:
- * @arg RTC_FLAG_SHPF
+ * This parameter can be:
+ * @arg RTC_FLAG_SHPF
* @retval None
*/
#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
/**
- * @brief Clear the RTC Time Stamp's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
- * @retval None
+ * @}
*/
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
- * @brief Clear the RTC Tamper's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @retval None
- */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
-/**
- * @brief Clear the RTC Wake Up timer's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @retval None
- */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC) */
-/**
* @}
*/
-
+
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTCEx_Exported_Functions
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
*/
-/** @addtogroup RTCEx_Exported_Functions_Group1
+/* RTC TimeStamp and Tamper functions *****************************************/
+/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions
* @{
*/
-/* RTC TimeStamp and Tamper functions *****************************************/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
@@ -645,11 +903,11 @@
*/
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
-/** @addtogroup RTCEx_Exported_Functions_Group2
+/* RTC Wake-up functions ******************************************************/
+/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
* @{
*/
-/* RTC Wake-up functions ******************************************************/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
@@ -662,11 +920,11 @@
* @}
*/
-/** @addtogroup RTCEx_Exported_Functions_Group3
+/* Extended Control functions ************************************************/
+/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
* @{
*/
-
-/* Extension Control functions ************************************************/
+
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB)
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
@@ -684,8 +942,103 @@
* @}
*/
-/* Extension RTC features functions *******************************************/
+/* Extended RTC features functions *******************************************/
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
+ * @{
+ */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR19) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR20) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
+ * @{
+ */
+
+/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
+ * @{
+ */
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
+ ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+#else
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA))
+#endif
+
+#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
+
+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
+ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+#else
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFF6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+
+#endif
+
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
+
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
+ ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
+ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
+ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
+ ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
+ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
+
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+
+
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
+ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+
+
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
+ ((SEL) == RTC_SHIFTADD1S_SET))
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
+ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
/**
* @}
*/
@@ -696,8 +1049,12 @@
/**
* @}
- */
+ */
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,109 +2,112 @@
******************************************************************************
* @file stm32f0xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief SMARTCARD HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
* + Peripheral Control functions
*
- @verbatim
- ===============================================================================
+ @verbatim
+ ==============================================================================
##### How to use this driver #####
- ===============================================================================
- [..]
+ ==============================================================================
+ [..]
The SMARTCARD HAL driver can be used as follows:
-
- (#) Declare a SMARTCARD_HandleTypeDef handle structure.
- (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit ()API:
+
+ (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
+ (#) Associate a USART to the SMARTCARD handle hsmartcard.
+ (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
(++) Enable the USARTx interface clock.
- (++) SMARTCARD pins configuration:
- (+++) Enable the clock for the SMARTCARD GPIOs.
- (+++) Configure these SMARTCARD pins as alternate function pull-up.
+ (++) USART pins configuration:
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
(++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
and HAL_SMARTCARD_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
(++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
and HAL_SMARTCARD_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
- error enabling or disabling in the hsmartcard Init structure.
-
+ error enabling or disabling in the hsmartcard handle Init structure.
+
(#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
- in the hsmartcard AdvancedInit structure.
+ in the hsmartcard handle AdvancedInit structure.
- (#) Initialize the SMARTCARD associated USART registers by calling the HAL_SMARTCARD_Init() API:
- (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) by
- calling the customed HAL_SMARTCARD_MspInit() API.
-
- -@@- The specific SMARTCARD interrupts (Transmission complete interrupt,
+ (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+ (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMARTCARD_MspInit() API.
+ [..]
+ (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
- (#) Three operation modes are available within this driver :
-
+ [..]
+ [..] Three operation modes are available within this driver :
+
*** Polling mode IO operation ***
=================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
(+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
-
- *** Interrupt mode IO operation ***
+
+ *** Interrupt mode IO operation ***
===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
- (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
- (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
- (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
- *** DMA mode IO operation ***
+ *** DMA mode IO operation ***
==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
- (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
- (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
- (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
*** SMARTCARD HAL driver macros list ***
========================================
[..]
Below the list of most used macros in SMARTCARD HAL driver.
-
- (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
- (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
- (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
+
+ (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
+ (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
+ (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
(+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
(+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
(+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
-
- [..]
+ (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
+
+ [..]
(@) You can refer to the SMARTCARD HAL driver header file for more useful macros
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -128,7 +131,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -136,35 +139,35 @@
#ifdef HAL_SMARTCARD_MODULE_ENABLED
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
-/** @defgroup SMARTCARD SMARTCARD HAL module driver
+/** @defgroup SMARTCARD SMARTCARD
* @brief HAL SMARTCARD module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
- * @{
- */
-#define TEACK_REACK_TIMEOUT 1000
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+ * @{
+ */
+#define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */
#define SMARTCARD_TXDMA_TIMEOUTVALUE 22000
#define SMARTCARD_TIMEOUT_VALUE 22000
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))
-#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
/**
* @}
*/
-
-/* Private macro -------------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions
@@ -172,88 +175,88 @@
*/
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
* @{
*/
-/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
-===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USART
- in Smartcard mode.
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx
+ associated to the SmartCard.
[..]
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO 7816-3 standard.
[..]
The USART can provide a clock to the smartcard through the SCLK output.
- In smartcard mode, SCLK is not associated to the communication but is simply derived
+ In smartcard mode, SCLK is not associated to the communication but is simply derived
from the internal peripheral input clock through a 5-bit prescaler.
[..]
- (+) For the Smartcard mode only these parameters can be configured:
- (++) Baud Rate
- (++) Parity: parity should be enabled,
- Frame Length is fixed to 8 bits plus parity:
- the USART frame format is given in the following table:
- +---------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|-----------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +---------------------------------------------------------------+
- or
- +---------------------------------------------------------------+
- | M1M0 bits | PCE bit | USART frame |
- |-----------------------|---------------------------------------|
- | 01 | 1 | | SB | 8 bit data | PB | STB | |
- +---------------------------------------------------------------+
+ (+) These parameters can be configured:
+ (++) Baud Rate
+ (++) Parity: parity should be enabled,
+ Frame Length is fixed to 8 bits plus parity:
+ the SMARTCARD frame format is given in the following table:
+ (+++) +---------------------------------------------------------------+
+ (+++) | M bit | PCE bit | SMARTCARD frame |
+ (+++) |---------------------|-----------------------------------------|
+ (+++) | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) +---------------------------------------------------------------+
+ (+++) or
+ (+++) +---------------------------------------------------------------+
+ (+++) | M1M0 bits | PCE bit | SMARTCARD frame |
+ (+++) |-----------------------|---------------------------------------|
+ (+++) | 01 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) +---------------------------------------------------------------+
- (++) Receiver/transmitter modes
- (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
- (++) Prescaler value
- (++) Guard bit time
- (++) NACK enabling or disabling on transmission error
+ (++) Receiver/transmitter modes
+ (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
+ (++) Prescaler value
+ (++) Guard bit time
+ (++) NACK enabling or disabling on transmission error
- (+) The following advanced features can be configured as well:
- (++) TX and/or RX pin level inversion
- (++) data logical level inversion
- (++) RX and TX pins swap
- (++) RX overrun detection disabling
- (++) DMA disabling on RX error
- (++) MSB first on communication line
- (++) Time out enabling (and if activated, timeout value)
- (++) Block length
- (++) Auto-retry counter
-
- [..]
- The HAL_SMARTCARD_Init() API follow respectively the USART (a)synchronous configuration procedures
- (details for the procedures are available in reference manual).
+ (+) The following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) Time out enabling (and if activated, timeout value)
+ (++) Block length
+ (++) Auto-retry counter
+ [..]
+ The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
+ (details for the procedures are available in reference manual).
@endverbatim
* @{
*/
/**
- * @brief Initializes the SMARTCARD mode according to the specified
- * parameters in the SMARTCARD_InitTypeDef and creates the associated handle .
- * @param hsmartcard: SMARTCARD handle
+ * @brief Initialize the SMARTCARD mode according to the specified
+ * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
@@ -263,52 +266,56 @@
{
return HAL_ERROR;
}
-
+
/* Check the USART associated to the SmartCard */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
-
+
if(hsmartcard->State == HAL_SMARTCARD_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ hsmartcard->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK */
HAL_SMARTCARD_MspInit(hsmartcard);
}
-
+
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_SMARTCARD_DISABLE(hsmartcard);
-
+
/* Set the SMARTCARD Communication parameters */
if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
{
return HAL_ERROR;
- }
-
+ }
+
if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
{
SMARTCARD_AdvFeatureConfig(hsmartcard);
}
-
- /* In SmartCard mode, the following bits must be kept cleared:
+
+ /* In SmartCard mode, the following bits must be kept cleared:
- LINEN in the USART_CR2 register,
- HDSEL and IREN bits in the USART_CR3 register.*/
- hsmartcard->Instance->CR2 &= ~(USART_CR2_LINEN);
- hsmartcard->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN);
-
- /* set the USART in SMARTCARD mode */
- hsmartcard->Instance->CR3 |= USART_CR3_SCEN;
-
+ hsmartcard->Instance->CR2 &= ~(USART_CR2_LINEN);
+ hsmartcard->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN);
+
+ /* set the USART in SMARTCARD mode */
+ hsmartcard->Instance->CR3 |= USART_CR3_SCEN;
+
/* Enable the Peripheral */
__HAL_SMARTCARD_ENABLE(hsmartcard);
-
+
/* TEACK and/or REACK to check before moving hsmartcard->State to Ready */
return (SMARTCARD_CheckIdleState(hsmartcard));
}
/**
- * @brief DeInitializes the SMARTCARD peripheral
- * @param hsmartcard: SMARTCARD handle
+ * @brief DeInitialize the SMARTCARD peripheral.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
@@ -318,135 +325,140 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_SMARTCARD_DISABLE(hsmartcard);
-
+
hsmartcard->Instance->CR1 = 0x0;
hsmartcard->Instance->CR2 = 0x0;
hsmartcard->Instance->CR3 = 0x0;
hsmartcard->Instance->RTOR = 0x0;
hsmartcard->Instance->GTPR = 0x0;
-
+
/* DeInit the low level hardware */
HAL_SMARTCARD_MspDeInit(hsmartcard);
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsmartcard->State = HAL_SMARTCARD_STATE_RESET;
-
+
/* Process Unlock */
__HAL_UNLOCK(hsmartcard);
-
+
return HAL_OK;
}
/**
- * @brief SMARTCARD MSP Init
- * @param hsmartcard: SMARTCARD handle
+ * @brief Initialize the SMARTCARD MSP.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARD_MspInit can be implemented in the user file
- */
+ */
}
/**
- * @brief SMARTCARD MSP DeInit
- * @param hsmartcard: SMARTCARD handle
+ * @brief DeInitialize the SMARTCARD MSP.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMARTCARD_MspDeInit can be implemented in the user file
- */
+ */
}
/**
* @}
*/
-/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
- * @brief SMARTCARD Transmit and Receive functions
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
*
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
[..]
This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
[..]
- Smartcard is a single wire half duplex communication protocol.
+ Smartcard is a single wire half duplex communication protocol.
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO 7816-3 standard. The USART should be configured as:
- - 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
- - 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+ (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These API s return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
- The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected
+ [..]
+ (+) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, the relevant API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
+ error is detected.
- (#) Blocking mode API s are :
+ (+) Blocking mode APIs are :
(++) HAL_SMARTCARD_Transmit()
- (++) HAL_SMARTCARD_Receive()
-
- (#) Non Blocking mode API s with Interrupt are :
+ (++) HAL_SMARTCARD_Receive()
+
+ (+) Non Blocking mode APIs with Interrupt are :
(++) HAL_SMARTCARD_Transmit_IT()
(++) HAL_SMARTCARD_Receive_IT()
(++) HAL_SMARTCARD_IRQHandler()
- (#) Non Blocking mode functions with DMA are :
+ (+) Non Blocking mode functions with DMA are :
(++) HAL_SMARTCARD_Transmit_DMA()
(++) HAL_SMARTCARD_Receive_DMA()
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SMARTCARD_TxCpltCallback()
(++) HAL_SMARTCARD_RxCpltCallback()
(++) HAL_SMARTCARD_ErrorCallback()
-
+
@endverbatim
* @{
*/
/**
- * @brief Send an amount of data in blocking mode
- * @param hsmartcard: SMARTCARD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout : Timeout duration
+ * @brief Send an amount of data in blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
+ * @param Timeout : Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hsmartcard);
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Check if a non-blocking receive process is ongoing or not */
- if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
}
@@ -454,24 +466,24 @@
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
-
+
hsmartcard->TxXferSize = Size;
hsmartcard->TxXferCount = Size;
while(hsmartcard->TxXferCount > 0)
{
- hsmartcard->TxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
+ hsmartcard->TxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
- }
- hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ }
+ hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF);
}
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
- {
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
}
/* Check if a non-blocking receive Process is ongoing or not */
- if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
}
@@ -479,216 +491,111 @@
{
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Receive an amount of data in blocking mode
- * @param hsmartcard: SMARTCARD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout : Timeout duration
+ * @brief Receive an amount of data in blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @param Timeout : Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
+{
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
- {
- if((pData == NULL) || (Size == 0))
+ {
+ if((pData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hsmartcard);
-
+
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Check if a non-blocking transmit process is ongoing or not */
- if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
}
else
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
- }
-
- hsmartcard->RxXferSize = Size;
+ }
+
+ hsmartcard->RxXferSize = Size;
hsmartcard->RxXferCount = Size;
/* Check the remain data to be received */
while(hsmartcard->RxXferCount > 0)
{
- hsmartcard->RxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
+ hsmartcard->RxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
- }
- *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
+ }
+ *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
}
-
+
/* Check if a non-blocking transmit Process is ongoing or not */
- if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
else
{
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
- }
-
+ }
+
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Send an amount of data in interrupt mode
- * @param hsmartcard: SMARTCARD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @brief Send an amount of data in interrupt mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
{
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hsmartcard);
-
+
hsmartcard->pTxBuffPtr = pData;
hsmartcard->TxXferSize = Size;
hsmartcard->TxXferCount = Size;
-
+
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Check if a receive process is ongoing or not */
- if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
- {
- hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
- }
- else
- {
- hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
- }
-
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive an amount of data in interrupt mode
- * @param hsmartcard: SMARTCARD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
- if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->pRxBuffPtr = pData;
- hsmartcard->RxXferSize = Size;
- hsmartcard->RxXferCount = Size;
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- /* Check if a transmit process is ongoing or not */
- if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
- {
- hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
- }
- else
- {
- hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
- }
-
- /* Enable the SMARTCARD Parity Error Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_PE);
-
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- /* Enable the SMARTCARD Data Register not empty Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in DMA mode
- * @param hsmartcard: SMARTCARD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
-{
- uint32_t *tmp;
-
- if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
- {
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->pTxBuffPtr = pData;
- hsmartcard->TxXferSize = Size;
- hsmartcard->TxXferCount = Size;
-
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- /* Check if a receive process is ongoing or not */
- if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
}
@@ -696,72 +603,185 @@
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
-
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a transmit process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_PE);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Data Register not empty Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ uint32_t *tmp;
+
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX))
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Check if a receive process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+
/* Set the SMARTCARD DMA transfer complete callback */
hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
-
+
/* Set the SMARTCARD error callback */
hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
/* Enable the SMARTCARD transmit DMA channel */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hsmartcard->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsmartcard->Instance->TDR, Size);
-
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_TCF);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the SMARTCARD associated USART CR3 register */
hsmartcard->Instance->CR3 |= USART_CR3_DMAT;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Receive an amount of data in DMA mode
- * @param hsmartcard: SMARTCARD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
- * the received data contain the parity bit (MSB position)
+ * @brief Receive an amount of data in DMA mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
+ * the received data contain the parity bit (MSB position).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
-
+
if ((hsmartcard->State == HAL_SMARTCARD_STATE_READY) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX))
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hsmartcard);
-
+
hsmartcard->pRxBuffPtr = pData;
hsmartcard->RxXferSize = Size;
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- /* Check if a transmit rocess is ongoing or not */
- if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
+ /* Check if a transmit process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
}
else
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
- }
-
+ }
+
/* Set the SMARTCARD DMA transfer complete callback */
hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
-
+
/* Set the SMARTCARD DMA error callback */
hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
@@ -769,69 +789,70 @@
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, *(uint32_t*)tmp, Size);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the SMARTCARD associated USART CR3 register */
hsmartcard->Instance->CR3 |= USART_CR3_DMAR;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
-
+
/**
- * @brief SMARTCARD interrupt requests handling.
- * @param hsmartcard: SMARTCARD handle
+ * @brief Handle SMARTCARD interrupt requests.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* SMARTCARD parity error interrupt occurred -------------------------------------*/
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_PE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_PE) != RESET))
- {
+ {
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
/* Set the SMARTCARD state ready to be able to start again the process */
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
-
- /* SMARTCARD frame error interrupt occured --------------------------------------*/
+
+ /* SMARTCARD frame error interrupt occurred --------------------------------------*/
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
- {
+ {
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
/* Set the SMARTCARD state ready to be able to start again the process */
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
-
- /* SMARTCARD noise error interrupt occured --------------------------------------*/
+
+ /* SMARTCARD noise error interrupt occurred --------------------------------------*/
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
- {
+ {
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
/* Set the SMARTCARD state ready to be able to start again the process */
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
-
- /* SMARTCARD Over-Run interrupt occured -----------------------------------------*/
+
+ /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
- {
+ {
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
/* Set the SMARTCARD state ready to be able to start again the process */
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
-
- /* SMARTCARD receiver timeout interrupt occured -----------------------------------------*/
+
+ /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RTO) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RTO) != RESET))
- {
+ {
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
/* Set the SMARTCARD state ready to be able to start again the process */
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
@@ -840,105 +861,108 @@
if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
{
HAL_SMARTCARD_ErrorCallback(hsmartcard);
- }
-
+ }
+
/* SMARTCARD in mode Receiver ---------------------------------------------------*/
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RXNE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RXNE) != RESET))
- {
+ {
SMARTCARD_Receive_IT(hsmartcard);
/* Clear RXNE interrupt flag */
__HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
}
-
+
/* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_EOB) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_EOB) != RESET))
- {
+ {
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
- __HAL_UNLOCK(hsmartcard);
+ __HAL_UNLOCK(hsmartcard);
HAL_SMARTCARD_RxCpltCallback(hsmartcard);
/* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
* to be available during HAL_SMARTCARD_RxCpltCallback() processing */
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
- }
+ }
/* SMARTCARD in mode Transmitter ------------------------------------------------*/
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TXE) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TXE) != RESET))
{
SMARTCARD_Transmit_IT(hsmartcard);
- }
-
+ }
+
/* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET))
{
SMARTCARD_EndTransmit_IT(hsmartcard);
- }
-}
+ }
+}
/**
- * @brief Tx Transfer completed callbacks
- * @param hsmartcard: SMARTCARD handle
+ * @brief Tx Transfer completed callback.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file
- */
+ the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief Rx Transfer completed callbacks
- * @param hsmartcard: SMARTCARD handle
+ * @brief Rx Transfer completed callback.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file
+ the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief SMARTCARD error callbacks
- * @param hsmartcard: SMARTCARD handle
+ * @brief SMARTCARD error callback.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_ErrorCallback can be implemented in the user file
- */
+ the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
+ */
}
/**
* @}
*/
-
-/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief SMARTCARD State and Errors functions
+
+/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SMARTCARD State and Errors functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral State and Errors functions #####
- ==============================================================================
- [..]
+ ==============================================================================
+ [..]
This subsection provides a set of functions allowing to return the State of SmartCard
- communication process and also return Peripheral Errors occurred during communication process
- (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SMARTCARD peripheral
- (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during
- communication.
-
- (+) SMARTCARD_SetConfig() API configures the SMARTCARD peripheral
- (+) SMARTCARD_AdvFeatureConfig() API optionally configures the SMARTCARD advanced features
- (+) SMARTCARD_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+ handle and also return Peripheral Errors occurred during communication process
+ (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
+ of the SMARTCARD peripheral.
+ (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
+ communication.
+
@endverbatim
* @{
*/
+
/**
- * @brief return the SMARTCARD state
- * @param hsmartcard: SMARTCARD handle
- * @retval HAL state
+ * @brief Return the SMARTCARD handle state.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval SMARTCARD handle state
*/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
{
@@ -946,10 +970,10 @@
}
/**
-* @brief Return the SMARTCARD error code
-* @param hsmartcard : pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD.
-* @retval SMARTCARD Error Code
+ * @brief Return the SMARTCARD handle error code.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+* @retval SMARTCARD handle Error Code
*/
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
{
@@ -959,48 +983,164 @@
/**
* @}
*/
-
+
/**
* @}
- */
+ */
/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
* @{
*/
-
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+ {
+
+ if(hsmartcard->TxXferCount == 0)
+ {
+ /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF);
+ hsmartcard->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
/**
- * @brief This function handles SMARTCARD Communication Timeout.
- * @param hsmartcard: SMARTCARD handle
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+
+ /* Check if a receive process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
+ }
+ else
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+ {
+
+ *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+
+ if(--hsmartcard->RxXferCount == 0)
+ {
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
+
+ /* Check if a transmit Process is ongoing or not */
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ {
+ hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
+
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+
+ hsmartcard->State = HAL_SMARTCARD_STATE_READY;
+ }
+
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Handle SMARTCARD Communication Timeout.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @param Flag: specifies the SMARTCARD flag to check.
* @param Status: The new Flag status (SET or RESET).
- * @param Timeout: Timeout duration
+ * @param Timeout: Timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
-
+
/* Wait until flag is set */
if(Status == RESET)
- {
+ {
while(__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) == RESET)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
-
+
hsmartcard->State= HAL_SMARTCARD_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
-
+
return HAL_TIMEOUT;
}
}
@@ -1012,64 +1152,64 @@
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
__HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
-
+
hsmartcard->State= HAL_SMARTCARD_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
-
+
return HAL_TIMEOUT;
}
}
}
}
- return HAL_OK;
+ return HAL_OK;
}
/**
- * @brief DMA SMARTCARD transmit process complete callback.
+ * @brief DMA SMARTCARD transmit process complete callback.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsmartcard->TxXferCount = 0;
-
+
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the SMARTCARD associated USART CR3 register */
hsmartcard->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT);
-
- /* Enable the SMARTCARD Transmit Complete Interrupt */
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
__HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
}
/**
- * @brief DMA SMARTCARD receive process complete callback.
+ * @brief DMA SMARTCARD receive process complete callback.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsmartcard->RxXferCount = 0;
-
- /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the SMARTCARD associated USART CR3 register */
hsmartcard->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR);
-
+
/* Check if a transmit Process is ongoing or not */
- if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
+ if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
{
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
}
@@ -1077,17 +1217,17 @@
{
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
}
-
+
HAL_SMARTCARD_RxCpltCallback(hsmartcard);
}
/**
- * @brief DMA SMARTCARD communication error callback.
+ * @brief DMA SMARTCARD communication error callback.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hsmartcard->RxXferCount = 0;
@@ -1098,159 +1238,46 @@
}
/**
- * @brief Send an amount of data in non blocking mode
- * @param hsmartcard: SMARTCARD handle.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
- {
-
- if(hsmartcard->TxXferCount == 0)
- {
- /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
-
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
-
- return HAL_OK;
- }
- else
- {
- hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF);
- hsmartcard->TxXferCount--;
-
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-/**
- * @brief Wraps up transmission in non blocking mode.
- * @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
-
- /* Check if a receive process is ongoing or not */
- if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
- {
- hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
- }
- else
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
-
- hsmartcard->State = HAL_SMARTCARD_STATE_READY;
- }
-
- HAL_SMARTCARD_TxCpltCallback(hsmartcard);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Receive an amount of data in non blocking mode
- * @param hsmartcard: SMARTCARD handle.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- if ((hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_RX) || (hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX))
- {
-
- *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
-
- if(--hsmartcard->RxXferCount == 0)
- {
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
-
- /* Check if a transmit Process is ongoing or not */
- if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
- {
- hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_TX;
- }
- else
- {
- /* Disable the SMARTCARD Parity Error Interrupt */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
-
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
-
- hsmartcard->State = HAL_SMARTCARD_STATE_READY;
- }
-
- HAL_SMARTCARD_RxCpltCallback(hsmartcard);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Configure the SMARTCARD associated USART peripheral
- * @param hsmartcard: SMARTCARD handle
+ * @brief Configure the SMARTCARD associated USART peripheral.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
{
uint32_t tmpreg = 0x00000000;
SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
- HAL_StatusTypeDef ret = HAL_OK;
-
- /* Check the parameters */
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
- assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
- assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
- assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
+ assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
+ assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
+ assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
- assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
- assert_param(IS_SMARTCARD_ONEBIT_SAMPLING(hsmartcard->Init.OneBitSampling));
+ assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
+ assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
- assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
+ assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
/*-------------------------- USART CR1 Configuration -----------------------*/
/* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
* Oversampling is forced to 16 (OVER8 = 0).
- * Configure the Parity and Mode:
+ * Configure the Parity and Mode:
* set PS bit according to hsmartcard->Init.Parity value
* set TE and RE bits according to hsmartcard->Init.Mode value */
tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
- /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor
- the bidirectional line to detect a NACK signal in case of parity error.
+ /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
Therefore, the receiver block must be enabled as well (RE bit must be set). */
if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLED))
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
- tmpreg |= USART_CR1_RE;
+ tmpreg |= USART_CR1_RE;
}
tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
@@ -1259,157 +1286,170 @@
/* Stop bits are forced to 1.5 (STOP = 11) */
tmpreg = hsmartcard->Init.StopBits;
/* Synchronous mode is activated by default */
- tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
+ tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
- MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* Configure
- * - one-bit sampling method versus three samples' majority rule
- * according to hsmartcard->Init.OneBitSampling
- * - NACK transmission in case of parity error according
- * to hsmartcard->Init.NACKEnable
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - one-bit sampling method versus three samples' majority rule
+ * according to hsmartcard->Init.OneBitSampling
+ * - NACK transmission in case of parity error according
+ * to hsmartcard->Init.NACKEnable
* - autoretry counter according to hsmartcard->Init.AutoRetryCount */
tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
-
+
/*-------------------------- USART GTPR Configuration ----------------------*/
tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
- MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
-
- /*-------------------------- USART RTOR Configuration ----------------------*/
+ MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
+
+ /*-------------------------- USART RTOR Configuration ----------------------*/
tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
- if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLED)
+ if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
{
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
}
MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- __HAL_SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
switch (clocksource)
{
- case SMARTCARD_CLOCKSOURCE_PCLK1:
+ case SMARTCARD_CLOCKSOURCE_PCLK1:
hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / hsmartcard->Init.BaudRate);
break;
- case SMARTCARD_CLOCKSOURCE_HSI:
- hsmartcard->Instance->BRR = (uint16_t)(HSI_VALUE / hsmartcard->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_SYSCLK:
+ case SMARTCARD_CLOCKSOURCE_HSI:
+ hsmartcard->Instance->BRR = (uint16_t)(HSI_VALUE / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_SYSCLK:
hsmartcard->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / hsmartcard->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_LSE:
- hsmartcard->Instance->BRR = (uint16_t)(LSE_VALUE / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_LSE:
+ hsmartcard->Instance->BRR = (uint16_t)(LSE_VALUE / hsmartcard->Init.BaudRate);
break;
- case SMARTCARD_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
+ case SMARTCARD_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
}
-
- return ret;
-}
-
-/**
- * @brief Check the SMARTCARD Idle State
- * @param hsmartcard: SMARTCARD handle
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-
- /* Initialize the SMARTCARD ErrorCode */
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- /* Check if the Transmitter is enabled */
- if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- {
- /* Wait until TEACK flag is set */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- }
- /* Check if the Receiver is enabled */
- if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Initialize the SMARTCARD state*/
- hsmartcard->State= HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
+ return ret;
}
-
+
+
/**
- * @brief Configure the SMARTCARD associated USART peripheral advanced feautures
- * @param hsmartcard: SMARTCARD handle
+ * @brief Configure the SMARTCARD associated USART peripheral advanced features.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Check whether the set of advanced features to configure is properly set */
+{
+ /* Check whether the set of advanced features to configure is properly set */
assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
-
+
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
{
assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
}
-
+
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
{
assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
}
-
+
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
{
assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
}
-
+
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
{
assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
}
-
+
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
{
- assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
+ assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
}
-
+
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
{
- assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
+ assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
}
-
- /* if required, configure MSB first on communication line */
+
+ /* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
{
- assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
+ assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
- }
+ }
+
+}
+
+/**
+ * @brief Check the SMARTCARD Idle State.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+ /* Initialize the SMARTCARD ErrorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
+ Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
+ */
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+ if (IS_UART_WAKEUP_INSTANCE(hsmartcard->Instance))
+ {
+ /* Check if the Transmitter is enabled */
+ if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the Receiver is enabled */
+ if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+
+ /* Initialize the SMARTCARD state*/
+ hsmartcard->State= HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
}
/**
@@ -1424,7 +1464,7 @@
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -32,7 +32,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -54,23 +54,22 @@
/** @addtogroup SMARTCARD
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
* @{
- */
-
+ */
-/**
- * @brief SMARTCARD Init Structure definition
- */
+/**
+ * @brief SMARTCARD Init Structure definition
+ */
typedef struct
{
uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
The baud rate register is computed using the following formula:
Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
-
+
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
@@ -82,7 +81,7 @@
@note The parity is enabled by default (PCE is forced to 1).
Since the WordLength is forced to 8 bits + parity, M is
forced to 1 and the parity bit is the 9th bit. */
-
+
uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref SMARTCARD_Mode */
@@ -95,85 +94,85 @@
uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref SMARTCARD_Last_Bit */
-
+
uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
Selecting the single sample method increases the receiver tolerance to clock
deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler */
-
+
uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time */
-
+
uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
in case of parity error.
- This parameter can be a value of @ref SMARTCARD_NACK_Enable */
-
- uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
+ This parameter can be a value of @ref SMARTCARD_NACK_Enable */
+
+ uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
-
- uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
- it is used to implement the Character Wait Time (CWT) and
- Block Wait Time (BWT). It is coded over 24 bits. */
-
+
+ uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
+ it is used to implement the Character Wait Time (CWT) and
+ Block Wait Time (BWT). It is coded over 24 bits. */
+
uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
- This parameter can be any value from 0x0 to 0xFF */
-
+ This parameter can be any value from 0x0 to 0xFF */
+
uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
- receive and transmit mode). When set to 0, retransmission is
+ receive and transmit mode). When set to 0, retransmission is
disabled. Otherwise, its maximum value is 7 (before signalling
- an error) */
-
+ an error) */
+
}SMARTCARD_InitTypeDef;
-/**
- * @brief SMARTCARD advanced features initalization structure definition
+/**
+ * @brief SMARTCARD advanced features initalization structure definition
*/
-typedef struct
+typedef struct
{
uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
- advanced features may be initialized at the same time. This parameter
- can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */
+ advanced features may be initialized at the same time. This parameter
+ can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
This parameter can be a value of @ref SMARTCARD_Tx_Inv */
-
+
uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
This parameter can be a value of @ref SMARTCARD_Rx_Inv */
uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
vs negative/inverted logic).
This parameter can be a value of @ref SMARTCARD_Data_Inv */
-
- uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
-
- uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
-
- uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
+
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
-
- uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
This parameter can be a value of @ref SMARTCARD_MSB_First */
}SMARTCARD_AdvFeatureInitTypeDef;
-/**
- * @brief HAL State structures definition
- */
+/**
+ * @brief HAL State structures definition
+ */
typedef enum
{
HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
}HAL_SMARTCARD_StateTypeDef;
-/**
- * @brief SMARTCARD clock sources
+/**
+ * @brief SMARTCARD clock sources
*/
typedef enum
{
@@ -181,43 +180,43 @@
SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
SMARTCARD_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
- SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
+ SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
}SMARTCARD_ClockSourceTypeDef;
-/**
- * @brief SMARTCARD handle Structure definition
- */
+/**
+ * @brief SMARTCARD handle Structure definition
+ */
typedef struct
{
USART_TypeDef *Instance; /*!< USART registers base address */
-
+
SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
-
+
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
-
+
uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
-
+
uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
-
+
uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
-
+
uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
-
+
uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
-
+
uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
-
+
DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
-
+
DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
-
+
HAL_LockTypeDef Lock; /*!< Locking object */
-
- HAL_SMARTCARD_StateTypeDef State; /*!< SmartCard communication state */
-
+
+ __IO HAL_SMARTCARD_StateTypeDef State; /*!< SmartCard communication state */
+
__IO uint32_t ErrorCode; /*!< SmartCard Error code
This parameter can be a value of @ref SMARTCARD_Error */
-
+
}SMARTCARD_HandleTypeDef;
/**
@@ -225,11 +224,11 @@
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
+/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants
* @{
*/
-/** @defgroup SMARTCARD_Error SMARTCARD Error
+/** @defgroup SMARTCARD_Error SMARTCARD Error
* @{
*/
#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
@@ -243,73 +242,64 @@
* @}
*/
-/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
-#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
-#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
+#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< SMARTCARD frame length */
/**
* @}
*/
-
-/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Stop Bits
+
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Stop Bits
* @{
*/
-#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP))
-#define IS_SMARTCARD_STOPBITS(STOPBITS) ((STOPBITS) == SMARTCARD_STOPBITS_1_5)
+#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */
/**
* @}
- */
+ */
-/** @defgroup SMARTCARD_Parity SMARTCARD Parity
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
* @{
- */
-#define SMARTCARD_PARITY_EVEN ((uint16_t)USART_CR1_PCE)
-#define SMARTCARD_PARITY_ODD ((uint16_t)(USART_CR1_PCE | USART_CR1_PS))
-#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
- ((PARITY) == SMARTCARD_PARITY_ODD))
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
- * @{
- */
-#define SMARTCARD_MODE_RX ((uint16_t)USART_CR1_RE)
-#define SMARTCARD_MODE_TX ((uint16_t)USART_CR1_TE)
-#define SMARTCARD_MODE_TX_RX ((uint16_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+ */
+#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< SMARTCARD frame even parity */
+#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity */
/**
* @}
*/
-/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
+/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
* @{
*/
-#define SMARTCARD_POLARITY_LOW ((uint16_t)0x0000)
-#define SMARTCARD_POLARITY_HIGH ((uint16_t)USART_CR2_CPOL)
-#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
+#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) /*!< SMARTCARD RX mode */
+#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) /*!< SMARTCARD TX mode */
+#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< SMARTCARD RX and TX mode */
/**
* @}
- */
+ */
+
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
+ * @{
+ */
+#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000) /*!< SMARTCARD frame low polarity */
+#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< SMARTCARD frame high polarity */
+/**
+ * @}
+ */
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
* @{
*/
-#define SMARTCARD_PHASE_1EDGE ((uint16_t)0x0000)
-#define SMARTCARD_PHASE_2EDGE ((uint16_t)USART_CR2_CPHA)
-#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
+#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000) /*!< SMARTCARD frame phase on first clock transition */
+#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< SMARTCARD frame phase on second clock transition */
/**
* @}
*/
-/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
* @{
*/
-#define SMARTCARD_LASTBIT_DISABLED ((uint16_t)0x0000)
-#define SMARTCARD_LASTBIT_ENABLED ((uint16_t)USART_CR2_LBCL)
-#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLED) || \
- ((LASTBIT) == SMARTCARD_LASTBIT_ENABLED))
+#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
+#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */
/**
* @}
*/
@@ -317,56 +307,42 @@
/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
* @{
*/
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED ((uint16_t)0x0000)
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED ((uint16_t)USART_CR3_ONEBIT)
-#define IS_SMARTCARD_ONEBIT_SAMPLING(ONEBIT) (((ONEBIT) == SMARTCARD_ONEBIT_SAMPLING_DISABLED) || \
- ((ONEBIT) == SMARTCARD_ONEBIT_SAMPLING_ENABLED))
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD frame one-bit sample disabled */
+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< SMARTCARD frame one-bit sample enabled */
/**
* @}
- */
+ */
-/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
+/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
* @{
*/
-#define SMARTCARD_NACK_ENABLED ((uint16_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLED ((uint16_t)0x0000)
-#define IS_SMARTCARD_NACK(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \
- ((NACK) == SMARTCARD_NACK_DISABLED))
+#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) /*!< SMARTCARD NACK transmission disabled */
+#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD NACK transmission enabled */
/**
* @}
*/
-/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
+/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
* @{
*/
-#define SMARTCARD_TIMEOUT_DISABLED ((uint32_t)0x00000000)
-#define SMARTCARD_TIMEOUT_ENABLED ((uint32_t)USART_CR2_RTOEN)
-#define IS_SMARTCARD_TIMEOUT(TIMEOUT) (((TIMEOUT) == SMARTCARD_TIMEOUT_DISABLED) || \
- ((TIMEOUT) == SMARTCARD_TIMEOUT_ENABLED))
+#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000) /*!< SMARTCARD receiver timeout disabled */
+#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< SMARTCARD receiver timeout enabled */
/**
* @}
*/
-
+
/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
* @{
*/
-#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
-#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
-#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
-#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
-#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
-#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
-#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)
-#define IS_SMARTCARD_ADVFEATURE_INIT(INIT) ((INIT) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
- SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
- SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
- SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
- SMARTCARD_ADVFEATURE_SWAP_INIT | \
- SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
- SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
- SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */
+#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */
/**
* @}
*/
@@ -374,10 +350,8 @@
/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
* @{
*/
-#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
-#define IS_SMARTCARD_ADVFEATURE_TXINV(TXINV) (((TXINV) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
- ((TXINV) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /*!< TX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
/**
* @}
*/
@@ -385,86 +359,75 @@
/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
* @{
*/
-#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
-#define IS_SMARTCARD_ADVFEATURE_RXINV(RXINV) (((RXINV) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
- ((RXINV) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /*!< RX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /*!< Binary data inversion disable */
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /*!< TX/RX pins swap disable */
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /*!< RX overrun enable */
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
/**
* @}
*/
-/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
+/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
* @{
*/
-#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
-#define IS_SMARTCARD_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
- ((DATAINV) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
- * @{
- */
-#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
-#define IS_SMARTCARD_ADVFEATURE_SWAP(SWAP) (((SWAP) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
- ((SWAP) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /*!< DMA enable on Reception Error */
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
/**
* @}
- */
-
-/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
- * @{
*/
-#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
-#define IS_SMARTCARD_OVERRUN(OVERRUN) (((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
- ((OVERRUN) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
- * @{
- */
-#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
-#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
- ((DMA) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
-/**
- * @}
- */
/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first
* @{
*/
-#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
-#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
- ((MSBFIRST) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /*!< Most significant bit sent/received first disable */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
/**
* @}
- */
+ */
-/** @defgroup SMARTCARD_Flags SMARTCARD Flags
+/** @defgroup SMARTCARD_Flags SMARTCARD Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000)
-#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000)
-#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000)
-#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000)
-#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800)
-#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
-#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
-#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
-#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008)
-#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004)
-#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002)
-#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001)
+#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
+#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
+#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
+#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
+#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
+#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */
+#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
+#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */
+#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
+#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
+#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
+#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
+#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
/**
* @}
*/
@@ -479,34 +442,67 @@
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
-
-#define SMARTCARD_IT_PE ((uint16_t)0x0028)
-#define SMARTCARD_IT_TXE ((uint16_t)0x0727)
-#define SMARTCARD_IT_TC ((uint16_t)0x0626)
-#define SMARTCARD_IT_RXNE ((uint16_t)0x0525)
-
-#define SMARTCARD_IT_ERR ((uint16_t)0x0060)
-#define SMARTCARD_IT_ORE ((uint16_t)0x0300)
-#define SMARTCARD_IT_NE ((uint16_t)0x0200)
-#define SMARTCARD_IT_FE ((uint16_t)0x0100)
-#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B)
-#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A)
+#define SMARTCARD_IT_PE ((uint16_t)0x0028) /*!< SMARTCARD parity error interruption */
+#define SMARTCARD_IT_TXE ((uint16_t)0x0727) /*!< SMARTCARD transmit data register empty interruption */
+#define SMARTCARD_IT_TC ((uint16_t)0x0626) /*!< SMARTCARD transmission complete interruption */
+#define SMARTCARD_IT_RXNE ((uint16_t)0x0525) /*!< SMARTCARD read data register not empty interruption */
+#define SMARTCARD_IT_IDLE ((uint16_t)0x0424) /*!< SMARTCARD idle line detection interruption */
+
+#define SMARTCARD_IT_ERR ((uint16_t)0x0060) /*!< SMARTCARD error interruption */
+#define SMARTCARD_IT_ORE ((uint16_t)0x0300) /*!< SMARTCARD overrun error interruption */
+#define SMARTCARD_IT_NE ((uint16_t)0x0200) /*!< SMARTCARD noise error interruption */
+#define SMARTCARD_IT_FE ((uint16_t)0x0100) /*!< SMARTCARD frame error interruption */
+
+#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B) /*!< SMARTCARD end of block interruption */
+#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A) /*!< SMARTCARD receiver timeout interruption */
/**
* @}
- */
-
+ */
/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
* @{
*/
-#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
-#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
-#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
+#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
+#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
+#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */
+#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
+#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
+#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
+#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
+#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
+ * @{
+ */
+#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) /*!< SMARTCARD auto retry counter LSB position in CR3 register */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
+ * @{
+ */
+#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) /*!< SMARTCARD guard time value LSB position in GTPR register */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
+ * @{
+ */
+#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) /*!< SMARTCARD block length LSB position in RTOR register */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
+ * @{
+ */
+#define SMARTCARD_IT_MASK ((uint16_t)0x001F) /*!< SMARTCARD interruptions flags mask */
/**
* @}
*/
@@ -516,151 +512,178 @@
*/
#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
-#define IS_SMARTCARD_REQUEST_PARAMETER(PARAM) (((PARAM) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
- ((PARAM) == SMARTCARD_TXDATA_FLUSH_REQUEST))
/**
* @}
*/
-
-
-/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
- * @{
- */
-#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17)
+
/**
* @}
*/
-
-/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
- * @{
- */
-#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8)
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
- * @{
- */
-#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24)
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flag mask
- * @{
- */
-#define SMARTCARD_IT_MASK ((uint16_t)0x001F)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
* @{
*/
-/** @brief Reset SMARTCARD handle state
+/** @brief Reset SMARTCARD handle state.
* @param __HANDLE__: SMARTCARD handle.
* @retval None
*/
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
-/** @brief Checks whether the specified Smartcard flag is set or not.
+/** @brief Flush the Smartcard Data registers.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
+ } while(0)
+
+/** @brief Clear the specified SMARTCARD pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg SMARTCARD_CLEAR_PEF: Parity error clear flag
+ * @arg SMARTCARD_CLEAR_FEF: Framing error clear flag
+ * @arg SMARTCARD_CLEAR_NEF: Noise detected clear flag
+ * @arg SMARTCARD_CLEAR_OREF: OverRun error clear flag
+ * @arg SMARTCARD_CLEAR_IDLEF: Idle line detected clear flag
+ * @arg SMARTCARD_CLEAR_TCF: Transmission complete clear flag
+ * @arg SMARTCARD_CLEAR_RTOF: Receiver timeout clear flag
+ * @arg SMARTCARD_CLEAR_EOBF: End of block clear flag
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the SMARTCARD PE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
+
+
+/** @brief Clear the SMARTCARD FE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
+
+/** @brief Clear the SMARTCARD NE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
+
+/** @brief Clear the SMARTCARD ORE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
+
+/** @brief Clear the SMARTCARD IDLE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
+
+/** @brief Check whether the specified Smartcard flag is set or not.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
- * @arg SMARTCARD_FLAG_REACK: Receive enable ackowledge flag
- * @arg SMARTCARD_FLAG_TEACK: Transmit enable ackowledge flag
+ * @arg SMARTCARD_FLAG_REACK: Receive enable acknowledge flag
+ * @arg SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag
* @arg SMARTCARD_FLAG_BUSY: Busy flag
- * @arg SMARTCARD_FLAG_EOBF: End of block flag
- * @arg SMARTCARD_FLAG_RTOF: Receiver timeout flag
+ * @arg SMARTCARD_FLAG_EOBF: End of block flag
+ * @arg SMARTCARD_FLAG_RTOF: Receiver timeout flag
* @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
- * @arg SMARTCARD_FLAG_TC: Transmission Complete flag
+ * @arg SMARTCARD_FLAG_TC: Transmission complete flag
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
- * @arg SMARTCARD_FLAG_ORE: OverRun Error flag
- * @arg SMARTCARD_FLAG_NE: Noise Error flag
- * @arg SMARTCARD_FLAG_FE: Framing Error flag
- * @arg SMARTCARD_FLAG_PE: Parity Error flag
+ * @arg SMARTCARD_FLAG_IDLE: Idle line detection flag
+ * @arg SMARTCARD_FLAG_ORE: Overrun error flag
+ * @arg SMARTCARD_FLAG_NE: Noise error flag
+ * @arg SMARTCARD_FLAG_FE: Framing error flag
+ * @arg SMARTCARD_FLAG_PE: Parity error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-/** @brief Enables the specified SmartCard interrupt.
+/** @brief Enable the specified SmartCard interrupt.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
- * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg SMARTCARD_IT_EOB: End of block interrupt
+ * @arg SMARTCARD_IT_RTO: Receive timeout interrupt
+ * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_PE: Parity error interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt(frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
-/** @brief Disables the specified SmartCard interrupt.
+/** @brief Disable the specified SmartCard interrupt.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
- * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg SMARTCARD_IT_EOB: End of block interrupt
+ * @arg SMARTCARD_IT_RTO: Receive timeout interrupt
+ * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_PE: Parity error interrupt
+ * @arg SMARTCARD_IT_ERR: Error interrupt(frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
-
-/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
+
+/** @brief Check whether the specified SmartCard interrupt has occurred or not.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __IT__: specifies the SMARTCARD interrupt to check.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
- * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_ORE: OverRun Error interrupt
- * @arg SMARTCARD_IT_NE: Noise Error interrupt
- * @arg SMARTCARD_IT_FE: Framing Error interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @arg SMARTCARD_IT_EOB: End of block interrupt
+ * @arg SMARTCARD_IT_RTO: Receive timeout interrupt
+ * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_ORE: Overrun error interrupt
+ * @arg SMARTCARD_IT_NE: Noise error interrupt
+ * @arg SMARTCARD_IT_FE: Framing error interrupt
+ * @arg SMARTCARD_IT_PE: Parity error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
-/** @brief Checks whether the specified SmartCard interrupt interrupt source is enabled.
+/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __IT__: specifies the SMARTCARD interrupt source to check.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOBF: End Of Block interrupt
- * @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_ORE: OverRun Error interrupt
- * @arg SMARTCARD_IT_NE: Noise Error interrupt
- * @arg SMARTCARD_IT_FE: Framing Error interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
+ * @arg SMARTCARD_IT_EOB: End of block interrupt
+ * @arg SMARTCARD_IT_RTO: Receive timeout interrupt
+ * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt
+ * @arg SMARTCARD_IT_TC: Transmission complete interrupt
+ * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt
+ * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
+ * @arg SMARTCARD_IT_ORE: Overrun error interrupt
+ * @arg SMARTCARD_IT_NE: Noise error interrupt
+ * @arg SMARTCARD_IT_FE: Framing error interrupt
+ * @arg SMARTCARD_IT_PE: Parity error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \
@@ -668,87 +691,261 @@
(__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
-/** @brief Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
+/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
- * @arg USART_CLEAR_PEF: Parity Error Clear Flag
- * @arg USART_CLEAR_FEF: Framing Error Clear Flag
- * @arg USART_CLEAR_NEF: Noise detected Clear Flag
- * @arg USART_CLEAR_OREF: OverRun Error Clear Flag
- * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
- * @arg USART_CLEAR_RTOF: Receiver Time Out Clear Flag
- * @arg USART_CLEAR_EOBF: End Of Block Clear Flag
+ * @arg SMARTCARD_CLEAR_PEF: Parity error clear flag
+ * @arg SMARTCARD_CLEAR_FEF: Framing error clear flag
+ * @arg SMARTCARD_CLEAR_NEF: Noise detected clear flag
+ * @arg SMARTCARD_CLEAR_OREF: OverRun error clear flag
+ * @arg SMARTCARD_CLEAR_IDLEF: Idle line detection clear flag
+ * @arg SMARTCARD_CLEAR_TCF: Transmission complete clear flag
+ * @arg SMARTCARD_CLEAR_RTOF: Receiver timeout clear flag
+ * @arg SMARTCARD_CLEAR_EOBF: End of block clear flag
* @retval None
*/
-#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific SMARTCARD request flag.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __REQ__: specifies the request flag to set
- * This parameter can be one of the following values:
- * @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request
- * @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ * This parameter can be one of the following values:
+ * @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive data flush Request
+ * @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request
*
* @retval None
- */
-#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+ */
+#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-/** @brief Enable the USART associated to the SMARTCARD Handle
+/** @brief Enable the SMARTCARD one bit sample method.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the SMARTCARD one bit sample method.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable the USART associated to the SMARTCARD Handle.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral
* @retval None
- */
+ */
#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable the USART associated to the SMARTCARD Handle
* @param __HANDLE__: specifies the SMARTCARD Handle.
* The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral
* @retval None
- */
+ */
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+/**
+ * @}
+ */
+
+/* Private macros -------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+ * @{
+ */
+
/** @brief Check the Baud rate range. The maximum Baud Rate is derived from the
* maximum clock on F0 (i.e. 48 MHz) divided by the oversampling used
- * on the SMARTCARD (i.e. 16)
+ * on the SMARTCARD (i.e. 16).
* @param __BAUDRATE__: Baud rate set by the configuration function.
- * @retval Test result (TRUE or FALSE)
- */
+ * @retval Test result (TRUE or FALSE)
+ */
#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
-/** @brief Check the block length range. The maximum SMARTCARD block length is 0xFF.
+/** @brief Check the block length range.
+ * @note The maximum SMARTCARD block length is 0xFF.
* @param __LENGTH__: block length.
- * @retval Test result (TRUE or FALSE)
+ * @retval Test result (TRUE or FALSE)
*/
#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
-/** @brief Check the receiver timeout value. The maximum SMARTCARD receiver timeout
- * value is 0xFFFFFF.
+/** @brief Check the receiver timeout value.
+ * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
* @param __TIMEOUTVALUE__: receiver timeout value.
- * @retval Test result (TRUE or FALSE)
+ * @retval Test result (TRUE or FALSE)
*/
#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
-/** @brief Check the SMARTCARD autoretry counter value. The maximum number of
- * retransmissions is 0x7.
- * @param __COUNT__: number of retransmissions
- * @retval Test result (TRUE or FALSE)
+/** @brief Check the SMARTCARD autoretry counter value.
+ * @note The maximum number of retransmissions is 0x7.
+ * @param __COUNT__: number of retransmissions.
+ * @retval Test result (TRUE or FALSE)
*/
#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
/**
+ * @brief Ensure that SMARTCARD frame length is valid.
+ * @param __LENGTH__: SMARTCARD frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
+
+/**
+ * @brief Ensure that SMARTCARD frame number of stop bits is valid.
+ * @param __STOPBITS__: SMARTCARD frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_SMARTCARD_STOPBITS(__STOPBITS__) ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)
+
+/**
+ * @brief Ensure that SMARTCARD frame parity is valid.
+ * @param __PARITY__: SMARTCARD frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
+ ((__PARITY__) == SMARTCARD_PARITY_ODD))
+
+/**
+ * @brief Ensure that SMARTCARD communication mode is valid.
+ * @param __MODE__: SMARTCARD communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))
+
+/**
+ * @brief Ensure that SMARTCARD frame polarity is valid.
+ * @param __CPOL__: SMARTCARD frame polarity.
+ * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+ */
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
+
+/**
+ * @brief Ensure that SMARTCARD frame phase is valid.
+ * @param __CPHA__: SMARTCARD frame phase.
+ * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+ */
+#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
+
+/**
+ * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
+ * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting.
+ * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+ */
+#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame sampling is valid.
+ * @param __ONEBIT__: SMARTCARD frame sampling.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD NACK transmission setting is valid.
+ * @param __NACK__: SMARTCARD NACK transmission setting.
+ * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
+ */
+#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
+ ((__NACK__) == SMARTCARD_NACK_DISABLE))
+
+/**
+ * @brief Ensure that SMARTCARD receiver timeout setting is valid.
+ * @param __TIMEOUT__: SMARTCARD receiver timeout setting.
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+ */
+#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD advanced features initialization is valid.
+ * @param __INIT__: SMARTCARD advanced features initialization.
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
+ SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
+ SMARTCARD_ADVFEATURE_SWAP_INIT | \
+ SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+ * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
+ * @param __TXINV__: SMARTCARD frame TX inversion setting.
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
+ ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
+ * @param __RXINV__: SMARTCARD frame RX inversion setting.
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
+ ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame data inversion setting is valid.
+ * @param __DATAINV__: SMARTCARD frame data inversion setting.
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
+ ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
+ * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting.
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
+ ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD frame overrun setting is valid.
+ * @param __OVERRUN__: SMARTCARD frame overrun setting.
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+ */
+#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+ * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
+ * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting.
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+ * @brief Ensure that SMARTCARD frame MSB first setting is valid.
+ * @param __MSBFIRST__: SMARTCARD frame MSB first setting.
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+ */
+#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+ * @brief Ensure that SMARTCARD request parameter is valid.
+ * @param __PARAM__: SMARTCARD request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
+
+/**
* @}
- */
+ */
/* Include SMARTCARD HAL Extended module */
-#include "stm32f0xx_hal_smartcard_ex.h"
+#include "stm32f0xx_hal_smartcard_ex.h"
-
/* Exported functions --------------------------------------------------------*/
-
/** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
* @{
*/
@@ -762,9 +959,10 @@
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+
/**
* @}
- */
+ */
/** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions
* @{
@@ -780,23 +978,25 @@
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+
/**
* @}
- */
+ */
/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
* @{
- */
+ */
/* Peripheral State and Error functions ***************************************/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+
/**
* @}
*/
-
+
/**
* @}
- */
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,26 +2,25 @@
******************************************************************************
* @file stm32f0xx_hal_smartcard_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief SMARTCARD HAL module driver.
*
- * This file provides extended firmware functions to manage the following
+ * This file provides extended firmware functions to manage the following
* functionalities of the SmartCard.
* + Initialization and de-initialization function
* + Peripheral Control function
*
- *
- @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The Extended SMARTCARD HAL driver can be used as follows:
+ *
+ @verbatim
+ =============================================================================
+ ##### SMARTCARD peripheral extended features #####
+ =============================================================================
+ [..]
+ The Extended SMARTCARD HAL driver can be used as follows:
-
- (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
- then if required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut,
+ (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
+ then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
auto-retry counter,...) in the hsmartcard AdvancedInit structure.
@@ -30,7 +29,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -54,7 +53,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -62,50 +61,51 @@
#ifdef HAL_SMARTCARD_MODULE_ENABLED
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
-/** @defgroup SMARTCARDEx SMARTCARD Extended HAL module driver
+/** @defgroup SMARTCARDEx SMARTCARDEx
* @brief SMARTCARD Extended HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions
* @{
*/
/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
* @brief Extended control functions
*
-@verbatim
- ===============================================================================
+@verbatim
+ ===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the SMARTCARD.
- (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
- (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the SMARTCARD.
+ (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
+ (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
(+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
- (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
-
+ (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
+
@endverbatim
* @{
*/
/**
- * @brief Update on the fly the SMARTCARD block length in RTOR register
- * @param hsmartcard: SMARTCARD handle
- * @param BlockLength: SMARTCARD block length (8-bit long at most)
+ * @brief Update on the fly the SMARTCARD block length in RTOR register.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param BlockLength: SMARTCARD block length (8-bit long at most)
* @retval None
*/
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
@@ -114,64 +114,67 @@
}
/**
- * @brief Update on the fly the receiver timeout value in RTOR register
- * @param hsmartcard: SMARTCARD handle
+ * @brief Update on the fly the receiver timeout value in RTOR register.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
- * value must be less or equal to 0x0FFFFFFFF.
+ * value must be less or equal to 0x0FFFFFFFF.
* @retval None
*/
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
{
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
- MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
}
/**
- * @brief Enable the SMARTCARD receiver timeout feature
- * @param hsmartcard: SMARTCARD handle
+ * @brief Enable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
{
-
+
/* Process Locked */
__HAL_LOCK(hsmartcard);
-
+
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
-
+
/* Set the USART RTOEN bit */
hsmartcard->Instance->CR2 |= USART_CR2_RTOEN;
-
+
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief Disable the SMARTCARD receiver timeout feature
- * @param hsmartcard: SMARTCARD handle
+ * @brief Disable the SMARTCARD receiver timeout feature.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
{
-
+
/* Process Locked */
__HAL_LOCK(hsmartcard);
-
+
hsmartcard->State = HAL_SMARTCARD_STATE_BUSY;
-
+
/* Clear the USART RTOEN bit */
hsmartcard->Instance->CR2 &= ~(USART_CR2_RTOEN);
-
+
hsmartcard->State = HAL_SMARTCARD_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
@@ -190,7 +193,7 @@
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smartcard_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_smartcard_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
- * @brief Header file of SMARTCARD HAL module.
+ * @version V1.3.0
+ * @date 26-June-2015
+ * @brief Header file of SMARTCARD HAL Extended module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -32,7 +32,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -54,9 +54,9 @@
/** @addtogroup SMARTCARDEx
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
@@ -70,7 +70,7 @@
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
*/
#if defined(STM32F031x6) || defined(STM32F038xx)
-#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
@@ -94,7 +94,7 @@
#elif defined (STM32F030x8) || \
defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F051x8) || defined (STM32F058xx)
-#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -127,7 +127,7 @@
} \
} while(0)
#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
-#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -185,7 +185,7 @@
} \
} while(0)
#elif defined(STM32F091xC) || defined(STM32F098xx)
-#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -279,24 +279,23 @@
/**
* @}
- */
+ */
/* Exported functions --------------------------------------------------------*/
-
-/* Initialization and de-initialization functions ****************************/
-/* IO operation functions *****************************************************/
-
/** @addtogroup SMARTCARDEx_Exported_Functions
* @{
*/
+/* Initialization and de-initialization functions ****************************/
+/* IO operation methods *******************************************************/
+
/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
* @{
*/
-
+
/* Peripheral Control functions ***********************************************/
-void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
-void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
@@ -304,7 +303,7 @@
/**
* @}
- */
+ */
/**
* @}
@@ -312,7 +311,7 @@
/**
* @}
- */
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,16 +2,16 @@
******************************************************************************
* @file stm32f0xx_hal_smbus.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief SMBUS HAL module driver.
- *
* This file provides firmware functions to manage the following
* functionalities of the System Management Bus (SMBus) peripheral,
- * based on I2C principales of operation :
+ * based on I2C principles of operation :
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -22,22 +22,22 @@
(#) Declare a SMBUS_HandleTypeDef handle structure, for example:
SMBUS_HandleTypeDef hsmbus;
- (#)Initialize the SMBUS low level resources by implement the HAL_SMBUS_MspInit ()API:
- (##) Enable the SMBUSx interface clock
- (##) SMBUS pins configuration
+ (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
+ (++) Enable the SMBUSx interface clock with __HAL_RCC_I2Cx_CLK_ENABLE()
+ (++) SMBUS pins configuration
(+++) Enable the clock for the SMBUS GPIOs
(+++) Configure SMBUS pins as alternate function open-drain
- (##) NVIC configuration if you need to use interrupt process
+ (++) NVIC configuration if you need to use interrupt process
(+++) Configure the SMBUSx interrupt priority
(+++) Enable the NVIC SMBUS IRQ Channel
- (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Adressing Mode,
+ (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing Mode,
Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
(#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
- (++) These API s configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_SMBUS_MspInit(&hsmbus) API.
+ (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
(#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
@@ -46,35 +46,35 @@
*** Interrupt mode IO operation ***
===================================
[..]
- (+) Transmit in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Transmit_IT()
- (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback
- (+) Receive in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Receive_IT()
- (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback
- (+) Abort a master/host SMBUS process commnunication with Interrupt using HAL_SMBUS_Master_Abort_IT()
+ (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
+ (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
+ (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
(++) The associated previous transfer callback is called at the end of abort process
- (++) mean HAL_SMBUS_MasterTxCpltCallback in case of previous state was master transmit
- (++) mean HAL_SMBUS_MasterRxCpltCallback in case of previous state was master receive
+ (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+ (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
(+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
- using HAL_SMBUS_Slave_Listen_IT() HAL_SMBUS_DisableListen_IT()
- (++) When address slave/device SMBUS match, HAL_SMBUS_SlaveAddrCallback is executed and user can
+ using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
+ (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
- (++) At Listen mode end HAL_SMBUS_SlaveListenCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_SlaveListenCpltCallback
- (+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Transmit_IT()
- (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback
- (+) Receive in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Receive_IT()
- (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback
+ (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
+ (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
+ (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
+ (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
+ (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
(+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
(++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ErrorCallback
+ add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
to check the Alert Error Code using function HAL_SMBUS_GetError()
(+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
(+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ErrorCallback
+ add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
to check the Error Code using function HAL_SMBUS_GetError()
*** SMBUS HAL driver macros list ***
@@ -97,7 +97,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -131,7 +131,7 @@
* @{
*/
-/** @defgroup SMBUS SMBUS HAL module driver
+/** @defgroup SMBUS SMBUS
* @brief SMBUS HAL module driver
* @{
*/
@@ -139,8 +139,8 @@
#ifdef HAL_SMBUS_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Define SMBUS Private Define
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Define SMBUS Private Constants
* @{
*/
#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! SMBUS TIMING clear register Mask */
@@ -158,18 +158,9 @@
*/
/* Private macro -------------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Macros SMBUS Private Macros
- * @{
- */
-#define __SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
-#define __SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
-/**
- * @}
- */
-
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
+/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
@@ -184,7 +175,7 @@
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
* @{
@@ -198,7 +189,7 @@
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the SMBUSx peripheral:
+ de-initialize the SMBUSx peripheral:
(+) User must Implement HAL_SMBUS_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
@@ -220,15 +211,15 @@
(+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
- of the selected SMBUSx periperal.
+ of the selected SMBUSx peripheral.
@endverbatim
* @{
*/
/**
- * @brief Initializes the SMBUS according to the specified parameters
- * in the SMBUS_InitTypeDef and create the associated handle.
+ * @brief Initialize the SMBUS according to the specified parameters
+ * in the SMBUS_InitTypeDef and initialize the associated handle.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval HAL status
@@ -256,6 +247,9 @@
if(hsmbus->State == HAL_SMBUS_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hsmbus->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_SMBUS_MspInit(hsmbus);
}
@@ -310,7 +304,7 @@
hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
/* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
- if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLED)
+ if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
&& ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
{
hsmbus->Instance->CR1 |= I2C_CR1_SBC;
@@ -327,7 +321,7 @@
}
/**
- * @brief DeInitializes the SMBUS peripheral.
+ * @brief DeInitialize the SMBUS peripheral.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval HAL status
@@ -362,27 +356,27 @@
}
/**
- * @brief SMBUS MSP Init.
+ * @brief Initialize the SMBUS MSP.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval None
*/
__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMBUS_MspInit could be implemented in the user file
*/
}
/**
- * @brief SMBUS MSP DeInit
+ * @brief DeInitialize the SMBUS MSP.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval None
*/
__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMBUS_MspDeInit could be implemented in the user file
*/
}
@@ -416,7 +410,7 @@
(++) HAL_SMBUS_Master_Receive_IT()
(++) HAL_SMBUS_Slave_Transmit_IT()
(++) HAL_SMBUS_Slave_Receive_IT()
- (++) HAL_SMBUS_Slave_Listen_IT() or alias HAL_SMBUS_EnableListen_IT()
+ (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
(++) HAL_SMBUS_DisableListen_IT()
(++) HAL_SMBUS_EnableAlert_IT()
(++) HAL_SMBUS_DisableAlert_IT()
@@ -426,8 +420,8 @@
(++) HAL_SMBUS_MasterRxCpltCallback()
(++) HAL_SMBUS_SlaveTxCpltCallback()
(++) HAL_SMBUS_SlaveRxCpltCallback()
- (++) HAL_SMBUS_SlaveAddrCallback() or alias HAL_SMBUS_AddrCallback()
- (++) HAL_SMBUS_SlaveListenCpltCallback() or alias HAL_SMBUS_ListenCpltCallback()
+ (++) HAL_SMBUS_AddrCallback()
+ (++) HAL_SMBUS_ListenCpltCallback()
(++) HAL_SMBUS_ErrorCallback()
@endverbatim
@@ -435,7 +429,7 @@
*/
/**
- * @brief Transmit in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt
+ * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param DevAddress: Target device address
@@ -499,7 +493,7 @@
/* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -523,7 +517,7 @@
}
/**
- * @brief Receive in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt
+ * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param DevAddress: Target device address
@@ -604,8 +598,8 @@
}
/**
- * @brief Abort a master/host SMBUS process commnunication with Interrupt
- * @note : This abort can be called only if state is ready
+ * @brief Abort a master/host SMBUS process communication with Interrupt.
+ * @note This abort can be called only if state is ready
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param DevAddress: Target device address
@@ -664,7 +658,7 @@
}
/**
- * @brief Transmit in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt
+ * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param pData: Pointer to data buffer
@@ -726,7 +720,7 @@
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -755,7 +749,7 @@
}
/**
- * @brief Receive in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt
+ * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param pData: Pointer to data buffer
@@ -801,7 +795,7 @@
/* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
/* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
/* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
- if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
+ if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
{
SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
@@ -832,12 +826,12 @@
}
/**
- * @brief This function enable the Address listen mode
+ * @brief Enable the Address listen mode with Interrupt.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus)
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
{
hsmbus->State = HAL_SMBUS_STATE_LISTEN;
@@ -848,7 +842,7 @@
}
/**
- * @brief This function disable the Address listen mode
+ * @brief Disable the Address listen mode with Interrupt.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval HAL status
@@ -872,7 +866,7 @@
}
/**
- * @brief This function enable the SMBUS alert mode.
+ * @brief Enable the SMBUS alert mode with Interrupt.
* @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUSx peripheral.
* @retval HAL status
@@ -891,7 +885,7 @@
return HAL_OK;
}
/**
- * @brief This function disable the SMBUS alert mode.
+ * @brief Disable the SMBUS alert mode with Interrupt.
* @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUSx peripheral.
* @retval HAL status
@@ -908,7 +902,7 @@
}
/**
- * @brief Checks if target device is ready for communication.
+ * @brief Check if target device is ready for communication.
* @note This function is used with Memory devices
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
@@ -939,7 +933,7 @@
do
{
/* Generate Start */
- hsmbus->Instance->CR2 = __HAL_SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
+ hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set or a NACK flag is set*/
@@ -1024,9 +1018,16 @@
return HAL_BUSY;
}
}
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
/**
- * @brief This function handles SMBUS event interrupt request.
+ * @brief Handle SMBUS event interrupt request.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval None
@@ -1037,10 +1038,10 @@
/* Use a local variable to store the current ISR flags */
/* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
- tmpisrvalue = __SMBUS_GET_ISR_REG(hsmbus);
+ tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
/* SMBUS in mode Transmitter ---------------------------------------------------*/
- if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
+ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
{
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
@@ -1055,7 +1056,7 @@
}
/* SMBUS in mode Receiver ----------------------------------------------------*/
- if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
+ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
{
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
@@ -1070,7 +1071,7 @@
}
/* SMBUS in mode Listener Only --------------------------------------------------*/
- if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
+ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
&& ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
{
if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
@@ -1081,7 +1082,7 @@
}
/**
- * @brief This function handles SMBUS error interrupt request.
+ * @brief Handle SMBUS error interrupt request.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval None
@@ -1142,10 +1143,10 @@
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
}
- /* Call the Error Callback in case of Error detected */
+ /* Call the Error Callback() in case of Error detected */
if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
{
- /* Do not Reset the the HAL state in case of ALERT error */
+ /* Do not Reset the HAL state in case of ALERT error */
if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
{
if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
@@ -1164,94 +1165,94 @@
}
/**
- * @brief Master Tx Transfer completed callbacks.
+ * @brief Master Tx Transfer completed callback.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval None
*/
__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMBUS_TxCpltCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
*/
}
/**
- * @brief Master Rx Transfer completed callbacks.
+ * @brief Master Rx Transfer completed callback.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval None
*/
__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMBUS_TxCpltCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
*/
}
-/** @brief Slave Tx Transfer completed callbacks.
+/** @brief Slave Tx Transfer completed callback.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval None
*/
__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMBUS_TxCpltCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
*/
}
/**
- * @brief Slave Rx Transfer completed callbacks.
+ * @brief Slave Rx Transfer completed callback.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval None
*/
__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMBUS_TxCpltCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
*/
}
/**
- * @brief Slave Address Match callbacks.
+ * @brief Slave Address Match callback.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param TransferDirection: Master request Transfer Direction (Write/Read)
* @param AddrMatchCode: Address Match Code
* @retval None
*/
-__weak void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
+__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMBUS_SlaveAddrCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_AddrCallback() could be implemented in the user file
*/
}
/**
- * @brief Listen Complete callbacks.
+ * @brief Listen Complete callback.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval None
*/
-__weak void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMBUS_SlaveListenCpltCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
*/
}
/**
- * @brief SMBUS error callbacks.
+ * @brief SMBUS error callback.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval None
*/
__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMBUS_ErrorCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMBUS_ErrorCallback() could be implemented in the user file
*/
}
@@ -1267,7 +1268,7 @@
##### Peripheral State and Errors functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1275,17 +1276,19 @@
*/
/**
- * @brief Returns the SMBUS state.
- * @param hsmbus : SMBUS handle
+ * @brief Return the SMBUS handle state.
+ * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
* @retval HAL state
*/
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
{
+ /* Return SMBUS handle state */
return hsmbus->State;
}
/**
-* @brief Return the SMBUS error code
+* @brief Return the SMBUS error code.
* @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval SMBUS Error Code
@@ -1309,7 +1312,7 @@
*/
/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval HAL status
@@ -1349,7 +1352,7 @@
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_SMBUS_RESET_CR2(hsmbus);
+ SMBUS_RESET_CR2(hsmbus);
/* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
/* Disable the selected SMBUS peripheral */
@@ -1375,7 +1378,7 @@
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
/* Clear Configuration Register 2 */
- __HAL_SMBUS_RESET_CR2(hsmbus);
+ SMBUS_RESET_CR2(hsmbus);
hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
hsmbus->State = HAL_SMBUS_STATE_READY;
@@ -1417,7 +1420,7 @@
SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -1426,8 +1429,8 @@
}
else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0))
{
- /* Call TxCpltCallback if no stop mode is set */
- if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ /* Call TxCpltCallback() if no stop mode is set */
+ if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
@@ -1466,8 +1469,8 @@
/* Generate a Stop command */
hsmbus->Instance->CR2 |= I2C_CR2_STOP;
}
- /* Call TxCpltCallback if no stop mode is set */
- else if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ /* Call TxCpltCallback() if no stop mode is set */
+ else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
{
/* No Generate Stop, to permit restart mode */
/* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
@@ -1506,7 +1509,7 @@
return HAL_OK;
}
/**
- * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval HAL status
@@ -1560,8 +1563,8 @@
}
else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
{
- TransferDirection = __HAL_SMBUS_GET_DIR(hsmbus);
- SlaveAddrCode = __HAL_SMBUS_GET_ADDR_MATCH(hsmbus);
+ TransferDirection = SMBUS_GET_DIR(hsmbus);
+ SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
/* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
/* Other ADDRInterrupt will be treat in next Listen usecase */
@@ -1571,7 +1574,7 @@
__HAL_UNLOCK(hsmbus);
/* Call Slave Addr callback */
- HAL_SMBUS_SlaveAddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+ HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
}
else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
{
@@ -1629,7 +1632,7 @@
SMBUS_TransferConfig(hsmbus, 0, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -1642,7 +1645,7 @@
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
- /* Check if all Datas have already been sent */
+ /* Check if all Data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
if(hsmbus->XferCount > 0)
{
@@ -1683,7 +1686,7 @@
hsmbus->Instance->CR2 |= I2C_CR2_NACK;
/* Clear Configuration Register 2 */
- __HAL_SMBUS_RESET_CR2(hsmbus);
+ SMBUS_RESET_CR2(hsmbus);
/* Clear STOP Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
@@ -1699,7 +1702,7 @@
__HAL_UNLOCK(hsmbus);
/* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */
- HAL_SMBUS_SlaveListenCpltCallback(hsmbus);
+ HAL_SMBUS_ListenCpltCallback(hsmbus);
}
}
@@ -1709,7 +1712,7 @@
return HAL_OK;
}
/**
- * @brief Manage the enabling of Interrupts
+ * @brief Manage the enabling of Interrupts.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
@@ -1751,7 +1754,7 @@
return HAL_OK;
}
/**
- * @brief Manage the disabling of Interrupts
+ * @brief Manage the disabling of Interrupts.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
@@ -1772,7 +1775,7 @@
/* Disable TC, STOP, NACK, TXI interrupt */
tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
- if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
&& ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
{
/* Disable ERR interrupt */
@@ -1791,7 +1794,7 @@
/* Disable TC, STOP, NACK, RXI interrupt */
tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
- if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
&& ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
{
/* Disable ERR interrupt */
@@ -1810,7 +1813,7 @@
/* Enable ADDR, STOP interrupt */
tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
- if(__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
@@ -1825,7 +1828,7 @@
return HAL_OK;
}
/**
- * @brief This function handles SMBUS Communication Timeout.
+ * @brief Handle SMBUS Communication Timeout.
* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param Flag: specifies the SMBUS flag to check.
@@ -1882,7 +1885,7 @@
}
/**
- * @brief Handles SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
* @param hsmbus: SMBUS handle.
* @param DevAddress: specifies the slave address to be programmed.
* @param Size: specifies the number of bytes to be programmed.
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_smbus.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of SMBUS HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -59,8 +59,9 @@
* @{
*/
-/**
+/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
* @brief SMBUS Configuration Structure definition
+ * @{
*/
typedef struct
{
@@ -68,7 +69,7 @@
This parameter calculated by referring to SMBUS initialization
section in Reference manual */
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
- This parameter can be a a value of @ref SMBUS_Analog_Filter */
+ This parameter can be a value of @ref SMBUS_Analog_Filter */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
@@ -102,9 +103,48 @@
This parameter calculated by referring to SMBUS initialization
section in Reference manual */
} SMBUS_InitTypeDef;
+/**
+ * @}
+ */
+/** @defgroup HAL_state_definition HAL state definition
+ * @brief HAL State definition
+ * @{
+ */
+#define HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000) /*!< SMBUS not yet initialized or disabled */
+#define HAL_SMBUS_STATE_READY ((uint32_t)0x00000001) /*!< SMBUS initialized and ready for use */
+#define HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002) /*!< SMBUS internal process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012) /*!< Master Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022) /*!< Master Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032) /*!< Slave Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042) /*!< Slave Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003) /*!< Timeout state */
+#define HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004) /*!< Reception process is ongoing */
+#define HAL_SMBUS_STATE_LISTEN ((uint32_t)0x00000008) /*!< Address Listen Mode is ongoing */
/**
+ * @}
+ */
+
+/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
+ * @brief SMBUS Error Code definition
+ * @{
+ */
+#define HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
+#define HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
+#define HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
+#define HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004) /*!< ACKF error */
+#define HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
+#define HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010) /*!< Timeout error */
+#define HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020) /*!< Bus Timeout error */
+#define HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040) /*!< Alert error */
+#define HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080) /*!< PEC error */
+/**
+ * @}
+ */
+
+/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
* @brief SMBUS handle Structure definition
+ * @{
*/
typedef struct
{
@@ -120,73 +160,33 @@
__IO uint32_t XferOptions; /*!< SMBUS transfer options */
- __IO uint32_t PreviousState; /*!< SMBUS communication Previous state
- This parameter can be a value of @ref SMBUS_State */
+ __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
HAL_LockTypeDef Lock; /*!< SMBUS locking object */
- __IO uint32_t State; /*!< SMBUS communication state
- This parameter can be a value of @ref SMBUS_State */
+ __IO uint32_t State; /*!< SMBUS communication state */
- __IO uint32_t ErrorCode; /*!< SMBUS Error code
- This parameter can be a value of @ref SMBUS_Error */
+ __IO uint32_t ErrorCode; /*!< SMBUS Error code */
}SMBUS_HandleTypeDef;
/**
* @}
*/
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
* @{
*/
-/** @defgroup SMBUS_Error SMBUS Error
- * @{
- */
-#define HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
-#define HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
-#define HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004) /*!< ACKF error */
-#define HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
-#define HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010) /*!< Timeout error */
-#define HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020) /*!< Bus Timeout error */
-#define HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040) /*!< Alert error */
-#define HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080) /*!< PEC error */
-/**
- * @}
- */
-
-/** @defgroup SMBUS_State SMBUS State
- * @{
- */
-
-#define HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000) /*!< SMBUS not yet initialized or disabled */
-#define HAL_SMBUS_STATE_READY ((uint32_t)0x00000001) /*!< SMBUS initialized and ready for use */
-#define HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002) /*!< SMBUS internal process is ongoing */
-#define HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012) /*!< Master Data Transmission process is ongoing */
-#define HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022) /*!< Master Data Reception process is ongoing */
-#define HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032) /*!< Slave Data Transmission process is ongoing */
-#define HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042) /*!< Slave Data Reception process is ongoing */
-#define HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003) /*!< Timeout state */
-#define HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004) /*!< Reception process is ongoing */
-#define HAL_SMBUS_STATE_SLAVE_LISTEN ((uint32_t)0x00000008) /*!< Address Listen Mode is ongoing */
- /* Aliases for inter STM32 series compatibility */
-#define HAL_SMBUS_STATE_LISTEN HAL_SMBUS_STATE_SLAVE_LISTEN
-
-/**
- * @}
- */
-
/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
* @{
*/
-#define SMBUS_ANALOGFILTER_ENABLED ((uint32_t)0x00000000)
-#define SMBUS_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF
-
-#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLED) || \
- ((FILTER) == SMBUS_ANALOGFILTER_DISABLED))
+#define SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
+#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
@@ -196,9 +196,6 @@
*/
#define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
#define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
-
-#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
- ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
/**
* @}
*/
@@ -207,11 +204,8 @@
* @{
*/
-#define SMBUS_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
-#define SMBUS_DUALADDRESS_ENABLED I2C_OAR2_OA2EN
-
-#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLED) || \
- ((ADDRESS) == SMBUS_DUALADDRESS_ENABLED))
+#define SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
+#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
@@ -228,15 +222,6 @@
#define SMBUS_OA2_MASK05 ((uint8_t)0x05)
#define SMBUS_OA2_MASK06 ((uint8_t)0x06)
#define SMBUS_OA2_MASK07 ((uint8_t)0x07)
-
-#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
- ((MASK) == SMBUS_OA2_MASK01) || \
- ((MASK) == SMBUS_OA2_MASK02) || \
- ((MASK) == SMBUS_OA2_MASK03) || \
- ((MASK) == SMBUS_OA2_MASK04) || \
- ((MASK) == SMBUS_OA2_MASK05) || \
- ((MASK) == SMBUS_OA2_MASK06) || \
- ((MASK) == SMBUS_OA2_MASK07))
/**
* @}
*/
@@ -245,11 +230,8 @@
/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
* @{
*/
-#define SMBUS_GENERALCALL_DISABLED ((uint32_t)0x00000000)
-#define SMBUS_GENERALCALL_ENABLED I2C_CR1_GCEN
-
-#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLED) || \
- ((CALL) == SMBUS_GENERALCALL_ENABLED))
+#define SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000)
+#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
@@ -257,11 +239,8 @@
/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
* @{
*/
-#define SMBUS_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
-#define SMBUS_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
-
-#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLED) || \
- ((STRETCH) == SMBUS_NOSTRETCH_ENABLED))
+#define SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
+#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
@@ -269,11 +248,8 @@
/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
* @{
*/
-#define SMBUS_PEC_DISABLED ((uint32_t)0x00000000)
-#define SMBUS_PEC_ENABLED I2C_CR1_PECEN
-
-#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLED) || \
- ((PEC) == SMBUS_PEC_ENABLED))
+#define SMBUS_PEC_DISABLE ((uint32_t)0x00000000)
+#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
/**
* @}
*/
@@ -284,10 +260,6 @@
#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN)
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000)
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN)
-
-#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
- ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
- ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
/**
* @}
*/
@@ -300,15 +272,6 @@
#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
-
-#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
- ((MODE) == SMBUS_AUTOEND_MODE) || \
- ((MODE) == SMBUS_SOFTEND_MODE) || \
- ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
-
/**
* @}
*/
@@ -321,12 +284,6 @@
#define SMBUS_GENERATE_STOP I2C_CR2_STOP
#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define SMBUS_GENERATE_START_WRITE I2C_CR2_START
-
-#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
- ((REQUEST) == SMBUS_GENERATE_START_READ) || \
- ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
- ((REQUEST) == SMBUS_NO_STARTSTOP))
-
/**
* @}
*/
@@ -341,14 +298,6 @@
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
-
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
- ((REQUEST) == SMBUS_NEXT_FRAME) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
-
/**
* @}
*/
@@ -410,16 +359,15 @@
* @{
*/
-/** @brief Reset SMBUS handle state
- * @param __HANDLE__: SMBUS handle.
+/** @brief Reset SMBUS handle state.
+ * @param __HANDLE__: specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
-/** @brief Enable or disable the specified SMBUS interrupts.
+/** @brief Enable the specified SMBUS interrupts.
* @param __HANDLE__: specifies the SMBUS Handle.
- * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * @param __INTERRUPT__: specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg SMBUS_IT_ERRI: Errors interrupt enable
* @arg SMBUS_IT_TCI: Transfer complete interrupt enable
@@ -431,13 +379,26 @@
*
* @retval None
*/
-
#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief Disable the specified SMBUS interrupts.
+ * @param __HANDLE__: specifies the SMBUS Handle.
+ * @param __INTERRUPT__: specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg SMBUS_IT_ERRI: Errors interrupt enable
+ * @arg SMBUS_IT_TCI: Transfer complete interrupt enable
+ * @arg SMBUS_IT_STOPI: STOP detection interrupt enable
+ * @arg SMBUS_IT_NACKI: NACK received interrupt enable
+ * @arg SMBUS_IT_ADDRI: Address match interrupt enable
+ * @arg SMBUS_IT_RXI: RX interrupt enable
+ * @arg SMBUS_IT_TXI: TX interrupt enable
+ *
+ * @retval None
+ */
#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-/** @brief Checks if the specified SMBUS interrupt source is enabled or disabled.
+/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
* @param __HANDLE__: specifies the SMBUS Handle.
- * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
* @param __INTERRUPT__: specifies the SMBUS interrupt source to check.
* This parameter can be one of the following values:
* @arg SMBUS_IT_ERRI: Errors interrupt enable
@@ -452,9 +413,8 @@
*/
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-/** @brief Checks whether the specified SMBUS flag is set or not.
+/** @brief Check whether the specified SMBUS flag is set or not.
* @param __HANDLE__: specifies the SMBUS Handle.
- * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SMBUS_FLAG_TXE: Transmit data register empty
@@ -479,9 +439,8 @@
#define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF)
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
-/** @brief Clears the SMBUS pending flags which are cleared by writing 1 in a specific bit.
+/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__: specifies the SMBUS Handle.
- * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg SMBUS_FLAG_ADDR: Address matched (slave mode)
@@ -498,25 +457,116 @@
*/
#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+/** @brief Enable the specified SMBUS peripheral.
+ * @param __HANDLE__: specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-#define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
-#define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
+/** @brief Disable the specified SMBUS peripheral.
+ * @param __HANDLE__: specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
+ * @param __HANDLE__: specifies the SMBUS Handle.
+ * @retval None
+ */
+#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
+ * @{
+ */
+
+#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
+ ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
+
+#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
+ ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
+
+#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
-#define __HAL_SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
-#define __HAL_SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
+ ((MASK) == SMBUS_OA2_MASK01) || \
+ ((MASK) == SMBUS_OA2_MASK02) || \
+ ((MASK) == SMBUS_OA2_MASK03) || \
+ ((MASK) == SMBUS_OA2_MASK04) || \
+ ((MASK) == SMBUS_OA2_MASK05) || \
+ ((MASK) == SMBUS_OA2_MASK06) || \
+ ((MASK) == SMBUS_OA2_MASK07))
+
+#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
+ ((CALL) == SMBUS_GENERALCALL_ENABLE))
+
+#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
+
+#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
+ ((PEC) == SMBUS_PEC_ENABLE))
+
+#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
-#define __HAL_SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
+ ((MODE) == SMBUS_AUTOEND_MODE) || \
+ ((MODE) == SMBUS_SOFTEND_MODE) || \
+ ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
+
+
+#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
+ ((REQUEST) == SMBUS_GENERATE_START_READ) || \
+ ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
+ ((REQUEST) == SMBUS_NO_STARTSTOP))
+
+
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
+ ((REQUEST) == SMBUS_NEXT_FRAME) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
+
+#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
+#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-#define __HAL_SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
-#define __HAL_SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
-#define __HAL_SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define __HAL_SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
-#define __HAL_SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
-#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK)
+#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
+#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
+#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
+#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
+
+#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
+#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32l4xx_hal_smbus.c file */
/**
* @}
*/
@@ -545,9 +595,18 @@
*/
/* IO operation functions *****************************************************/
+/** @addtogroup Blocking_mode_Polling Blocking mode Polling
+ * @{
+ */
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+/**
+ * @}
+ */
+/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
+ * @{
+ */
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
@@ -557,12 +616,15 @@
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+/**
+ * @}
+ */
-/* Aliases for new API and to insure inter STM32 series compatibility */
-#define HAL_SMBUS_EnableListen_IT HAL_SMBUS_Slave_Listen_IT
-
+/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
@@ -570,13 +632,8 @@
void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-
-/* Aliases for new API and to insure inter STM32 series compatibility */
-#define HAL_SMBUS_AddrCallback HAL_SMBUS_SlaveAddrCallback
-#define HAL_SMBUS_ListenCpltCallback HAL_SMBUS_SlaveListenCpltCallback
-
+void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
/**
@@ -599,6 +656,12 @@
* @}
*/
+
+
+/**
+ * @}
+ */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,87 +2,95 @@
******************************************************************************
* @file stm32f0xx_hal_spi.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief SPI HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the SPI peripheral:
- * + Initialization/de-initialization functions
- * + I/O operation functions
- * + Peripheral Control functions
+ * This file provides firmware functions to manage the following
+ * functionalities of the Serial Peripheral Interface (SPI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
* + Peripheral State functions
- *
+ *
@verbatim
-===============================================================================
- ##### How to use this driver #####
- ===============================================================================
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
[..]
- The SPI HAL driver can be used as follows:
-
- (#) Declare a SPI_HandleTypeDef handle structure, for example:
- SPI_HandleTypeDef hspi;
-
- (#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API:
- (##) Enable the SPIx interface clock
- (##) SPI pins configuration
- (+++) Enable the clock for the SPI GPIOs
- (+++) Configure these SPI pins as alternate function push-pull
- (##) NVIC configuration if you need to use interrupt process
- (+++) Configure the SPIx interrupt priority
- (+++) Enable the NVIC SPI IRQ handle
- (##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
- (+++) Enable the DMAx interface clock using
- (+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx channel
- (+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
-
- (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
- management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
-
- (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
- (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_SPI_MspInit(&hspi) API.
-
- [..]
- Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
- the following table resume the max SPI frequency reached with data size 8bits/16bits:
- +-----------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Tranfert mode |--------------------|--------------------|--------------------|
- | | | Master | Slave | Master | Slave | Master | Slave |
- |=========================================================================================|
- | T | Polling | Fcpu/32 | Fcpu/32 | NA | NA | NA | NA |
- | X |----------------|----------|---------|----------|---------|----------|---------|
- | / | Interrupt | Fcpu/32 | Fcpu/32 | NA | NA | NA | NA |
- | R |----------------|----------|---------|----------|---------|----------|---------|
- | X | DMA | Fcpu/32 | Fcpu/16 | NA | NA | NA | NA |
- |=========|================|==========|=========|==========|=========|==========|=========|
- | | Polling | Fcpu/32 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 |
- | |----------------|----------|---------|----------|---------|----------|---------|
- | R | Interrupt | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 |
- | X |----------------|----------|---------|----------|---------|----------|---------|
- | | DMA | Fcpu/4 | Fcpu/8 | Fcpu/4 | Fcpu/4 | Fcpu/8 | Fcpu/16 |
- |=========|================|==========|=========|==========|=========|==========|=========|
- | | Polling | Fcpu/16 | Fcpu/16 | NA | NA | Fcpu/16 | Fcpu/16 |
- | |----------------|----------|---------|----------|---------|----------|---------|
- | T | Interrupt | Fcpu/32 | Fcpu/16 | NA | NA | Fcpu/16 | Fcpu/16 |
- | X |----------------|----------|---------|----------|---------|----------|---------|
- | | DMA | Fcpu/2 | Fcpu/16 | NA | NA | Fcpu/8 | Fcpu/16 |
- +-----------------------------------------------------------------------------------------+
- @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
- SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
- @note
- (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
- (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
- (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
-
+ The SPI HAL driver can be used as follows:
+
+ (#) Declare a SPI_HandleTypeDef handle structure, for example:
+ SPI_HandleTypeDef hspi;
+
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
+ (##) Enable the SPIx interface clock
+ (##) SPI pins configuration
+ (+++) Enable the clock for the SPI GPIOs
+ (+++) Configure these SPI pins as alternate function push-pull
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the SPIx interrupt priority
+ (+++) Enable the NVIC SPI IRQ handle
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+ (+++) Enable the DMAx clock
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx channel
+ (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
+
+ (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
+ management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
+
+ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SPI_MspInit() API.
+ [..]
+ Circular mode restriction:
+ (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
+ (##) Master 2Lines RxOnly
+ (##) Master 1Line Rx
+ (#) The CRC feature is not managed when the DMA circular mode is enabled
+ (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
+ the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+ [..]
+ Using the HAL it is not possible to reach all supported SPI frequency with the differents
+ the following table resume the max SPI frequency reached with data size 8bits/16bits,
+ according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
+ +-----------------------------------------------------------------------------------------
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line
+ | Process | Tranfert mode |---------------------|---------------------|------------------
+ | | | Master | Slave | Master | Slave | Master | Slave
+ |=========================================================================================
+ | T | Polling | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA
+ | X |----------------|----------|----------|----------|----------|----------|-------
+ | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA
+ | R |----------------|----------|----------|----------|----------|----------|-------
+ | X | DMA | fPCLK/32 | fPCLK/16 | NA | NA | NA | NA
+ |=========|================|==========|==========|==========|==========|==========|=======
+ | | Polling | fPCLK/32 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/
+ | |----------------|----------|----------|----------|----------|----------|-------
+ | R | Interrupt | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/16 | fPCLK/
+ | X |----------------|----------|----------|----------|----------|----------|-------
+ | | DMA | fPCLK/4 | fPCLK/8 | fPCLK/4 | fPCLK/4 | fPCLK/8 | fPCLK/
+ |=========|================|==========|==========|==========|==========|==========|=======
+ | | Polling | fPCLK/16 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/
+ | |----------------|----------|----------|----------|----------|----------|-------
+ | T | Interrupt | fPCLK/32 | fPCLK/16 | NA | NA | fPCLK/16 | fPCLK/
+ | X |----------------|----------|----------|----------|----------|----------|-------
+ | | DMA | fPCLK/2 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/
+ +-----------------------------------------------------------------------------------------
+ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16
+ SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling
+ @note
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_S
+ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+ (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -106,41 +114,38 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
-
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
-
+
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
-/** @defgroup SPI SPI HAL module driver
+/** @defgroup SPI SPI
* @brief SPI HAL module driver
* @{
*/
#ifdef HAL_SPI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
+/* Private defines -----------------------------------------------------------*/
/** @defgroup SPI_Private_Constants SPI Private Constants
* @{
*/
#define SPI_DEFAULT_TIMEOUT 50
-#define SPI_FIFO_SIZE 4
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup SPI_Private_Functions SPI Private Functions
* @{
*/
-
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
@@ -166,6 +171,7 @@
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
/**
* @}
*/
@@ -176,23 +182,23 @@
* @{
*/
-/** @defgroup SPI_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
- ##### Initialization and Configuration functions #####
+ ##### Initialization and de-initialization functions #####
===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the SPIx peripheral:
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SPIx peripheral:
- (+) User must Implement HAL_SPI_MspInit() function in which he configures
+ (+) User must implement HAL_SPI_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
- (+) Call the function HAL_SPI_Init() to configure the selected device with
+ (+) Call the function HAL_SPI_Init() to configure the selected device with
the selected configuration:
(++) Mode
- (++) Direction
+ (++) Direction
(++) Data Size
(++) Clock Polarity and Phase
(++) NSS Management
@@ -201,33 +207,33 @@
(++) TIMode
(++) CRC Calculation
(++) CRC Polynomial if CRC enabled
- (++) CRC Length, used only with Data8 and Data16
+ (++) CRC Length, used only with Data8 and Data16
(++) FIFO reception threshold
- (+) Call the function HAL_SPI_DeInit() to restore the default configuration
- of the selected SPIx periperal.
-
+ (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+ of the selected SPIx peripheral.
+
@endverbatim
* @{
*/
/**
- * @brief Initializes the SPI according to the specified parameters
- * in the SPI_InitTypeDef and create the associated handle.
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * @brief Initialize the SPI according to the specified parameters
+ * in the SPI_InitTypeDef and initialize the associated handle.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
uint32_t frxth;
-
+
/* Check the SPI handle allocation */
if(hspi == NULL)
- {
+ {
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
assert_param(IS_SPI_MODE(hspi->Init.Mode));
@@ -243,15 +249,21 @@
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
-
+
+ if(hspi->State == HAL_SPI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hspi->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspInit(hspi);
+ }
+
hspi->State = HAL_SPI_STATE_BUSY;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC... */
- HAL_SPI_MspInit(hspi);
-
+
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
-
+
/* Align by default the rs fifo threshold on the data size */
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
@@ -261,18 +273,18 @@
{
frxth = SPI_RXFIFO_THRESHOLD_QF;
}
-
+
/* CRC calculation is valid only for 16Bit and 8 Bit */
if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
{
/* CRC must be disabled */
- hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
}
-
+
/* Align the CRC Length on the data size */
if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
{
- /* CRC Lengtht aligned on the data size : value set by default */
+ /* CRC Length aligned on the data size : value set by default */
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
@@ -282,24 +294,24 @@
hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
}
}
-
+
/*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit, CRC calculation state, CRC Length */
- hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
+ hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
-
+
if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
hspi->Instance->CR1|= SPI_CR1_CRCL;
}
-
+
/* Configure : NSS management */
/* Configure : Rx Fifo Threshold */
hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
hspi->Init.DataSize ) | frxth;
-
+
/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
/* Configure : CRC Polynomial */
hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
@@ -309,14 +321,14 @@
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->State= HAL_SPI_STATE_READY;
-
+
return HAL_OK;
}
/**
- * @brief DeInitializes the SPI peripheral
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * @brief DeInitialize the SPI peripheral.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
@@ -330,49 +342,44 @@
/* Check the parameters */
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
hspi->State = HAL_SPI_STATE_BUSY;
-
- /* check flag before the SPI disable */
- SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
- SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT);
- SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
-
+
/* Disable the SPI Peripheral Clock */
__HAL_SPI_DISABLE(hspi);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_SPI_MspDeInit(hspi);
-
+
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->State = HAL_SPI_STATE_RESET;
-
+
__HAL_UNLOCK(hspi);
-
+
return HAL_OK;
}
/**
- * @brief SPI MSP Init
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Initialize the SPI MSP.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
- __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_MspInit could be implenetd in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspInit should be implemented in the user file
*/
}
/**
- * @brief SPI MSP DeInit
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief DeInitialize the SPI MSP.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
- __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_MspDeInit could be implenetd in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspDeInit should be implemented in the user file
*/
}
@@ -380,64 +387,46 @@
* @}
*/
-/** @defgroup SPI_Exported_Functions_Group2 I/O operation functions
- * @brief Data transfers functions
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
*
-@verbatim
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
===============================================================================
- ##### IO operation functions #####
- ===============================================================================
+ [..]
This subsection provides a set of functions allowing to manage the SPI
data transfers.
-
- [..] The SPI supports master and slave mode :
+
+ [..] The SPI supports master and slave mode :
(#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) Non Blocking mode: The communication is performed using Interrupts
- or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
- The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
-
- (#) Blocking mode APIs are :
- (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_TransmitReceive() in full duplex mode
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
- (#) Non Blocking mode APIs with Interrupt are :
- (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_TransmitReceive_IT()in full duplex mode
- (++) HAL_SPI_IRQHandler()
-
- (#) Non Blocking mode functions with DMA are :
- (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
- (++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
-
- (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
- (++) HAL_SPI_TxCpltCallback()
- (++) HAL_SPI_RxCpltCallback()
- (++) HAL_SPI_ErrorCallback()
- (++) HAL_SPI_TxRxCpltCallback()
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+ exist for 1Line (simplex) and 2Lines (full duplex) modes.
@endverbatim
* @{
*/
/**
- * @brief Transmit an amount of data in blocking mode
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData : pointer to data buffer
- * @param Size : amount of data to be sent
- * @param Timeout : Timeout duration
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -450,49 +439,49 @@
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ if(hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
-
+
if((pData == NULL ) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
}
- /* Set the transaction information */
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t*)NULL;
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
hspi->RxXferSize = 0;
hspi->RxXferCount = 0;
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_TX(hspi);
+ SPI_1LINE_TX(hspi);
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
- /* Check if the SPI is already enabled */
+ /* Check if the SPI is already enabled */
if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
-
+
/* Transmit data in 16 Bit mode */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
/* Transmit data in 16 Bit mode */
while (hspi->TxXferCount > 0)
@@ -507,7 +496,7 @@
else
{
/* Timeout management */
- if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -525,7 +514,7 @@
{
if(hspi->TxXferCount > 1)
{
- /* write on the data register in packaing mode */
+ /* write on the data register in packing mode */
hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2;
@@ -533,13 +522,13 @@
else
{
*((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
- hspi->TxXferCount--;
+ hspi->TxXferCount--;
}
}
else
{
/* Timeout management */
- if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -549,20 +538,26 @@
}
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
}
- /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ /* Check the end of the transaction */
+ if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
-
+
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- errorcode = HAL_ERROR;
+ {
+ errorcode = HAL_ERROR;
}
error:
@@ -573,12 +568,12 @@
}
/**
- * @brief Receive an amount of data in blocking mode
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData : pointer to data buffer
- * @param Size : amount of data to be sent
- * @param Timeout : Timeout duration
+ * @brief Receive an amount of data in blocking mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -590,11 +585,11 @@
if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
/* the receive process is not supported in 2Lines direction master mode */
- /* in this case we call the transmitReceive process */
+ /* in this case we call the TransmitReceive process */
/* Process Locked */
return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
}
-
+
/* Process Locked */
__HAL_LOCK(hspi);
@@ -609,40 +604,40 @@
errorcode = HAL_ERROR;
goto error;
}
-
+
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pRxBuffPtr = pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
- hspi->pTxBuffPtr = (uint8_t*)NULL;
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
hspi->TxXferSize = 0;
hspi->TxXferCount = 0;
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
/* this is done to handle the CRCNEXT before the latest data */
hspi->RxXferCount--;
}
- /* Set the Rx Fido thresold */
+ /* Set the Rx Fido threshold */
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- /* set fiforxthresold according the reception data lenght: 16bit */
+ /* set fiforxthresold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthresold according the reception data lenght: 8bit */
+ /* set fiforxthresold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
/* Configure communication direction 1Line and enabled SPI if needed */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_RX(hspi);
+ SPI_1LINE_RX(hspi);
}
/* Check if the SPI is already enabled */
@@ -654,7 +649,7 @@
if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
{
- /* Transfert loop */
+ /* Transfer loop */
while(hspi->RxXferCount > 0)
{
/* Check the RXNE flag */
@@ -666,7 +661,7 @@
}
else
{
- /* Timeout manamgement */
+ /* Timeout management */
if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
{
errorcode = HAL_TIMEOUT;
@@ -677,7 +672,7 @@
}
else
{
- /* Transfert loop */
+ /* Transfer loop */
while(hspi->RxXferCount > 0)
{
/* Check the RXNE flag */
@@ -689,8 +684,8 @@
}
else
{
- /* Timeout mamangement */
- if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ /* Timeout management */
+ if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -700,18 +695,19 @@
}
/* Handle the CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* freeze the CRC before the latest data */
hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
-
+
/* Read the latest data */
if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
{
+ /* the latest data has not been received */
errorcode = HAL_TIMEOUT;
goto error;
}
-
+
/* Receive last data in 16 Bit mode */
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
@@ -722,31 +718,39 @@
{
*hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;
}
-
+
/* Wait until TXE flag */
if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
{
/* Flag Error*/
- hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ hspi->ErrorCode = HAL_SPI_ERROR_CRC;
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
-
+
if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
UNUSED(tmpreg);
}
else
{
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
UNUSED(tmpreg);
+
if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
{
- /* Erreur on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ /* Error on the CRC reception */
+ hspi->ErrorCode = HAL_SPI_ERROR_CRC;
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
UNUSED(tmpreg);
}
}
@@ -755,22 +759,21 @@
/* Check the end of the transaction */
if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
{
- errorcode = HAL_TIMEOUT;
- goto error;
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
-
+
/* Check if CRC error occurred */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
-
+
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
errorcode = HAL_ERROR;
}
-
+
error :
hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
@@ -778,13 +781,13 @@
}
/**
- * @brief Transmit and Receive an amount of data in blocking mode
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData : pointer to transmission data buffer
- * @param pRxData : pointer to reception data buffer to be
- * @param Size : amount of data to be sent
- * @param Timeout : Timeout duration
+ * @brief Transmit and Receive an amount of data in blocking mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @param Size: amount of data to be sent and received
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
@@ -792,9 +795,8 @@
__IO uint16_t tmpreg;
uint32_t tickstart = HAL_GetTick();
HAL_StatusTypeDef errorcode = HAL_OK;
-
+
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- assert_param(pTxData != NULL);
/* Process Locked */
__HAL_LOCK(hspi);
@@ -804,13 +806,13 @@
errorcode = HAL_BUSY;
goto error;
}
-
+
if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
}
-
+
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pRxBuffPtr = pRxData;
@@ -818,36 +820,36 @@
hspi->RxXferSize = Size;
hspi->pTxBuffPtr = pTxData;
hspi->TxXferCount = Size;
- hspi->TxXferSize = Size;
-
+ hspi->TxXferSize = Size;
+
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
-
+
/* Set the Rx Fido threshold */
if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
{
- /* set fiforxthreshold according the reception data lenght: 16bit */
+ /* set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthreshold according the reception data lenght: 8bit */
+ /* set fiforxthreshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
-
- /* Check if the SPI is already enabled */
+
+ /* Check if the SPI is already enabled */
if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
{
- /* Enable SPI peripheral */
+ /* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
-
+
/* Transmit and Receive data in 16 Bit mode */
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
+ {
while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
{
/* Check TXE flag */
@@ -856,14 +858,14 @@
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
-
+
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
- }
+ }
}
-
+
/* Check RXNE flag */
if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
{
@@ -876,11 +878,11 @@
errorcode = HAL_TIMEOUT;
goto error;
}
- }
+ }
}
/* Transmit and Receive data in 8 Bit mode */
else
- {
+ {
while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
{
/* check TXE flag */
@@ -891,20 +893,20 @@
hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2;
- }
+ }
else
{
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
hspi->TxXferCount--;
}
-
+
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
}
-
+
/* Wait until RXNE flag is reset */
if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
{
@@ -932,34 +934,42 @@
}
}
}
-
+
/* Read CRC from DR to close CRC calculation process */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until TXE flag */
if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
- {
- /* Erreur on the CRC reception */
+ {
+ /* Error on the CRC reception */
hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
-
+
if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
UNUSED(tmpreg);
}
else
{
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
UNUSED(tmpreg);
+
if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
- {
- /* Erreur on the CRC reception */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ {
+ /* Error on the CRC reception */
hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
- }
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
UNUSED(tmpreg);
}
}
@@ -971,61 +981,67 @@
hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
/* Clear CRC Flag */
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-
- errorcode = HAL_ERROR;
- }
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
+
errorcode = HAL_ERROR;
}
-error :
+ /* Check the end of the transaction */
+ if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error :
hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return errorcode;
}
/**
- * @brief Transmit an amount of data in no-blocking mode with Interrupt
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData : pointer to data buffer
- * @param Size : amount of data to be sent
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
+
/* Process Locked */
__HAL_LOCK(hspi);
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
}
-
+
if(hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
-
- /* prepore the transfer */
+
+ /* prepare the transfer */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t*)NULL;
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
hspi->RxXferSize = 0;
hspi->RxXferCount = 0;
- hspi->RxISR = (void (*)(SPI_HandleTypeDef *))NULL;
+ hspi->RxISR = NULL;
- /* Set the function for IT treatement */
+ /* Set the function for IT treatment */
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
{
hspi->TxISR = SPI_TxISR_16BIT;
@@ -1034,81 +1050,81 @@
{
hspi->TxISR = SPI_TxISR_8BIT;
}
-
+
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_TX(hspi);
+ SPI_1LINE_TX(hspi);
}
-
+
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
-
+
/* Enable TXE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
-
-
- /* Check if the SPI is already enabled */
+
+
+ /* Check if the SPI is already enabled */
if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
{
- /* Enable SPI peripheral */
+ /* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
-
+
error :
__HAL_UNLOCK(hspi);
return errorcode;
}
/**
- * @brief Receive an amount of data in no-blocking mode with Interrupt
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData : pointer to data buffer
- * @param Size : amount of data to be sent
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
-
+
/* Process Locked */
__HAL_LOCK(hspi);
-
+
if(hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
if((pData == NULL) || (Size == 0))
- {
+ {
errorcode = HAL_ERROR;
goto error;
}
-
+
/* Configure communication */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pRxBuffPtr = pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
- hspi->pTxBuffPtr = (uint8_t*)NULL;
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
hspi->TxXferSize = 0;
hspi->TxXferCount = 0;
-
+
if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
/* Process Unlocked */
__HAL_UNLOCK(hspi);
/* the receive process is not supported in 2Lines direction master mode */
- /* in this we call the transmitReceive process */
+ /* in this we call the TransmitReceive process */
return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
}
-
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->CRCSize = 1;
if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
@@ -1120,44 +1136,44 @@
{
hspi->CRCSize = 0;
}
-
- hspi->TxISR = (void (*)(SPI_HandleTypeDef *))NULL;
- /* check the data size to adapt Rx threshold and the set the function for IT treatement */
+
+ hspi->TxISR = NULL;
+ /* check the data size to adapt Rx threshold and the set the function for IT treatment */
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
{
- /* set fiforxthresold according the reception data lenght: 16 bit */
+ /* set fiforxthresold according the reception data length: 16 bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_RxISR_16BIT;
}
else
{
- /* set fiforxthresold according the reception data lenght: 8 bit */
+ /* set fiforxthresold according the reception data length: 8 bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_RxISR_8BIT;
}
-
+
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_RX(hspi);
+ SPI_1LINE_RX(hspi);
}
-
+
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
-
+
/* Enable TXE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Check if the SPI is already enabled */
+
+ /* Check if the SPI is already enabled */
if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
- /* Enable SPI peripheral */
+ /* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
-
+
error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -1165,37 +1181,37 @@
}
/**
- * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData : pointer to transmission data buffer
- * @param pRxData : pointer to reception data buffer to be
- * @param Size : amount of data to be sent
+ * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @param Size: amount of data to be sent and received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
+
/* Process locked */
__HAL_LOCK(hspi);
-
+
if(!((hspi->State == HAL_SPI_STATE_READY) || \
((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
}
-
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
{
- errorcode = HAL_ERROR;
+ errorcode = HAL_ERROR;
goto error;
}
-
+
hspi->CRCSize = 0;
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->CRCSize = 1;
if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
@@ -1203,12 +1219,12 @@
hspi->CRCSize = 2;
}
}
-
+
if(hspi->State != HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
-
+
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = pTxData;
hspi->TxXferSize = Size;
@@ -1216,47 +1232,47 @@
hspi->pRxBuffPtr = pRxData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
-
- /* Set the function for IT treatement */
+
+ /* Set the function for IT treatment */
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
{
hspi->RxISR = SPI_2linesRxISR_16BIT;
- hspi->TxISR = SPI_2linesTxISR_16BIT;
+ hspi->TxISR = SPI_2linesTxISR_16BIT;
}
else
{
hspi->RxISR = SPI_2linesRxISR_8BIT;
hspi->TxISR = SPI_2linesTxISR_8BIT;
}
-
+
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
-
+
/* check if packing mode is enabled and if there is more than 2 data to receive */
if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
{
- /* set fiforxthresold according the reception data lenght: 16 bit */
+ /* set fiforxthresold according the reception data length: 16 bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthresold according the reception data lenght: 8 bit */
+ /* set fiforxthresold according the reception data length: 8 bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
-
+
/* Enable TXE, RXNE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Check if the SPI is already enabled */
+
+ /* Check if the SPI is already enabled */
if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
- /* Enable SPI peripheral */
+ /* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
-
+
error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -1264,63 +1280,63 @@
}
/**
- * @brief Transmit an amount of data in no-blocking mode with DMA
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData : pointer to data buffer
- * @param Size : amount of data to be sent
+ * @brief Transmit an amount of data in non-blocking mode with DMA.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
+{
HAL_StatusTypeDef errorcode = HAL_OK;
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
+
/* Process Locked */
__HAL_LOCK(hspi);
-
- if(hspi->State != HAL_SPI_STATE_READY)
+
+ if(hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
-
+
if((pData == NULL) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
}
-
+
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = (uint8_t*)NULL;
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
hspi->RxXferSize = 0;
hspi->RxXferCount = 0;
-
+
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_TX(hspi);
+ SPI_1LINE_TX(hspi);
}
-
+
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
-
+
/* Set the SPI TxDMA Half transfer complete callback */
hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-
- /* Set the SPI TxDMA transfert complete callback */
+
+ /* Set the SPI TxDMA transfer complete callback */
hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
-
+
/* Set the DMA error callback */
hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
+
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
/* packing mode is enabled only if the DMA setting is HALWORD */
if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
@@ -1337,83 +1353,84 @@
hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
}
}
-
+
/* Enable the Tx DMA channel */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
- /* Check if the SPI is already enabled */
+
+ /* Check if the SPI is already enabled */
if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
{
- /* Enable SPI peripheral */
+ /* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
+
+error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return errorcode;
}
/**
- * @brief Receive an amount of data in no-blocking mode with DMA
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pData : pointer to data buffer
- * @param Size : amount of data to be sent
- * @retval HAL status
- */
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @note When the CRC feature is enabled the pData Length must be Size + 1.
+ * @param Size: amount of data to be sent
+ * @retval HAL status
+ */
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
-
+
/* Process Locked */
__HAL_LOCK(hspi);
-
+
if(hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
-
+
if((pData == NULL) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
}
-
+
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pRxBuffPtr = pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
- hspi->pTxBuffPtr = (uint8_t*)NULL;
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
hspi->TxXferSize = 0;
hspi->TxXferCount = 0;
-
+
if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
/* Process Unlocked */
- __HAL_UNLOCK(hspi);
+ __HAL_UNLOCK(hspi);
/* the receive process is not supported in 2Lines direction master mode */
- /* in this case we call the transmitReceive process */
+ /* in this case we call the TransmitReceive process */
return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
}
-
+
/* Configure communication direction : 1Line */
if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
- __HAL_SPI_1LINE_RX(hspi);
+ SPI_1LINE_RX(hspi);
}
-
+
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
-
+
/* packing mode management is enabled by the DMA settings */
if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
{
@@ -1421,83 +1438,84 @@
errorcode = HAL_ERROR;
goto error;
}
-
+
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- /* set fiforxthresold according the reception data lenght: 16bit */
+ /* set fiforxthresold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthresold according the reception data lenght: 8bit */
+ /* set fiforxthresold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
-
+
/* Set the SPI RxDMA Half transfer complete callback */
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-
- /* Set the SPI Rx DMA transfert complete callback */
+
+ /* Set the SPI Rx DMA transfer complete callback */
hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-
+
/* Set the DMA error callback */
hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Enable Rx DMA Request */
+
+ /* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
+
/* Enable the Rx DMA channel */
HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
- /* Check if the SPI is already enabled */
+
+ /* Check if the SPI is already enabled */
if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
- /* Enable SPI peripheral */
+ /* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
-
+
error:
/* Process Unlocked */
- __HAL_UNLOCK(hspi);
+ __HAL_UNLOCK(hspi);
return errorcode;
}
/**
- * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param pTxData : pointer to transmission data buffer
- * @param pRxData : pointer to reception data buffer
- * @param Size : amount of data to be sent
+ * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1
+ * @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
+
/* Process locked */
__HAL_LOCK(hspi);
-
+
if(!((hspi->State == HAL_SPI_STATE_READY) ||
((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
}
-
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
{
errorcode = HAL_ERROR;
goto error;
}
-
+
/* check if the transmit Receive function is not called by a receive master */
if(hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
+ {
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
-
+
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = (uint8_t *)pTxData;
hspi->TxXferSize = Size;
@@ -1505,27 +1523,27 @@
hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
-
+
/* Reset CRC Calculation + increase the rxsize */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
-
+
/* Reset the threshold bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
-
+
/* the packing mode management is enabled by the DMA settings according the spi data size */
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- /* set fiforxthreshold according the reception data lenght: 16bit */
+ /* set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthresold according the reception data lenght: 8bit */
+ /* set fiforxthresold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
+
if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
{
if((hspi->TxXferSize & 0x1) == 0x0)
@@ -1539,12 +1557,12 @@
hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
}
}
-
+
if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
{
- /* set fiforxthresold according the reception data lenght: 16bit */
+ /* set fiforxthresold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
-
+
if((hspi->RxXferCount & 0x1) == 0x0 )
{
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
@@ -1557,7 +1575,7 @@
}
}
}
-
+
/* Set the SPI Rx DMA transfer complete callback if the transfer request is a
reception request (RXNE) */
if(hspi->State == HAL_SPI_STATE_BUSY_RX)
@@ -1572,86 +1590,87 @@
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
}
-
+
/* Set the DMA error callback */
hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Enable Rx DMA Request */
+
+ /* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
+
/* Enable the Rx DMA channel */
HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
-
+
/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
is performed in DMA reception complete callback */
- hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL;
-
+ hspi->hdmatx->XferHalfCpltCallback = NULL;
+ hspi->hdmatx->XferCpltCallback = NULL;
+
/* Set the DMA error callback */
hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
+
/* Enable the Tx DMA channel */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
+
/* Check if the SPI is already enabled */
if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
-
+
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-error :
+
+error :
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return errorcode;
}
/**
- * @brief Pauses the DMA Transfer.
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
+ * @brief Pause the DMA Transfer.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
{
/* Process Locked */
__HAL_LOCK(hspi);
-
+
/* Disable the SPI DMA Tx & Rx requests */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
+
/* Process Unlocked */
__HAL_UNLOCK(hspi);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief Resumes the DMA Transfer.
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
+ * @brief Resume the DMA Transfer.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
{
/* Process Locked */
__HAL_LOCK(hspi);
-
+
/* Enable the SPI DMA Tx & Rx requests */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
+
/* Process Unlocked */
__HAL_UNLOCK(hspi);
-
+
return HAL_OK;
}
/**
- * @brief Stops the DMA Transfer.
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
+ * @brief Stop the DMA Transfer.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
@@ -1661,7 +1680,7 @@
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
*/
-
+
/* Abort the SPI DMA tx channel */
if(hspi->hdmatx != NULL)
{
@@ -1672,7 +1691,7 @@
{
HAL_DMA_Abort(hspi->hdmarx);
}
-
+
/* Disable the SPI DMA Tx & Rx requests */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
hspi->State = HAL_SPI_STATE_READY;
@@ -1680,16 +1699,16 @@
}
/**
- * @brief This function handles SPI interrupt request.
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval None.
+ * @brief Handle SPI interrupt request.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval None
*/
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
{
uint32_t itsource = hspi->Instance->CR2;
uint32_t itflag = hspi->Instance->SR;
-
+
/* SPI in mode Receiver ----------------------------------------------------*/
if(((itflag & SPI_FLAG_OVR) == RESET) &&
((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
@@ -1697,18 +1716,18 @@
hspi->RxISR(hspi);
return;
}
-
- /* SPI in mode Tramitter ---------------------------------------------------*/
+
+ /* SPI in mode Transmitter ---------------------------------------------------*/
if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
- {
+ {
hspi->TxISR(hspi);
return;
}
-
- /* SPI in Erreur Treatment ---------------------------------------------------*/
- if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
+
+ /* SPI in Error Treatment ---------------------------------------------------*/
+ if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
{
- /* SPI Overrun error interrupt occured -------------------------------------*/
+ /* SPI Overrun error interrupt occurred -------------------------------------*/
if((itflag & SPI_FLAG_OVR) != RESET)
{
if(hspi->State != HAL_SPI_STATE_BUSY_TX)
@@ -1721,21 +1740,21 @@
return;
}
}
-
- /* SPI Mode Fault error interrupt occured -------------------------------------*/
+
+ /* SPI Mode Fault error interrupt occurred -------------------------------------*/
if((itflag & SPI_FLAG_MODF) != RESET)
- {
+ {
hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
__HAL_SPI_CLEAR_MODFFLAG(hspi);
}
-
- /* SPI Frame error interrupt occured ----------------------------------------*/
+
+ /* SPI Frame error interrupt occurred ----------------------------------------*/
if((itflag & SPI_FLAG_FRE) != RESET)
- {
+ {
hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
__HAL_SPI_CLEAR_FREFLAG(hspi);
}
-
+
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_ErrorCallback(hspi);
@@ -1744,154 +1763,135 @@
}
/**
- * @brief Flush the RX fifo.
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
- * @retval HAL status
+ * @brief Tx Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
-HAL_StatusTypeDef HAL_SPI_FlushRxFifo(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
- __IO uint32_t tmpreg;
- uint8_t count = 0;
- while((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
- {
- count++;
- tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg);
- if(count == SPI_FIFO_SIZE)
- {
- return HAL_TIMEOUT;
- }
- };
- return HAL_OK;
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxCpltCallback should be implemented in the user file
+ */
}
/**
- * @brief Tx Transfer completed callbacks
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Rx Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxCpltCallback could be implenetd in the user file
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxCpltCallback should be implemented in the user file
+ */
}
/**
- * @brief Rx Transfer completed callbacks
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
- */
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_RxCpltCallback could be implenetd in the user file
- */
-}
-
-/**
- * @brief Tx and Rx Transfer completed callbacks
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Tx and Rx Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxRxCpltCallback could be implenetd in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxCpltCallback should be implemented in the user file
*/
}
/**
- * @brief Tx Half Transfer completed callbacks
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Tx Half Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
*/
}
/**
- * @brief Rx Half Transfer completed callbacks
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Tx and Rx Half Transfer callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
*/
}
/**
- * @brief Tx and Rx Transfer completed callbacks
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
- */
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
- */
-}
-
-/**
- * @brief SPI error callbacks
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief SPI error callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_ErrorCallback could be implenetd in the user file
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_ErrorCallback should be implemented in the user file
+ */
+ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
+ and user can use HAL_SPI_GetError() API to check the latest error occurred
+ */
}
/**
* @}
*/
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral Control functions
- * @brief SPI control functions
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SPI control functions
*
-@verbatim
+@verbatim
===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to control the SPI.
- (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral.
+ (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
@endverbatim
* @{
*/
/**
- * @brief Return the SPI state
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * @brief Return the SPI handle state.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @retval SPI state
*/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
{
+ /* Return SPI handle state */
return hspi->State;
}
/**
- * @brief Return the SPI error code
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval SPI Error Code
+ * @brief Return the SPI error code.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI error code in bitmap format
*/
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
{
@@ -1907,35 +1907,41 @@
* @}
*/
-/** @addtogroup SPI_Private_Functions SPI Private Functions
- * @brief Data transfers Private functions
+/** @addtogroup SPI_Private_Functions
+ * @brief Private functions
* @{
*/
/**
- * @brief DMA SPI transmit process complete callback
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None.
+ * @brief DMA SPI transmit process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
*/
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
{
/* Disable Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
- /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received data is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
-
+
hspi->TxXferCount = 0;
hspi->State = HAL_SPI_STATE_READY;
-
+
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
@@ -1946,66 +1952,73 @@
}
/**
- * @brief DMA SPI receive process complete callback
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None.
+ * @brief DMA SPI receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
*/
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
{
__IO uint16_t tmpreg;
-
+
/* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until TXE flag */
if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
{
- /* Erreur on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ /* Error on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
}
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
+ {
tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
UNUSED(tmpreg);
}
else
{
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
UNUSED(tmpreg);
+
if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
{
- /* Erreur on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ /* Error on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
}
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
UNUSED(tmpreg);
}
}
}
-
+
/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
/* Check the end of the transaction */
- SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
-
+ if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ }
+
hspi->RxXferCount = 0;
hspi->State = HAL_SPI_STATE_READY;
-
+
/* Check if CRC error occurred */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
-
+
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
@@ -2016,58 +2029,65 @@
}
/**
- * @brief DMA SPI transmit receive process complete callback
+ * @brief DMA SPI transmit receive process complete callback.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None.
+ * the configuration information for the specified DMA module.
+ * @retval None
*/
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
{
__IO int16_t tmpreg;
/* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
- {
+ {
if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
{
- /* Erreur on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ /* Error on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
}
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
UNUSED(tmpreg);
}
else
{
if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
{
- /* Erreur on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ /* Error on the CRC reception */
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
}
tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
UNUSED(tmpreg);
}
- }
-
+ }
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ }
+
/* Disable Rx/Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
hspi->TxXferCount = 0;
hspi->RxXferCount = 0;
hspi->State = HAL_SPI_STATE_READY;
-
+
/* Check if CRC error occurred */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
- hspi->ErrorCode = HAL_SPI_ERROR_CRC;
+ hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
-
+
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
@@ -2078,10 +2098,10 @@
}
/**
- * @brief DMA SPI half transmit process complete callback
+ * @brief DMA SPI half transmit process complete callback.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None.
+ * the configuration information for the specified DMA module.
+ * @retval None
*/
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
{
@@ -2091,10 +2111,10 @@
}
/**
- * @brief DMA SPI half receive process complete callback
+ * @brief DMA SPI half receive process complete callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None.
+ * the configuration information for the specified DMA module.
+ * @retval None
*/
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
{
@@ -2104,12 +2124,12 @@
}
/**
- * @brief DMA SPI Half transmit receive process complete callback
+ * @brief DMA SPI half transmit receive process complete callback.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None.
+ * the configuration information for the specified DMA module.
+ * @retval None
*/
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
@@ -2117,28 +2137,28 @@
}
/**
- * @brief DMA SPI communication error callback
+ * @brief DMA SPI communication error callback.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None.
+ * the configuration information for the specified DMA module.
+ * @retval None
*/
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
{
SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
/* Stop the disable DMA transfer on SPI side */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
+
hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_ErrorCallback(hspi);
}
/**
- * @brief Rx Handler for Transmit and Receive in Interrupt mode
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
@@ -2148,11 +2168,11 @@
*((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount -= 2;
- if(hspi->RxXferCount == 1)
+ if(hspi->RxXferCount == 1)
{
- /* set fiforxthresold according the reception data lenght: 8bit */
- SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- }
+ /* set fiforxthresold according the reception data length: 8bit */
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ }
}
/* Receive data in 8 Bit mode */
else
@@ -2160,19 +2180,20 @@
*hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
hspi->RxXferCount--;
}
-
+
/* check end of the reception */
if(hspi->RxXferCount == 0)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- hspi->RxISR = SPI_2linesRxISR_8BITCRC;
+ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+ hspi->RxISR = SPI_2linesRxISR_8BITCRC;
return;
}
-
+
/* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
if(hspi->TxXferCount == 0)
{
SPI_CloseRxTx_ISR(hspi);
@@ -2181,23 +2202,25 @@
}
/**
- * @brief Rx Handler for Transmit and Receive in Interrupt mode
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
__IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
UNUSED(tmpreg);
+
hspi->CRCSize--;
-
+
/* check end of the reception */
if(hspi->CRCSize == 0)
{
/* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
if(hspi->TxXferCount == 0)
{
SPI_CloseRxTx_ISR(hspi);
@@ -2206,10 +2229,10 @@
}
/**
- * @brief Tx Handler for Transmit and Receive in Interrupt mode
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
@@ -2222,52 +2245,52 @@
}
/* Transmit data in 8 Bit mode */
else
- {
+ {
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
hspi->TxXferCount--;
}
-
+
/* check the end of the transmission */
if(hspi->TxXferCount == 0)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
+
if(hspi->RxXferCount == 0)
- {
+ {
SPI_CloseRxTx_ISR(hspi);
}
}
}
/**
- * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 16 Bit mode */
*((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
-
+ hspi->RxXferCount--;
+
if(hspi->RxXferCount == 0)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- hspi->RxISR = SPI_2linesRxISR_16BITCRC;
+ hspi->RxISR = SPI_2linesRxISR_16BITCRC;
return;
}
-
+
/* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
if(hspi->TxXferCount == 0)
{
SPI_CloseRxTx_ISR(hspi);
@@ -2276,28 +2299,29 @@
}
/**
- * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 16 Bit mode */
__IO uint16_t tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
UNUSED(tmpreg);
-
+
/* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
SPI_CloseRxTx_ISR(hspi);
}
/**
- * @brief Tx Handler for Transmit and Receive in Interrupt mode
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
@@ -2305,64 +2329,66 @@
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
-
+
/* Enable CRC Transmission */
if(hspi->TxXferCount == 0)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
-
+
if(hspi->RxXferCount == 0)
- {
+ {
SPI_CloseRxTx_ISR(hspi);
}
}
}
/**
- * @brief Manage the CRC receive in Interrupt context
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Manage the CRC 8-bit receive in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg = *((uint8_t*)&hspi->Instance->DR);
+ __IO uint8_t tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
+ /* To avoid GCC warning */
UNUSED(tmpreg);
+
hspi->CRCSize--;
-
+
if(hspi->CRCSize == 0)
- {
+ {
SPI_CloseRx_ISR(hspi);
}
}
/**
- * @brief Manage the recieve in Interrupt context
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Manage the receive 8-bit in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
*hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
hspi->RxXferCount--;
-
+
/* Enable CRC Transmission */
- if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
-
+
if(hspi->RxXferCount == 0)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- hspi->RxISR = SPI_RxISR_8BITCRC;
+ hspi->RxISR = SPI_RxISR_8BITCRC;
return;
}
SPI_CloseRx_ISR(hspi);
@@ -2370,45 +2396,46 @@
}
/**
- * @brief Manage the CRC 16bit recieve in Interrupt context
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Manage the CRC 16-bit receive in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
__IO uint16_t tmpreg;
-
+
tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
UNUSED(tmpreg);
-
+
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
+
SPI_CloseRx_ISR(hspi);
}
/**
- * @brief Manage the 16Bit recieve in Interrupt context
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Manage the 16-bit receive in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
*((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
-
+
/* Enable CRC Transmission */
- if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
+ if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
}
-
+
if(hspi->RxXferCount == 0)
- {
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ {
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_RxISR_16BITCRC;
return;
@@ -2418,19 +2445,19 @@
}
/**
- * @brief Handle the data 8Bit transmit in Interrupt mode
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Handle the data 8-bit transmit in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
hspi->TxXferCount--;
-
+
if(hspi->TxXferCount == 0)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Enable CRC Transmission */
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
@@ -2440,21 +2467,21 @@
}
/**
- * @brief Handle the data 16Bit transmit in Interrupt mode
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Handle the data 16-bit transmit in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
-{
+{
/* Transmit data in 16 Bit mode */
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
-
+
if(hspi->TxXferCount == 0)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Enable CRC Transmission */
hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
@@ -2464,9 +2491,9 @@
}
/**
- * @brief This function handles SPI Communication Timeout.
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param Flag : SPI flag to check
* @param State : flag state to check
* @param Timeout : Timeout duration
@@ -2475,7 +2502,7 @@
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
-
+
while((hspi->Instance->SR & Flag) != State)
{
if(Timeout != HAL_MAX_DELAY)
@@ -2485,39 +2512,39 @@
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
-
+
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
+
if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
-
+
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
-
+
hspi->State= HAL_SPI_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hspi);
-
+
return HAL_TIMEOUT;
}
}
}
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief This function handles SPI Communication Timeout.
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * @brief Handle SPI FIFO Communication Timeout.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
* @param Fifo : Fifo to check
* @param State : Fifo state to check
* @param Timeout : Timeout duration
@@ -2533,9 +2560,10 @@
if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
{
tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
+ /* To avoid GCC warning */
UNUSED(tmpreg);
}
-
+
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
@@ -2543,40 +2571,40 @@
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
-
+
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
+
if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
-
+
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- __HAL_SPI_RESET_CRC(hspi);
+ SPI_RESET_CRC(hspi);
}
-
+
hspi->State = HAL_SPI_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hspi);
-
+
return HAL_TIMEOUT;
}
}
}
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief This function handles the check of the RX transaction complete.
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Timeout : Timeout duration
+ * @brief Handle the check of the RX transaction complete.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Timeout : Timeout duration
* @retval None.
*/
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
@@ -2585,32 +2613,66 @@
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
-
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- return HAL_TIMEOUT;
- }
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
+ }
+
+ /* Control the BSY flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ return HAL_TIMEOUT;
+ }
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Empty the FRLVL fifo */
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
{
hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
return HAL_TIMEOUT;
}
- }
+ }
return HAL_OK;
}
-
+
/**
- * @brief This function handles the close of the RXTX transaction.
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Handle the check of the RXTX or TX transaction complete.
+ * @param hspi: SPI handle
+ * @param Timeout : Timeout duration
+ */
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
+{
+ /* Control if the TX fifo is empty */
+ if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ return HAL_TIMEOUT;
+ }
+ /* Control the BSY flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ {
+ hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ return HAL_TIMEOUT;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the end of the RXTX transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
{
/* Disable ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
-
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ }
+
/* Check if CRC error occurred */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
@@ -2632,7 +2694,7 @@
{
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_TxRxCpltCallback(hspi);
- }
+ }
}
else
{
@@ -2643,33 +2705,35 @@
}
/**
- * @brief This function handles the close of the RX transaction.
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Handle the end of the RX transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
{
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
+
/* Check the end of the transaction */
- SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
-
- hspi->State = HAL_SPI_STATE_READY;
-
+ if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ }
+ hspi->State = HAL_SPI_STATE_READY;
+
/* Check if CRC error occurred */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- HAL_SPI_ErrorCallback(hspi);
+ HAL_SPI_ErrorCallback(hspi);
}
else
{
if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
- HAL_SPI_RxCpltCallback(hspi);
+ HAL_SPI_RxCpltCallback(hspi);
}
else
{
@@ -2679,22 +2743,28 @@
}
/**
- * @brief This function handles the close of the TX transaction.
- * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None.
+ * @brief Handle the end of the TX transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
{
/* Disable TXE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-
- /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+
+ /* Check the end of the transaction */
+ if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ {
+ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
-
+
hspi->State = HAL_SPI_STATE_READY;
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
@@ -2711,6 +2781,7 @@
*/
#endif /* HAL_SPI_MODULE_ENABLED */
+
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_spi.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -32,7 +32,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -52,26 +52,26 @@
/** @addtogroup SPI
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup SPI_Exported_Types SPI Exported Types
* @{
*/
-/**
- * @brief SPI Configuration Structure definition
+/**
+ * @brief SPI Configuration Structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the SPI operating mode.
- This parameter can be a value of @ref SPI_mode */
+ This parameter can be a value of @ref SPI_Mode */
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
This parameter can be a value of @ref SPI_Direction */
uint32_t DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_data_size */
+ This parameter can be a value of @ref SPI_Data_Size */
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
@@ -91,7 +91,7 @@
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
+
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .
This parameter can be a value of @ref SPI_TI_mode */
@@ -101,75 +101,74 @@
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
- uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
- CRC Length is only used with Data8 and Data16, not other data size
- This parameter must 0 or 1 or 2*/
+ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
+ CRC Length is only used with Data8 and Data16, not other data size
+ This parameter can be a value of @ref SPI_CRC_length */
uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
This parameter can be a value of @ref SPI_NSSP_Mode
- This mode is activated by the NSSP bit in the SPIx_CR2 register and
- it takes effect only if the SPI interface is configured as Motorola SPI
- master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
+ This mode is activated by the NSSP bit in the SPIx_CR2 register and
+ it takes effect only if the SPI interface is configured as Motorola SPI
+ master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
CPOL setting is ignored).. */
} SPI_InitTypeDef;
-/**
- * @brief HAL State structures definition
- */
+/**
+ * @brief HAL State structures definition
+ */
typedef enum
{
HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */
HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */
}HAL_SPI_StateTypeDef;
-/**
- * @brief SPI handle Structure definition
- */
+/**
+ * @brief SPI handle Structure definition
+ */
typedef struct __SPI_HandleTypeDef
{
- SPI_TypeDef *Instance; /*!< SPI registers base address */
-
- SPI_InitTypeDef Init; /*!< SPI communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SPI Tx Transfer size */
-
- uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
+ SPI_TypeDef *Instance; /* SPI registers base address */
+
+ SPI_InitTypeDef Init; /* SPI communication parameters */
+
+ uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /* SPI Tx Transfer size */
+
+ uint16_t TxXferCount; /* SPI Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
+
+ uint16_t RxXferSize; /* SPI Rx Transfer size */
+
+ uint16_t RxXferCount; /* SPI Rx Transfer Counter */
- uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< SPI Rx Transfer size */
-
- uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
-
- uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
+ uint32_t CRCSize; /* SPI CRC size used for the transfer */
+
+ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */
+
+ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */
+
+ DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
- void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx IRQ handler */
-
- void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx IRQ handler */
+ DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
- DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
+ HAL_LockTypeDef Lock; /* Locking object */
- DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
- HAL_SPI_StateTypeDef State; /*!< SPI communication state */
-
- __IO uint32_t ErrorCode; /*!< SPI Error code
- This parameter can be a value of @ref SPI_Error */
+ uint32_t ErrorCode; /* SPI Error code */
}SPI_HandleTypeDef;
/**
* @}
- */
+ */
/* Exported constants --------------------------------------------------------*/
@@ -177,24 +176,25 @@
* @{
*/
-/** @defgroup SPI_Error SPI Error
+/** @defgroup SPI_Error_Code SPI Error Code
* @{
- */
- #define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
- #define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001) /*!< MODF error */
- #define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002) /*!< CRC error */
- #define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004) /*!< OVR error */
- #define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008) /*!< FRE error */
- #define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
- #define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020) /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
- #define HAL_SPI_ERROR_UNKNOW ((uint32_t)0x00000040) /*!< Unknow Error error */
+ */
+#define HAL_SPI_ERROR_NONE (uint32_t)0x00000000 /*!< No error */
+#define HAL_SPI_ERROR_MODF (uint32_t)0x00000001 /*!< MODF error */
+#define HAL_SPI_ERROR_CRC (uint32_t)0x00000002 /*!< CRC error */
+#define HAL_SPI_ERROR_OVR (uint32_t)0x00000004 /*!< OVR error */
+#define HAL_SPI_ERROR_FRE (uint32_t)0x00000008 /*!< FRE error */
+#define HAL_SPI_ERROR_DMA (uint32_t)0x00000010 /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG (uint32_t)0x00000020 /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040 /*!< Unknown error */
/**
* @}
*/
-/** @defgroup SPI_mode SPI mode
+
+/** @defgroup SPI_Mode SPI Mode
* @{
- */
+ */
#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
@@ -203,12 +203,12 @@
* @}
*/
-/** @defgroup SPI_Direction SPI Direction
+/** @defgroup SPI_Direction SPI Direction Mode
* @{
*/
-#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
-#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
+#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
@@ -221,23 +221,23 @@
/**
* @}
*/
-
-/** @defgroup SPI_data_size SPI Data size
+
+/** @defgroup SPI_Data_Size SPI Data Size
* @{
*/
-#define SPI_DATASIZE_4BIT ((uint32_t)0x0300) /*!< SPI Datasize = 4bits */
-#define SPI_DATASIZE_5BIT ((uint32_t)0x0400) /*!< SPI Datasize = 5bits */
-#define SPI_DATASIZE_6BIT ((uint32_t)0x0500) /*!< SPI Datasize = 6bits */
-#define SPI_DATASIZE_7BIT ((uint32_t)0x0600) /*!< SPI Datasize = 7bits */
-#define SPI_DATASIZE_8BIT ((uint32_t)0x0700) /*!< SPI Datasize = 8bits */
-#define SPI_DATASIZE_9BIT ((uint32_t)0x0800) /*!< SPI Datasize = 9bits */
-#define SPI_DATASIZE_10BIT ((uint32_t)0x0900) /*!< SPI Datasize = 10bits */
-#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00) /*!< SPI Datasize = 11bits */
-#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00) /*!< SPI Datasize = 12bits */
-#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00) /*!< SPI Datasize = 13bits */
-#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) /*!< SPI Datasize = 14bits */
-#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) /*!< SPI Datasize = 15bits */
-#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) /*!< SPI Datasize = 16bits */
+#define SPI_DATASIZE_4BIT ((uint32_t)0x0300) /*!< SPI Datasize = 4bits */
+#define SPI_DATASIZE_5BIT ((uint32_t)0x0400) /*!< SPI Datasize = 5bits */
+#define SPI_DATASIZE_6BIT ((uint32_t)0x0500) /*!< SPI Datasize = 6bits */
+#define SPI_DATASIZE_7BIT ((uint32_t)0x0600) /*!< SPI Datasize = 7bits */
+#define SPI_DATASIZE_8BIT ((uint32_t)0x0700) /*!< SPI Datasize = 8bits */
+#define SPI_DATASIZE_9BIT ((uint32_t)0x0800) /*!< SPI Datasize = 9bits */
+#define SPI_DATASIZE_10BIT ((uint32_t)0x0900) /*!< SPI Datasize = 10bits */
+#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00) /*!< SPI Datasize = 11bits */
+#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00) /*!< SPI Datasize = 12bits */
+#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00) /*!< SPI Datasize = 13bits */
+#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) /*!< SPI Datasize = 14bits */
+#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) /*!< SPI Datasize = 15bits */
+#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) /*!< SPI Datasize = 16bits */
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
((DATASIZE) == SPI_DATASIZE_15BIT) || \
((DATASIZE) == SPI_DATASIZE_14BIT) || \
@@ -251,14 +251,13 @@
((DATASIZE) == SPI_DATASIZE_6BIT) || \
((DATASIZE) == SPI_DATASIZE_5BIT) || \
((DATASIZE) == SPI_DATASIZE_4BIT))
-
/**
* @}
- */
+ */
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
- */
+ */
#define SPI_POLARITY_LOW ((uint32_t)0x00000000) /*!< SPI polarity Low */
#define SPI_POLARITY_HIGH SPI_CR1_CPOL /*!< SPI polarity High */
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
@@ -280,7 +279,7 @@
/** @defgroup SPI_Slave_Select_management SPI Slave Select management
* @{
- */
+ */
#define SPI_NSS_SOFT SPI_CR1_SSM
#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
@@ -290,19 +289,19 @@
/**
* @}
*/
-
-/** @defgroup SPI_NSSP_Mode SPI NSS pulse management
+
+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
* @{
- */
-#define SPI_NSS_PULSE_ENABLED SPI_CR2_NSSP
-#define SPI_NSS_PULSE_DISABLED ((uint32_t)0x00000000)
+ */
+#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
+#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)
-#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLED) || \
- ((NSSP) == SPI_NSS_PULSE_DISABLED))
+#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
+ ((NSSP) == SPI_NSS_PULSE_DISABLE))
/**
* @}
*/
-
+
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
@@ -324,11 +323,11 @@
((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
/**
* @}
- */
+ */
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
* @{
- */
+ */
#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
@@ -340,53 +339,53 @@
/** @defgroup SPI_TI_mode SPI TI mode
* @{
*/
-#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
-#define SPI_TIMODE_ENABLED SPI_CR2_FRF
-#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
- ((MODE) == SPI_TIMODE_ENABLED))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
- * @{
- */
-#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
-#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
- ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
+#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
+#define SPI_TIMODE_ENABLE SPI_CR2_FRF
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
+ ((MODE) == SPI_TIMODE_ENABLE))
/**
* @}
*/
-/** @defgroup SPI_CRC_length SPI CRC length
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
+ * @{
+ */
+#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_length SPI CRC Length
* @{
* This parameter can be one of the following values:
- * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
+ * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
* SPI_CRC_LENGTH_8BIT : CRC 8bit
- * SPI_CRC_LENGTH_16BIT : CRC 16bit
+ * SPI_CRC_LENGTH_16BIT : CRC 16bit
*/
-#define SPI_CRC_LENGTH_DATASIZE 0
-#define SPI_CRC_LENGTH_8BIT 1
-#define SPI_CRC_LENGTH_16BIT 2
+#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)
+#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)
+#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)
#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
((LENGTH) == SPI_CRC_LENGTH_16BIT))
/**
* @}
*/
-
-/** @defgroup SPI_FIFO_reception_threshold SPI FIFO reception threshold
+
+/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
* @{
* This parameter can be one of the following values:
* SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
- * RXNE event is generated if the FIFO
- * level is greater or equal to 1/2(16-bits).
- * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
+ * RXNE event is generated if the FIFO
+ * level is greater or equal to 1/2(16-bits).
+ * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
* level is greater or equal to 1/4(8 bits). */
-#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x0)
+#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000)
/**
* @}
@@ -411,8 +410,8 @@
* Elements values convention: 0xXXXXYYYY
* - XXXX : Flag register Index
* - YYYY : Flag mask
- * @{
- */
+ * @{
+ */
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
@@ -426,25 +425,25 @@
* @}
*/
-/** @defgroup SPI_transmission_fifo_status_level SPI transmission fifo status level
+/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
* @{
- */
+ */
#define SPI_FTLVL_EMPTY ((uint32_t)0x0000)
-#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
-#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
+#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
+#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
#define SPI_FTLVL_FULL ((uint32_t)0x1800)
/**
* @}
- */
+ */
-/** @defgroup SPI_reception_fifo_status_level SPI reception fifo status level
+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
* @{
- */
+ */
#define SPI_FRLVL_EMPTY ((uint32_t)0x0000)
-#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
-#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
-#define SPI_FRLVL_FULL ((uint32_t)0x0600)
+#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
+#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
+#define SPI_FRLVL_FULL ((uint32_t)0x0600)
/**
* @}
*/
@@ -453,22 +452,21 @@
* @}
*/
-
/* Exported macros ------------------------------------------------------------*/
/** @defgroup SPI_Exported_Macros SPI Exported Macros
* @{
*/
-
-/** @brief Reset SPI handle state
+
+/** @brief Reset SPI handle state.
* @param __HANDLE__: SPI handle.
* @retval None
*/
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-/** @brief Enables or disables the specified SPI interrupts.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Enable or disable the specified SPI interrupts.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ : specifies the interrupt source to enable or disable.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
@@ -477,11 +475,11 @@
*/
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
-
-/** @brief Checks if the specified SPI interrupt source is enabled or disabled.
- * @param __HANDLE__ : specifies the SPI Handle.
+
+/** @brief Check whether the specified SPI interrupt source is enabled or not.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ : specifies the SPI interrupt source to check.
+ * @param __INTERRUPT__: specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
@@ -490,10 +488,10 @@
*/
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-/** @brief Checks whether the specified SPI flag is set or not.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __FLAG__ : specifies the flag to check.
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
@@ -501,111 +499,127 @@
* @arg SPI_FLAG_MODF: Mode fault flag
* @arg SPI_FLAG_OVR: Overrun flag
* @arg SPI_FLAG_BSY: Busy flag
- * @arg SPI_FLAG_FRE: Frame format error flag
+ * @arg SPI_FLAG_FRE: Frame format error flag
* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
- * @arg SPI_FLAG_FRLVL: SPI fifo reception level
+ * @arg SPI_FLAG_FRLVL: SPI fifo reception level
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-/** @brief Clears the SPI CRCERR pending flag.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Clear the SPI CRCERR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
-
-/** @brief Clears the SPI MODF pending flag.
- * @param __HANDLE__ : specifies the SPI Handle.
+
+/** @brief Clear the SPI MODF pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- *
+ *
* @retval None
- */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{\
- __IO uint32_t tmpreg;\
- tmpreg = (__HANDLE__)->Instance->SR;\
- UNUSED(tmpreg); \
- (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);\
- }while(0)
+ */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
+ UNUSED(tmpreg); \
+ } while(0)
-/** @brief Clears the SPI OVR pending flag.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Clear the SPI OVR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- *
+ *
* @retval None
- */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg); \
- } while(0)
-
-/** @brief Clears the SPI FRE pending flag.
- * @param __HANDLE__ : specifies the SPI Handle.
+ */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Clear the SPI FRE pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- *
+ *
* @retval None
- */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) do{\
- __IO uint32_t tmpreg;\
- tmpreg = ((__HANDLE__)->Instance->SR);\
- UNUSED(tmpreg); \
- }while(0)
-/** @brief Enables the SPI.
- * @param __HANDLE__ : specifies the SPI Handle.
+ */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0)
+
+/** @brief Enable the SPI peripheral.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
-/** @brief Disables the SPI.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Disable the SPI peripheral.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
-/** @brief Sets the SPI transmit-only mode.
- * @param __HANDLE__ : specifies the SPI Handle.
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+
+/** @brief Set the SPI transmit-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
-
-/** @brief Sets the SPI receive-only mode.
- * @param __HANDLE__ : specifies the SPI Handle.
+#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+
+/** @brief Set the SPI receive-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
-
-/** @brief Resets the CRC calculation of the SPI.
- * @param __HANDLE__ : specifies the SPI Handle.
+#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
+
+/** @brief Reset the CRC calculation of the SPI.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
- (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
+ (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
+
+
/**
* @}
*/
-
+
+/* Include SPI HAL Extended module */
+#include "stm32f0xx_hal_spi_ex.h"
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPI_Exported_Functions
* @{
*/
-/** @addtogroup SPI_Exported_Functions_Group1
+/* Initialization and de-initialization functions ****************************/
+/** @addtogroup SPI_Exported_Functions_Group1
* @{
*/
-
-/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_InitExtended(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
@@ -613,11 +627,10 @@
* @}
*/
+/* IO operation functions *****************************************************/
/** @addtogroup SPI_Exported_Functions_Group2
* @{
*/
-
-/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
@@ -630,7 +643,6 @@
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_FlushRxFifo(SPI_HandleTypeDef *hspi);
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
@@ -644,13 +656,12 @@
* @}
*/
+/* Peripheral State and Error functions ***************************************/
/** @addtogroup SPI_Exported_Functions_Group3
* @{
*/
-
-/* Peripheral State and Error functions ***************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
/**
* @}
*/
@@ -658,14 +669,14 @@
/**
* @}
*/
-
-/**
- * @}
- */
/**
* @}
- */
+ */
+
+/**
+ * @}
+ */
#ifdef __cplusplus
}
@@ -674,4 +685,3 @@
#endif /* __STM32F0xx_HAL_SPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.c Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,133 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_spi_ex.c
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 26-June-2015
+ * @brief Extended SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * SPI peripheral extended functionalities :
+ * + IO operation functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPIEx SPIEx
+ * @brief SPI Extended HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
+ * @{
+ */
+#define SPI_FIFO_SIZE 4
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
+ * @{
+ */
+
+/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of extended functions to manage the SPI
+ data transfers.
+
+ (#) Rx data flush function:
+ (++) HAL_SPIEx_FlushRxFifo()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Flush the RX fifo.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t tmpreg;
+ uint8_t count = 0;
+ while((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
+ {
+ count++;
+ tmpreg = hspi->Instance->DR;
+ UNUSED(tmpreg); /* To avoid GCC warning */
+ if(count == SPI_FIFO_SIZE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,93 @@
+ /**
+ ******************************************************************************
+ * @file stm32f0xx_hal_spi_ex.h
+ * @author MCD Application Team
+ * @version V1.3.0
+ * @date 26-June-2015
+ * @brief Header file of SPI HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F0xx_HAL_SPI_EX_H
+#define __STM32F0xx_HAL_SPI_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPIEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPIEx_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/* IO operation functions *****************************************************/
+/** @addtogroup SPIEx_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0xx_HAL_SPI_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_tim.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -35,7 +35,7 @@
==============================================================================
##### TIMER Generic features #####
==============================================================================
- [..] The Timer features include:
+ [..] The Timer features include:
(#) 16-bit up, down, up/down auto-reload counter.
(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
counter clock frequency either by any factor between 1 and 65536.
@@ -43,32 +43,32 @@
(++) Input Capture
(++) Output Compare
(++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
-
+ (++) One-pulse mode output
+
##### How to use this driver #####
==============================================================================
[..]
(#) Initialize the TIM low level resources by implementing the following functions
depending from feature used :
- (++) Time Base : HAL_TIM_Base_MspInit()
+ (++) Time Base : HAL_TIM_Base_MspInit()
(++) Input Capture : HAL_TIM_IC_MspInit()
(++) Output Compare : HAL_TIM_OC_MspInit()
(++) PWM generation : HAL_TIM_PWM_MspInit()
(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-
+
(#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
(##) TIM pins configuration
(+++) Enable the clock for the TIM GPIOs using the following function:
- __GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
(#) The external Clock can be configured, if needed (the default clock is the
internal clock from the APBx), using the following function:
HAL_TIM_ConfigClockSource, the clock configuration should be done before
any start function.
-
+
(#) Configure the TIM in the desired functioning mode using one of the
Initialization function of this driver:
(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
@@ -82,7 +82,7 @@
in One Pulse Mode.
(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
- (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
@@ -93,12 +93,12 @@
(#) The DMA Burst is managed with the two following functions:
HAL_TIM_DMABurst_WriteStart()
HAL_TIM_DMABurst_ReadStart()
-
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -122,8 +122,8 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
- */
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@@ -132,7 +132,7 @@
* @{
*/
-/** @defgroup TIM TIM HAL module driver
+/** @defgroup TIM TIM
* @brief TIM HAL module driver
* @{
*/
@@ -180,13 +180,13 @@
/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
* @brief Time Base functions
*
-@verbatim
+@verbatim
==============================================================================
##### Time Base functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM base.
+ (+) Initialize and configure the TIM base.
(+) De-initialize the TIM base.
(+) Start the Time Base.
(+) Stop the Time Base.
@@ -194,7 +194,7 @@
(+) Stop the Time Base and disable interrupt.
(+) Start the Time Base and enable DMA transfer.
(+) Stop the Time Base and disable DMA transfer.
-
+
@endverbatim
* @{
*/
@@ -205,33 +205,36 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
+{
/* Check the TIM handle allocation */
if(htim == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
+
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
}
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
+
/* Set the Time Base configuration */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
/* Initialize the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
return HAL_OK;
}
@@ -244,18 +247,18 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
/* Release Lock */
__HAL_UNLOCK(htim);
@@ -296,16 +299,16 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Change the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -319,16 +322,16 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -342,13 +345,13 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -364,10 +367,10 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Disable the TIM Update interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -380,40 +383,40 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
+{
/* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((pData == 0 ) && (Length > 0))
+ if((pData == 0 ) && (Length > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
+ }
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
-
+
/* Enable the TIM Update DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
+ __HAL_TIM_ENABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -427,16 +430,16 @@
{
/* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
+
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -444,17 +447,17 @@
/**
* @}
*/
-
+
/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
* @brief Time Output Compare functions
*
-@verbatim
+@verbatim
==============================================================================
##### Time Output Compare functions #####
==============================================================================
[..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM Output Compare.
+ (+) Initialize and configure the TIM Output Compare.
(+) De-initialize the TIM Output Compare.
(+) Start the Time Output Compare.
(+) Stop the Time Output Compare.
@@ -462,7 +465,7 @@
(+) Stop the Time Output Compare and disable interrupt.
(+) Start the Time Output Compare and enable DMA transfer.
(+) Stop the Time Output Compare and disable DMA transfer.
-
+
@endverbatim
* @{
*/
@@ -484,22 +487,25 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
+
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspInit(htim);
}
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
- /* Init the base time for the Output Compare */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
+ /* Init the base time for the Output Compare */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
/* Initialize the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
return HAL_OK;
}
@@ -512,18 +518,18 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
/* Release Lock */
__HAL_UNLOCK(htim);
@@ -556,32 +562,32 @@
/**
* @brief Starts the TIM Output Compare signal generation.
- * @param htim : TIM Output Compare handle
+ * @param htim : TIM Output Compare handle
* @param Channel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
-
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
+ __HAL_TIM_ENABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -601,22 +607,22 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
- }
-
+ }
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode.
@@ -633,45 +639,45 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
break;
- }
+ }
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -679,7 +685,7 @@
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -699,53 +705,53 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
- break;
- }
-
+ break;
+ }
+
/* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -767,104 +773,104 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0 ) && (Length > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
+
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
+
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
+
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
}
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
- }
-
+ }
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
+ __HAL_TIM_ENABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -884,56 +890,56 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
- }
-
+ }
+
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -945,13 +951,13 @@
/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
* @brief Time PWM functions
*
-@verbatim
+@verbatim
==============================================================================
##### Time PWM functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM OPWM.
+ (+) Initialize and configure the TIM OPWM.
(+) De-initialize the TIM PWM.
(+) Start the Time PWM.
(+) Stop the Time PWM.
@@ -959,7 +965,7 @@
(+) Stop the Time PWM and disable interrupt.
(+) Start the Time PWM and enable DMA transfer.
(+) Stop the Time PWM and disable DMA transfer.
-
+
@endverbatim
* @{
*/
@@ -984,19 +990,22 @@
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
}
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the PWM */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
+
+ /* Init the base time for the PWM */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
/* Initialize the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
return HAL_OK;
}
@@ -1009,18 +1018,18 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
/* Release Lock */
__HAL_UNLOCK(htim);
@@ -1066,22 +1075,22 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Stops the PWM signal generation.
@@ -1095,28 +1104,28 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
+{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Starts the PWM signal generation in interrupt mode.
@@ -1133,45 +1142,45 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
break;
- }
-
+ }
+
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -1179,10 +1188,10 @@
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Stops the PWM signal generation in interrupt mode.
@@ -1199,56 +1208,56 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
- break;
+ break;
}
-
+
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Starts the TIM PWM signal generation in DMA mode.
@@ -1267,104 +1276,104 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0 ) && (Length > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
+
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
+
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+
/* Enable the TIM Output Capture/Compare 3 request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
+
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
}
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
-
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
+ __HAL_TIM_ENABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -1384,56 +1393,56 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
- }
-
+ }
+
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -1445,13 +1454,13 @@
/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
* @brief Time Input Capture functions
*
-@verbatim
+@verbatim
==============================================================================
##### Time Input Capture functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM Input Capture.
+ (+) Initialize and configure the TIM Input Capture.
(+) De-initialize the TIM Input Capture.
(+) Start the Time Input Capture.
(+) Stop the Time Input Capture.
@@ -1459,7 +1468,7 @@
(+) Stop the Time Input Capture and disable interrupt.
(+) Start the Time Input Capture and enable DMA transfer.
(+) Stop the Time Input Capture and disable DMA transfer.
-
+
@endverbatim
* @{
*/
@@ -1480,23 +1489,26 @@
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspInit(htim);
}
-
+
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the input capture */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the input capture */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
/* Initialize the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
return HAL_OK;
}
@@ -1509,18 +1521,18 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspDeInit(htim);
-
- /* Change TIM state */
+
+ /* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
-
+
/* Release Lock */
__HAL_UNLOCK(htim);
@@ -1566,16 +1578,16 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ __HAL_TIM_ENABLE(htim);
/* Return function status */
- return HAL_OK;
-}
+ return HAL_OK;
+}
/**
* @brief Stops the TIM Input Capture measurement.
@@ -1589,16 +1601,16 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
+{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
/* Disable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -1618,49 +1630,49 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
break;
- }
+ }
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ __HAL_TIM_ENABLE(htim);
/* Return function status */
- return HAL_OK;
-}
+ return HAL_OK;
+}
/**
* @brief Stops the TIM Input Capture measurement in interrupt mode.
@@ -1677,47 +1689,47 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
- break;
- }
-
+ break;
+ }
+
/* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -1740,99 +1752,99 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((pData == 0 ) && (Length > 0))
+ if((pData == 0 ) && (Length > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
-
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
-
+
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
-
+
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
-
+
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
}
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
+ __HAL_TIM_ENABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -1853,50 +1865,50 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
}
/* Disable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -1907,13 +1919,13 @@
/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
* @brief Time One Pulse functions
*
-@verbatim
+@verbatim
==============================================================================
##### Time One Pulse functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM One Pulse.
+ (+) Initialize and configure the TIM One Pulse.
(+) De-initialize the TIM One Pulse.
(+) Start the Time One Pulse.
(+) Stop the Time One Pulse.
@@ -1921,7 +1933,7 @@
(+) Stop the Time One Pulse and disable interrupt.
(+) Start the Time One Pulse and enable DMA transfer.
(+) Stop the Time One Pulse and disable DMA transfer.
-
+
@endverbatim
* @{
*/
@@ -1948,33 +1960,36 @@
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
-
+
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OnePulse_MspInit(htim);
}
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
+
/* Configure the Time base in the One Pulse Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
+
/* Reset the OPM Bit */
htim->Instance->CR1 &= ~TIM_CR1_OPM;
/* Configure the OPM Mode */
htim->Instance->CR1 |= OnePulseMode;
-
+
/* Initialize the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
return HAL_OK;
}
/**
- * @brief DeInitializes the TIM One Pulse
+ * @brief DeInitializes the TIM One Pulse
* @param htim : TIM One Pulse handle
* @retval HAL status
*/
@@ -1982,18 +1997,18 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_OnePulse_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
/* Release Lock */
__HAL_UNLOCK(htim);
@@ -2040,19 +2055,19 @@
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
+
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
-
+
/* Return function status */
return HAL_OK;
}
@@ -2073,19 +2088,19 @@
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -2106,25 +2121,25 @@
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
+
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
-
+
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
+
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
-
+
/* Return function status */
return HAL_OK;
}
@@ -2141,28 +2156,28 @@
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
+
/* Disable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -2174,13 +2189,13 @@
/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
* @brief Time Encoder functions
*
-@verbatim
+@verbatim
==============================================================================
##### Time Encoder functions #####
==============================================================================
[..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM Encoder.
+ (+) Initialize and configure the TIM Encoder.
(+) De-initialize the TIM Encoder.
(+) Start the Time Encoder.
(+) Stop the Time Encoder.
@@ -2188,7 +2203,7 @@
(+) Stop the Time Encoder and disable interrupt.
(+) Start the Time Encoder and enable DMA transfer.
(+) Stop the Time Encoder and disable DMA transfer.
-
+
@endverbatim
* @{
*/
@@ -2203,13 +2218,13 @@
uint32_t tmpsmcr = 0;
uint32_t tmpccmr1 = 0;
uint32_t tmpccer = 0;
-
+
/* Check the TIM handle allocation */
if(htim == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
@@ -2223,20 +2238,23 @@
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
}
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
+
/* Reset the SMS bits */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-
+
/* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
@@ -2252,7 +2270,7 @@
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
-
+
/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
@@ -2263,7 +2281,7 @@
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
-
+
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
@@ -2272,16 +2290,16 @@
/* Write to TIMx CCER */
htim->Instance->CCER = tmpccer;
-
+
/* Initialize the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
return HAL_OK;
}
/**
- * @brief DeInitializes the TIM Encoder interface
+ * @brief DeInitializes the TIM Encoder interface
* @param htim : TIM Encoder handle
* @retval HAL status
*/
@@ -2289,18 +2307,18 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_Encoder_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
/* Release Lock */
__HAL_UNLOCK(htim);
@@ -2338,36 +2356,37 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
/* Enable the encoder interface channels */
switch (Channel)
{
case TIM_CHANNEL_1:
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- break;
- }
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
break;
- }
+ }
default :
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
}
- }
+ }
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -2379,38 +2398,39 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
/* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
switch (Channel)
{
case TIM_CHANNEL_1:
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- break;
- }
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ break;
+ }
case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
break;
- }
+ }
default :
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
}
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -2422,42 +2442,43 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
/* Enable the encoder interface channels */
/* Enable the capture compare Interrupts 1 and/or 2 */
switch (Channel)
{
case TIM_CHANNEL_1:
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
+ break;
+ }
case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
break;
- }
+ }
default :
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
+ break;
}
- }
-
+ }
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -2469,45 +2490,46 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
/* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
if(Channel == TIM_CHANNEL_1)
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
/* Disable the capture compare Interrupts 1 */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
+ }
else if(Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
/* Disable the capture compare Interrupts 2 */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
+ }
else
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
/* Disable the capture compare Interrupts 1 and 2 */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -2519,6 +2541,7 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @param pData1 : The destination Buffer address for IC1.
* @param pData2 : The destination Buffer address for IC2.
* @param Length : The length of data to be transferred from TIM peripheral to memory.
@@ -2528,105 +2551,105 @@
{
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
+ if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
-
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
-
- /* Enable the TIM Input Capture DMA request */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
+
+ /* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
+
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
}
break;
-
+
case TIM_CHANNEL_ALL:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
-
+
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
+
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
default:
break;
- }
+ }
/* Return function status */
return HAL_OK;
}
@@ -2638,45 +2661,46 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
+
/* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
if(Channel == TIM_CHANNEL_1)
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
/* Disable the capture compare DMA Request 1 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
+ }
else if(Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
/* Disable the capture compare DMA Request 2 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
+ }
else
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
/* Disable the capture compare DMA Request 1 and 2 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -2687,13 +2711,13 @@
/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
* @brief IRQ handler management
*
-@verbatim
+@verbatim
==============================================================================
##### IRQ handler management #####
- ==============================================================================
- [..]
+ ==============================================================================
+ [..]
This section provides Timer IRQ handler function.
-
+
@endverbatim
* @{
*/
@@ -2707,12 +2731,12 @@
/* Capture compare 1 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
/* Input capture event */
if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
{
@@ -2731,13 +2755,34 @@
/* Capture compare 2 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
- {
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 3 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
+ {
HAL_TIM_IC_CaptureCallback(htim);
}
/* Output compare event */
@@ -2747,39 +2792,18 @@
HAL_TIM_PWM_PulseFinishedCallback(htim);
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 3 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
- {
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- /* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* Capture compare 4 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
- {
+ {
HAL_TIM_IC_CaptureCallback(htim);
}
/* Output compare event */
@@ -2789,13 +2813,13 @@
HAL_TIM_PWM_PulseFinishedCallback(htim);
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
+ }
}
/* TIM Update event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
- {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
+ {
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
HAL_TIM_PeriodElapsedCallback(htim);
}
@@ -2803,8 +2827,8 @@
/* TIM Break input event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
- {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+ {
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
HAL_TIMEx_BreakCallback(htim);
}
@@ -2812,8 +2836,8 @@
/* TIM Trigger detection event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
- {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
+ {
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
HAL_TIM_TriggerCallback(htim);
}
@@ -2821,8 +2845,8 @@
/* TIM commutation event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
- {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
+ {
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
HAL_TIMEx_CommutationCallback(htim);
}
@@ -2836,22 +2860,22 @@
/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
* @brief Peripheral Control functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral Control functions #####
- ==============================================================================
- [..]
+ ==============================================================================
+ [..]
This section provides functions allowing to:
- (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
(+) Configure External Clock source.
(+) Configure Complementary channels, break features and dead time.
(+) Configure Master and the Slave synchronization.
(+) Configure the DMA Burst Mode.
-
+
@endverbatim
* @{
*/
-
+
/**
* @brief Initializes the TIM Output Compare Channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
@@ -2868,18 +2892,18 @@
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
-
+
/* Check input state */
- __HAL_LOCK(htim);
-
+ __HAL_LOCK(htim);
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -2889,7 +2913,7 @@
TIM_OC1_SetConfig(htim->Instance, sConfig);
}
break;
-
+
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
@@ -2897,7 +2921,7 @@
TIM_OC2_SetConfig(htim->Instance, sConfig);
}
break;
-
+
case TIM_CHANNEL_3:
{
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
@@ -2905,7 +2929,7 @@
TIM_OC3_SetConfig(htim->Instance, sConfig);
}
break;
-
+
case TIM_CHANNEL_4:
{
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
@@ -2913,14 +2937,14 @@
TIM_OC4_SetConfig(htim->Instance, sConfig);
}
break;
-
+
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
+
+ __HAL_UNLOCK(htim);
+
return HAL_OK;
}
@@ -2945,11 +2969,11 @@
assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-
+
__HAL_LOCK(htim);
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
if (Channel == TIM_CHANNEL_1)
{
/* TI1 Configuration */
@@ -2957,7 +2981,7 @@
sConfig->ICPolarity,
sConfig->ICSelection,
sConfig->ICFilter);
-
+
/* Reset the IC1PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
@@ -2968,12 +2992,12 @@
{
/* TI2 Configuration */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance,
+
+ TIM_TI2_SetConfig(htim->Instance,
sConfig->ICPolarity,
sConfig->ICSelection,
sConfig->ICFilter);
-
+
/* Reset the IC2PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
@@ -2984,12 +3008,12 @@
{
/* TI3 Configuration */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- TIM_TI3_SetConfig(htim->Instance,
+
+ TIM_TI3_SetConfig(htim->Instance,
sConfig->ICPolarity,
sConfig->ICSelection,
sConfig->ICFilter);
-
+
/* Reset the IC3PSC Bits */
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
@@ -3000,24 +3024,24 @@
{
/* TI4 Configuration */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- TIM_TI4_SetConfig(htim->Instance,
+
+ TIM_TI4_SetConfig(htim->Instance,
sConfig->ICPolarity,
sConfig->ICSelection,
sConfig->ICFilter);
-
+
/* Reset the IC4PSC Bits */
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
/* Set the IC4PSC value */
htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
}
-
+
htim->State = HAL_TIM_STATE_READY;
-
+
__HAL_UNLOCK(htim);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
@@ -3036,18 +3060,18 @@
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
{
__HAL_LOCK(htim);
-
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -3055,69 +3079,69 @@
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
-
+
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
+
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
htim->Instance->CCMR1 |= sConfig->OCFastMode;
}
break;
-
+
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
-
+
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
+
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
}
break;
-
+
case TIM_CHANNEL_3:
{
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
-
+
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
+
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
}
break;
-
+
case TIM_CHANNEL_4:
{
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
-
+
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
+
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
}
break;
-
+
default:
- break;
+ break;
}
-
+
htim->State = HAL_TIM_STATE_READY;
-
+
__HAL_UNLOCK(htim);
-
+
return HAL_OK;
}
@@ -3139,61 +3163,61 @@
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
{
TIM_OC_InitTypeDef temp1;
-
+
/* Check the parameters */
assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
- if(OutputChannel != InputChannel)
+ if(OutputChannel != InputChannel)
{
__HAL_LOCK(htim);
-
+
htim->State = HAL_TIM_STATE_BUSY;
- /* Extract the Ouput compare configuration from sConfig structure */
+ /* Extract the Ouput compare configuration from sConfig structure */
temp1.OCMode = sConfig->OCMode;
temp1.Pulse = sConfig->Pulse;
temp1.OCPolarity = sConfig->OCPolarity;
temp1.OCNPolarity = sConfig->OCNPolarity;
temp1.OCIdleState = sConfig->OCIdleState;
- temp1.OCNIdleState = sConfig->OCNIdleState;
-
+ temp1.OCNIdleState = sConfig->OCNIdleState;
+
switch (OutputChannel)
{
case TIM_CHANNEL_1:
{
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_OC1_SetConfig(htim->Instance, &temp1);
+
+ TIM_OC1_SetConfig(htim->Instance, &temp1);
}
break;
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
TIM_OC2_SetConfig(htim->Instance, &temp1);
}
break;
default:
- break;
- }
+ break;
+ }
switch (InputChannel)
{
case TIM_CHANNEL_1:
{
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
+
TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
sConfig->ICSelection, sConfig->ICFilter);
-
+
/* Reset the IC1PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
/* Select the Trigger source */
htim->Instance->SMCR &= ~TIM_SMCR_TS;
htim->Instance->SMCR |= TIM_TS_TI1FP1;
-
- /* Select the Slave Mode */
+
+ /* Select the Slave Mode */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
}
@@ -3201,63 +3225,63 @@
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
sConfig->ICSelection, sConfig->ICFilter);
-
+
/* Reset the IC2PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
+
/* Select the Trigger source */
htim->Instance->SMCR &= ~TIM_SMCR_TS;
htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
- /* Select the Slave Mode */
+
+ /* Select the Slave Mode */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
}
break;
-
+
default:
- break;
+ break;
}
-
+
htim->State = HAL_TIM_STATE_READY;
-
+
__HAL_UNLOCK(htim);
-
+
return HAL_OK;
-}
+}
else
{
return HAL_ERROR;
}
-}
+}
/**
- * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
* @param htim : TIM handle
* @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
* This parameter can be one of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_RCR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_BDTR
- * @arg TIM_DMABase_DCR
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
* @param BurstRequestSrc : TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -3269,7 +3293,7 @@
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer : The Buffer address.
* @param BurstLength : DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
@@ -3280,16 +3304,16 @@
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((BurstBuffer == 0 ) && (BurstLength > 0))
+ if((BurstBuffer == 0 ) && (BurstLength > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
@@ -3299,100 +3323,100 @@
switch(BurstRequestSrc)
{
case TIM_DMA_UPDATE:
- {
+ {
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC1:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC2:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC3:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC4:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_COM:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
-
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_TRIGGER:
- {
+ {
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
default:
- break;
+ break;
}
/* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
/* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -3407,54 +3431,54 @@
{
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
+
/* Abort the DMA transfer (at least disable the DMA channel) */
switch(BurstRequestSrc)
{
case TIM_DMA_UPDATE:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
}
break;
case TIM_DMA_CC1:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
}
break;
case TIM_DMA_CC2:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
}
break;
case TIM_DMA_CC3:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
}
break;
case TIM_DMA_CC4:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
}
break;
case TIM_DMA_COM:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
}
break;
case TIM_DMA_TRIGGER:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
}
break;
default:
- break;
+ break;
}
-
+
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -3462,25 +3486,25 @@
* @param htim : TIM handle
* @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
* This parameter can be one of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_RCR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_BDTR
- * @arg TIM_DMABase_DCR
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
* @param BurstRequestSrc : TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -3492,7 +3516,7 @@
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer : The Buffer address.
* @param BurstLength : DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
@@ -3503,120 +3527,120 @@
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((BurstBuffer == 0 ) && (BurstLength > 0))
+ if((BurstBuffer == 0 ) && (BurstLength > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
+ }
switch(BurstRequestSrc)
{
case TIM_DMA_UPDATE:
- {
+ {
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC1:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC2:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC3:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC4:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_COM:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
-
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_TRIGGER:
- {
+ {
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
default:
- break;
+ break;
}
/* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
+
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -3631,54 +3655,54 @@
{
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
+
/* Abort the DMA transfer (at least disable the DMA channel) */
switch(BurstRequestSrc)
{
case TIM_DMA_UPDATE:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
}
break;
case TIM_DMA_CC1:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
}
break;
case TIM_DMA_CC2:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
}
break;
case TIM_DMA_CC3:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
}
break;
case TIM_DMA_CC4:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
}
break;
case TIM_DMA_COM:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
}
break;
case TIM_DMA_TRIGGER:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
}
break;
default:
- break;
+ break;
}
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -3686,104 +3710,104 @@
* @param htim : TIM handle
* @param EventSource : specifies the event source.
* This parameter can be one of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_COM: Timer COM event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @arg TIM_EventSource_Break: Timer Break event source
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1, TIM15, TIM16 and TIM17.
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+ * @note TIM6 and TIM7 can only generate an update event.
+ * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
* @retval HAL status
- */
+ */
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-
+
/* Process Locked */
__HAL_LOCK(htim);
-
+
/* Change the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Set the event sources */
htim->Instance->EGR = EventSource;
-
+
/* Change the TIM state */
htim->State = HAL_TIM_STATE_READY;
-
+
__HAL_UNLOCK(htim);
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Configures the OCRef clear feature
* @param htim : TIM handle
* @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
- * contains the OCREF clear feature and parameters for the TIM peripheral.
+ * contains the OCREF clear feature and parameters for the TIM peripheral.
* @param Channel : specifies the TIM Channel
* This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
{
uint32_t tmpsmcr = 0;
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
+
/* Process Locked */
__HAL_LOCK(htim);
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
switch (sClearInputConfig->ClearInputSource)
{
case TIM_CLEARINPUTSOURCE_NONE:
{
/* Clear the OCREF clear selection bit */
tmpsmcr &= ~TIM_SMCR_OCCS;
-
+
/* Clear the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
+
/* Set TIMx_SMCR */
htim->Instance->SMCR = tmpsmcr;
}
break;
-
+
case TIM_CLEARINPUTSOURCE_ETR:
{
TIM_ETR_SetConfig(htim->Instance,
sClearInputConfig->ClearInputPrescaler,
sClearInputConfig->ClearInputPolarity,
sClearInputConfig->ClearInputFilter);
-
+
/* Set the OCREF clear selection bit */
htim->Instance->SMCR |= TIM_SMCR_OCCS;
}
break;
- default:
- break;
+ default:
+ break;
}
-
+
switch (Channel)
- {
+ {
case TIM_CHANNEL_1:
{
if(sClearInputConfig->ClearInputState != RESET)
@@ -3794,13 +3818,13 @@
else
{
/* Disable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
}
- }
+ }
break;
- case TIM_CHANNEL_2:
+ case TIM_CHANNEL_2:
{
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
if(sClearInputConfig->ClearInputState != RESET)
{
/* Enable the Ocref clear feature for Channel 2 */
@@ -3809,13 +3833,13 @@
else
{
/* Disable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
}
- }
+ }
break;
- case TIM_CHANNEL_3:
+ case TIM_CHANNEL_3:
{
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
if(sClearInputConfig->ClearInputState != RESET)
{
/* Enable the Ocref clear feature for Channel 3 */
@@ -3824,13 +3848,13 @@
else
{
/* Disable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
}
- }
+ }
break;
- case TIM_CHANNEL_4:
+ case TIM_CHANNEL_4:
{
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
if(sClearInputConfig->ClearInputState != RESET)
{
/* Enable the Ocref clear feature for Channel 4 */
@@ -3839,68 +3863,68 @@
else
{
/* Disable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
}
- }
+ }
break;
- default:
+ default:
break;
}
-
- htim->State = HAL_TIM_STATE_READY;
-
+
+ htim->State = HAL_TIM_STATE_READY;
+
__HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
+
+ return HAL_OK;
+}
/**
* @brief Configures the clock source to be used
* @param htim : TIM handle
* @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
- * contains the clock source information for the TIM peripheral.
+ * contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
{
uint32_t tmpsmcr = 0;
-
+
/* Process Locked */
__HAL_LOCK(htim);
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
+
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
htim->Instance->SMCR = tmpsmcr;
-
+
switch (sClockSourceConfig->ClockSource)
{
case TIM_CLOCKSOURCE_INTERNAL:
{
- assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Disable slave mode to clock the prescaler directly with the internal clock */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
}
break;
-
+
case TIM_CLOCKSOURCE_ETRMODE1:
{
/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-
+
/* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
@@ -3912,29 +3936,29 @@
htim->Instance->SMCR = tmpsmcr;
}
break;
-
+
case TIM_CLOCKSOURCE_ETRMODE2:
{
/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
-
+
/* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
}
break;
-
+
case TIM_CLOCKSOURCE_TI1:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
}
@@ -3943,9 +3967,9 @@
{
/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- TIM_TI2_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
+
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
}
@@ -3954,8 +3978,8 @@
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
@@ -3965,7 +3989,7 @@
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
+
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
}
break;
@@ -3973,7 +3997,7 @@
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
+
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
}
break;
@@ -3981,7 +4005,7 @@
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
+
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
}
break;
@@ -3989,18 +4013,18 @@
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
+
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
}
break;
-
+
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
-
+
__HAL_UNLOCK(htim);
-
+
return HAL_OK;
}
@@ -4019,9 +4043,9 @@
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
{
uint32_t tmpcr2 = 0;
-
+
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
/* Get the TIMx CR2 register value */
@@ -4032,7 +4056,7 @@
/* Set the the TI1 selection */
tmpcr2 |= TI1_Selection;
-
+
/* Write to TIMxCR2 */
htim->Instance->CR2 = tmpcr2;
@@ -4045,7 +4069,7 @@
* @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
* timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
@@ -4054,61 +4078,61 @@
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
+
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-
+
/* Disable Trigger Interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
-
+
/* Disable Trigger DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
+
htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
+
+ __HAL_UNLOCK(htim);
+
return HAL_OK;
}
-
+
/**
* @brief Configures the TIM in Slave mode in interrupt mode
* @param htim: TIM handle.
* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
* timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef * sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
+
__HAL_LOCK(htim);
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-
+
/* Enable Trigger Interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-
+
/* Disable Trigger DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
+
htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
+
+ __HAL_UNLOCK(htim);
+
return HAL_OK;
-}
+}
/**
* @brief Read the captured value from Capture Compare unit
@@ -4124,74 +4148,74 @@
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpreg = 0;
-
+
__HAL_LOCK(htim);
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
+
/* Return the capture 1 value */
tmpreg = htim->Instance->CCR1;
-
+
break;
}
case TIM_CHANNEL_2:
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
/* Return the capture 2 value */
tmpreg = htim->Instance->CCR2;
-
+
break;
}
-
+
case TIM_CHANNEL_3:
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
+
/* Return the capture 3 value */
tmpreg = htim->Instance->CCR3;
-
+
break;
}
-
+
case TIM_CHANNEL_4:
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
+
/* Return the capture 4 value */
tmpreg = htim->Instance->CCR4;
-
+
break;
}
-
+
default:
- break;
+ break;
}
-
- __HAL_UNLOCK(htim);
+
+ __HAL_UNLOCK(htim);
return tmpreg;
}
/**
* @}
*/
-
+
/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
* @brief TIM Callbacks functions
*
-@verbatim
+@verbatim
==============================================================================
##### TIM Callbacks functions #####
- ==============================================================================
- [..]
+ ==============================================================================
+ [..]
This section provides TIM callback functions:
(+) Timer Period elapsed callback
(+) Timer Output Compare callback
@@ -4213,7 +4237,7 @@
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
-
+
}
/**
* @brief Output Compare callback in non blocking mode
@@ -4281,10 +4305,10 @@
/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
* @brief Peripheral State functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral State functions #####
- ==============================================================================
+ ==============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
and the data flow.
@@ -4359,37 +4383,37 @@
/**
* @}
- */
+ */
/** @addtogroup TIM_Private_Functions TIM_Private_Functions
* @{
- */
-
+ */
+
/**
* @brief TIM DMA error callback
* @param hdma : pointer to DMA handle.
* @retval None
*/
-void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
htim->State= HAL_TIM_STATE_READY;
-
+
HAL_TIM_ErrorCallback(htim);
}
/**
- * @brief TIM DMA Delay Pulse complete callback.
+ * @brief TIM DMA Delay Pulse complete callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
-void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
+
+ htim->State= HAL_TIM_STATE_READY;
+
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
@@ -4412,16 +4436,16 @@
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
- * @brief TIM DMA Capture complete callback.
+ * @brief TIM DMA Capture complete callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
-void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
htim->State= HAL_TIM_STATE_READY;
-
+
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
@@ -4438,37 +4462,37 @@
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
}
-
- HAL_TIM_IC_CaptureCallback(htim);
-
+
+ HAL_TIM_IC_CaptureCallback(htim);
+
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
-
+
/**
- * @brief TIM DMA Period Elapse complete callback.
+ * @brief TIM DMA Period Elapse complete callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
htim->State= HAL_TIM_STATE_READY;
-
+
HAL_TIM_PeriodElapsedCallback(htim);
}
/**
- * @brief TIM DMA Trigger callback.
+ * @brief TIM DMA Trigger callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
HAL_TIM_TriggerCallback(htim);
}
@@ -4482,7 +4506,7 @@
{
uint32_t tmpcr1 = 0;
tmpcr1 = TIMx->CR1;
-
+
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
{
@@ -4490,7 +4514,7 @@
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
tmpcr1 |= Structure->CounterMode;
}
-
+
if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
{
/* Set the clock division */
@@ -4502,11 +4526,11 @@
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
-
+
/* Set the Prescaler value */
TIMx->PSC = (uint32_t)Structure->Prescaler;
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
@@ -4527,16 +4551,16 @@
{
uint32_t tmpccmrx = 0;
uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpcr2 = 0;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
-
+
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
+ tmpcr2 = TIMx->CR2;
+
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
@@ -4545,7 +4569,7 @@
tmpccmrx &= ~TIM_CCMR1_CC1S;
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
-
+
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
/* Set the Output Compare Polarity */
@@ -4555,7 +4579,7 @@
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
+
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
/* Set the Output N Polarity */
@@ -4563,7 +4587,7 @@
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
}
-
+
if(IS_TIM_BREAK_INSTANCE(TIMx))
{
/* Check parameters */
@@ -4580,16 +4604,16 @@
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
-
+
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
-
+
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
-
+
/* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
+ TIMx->CCER = tmpccer;
+}
/**
* @brief Time Ouput Compare 2 configuration
@@ -4601,33 +4625,33 @@
{
uint32_t tmpccmrx = 0;
uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpcr2 = 0;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
-
+
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
+ tmpcr2 = TIMx->CR2;
+
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
tmpccmrx &= ~TIM_CCMR1_CC2S;
-
+
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8);
-
+
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4);
if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- {
+ {
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
@@ -4638,7 +4662,7 @@
tmpccer |= (OC_Config->OCNPolarity << 4);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
-
+
}
if(IS_TIM_BREAK_INSTANCE(TIMx))
@@ -4658,15 +4682,15 @@
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
-
+
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
-
+
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
-
+
/* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
+ TIMx->CCER = tmpccer;
}
/**
@@ -4679,32 +4703,32 @@
{
uint32_t tmpccmrx = 0;
uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpcr2 = 0;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
-
+
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
+ tmpcr2 = TIMx->CR2;
+
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
- tmpccmrx &= ~TIM_CCMR2_CC3S;
+ tmpccmrx &= ~TIM_CCMR2_CC3S;
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
-
+
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8);
if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- {
+ {
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
@@ -4716,7 +4740,7 @@
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
}
-
+
if(IS_TIM_BREAK_INSTANCE(TIMx))
{
/* Check parameters */
@@ -4734,15 +4758,15 @@
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
-
+
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
-
+
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
-
+
/* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
+ TIMx->CCER = tmpccer;
}
/**
@@ -4755,26 +4779,26 @@
{
uint32_t tmpccmrx = 0;
uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpcr2 = 0;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
-
+
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
+ tmpcr2 = TIMx->CR2;
+
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
tmpccmrx &= ~TIM_CCMR2_CC4S;
-
+
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8);
-
+
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
/* Set the Output Compare Polarity */
@@ -4792,15 +4816,15 @@
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
-
+
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
-
+
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
-
+
/* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
+ TIMx->CCER = tmpccer;
}
void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
@@ -4825,7 +4849,7 @@
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
-
+
/* Configure the trigger prescaler, filter, and polarity */
switch (sSlaveConfig->InputTrigger)
{
@@ -4837,92 +4861,91 @@
assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
/* Configure the ETR Trigger source */
- TIM_ETR_SetConfig(htim->Instance,
- sSlaveConfig->TriggerPrescaler,
- sSlaveConfig->TriggerPolarity,
+ TIM_ETR_SetConfig(htim->Instance,
+ sSlaveConfig->TriggerPrescaler,
+ sSlaveConfig->TriggerPolarity,
sSlaveConfig->TriggerFilter);
}
break;
-
+
case TIM_TS_TI1F_ED:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
+
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = htim->Instance->CCER;
htim->Instance->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = htim->Instance->CCMR1;
-
+ tmpccmr1 = htim->Instance->CCMR1;
+
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
-
+
/* Write to TIMx CCMR1 and CCER registers */
htim->Instance->CCMR1 = tmpccmr1;
- htim->Instance->CCER = tmpccer;
-
+ htim->Instance->CCER = tmpccer;
+
}
break;
-
+
case TIM_TS_TI1FP1:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
+
/* Configure TI1 Filter and Polarity */
TIM_TI1_ConfigInputStage(htim->Instance,
sSlaveConfig->TriggerPolarity,
sSlaveConfig->TriggerFilter);
}
break;
-
+
case TIM_TS_TI2FP2:
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
+
/* Configure TI2 Filter and Polarity */
TIM_TI2_ConfigInputStage(htim->Instance,
sSlaveConfig->TriggerPolarity,
sSlaveConfig->TriggerFilter);
}
break;
-
+
case TIM_TS_ITR0:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
}
break;
-
+
case TIM_TS_ITR1:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
}
break;
-
+
case TIM_TS_ITR2:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
}
break;
-
+
case TIM_TS_ITR3:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
}
break;
-
+
default:
break;
}
@@ -4933,14 +4956,14 @@
* @param TIMx to select the TIM peripheral.
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI : TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI : TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC : TIM Input 1 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC.
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -4964,12 +4987,12 @@
{
tmpccmr1 &= ~TIM_CCMR1_CC1S;
tmpccmr1 |= TIM_ICSelection;
- }
+ }
else
{
tmpccmr1 |= TIM_CCMR1_CC1S_0;
}
-
+
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
@@ -4988,9 +5011,9 @@
* @param TIMx to select the TIM peripheral.
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -4999,20 +5022,20 @@
{
uint32_t tmpccmr1 = 0;
uint32_t tmpccer = 0;
-
+
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
-
+ tmpccmr1 = TIMx->CCMR1;
+
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
tmpccmr1 |= (TIM_ICFilter << 4);
-
+
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
tmpccer |= TIM_ICPolarity;
-
+
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
TIMx->CCER = tmpccer;
@@ -5023,14 +5046,14 @@
* @param TIMx to select the TIM peripheral
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI : TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI : TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC : TIM Input 2 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC.
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -5071,9 +5094,9 @@
* @param TIMx to select the TIM peripheral.
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -5082,12 +5105,12 @@
{
uint32_t tmpccmr1 = 0;
uint32_t tmpccer = 0;
-
+
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1;
tmpccer = TIMx->CCER;
-
+
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
tmpccmr1 |= (TIM_ICFilter << 12);
@@ -5106,14 +5129,14 @@
* @param TIMx to select the TIM peripheral
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI : TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI : TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC : TIM Input 3 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC.
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -5154,14 +5177,14 @@
* @param TIMx to select the TIM peripheral
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI : TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI : TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC : TIM Input 4 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC.
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
@@ -5215,7 +5238,7 @@
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
{
uint32_t tmpsmcr = 0;
-
+
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
/* Reset the TS Bits */
@@ -5257,19 +5280,19 @@
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
-}
+}
/**
* @brief Enables or disables the TIM Capture Compare Channel x.
* @param TIMx to select the TIM peripheral
* @param Channel : specifies the TIM Channel
* This parameter can be one of the following values:
- * @arg TIM_Channel_1 : TIM Channel 1
- * @arg TIM_Channel_2 : TIM Channel 2
- * @arg TIM_Channel_3 : TIM Channel 3
- * @arg TIM_Channel_4 : TIM Channel 4
+ * @arg TIM_CHANNEL_1 : TIM Channel 1
+ * @arg TIM_CHANNEL_2 : TIM Channel 2
+ * @arg TIM_CHANNEL_3 : TIM Channel 3
+ * @arg TIM_CHANNEL_4 : TIM Channel 4
* @param ChannelState : specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
@@ -5277,7 +5300,7 @@
uint32_t tmp = 0;
/* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << Channel;
@@ -5285,7 +5308,7 @@
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
- /* Set or reset the CCxE Bit */
+ /* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << Channel);
}
@@ -5297,9 +5320,9 @@
#endif /* HAL_TIM_MODULE_ENABLED */
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_tim.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_TIM_H
@@ -52,15 +52,14 @@
/** @addtogroup TIM
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup TIM_Exported_Types TIM Exported Types
* @{
*/
-
-/**
- * @brief TIM Time base Configuration Structure definition
+/**
+ * @brief TIM Time base Configuration Structure definition
*/
typedef struct
{
@@ -72,7 +71,7 @@
uint32_t Period; /*!< Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t ClockDivision; /*!< Specifies the clock division.
This parameter can be a value of @ref TIM_ClockDivision */
@@ -83,20 +82,20 @@
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
@note This parameter is valid only for TIM1 and TIM8. */
} TIM_Base_InitTypeDef;
-/**
- * @brief TIM Output Compare Configuration Structure definition
+/**
+ * @brief TIM Output Compare Configuration Structure definition
*/
typedef struct
-{
+{
uint32_t OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
@@ -104,7 +103,7 @@
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
@note This parameter is valid only for TIM1 and TIM8. */
-
+
uint32_t OCFastMode; /*!< Specifies the Fast mode state.
This parameter can be a value of @ref TIM_Output_Fast_State
@note This parameter is valid only in PWM1 and PWM2 mode. */
@@ -117,18 +116,18 @@
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OC_InitTypeDef;
+} TIM_OC_InitTypeDef;
-/**
- * @brief TIM One Pulse Mode Configuration Structure definition
+/**
+ * @brief TIM One Pulse Mode Configuration Structure definition
*/
typedef struct
-{
+{
uint32_t OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
@@ -152,15 +151,15 @@
This parameter can be a value of @ref TIM_Input_Capture_Selection */
uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_OnePulse_InitTypeDef;
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
-/**
- * @brief TIM Input Capture Configuration Structure definition
+/**
+ * @brief TIM Input Capture Configuration Structure definition
*/
typedef struct
-{
+{
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -174,14 +173,14 @@
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_IC_InitTypeDef;
-/**
- * @brief TIM Encoder Configuration Structure definition
+/**
+ * @brief TIM Encoder Configuration Structure definition
*/
typedef struct
{
uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Encoder_Mode */
-
+
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -193,7 +192,7 @@
uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
+
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -204,48 +203,48 @@
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC2Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_Encoder_InitTypeDef;
-/**
- * @brief Clock Configuration Handle Structure definition
+/**
+ * @brief TIM Clock Configuration Handle Structure definition
*/
typedef struct
{
uint32_t ClockSource; /*!< TIM clock sources
- This parameter can be a value of @ref TIM_Clock_Source */
+ This parameter can be a value of @ref TIM_Clock_Source */
uint32_t ClockPolarity; /*!< TIM clock polarity
This parameter can be a value of @ref TIM_Clock_Polarity */
uint32_t ClockPrescaler; /*!< TIM clock prescaler
This parameter can be a value of @ref TIM_Clock_Prescaler */
uint32_t ClockFilter; /*!< TIM clock filter
- This parameter can be a value of @ref TIM_Clock_Filter */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
}TIM_ClockConfigTypeDef;
-/**
- * @brief Clear Input Configuration Handle Structure definition
+/**
+ * @brief TIM Clear Input Configuration Handle Structure definition
*/
typedef struct
-{
+{
uint32_t ClearInputState; /*!< TIM clear Input state
- This parameter can be ENABLE or DISABLE */
+ This parameter can be ENABLE or DISABLE */
uint32_t ClearInputSource; /*!< TIM clear Input sources
- This parameter can be a value of @ref TIM_ClearInput_Source */
+ This parameter can be a value of @ref TIM_ClearInput_Source */
uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
This parameter can be a value of @ref TIM_ClearInput_Polarity */
uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
This parameter can be a value of @ref TIM_ClearInput_Prescaler */
uint32_t ClearInputFilter; /*!< TIM Clear Input filter
- This parameter can be a value of @ref TIM_ClearInput_Filter */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
}TIM_ClearInputConfigTypeDef;
-/**
- * @brief TIM Slave configuration Structure definition
+/**
+ * @brief TIM Slave configuration Structure definition
*/
typedef struct {
uint32_t SlaveMode; /*!< Slave mode selection
- This parameter can be a value of @ref TIM_Slave_Mode */
+ This parameter can be a value of @ref TIM_Slave_Mode */
uint32_t InputTrigger; /*!< Input Trigger source
This parameter can be a value of @ref TIM_Trigger_Selection */
uint32_t TriggerPolarity; /*!< Input Trigger polarity
@@ -253,46 +252,46 @@
uint32_t TriggerPrescaler; /*!< Input trigger prescaler
This parameter can be a value of @ref TIM_Trigger_Prescaler */
uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a value of @ref TIM_Trigger_Filter */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
}TIM_SlaveConfigTypeDef;
-/**
- * @brief HAL State structures definition
+/**
+ * @brief HAL State structures definition
*/
typedef enum
{
HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
- HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+ HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
}HAL_TIM_StateTypeDef;
-/**
- * @brief HAL Active channel structures definition
+/**
+ * @brief HAL Active channel structures definition
*/
typedef enum
{
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
}HAL_TIM_ActiveChannel;
-/**
- * @brief TIM Time Base Handle Structure definition
+/**
+ * @brief TIM Time Base Handle Structure definition
*/
typedef struct
{
- TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
This array is accessed by a @ref TIM_DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
}TIM_HandleTypeDef;
/**
@@ -304,7 +303,7 @@
* @{
*/
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
* @{
*/
#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
@@ -317,8 +316,8 @@
/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
* @{
*/
-#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
/**
* @}
*/
@@ -337,41 +336,28 @@
/** @defgroup TIM_Counter_Mode TIM Counter Mode
* @{
*/
-
#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
-
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
- ((MODE) == TIM_COUNTERMODE_DOWN) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
-/**
- * @}
- */
-
-/** @defgroup TIM_ClockDivision TIM Clock Division
- * @{
- */
-
-#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
-#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
-#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
-
-#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV4))
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare & PWM modes
+/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
+#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
+#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
+#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
+/**
+ * @}
+ */
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
+ * @{
+ */
#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
@@ -380,78 +366,33 @@
#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
-
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
- ((MODE) == TIM_OCMODE_PWM2))
-
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
- ((MODE) == TIM_OCMODE_ACTIVE) || \
- ((MODE) == TIM_OCMODE_INACTIVE) || \
- ((MODE) == TIM_OCMODE_TOGGLE) || \
- ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State
- * @{
- */
-
-#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
-#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
-
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
- ((STATE) == TIM_OUTPUTSTATE_ENABLE))
-/**
- * @}
- */
/** @defgroup TIM_Output_Fast_State TIM Output Fast State
* @{
*/
#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
-
-#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
- ((STATE) == TIM_OCFAST_ENABLE))
/**
* @}
*/
-/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
- * @{
- */
-#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
-#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
-
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
- ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
-/**
- * @}
- */
-
/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
* @{
*/
-
#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
-
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCPOLARITY_LOW))
/**
* @}
*/
/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
* @{
- */
-
+ */
#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
-
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCNPOLARITY_LOW))
/**
* @}
*/
@@ -459,11 +400,8 @@
/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
* @{
*/
-
#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
- ((STATE) == TIM_OCIDLESTATE_RESET))
/**
* @}
*/
@@ -471,11 +409,8 @@
/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
* @{
*/
-
#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
- ((STATE) == TIM_OCNIDLESTATE_RESET))
/**
* @}
*/
@@ -488,22 +423,6 @@
#define TIM_CHANNEL_3 ((uint32_t)0x0008)
#define TIM_CHANNEL_4 ((uint32_t)0x000C)
#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
-
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4) || \
- ((CHANNEL) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3))
/**
* @}
*/
@@ -511,14 +430,9 @@
/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
* @{
*/
-
#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
-
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
- ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
- ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
/**
* @}
*/
@@ -526,16 +440,11 @@
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
-
#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_TRC))
/**
* @}
*/
@@ -543,16 +452,10 @@
/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
* @{
*/
-
#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
-
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
/**
* @}
*/
@@ -560,31 +463,25 @@
/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
* @{
*/
-
#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
-
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
- ((MODE) == TIM_OPMODE_REPETITIVE))
/**
* @}
*/
+
/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
* @{
- */
+ */
#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
-
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
- ((MODE) == TIM_ENCODERMODE_TI2) || \
- ((MODE) == TIM_ENCODERMODE_TI12))
/**
* @}
*/
-/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+
+/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
* @{
- */
+ */
#define TIM_IT_UPDATE (TIM_DIER_UIE)
#define TIM_IT_CC1 (TIM_DIER_CC1IE)
#define TIM_IT_CC2 (TIM_DIER_CC2IE)
@@ -597,7 +494,7 @@
* @}
*/
-/** @defgroup TIM_COMMUTATION TIM Commutation
+/** @defgroup TIM_Commutation_Source TIM Commutation Source
* @{
*/
#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
@@ -606,10 +503,10 @@
/**
* @}
*/
+
/** @defgroup TIM_DMA_sources TIM DMA Sources
* @{
*/
-
#define TIM_DMA_UPDATE (TIM_DIER_UDE)
#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
@@ -617,8 +514,6 @@
#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define TIM_DMA_COM (TIM_DIER_COMDE)
#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
-
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
/**
* @}
*/
@@ -626,16 +521,14 @@
/** @defgroup TIM_Event_Source TIM Event Source
* @{
*/
-#define TIM_EventSource_Update TIM_EGR_UG
-#define TIM_EventSource_CC1 TIM_EGR_CC1G
-#define TIM_EventSource_CC2 TIM_EGR_CC2G
-#define TIM_EventSource_CC3 TIM_EGR_CC3G
-#define TIM_EventSource_CC4 TIM_EGR_CC4G
-#define TIM_EventSource_COM TIM_EGR_COMG
-#define TIM_EventSource_Trigger TIM_EGR_TG
-#define TIM_EventSource_Break TIM_EGR_BG
-
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
/**
* @}
*/
@@ -643,7 +536,6 @@
/** @defgroup TIM_Flag_definition TIM Flag Definition
* @{
*/
-
#define TIM_FLAG_UPDATE (TIM_SR_UIF)
#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
@@ -656,19 +548,6 @@
#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
-
-#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
- ((FLAG) == TIM_FLAG_CC1) || \
- ((FLAG) == TIM_FLAG_CC2) || \
- ((FLAG) == TIM_FLAG_CC3) || \
- ((FLAG) == TIM_FLAG_CC4) || \
- ((FLAG) == TIM_FLAG_COM) || \
- ((FLAG) == TIM_FLAG_TRIGGER) || \
- ((FLAG) == TIM_FLAG_BREAK) || \
- ((FLAG) == TIM_FLAG_CC1OF) || \
- ((FLAG) == TIM_FLAG_CC2OF) || \
- ((FLAG) == TIM_FLAG_CC3OF) || \
- ((FLAG) == TIM_FLAG_CC4OF))
/**
* @}
*/
@@ -676,8 +555,8 @@
/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
*/
-#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
-#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
+#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
+#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
@@ -686,17 +565,6 @@
#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
-
-#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
/**
* @}
*/
@@ -704,52 +572,31 @@
/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
* @{
*/
-#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
-
-#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
/**
* @}
*/
+
/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
* @{
- */
+ */
#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-
-#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
/**
* @}
*/
-/** @defgroup TIM_Clock_Filter TIM Clock Filter
- * @{
- */
-
-#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
* @{
*/
-#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
+#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
-
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
- ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
/**
* @}
*/
@@ -757,15 +604,11 @@
/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
* @{
*/
-#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
-
-
-#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
/**
* @}
- */
+ */
/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
* @{
@@ -774,81 +617,53 @@
#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-
-#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
/**
* @}
*/
-/** @defgroup TIM_ClearInput_Filter TIM Clear Input Filter
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
* @{
*/
-
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode
- * @{
- */
#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
- ((STATE) == TIM_OSSR_DISABLE))
/**
* @}
*/
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
* @{
*/
#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
- ((STATE) == TIM_OSSI_DISABLE))
/**
* @}
*/
-/** @defgroup TIM_Lock_level TIM Lock Configuration
+
+/** @defgroup TIM_Lock_level TIM Lock level
* @{
*/
#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
-
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
- ((LEVEL) == TIM_LOCKLEVEL_1) || \
- ((LEVEL) == TIM_LOCKLEVEL_2) || \
- ((LEVEL) == TIM_LOCKLEVEL_3))
/**
* @}
*/
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
* @{
*/
#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
- ((STATE) == TIM_BREAK_DISABLE))
/**
* @}
*/
+
/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
* @{
*/
#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
-
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
- ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
/**
* @}
*/
@@ -857,9 +672,6 @@
*/
#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
/**
* @}
*/
@@ -867,64 +679,42 @@
/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
* @{
*/
-#define TIM_TRGO_RESET ((uint32_t)0x0000)
-#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
-#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
-#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
-#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
- ((SOURCE) == TIM_TRGO_ENABLE) || \
- ((SOURCE) == TIM_TRGO_UPDATE) || \
- ((SOURCE) == TIM_TRGO_OC1) || \
- ((SOURCE) == TIM_TRGO_OC1REF) || \
- ((SOURCE) == TIM_TRGO_OC2REF) || \
- ((SOURCE) == TIM_TRGO_OC3REF) || \
- ((SOURCE) == TIM_TRGO_OC4REF))
-
-
+#define TIM_TRGO_RESET ((uint32_t)0x0000)
+#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
+#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
+#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
+#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
+#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
+#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
/**
* @}
- */
+ */
/** @defgroup TIM_Slave_Mode TIM Slave Mode
* @{
*/
-
#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
-
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
- ((MODE) == TIM_SLAVEMODE_GATED) || \
- ((MODE) == TIM_SLAVEMODE_RESET) || \
- ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
- ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
/**
* @}
*/
-/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
* @{
*/
-
#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
-
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
/**
* @}
*/
+
/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
* @{
*/
-
#define TIM_TS_ITR0 ((uint32_t)0x0000)
#define TIM_TS_ITR1 ((uint32_t)0x0010)
#define TIM_TS_ITR2 ((uint32_t)0x0020)
@@ -934,26 +724,6 @@
#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
#define TIM_TS_ETRF ((uint32_t)0x0070)
#define TIM_TS_NONE ((uint32_t)0xFFFF)
-
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_NONE))
/**
* @}
*/
@@ -961,17 +731,11 @@
/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
* @{
*/
-#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-
-#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
/**
* @}
*/
@@ -983,20 +747,6 @@
#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-
-#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Filter TIM Trigger Filter
- * @{
- */
-
-#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
/**
* @}
*/
@@ -1004,61 +754,35 @@
/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
* @{
*/
-
#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
-
-#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
- ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
-
/**
* @}
*/
-/** @defgroup TIM_DMA_Base_address TIM DMA Base address
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
* @{
*/
-#define TIM_DMABase_CR1 (0x00000000)
-#define TIM_DMABase_CR2 (0x00000001)
-#define TIM_DMABase_SMCR (0x00000002)
-#define TIM_DMABase_DIER (0x00000003)
-#define TIM_DMABase_SR (0x00000004)
-#define TIM_DMABase_EGR (0x00000005)
-#define TIM_DMABase_CCMR1 (0x00000006)
-#define TIM_DMABase_CCMR2 (0x00000007)
-#define TIM_DMABase_CCER (0x00000008)
-#define TIM_DMABase_CNT (0x00000009)
-#define TIM_DMABase_PSC (0x0000000A)
-#define TIM_DMABase_ARR (0x0000000B)
-#define TIM_DMABase_RCR (0x0000000C)
-#define TIM_DMABase_CCR1 (0x0000000D)
-#define TIM_DMABase_CCR2 (0x0000000E)
-#define TIM_DMABase_CCR3 (0x0000000F)
-#define TIM_DMABase_CCR4 (0x00000010)
-#define TIM_DMABase_BDTR (0x00000011)
-#define TIM_DMABase_DCR (0x00000012)
-#define TIM_DMABase_OR (0x00000013)
-
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
- ((BASE) == TIM_DMABase_CR2) || \
- ((BASE) == TIM_DMABase_SMCR) || \
- ((BASE) == TIM_DMABase_DIER) || \
- ((BASE) == TIM_DMABase_SR) || \
- ((BASE) == TIM_DMABase_EGR) || \
- ((BASE) == TIM_DMABase_CCMR1) || \
- ((BASE) == TIM_DMABase_CCMR2) || \
- ((BASE) == TIM_DMABase_CCER) || \
- ((BASE) == TIM_DMABase_CNT) || \
- ((BASE) == TIM_DMABase_PSC) || \
- ((BASE) == TIM_DMABase_ARR) || \
- ((BASE) == TIM_DMABase_RCR) || \
- ((BASE) == TIM_DMABase_CCR1) || \
- ((BASE) == TIM_DMABase_CCR2) || \
- ((BASE) == TIM_DMABase_CCR3) || \
- ((BASE) == TIM_DMABase_CCR4) || \
- ((BASE) == TIM_DMABase_BDTR) || \
- ((BASE) == TIM_DMABase_DCR) || \
- ((BASE) == TIM_DMABase_OR))
+#define TIM_DMABASE_CR1 (0x00000000)
+#define TIM_DMABASE_CR2 (0x00000001)
+#define TIM_DMABASE_SMCR (0x00000002)
+#define TIM_DMABASE_DIER (0x00000003)
+#define TIM_DMABASE_SR (0x00000004)
+#define TIM_DMABASE_EGR (0x00000005)
+#define TIM_DMABASE_CCMR1 (0x00000006)
+#define TIM_DMABASE_CCMR2 (0x00000007)
+#define TIM_DMABASE_CCER (0x00000008)
+#define TIM_DMABASE_CNT (0x00000009)
+#define TIM_DMABASE_PSC (0x0000000A)
+#define TIM_DMABASE_ARR (0x0000000B)
+#define TIM_DMABASE_RCR (0x0000000C)
+#define TIM_DMABASE_CCR1 (0x0000000D)
+#define TIM_DMABASE_CCR2 (0x0000000E)
+#define TIM_DMABASE_CCR3 (0x0000000F)
+#define TIM_DMABASE_CCR4 (0x00000010)
+#define TIM_DMABASE_BDTR (0x00000011)
+#define TIM_DMABASE_DCR (0x00000012)
+#define TIM_DMABASE_OR (0x00000013)
/**
* @}
*/
@@ -1066,53 +790,24 @@
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-
-#define TIM_DMABurstLength_1Transfer (0x00000000)
-#define TIM_DMABurstLength_2Transfers (0x00000100)
-#define TIM_DMABurstLength_3Transfers (0x00000200)
-#define TIM_DMABurstLength_4Transfers (0x00000300)
-#define TIM_DMABurstLength_5Transfers (0x00000400)
-#define TIM_DMABurstLength_6Transfers (0x00000500)
-#define TIM_DMABurstLength_7Transfers (0x00000600)
-#define TIM_DMABurstLength_8Transfers (0x00000700)
-#define TIM_DMABurstLength_9Transfers (0x00000800)
-#define TIM_DMABurstLength_10Transfers (0x00000900)
-#define TIM_DMABurstLength_11Transfers (0x00000A00)
-#define TIM_DMABurstLength_12Transfers (0x00000B00)
-#define TIM_DMABurstLength_13Transfers (0x00000C00)
-#define TIM_DMABurstLength_14Transfers (0x00000D00)
-#define TIM_DMABurstLength_15Transfers (0x00000E00)
-#define TIM_DMABurstLength_16Transfers (0x00000F00)
-#define TIM_DMABurstLength_17Transfers (0x00001000)
-#define TIM_DMABurstLength_18Transfers (0x00001100)
-
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
- ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_18Transfers))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Filer_Value TIM Input Capture Value
- * @{
- */
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
+#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
+#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
+#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
+#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
+#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
+#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
+#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
+#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
+#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
+#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
+#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
+#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
+#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
+#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
+#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
+#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
+#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
/**
* @}
*/
@@ -1131,7 +826,7 @@
* @}
*/
-/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
* @{
*/
#define TIM_CCx_ENABLE ((uint32_t)0x0001)
@@ -1145,7 +840,325 @@
/**
* @}
*/
-
+
+/* Private Constants -----------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+ * @{
+ */
+
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+
+/**
+ * @}
+ */
+
+/* Private Macros -----------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
+ ((MODE) == TIM_COUNTERMODE_DOWN) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
+ ((DIV) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
+ ((MODE) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
+ ((MODE) == TIM_OCMODE_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_INACTIVE) || \
+ ((MODE) == TIM_OCMODE_TOGGLE) || \
+ ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
+
+#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
+ ((STATE) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
+ ((POLARITY) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
+ ((STATE) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
+ ((STATE) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))
+
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
+ ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((SELECTION) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
+ ((MODE) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
+ ((MODE) == TIM_ENCODERMODE_TI2) || \
+ ((MODE) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
+
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
+
+#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
+ ((FLAG) == TIM_FLAG_CC1) || \
+ ((FLAG) == TIM_FLAG_CC2) || \
+ ((FLAG) == TIM_FLAG_CC3) || \
+ ((FLAG) == TIM_FLAG_CC4) || \
+ ((FLAG) == TIM_FLAG_COM) || \
+ ((FLAG) == TIM_FLAG_TRIGGER) || \
+ ((FLAG) == TIM_FLAG_BREAK) || \
+ ((FLAG) == TIM_FLAG_CC1OF) || \
+ ((FLAG) == TIM_FLAG_CC2OF) || \
+ ((FLAG) == TIM_FLAG_CC3OF) || \
+ ((FLAG) == TIM_FLAG_CC4OF))
+
+#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
+ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
+ ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
+ ((STATE) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
+ ((STATE) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
+ ((LEVEL) == TIM_LOCKLEVEL_1) || \
+ ((LEVEL) == TIM_LOCKLEVEL_2) || \
+ ((LEVEL) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
+ ((STATE) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
+ ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
+ ((SOURCE) == TIM_TRGO_ENABLE) || \
+ ((SOURCE) == TIM_TRGO_UPDATE) || \
+ ((SOURCE) == TIM_TRGO_OC1) || \
+ ((SOURCE) == TIM_TRGO_OC1REF) || \
+ ((SOURCE) == TIM_TRGO_OC2REF) || \
+ ((SOURCE) == TIM_TRGO_OC3REF) || \
+ ((SOURCE) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
+ ((MODE) == TIM_SLAVEMODE_GATED) || \
+ ((MODE) == TIM_SLAVEMODE_RESET) || \
+ ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
+ ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
+
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+
+#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
+ ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
+ ((BASE) == TIM_DMABASE_CR2) || \
+ ((BASE) == TIM_DMABASE_SMCR) || \
+ ((BASE) == TIM_DMABASE_DIER) || \
+ ((BASE) == TIM_DMABASE_SR) || \
+ ((BASE) == TIM_DMABASE_EGR) || \
+ ((BASE) == TIM_DMABASE_CCMR1) || \
+ ((BASE) == TIM_DMABASE_CCMR2) || \
+ ((BASE) == TIM_DMABASE_CCER) || \
+ ((BASE) == TIM_DMABASE_CNT) || \
+ ((BASE) == TIM_DMABASE_PSC) || \
+ ((BASE) == TIM_DMABASE_ARR) || \
+ ((BASE) == TIM_DMABASE_RCR) || \
+ ((BASE) == TIM_DMABASE_CCR1) || \
+ ((BASE) == TIM_DMABASE_CCR2) || \
+ ((BASE) == TIM_DMABASE_CCR3) || \
+ ((BASE) == TIM_DMABASE_CCR4) || \
+ ((BASE) == TIM_DMABASE_BDTR) || \
+ ((BASE) == TIM_DMABASE_DCR) || \
+ ((BASE) == TIM_DMABASE_OR))
+
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+ ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+
+/** @brief Set TIM IC prescaler
+ * @param __HANDLE__: TIM handle
+ * @param __CHANNEL__: specifies TIM Channel
+ * @param __ICPSC__: specifies the prescaler value.
+ * @retval None
+ */
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
+
+/** @brief Reset TIM IC prescaler
+ * @param __HANDLE__: TIM handle
+ * @param __CHANNEL__: specifies TIM Channel
+ * @retval None
+ */
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+
+/** @brief Set TIM IC polarity
+ * @param __HANDLE__: TIM handle
+ * @param __CHANNEL__: specifies TIM Channel
+ * @param __POLARITY__: specifies TIM Channel Polarity
+ * @retval None
+ */
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
+
+/** @brief Reset TIM IC polarity
+ * @param __HANDLE__: TIM handle
+ * @param __CHANNEL__: specifies TIM Channel
+ * @retval None
+ */
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
+
+/**
+ * @}
+ */
+
+/* Private Functions --------------------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+/**
+ * @}
+ */
+
/* Exported macros -----------------------------------------------------------*/
/** @defgroup TIM_Exported_Macros TIM Exported Macros
* @{
@@ -1178,57 +1191,174 @@
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
{ \
- if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \
} \
} while(0)
/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
+ channels have been disabled */
/**
* @brief Disable the TIM main Output.
* @param __HANDLE__: TIM handle
* @retval None
+ * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
{ \
- if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \
} \
} while(0)
+/**
+ * @brief Enables the specified TIM interrupt.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/**
+ * @brief Disables the specified TIM interrupt.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Enables the specified DMA request.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __DMA__: specifies the TIM DMA request to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/**
+ * @brief Disables the specified DMA request.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __DMA__: specifies the TIM DMA request to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/**
+ * @brief Checks whether the specified TIM interrupt flag is set or not.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __FLAG__: specifies the TIM interrupt flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clears the specified TIM interrupt flag.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __FLAG__: specifies the TIM interrupt flag to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+/**
+ * @brief Checks whether the specified TIM interrupt has occurred or not.
+ * @param __HANDLE__: TIM handle
+ * @param __INTERRUPT__: specifies the TIM interrupt source to check.
+ * @retval The state of TIM_IT (SET or RESET).
+ */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Clear the TIM interrupt pending bits
+ * @param __HANDLE__: TIM handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * @retval None
+ */
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
-#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
+/**
+ * @brief Indicates whether or not the TIM Counter is used as downcounter
+ * @param __HANDLE__: TIM handle.
+ * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+ * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
+mode.
+ */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
-#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
+/**
+ * @brief Sets the TIM active prescaler register value on update event.
+ * @param __HANDLE__: TIM handle.
+ * @param __PRESC__: specifies the active prescaler register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
-#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
-
/**
* @brief Sets the TIM Capture Compare Register value on runtime without
* calling another time ConfigChannel function.
@@ -1242,7 +1372,7 @@
* @param __COMPARE__: specifies the Capture Compare register new value.
* @retval None
*/
-#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
/**
@@ -1256,7 +1386,7 @@
* @arg TIM_CHANNEL_4: get capture/compare 4 register value
* @retval None
*/
-#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
/**
@@ -1265,16 +1395,16 @@
* @param __COUNTER__: specifies the Counter register new value.
* @retval None
*/
-#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
/**
* @brief Gets the TIM Counter Register value on runtime.
* @param __HANDLE__: TIM handle.
* @retval None
*/
-#define __HAL_TIM_GetCounter(__HANDLE__) \
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
((__HANDLE__)->Instance->CNT)
-
+
/**
* @brief Sets the TIM Autoreload Register value on runtime without calling
* another time any Init function.
@@ -1282,7 +1412,7 @@
* @param __AUTORELOAD__: specifies the Counter register new value.
* @retval None
*/
-#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
do{ \
(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
@@ -1293,35 +1423,35 @@
* @param __HANDLE__: TIM handle.
* @retval None
*/
-#define __HAL_TIM_GetAutoreload(__HANDLE__) \
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
((__HANDLE__)->Instance->ARR)
-
+
/**
* @brief Sets the TIM Clock Division value on runtime without calling
- * another time any Init function.
+ * another time any Init function.
* @param __HANDLE__: TIM handle.
* @param __CKD__: specifies the clock division value.
* This parameter can be one of the following value:
* @arg TIM_CLOCKDIVISION_DIV1
* @arg TIM_CLOCKDIVISION_DIV2
- * @arg TIM_CLOCKDIVISION_DIV4
+ * @arg TIM_CLOCKDIVISION_DIV4
* @retval None
*/
-#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
do{ \
(__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \
(__HANDLE__)->Instance->CR1 |= (__CKD__); \
(__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0)
-
+
/**
* @brief Gets the TIM Clock Division value on runtime
- * @param __HANDLE__: TIM handle.
+ * @param __HANDLE__: TIM handle.
* @retval None
*/
-#define __HAL_TIM_GetClockDivision(__HANDLE__) \
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
+
/**
* @brief Sets the TIM Input Capture prescaler on runtime without calling
* another time HAL_TIM_IC_ConfigChannel() function.
@@ -1340,11 +1470,11 @@
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
* @retval None
*/
-#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
do{ \
- __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
- __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0)
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0)
/**
* @brief Gets the TIM Input Capture prescaler on runtime
@@ -1357,12 +1487,12 @@
* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
* @retval None
*/
-#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
-
+
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
* @param __HANDLE__: TIM handle.
@@ -1389,6 +1519,28 @@
((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
/**
+ * @brief Sets the TIM Capture x input polarity on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __POLARITY__: Polarity for TIx source
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+ * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
+ * @retval None
+ */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0)
+
+/**
* @}
*/
@@ -1396,12 +1548,11 @@
#include "stm32f0xx_hal_tim_ex.h"
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+/** @addtogroup TIM_Exported_Functions
* @{
*/
-/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
- * @brief Time Base functions
+/** @addtogroup TIM_Exported_Functions_Group1
* @{
*/
/* Time Base functions ********************************************************/
@@ -1422,8 +1573,7 @@
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
- * @brief Time Output Compare functions
+/** @addtogroup TIM_Exported_Functions_Group2
* @{
*/
/* Timer Output Compare functions **********************************************/
@@ -1440,12 +1590,12 @@
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
- * @brief Time PWM functions
+/** @addtogroup TIM_Exported_Functions_Group3
* @{
*/
/* Timer PWM functions *********************************************************/
@@ -1466,8 +1616,7 @@
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
- * @brief Time Input Capture functions
+/** @addtogroup TIM_Exported_Functions_Group4
* @{
*/
/* Timer Input Capture functions ***********************************************/
@@ -1488,8 +1637,7 @@
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
- * @brief Time One Pulse functions
+/** @addtogroup TIM_Exported_Functions_Group5
* @{
*/
/* Timer One Pulse functions ***************************************************/
@@ -1507,8 +1655,7 @@
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
- * @brief Time Encoder functions
+/** @addtogroup TIM_Exported_Functions_Group6
* @{
*/
/* Timer Encoder functions *****************************************************/
@@ -1525,12 +1672,12 @@
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief IRQ handler management
+/** @addtogroup TIM_Exported_Functions_Group7
* @{
*/
/* Interrupt Handler functions **********************************************/
@@ -1539,8 +1686,7 @@
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group8 Peripheral Control functions
- * @brief Peripheral Control functions
+/** @addtogroup TIM_Exported_Functions_Group8
* @{
*/
/* Control functions *********************************************************/
@@ -1561,12 +1707,12 @@
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+
/**
* @}
*/
/** @addtogroup TIM_Exported_Functions_Group9
- * @brief TIM Callbacks functions
* @{
*/
/* Callback in non blocking modes (Interrupt and DMA) *************************/
@@ -1581,7 +1727,6 @@
*/
/** @addtogroup TIM_Exported_Functions_Group10
- * @brief Peripheral State functions
* @{
*/
/* Peripheral State functions **************************************************/
@@ -1591,6 +1736,7 @@
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+
/**
* @}
*/
@@ -1599,40 +1745,12 @@
* @}
*/
-/* Private Macros -----------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-/**
- * @}
- */
-
-/* Private Functions --------------------------------------------------------*/
-/** @addtogroup TIM_Private_Functions
- * @{
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
-void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
-
/**
* @}
*/
/**
* @}
- */
-
-/**
- * @}
*/
#ifdef __cplusplus
@@ -1642,4 +1760,3 @@
#endif /* __STM32F0xx_HAL_TIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,22 +2,22 @@
******************************************************************************
* @file stm32f0xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer Extended peripheral:
* + Time Hall Sensor Interface Initialization
* + Time Hall Sensor Interface Start
- * + Time Complementary signal bread and dead time configuration
+ * + Time Complementary signal bread and dead time configuration
* + Time Master and Slave synchronization configuration
* + Timer remapping capabilities configuration
@verbatim
==============================================================================
##### TIMER Extended features #####
==============================================================================
- [..]
- The Timer Extended features include:
+ [..]
+ The Timer Extended features include:
(#) Complementary outputs with programmable dead-time for :
(++) Output Compare
(++) PWM generation (Edge and Center-aligned Mode)
@@ -26,7 +26,7 @@
interconnect several timers together.
(#) Break input to put the timer output signals in reset state or in a known state.
(#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
- positioning purposes
+ positioning purposes
##### How to use this driver #####
==============================================================================
@@ -37,19 +37,19 @@
(++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
(++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
(++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
-
+
(#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
(##) TIM pins configuration
(+++) Enable the clock for the TIM GPIOs using the following function:
- __GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
(#) The external Clock can be configured, if needed (the default clock is the
internal clock from the APBx), using the following function:
HAL_TIM_ConfigClockSource, the clock configuration should be done before
any start function.
-
+
(#) Configure the TIM in the desired functioning mode using one of the
initialization function of this driver:
(++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
@@ -58,18 +58,18 @@
with the Hall sensor Interface and another Timer should be used to use
the commutation event).
- (#) Activate the TIM peripheral using one of the start functions:
+ (#) Activate the TIM peripheral using one of the start functions:
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
-
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -94,7 +94,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
-*/
+*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@@ -103,7 +103,7 @@
* @{
*/
-/** @defgroup TIMEx TIMEx Extended HAL module driver
+/** @defgroup TIMEx TIMEx
* @brief TIM Extended HAL module driver
* @{
*/
@@ -119,7 +119,7 @@
/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
+static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
/**
* @}
*/
@@ -133,13 +133,13 @@
/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
*
-@verbatim
+@verbatim
==============================================================================
##### Timer Hall Sensor functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
- (+) Initialize and configure TIM HAL Sensor.
+ (+) Initialize and configure TIM HAL Sensor.
(+) De-initialize TIM HAL Sensor.
(+) Start the Hall Sensor Interface.
(+) Stop the Hall Sensor Interface.
@@ -147,7 +147,7 @@
(+) Stop the Hall Sensor Interface and disable interrupts.
(+) Start the Hall Sensor Interface and enable DMA transfers.
(+) Stop the Hall Sensor Interface and disable DMA transfers.
-
+
@endverbatim
* @{
*/
@@ -160,13 +160,13 @@
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
{
TIM_OC_InitTypeDef OC_Config;
-
+
/* Check the TIM handle allocation */
if(htim == NULL)
{
return HAL_ERROR;
}
-
+
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
@@ -174,34 +174,40 @@
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIMEx_HallSensor_MspInit(htim);
+ }
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIMEx_HallSensor_MspInit(htim);
-
+
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
+
/* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
-
+
/* Reset the IC1PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
/* Set the IC1PSC value */
htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
-
+
/* Enable the Hall sensor interface (XOR function of the three inputs) */
htim->Instance->CR2 |= TIM_CR2_TI1S;
-
+
/* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
htim->Instance->SMCR &= ~TIM_SMCR_TS;
htim->Instance->SMCR |= TIM_TS_TI1F_ED;
-
- /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
-
+
/* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
@@ -209,15 +215,15 @@
OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
- OC_Config.Pulse = sConfig->Commutation_Delay;
-
+ OC_Config.Pulse = sConfig->Commutation_Delay;
+
TIM_OC2_SetConfig(htim->Instance, &OC_Config);
-
+
/* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
register to 101 */
htim->Instance->CR2 &= ~TIM_CR2_MMS;
- htim->Instance->CR2 |= TIM_TRGO_OC2REF;
-
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
/* Initialize the TIM state*/
htim->State= HAL_TIM_STATE_READY;
@@ -225,7 +231,7 @@
}
/**
- * @brief DeInitializes the TIM Hall Sensor interface
+ * @brief DeInitializes the TIM Hall Sensor interface
* @param htim : TIM Hall Sensor handle
* @retval HAL status
*/
@@ -235,16 +241,16 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIMEx_HallSensor_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
/* Release Lock */
__HAL_UNLOCK(htim);
@@ -284,14 +290,14 @@
{
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- /* Enable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -305,14 +311,14 @@
{
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
+
/* Disable the Input Capture channels 1, 2 and 3
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -323,20 +329,20 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
-{
+{
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
+
/* Enable the capture compare Interrupts 1 event */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
- /* Enable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -350,17 +356,17 @@
{
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
/* Disable the capture compare Interrupts event */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -376,40 +382,40 @@
{
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0 ) && (Length > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
}
- /* Enable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
/* Set the DMA Input Capture 1 Callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel for Capture 1*/
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
/* Enable the capture compare 1 Interrupt */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -423,18 +429,18 @@
{
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-
- /* Disable the Input Capture channels 1
- (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
/* Disable the capture compare Interrupts 1 event */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -442,15 +448,15 @@
/**
* @}
*/
-
+
/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
*
-@verbatim
+@verbatim
==============================================================================
##### Timer Complementary Output Compare functions #####
- ==============================================================================
- [..]
+ ==============================================================================
+ [..]
This section provides functions allowing to:
(+) Start the Complementary Output Compare/PWM.
(+) Stop the Complementary Output Compare/PWM.
@@ -458,15 +464,15 @@
(+) Stop the Complementary Output Compare/PWM and disable interrupts.
(+) Start the Complementary Output Compare/PWM and enable DMA transfers.
(+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
-
+
@endverbatim
* @{
*/
-
+
/**
* @brief Starts the TIM Output Compare signal generation on the complementary
* output.
- * @param htim : TIM Output Compare handle
+ * @param htim : TIM Output Compare handle
* @param Channel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
@@ -478,20 +484,20 @@
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
+
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Stops the TIM Output Compare signal generation on the complementary
@@ -506,22 +512,22 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
+{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
+
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode
@@ -538,57 +544,57 @@
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
break;
- }
-
+ }
+
/* Enable the TIM Break interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
+
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
+
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode
@@ -607,45 +613,45 @@
uint32_t tmpccer = 0;
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
- break;
+ break;
}
-
+
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
+
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
@@ -658,10 +664,10 @@
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode
@@ -680,102 +686,102 @@
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0 ) && (Length > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
+
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
+
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
+
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
}
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
+
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
-
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
+ __HAL_TIM_ENABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -795,54 +801,54 @@
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
- }
-
+ }
+
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
+
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -850,15 +856,15 @@
/**
* @}
*/
-
+
/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
*
-@verbatim
+@verbatim
==============================================================================
##### Timer Complementary PWM functions #####
- ==============================================================================
- [..]
+ ==============================================================================
+ [..]
This section provides functions allowing to:
(+) Start the Complementary PWM.
(+) Stop the Complementary PWM.
@@ -876,7 +882,7 @@
(+) Stop the Complementary One Pulse.
(+) Start the Complementary One Pulse and enable interrupts.
(+) Stop the Complementary One Pulse and disable interrupts.
-
+
@endverbatim
* @{
*/
@@ -895,20 +901,20 @@
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
+
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Stops the PWM signal generation on the complementary output.
@@ -922,22 +928,22 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
+{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
/* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Starts the PWM signal generation in interrupt mode on the
@@ -954,57 +960,57 @@
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
break;
- }
-
+ }
+
/* Enable the TIM Break interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
+
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
+
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Stops the PWM signal generation in interrupt mode on the
@@ -1023,61 +1029,61 @@
uint32_t tmpccer = 0;
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
- break;
+ break;
}
-
+
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
+
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
-
+
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Starts the TIM PWM signal generation in DMA mode on the
@@ -1096,102 +1102,102 @@
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0 ) && (Length > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
+
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
+
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
+
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
}
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
+
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
-
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
+ __HAL_TIM_ENABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -1211,54 +1217,54 @@
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
-
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
- }
-
+ }
+
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
+
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -1266,21 +1272,21 @@
/**
* @}
*/
-
+
/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
*
-@verbatim
+@verbatim
==============================================================================
##### Timer Complementary One Pulse functions #####
- ==============================================================================
- [..]
+ ==============================================================================
+ [..]
This section provides functions allowing to:
(+) Start the Complementary One Pulse generation.
(+) Stop the Complementary One Pulse.
(+) Start the Complementary One Pulse and enable interrupts.
(+) Stop the Complementary One Pulse and disable interrupts.
-
+
@endverbatim
* @{
*/
@@ -1298,14 +1304,14 @@
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
-
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
/* Enable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -1324,17 +1330,17 @@
{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Disable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
+
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
-
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -1352,24 +1358,24 @@
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
+
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
+
/* Enable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
/* Enable the Main Ouput */
__HAL_TIM_MOE_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
- }
-
+ }
+
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
@@ -1383,46 +1389,44 @@
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Check the parameters */
- assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
+
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
+
/* Disable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
+
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
-
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
}
-
-
/**
* @}
*/
/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
* @brief Peripheral Control functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral Control functions #####
- ==============================================================================
- [..]
+ ==============================================================================
+ [..]
This section provides functions allowing to:
(+) Configure the commutation event in case of use of the Hall sensor interface.
(+) Configure Complementary channels, break features and dead time.
(+) Configure Master synchronization.
(+) Configure timer remapping capabilities.
-
+
@endverbatim
* @{
*/
@@ -1430,7 +1434,7 @@
* @brief Configure the TIM commutation event sequence.
* @note: this function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
+ * the typical use of this feature is with the use of another Timer(interface Timer)
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
@@ -1453,25 +1457,25 @@
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
+
__HAL_LOCK(htim);
-
+
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
+ {
/* Select the Input trigger */
htim->Instance->SMCR &= ~TIM_SMCR_TS;
htim->Instance->SMCR |= InputTrigger;
}
-
+
/* Select the Capture Compare preload feature */
htim->Instance->CR2 |= TIM_CR2_CCPC;
/* Select the Commutation event source */
htim->Instance->CR2 &= ~TIM_CR2_CCUS;
htim->Instance->CR2 |= CommutationSource;
-
+
__HAL_UNLOCK(htim);
-
+
return HAL_OK;
}
@@ -1479,7 +1483,7 @@
* @brief Configure the TIM commutation event sequence with interrupt.
* @note: this function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
+ * the typical use of this feature is with the use of another Timer(interface Timer)
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
@@ -1502,28 +1506,28 @@
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
+
__HAL_LOCK(htim);
-
+
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
+ {
/* Select the Input trigger */
htim->Instance->SMCR &= ~TIM_SMCR_TS;
htim->Instance->SMCR |= InputTrigger;
}
-
+
/* Select the Capture Compare preload feature */
htim->Instance->CR2 |= TIM_CR2_CCPC;
/* Select the Commutation event source */
htim->Instance->CR2 &= ~TIM_CR2_CCUS;
htim->Instance->CR2 |= CommutationSource;
-
+
/* Enable the Commutation Interrupt Request */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
__HAL_UNLOCK(htim);
-
+
return HAL_OK;
}
@@ -1531,7 +1535,7 @@
* @brief Configure the TIM commutation event sequence with DMA.
* @note: this function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
- * the typical use of this feature is with the use of another Timer(interface Timer)
+ * the typical use of this feature is with the use of another Timer(interface Timer)
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
@@ -1555,43 +1559,43 @@
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
-
+
__HAL_LOCK(htim);
-
+
if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
(InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
- {
+ {
/* Select the Input trigger */
htim->Instance->SMCR &= ~TIM_SMCR_TS;
htim->Instance->SMCR |= InputTrigger;
}
-
+
/* Select the Capture Compare preload feature */
htim->Instance->CR2 |= TIM_CR2_CCPC;
/* Select the Commutation event source */
htim->Instance->CR2 &= ~TIM_CR2_CCUS;
htim->Instance->CR2 |= CommutationSource;
-
+
/* Enable the Commutation DMA Request */
/* Set the DMA Commutation Callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
-
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
/* Enable the Commutation DMA Request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
__HAL_UNLOCK(htim);
-
+
return HAL_OK;
}
/**
* @brief Configures the TIM in master mode.
- * @param htim : TIM handle.
+ * @param htim : TIM handle.
* @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that
* contains the selected trigger output (TRGO) and the Master/Slave
- * mode.
+ * mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
@@ -1600,7 +1604,7 @@
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
+
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
@@ -1614,11 +1618,11 @@
htim->Instance->SMCR &= ~TIM_SMCR_MSM;
/* Set or Reset the MSM Bit */
htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
-
+
htim->State = HAL_TIM_STATE_READY;
-
+
__HAL_UNLOCK(htim);
-
+
return HAL_OK;
}
@@ -1627,10 +1631,10 @@
* and the AOE(automatic output enable).
* @param htim : TIM handle
* @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
+ * contains the BDTR Register configuration information for the TIM peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
/* Check the parameters */
@@ -1642,27 +1646,27 @@
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
-
+
/* Process Locked */
__HAL_LOCK(htim);
-
+
htim->State = HAL_TIM_STATE_BUSY;
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
- htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
+ htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
sBreakDeadTimeConfig->OffStateIDLEMode |
sBreakDeadTimeConfig->LockLevel |
sBreakDeadTimeConfig->DeadTime |
sBreakDeadTimeConfig->BreakState |
sBreakDeadTimeConfig->BreakPolarity |
sBreakDeadTimeConfig->AutomaticOutput;
-
-
- htim->State = HAL_TIM_STATE_READY;
-
+
+
+ htim->State = HAL_TIM_STATE_READY;
+
__HAL_UNLOCK(htim);
-
+
return HAL_OK;
}
@@ -1674,24 +1678,24 @@
* @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
* @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
* @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
- * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
+ * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
{
__HAL_LOCK(htim);
-
+
/* Check parameters */
assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
assert_param(IS_TIM_REMAP(Remap));
-
+
/* Set the Timer remapping configuration */
htim->Instance->OR = Remap;
-
+
htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
+
+ __HAL_UNLOCK(htim);
+
return HAL_OK;
}
@@ -1702,11 +1706,11 @@
/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
* @brief Extension Callbacks functions
*
-@verbatim
+@verbatim
==============================================================================
##### Extension Callbacks functions #####
- ==============================================================================
- [..]
+ ==============================================================================
+ [..]
This section provides Extension TIM callback functions:
(+) Timer Commutation callback
(+) Timer Break callback
@@ -1740,17 +1744,17 @@
}
/**
- * @brief TIM DMA Commutation callback.
+ * @brief TIM DMA Commutation callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
-void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIMEx_CommutationCallback(htim);
+
+ HAL_TIMEx_CommutationCallback(htim);
}
/**
@@ -1760,10 +1764,10 @@
/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
* @brief Extension Peripheral State functions
*
-@verbatim
+@verbatim
==============================================================================
##### Extension Peripheral State functions #####
- ==============================================================================
+ ==============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
and the data flow.
@@ -1788,7 +1792,7 @@
/**
* @}
- */
+ */
/** @addtogroup TIMEx_Private_Functions
* @{
@@ -1799,11 +1803,11 @@
* @param TIMx to select the TIM peripheral
* @param Channel : specifies the TIM Channel
* This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
* @param ChannelNState : specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
* @retval None
*/
static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
@@ -1815,21 +1819,21 @@
/* Reset the CCxNE Bit */
TIMx->CCER &= ~tmp;
- /* Set or reset the CCxNE Bit */
+ /* Set or reset the CCxNE Bit */
TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
}
/**
* @}
- */
+ */
#endif /* HAL_TIM_MODULE_ENABLED */
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_tim_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_TIM_EX_H
@@ -52,44 +52,45 @@
/** @addtogroup TIMEx
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIMEx Extended Exported Types
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIMEx Exported Types
* @{
*/
-/**
- * @brief TIM Hall sensor Configuration Structure definition
+
+/**
+ * @brief TIM Hall sensor Configuration Structure definition
*/
typedef struct
{
-
+
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
+
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
+
uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef;
-/**
- * @brief TIM Master configuration Structure definition
+/**
+ * @brief TIM Master configuration Structure definition
*/
typedef struct {
uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
- This parameter can be a value of @ref TIM_Master_Mode_Selection */
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
uint32_t MasterSlaveMode; /*!< Master/slave mode selection
This parameter can be a value of @ref TIM_Master_Slave_Mode */
}TIM_MasterConfigTypeDef;
-/**
- * @brief TIM Break and Dead time configuration Structure definition
+/**
+ * @brief TIM Break and Dead time configuration Structure definition
*/
typedef struct
{
@@ -98,7 +99,7 @@
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
uint32_t LockLevel; /*!< TIM Lock level
- This parameter can be a value of @ref TIM_Lock_level */
+ This parameter can be a value of @ref TIM_Lock_level */
uint32_t DeadTime; /*!< TIM dead Time
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint32_t BreakState; /*!< TIM Break State
@@ -106,18 +107,18 @@
uint32_t BreakPolarity; /*!< TIM Break input polarity
This parameter can be a value of @ref TIM_Break_Polarity */
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
} TIM_BreakDeadTimeConfigTypeDef;
/**
* @}
- */
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
* @{
*/
-
+
/** @defgroup TIMEx_Remap TIMEx Remap
* @{
*/
@@ -135,10 +136,10 @@
* @}
*/
-/** @defgroup TIM_Clock_Filter TIM Clock Filter
+/** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter
* @{
*/
-#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF)
+#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF) /*!< BreakDead Time */
/**
* @}
*/
@@ -154,8 +155,7 @@
* @{
*/
-/** @addtogroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
+/** @addtogroup TIMEx_Exported_Functions_Group1
* @{
*/
/* Timer Hall Sensor functions **********************************************/
@@ -178,8 +178,7 @@
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
+/** @addtogroup TIMEx_Exported_Functions_Group2
* @{
*/
/* Timer Complementary Output Compare functions *****************************/
@@ -198,8 +197,7 @@
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
+/** @addtogroup TIMEx_Exported_Functions_Group3
* @{
*/
/* Timer Complementary PWM functions ****************************************/
@@ -217,8 +215,7 @@
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
+/** @addtogroup TIMEx_Exported_Functions_Group4
* @{
*/
/* Timer Complementary One Pulse functions **********************************/
@@ -233,8 +230,7 @@
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
- * @brief Peripheral Control functions
+/** @addtogroup TIMEx_Exported_Functions_Group5
* @{
*/
/* Extended Control functions ************************************************/
@@ -248,20 +244,17 @@
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
- * @brief Extended Callbacks functions
+/** @addtogroup TIMEx_Exported_Functions_Group6
* @{
*/
/* Extension Callback *********************************************************/
void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
- * @brief Extended Peripheral State functions
+/** @addtogroup TIMEx_Exported_Functions_Group7
* @{
*/
/* Extension Peripheral State functions **************************************/
@@ -272,16 +265,27 @@
/**
* @}
- */
+ */
+/* End of exported functions -------------------------------------------------*/
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+* @{
+*/
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
/**
- * @}
- */
+* @}
+*/
+/* End of private functions --------------------------------------------------*/
/**
* @}
*/
-
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
@@ -290,4 +294,3 @@
#endif /* __STM32F0xx_HAL_TIM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_tsc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief This file provides firmware functions to manage the following
* functionalities of the Touch Sensing Controller (TSC) peripheral:
* + Initialization and DeInitialization
@@ -47,10 +47,10 @@
##### How to use this driver #####
================================================================================
[..]
- (#) Enable the TSC interface clock using __TSC_CLK_ENABLE() macro.
+ (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro.
(#) GPIO pins configuration
- (++) Enable the clock for the TSC GPIOs using __GPIOx_CLK_ENABLE() macro.
+ (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro.
(++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
using HAL_GPIO_Init() function.
@@ -81,7 +81,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -121,7 +121,7 @@
* @{
*/
-/** @defgroup TSC TSC HAL module driver
+/** @defgroup TSC TSC
* @brief TSC HAL module driver
* @{
*/
@@ -179,7 +179,13 @@
assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
-
+
+ if(htsc->State == HAL_TSC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htsc->Lock = HAL_UNLOCKED;
+ }
+
/* Initialize the TSC state */
htsc->State = HAL_TSC_STATE_BUSY;
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tsc.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f0xx_hal_tsc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief This file contains all the functions prototypes for the TSC firmware
* library.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -282,9 +282,9 @@
/** @defgroup TSC_Synchronization_pin_polarity TSC Synchronization pin polarity
* @{
*/
-#define TSC_SYNC_POL_FALL ((uint32_t)0)
-#define TSC_SYNC_POL_RISE_HIGH (TSC_CR_SYNCPOL)
-#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POL_FALL) || ((VAL) == TSC_SYNC_POL_RISE_HIGH))
+#define TSC_SYNC_POLARITY_FALLING ((uint32_t)0)
+#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
+#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
/**
* @}
*/
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,69 +2,68 @@
******************************************************************************
* @file stm32f0xx_hal_uart.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
- @verbatim
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
===============================================================================
- ##### How to use this driver #####
-================================================================================
- [..]
+ [..]
The UART HAL driver can be used as follows:
-
- (#) Declare a UART_HandleTypeDef handle structure.
- (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit ()API:
- (##) Enable the USARTx interface clock.
- (##) UART pins configuration:
+ (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) UART pins configuration:
(+++) Enable the clock for the UART GPIOs.
(+++) Configure these UART pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+ (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
and HAL_UART_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
(+++) Enable the NVIC USART IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+ (++) UART interrupts handling:
+ -@@- The specific UART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) are managed using the macros
+ __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
+ (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
and HAL_UART_Receive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx channel.
(+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initilalized DMA handle to the UART DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
- (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) in the huart Init structure.
-
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+ flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
(#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
- in the huart AdvancedInit structure.
+ in the huart handle AdvancedInit structure.
(#) For the UART asynchronous mode, initialize the UART registers by calling
the HAL_UART_Init() API.
-
- (#) For the UART Half duplex mode, initialize the UART registers by calling
- the HAL_HalfDuplex_Init() API.
-
- (#) For the UART Multiprocessor mode, initialize the UART registers
- by calling the HAL_MultiProcessor_Init() API.
- (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
- by calling the HAL_RS485Ex_Init() API.
+ (#) For the UART Half duplex mode, initialize the UART registers by calling
+ the HAL_HalfDuplex_Init() API.
+
+ (#) For the UART Multiprocessor mode, initialize the UART registers
+ by calling the HAL_MultiProcessor_Init() API.
- [..]
- (@) The specific UART interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive process.
+ (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
- [..]
+ [..]
(@) These APIs(HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(),
- also configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by
- calling the customed HAL_UART_MspInit() API.
+ also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+ calling the customized HAL_UART_MspInit() API.
Three operation modes are available within this driver :
@@ -128,7 +127,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -152,7 +151,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -162,25 +161,27 @@
* @{
*/
-/** @defgroup UART UART HAL module driver
+/** @defgroup UART UART
* @brief HAL UART module driver
* @{
*/
+
#ifdef HAL_UART_MODULE_ENABLED
-
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup UART_Private_Constants UART Private Constants
+/** @defgroup UART_Private_Constants UART Private Constants
* @{
*/
-#define HAL_UART_TXDMA_TIMEOUTVALUE 22000
+#define UART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< UART TX or RX enable acknowledge time-out value */
+#define UART_TXDMA_TIMEOUTVALUE 22000
#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup UART_Private_Functions UART Private Functions
@@ -190,50 +191,64 @@
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup UART_Exported_Functions UART Exported Functions
* @{
*/
-/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and Configuration functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
in asynchronous mode.
- (+) For the asynchronous mode only these parameters can be configured:
+ (+) For the asynchronous mode the parameters below can be configured:
(++) Baud Rate
- (++) Word Length
+ (++) Word Length
(++) Stop Bit
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible UART frame formats are as listed in the following table:
- |-----------|-----------|---------------------------------------|
- | M1M0 bits | PCE bit | UART frame |
- |-----------------------|---------------------------------------|
- | 00 | 0 | | SB | 8-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 00 | 1 | | SB | 7-bit data | PB | STB | |
- |-----------|-----------|---------------------------------------|
- | 01 | 0 | | SB | 9-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 01 | 1 | | SB | 8-bit data | PB | STB | |
- +---------------------------------------------------------------+
- | 10 | 0 | | SB | 7-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 10 | 1 | | SB | 6-bit data | PB | STB | |
- +---------------------------------------------------------------+
+ According to device capability (support or not of 7-bit word length),
+ frame length is either defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
+ Possible UART frame formats are as listed in the following table:
+
+ (+++) Table 1. UART frame format.
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M bit | PCE bit | UART frame |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | | SB | 8-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | | SB | 9-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M1 bit | M0 bit | PCE bit | UART frame |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
(++) Hardware flow control
(++) Receiver/transmitter modes
(++) Over Sampling Method
@@ -247,8 +262,8 @@
(++) MSB first on communication line
(++) auto Baud rate detection
[..]
- The HAL_UART_Init(), HAL_HalfDuplex_Init() and HAL_MultiProcessor_Init()
- API follow respectively the UART asynchronous, UART Half duplex and multiprocessor
+ The HAL_UART_Init(), HAL_HalfDuplex_Init() and HAL_MultiProcessor_Init()
+ API follow respectively the UART asynchronous, UART Half duplex and multiprocessor mode
configuration procedures (details for the procedures are available in reference manual).
@endverbatim
@@ -256,9 +271,9 @@
*/
/**
- * @brief Initializes the UART mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle .
- * @param huart: uart handle
+ * @brief Initialize the UART mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart: UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
@@ -268,7 +283,7 @@
{
return HAL_ERROR;
}
-
+
if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
{
/* Check the parameters */
@@ -279,46 +294,49 @@
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
-
+
if(huart->State == HAL_UART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
}
-
+
huart->State = HAL_UART_STATE_BUSY;
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
-
+
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
- }
-
+ }
+
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
-
- /* In asynchronous mode, the following bits must be kept cleared:
+
+ /* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
- huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
- huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
-
+ huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
+ huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
-
+
/* TEACK and/or REACK to check before moving huart->State to Ready */
return (UART_CheckIdleState(huart));
}
/**
- * @brief Initializes the half-duplex mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle .
- * @param huart: uart handle
+ * @brief Initialize the half-duplex mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart: UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
@@ -328,65 +346,68 @@
{
return HAL_ERROR;
}
-
+
/* Check UART instance */
assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
-
+
if(huart->State == HAL_UART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
}
-
+
huart->State = HAL_UART_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
-
+
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
- }
-
+ }
+
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
-
- /* In half-duplex mode, the following bits must be kept cleared:
+
+ /* In half-duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/
huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);
-
+
/* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
huart->Instance->CR3 |= USART_CR3_HDSEL;
-
+
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
-
+
/* TEACK and/or REACK to check before moving huart->State to Ready */
return (UART_CheckIdleState(huart));
}
/**
- * @brief Initializes the multiprocessor mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle.
- * @param huart: UART handle
- * @param Address: UART node address (4-, 6-, 7- or 8-bit long)
+ * @brief Initialize the multiprocessor mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart: UART handle.
+ * @param Address: UART node address (4-, 6-, 7- or 8-bit long).
* @param WakeUpMethod: specifies the UART wakeup method.
* This parameter can be one of the following values:
* @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection
* @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark
* @note If the user resorts to idle line detection wake up, the Address parameter
- * is useless and ignored by the initialization function.
- * @note If the user resorts to address mark wake up, the address length detection
- * is configured by default to 4 bits only. For the UART to be able to
+ * is useless and ignored by the initialization function.
+ * @note If the user resorts to address mark wake up, the address length detection
+ * is configured by default to 4 bits only. For the UART to be able to
* manage 6-, 7- or 8-bit long addresses detection, the API
- * HAL_MultiProcessorEx_AddressLength_Set() must be called after
- * HAL_MultiProcessor_Init().
+ * HAL_MultiProcessorEx_AddressLength_Set() must be called after
+ * HAL_MultiProcessor_Init().
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
@@ -399,54 +420,57 @@
/* Check the wake up method parameter */
assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
-
+
if(huart->State == HAL_UART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
}
-
+
huart->State = HAL_UART_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
-
+
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
- }
-
+ }
+
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
-
- /* In multiprocessor mode, the following bits must be kept cleared:
+
+ /* In multiprocessor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register. */
huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
-
+
if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
{
/* If address mark wake up method is chosen, set the USART address node */
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
}
-
+
/* Set the wake up method by setting the WAKE bit in the CR1 register */
MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
-
+
/* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
+ __HAL_UART_ENABLE(huart);
+
/* TEACK and/or REACK to check before moving huart->State to Ready */
return (UART_CheckIdleState(huart));
}
/**
- * @brief DeInitializes the UART peripheral
- * @param huart: uart handle
+ * @brief DeInitialize the UART peripheral.
+ * @param huart: UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
@@ -456,141 +480,138 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
huart->State = HAL_UART_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
-
+
huart->Instance->CR1 = 0x0;
huart->Instance->CR2 = 0x0;
huart->Instance->CR3 = 0x0;
-
+
/* DeInit the low level hardware */
HAL_UART_MspDeInit(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->State = HAL_UART_STATE_RESET;
-
+
/* Process Unlock */
__HAL_UNLOCK(huart);
-
+
return HAL_OK;
}
/**
- * @brief UART MSP Init
- * @param huart: uart handle
+ * @brief Initialize the UART MSP.
+ * @param huart: UART handle.
* @retval None
*/
__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_MspInit can be implemented in the user file
- */
+ */
}
/**
- * @brief UART MSP DeInit
- * @param huart: uart handle
+ * @brief DeInitialize the UART MSP.
+ * @param huart: UART handle.
* @retval None
*/
__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
{
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_MspDeInit could be implemented in the user file
- */
+ the HAL_UART_MspDeInit can be implemented in the user file
+ */
}
/**
* @}
*/
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions
- * @brief UART Transmit and Receive functions
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+ * @brief UART Transmit/Receive functions
*
-@verbatim
- ==============================================================================
+@verbatim
+ ===============================================================================
##### IO operation functions #####
- ==============================================================================
- [..]
+ ===============================================================================
This subsection provides a set of functions allowing to manage the UART asynchronous
and Half duplex data transfers.
(#) There are two mode of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+ (+) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (+) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
- The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
- (#) Blocking mode APIs are :
- (++) HAL_UART_Transmit()
- (++) HAL_UART_Receive()
-
- (#) Non Blocking mode APIs with Interrupt are :
- (++) HAL_UART_Transmit_IT()
- (++) HAL_UART_Receive_IT()
- (++) HAL_UART_IRQHandler()
- (++) UART_Transmit_IT()
- (++) UART_Receive_IT()
+ (#) Blocking mode API's are :
+ (+) HAL_UART_Transmit()
+ (+) HAL_UART_Receive()
+
+ (#) Non-Blocking mode API's with Interrupt are :
+ (+) HAL_UART_Transmit_IT()
+ (+) HAL_UART_Receive_IT()
+ (+) HAL_UART_IRQHandler()
- (#) Non Blocking mode APIs with DMA are :
- (++) HAL_UART_Transmit_DMA()
- (++) HAL_UART_Receive_DMA()
- (++) HAL_UART_DMAPause()
- (++) HAL_UART_DMAResume()
- (++) HAL_UART_DMAStop()
+ (#) No-Blocking mode API's with DMA are :
+ (+) HAL_UART_Transmit_DMA()
+ (+) HAL_UART_Receive_DMA()
+ (+) HAL_UART_DMAPause()
+ (+) HAL_UART_DMAResume()
+ (+) HAL_UART_DMAStop()
- (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
- (++) HAL_UART_TxHalfCpltCallback()
- (++) HAL_UART_TxCpltCallback()
- (++) HAL_UART_RxHalfCpltCallback()
- (++) HAL_UART_RxCpltCallback()
- (++) HAL_UART_ErrorCallback()
+ (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (+) HAL_UART_TxHalfCpltCallback()
+ (+) HAL_UART_TxCpltCallback()
+ (+) HAL_UART_RxHalfCpltCallback()
+ (+) HAL_UART_RxCpltCallback()
+ (+) HAL_UART_ErrorCallback()
- [..]
- (@) In the Half duplex communication, it is forbidden to run the transmit
+
+ -@- In the Half duplex communication, it is forbidden to run the transmit
and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
-
+
@endverbatim
* @{
*/
/**
- * @brief Send an amount of data in blocking mode
- * @param huart: uart handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout : Timeout duration
+ * @brief Send an amount of data in blocking mode.
+ * @param huart: UART handle.
+ * @param pData: Pointer to data buffer.
+ * @param Size: Amount of data to be sent.
+ * @param Timeout: Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint16_t* tmp;
if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(huart);
-
+
huart->ErrorCode = HAL_UART_ERROR_NONE;
/* Check if a non-blocking receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_RX)
+ if(huart->State == HAL_UART_STATE_BUSY_RX)
{
huart->State = HAL_UART_STATE_BUSY_TX_RX;
}
@@ -598,33 +619,33 @@
{
huart->State = HAL_UART_STATE_BUSY_TX;
}
-
+
huart->TxXferSize = Size;
huart->TxXferCount = Size;
while(huart->TxXferCount > 0)
{
huart->TxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
}
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
tmp = (uint16_t*) pData;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
pData += 2;
}
else
{
- huart->Instance->TDR = (*pData++ & (uint8_t)0xFF);
- }
+ huart->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ }
}
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
- {
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
}
/* Check if a non-blocking receive Process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
{
huart->State = HAL_UART_STATE_BUSY_RX;
}
@@ -632,10 +653,10 @@
{
huart->State = HAL_UART_STATE_READY;
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
+
return HAL_OK;
}
else
@@ -645,31 +666,31 @@
}
/**
- * @brief Receive an amount of data in blocking mode
- * @param huart: uart handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout : Timeout duration
+ * @brief Receive an amount of data in blocking mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @param Timeout: Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
+{
uint16_t* tmp;
uint16_t uhMask;
if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
- {
- if((pData == NULL ) || (Size == 0))
+ {
+ if((pData == NULL ) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(huart);
-
+
huart->ErrorCode = HAL_UART_ERROR_NONE;
/* Check if a non-blocking transmit process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX)
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
{
huart->State = HAL_UART_STATE_BUSY_TX_RX;
}
@@ -677,22 +698,22 @@
{
huart->State = HAL_UART_STATE_BUSY_RX;
}
-
- huart->RxXferSize = Size;
+
+ huart->RxXferSize = Size;
huart->RxXferCount = Size;
-
+
/* Computation of UART mask to apply to RDR register */
- __HAL_UART_MASK_COMPUTATION(huart);
+ UART_MASK_COMPUTATION(huart);
uhMask = huart->Mask;
-
+
/* as long as data have to be received */
while(huart->RxXferCount > 0)
{
huart->RxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
- }
+ }
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
tmp = (uint16_t*) pData ;
@@ -701,56 +722,56 @@
}
else
{
- *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
- }
+ *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ }
}
-
+
/* Check if a non-blocking transmit Process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
{
huart->State = HAL_UART_STATE_BUSY_TX;
}
else
{
huart->State = HAL_UART_STATE_READY;
- }
+ }
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Send an amount of data in interrupt mode
- * @param huart: uart handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @brief Send an amount of data in interrupt mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
+{
if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(huart);
-
+
huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
-
+
huart->ErrorCode = HAL_UART_ERROR_NONE;
/* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_RX)
+ if(huart->State == HAL_UART_STATE_BUSY_RX)
{
huart->State = HAL_UART_STATE_BUSY_TX_RX;
}
@@ -758,53 +779,53 @@
{
huart->State = HAL_UART_STATE_BUSY_TX;
}
-
+
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
-
+
/* Process Unlocked */
- __HAL_UNLOCK(huart);
-
+ __HAL_UNLOCK(huart);
+
/* Enable the UART Transmit Data Register Empty Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Receive an amount of data in interrupt mode
- * @param huart: uart handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
+ * @brief Receive an amount of data in interrupt mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
+{
if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(huart);
-
+
huart->pRxBuffPtr = pData;
huart->RxXferSize = Size;
huart->RxXferCount = Size;
-
+
/* Computation of UART mask to apply to RDR register */
- __HAL_UART_MASK_COMPUTATION(huart);
-
+ UART_MASK_COMPUTATION(huart);
+
huart->ErrorCode = HAL_UART_ERROR_NONE;
/* Check if a transmit process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX)
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
{
huart->State = HAL_UART_STATE_BUSY_TX_RX;
}
@@ -812,55 +833,55 @@
{
huart->State = HAL_UART_STATE_BUSY_RX;
}
-
+
/* Enable the UART Parity Error Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_PE);
-
+
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
-
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
+
/* Enable the UART Data Register not empty Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Send an amount of data in DMA mode
- * @param huart: uart handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @brief Send an amount of data in DMA mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
-
+
if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX))
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(huart);
-
+
huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
- huart->TxXferCount = Size;
-
+ huart->TxXferCount = Size;
+
huart->ErrorCode = HAL_UART_ERROR_NONE;
/* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_RX)
+ if(huart->State == HAL_UART_STATE_BUSY_RX)
{
huart->State = HAL_UART_STATE_BUSY_TX_RX;
}
@@ -868,64 +889,67 @@
{
huart->State = HAL_UART_STATE_BUSY_TX;
}
-
+
/* Set the UART DMA transfer complete callback */
huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-
+
/* Set the UART DMA Half transfer complete callback */
- huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
/* Set the DMA error callback */
huart->hdmatx->XferErrorCallback = UART_DMAError;
/* Enable the UART transmit DMA channel */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);
-
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
huart->Instance->CR3 |= USART_CR3_DMAT;
-
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Receive an amount of data in DMA mode
- * @param huart: uart handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @note When the UART parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position)
+ * @brief Receive an amount of data in DMA mode.
+ * @param huart: UART handle.
+ * @param pData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
-
+
if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX))
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(huart);
-
+
huart->pRxBuffPtr = pData;
huart->RxXferSize = Size;
-
+
huart->ErrorCode = HAL_UART_ERROR_NONE;
/* Check if a transmit process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX)
+ if(huart->State == HAL_UART_STATE_BUSY_TX)
{
huart->State = HAL_UART_STATE_BUSY_TX_RX;
}
@@ -933,13 +957,13 @@
{
huart->State = HAL_UART_STATE_BUSY_RX;
}
-
+
/* Set the UART DMA transfer complete callback */
huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
+
/* Set the UART DMA Half transfer complete callback */
huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
+
/* Set the DMA error callback */
huart->hdmarx->XferErrorCallback = UART_DMAError;
@@ -947,31 +971,31 @@
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the UART CR3 register */
huart->Instance->CR3 |= USART_CR3_DMAR;
-
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Pauses the DMA Transfer.
- * @param huart: UART handle
- * @retval None
+ * @brief Pause the DMA Transfer.
+ * @param huart: UART handle.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
-
+
if(huart->State == HAL_UART_STATE_BUSY_TX)
{
/* Disable the UART DMA Tx request */
@@ -989,23 +1013,23 @@
/* Disable the UART DMA Rx request */
huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief Resumes the DMA Transfer.
- * @param huart: UART handle
- * @retval None
+ * @brief Resume the DMA Transfer.
+ * @param huart: UART handle.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
-
+
if(huart->State == HAL_UART_STATE_BUSY_TX)
{
/* Enable the UART DMA Tx request */
@@ -1013,42 +1037,49 @@
}
else if(huart->State == HAL_UART_STATE_BUSY_RX)
{
+ /* Clear the Overrun flag before resumming the Rx transfer*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
/* Enable the UART DMA Rx request */
huart->Instance->CR3 |= USART_CR3_DMAR;
}
else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
{
+ /* Clear the Overrun flag before resumming the Rx transfer*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
/* Enable the UART DMA Rx request before the DMA Tx request */
huart->Instance->CR3 |= USART_CR3_DMAR;
+
/* Enable the UART DMA Tx request */
huart->Instance->CR3 |= USART_CR3_DMAT;
}
- /* If the UART peripheral is still not enabled, enable it */
- if ((huart->Instance->CR1 & USART_CR1_UE) == 0)
- {
- /* Enable UART peripheral */
- __HAL_UART_ENABLE(huart);
- }
-
- /* TEACK and/or REACK to check before moving huart->State to Ready */
- return (UART_CheckIdleState(huart));
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
}
/**
- * @brief Stops the DMA Transfer.
- * @param huart: UART handle
- * @retval None
+ * @brief Stop the DMA Transfer.
+ * @param huart: UART handle.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
{
- /* Process Locked */
- __HAL_LOCK(huart);
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+ HAL_UART_TxHalfCpltCallback() / HAL_UART_RxHalfCpltCallback ():
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
+ generated if the DMA transfer interruption occurs at the middle or at the end of the stream
+ and the corresponding call back is executed.
+ */
/* Disable the UART Tx/Rx DMA requests */
huart->Instance->CR3 &= ~USART_CR3_DMAT;
huart->Instance->CR3 &= ~USART_CR3_DMAR;
-
+
/* Abort the UART DMA tx channel */
if(huart->hdmatx != NULL)
{
@@ -1059,219 +1090,218 @@
{
HAL_DMA_Abort(huart->hdmarx);
}
-
- /* Disable UART peripheral */
- __HAL_UART_DISABLE(huart);
-
+
huart->State = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
+
return HAL_OK;
}
-
+
/**
- * @brief Tx Transfer completed callbacks
- * @param huart: uart handle
+ * @brief Tx Transfer completed callback.
+ * @param huart: UART handle.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback can be implemented in the user file
- */
+ the HAL_UART_TxCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief Tx Half Transfer completed callbacks.
- * @param huart: UART handle
+ * @brief Tx Half Transfer completed callback.
+ * @param huart: UART handle.
* @retval None
*/
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
{
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_TxHalfCpltCallback can be implemented in the user file
- */
+ the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief Rx Transfer completed callbacks
- * @param huart: uart handle
+ * @brief Rx Transfer completed callback.
+ * @param huart: UART handle.
* @retval None
*/
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_RxCpltCallback can be implemented in the user file
+ the HAL_UART_RxCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief Rx Half Transfer completed callbacks.
- * @param huart: UART handle
+ * @brief Rx Half Transfer completed callback.
+ * @param huart: UART handle.
* @retval None
*/
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
{
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_RxHalfCpltCallback can be implemented in the user file
+ the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief UART error callbacks
- * @param huart: uart handle
+ * @brief UART error callback.
+ * @param huart: UART handle.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_ErrorCallback can be implemented in the user file
- */
+ the HAL_UART_ErrorCallback can be implemented in the user file.
+ */
}
/**
* @}
- */
+ */
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
- * @brief UART control functions
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @brief UART control functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to control the UART.
- (+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral.
(+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
(+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
(+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
- (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
- (+) HAL_UART_EnableStopMode() API enables the UART to wake up the MCU from stop mode
- (+) HAL_UART_DisableStopMode() API disables the above functionality
- (+) UART_SetConfig() API configures the UART peripheral
- (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
- (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
- (+) UART_Wakeup_AddressConfig() API configures the wake-up from stop mode parameters
- (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
- (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+ (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+ (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
@endverbatim
* @{
*/
/**
- * @brief Enable UART in mute mode (doesn't mean UART enters mute mode;
- * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)
- * @param huart: UART handle
+ * @brief Enable UART in mute mode (does not mean UART enters mute mode;
+ * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+ * @param huart: UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
-{
+{
/* Process Locked */
__HAL_LOCK(huart);
-
+
huart->State = HAL_UART_STATE_BUSY;
-
+
/* Enable USART mute mode by setting the MME bit in the CR1 register */
huart->Instance->CR1 |= USART_CR1_MME;
-
+
huart->State = HAL_UART_STATE_READY;
-
+
return (UART_CheckIdleState(huart));
}
/**
- * @brief Disable UART mute mode (doesn't mean it actually wakes up the software,
+ * @brief Disable UART mute mode (does not mean the UART actually exits mute mode
* as it may not have been in mute mode at this very moment).
- * @param huart: uart handle
+ * @param huart: UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
-{
+{
/* Process Locked */
__HAL_LOCK(huart);
-
+
huart->State = HAL_UART_STATE_BUSY;
-
+
/* Disable USART mute mode by clearing the MME bit in the CR1 register */
huart->Instance->CR1 &= ~(USART_CR1_MME);
-
+
huart->State = HAL_UART_STATE_READY;
-
+
return (UART_CheckIdleState(huart));
}
/**
* @brief Enter UART mute mode (means UART actually enters mute mode).
- * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
- * @param huart: uart handle
- * @retval HAL status
+ * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+ * @param huart: UART handle.
+ * @retval None
*/
void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
-{
+{
__HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
}
/**
- * @brief Enables the UART transmitter and disables the UART receiver.
- * @param huart: UART handle
+ * @brief Enable the UART transmitter and disable the UART receiver.
+ * @param huart: UART handle.
* @retval HAL status
- * @retval None
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->State = HAL_UART_STATE_BUSY;
-
+
/* Clear TE and RE bits */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
/* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
SET_BIT(huart->Instance->CR1, USART_CR1_TE);
-
+
huart->State = HAL_UART_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief Enables the UART receiver and disables the UART transmitter.
- * @param huart: UART handle
- * @retval HAL status
+ * @brief Enable the UART receiver and disable the UART transmitter.
+ * @param huart: UART handle.
+ * @retval HAL status.
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
{
/* Process Locked */
__HAL_LOCK(huart);
huart->State = HAL_UART_STATE_BUSY;
-
+
/* Clear TE and RE bits */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
/* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
SET_BIT(huart->Instance->CR1, USART_CR1_RE);
-
+
huart->State = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
- return HAL_OK;
+ return HAL_OK;
}
/**
* @}
- */
-
-/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
+ */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief UART Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Return the UART handle state.
+ (+) Return the UART handle error code
+
+@endverbatim
* @{
*/
/**
- * @brief return the UART state
- * @param huart: uart handle
+ * @brief Return the UART handle state.
+ * @param huart : pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
* @retval HAL state
*/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
@@ -1280,7 +1310,7 @@
}
/**
-* @brief Return the UART error code
+* @brief Return the UART handle error code.
* @param huart : pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART.
* @retval UART Error Code
@@ -1289,187 +1319,268 @@
{
return huart->ErrorCode;
}
+/**
+ * @}
+ */
/**
* @}
- */
-
-/**
- * @}
- */
-
+ */
+
/** @defgroup UART_Private_Functions UART Private Functions
* @{
*/
-
+
/**
- * @brief Send an amount of data in interrupt mode
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_UART_Transmit_IT()
- * @param huart: UART handle
+ * @brief Configure the UART peripheral.
+ * @param huart: UART handle.
* @retval HAL status
*/
-HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
- uint16_t* tmp;
+ uint32_t tmpreg = 0x00000000;
+ UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
+ uint16_t brrtemp = 0x0000;
+ uint16_t usartdiv = 0x0000;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ assert_param(IS_UART_PARITY(huart->Init.Parity));
+ assert_param(IS_UART_MODE(huart->Init.Mode));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+ * the UART Word Length, Parity, Mode and oversampling:
+ * set the M bits according to huart->Init.WordLength value
+ * set PCE and PS bits according to huart->Init.Parity value
+ * set TE and RE bits according to huart->Init.Mode value
+ * set OVER8 bit according to huart->Init.OverSampling value */
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+ * to huart->Init.StopBits value */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according
+ * to huart->Init.HwFlowCtl value
+ * - one-bit sampling method versus three samples' majority rule according
+ * to huart->Init.OneBitSampling */
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
+ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ UART_GETCLOCKSOURCE(huart, clocksource);
- if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
+ /* Check UART Over Sampling to set Baud Rate Register */
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
{
-
- if(huart->TxXferCount == 0)
+ switch (clocksource)
{
- /* Disable the UART Transmit Data Register Empty Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-
- /* Enable the UART Transmit Complete Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
-
- return HAL_OK;
+ case UART_CLOCKSOURCE_PCLK1:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
}
- else
- {
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) huart->pTxBuffPtr;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- huart->pTxBuffPtr += 2;
- }
- else
- {
- huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF);
- }
- huart->TxXferCount--;
-
- return HAL_OK;
- }
+ brrtemp = usartdiv & 0xFFF0;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
+ huart->Instance->BRR = brrtemp;
}
else
{
- return HAL_BUSY;
+ switch (clocksource)
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_SYSCLK:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_LSE:
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
+ break;
+ case UART_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+ }
+
+ return ret;
+
+}
+
+/**
+ * @brief Configure the UART peripheral advanced features.
+ * @param huart: UART handle.
+ * @retval None
+ */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure auto Baud rate detection scheme */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ {
+ assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ /* set auto Baudrate detection parameters if detection is enabled */
+ if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ {
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ }
+ }
+
+ /* if required, configure MSB first on communication line */
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
}
}
/**
- * @brief Receive an amount of data in interrupt mode
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart: UART handle
- * @retval HAL status
- */
-HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
-{
- uint16_t* tmp;
- uint16_t uhMask = huart->Mask;
-
- if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
- {
-
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) huart->pRxBuffPtr ;
- *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
- huart->pRxBuffPtr +=2;
- }
- else
- {
- *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
- }
-
- if(--huart->RxXferCount == 0)
- {
- __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-
- /* Check if a transmit Process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
- else
- {
- /* Disable the UART Parity Error Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
- huart->State = HAL_UART_STATE_READY;
- }
-
- HAL_UART_RxCpltCallback(huart);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Check the UART Idle State
- * @param huart: uart handle
+ * @brief Check the UART Idle State.
+ * @param huart: UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
-
- /* Check if the Transmitter is enabled */
- if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+
+ /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
+ Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
+ */
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+ if (IS_UART_WAKEUP_INSTANCE(huart->Instance))
{
- /* Wait until TEACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout Occured */
- return HAL_TIMEOUT;
- }
- }
- /* Check if the Receiver is enabled */
- if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout Occured */
- return HAL_TIMEOUT;
+ /* Check if the Transmitter is enabled */
+ if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, UART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the Receiver is enabled */
+ if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, UART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
}
}
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/* Initialize the UART State */
- huart->State= HAL_UART_STATE_READY;
+ huart->State= HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
+
return HAL_OK;
}
+
/**
- * @brief This function handles UART Communication Timeout.
- * @param huart: UART handle
+ * @brief Handle UART Communication Timeout.
+ * @param huart: UART handle.
* @param Flag: specifies the UART flag to check.
- * @param Status: The new Flag status (SET or RESET).
- * @param Timeout: Timeout duration
+ * @param Status: the Flag status (SET or RESET).
+ * @param Timeout: Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
/* Wait until flag is set */
if(Status == RESET)
- {
+ {
while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
@@ -1494,7 +1605,7 @@
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
@@ -1512,49 +1623,41 @@
}
}
}
- return HAL_OK;
+ return HAL_OK;
}
/**
- * @brief DMA UART transmit process complete callback
- * @param hdma: DMA handle
+ * @brief DMA UART transmit process complete callback.
+ * @param hdma: DMA handle.
* @retval None
*/
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- huart->TxXferCount = 0;
- /* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the UART CR3 register */
- huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ huart->TxXferCount = 0;
- /* Wait for UART TC Flag */
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, HAL_UART_TXDMA_TIMEOUTVALUE) != HAL_OK)
- {
- /* Timeout Occured */
- huart->State = HAL_UART_STATE_TIMEOUT;
- HAL_UART_ErrorCallback(huart);
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the UART CR3 register */
+ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
}
+ /* DMA Circular mode */
else
{
- /* No Timeout */
- /* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_READY;
- }
HAL_UART_TxCpltCallback(huart);
}
+
}
/**
- * @brief DMA UART transmit process half complete callback
- * @param hdma : DMA handle
+ * @brief DMA UART transmit process half complete callback.
+ * @param hdma : DMA handle.
* @retval None
*/
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1565,49 +1668,55 @@
}
/**
- * @brief DMA UART receive process complete callback
- * @param hdma: DMA handle
+ * @brief DMA UART receive process complete callback.
+ * @param hdma: DMA handle.
* @retval None
*/
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- huart->RxXferCount = 0;
-
- /* Disable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
- huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
- /* Check if a transmit Process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
{
- huart->State = HAL_UART_STATE_BUSY_TX;
+ huart->RxXferCount = 0;
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the UART CR3 register */
+ huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+
+ /* Check if a transmit Process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+ else
+ {
+ huart->State = HAL_UART_STATE_READY;
+ }
}
- else
- {
- huart->State = HAL_UART_STATE_READY;
- }
+
HAL_UART_RxCpltCallback(huart);
}
/**
- * @brief DMA UART receive process half complete callback
- * @param hdma : DMA handle
+ * @brief DMA UART receive process half complete callback.
+ * @param hdma : DMA handle.
* @retval None
*/
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- HAL_UART_RxHalfCpltCallback(huart);
+ HAL_UART_RxHalfCpltCallback(huart);
}
/**
- * @brief DMA UART communication error callback
- * @param hdma: DMA handle
+ * @brief DMA UART communication error callback.
+ * @param hdma: DMA handle.
* @retval None
*/
-static void UART_DMAError(DMA_HandleTypeDef *hdma)
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
huart->RxXferCount = 0;
@@ -1618,187 +1727,147 @@
}
/**
- * @brief Configure the UART peripheral
- * @param huart: uart handle
- * @retval None
+ * @brief Send an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart: UART handle.
+ * @retval HAL status
*/
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
{
- uint32_t tmpreg = 0x00000000;
- UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
- uint16_t brrtemp = 0x0000;
- uint16_t usartdiv = 0x0000;
- HAL_StatusTypeDef ret = HAL_OK;
-
- /* Check the parameters */
- assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
- assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
- assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
- assert_param(IS_UART_PARITY(huart->Init.Parity));
- assert_param(IS_UART_MODE(huart->Init.Mode));
- assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
- assert_param(IS_UART_ONEBIT_SAMPLING(huart->Init.OneBitSampling));
+ uint16_t* tmp;
+
+ if ((huart->State == HAL_UART_STATE_BUSY_TX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
+ {
+
+ if(huart->TxXferCount == 0)
+ {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) huart->pTxBuffPtr;
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ huart->pTxBuffPtr += 2;
+ }
+ else
+ {
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF);
+ }
+
+ huart->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
- * the UART Word Length, Parity, Mode and oversampling:
- * set the M bits according to huart->Init.WordLength value
- * set PCE and PS bits according to huart->Init.Parity value
- * set TE and RE bits according to huart->Init.Mode value
- * set OVER8 bit according to huart->Init.OverSampling value */
- tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable the UART Transmit Complete Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
- /*-------------------------- USART CR2 Configuration -----------------------*/
- /* Configure the UART Stop Bits: Set STOP[13:12] bits according
- * to huart->Init.StopBits value */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* Configure
- * - UART HardWare Flow Control: set CTSE and RTSE bits according
- * to huart->Init.HwFlowCtl value
- * - one-bit sampling method versus three samples' majority rule according
- * to huart->Init.OneBitSampling */
- tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
- MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- __HAL_UART_GETCLOCKSOURCE(huart, clocksource);
-
- /* Check the Over Sampling to set Baud Rate Register */
- if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ /* Check if a receive process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
{
- switch (clocksource)
- {
- case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(__DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(__DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(__DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(__DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
-
- brrtemp = usartdiv & 0xFFF0;
- brrtemp |= (uint16_t) ((usartdiv & (uint16_t)0x000F) >> 1U);
- huart->Instance->BRR = brrtemp;
+ huart->State = HAL_UART_STATE_BUSY_RX;
}
else
{
- switch (clocksource)
- {
- case UART_CLOCKSOURCE_PCLK1:
- huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_HSI:
- huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_SYSCLK:
- huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_LSE:
- huart->Instance->BRR = (uint16_t)(__DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
- break;
- case UART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
- }
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State = HAL_UART_STATE_READY;
}
- return ret;
+ HAL_UART_TxCpltCallback(huart);
+ return HAL_OK;
}
+
/**
- * @brief Configure the UART peripheral advanced feautures
- * @param huart: uart handle
- * @retval None
+ * @brief Receive an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart: UART handle.
+ * @retval HAL status
*/
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
-{
- /* Check whether the set of advanced features to configure is properly set */
- assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
-
- /* if required, configure TX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- }
-
- /* if required, configure RX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
- }
-
- /* if required, configure data inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
- }
-
- /* if required, configure RX/TX pins swap */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
+{
+ uint16_t* tmp;
+ uint16_t uhMask = huart->Mask;
+
+ if((huart->State == HAL_UART_STATE_BUSY_RX) || (huart->State == HAL_UART_STATE_BUSY_TX_RX))
{
- assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- }
-
- /* if required, configure RX overrun detection disabling */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- {
- assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- }
-
- /* if required, configure DMA disabling on reception error */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) huart->pRxBuffPtr ;
+ *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
+ huart->pRxBuffPtr +=2;
+ }
+ else
+ {
+ *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ }
+
+ if(--huart->RxXferCount == 0)
+ {
+ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+
+ /* Check if a transmit Process is ongoing or not */
+ if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
+ {
+ huart->State = HAL_UART_STATE_BUSY_TX;
+ }
+ else
+ {
+ /* Disable the UART Parity Error Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+ huart->State = HAL_UART_STATE_READY;
+ }
+
+ HAL_UART_RxCpltCallback(huart);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
}
-
- /* if required, configure auto Baud rate detection scheme */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ else
{
- assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- /* set auto Baudrate detection parameters if detection is enabled */
- if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
- {
- assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
- }
- }
-
- /* if required, configure MSB first on communication line */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- {
- assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
- MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+ return HAL_BUSY;
}
}
/**
* @}
*/
-
+
#endif /* HAL_UART_MODULE_ENABLED */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_uart.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -52,17 +52,16 @@
/** @addtogroup UART
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup UART_Exported_Types UART Exported Types
* @{
- */
-
+ */
-/**
- * @brief UART Init Structure definition
- */
+/**
+ * @brief UART Init Structure definition
+ */
typedef struct
{
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
@@ -70,7 +69,7 @@
- If oversampling is 16 or in LIN mode (LIN mode not available on F030xx devices),
Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
- If oversampling is 8,
- Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
@@ -86,64 +85,66 @@
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
-
+
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref UART_Mode */
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref UART_Hardware_Flow_Control */
-
- uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
- This parameter can be a value of @ref UART_Over_Sampling */
-
+
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
+ This parameter can be a value of @ref UART_Over_Sampling */
+
uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
Selecting the single sample method increases the receiver tolerance to clock
- deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+ deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
}UART_InitTypeDef;
-/**
- * @brief UART Advanced Features initalization structure definition
+/**
+ * @brief UART Advanced Features initalization structure definition
*/
-typedef struct
+typedef struct
{
uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
Advanced Features may be initialized at the same time .
This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */
-
+
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
This parameter can be a value of @ref UART_Tx_Inv */
-
+
uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
This parameter can be a value of @ref UART_Rx_Inv */
uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
vs negative/inverted logic).
This parameter can be a value of @ref UART_Data_Inv */
-
- uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
This parameter can be a value of @ref UART_Rx_Tx_Swap */
-
- uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
This parameter can be a value of @ref UART_Overrun_Disable */
-
- uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
+
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */
-
- uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
- This parameter can be a value of @ref UART_AutoBaudRate_Enable */
-
- uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
- detection is carried out.
+
+ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
+ This parameter can be a value of @ref UART_AutoBaudRate_Enable */
+
+ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
+ detection is carried out.
This parameter can be a value of @ref UARTEx_AutoBaud_Rate_Mode */
-
- uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
This parameter can be a value of @ref UART_MSB_First */
} UART_AdvFeatureInitTypeDef;
-/**
- * @brief HAL UART State structures definition
- */
+
+
+/**
+ * @brief HAL UART State structures definition
+ */
typedef enum
{
HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
@@ -165,12 +166,12 @@
UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
UART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
- UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
+ UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
}UART_ClockSourceTypeDef;
-/**
- * @brief UART handle Structure definition
- */
+/**
+ * @brief UART handle Structure definition
+ */
typedef struct
{
USART_TypeDef *Instance; /*!< UART registers base address */
@@ -199,19 +200,18 @@
HAL_LockTypeDef Lock; /*!< Locking object */
- HAL_UART_StateTypeDef State; /*!< UART communication state */
-
- __IO uint32_t ErrorCode; /*!< UART Error code
- This parameter can be a value of @ref UART_Error */
-
+ __IO HAL_UART_StateTypeDef State; /*!< UART communication state */
+
+ __IO uint32_t ErrorCode; /*!< UART Error code */
+
}UART_HandleTypeDef;
/**
* @}
*/
-
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported constants
+/** @defgroup UART_Exported_Constants UART Exported Constants
* @{
*/
@@ -234,60 +234,46 @@
#define UART_STOPBITS_1 ((uint32_t)0x0000)
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
- ((STOPBITS) == UART_STOPBITS_2) || \
- ((STOPBITS) == UART_STOPBITS_1_5))
/**
* @}
- */
+ */
/** @defgroup UART_Parity UART Parity
* @{
- */
-#define UART_PARITY_NONE ((uint32_t)0x0000)
-#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
- ((PARITY) == UART_PARITY_EVEN) || \
- ((PARITY) == UART_PARITY_ODD))
+ */
+#define UART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */
+#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
+#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
/**
* @}
- */
+ */
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
* @{
- */
-#define UART_HWCONTROL_NONE ((uint32_t)0x0000)
-#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
-#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
-#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == UART_HWCONTROL_NONE) || \
- ((CONTROL) == UART_HWCONTROL_RTS) || \
- ((CONTROL) == UART_HWCONTROL_CTS) || \
- ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+ */
+#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) /*!< No hardware control */
+#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /*!< Request To Send */
+#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /*!< Clear To Send */
+#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< Request and Clear To Send */
/**
* @}
*/
/** @defgroup UART_Mode UART Transfer Mode
* @{
- */
-#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
-#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
-#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((MODE) != (uint32_t)0x00))
+ */
+#define UART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
+#define UART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
+#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
/**
* @}
*/
-
- /** @defgroup UART_State UART State
+
+/** @defgroup UART_State UART State
* @{
- */
-#define UART_STATE_DISABLE ((uint32_t)0x0000)
-#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
-#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
- ((STATE) == UART_STATE_ENABLE))
+ */
+#define UART_STATE_DISABLE ((uint32_t)0x00000000) /*!< UART disabled */
+#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< UART enabled */
/**
* @}
*/
@@ -295,55 +281,35 @@
/** @defgroup UART_Over_Sampling UART Over Sampling
* @{
*/
-#define UART_OVERSAMPLING_16 ((uint32_t)0x0000)
-#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
-#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
- ((SAMPLING) == UART_OVERSAMPLING_8))
+#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */
/**
* @}
- */
+ */
/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
* @{
*/
-#define UART_ONEBIT_SAMPLING_DISABLED ((uint32_t)0x0000)
-#define UART_ONEBIT_SAMPLING_ENABLED ((uint32_t)USART_CR3_ONEBIT)
-#define IS_UART_ONEBIT_SAMPLING(ONEBIT) (((ONEBIT) == UART_ONEBIT_SAMPLING_DISABLED) || \
- ((ONEBIT) == UART_ONEBIT_SAMPLING_ENABLED))
+#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enable */
/**
* @}
- */
-
+ */
-/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
+/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
* @{
*/
-#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000)
-#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
-#define IS_UART_RECEIVER_TIMEOUT(TIMEOUT) (((TIMEOUT) == UART_RECEIVER_TIMEOUT_DISABLE) || \
- ((TIMEOUT) == UART_RECEIVER_TIMEOUT_ENABLE))
+#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) /*!< UART receiver timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< UART receiver timeout enable */
/**
* @}
- */
+ */
-/** @defgroup UART_One_Bit UART One Bit sampling
- * @{
- */
-#define UART_ONE_BIT_SAMPLE_DISABLED ((uint32_t)0x00000000)
-#define UART_ONE_BIT_SAMPLE_ENABLED ((uint32_t)USART_CR3_ONEBIT)
-#define IS_UART_ONEBIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLED) || \
- ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLED))
-/**
- * @}
- */
-
/** @defgroup UART_DMA_Tx UART DMA Tx
* @{
*/
-#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000)
-#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
-#define IS_UART_DMA_TX(DMATX) (((DMATX) == UART_DMA_TX_DISABLE) || \
- ((DMATX) == UART_DMA_TX_ENABLE))
+#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< UART DMA TX enabled */
/**
* @}
*/
@@ -351,10 +317,8 @@
/** @defgroup UART_DMA_Rx UART DMA Rx
* @{
*/
-#define UART_DMA_RX_DISABLE ((uint32_t)0x0000)
-#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
-#define IS_UART_DMA_RX(DMARX) (((DMARX) == UART_DMA_RX_DISABLE) || \
- ((DMARX) == UART_DMA_RX_ENABLE))
+#define UART_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< UART DMA RX enabled */
/**
* @}
*/
@@ -362,21 +326,17 @@
/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
* @{
*/
-#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000)
-#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL)
-#define IS_UART_HALF_DUPLEX(HDSEL) (((HDSEL) == UART_HALF_DUPLEX_DISABLE) || \
- ((HDSEL) == UART_HALF_DUPLEX_ENABLE))
+#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000) /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /*!< UART half-duplex enabled */
/**
* @}
- */
+ */
/** @defgroup UART_WakeUp_Address_Length UART WakeUp Address Length
* @{
*/
-#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000)
-#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7)
-#define IS_UART_ADDRESSLENGTH_DETECT(ADDRESS) (((ADDRESS) == UART_ADDRESS_DETECT_4B) || \
- ((ADDRESS) == UART_ADDRESS_DETECT_7B))
+#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000) /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */
/**
* @}
*/
@@ -384,10 +344,8 @@
/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
* @{
*/
-#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)
-#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
-#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
- ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
+#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) /*!< UART wake-up on idle line */
+#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /*!< UART wake-up on address mark */
/**
* @}
*/
@@ -416,24 +374,15 @@
/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
* @{
*/
-#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
-#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
-#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
-#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
-#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
-#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
-#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
-#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040)
-#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)
-#define IS_UART_ADVFEATURE_INIT(INIT) ((INIT) <= (UART_ADVFEATURE_NO_INIT | \
- UART_ADVFEATURE_TXINVERT_INIT | \
- UART_ADVFEATURE_RXINVERT_INIT | \
- UART_ADVFEATURE_DATAINVERT_INIT | \
- UART_ADVFEATURE_SWAP_INIT | \
- UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
- UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
- UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
- UART_ADVFEATURE_MSBFIRST_INIT))
+#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */
+#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */
+#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */
+#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */
+#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) /*!< Auto Baud rate detection initialization */
+#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */
/**
* @}
*/
@@ -441,10 +390,8 @@
/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
* @{
*/
-#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
-#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
-#define IS_UART_ADVFEATURE_TXINV(TXINV) (((TXINV) == UART_ADVFEATURE_TXINV_DISABLE) || \
- ((TXINV) == UART_ADVFEATURE_TXINV_ENABLE))
+#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
/**
* @}
*/
@@ -452,10 +399,8 @@
/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
* @{
*/
-#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
-#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
-#define IS_UART_ADVFEATURE_RXINV(RXINV) (((RXINV) == UART_ADVFEATURE_RXINV_DISABLE) || \
- ((RXINV) == UART_ADVFEATURE_RXINV_ENABLE))
+#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
/**
* @}
*/
@@ -463,10 +408,8 @@
/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
* @{
*/
-#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
-#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
-#define IS_UART_ADVFEATURE_DATAINV(DATAINV) (((DATAINV) == UART_ADVFEATURE_DATAINV_DISABLE) || \
- ((DATAINV) == UART_ADVFEATURE_DATAINV_ENABLE))
+#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
/**
* @}
*/
@@ -474,10 +417,8 @@
/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
* @{
*/
-#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
-#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
-#define IS_UART_ADVFEATURE_SWAP(SWAP) (((SWAP) == UART_ADVFEATURE_SWAP_DISABLE) || \
- ((SWAP) == UART_ADVFEATURE_SWAP_ENABLE))
+#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
/**
* @}
*/
@@ -485,10 +426,8 @@
/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
* @{
*/
-#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
-#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
-#define IS_UART_OVERRUN(OVERRUN) (((OVERRUN) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
- ((OVERRUN) == UART_ADVFEATURE_OVERRUN_DISABLE))
+#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /*!< RX overrun enable */
+#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
/**
* @}
*/
@@ -496,10 +435,8 @@
/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
* @{
*/
-#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN)
-#define IS_UART_ADVFEATURE_AUTOBAUDRATE(AUTOBAUDRATE) (((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
- ((AUTOBAUDRATE) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) /*!< RX Auto Baud rate detection enable */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /*!< RX Auto Baud rate detection disable */
/**
* @}
*/
@@ -507,10 +444,8 @@
/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
* @{
*/
-#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
-#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
-#define IS_UART_ADVFEATURE_DMAONRXERROR(DMA) (((DMA) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
- ((DMA) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /*!< DMA enable on Reception Error */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
/**
* @}
*/
@@ -518,10 +453,8 @@
/** @defgroup UART_MSB_First UART Advanced Feature MSB First
* @{
*/
-#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
-#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
-#define IS_UART_ADVFEATURE_MSBFIRST(MSBFIRST) (((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
- ((MSBFIRST) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /*!< Most significant bit sent/received first disable */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
/**
* @}
*/
@@ -529,10 +462,8 @@
/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
* @{
*/
-#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000)
-#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME)
-#define IS_UART_MUTE_MODE(MUTE) (((MUTE) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
- ((MUTE) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /*!< UART mute mode enable */
/**
* @}
*/
@@ -548,10 +479,8 @@
/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
* @{
*/
-#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000)
-#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP)
-#define IS_UART_DE_POLARITY(POLARITY) (((POLARITY) == UART_DE_POLARITY_HIGH) || \
- ((POLARITY) == UART_DE_POLARITY_LOW))
+#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /*!< Driver enable signal is active low */
/**
* @}
*/
@@ -559,7 +488,7 @@
/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
* @{
*/
-#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21)
+#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21)
/**
* @}
*/
@@ -567,50 +496,101 @@
/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
* @{
*/
-#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16)
+#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16)
/**
* @}
*/
/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
* @{
- */
-#define UART_IT_MASK ((uint32_t)0x001F)
+ */
+#define UART_IT_MASK ((uint32_t)0x001F)
/**
* @}
*/
-
+
/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
* @{
- */
-#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF
+ */
+#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF
/**
* @}
*/
+
/**
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup UART_Exported_Macros UART Exported Macros
* @{
*/
-
-/** @brief Reset UART handle state
+
+/** @brief Reset UART handle state.
* @param __HANDLE__: UART handle.
* @retval None
*/
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
-/** @brief Checks whether the specified UART flag is set or not.
+/** @brief Clear the specified UART pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg UART_CLEAR_PEF, Parity Error Clear Flag
+ * @arg UART_CLEAR_FEF, Framing Error Clear Flag
+ * @arg UART_CLEAR_NEF, Noise detected Clear Flag
+ * @arg UART_CLEAR_OREF, OverRun Error Clear Flag
+ * @arg UART_CLEAR_IDLEF, IDLE line detected Clear Flag
+ * @arg UART_CLEAR_TCF, Transmission Complete Clear Flag
+ * @arg UART_CLEAR_LBDF, LIN Break Detection Clear Flag (not available on all devices)
+ * @arg UART_CLEAR_CTSF, CTS Interrupt Clear Flag
+ * @arg UART_CLEAR_RTOF, Receiver Time Out Clear Flag
+ * @arg UART_CLEAR_EOBF, End Of Block Clear Flag (not available on all devices)
+ * @arg UART_CLEAR_CMF, Character Match Clear Flag
+ * @arg UART_CLEAR_WUF, Wake Up from stop mode Clear Flag (not available on all devices)
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the UART PE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
+
+/** @brief Clear the UART FE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
+
+/** @brief Clear the UART NE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
+
+/** @brief Clear the UART ORE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
+
+/** @brief Clear the UART IDLE pending flag.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
+/** @brief Check whether the specified UART flag is set or not.
* @param __HANDLE__: specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or
* UART peripheral (datasheet: up to four USART/UARTs)
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
- * @arg UART_FLAG_REACK: Receive enable ackowledge flag
- * @arg UART_FLAG_TEACK: Transmit enable ackowledge flag
+ * @arg UART_FLAG_REACK: Receive enable acknowledge flag
+ * @arg UART_FLAG_TEACK: Transmit enable acknowledge flag
* @arg UART_FLAG_WUF: Wake up from stop mode flag (not available on F030xx devices)
* @arg UART_FLAG_RWU: Receiver wake up flag (not available on F030xx devices)
* @arg UART_FLAG_SBKF: Send Break flag
@@ -619,7 +599,7 @@
* @arg UART_FLAG_ABRF: Auto Baud rate detection flag
* @arg UART_FLAG_ABRE: Auto Baud rate detection error flag
* @arg UART_FLAG_EOBF: End of block flag (not available on F030xx devices)
- * @arg UART_FLAG_RTOF: Receiver timeout flag
+ * @arg UART_FLAG_RTOF: Receiver timeout flag
* @arg UART_FLAG_CTS: CTS Change flag
* @arg UART_FLAG_LBD: LIN Break detection flag (not available on F030xx devices)
* @arg UART_FLAG_TXE: Transmit data register empty flag
@@ -632,9 +612,9 @@
* @arg UART_FLAG_PE: Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-/** @brief Enables the specified UART interrupt.
+/** @brief Enable the specified UART interrupt.
* @param __HANDLE__: specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or
* UART peripheral. (datasheet: up to four USART/UARTs)
@@ -657,14 +637,14 @@
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-/** @brief Disables the specified UART interrupt.
+/** @brief Disable the specified UART interrupt.
* @param __HANDLE__: specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or
* UART peripheral. (datasheet: up to four USART/UARTs)
* @param __INTERRUPT__: specifies the UART interrupt source to disable.
* This parameter can be one of the following values:
* @arg UART_IT_WUF: Wakeup from stop mode interrupt (not available on F030xx devices)
- * @arg UART_IT_CM: Character match interrupt
+ * @arg UART_IT_CM: Character match interrupt
* @arg UART_IT_CTS: CTS change interrupt
* @arg UART_IT_LBD: LIN Break detection interrupt (not available on F030xx devices)
* @arg UART_IT_TXE: Transmit Data Register empty interrupt
@@ -672,21 +652,21 @@
* @arg UART_IT_RXNE: Receive Data register not empty interrupt
* @arg UART_IT_IDLE: Idle line detection interrupt
* @arg UART_IT_PE: Parity Error interrupt
- * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg UART_IT_ERR: Error interrupt (Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
-/** @brief Checks whether the specified UART interrupt has occurred or not.
+/** @brief Check whether the specified UART interrupt has occurred or not.
* @param __HANDLE__: specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or
* UART peripheral. (datasheet: up to four USART/UARTs)
* @param __IT__: specifies the UART interrupt to check.
* This parameter can be one of the following values:
* @arg UART_IT_WUF: Wakeup from stop mode interrupt (not available on F030xx devices)
- * @arg UART_IT_CM: Character match interrupt
+ * @arg UART_IT_CM: Character match interrupt
* @arg UART_IT_CTS: CTS change interrupt
* @arg UART_IT_LBD: LIN Break detection interrupt (not available on F030xx devices)
* @arg UART_IT_TXE: Transmit Data Register empty interrupt
@@ -696,12 +676,12 @@
* @arg UART_IT_ORE: OverRun Error interrupt
* @arg UART_IT_NE: Noise Error interrupt
* @arg UART_IT_FE: Framing Error interrupt
- * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
-/** @brief Checks whether the specified UART interrupt source is enabled.
+/** @brief Check whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__: specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or
* UART peripheral. (datasheet: up to four USART/UARTs)
@@ -718,34 +698,34 @@
* @arg UART_IT_ORE: OverRun Error interrupt
* @arg UART_IT_NE: Noise Error interrupt
* @arg UART_IT_FE: Framing Error interrupt
- * @arg UART_IT_PE: Parity Error interrupt
+ * @arg UART_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
-/** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag.
+/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__: specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3 or 4 to select the USART or
* UART peripheral. (datasheet: up to four USART/UARTs)
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
- * @arg UART_CLEAR_PEF: Parity Error Clear Flag
- * @arg UART_CLEAR_FEF: Framing Error Clear Flag
- * @arg UART_CLEAR_NEF: Noise detected Clear Flag
- * @arg UART_CLEAR_OREF: OverRun Error Clear Flag
- * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag
- * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag
+ * @arg UART_CLEAR_PEF: Parity Error Clear Flag
+ * @arg UART_CLEAR_FEF: Framing Error Clear Flag
+ * @arg UART_CLEAR_NEF: Noise detected Clear Flag
+ * @arg UART_CLEAR_OREF: OverRun Error Clear Flag
+ * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag
+ * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag
* @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag (not available on F030xx devices)
- * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag
- * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag
- * @arg UART_CLEAR_EOBF: End Of Block Clear Flag (not available on F030xx devices)
- * @arg UART_CLEAR_CMF: Character Match Clear Flag
+ * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag
+ * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag
+ * @arg UART_CLEAR_EOBF: End Of Block Clear Flag (not available on F030xx devices)
+ * @arg UART_CLEAR_CMF: Character Match Clear Flag
* @arg UART_CLEAR_WUF: Wake Up from stop mode Clear Flag (not available on F030xx devices)
* @retval None
*/
-#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific UART request flag.
* @param __HANDLE__: specifies the UART Handle.
@@ -753,29 +733,113 @@
* UART peripheral. (datasheet: up to four USART/UARTs)
* @param __REQ__: specifies the request flag to set
* This parameter can be one of the following values:
- * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
- * @arg UART_SENDBREAK_REQUEST: Send Break Request
- * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request
- * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
- * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request (not available on F030xx devices)
+ * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
+ * @arg UART_SENDBREAK_REQUEST: Send Break Request
+ * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request
+ * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
+ * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request (not available on F030xx devices)
* @retval None
*/
-#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the UART one bit sample method.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-/** @brief Enable UART
+/** @brief Disable the UART one bit sample method.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable UART.
* @param __HANDLE__: specifies the UART Handle.
* The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral
* @retval None
- */
+ */
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-/** @brief Disable UART
+/** @brief Disable UART.
* @param __HANDLE__: specifies the UART Handle.
* The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral
* @retval None
*/
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+/** @brief Enable CTS flow control.
+ * @note This macro allows to enable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
+ } while(0)
+
+/** @brief Disable CTS flow control.
+ * @note This macro allows to disable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
+ } while(0)
+
+/** @brief Enable RTS flow control.
+ * @note This macro allows to enable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
+ } while(0)
+
+/** @brief Disable RTS flow control.
+ * @note This macro allows to disable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
+ } while(0)
+
/**
* @}
*/
@@ -785,54 +849,256 @@
* @{
*/
-/** @brief BRR division operation to set BRR register in 8-bit oversampling mode
- * @param _PCLK_: UART clock
- * @param _BAUD_: Baud rate set by the user
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
+ * @param __PCLK__: UART clock.
+ * @param __BAUD__: Baud rate set by the user.
* @retval Division result
*/
-#define __DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*2)/((_BAUD_)))
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) (((__PCLK__)*2)/((__BAUD__)))
-/** @brief BRR division operation to set BRR register in 16-bit oversampling mode
- * @param _PCLK_: UART clock
- * @param _BAUD_: Baud rate set by the user
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
+ * @param __PCLK__: UART clock.
+ * @param __BAUD__: Baud rate set by the user.
* @retval Division result
*/
-#define __DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_)))
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__))/((__BAUD__)))
/** @brief Check UART Baud rate
- * @param BAUDRATE: Baudrate specified by the user
+ * @param __BAUDRATE__: Baudrate specified by the user.
* The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz)
* divided by the smallest oversampling used on the USART (i.e. 8)
+ * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
+ */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)
+
+/** @brief Check UART assertion time.
+ * @param __TIME__: 5-bit value assertion time.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
+
+/** @brief Check UART deassertion time.
+ * @param __TIME__: 5-bit value deassertion time.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
+
+/**
+ * @brief Ensure that UART frame number of stop bits is valid.
+ * @param __STOPBITS__: UART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) UART_STOPBITS_1_5
+ */
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
+ ((__STOPBITS__) == UART_STOPBITS_2) || \
+ ((__STOPBITS__) == UART_STOPBITS_1_5))
+
+/**
+ * @brief Ensure that UART frame parity is valid.
+ * @param __PARITY__: UART frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
+ ((__PARITY__) == UART_PARITY_EVEN) || \
+ ((__PARITY__) == UART_PARITY_ODD))
-/** @brief Check UART assertion time
- * @param TIME: 5-bit value assertion time
- * @retval Test result (TRUE or FALSE).
+/**
+ * @brief Ensure that UART hardware flow control is valid.
+ * @param __CONTROL__: UART hardware flow control.
+ * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+ */
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
+ (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_CTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+
+/**
+ * @brief Ensure that UART communication mode is valid.
+ * @param __MODE__: UART communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
+
+/**
+ * @brief Ensure that UART state is valid.
+ * @param __STATE__: UART state.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
+ ((__STATE__) == UART_STATE_ENABLE))
+
+/**
+ * @brief Ensure that UART oversampling is valid.
+ * @param __SAMPLING__: UART oversampling.
+ * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
*/
-#define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F)
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == UART_OVERSAMPLING_8))
+
+/**
+ * @brief Ensure that UART frame sampling is valid.
+ * @param __ONEBIT__: UART frame sampling.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+ * @brief Ensure that Address Length detection parameter is valid.
+ * @param __ADDRESS__: UART Adress length value.
+ * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+ */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+ * @brief Ensure that UART receiver timeout setting is valid.
+ * @param __TIMEOUT__: UART receiver timeout setting.
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+ */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/**
+ * @brief Ensure that UART DMA TX state is valid.
+ * @param __DMATX__: UART DMA TX state.
+ * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+ */
+#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \
+ ((__DMATX__) == UART_DMA_TX_ENABLE))
+
+/**
+ * @brief Ensure that UART DMA RX state is valid.
+ * @param __DMARX__: UART DMA RX state.
+ * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+ */
+#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \
+ ((__DMARX__) == UART_DMA_RX_ENABLE))
+
+/**
+ * @brief Ensure that UART half-duplex state is valid.
+ * @param __HDSEL__: UART half-duplex state.
+ * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+ */
+#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+ ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
+
+/**
+ * @brief Ensure that UART wake-up method is valid.
+ * @param __WAKEUP__: UART wake-up method .
+ * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+ */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+ ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+/**
+ * @brief Ensure that UART advanced features initialization is valid.
+ * @param __INIT__: UART advanced features initialization.
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \
+ UART_ADVFEATURE_TXINVERT_INIT | \
+ UART_ADVFEATURE_RXINVERT_INIT | \
+ UART_ADVFEATURE_DATAINVERT_INIT | \
+ UART_ADVFEATURE_SWAP_INIT | \
+ UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
+ UART_ADVFEATURE_MSBFIRST_INIT))
-/** @brief Check UART deassertion time
- * @param TIME: 5-bit value deassertion time
- * @retval Test result (TRUE or FALSE).
+/**
+ * @brief Ensure that UART frame TX inversion setting is valid.
+ * @param __TXINV__: UART frame TX inversion setting.
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+ ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame RX inversion setting is valid.
+ * @param __RXINV__: UART frame RX inversion setting.
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+ ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame data inversion setting is valid.
+ * @param __DATAINV__: UART frame data inversion setting.
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+ ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+ * @param __SWAP__: UART frame RX/TX pins swap setting.
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+ ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
+
+/**
+ * @brief Ensure that UART frame overrun setting is valid.
+ * @param __OVERRUN__: UART frame overrun setting.
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
*/
-#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)
+#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+ * @brief Ensure that UART auto Baud rate state is valid.
+ * @param __AUTOBAUDRATE__: UART auto Baud rate state.
+ * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+ ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+
+/**
+ * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+ * @param __DMA__: UART DMA enabling or disabling on error setting.
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+ * @brief Ensure that UART frame MSB first setting is valid.
+ * @param __MSBFIRST__: UART frame MSB first setting.
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+ * @brief Ensure that UART mute mode state is valid.
+ * @param __MUTE__: UART mute mode state.
+ * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+ */
+#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+ ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+
+/**
+ * @brief Ensure that UART driver enable polarity is valid.
+ * @param __POLARITY__: UART driver enable polarity.
+ * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+ */
+#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+ ((__POLARITY__) == UART_DE_POLARITY_LOW))
/**
* @}
*/
/* Include UART HAL Extension module */
-#include "stm32f0xx_hal_uart_ex.h"
+#include "stm32f0xx_hal_uart_ex.h"
/* Exported functions --------------------------------------------------------*/
-
/** @addtogroup UART_Exported_Functions UART Exported Functions
* @{
*/
-
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
@@ -848,7 +1114,7 @@
* @}
*/
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
* @{
*/
@@ -862,6 +1128,7 @@
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
@@ -876,10 +1143,10 @@
* @{
*/
-/* Peripheral Control functions ***********************************************/
-void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
@@ -887,22 +1154,23 @@
* @}
*/
-/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
/* Peripheral State and Errors functions **************************************************/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
/**
* @}
- */
+ */
/**
* @}
- */
+ */
+/* Private functions -----------------------------------------------------------*/
/** @addtogroup UART_Private_Functions
* @{
*/
@@ -910,15 +1178,16 @@
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
/**
* @}
- */
-
+ */
+
/**
* @}
- */
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,10 +2,9 @@
******************************************************************************
* @file stm32f0xx_hal_uart_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Extended UART HAL module driver.
- *
* This file provides firmware functions to manage the following extended
* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
* + Initialization and de-initialization functions
@@ -13,23 +12,21 @@
*
*
@verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The Extended UART HAL driver can be used as follows:
-
+ ==============================================================================
+ ##### UART peripheral extended features #####
+ ==============================================================================
+
(#) Declare a UART_HandleTypeDef handle structure.
- (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
- by calling the HAL_RS485Ex_Init() API.
-
+ (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -53,7 +50,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -63,7 +60,7 @@
* @{
*/
-/** @defgroup UARTEx UARTEx Extended HAL module driver
+/** @defgroup UARTEx UARTEx
* @brief UART Extended HAL module driver
* @{
*/
@@ -72,17 +69,15 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-
/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
* @{
*/
#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
-static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
/**
* @}
@@ -94,7 +89,7 @@
* @{
*/
-/** @defgroup UARTEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
+/** @defgroup UARTEx_Exported_Functions_Group1 Extended Initialization and de-initialization functions
* @brief Extended Initialization and Configuration Functions
*
@verbatim
@@ -104,29 +99,43 @@
[..]
This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
in asynchronous mode.
- (+) For the asynchronous mode only these parameters can be configured:
+ (+) For the asynchronous mode the parameters below can be configured:
(++) Baud Rate
(++) Word Length (Fixed to 8-bits only for LIN mode)
(++) Stop Bit
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible UART frame formats are as listed in the following table:
- |-----------|-----------|---------------------------------------|
- | M1M0 bits | PCE bit | UART frame |
- |-----------------------|---------------------------------------|
- | 00 | 0 | | SB | 8-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 00 | 1 | | SB | 7-bit data | PB | STB | |
- |-----------|-----------|---------------------------------------|
- | 01 | 0 | | SB | 9-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 01 | 1 | | SB | 8-bit data | PB | STB | |
- +---------------------------------------------------------------+
- | 10 | 0 | | SB | 7-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 10 | 1 | | SB | 6-bit data | PB | STB | |
- +---------------------------------------------------------------+
+ According to device capability (support or not of 7-bit word length),
+ frame length is either defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
+ Possible UART frame formats are as listed in the following table:
+
+ (+++) Table 1. UART frame format.
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M bit | PCE bit | UART frame |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | | SB | 8-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | | SB | 9-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M1 bit | M0 bit | PCE bit | UART frame |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
(++) Hardware flow control
(++) Receiver/transmitter modes
(++) Over Sampling Method
@@ -148,30 +157,29 @@
* @{
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/**
- * @brief Initializes the RS485 Driver enable feature according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle .
- * @param huart: uart handle
- * @param UART_DEPolarity: select the driver enable polarity
+ * @brief Initialize the RS485 Driver enable feature according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart: UART handle.
+ * @param Polarity: select the driver enable polarity.
* This parameter can be one of the following values:
* @arg UART_DE_POLARITY_HIGH: DE signal is active high
* @arg UART_DE_POLARITY_LOW: DE signal is active low
- * @param UART_DEAssertionTime: Driver Enable assertion time
+ * @param AssertionTime: Driver Enable assertion time:
* 5-bit value defining the time between the activation of the DE (Driver Enable)
* signal and the beginning of the start bit. It is expressed in sample time
- * units (1/8 or 1/16 bit time, depending on the oversampling rate)
- * @param UART_DEDeassertionTime: Driver Enable deassertion time
+ * units (1/8 or 1/16 bit time, depending on the oversampling rate)
+ * @param DeassertionTime: Driver Enable deassertion time:
* 5-bit value defining the time between the end of the last stop bit, in a
* transmitted message, and the de-activation of the DE (Driver Enable) signal.
* It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
- * oversampling rate).
+ * oversampling rate).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPolarity, uint32_t UART_DEAssertionTime, uint32_t UART_DEDeassertionTime)
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
{
uint32_t temp = 0x0;
-
+
/* Check the UART handle allocation */
if(huart == NULL)
{
@@ -179,62 +187,64 @@
}
/* Check the Driver Enable UART instance */
assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
-
+
/* Check the Driver Enable polarity */
- assert_param(IS_UART_DE_POLARITY(UART_DEPolarity));
-
+ assert_param(IS_UART_DE_POLARITY(Polarity));
+
/* Check the Driver Enable assertion time */
- assert_param(IS_UART_ASSERTIONTIME(UART_DEAssertionTime));
-
+ assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
/* Check the Driver Enable deassertion time */
- assert_param(IS_UART_DEASSERTIONTIME(UART_DEDeassertionTime));
-
+ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
if(huart->State == HAL_UART_STATE_RESET)
- {
- /* Init the low level hardware : GPIO, CLOCK */
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
HAL_UART_MspInit(huart);
}
-
+
huart->State = HAL_UART_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
-
+
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
- }
-
- if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ }
+
+ if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
-
+
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
- huart->Instance->CR3 |= USART_CR3_DEM;
-
+ SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
/* Set the Driver Enable polarity */
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, UART_DEPolarity);
-
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
/* Set the Driver Enable assertion and deassertion times */
- temp = (UART_DEAssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
- temp |= (UART_DEDeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+ temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
-
+
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
-
+
/* TEACK and/or REACK to check before moving huart->State to Ready */
return (UART_CheckIdleState(huart));
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)*/
#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/**
- * @brief Initializes the LIN mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle.
- * @param huart: uart handle
+ * @brief Initialize the LIN mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle .
+ * @param huart: UART handle.
* @param BreakDetectLength: specifies the LIN break detection length.
* This parameter can be one of the following values:
* @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
@@ -248,59 +258,68 @@
{
return HAL_ERROR;
}
-
- /* Check the parameters */
+
+ /* Check the LIN UART instance */
assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+ /* Check the Break detection length parameter */
assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-
+
/* LIN mode limited to 16-bit oversampling only */
if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
{
return HAL_ERROR;
}
-
- /* in LIN mode, data length is limited to 8-bit only */
- if(huart->Init.WordLength!= UART_WORDLENGTH_8B)
+ /* LIN mode limited to 8-bit data length */
+ if(huart->Init.WordLength != UART_WORDLENGTH_8B)
{
return HAL_ERROR;
}
- /* Init the low level hardware : GPIO, CLOCK, CORTEX */
- HAL_UART_MspInit(huart);
-
+ if(huart->State == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+ }
+
+ huart->State = HAL_UART_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
-
+
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
{
return HAL_ERROR;
- }
-
+ }
+
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
{
UART_AdvFeatureConfig(huart);
}
-
- /* In LIN mode, the following bits must be kept cleared:
+
+ /* In LIN mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/
huart->Instance->CR2 &= ~(USART_CR2_CLKEN);
huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);
-
+
/* Enable the LIN mode by setting the LINEN bit in the CR2 register */
huart->Instance->CR2 |= USART_CR2_LINEN;
-
+
/* Set the USART LIN Break detection length. */
MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
-
+
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
-
+
/* TEACK and/or REACK to check before moving huart->State to Ready */
return (UART_CheckIdleState(huart));
}
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+
/**
* @}
*/
@@ -320,7 +339,7 @@
(++) HAL_UART_IRQHandler()
(#) Callback provided in No_Blocking mode:
- (++) HAL_UART_WakeupCallback()
+ (++) HAL_UARTEx_WakeupCallback()
@endverbatim
* @{
@@ -328,101 +347,102 @@
/**
- * @brief This function handles UART interrupt request.
- * @param huart: uart handle
+ * @brief Handle UART interrupt request.
+ * @param huart: UART handle.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
/* UART parity error interrupt occurred -------------------------------------*/
if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET))
- {
+ {
__HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
-
+
huart->ErrorCode |= HAL_UART_ERROR_PE;
/* Set the UART state ready to be able to start again the process */
huart->State = HAL_UART_STATE_READY;
}
-
- /* UART frame error interrupt occured --------------------------------------*/
+
+ /* UART frame error interrupt occurred --------------------------------------*/
if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
- {
+ {
__HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
-
+
huart->ErrorCode |= HAL_UART_ERROR_FE;
/* Set the UART state ready to be able to start again the process */
huart->State = HAL_UART_STATE_READY;
}
-
- /* UART noise error interrupt occured --------------------------------------*/
+
+ /* UART noise error interrupt occurred --------------------------------------*/
if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
- {
+ {
__HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_NE;
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
/* Set the UART state ready to be able to start again the process */
huart->State = HAL_UART_STATE_READY;
}
-
- /* UART Over-Run interrupt occured -----------------------------------------*/
+
+ /* UART Over-Run interrupt occurred -----------------------------------------*/
if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
- {
+ {
__HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
-
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
+
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
/* Set the UART state ready to be able to start again the process */
huart->State = HAL_UART_STATE_READY;
}
-
+
/* Call UART Error Call back function if need be --------------------------*/
if(huart->ErrorCode != HAL_UART_ERROR_NONE)
{
HAL_UART_ErrorCallback(huart);
}
-
+
#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/* UART wakeup from Stop mode interrupt occurred -------------------------------------*/
if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET))
- {
+ {
__HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
/* Set the UART state ready to be able to start again the process */
huart->State = HAL_UART_STATE_READY;
- HAL_UART_WakeupCallback(huart);
+ HAL_UARTEx_WakeupCallback(huart);
}
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
-
+
/* UART in mode Receiver ---------------------------------------------------*/
if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET))
- {
+ {
UART_Receive_IT(huart);
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
-
+
/* UART in mode Transmitter ------------------------------------------------*/
if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET))
{
UART_Transmit_IT(huart);
- }
-
- /* UART in mode Transmitter ------------------------------------------------*/
+ }
+
+ /* UART in mode Transmitter (transmission end) -----------------------------*/
if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET))
{
UART_EndTransmit_IT(huart);
- }
+ }
+
}
#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/**
- * @brief UART wakeup from Stop mode callback
- * @param huart: uart handle
+ * @brief UART wakeup from Stop mode callback
+ * @param huart: UART handle
* @retval None
*/
- __weak void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart)
+ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UART_WakeupCallback can be implemented in the user file
+ the HAL_UARTEx_WakeupCallback can be implemented in the user file
*/
}
#endif /*!defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)*/
@@ -441,12 +461,12 @@
===============================================================================
[..]
This subsection provides extended functions allowing to control the UART.
- (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
- detection length to more than 4 bits for multiprocessor address mark wake up.
(+) HAL_UARTEx_StopModeWakeUpSourceConfig() API sets Wakeup from Stop mode interrupt flag selection
(+) HAL_UARTEx_EnableStopMode() API allows the UART to wake up the MCU from Stop mode as
long as UART clock is HSI or LSE
(+) HAL_UARTEx_DisableStopMode() API disables the above feature
+ (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+ detection length to more than 4 bits for multiprocessor address mark wake up.
(+) HAL_LIN_SendBreak() API transmits the break characters
@endverbatim
@@ -455,59 +475,65 @@
#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/**
- * @brief Set Wakeup from Stop mode interrupt flag selection
- * @param huart: uart handle,
+ * @brief Set Wakeup from Stop mode interrupt flag selection.
+ * @param huart: UART handle.
* @param WakeUpSelection: address match, Start Bit detection or RXNE bit status.
- * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg UART_WAKEUP_ON_ADDRESS
* @arg UART_WAKEUP_ON_STARTBIT
- * @arg UART_WAKEUP_ON_READDATA_NONEMPTY
+ * @arg UART_WAKEUP_ON_READDATA_NONEMPTY
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
{
- /* Check parameters */
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* check the wake-up from stop mode UART instance */
assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance));
+ /* check the wake-up selection parameter */
assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
-
+
/* Process Locked */
__HAL_LOCK(huart);
-
+
huart->State = HAL_UART_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the wake-up selection scheme */
MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
-
+
if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
{
- UART_Wakeup_AddressConfig(huart, WakeUpSelection);
+ UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
}
-
+
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
-
+
/* Wait until REACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- {
- return HAL_TIMEOUT;
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
}
else
{
/* Initialize the UART State */
- huart->State= HAL_UART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
- return HAL_OK;
+ huart->State = HAL_UART_STATE_READY;
}
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return status;
}
+
/**
- * @brief Enable UART Stop Mode
- * The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE
- * @param huart: uart handle
+ * @brief Enable UART Stop Mode.
+ * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+ * @param huart: UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
@@ -517,23 +543,23 @@
/* Process Locked */
__HAL_LOCK(huart);
-
+
huart->State = HAL_UART_STATE_BUSY;
-
- /* Set the USART UESM bit */
- huart->Instance->CR1 |= USART_CR1_UESM;
-
+
+ /* Set UESM bit */
+ SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
huart->State = HAL_UART_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief Disable UART Stop Mode
- * @param huart: uart handle
+ * @brief Disable UART Stop Mode.
+ * @param huart: UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
@@ -543,34 +569,32 @@
/* Process Locked */
__HAL_LOCK(huart);
-
- huart->State = HAL_UART_STATE_BUSY;
+
+ huart->State = HAL_UART_STATE_BUSY;
- /* Clear USART UESM bit */
- huart->Instance->CR1 &= ~(USART_CR1_UESM);
-
+ /* Clear UESM bit */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
huart->State = HAL_UART_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
- return HAL_OK;
+
+ return HAL_OK;
}
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
-
/**
- * @brief By default in multiprocessor mode, when the wake up method is set
- * to address mark, the UART handles only 4-bit long addresses detection.
- * This API allows to enable longer addresses detection (6-, 7- or 8-bit
- * long):
- * - 6-bit address detection in 7-bit data mode
- * - 7-bit address detection in 8-bit data mode
- * - 8-bit address detection in 9-bit data mode
- * @param huart: UART handle
+ * @brief By default in multiprocessor mode, when the wake up method is set
+ * to address mark, the UART handles only 4-bit long addresses detection;
+ * this API allows to enable longer addresses detection (6-, 7- or 8-bit
+ * long).
+ * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+ * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+ * @param huart: UART handle.
* @param AddressLength: this parameter can be one of the following values:
* @arg UART_ADDRESS_DETECT_4B: 4-bit long address
- * @arg UART_ADDRESS_DETECT_7B: 6-, 7- or 8-bit long address
+ * @arg UART_ADDRESS_DETECT_7B: 6-, 7- or 8-bit long address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
@@ -583,18 +607,18 @@
/* Check the address length parameter */
assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
-
+
huart->State = HAL_UART_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
-
+
/* Set the address length */
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
-
+
/* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
+ __HAL_UART_ENABLE(huart);
+
/* TEACK and/or REACK to check before moving huart->State to Ready */
return (UART_CheckIdleState(huart));
}
@@ -602,31 +626,30 @@
#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/**
- * @brief Transmits break characters.
- * @param huart: UART handle
+ * @brief Transmit break characters.
+ * @param huart: UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
{
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
-
+
/* Process Locked */
__HAL_LOCK(huart);
-
+
huart->State = HAL_UART_STATE_BUSY;
-
+
/* Send break characters */
- huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
-
+ huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
+
huart->State = HAL_UART_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
- return HAL_OK;
+
+ return HAL_OK;
}
-
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/**
@@ -635,49 +658,20 @@
/**
* @}
- */
+ */
/** @addtogroup UARTEx_Private_Functions
* @{
*/
-
-/**
- * @brief Wraps up transmission in non blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
- /* Disable the UART Transmit Complete Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
-
- /* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
- else
- {
- /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
- huart->State = HAL_UART_STATE_READY;
- }
-
- HAL_UART_TxCpltCallback(huart);
-
- return HAL_OK;
-}
#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/**
- * @brief Initializes the UART wake-up from stop mode parameters when triggered by address detection.
- * @param huart: uart handle
- * @param WakeUpSelection: UART wake up from stop mode parameters
- * @retval HAL status
- */
-static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+ * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+ * @param huart: UART handle.
+ * @param WakeUpSelection: UART wake up from stop mode parameters.
+ * @retval None
+ */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
{
/* Check parmeters */
assert_param(IS_UART_WAKEUP_INSTANCE(huart->Instance));
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_uart_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_uart_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of UART HAL Extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -32,7 +32,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -52,29 +52,30 @@
/** @addtogroup UARTEx
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
* @{
- */
-
-/**
- * @brief UART wake up from stop mode parameters
*/
-typedef struct
+
+/**
+ * @brief UART wake up from stop mode parameters
+ */
+typedef struct
{
uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
be filled up. */
-
+
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
This parameter can be a value of @ref UART_WakeUp_Address_Length */
-
+
uint8_t Address; /*!< UART/USART node address (7-bit long max) */
} UART_WakeUpTypeDef;
+
/**
* @}
*/
@@ -84,7 +85,7 @@
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
* @{
*/
-
+
/** @defgroup UARTEx_Word_Length UARTEx Word Length
* @{
*/
@@ -94,14 +95,9 @@
#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
-#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_7B) || \
- ((LENGTH) == UART_WORDLENGTH_8B) || \
- ((LENGTH) == UART_WORDLENGTH_9B))
#else
#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
- ((LENGTH) == UART_WORDLENGTH_9B))
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
@@ -115,35 +111,26 @@
#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE)
-#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
- ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
- ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
- ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000) /*!< Auto Baud rate detection on start bit */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /*!< Auto Baud rate detection on 0x7F frame detection */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /*!< Auto Baud rate detection on 0x55 frame detection */
#else
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0)
-#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(MODE) (((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
- ((MODE) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE))
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000) /*!< Auto Baud rate detection on start bit */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
/**
* @}
*/
-
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/** @defgroup UARTEx_LIN UARTEx Local Interconnection Network mode
* @{
*/
-#define UART_LIN_DISABLE ((uint32_t)0x00000000)
-#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN)
-#define IS_UART_LIN(LIN) (((LIN) == UART_LIN_DISABLE) || \
- ((LIN) == UART_LIN_ENABLE))
+#define UART_LIN_DISABLE ((uint32_t)0x00000000) /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /*!< Local Interconnect Network enable */
/**
* @}
*/
@@ -151,10 +138,8 @@
/** @defgroup UARTEx_LIN_Break_Detection UARTEx LIN Break Detection
* @{
*/
-#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
-#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
- ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
+#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /*!< LIN 11-bit break detection length */
/**
* @}
*/
@@ -165,7 +150,9 @@
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
#define UART_FLAG_REACK ((uint32_t)0x00400000)
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#define UART_FLAG_TEACK ((uint32_t)0x00200000)
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
#define UART_FLAG_WUF ((uint32_t)0x00100000)
@@ -176,9 +163,9 @@
#define UART_FLAG_BUSY ((uint32_t)0x00010000)
#define UART_FLAG_ABRF ((uint32_t)0x00008000)
#define UART_FLAG_ABRE ((uint32_t)0x00004000)
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
#define UART_FLAG_EOBF ((uint32_t)0x00001000)
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#define UART_FLAG_RTOF ((uint32_t)0x00000800)
#define UART_FLAG_CTS ((uint32_t)0x00000400)
#define UART_FLAG_CTSIF ((uint32_t)0x00000200)
@@ -239,7 +226,9 @@
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
@@ -255,68 +244,79 @@
#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */
#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */
#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
-#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \
- ((PARAM) == UART_SENDBREAK_REQUEST) || \
- ((PARAM) == UART_MUTE_MODE_REQUEST) || \
- ((PARAM) == UART_RXDATA_FLUSH_REQUEST) || \
- ((PARAM) == UART_TXDATA_FLUSH_REQUEST))
#else
-#define IS_UART_REQUEST_PARAMETER(PARAM) (((PARAM) == UART_AUTOBAUD_REQUEST) || \
- ((PARAM) == UART_SENDBREAK_REQUEST) || \
- ((PARAM) == UART_MUTE_MODE_REQUEST) || \
- ((PARAM) == UART_RXDATA_FLUSH_REQUEST))
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
/**
* @}
*/
-
+
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/** @defgroup UART_Stop_Mode_Enable UARTEx Advanced Feature Stop Mode Enable
* @{
*/
-#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000)
-#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM)
-#define IS_UART_ADVFEATURE_STOPMODE(STOPMODE) (((STOPMODE) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
- ((STOPMODE) == UART_ADVFEATURE_STOPMODE_ENABLE))
+#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /*!< UART stop mode enable */
/**
* @}
*/
-
+
/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
* @{
*/
-#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x0000)
-#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1)
-#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS)
-#define IS_UART_WAKEUP_SELECTION(WAKE) (((WAKE) == UART_WAKEUP_ON_ADDRESS) || \
- ((WAKE) == UART_WAKEUP_ON_STARTBIT) || \
- ((WAKE) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x00000000) /*!< UART wake-up on address */
+#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /*!< UART wake-up on start bit */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /*!< UART wake-up on receive data register not empty */
/**
* @}
- */
+ */
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-
+
/**
* @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
+ */
+/* Exported macros ------------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros
* @{
*/
-/** @brief Reports the UART clock source.
- * @param __HANDLE__: specifies the UART Handle
- * @param __CLOCKSOURCE__ : output variable
+/** @brief Flush the UART Data registers.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#if !defined(STM32F030x6) && !defined(STM32F030x8)
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+ } while(0)
+#else
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+ } while(0)
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+ * @{
+ */
+
+/** @brief Report the UART clock source.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @param __CLOCKSOURCE__: output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
-#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
@@ -340,7 +340,7 @@
#elif defined (STM32F030x8) || defined (STM32F070x6) || \
defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F051x8) || defined (STM32F058xx)
-#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -373,7 +373,7 @@
} \
} while(0)
#elif defined(STM32F070xB)
-#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -414,7 +414,7 @@
} \
} while(0)
#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
-#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -472,7 +472,7 @@
} \
} while(0)
#elif defined(STM32F091xC) || defined (STM32F098xx)
-#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -563,7 +563,7 @@
} \
} while(0)
#elif defined(STM32F030xC)
-#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -615,19 +615,19 @@
#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
-/** @brief Computes the UART mask to apply to retrieve the received data
+/** @brief Compute the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
- * If PCE = 1, the parity bit is not included in the data extracted
+ * @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
- * DMA transfers.
- * @param __HANDLE__: specifies the UART Handle
- * @retval none
- */
+ * DMA transfers.
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+ */
#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
-#define __HAL_UART_MASK_COMPUTATION(__HANDLE__) \
+#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
@@ -662,9 +662,9 @@
(__HANDLE__)->Mask = 0x003F ; \
} \
} \
-} while(0)
+} while(0)
#else
-#define __HAL_UART_MASK_COMPUTATION(__HANDLE__) \
+#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
@@ -692,6 +692,100 @@
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+
+/**
+ * @brief Ensure that UART frame length is valid.
+ * @param __LENGTH__: UART frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_9B))
+#else
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_9B))
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+
+/**
+ * @brief Ensure that UART auto Baud rate detection mode is valid.
+ * @param __MODE__: UART auto Baud rate detection mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+#else
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE))
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+/**
+ * @brief Ensure that UART LIN state is valid.
+ * @param __LIN__: UART LIN state.
+ * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+ */
+#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \
+ ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+ * @brief Ensure that UART LIN break detection length is valid.
+ * @param __LENGTH__: UART LIN break detection length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+/**
+ * @brief Ensure that UART request parameter is valid.
+ * @param __PARAM__: UART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
+ ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
+ ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+#else
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
+ ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
+ ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST))
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+/**
+ * @brief Ensure that UART stop mode state is valid.
+ * @param __STOPMODE__: UART stop mode state.
+ * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+ ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+/**
+ * @brief Ensure that UART wake-up selection is valid.
+ * @param __WAKE__: UART wake-up selection.
+ * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+ */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
+ ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
+ ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
/**
* @}
*/
@@ -706,8 +800,8 @@
* @{
*/
/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPolarity, uint32_t UART_DEAssertionTime, uint32_t UART_DEDeassertionTime);
#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t UART_DEPolarity, uint32_t UART_DEAssertionTime, uint32_t UART_DEDeassertionTime);
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/**
@@ -718,12 +812,10 @@
* @brief Extended UART Interrupt handling function
* @{
*/
-
+
/* IO operation functions ***************************************************/
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-
#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
-void HAL_UART_WakeupCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/**
* @}
@@ -749,16 +841,17 @@
/**
* @}
- */
+ */
+/* Private functions ---------------------------------------------------------*/
/**
* @}
- */
+ */
/**
* @}
- */
+ */
#ifdef __cplusplus
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,115 +2,117 @@
******************************************************************************
* @file stm32f0xx_hal_usart.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief USART HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter
+ * Peripheral (USART).
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
- * + Peripheral State and Errors functions
- @verbatim
+ * + Peripheral State and Error functions
+ *
+ @verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
- The USART HAL driver can be used as follows:
-
- (#) Declare a USART_HandleTypeDef handle structure.
- (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit ()API:
- (##) Enable the USARTx interface clock.
- (##) USART pins configuration:
+ The USART HAL driver can be used as follows:
+
+ (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart).
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) USART pins configuration:
(+++) Enable the clock for the USART GPIOs.
(+++) Configure these USART pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
- HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
+ (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
+ HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
(+++) Enable the NVIC USART IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
- HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
+ (++) USART interrupts handling:
+ -@@- The specific USART interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
+ (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
+ HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx channel.
(+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
- (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) in the husart Init structure.
-
- (#) Initialize the USART registers by calling the HAL_USART_Init() API:
- (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_USART_MspInit(&husart) API.
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+ flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
- -@@- The specific USART interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
-
- (#) Three operation modes are available within this driver :
-
+ (#) Initialize the USART registers by calling the HAL_USART_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_USART_MspInit(&husart) API.
+
+ (#) Three operation modes are available within this driver :
+
*** Polling mode IO operation ***
=================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
(+) Receive an amount of data in blocking mode using HAL_USART_Receive()
-
- *** Interrupt mode IO operation ***
+
+ *** Interrupt mode IO operation ***
===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
- (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
+ (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
- (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxCpltCallback
- (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
+ (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_USART_ErrorCallback
-
- *** DMA mode IO operation ***
+
+ *** DMA mode IO operation ***
==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
- (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
- (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxCpltCallback
- (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
+ (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_USART_ErrorCallback
- (+) Pause the DMA Transfer using HAL_USART_DMAPause()
- (+) Resume the DMA Transfer using HAL_USART_DMAResume()
- (+) Stop the DMA Transfer using HAL_USART_DMAStop()
-
+ (+) Pause the DMA Transfer using HAL_USART_DMAPause()
+ (+) Resume the DMA Transfer using HAL_USART_DMAResume()
+ (+) Stop the DMA Transfer using HAL_USART_DMAStop()
+
*** USART HAL driver macros list ***
- =============================================
+ =============================================
[..]
Below the list of most used macros in USART HAL driver.
-
- (+) __HAL_USART_ENABLE: Enable the USART peripheral
- (+) __HAL_USART_DISABLE: Disable the USART peripheral
+
+ (+) __HAL_USART_ENABLE: Enable the USART peripheral
+ (+) __HAL_USART_DISABLE: Disable the USART peripheral
(+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
(+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
(+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
(+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
-
- [..]
+
+ [..]
(@) You can refer to the USART HAL driver header file for more useful macros
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -134,7 +136,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -144,29 +146,31 @@
* @{
*/
-/** @defgroup USART USART HAL module driver
+/** @defgroup USART USART
* @brief HAL USART Synchronous module driver
* @{
*/
+
#ifdef HAL_USART_MODULE_ENABLED
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup USART_Private_Constants USART Private Constants
+/** @defgroup USART_Private_Constants USART Private Constants
* @{
*/
-#define DUMMY_DATA ((uint16_t) 0xFFFF)
-#define TEACK_REACK_TIMEOUT ((uint32_t) 1000)
+#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */
+#define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< USART TX or RX enable acknowledge time-out value */
#define USART_TXDMA_TIMEOUTVALUE 22000
#define USART_TIMEOUT_VALUE 22000
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE))
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
- USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP))
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
+ USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup USART_Private_Functions USART Private Functions
@@ -176,7 +180,7 @@
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
@@ -188,56 +192,65 @@
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
-
+/* Exported functions --------------------------------------------------------*/
/** @defgroup USART_Exported_Functions USART Exported Functions
* @{
*/
-/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
- ==============================================================================
+@verbatim
+ ===============================================================================
##### Initialization and Configuration functions #####
- ==============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to initialize the USART
+ This subsection provides a set of functions allowing to initialize the USART
in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
+ (+) For the asynchronous mode only these parameters can be configured:
(++) Baud Rate
- (++) Word Length
+ (++) Word Length
(++) Stop Bit
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits)
- or by the M1 and M0 bits (7-bit, 8-bit or 9-bit),
- the possible USART frame formats are as listed in the following table:
- +---------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |-----------|-----------|---------------------------------------|
- | 0 | 0 | | SB | 8-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7-bit data | PB | STB | |
- |-----------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8-bit data | PB | STB | |
- +---------------------------------------------------------------+
- | M1M0 bits | PCE bit | USART frame |
- |-----------------------|---------------------------------------|
- | 10 | 0 | | SB | 7-bit data | STB | |
- |-----------|-----------|---------------------------------------|
- | 10 | 1 | | SB | 6-bit data | PB | STB | |
- +---------------------------------------------------------------+
+ According to device capability (support or not of 7-bit word length),
+ frame length is either defined by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
+ Possible USART frame formats are as listed in the following table:
+ (+++) Table 1. USART frame format.
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M bit | PCE bit | USART frame |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | | SB | 8-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | | SB | 9-bit data | STB | |
+ (+++) |-------------------|-----------|---------------------------------------|
+ (+++) | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
+ (+++) | M1 bit | M0 bit | PCE bit | USART frame |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ (+++) |---------|---------|-----------|---------------------------------------|
+ (+++) | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ (+++) +-----------------------------------------------------------------------+
(++) USART polarity
(++) USART phase
(++) USART LastBit
(++) Receiver/transmitter modes
[..]
- The HAL_USART_Init() function follows the USART synchronous configuration
+ The HAL_USART_Init() function follows the USART synchronous configuration
procedure (details for the procedure are available in reference manual).
@endverbatim
@@ -245,9 +258,9 @@
*/
/**
- * @brief Initializes the USART mode according to the specified
- * parameters in the USART_InitTypeDef and create the associated handle .
- * @param husart: usart handle
+ * @brief Initializes the USART mode according to the specified
+ * parameters in the USART_InitTypeDef and initialize the associated handle.
+ * @param husart: USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
@@ -257,43 +270,46 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_USART_INSTANCE(husart->Instance));
-
+
if(husart->State == HAL_USART_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ husart->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK */
HAL_USART_MspInit(husart);
}
-
+
husart->State = HAL_USART_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_USART_DISABLE(husart);
-
+
/* Set the Usart Communication parameters */
if (USART_SetConfig(husart) == HAL_ERROR)
{
return HAL_ERROR;
}
-
- /* In Synchronous mode, the following bits must be kept cleared:
+
+ /* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
husart->Instance->CR2 &= ~USART_CR2_LINEN;
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
-
- /* Enable the Peripharal */
+
+ /* Enable the Peripheral */
__HAL_USART_ENABLE(husart);
-
+
/* TEACK and/or REACK to check before moving husart->State to Ready */
return (USART_CheckIdleState(husart));
}
/**
- * @brief DeInitializes the USART peripheral
- * @param husart: usart handle
+ * @brief DeInitialize the USART peripheral.
+ * @param husart: USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
@@ -303,307 +319,305 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_USART_INSTANCE(husart->Instance));
-
+
husart->State = HAL_USART_STATE_BUSY;
-
+
husart->Instance->CR1 = 0x0;
husart->Instance->CR2 = 0x0;
husart->Instance->CR3 = 0x0;
-
+
/* DeInit the low level hardware */
HAL_USART_MspDeInit(husart);
-
+
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_RESET;
-
+
/* Process Unlock */
__HAL_UNLOCK(husart);
-
+
return HAL_OK;
}
/**
- * @brief USART MSP Init
- * @param husart: usart handle
+ * @brief Initialize the USART MSP.
+ * @param husart: USART handle.
* @retval None
*/
__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_MspInit can be implemented in the user file
- */
+ */
}
/**
- * @brief USART MSP DeInit
- * @param husart: usart handle
+ * @brief DeInitialize the USART MSP.
+ * @param husart: USART handle.
* @retval None
*/
__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_MspDeInit can be implemented in the user file
- */
+ */
}
/**
* @}
*/
-/** @defgroup USART_Exported_Functions_Group2 IO operation functions
- * @brief USART Transmit and Receive functions
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+ * @brief USART Transmit and Receive functions
*
-@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the USART synchronous
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage the USART synchronous
data transfers.
-
- [..]
- The USART supports master mode only: it cannot receive or send data related to an input
+
+ [..] The USART supports master mode only: it cannot receive or send data related to an input
clock (SCLK is always an output).
(#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) Non Blocking mode: The communication is performed using Interrupts
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+ The end of the data processing will be indicated through the
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
- The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
(#) Blocking mode APIs are :
(++) HAL_USART_Transmit()in simplex mode
(++) HAL_USART_Receive() in full duplex receive only
- (++) HAL_USART_TransmitReceive() in full duplex mode
-
- (#) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_USART_TransmitReceive() in full duplex mode
+
+ (#) No-Blocking mode APIs with Interrupt are :
(++) HAL_USART_Transmit_IT()in simplex mode
(++) HAL_USART_Receive_IT() in full duplex receive only
(++) HAL_USART_TransmitReceive_IT()in full duplex mode
(++) HAL_USART_IRQHandler()
- (#) Non Blocking mode functions with DMA are :
+ (#) No-Blocking mode APIs with DMA are :
(++) HAL_USART_Transmit_DMA()in simplex mode
(++) HAL_USART_Receive_DMA() in full duplex receive only
(++) HAL_USART_TransmitReceive_DMA() in full duplex mode
(++) HAL_USART_DMAPause()
(++) HAL_USART_DMAResume()
(++) HAL_USART_DMAStop()
-
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+
+ (#) A set of Transfer Complete Callbacks are provided in No-Blocking mode:
(++) HAL_USART_TxCpltCallback()
(++) HAL_USART_RxCpltCallback()
(++) HAL_USART_TxHalfCpltCallback()
(++) HAL_USART_RxHalfCpltCallback()
(++) HAL_USART_ErrorCallback()
(++) HAL_USART_TxRxCpltCallback()
-
+
@endverbatim
* @{
*/
/**
- * @brief Simplex Send an amount of data in blocking mode
- * @param husart: USART handle
- * @param pTxData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout : Timeout duration
+ * @brief Simplex send an amount of data in blocking mode.
+ * @param husart: USART handle.
+ * @param pTxData: Pointer to data buffer.
+ * @param Size: Amount of data to be sent.
+ * @param Timeout: Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp=0;
-
+ uint16_t* tmp=0;
+
if(husart->State == HAL_USART_STATE_READY)
- {
- if((pTxData == NULL) || (Size == 0))
+ {
+ if((pTxData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(husart);
-
+
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
-
+
husart->TxXferSize = Size;
husart->TxXferCount = Size;
-
+
/* Check the remaining data to be sent */
while(husart->TxXferCount > 0)
{
husart->TxXferCount--;
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
- {
+ {
return HAL_TIMEOUT;
}
- if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) pTxData;
- husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
pTxData += 2;
}
else
{
- husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF);
- }
+ husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF);
+ }
}
-
+
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
- {
+ {
return HAL_TIMEOUT;
}
-
+
husart->State = HAL_USART_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Receive an amount of data in blocking mode
- * To receive synchronous data, dummy data are simultaneously transmitted
- * @param husart: USART handle
- * @param pRxData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout : Timeout duration
+ * @brief Receive an amount of data in blocking mode.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @param husart: USART handle.
+ * @param pRxData: Pointer to data buffer.
+ * @param Size: Amount of data to be received.
+ * @param Timeout: Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
+{
uint16_t* tmp=0;
- uint16_t uhMask;
-
+ uint16_t uhMask;
+
if(husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0))
+ if((pRxData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(husart);
-
+
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
-
- husart->RxXferSize = Size;
+
+ husart->RxXferSize = Size;
husart->RxXferCount = Size;
/* Computation of USART mask to apply to RDR register */
- __HAL_USART_MASK_COMPUTATION(husart);
+ USART_MASK_COMPUTATION(husart);
uhMask = husart->Mask;
-
+
/* as long as data have to be received */
while(husart->RxXferCount > 0)
{
husart->RxXferCount--;
-
- /* Wait until TC flag is set to send dummy byte in order to generate the
+
+ /* Wait until TC flag is set to send dummy byte in order to generate the
* clock for the slave to send data.
- * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
+ * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
* can be written for all the cases. */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
+ {
+ return HAL_TIMEOUT;
}
- husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x0FF);
-
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
+
/* Wait for RXNE Flag */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
+ {
return HAL_TIMEOUT;
}
-
- if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) pRxData ;
*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- pRxData +=2;
+ pRxData +=2;
}
else
{
- *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
+ *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
}
-
+
husart->State = HAL_USART_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Full-Duplex Send and Receive an amount of data in blocking mode
- * @param husart: USART handle
- * @param pTxData: pointer to TX data buffer
- * @param pRxData: pointer to RX data buffer
- * @param Size: amount of data to be sent (same amount to be received)
- * @param Timeout : Timeout duration
+ * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
+ * @param husart: USART handle.
+ * @param pTxData: pointer to TX data buffer.
+ * @param pRxData: pointer to RX data buffer.
+ * @param Size: amount of data to be sent (same amount to be received).
+ * @param Timeout: Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp=0;
- uint16_t uhMask;
-
+ uint16_t uhMask;
+
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(husart);
-
+
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
-
+
husart->RxXferSize = Size;
husart->TxXferSize = Size;
husart->TxXferCount = Size;
husart->RxXferCount = Size;
-
+
/* Computation of USART mask to apply to RDR register */
- __HAL_USART_MASK_COMPUTATION(husart);
+ USART_MASK_COMPUTATION(husart);
uhMask = husart->Mask;
/* Check the remain data to be sent */
while(husart->TxXferCount > 0)
{
husart->TxXferCount--;
- husart->RxXferCount--;
-
- /* Wait until TC flag is set to send data */
+ husart->RxXferCount--;
+
+ /* Wait until TC flag is set to send data */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
+ {
+ return HAL_TIMEOUT;
}
- if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) pTxData;
husart->Instance->TDR = (*tmp & uhMask);
@@ -611,404 +625,412 @@
}
else
{
- husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
- }
-
+ husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
+ }
+
/* Wait for RXNE Flag */
if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
+ {
return HAL_TIMEOUT;
}
-
- if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) pRxData ;
*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- pRxData +=2;
+ pRxData +=2;
}
else
{
- *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
+ *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ }
}
-
+
husart->State = HAL_USART_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Send an amount of data in interrupt mode
- * @param husart: USART handle
- * @param pTxData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @brief Send an amount of data in interrupt mode.
+ * @param husart: USART handle.
+ * @param pTxData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
-{
+{
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(husart);
-
+
husart->pTxBuffPtr = pTxData;
husart->TxXferSize = Size;
husart->TxXferCount = Size;
-
+
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
-
- /* The USART Error Interrupts: (Frame error, noise error, overrun error)
+
+ /* The USART Error Interrupts: (Frame error, noise error, overrun error)
are not managed by the USART Transmit Process to avoid the overrun interrupt
when the usart mode is configured for transmit and receive "USART_MODE_TX_RX"
- to benefit for the frame error and noise interrupts the usart mode should be
+ to benefit for the frame error and noise interrupts the usart mode should be
configured only for transmit "USART_MODE_TX" */
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
/* Enable the USART Transmit Data Register Empty Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Receive an amount of data in blocking mode
- * To receive synchronous data, dummy data are simultaneously transmitted
- * @param husart: usart handle
- * @param pRxData: pointer to data buffer
- * @param Size: amount of data to be received
+ * @brief Receive an amount of data in blocking mode.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @param husart: USART handle.
+ * @param pRxData: pointer to data buffer.
+ * @param Size: amount of data to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
{
if(husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0))
+ if((pRxData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(husart);
-
+
husart->pRxBuffPtr = pRxData;
husart->RxXferSize = Size;
husart->RxXferCount = Size;
-
- __HAL_USART_MASK_COMPUTATION(husart);
+
+ USART_MASK_COMPUTATION(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
-
+
/* Enable the USART Parity Error Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_PE);
-
+
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
-
+
/* Enable the USART Data Register not empty Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
/* Send dummy byte in order to generate the clock for the Slave to send the next data */
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
- husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x01FF);
- }
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FF);
+ }
else
{
- husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF);
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
}
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Full-Duplex Send and Receive an amount of data in interrupt mode
- * @param husart: USART handle
- * @param pTxData: pointer to TX data buffer
- * @param pRxData: pointer to RX data buffer
- * @param Size: amount of data to be sent (same amount to be received)
+ * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
+ * @param husart: USART handle.
+ * @param pTxData: pointer to TX data buffer.
+ * @param pRxData: pointer to RX data buffer.
+ * @param Size: amount of data to be sent (same amount to be received).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
+
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(husart);
-
+
husart->pRxBuffPtr = pRxData;
husart->RxXferSize = Size;
husart->RxXferCount = Size;
husart->pTxBuffPtr = pTxData;
husart->TxXferSize = Size;
husart->TxXferCount = Size;
-
+
/* Computation of USART mask to apply to RDR register */
- __HAL_USART_MASK_COMPUTATION(husart);
-
+ USART_MASK_COMPUTATION(husart);
+
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
+
/* Enable the USART Data Register not empty Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
-
+ __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
+
/* Enable the USART Parity Error Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_PE);
-
+
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
/* Enable the USART Transmit Data Register Empty Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
- }
+ return HAL_BUSY;
+ }
+
}
/**
- * @brief Send an amount of data in DMA mode
- * @param husart: USART handle
- * @param pTxData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @brief Send an amount of data in DMA mode.
+ * @param husart: USART handle.
+ * @param pTxData: pointer to data buffer.
+ * @param Size: amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
{
uint32_t *tmp=0;
-
+
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Process Locked */
- __HAL_LOCK(husart);
-
+ __HAL_LOCK(husart);
+
husart->pTxBuffPtr = pTxData;
husart->TxXferSize = Size;
husart->TxXferCount = Size;
-
+
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
-
+
/* Set the USART DMA transfer complete callback */
husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
+
/* Set the USART DMA Half transfer complete callback */
husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
-
+
/* Set the DMA error callback */
husart->hdmatx->XferErrorCallback = USART_DMAError;
/* Enable the USART transmit DMA channel */
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
-
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
husart->Instance->CR3 |= USART_CR3_DMAT;
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Full-Duplex Receive an amount of data in non-blocking mode
- * @param husart: USART handle
- * @param pRxData: pointer to data buffer
- * @param Size: amount of data to be received
- * @note When the USART parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position)
+ * @brief Receive an amount of data in DMA mode.
+ * @param husart: USART handle.
+ * @param pRxData: pointer to data buffer.
+ * @param Size: amount of data to be received.
+ * @note When the USART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
* @retval HAL status
- * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
*/
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
{
- uint32_t *tmp=0;
-
+ uint32_t *tmp;
+
if(husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0))
+ if((pRxData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(husart);
-
+
husart->pRxBuffPtr = pRxData;
husart->RxXferSize = Size;
husart->pTxBuffPtr = pRxData;
husart->TxXferSize = Size;
-
+
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
-
+
/* Set the USART DMA Rx transfer complete callback */
husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
+
/* Set the USART DMA Half transfer complete callback */
- husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
-
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+
/* Set the USART DMA Rx transfer error callback */
husart->hdmarx->XferErrorCallback = USART_DMAError;
-
+
/* Enable the USART receive DMA channel */
tmp = (uint32_t*)&pRxData;
HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
-
+
/* Enable the USART transmit DMA channel: the transmit channel is used in order
- to generate in the non-blocking mode the clock to the slave device,
+ to generate in the non-blocking mode the clock to the slave device,
this mode isn't a simplex receive mode but a full-duplex receive mode */
tmp = (uint32_t*)&pRxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
husart->Instance->CR3 |= USART_CR3_DMAR;
-
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
husart->Instance->CR3 |= USART_CR3_DMAT;
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode
- * @param husart: usart handle
- * @param pTxData: pointer to TX data buffer
- * @param pRxData: pointer to RX data buffer
- * @param Size: amount of data to be received/sent
+ * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
+ * @param husart: USART handle.
+ * @param pTxData: pointer to TX data buffer.
+ * @param pRxData: pointer to RX data buffer.
+ * @param Size: amount of data to be received/sent.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
- uint32_t *tmp=0;
-
+ uint32_t *tmp;
+
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(husart);
-
+
husart->pRxBuffPtr = pRxData;
husart->RxXferSize = Size;
husart->pTxBuffPtr = pTxData;
husart->TxXferSize = Size;
-
+
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
+
/* Set the USART DMA Rx transfer complete callback */
husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
+
/* Set the USART DMA Half transfer complete callback */
husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
/* Set the USART DMA Tx transfer complete callback */
husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
+
/* Set the USART DMA Half transfer complete callback */
husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
/* Set the USART DMA Tx transfer error callback */
husart->hdmatx->XferErrorCallback = USART_DMAError;
-
+
/* Set the USART DMA Rx transfer error callback */
husart->hdmarx->XferErrorCallback = USART_DMAError;
-
+
/* Enable the USART receive DMA channel */
tmp = (uint32_t*)&pRxData;
HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
-
+
/* Enable the USART transmit DMA channel */
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
husart->Instance->CR3 |= USART_CR3_DMAR;
-
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
husart->Instance->CR3 |= USART_CR3_DMAT;
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
-
+
/**
- * @brief Pauses the DMA Transfer.
- * @param husart: USART handle
- * @retval None
+ * @brief Pause the DMA Transfer.
+ * @param husart: USART handle.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
{
@@ -1036,13 +1058,13 @@
/* Process Unlocked */
__HAL_UNLOCK(husart);
- return HAL_OK;
+ return HAL_OK;
}
/**
- * @brief Resumes the DMA Transfer.
- * @param husart: USART handle
- * @retval None
+ * @brief Resume the DMA Transfer.
+ * @param husart: USART handle.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
{
@@ -1056,24 +1078,24 @@
}
else if(husart->State == HAL_USART_STATE_BUSY_RX)
{
+ /* Clear the Overrun flag before resumming the Rx transfer*/
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
+
/* Enable the USART DMA Rx request */
husart->Instance->CR3 |= USART_CR3_DMAR;
}
else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
{
+ /* Clear the Overrun flag before resumming the Rx transfer*/
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
+
/* Enable the USART DMA Rx request before the DMA Tx request */
husart->Instance->CR3 |= USART_CR3_DMAR;
+
/* Enable the USART DMA Tx request */
husart->Instance->CR3 |= USART_CR3_DMAT;
}
- /* If the USART peripheral is still not enabled, enable it */
- if ((husart->Instance->CR1 & USART_CR1_UE) == 0)
- {
- /* Enable USART peripheral */
- __HAL_USART_ENABLE(husart);
- }
-
/* Process Unlocked */
__HAL_UNLOCK(husart);
@@ -1081,91 +1103,90 @@
}
/**
- * @brief Stops the DMA Transfer.
- * @param husart: USART handle
- * @retval None
+ * @brief Stop the DMA Transfer.
+ * @param husart: USART handle.
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
{
- /* Process Locked */
- __HAL_LOCK(husart);
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
+ HAL_USART_TxHalfCpltCallback() / HAL_USART_RxHalfCpltCallback ():
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
+ generated if the DMA transfer interruption occurs at the middle or at the end of the stream
+ and the corresponding call back is executed.
+ */
/* Disable the USART Tx/Rx DMA requests */
husart->Instance->CR3 &= ~USART_CR3_DMAT;
husart->Instance->CR3 &= ~USART_CR3_DMAR;
- /* Abort the USART DMA tx Channel */
+ /* Abort the USART DMA tx channel */
if(husart->hdmatx != NULL)
{
HAL_DMA_Abort(husart->hdmatx);
}
- /* Abort the USART DMA rx Channel */
+ /* Abort the USART DMA rx channel */
if(husart->hdmarx != NULL)
{
HAL_DMA_Abort(husart->hdmarx);
}
- /* Disable USART peripheral */
- __HAL_USART_DISABLE(husart);
-
husart->State = HAL_USART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ return HAL_OK;
+}
- return HAL_OK;
-}
-
/**
- * @brief This function handles USART interrupt request.
- * @param husart: USART handle
+ * @brief Handle USART interrupt request.
+ * @param husart: USART handle.
* @retval None
*/
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
{
-
- /* USART parity error interrupt occured ------------------------------------*/
+
+ /* USART parity error interrupt occurred ------------------------------------*/
if((__HAL_USART_GET_IT(husart, USART_IT_PE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_IT_PE);
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
husart->ErrorCode |= HAL_USART_ERROR_PE;
/* Set the USART state ready to be able to start again the process */
husart->State = HAL_USART_STATE_READY;
}
-
- /* USART frame error interrupt occured -------------------------------------*/
+
+ /* USART frame error interrupt occurred -------------------------------------*/
if((__HAL_USART_GET_IT(husart, USART_IT_FE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_IT_FE);
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
husart->ErrorCode |= HAL_USART_ERROR_FE;
/* Set the USART state ready to be able to start again the process */
husart->State = HAL_USART_STATE_READY;
}
-
- /* USART noise error interrupt occured -------------------------------------*/
+
+ /* USART noise error interrupt occurred -------------------------------------*/
if((__HAL_USART_GET_IT(husart, USART_IT_NE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_IT_NE);
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
husart->ErrorCode |= HAL_USART_ERROR_NE;
/* Set the USART state ready to be able to start again the process */
husart->State = HAL_USART_STATE_READY;
}
-
- /* USART Over-Run interrupt occured ----------------------------------------*/
+
+ /* USART Over-Run interrupt occurred ----------------------------------------*/
if((__HAL_USART_GET_IT(husart, USART_IT_ORE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_IT_ORE);
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
husart->ErrorCode |= HAL_USART_ERROR_ORE;
/* Set the USART state ready to be able to start again the process */
husart->State = HAL_USART_STATE_READY;
}
-
+
/* Call USART Error Call back function if need be --------------------------*/
if(husart->ErrorCode != HAL_USART_ERROR_NONE)
{
HAL_USART_ErrorCallback(husart);
- }
-
+ }
+
/* USART in mode Receiver --------------------------------------------------*/
if((__HAL_USART_GET_IT(husart, USART_IT_RXNE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE) != RESET))
{
@@ -1178,10 +1199,10 @@
USART_TransmitReceive_IT(husart);
}
}
-
+
/* USART in mode Transmitter -----------------------------------------------*/
if((__HAL_USART_GET_IT(husart, USART_IT_TXE) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE) != RESET))
- {
+ {
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
USART_Transmit_IT(husart);
@@ -1191,55 +1212,54 @@
USART_TransmitReceive_IT(husart);
}
}
-
+
/* USART in mode Transmitter (transmission end) -----------------------------*/
if((__HAL_USART_GET_IT(husart, USART_IT_TC) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC) != RESET))
{
USART_EndTransmit_IT(husart);
- }
+ }
}
-
/**
- * @brief Tx Transfer completed callbacks
- * @param husart: usart handle
+ * @brief Tx Transfer completed callback.
+ * @param husart: USART handle.
* @retval None
*/
__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
{
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_TxCpltCallback can be implemented in the user file
- */
+ the HAL_USART_TxCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief Tx Half Transfer completed callbacks.
+ * @brief Tx Half Transfer completed callback.
* @param husart: USART handle
* @retval None
*/
__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
{
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_TxHalfCpltCallback can be implemented in the user file
- */
+ the HAL_USART_TxHalfCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief Rx Transfer completed callbacks.
- * @param husart: USART handle
+ * @brief Rx Transfer completed callback.
+ * @param husart: USART handle.
* @retval None
*/
__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
{
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_RxCpltCallback can be implemented in the user file
+ the HAL_USART_RxCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief Rx Half Transfer completed callbacks
- * @param husart: usart handle
+ * @brief Rx Half Transfer completed callback.
+ * @param husart: USART handle.
* @retval None
*/
__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1250,8 +1270,8 @@
}
/**
- * @brief Tx/Rx Transfers completed callback for the non-blocking process
- * @param husart: usart handle
+ * @brief Tx/Rx Transfers completed callback for the non-blocking process.
+ * @param husart: USART handle
* @retval None
*/
__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
@@ -1262,42 +1282,43 @@
}
/**
- * @brief USART error callbacks
- * @param husart: usart handle
+ * @brief USART error callback.
+ * @param husart: USART handle.
* @retval None
*/
__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
{
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_USART_ErrorCallback can be implemented in the user file
- */
+ the HAL_USART_ErrorCallback can be implemented in the user file.
+ */
}
/**
* @}
*/
-/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief USART control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief USART Peripheral State and Error functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to control the USART.
- (+) HAL_USART_GetState() API can be helpful to check in run-time the state of the USART peripheral.
- (+) USART_SetConfig() API is used to set the USART communication parameters.
- (+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization
-
+ This subsection provides functions allowing to :
+ (+) Return the USART handle state
+ (+) Return the USART handle error code
+
@endverbatim
* @{
*/
+
/**
- * @brief return the USART state
- * @param husart: USART handle
- * @retval HAL state
+ * @brief Return the USART handle state.
+ * @param husart : pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
+ * @retval USART handle state
*/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
{
@@ -1305,10 +1326,10 @@
}
/**
- * @brief Return the USART error code
+ * @brief Return the USART error code.
* @param husart : pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART.
- * @retval USART Error Code
+ * the configuration information for the specified USART.
+ * @retval USART handle Error Code
*/
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
{
@@ -1323,154 +1344,180 @@
* @}
*/
-/** @defgroup USART_Private_Functions USART Private Functions
- * @brief USART Private functions
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @brief USART Private functions
+ *
+@verbatim
+ [..]
+ This subsection provides a set of functions allowing to control the USART.
+ (+) USART_SetConfig() API is used to set the USART communication parameters.
+ (+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization
+
+@endverbatim
* @{
*/
/**
- * @brief Configure the USART peripheral
- * @param husart: USART handle
- * @retval None
+ * @brief Configure the USART peripheral.
+ * @param husart: USART handle.
+ * @retval HAL status
*/
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
{
uint32_t tmpreg = 0x0;
USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
HAL_StatusTypeDef ret = HAL_OK;
-
+ uint16_t brrtemp = 0x0000;
+ uint16_t usartdiv = 0x0000;
+
/* Check the parameters */
assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
- assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
+ assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
assert_param(IS_USART_PARITY(husart->Init.Parity));
assert_param(IS_USART_MODE(husart->Init.Mode));
-
+
/*-------------------------- USART CR1 Configuration -----------------------*/
- /* Clear M, PCE, PS, TE and RE bits and configure
- * the USART Word Length, Parity and Mode:
- * set the M bits according to husart->Init.WordLength value
+ /* Clear M, PCE, PS, TE and RE bits and configure
+ * the USART Word Length, Parity and Mode:
+ * set the M bits according to husart->Init.WordLength value
* set PCE and PS bits according to husart->Init.Parity value
- * set TE and RE bits according to husart->Init.Mode value */
- tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode;
+ * set TE and RE bits according to husart->Init.Mode value
+ * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
+ tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
-
+
/*---------------------------- USART CR2 Configuration ---------------------*/
/* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
* set CPOL bit according to husart->Init.CLKPolarity value
* set CPHA bit according to husart->Init.CLKPhase value
* set LBCL bit according to husart->Init.CLKLastBit value
* set STOP[13:12] bits according to husart->Init.StopBits value */
- tmpreg = (uint32_t)(USART_CLOCK_ENABLED);
+ tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
- /*-------------------------- USART CR3 Configuration -----------------------*/
+ /*-------------------------- USART CR3 Configuration -----------------------*/
/* no CR3 register configuration */
/*-------------------------- USART BRR Configuration -----------------------*/
- __HAL_USART_GETCLOCKSOURCE(husart, clocksource);
+ /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */
+ USART_GETCLOCKSOURCE(husart, clocksource);
switch (clocksource)
{
- case USART_CLOCKSOURCE_PCLK1:
- husart->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / husart->Init.BaudRate);
+ case USART_CLOCKSOURCE_PCLK1:
+ usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK1Freq()) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)((2*HSI_VALUE) / husart->Init.BaudRate);
break;
- case USART_CLOCKSOURCE_HSI:
- husart->Instance->BRR = (uint16_t)(HSI_VALUE / husart->Init.BaudRate);
- break;
- case USART_CLOCKSOURCE_SYSCLK:
- husart->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / husart->Init.BaudRate);
- break;
- case USART_CLOCKSOURCE_LSE:
- husart->Instance->BRR = (uint16_t)(LSE_VALUE / husart->Init.BaudRate);
- break;
+ case USART_CLOCKSOURCE_SYSCLK:
+ usartdiv = (uint16_t)((2*HAL_RCC_GetSysClockFreq()) / husart->Init.BaudRate);
+ break;
+ case USART_CLOCKSOURCE_LSE:
+ usartdiv = (uint16_t)((2*LSE_VALUE) / husart->Init.BaudRate);
+ break;
case USART_CLOCKSOURCE_UNDEFINED:
- default:
- ret = HAL_ERROR;
- break;
+ default:
+ ret = HAL_ERROR;
+ break;
}
- return ret;
+ brrtemp = usartdiv & 0xFFF0;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
+ husart->Instance->BRR = brrtemp;
+
+ return ret;
}
/**
- * @brief Check the USART Idle State
- * @param husart: USART handle
+ * @brief Check the USART Idle State.
+ * @param husart: USART handle.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
{
/* Initialize the USART ErrorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
-
- /* Check if the Transmitter is enabled */
- if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+
+ /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
+ Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
+ */
+#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+ if (IS_UART_WAKEUP_INSTANCE(husart->Instance))
{
- /* Wait until TEACK flag is set */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- husart->State= HAL_USART_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- /* Check if the Receiver is enabled */
- if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- husart->State= HAL_USART_STATE_TIMEOUT;
- return HAL_TIMEOUT;
+ /* Check if the Transmitter is enabled */
+ if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the Receiver is enabled */
+ if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
}
}
-
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+
/* Initialize the USART state*/
- husart->State= HAL_USART_STATE_READY;
-
+ husart->State= HAL_USART_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
- return HAL_OK;
+
+ return HAL_OK;
}
+
/**
- * @brief This function handles USART Communication Timeout.
- * @param husart: USART handle
+ * @brief Handle USART Communication Timeout.
+ * @param husart: USART handle.
* @param Flag: specifies the USART flag to check.
- * @param Status: The new Flag status (SET or RESET).
- * @param Timeout: Timeout duration
+ * @param Status: the Flag status (SET or RESET).
+ * @param Timeout: timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
-
+
/* Wait until flag is set */
if(Status == RESET)
- {
+ {
while(__HAL_USART_GET_FLAG(husart, Flag) == RESET)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
__HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
__HAL_USART_DISABLE_IT(husart, USART_IT_PE);
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
+
husart->State= HAL_USART_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
return HAL_TIMEOUT;
}
}
@@ -1483,69 +1530,66 @@
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
__HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
__HAL_USART_DISABLE_IT(husart, USART_IT_PE);
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
+
husart->State= HAL_USART_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
return HAL_TIMEOUT;
}
}
}
}
- return HAL_OK;
+ return HAL_OK;
}
/**
- * @brief DMA USART transmit process complete callback
- * @param hdma : DMA handle
+ * @brief DMA USART transmit process complete callback.
+ * @param hdma: DMA handle
* @retval None
*/
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- husart->TxXferCount = 0;
-
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- /* Wait for USART TC Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TXDMA_TIMEOUTVALUE) != HAL_OK)
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ husart->TxXferCount = 0;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
{
- /* Timeout Occured */
- husart->State = HAL_USART_STATE_TIMEOUT;
- HAL_USART_ErrorCallback(husart);
- }
- else
- {
- /* No Timeout */
- /* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the USART CR3 register */
husart->Instance->CR3 &= ~(USART_CR3_DMAT);
- husart->State= HAL_USART_STATE_READY;
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
}
}
- /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
+ /* DMA Circular mode */
else
{
- husart->State= HAL_USART_STATE_BUSY_RX;
- HAL_USART_TxCpltCallback(husart);
-}
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ HAL_USART_TxCpltCallback(husart);
+ }
+ }
}
/**
- * @brief DMA USART transmit process half complete callback
- * @param hdma : DMA handle
+ * @brief DMA USART transmit process half complete callback.
+ * @param hdma : DMA handle.
* @retval None
*/
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1556,46 +1600,71 @@
}
/**
- * @brief DMA USART receive process complete callback
- * @param hdma : DMA handle
+ * @brief DMA USART receive process complete callback.
+ * @param hdma: DMA handle.
* @retval None
*/
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- husart->RxXferCount = 0;
-
- /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
- in USART CR3 register */
- husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
- /* similarly, disable the DMA TX transfer that was started to provide the
- clock to the slave device */
- husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ husart->RxXferCount = 0;
+
+ /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
+ in USART CR3 register */
+ husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+ /* similarly, disable the DMA TX transfer that was started to provide the
+ clock to the slave device */
+ husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
- husart->State= HAL_USART_STATE_READY;
-
- HAL_USART_RxCpltCallback(husart);
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ husart->State= HAL_USART_STATE_READY;
+ }
+ /* DMA circular mode */
+ else
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ }
+
}
/**
- * @brief DMA USART receive process half complete callback
- * @param hdma : DMA handle
+ * @brief DMA USART receive process half complete callback.
+ * @param hdma : DMA handle.
* @retval None
*/
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- HAL_USART_RxHalfCpltCallback(husart);
+ HAL_USART_RxHalfCpltCallback(husart);
}
/**
- * @brief DMA USART communication error callback
- * @param hdma : DMA handle
+ * @brief DMA USART communication error callback.
+ * @param hdma: DMA handle.
* @retval None
*/
-static void USART_DMAError(DMA_HandleTypeDef *hdma)
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
@@ -1603,146 +1672,147 @@
husart->TxXferCount = 0;
husart->ErrorCode |= HAL_USART_ERROR_DMA;
husart->State= HAL_USART_STATE_READY;
-
+
HAL_USART_ErrorCallback(husart);
}
/**
- * @brief Simplex Send an amount of data in non-blocking mode.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_Transmit_IT()
- * @param husart: USART handle
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @param husart: USART handle.
* @retval HAL status
- * @note The USART errors are not managed to avoid the overrun error.
*/
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
{
uint16_t* tmp=0;
- if (husart->State == HAL_USART_STATE_BUSY_TX)
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
{
-
- if(husart->TxXferCount == 0)
+
+ if(husart->TxXferCount == 0)
{
/* Disable the USART Transmit Complete Interrupt */
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-
- /* Enable the USART Transmit Complete Interrupt */
+
+ /* Enable the USART Transmit Complete Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_TC);
-
+
return HAL_OK;
}
else
{
- if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) husart->pTxBuffPtr;
- husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
husart->pTxBuffPtr += 2;
}
else
- {
- husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF);
- }
+ {
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF);
+ }
husart->TxXferCount--;
-
+
return HAL_OK;
}
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Wraps up transmission in non blocking mode.
+ * @brief Wraps up transmission in non-blocking mode.
* @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
{
- /* Disable the USART Transmit Complete Interrupt */
+ /* Disable the USART Transmit Complete Interrupt */
__HAL_USART_DISABLE_IT(husart, USART_IT_TC);
-
+
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
+
husart->State = HAL_USART_STATE_READY;
-
+
HAL_USART_TxCpltCallback(husart);
-
+
return HAL_OK;
}
/**
- * @brief Simplex Receive an amount of data in non-blocking mode.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_Receive_IT()
- * @param husart: USART handle
+ * @brief Simplex receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @param husart: USART handle
* @retval HAL status
*/
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
{
uint16_t* tmp=0;
- uint16_t uhMask = husart->Mask;
+ uint16_t uhMask = husart->Mask;
if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
-
- if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pRxBuffPtr ;
+ {
+
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ tmp = (uint16_t*) husart->pRxBuffPtr;
*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
husart->pRxBuffPtr += 2;
- }
+ }
else
{
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
}
+
/* Send dummy byte in order to generate the clock for the Slave to Send the next data */
- husart->Instance->TDR = (DUMMY_DATA & (uint16_t)0x00FF);
-
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+
if(--husart->RxXferCount == 0)
- {
- __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+ {
+ __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
/* Disable the USART Parity Error Interrupt */
__HAL_USART_DISABLE_IT(husart, USART_IT_PE);
-
+
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
+
husart->State = HAL_USART_STATE_READY;
-
+
HAL_USART_RxCpltCallback(husart);
-
+
return HAL_OK;
}
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_TransmitReceive_IT()
- * @param husart: USART handle
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_TransmitReceive_IT().
+ * @param husart: USART handle.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
{
uint16_t* tmp=0;
- uint16_t uhMask = husart->Mask;
+ uint16_t uhMask = husart->Mask;
if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
{
@@ -1751,18 +1821,18 @@
{
if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
{
- if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) husart->pTxBuffPtr;
husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
husart->pTxBuffPtr += 2;
- }
+ }
else
{
- husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
}
husart->TxXferCount--;
-
+
/* Check the latest data transmitted */
if(husart->TxXferCount == 0)
{
@@ -1770,48 +1840,48 @@
}
}
}
-
+
if(husart->RxXferCount != 0x00)
{
if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
{
- if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- tmp = (uint16_t*) husart->pRxBuffPtr ;
+ tmp = (uint16_t*) husart->pRxBuffPtr;
*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
husart->pRxBuffPtr += 2;
}
else
- {
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ {
+ *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
}
husart->RxXferCount--;
}
}
-
+
/* Check the latest data received */
if(husart->RxXferCount == 0)
{
__HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
-
+
/* Disable the USART Parity Error Interrupt */
__HAL_USART_DISABLE_IT(husart, USART_IT_PE);
-
+
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
+
husart->State = HAL_USART_STATE_READY;
-
+
HAL_USART_TxRxCpltCallback(husart);
-
+
return HAL_OK;
}
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_usart.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -32,7 +32,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -52,28 +52,27 @@
/** @addtogroup USART
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup USART_Exported_Types USART Exported Types
* @{
- */
-
+ */
-/**
- * @brief USART Init Structure definition
- */
+/**
+ * @brief USART Init Structure definition
+ */
typedef struct
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))) */
+ Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USARTEx_Word_Length */
+ This parameter can be a value of @ref USARTEx_Word_Length. */
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_Stop_Bits */
+ This parameter can be a value of @ref USART_Stop_Bits. */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@@ -81,37 +80,37 @@
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
-
+
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_Mode */
+ This parameter can be a value of @ref USART_Mode. */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_Clock_Polarity */
+ This parameter can be a value of @ref USART_Clock_Polarity. */
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_Clock_Phase */
+ This parameter can be a value of @ref USART_Clock_Phase. */
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_Last_Bit */
+ This parameter can be a value of @ref USART_Last_Bit. */
}USART_InitTypeDef;
-/**
- * @brief HAL State structures definition
- */
+/**
+ * @brief HAL USART State structures definition
+ */
typedef enum
{
- HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
- HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
+ HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
+ HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
+ HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
+ HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
+ HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */
- HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_USART_STATE_ERROR = 0x04 /*!< Error */
+ HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_USART_STATE_ERROR = 0x04 /*!< Error */
}HAL_USART_StateTypeDef;
-/**
+/**
* @brief USART clock sources definitions
*/
typedef enum
@@ -120,43 +119,43 @@
USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
- USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
+ USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
}USART_ClockSourceTypeDef;
-/**
- * @brief USART handle Structure definition
- */
+
+/**
+ * @brief USART handle Structure definition
+ */
typedef struct
{
USART_TypeDef *Instance; /*!< USART registers base address */
-
+
USART_InitTypeDef Init; /*!< USART communication parameters */
-
+
uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
-
+
uint16_t TxXferSize; /*!< USART Tx Transfer size */
-
+
uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
-
+
uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
-
+
uint16_t RxXferSize; /*!< USART Rx Transfer size */
-
+
uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
-
+
uint16_t Mask; /*!< USART Rx RDR register mask */
-
+
DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
-
+
DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- HAL_USART_StateTypeDef State; /*!< USART communication state */
-
- __IO uint32_t ErrorCode; /*!< USART Error code
- This parameter can be a value of @ref USART_Error */
-
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_USART_StateTypeDef State; /*!< USART communication state */
+
+ __IO uint32_t ErrorCode; /*!< USART Error code */
+
}USART_HandleTypeDef;
/**
@@ -164,7 +163,7 @@
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_Exported_Constants USART Exported constants
+/** @defgroup USART_Exported_Constants USART Exported Constants
* @{
*/
@@ -187,64 +186,53 @@
#define USART_STOPBITS_1 ((uint32_t)0x0000)
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
- ((STOPBITS) == USART_STOPBITS_1_5) || \
- ((STOPBITS) == USART_STOPBITS_2))
/**
* @}
*/
/** @defgroup USART_Parity USART Parity
* @{
- */
-#define USART_PARITY_NONE ((uint32_t)0x0000)
-#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
- ((PARITY) == USART_PARITY_EVEN) || \
- ((PARITY) == USART_PARITY_ODD))
+ */
+#define USART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */
+#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
+#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
/**
* @}
- */
+ */
/** @defgroup USART_Mode USART Mode
* @{
- */
-#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
-#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
-#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
+ */
+#define USART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
+#define USART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
+#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
/**
* @}
*/
-
+
/** @defgroup USART_Clock USART Clock
* @{
- */
-#define USART_CLOCK_DISABLED ((uint32_t)0x0000)
-#define USART_CLOCK_ENABLED ((uint32_t)USART_CR2_CLKEN)
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \
- ((CLOCK) == USART_CLOCK_ENABLED))
+ */
+#define USART_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< USART clock disable */
+#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /*!< USART clock enable */
/**
* @}
- */
+ */
/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
-#define USART_POLARITY_LOW ((uint32_t)0x0000)
-#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
-#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
+#define USART_POLARITY_LOW ((uint32_t)0x00000000) /*!< USART Clock signal is steady Low */
+#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */
/**
* @}
- */
+ */
/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
-#define USART_PHASE_1EDGE ((uint32_t)0x0000)
-#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
-#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
+#define USART_PHASE_1EDGE ((uint32_t)0x00000000) /*!< USART frame phase on first clock transition */
+#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< USART frame phase on second clock transition */
/**
* @}
*/
@@ -252,34 +240,8 @@
/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
-#define USART_LASTBIT_DISABLE ((uint32_t)0x0000)
-#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
- ((LASTBIT) == USART_LASTBIT_ENABLE))
-/**
- * @}
- */
-
-
-/** @defgroup USART_Flags USART Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
- * @{
- */
-#define USART_FLAG_REACK ((uint32_t)0x00400000)
-#define USART_FLAG_TEACK ((uint32_t)0x00200000)
-#define USART_FLAG_BUSY ((uint32_t)0x00010000)
-#define USART_FLAG_CTS ((uint32_t)0x00000400)
-#define USART_FLAG_CTSIF ((uint32_t)0x00000200)
-#define USART_FLAG_LBDF ((uint32_t)0x00000100)
-#define USART_FLAG_TXE ((uint32_t)0x00000080)
-#define USART_FLAG_TC ((uint32_t)0x00000040)
-#define USART_FLAG_RXNE ((uint32_t)0x00000020)
-#define USART_FLAG_IDLE ((uint32_t)0x00000010)
-#define USART_FLAG_ORE ((uint32_t)0x00000008)
-#define USART_FLAG_NE ((uint32_t)0x00000004)
-#define USART_FLAG_FE ((uint32_t)0x00000002)
-#define USART_FLAG_PE ((uint32_t)0x00000001)
+#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000) /*!< USART frame last data bit clock pulse not output to SCLK pin */
+#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< USART frame last data bit clock pulse output to SCLK pin */
/**
* @}
*/
@@ -294,17 +256,16 @@
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
-
-#define USART_IT_PE ((uint16_t)0x0028)
-#define USART_IT_TXE ((uint16_t)0x0727)
-#define USART_IT_TC ((uint16_t)0x0626)
-#define USART_IT_RXNE ((uint16_t)0x0525)
-#define USART_IT_IDLE ((uint16_t)0x0424)
-#define USART_IT_ERR ((uint16_t)0x0060)
-#define USART_IT_ORE ((uint16_t)0x0300)
-#define USART_IT_NE ((uint16_t)0x0200)
-#define USART_IT_FE ((uint16_t)0x0100)
+#define USART_IT_PE ((uint16_t)0x0028) /*!< USART parity error interruption */
+#define USART_IT_TXE ((uint16_t)0x0727) /*!< USART transmit data register empty interruption */
+#define USART_IT_TC ((uint16_t)0x0626) /*!< USART transmission complete interruption */
+#define USART_IT_RXNE ((uint16_t)0x0525) /*!< USART read data register not empty interruption */
+#define USART_IT_IDLE ((uint16_t)0x0424) /*!< USART idle interruption */
+#define USART_IT_ERR ((uint16_t)0x0060) /*!< USART error interruption */
+#define USART_IT_ORE ((uint16_t)0x0300) /*!< USART overrun error interruption */
+#define USART_IT_NE ((uint16_t)0x0200) /*!< USART noise error interruption */
+#define USART_IT_FE ((uint16_t)0x0100) /*!< USART frame error interruption */
/**
* @}
*/
@@ -312,32 +273,21 @@
/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
* @{
*/
-#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
-#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
-#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
-/**
- * @}
- */
-
-/** @defgroup USART_Request_Parameters USART Request Parameters
- * @{
- */
-#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
-#define IS_USART_REQUEST_PARAMETER(PARAM) (((PARAM) == USART_RXDATA_FLUSH_REQUEST) || \
- ((PARAM) == USART_TXDATA_FLUSH_REQUEST))
+#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
/**
* @}
*/
-/** @defgroup USART_Interruption_Mask USART interruptions flag mask
+/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
* @{
- */
-#define USART_IT_MASK ((uint16_t)0x001F)
+ */
+#define USART_IT_MASK ((uint16_t)0x001F) /*!< USART interruptions flags mask */
/**
* @}
*/
@@ -345,27 +295,26 @@
/**
* @}
*/
-
-/* Exported macro ------------------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup USART_Exported_Macros USART Exported Macros
* @{
- */
+ */
-
-/** @brief Reset USART handle state
+/** @brief Reset USART handle state.
* @param __HANDLE__: USART handle.
* @retval None
*/
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
-/** @brief Checks whether the specified USART flag is set or not.
+/** @brief Check whether the specified USART flag is set or not.
* @param __HANDLE__: specifies the USART Handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
- * @arg USART_FLAG_REACK: Receive enable ackowledge flag
- * @arg USART_FLAG_TEACK: Transmit enable ackowledge flag
- * @arg USART_FLAG_BUSY: Busy flag
- * @arg USART_FLAG_CTS: CTS Change flag
+ * @arg USART_FLAG_REACK: Receive enable acknowledge flag
+ * @arg USART_FLAG_TEACK: Transmit enable acknowledge flag
+ * @arg USART_FLAG_BUSY: Busy flag
+ * @arg USART_FLAG_CTS: CTS Change flag
* @arg USART_FLAG_TXE: Transmit data register empty flag
* @arg USART_FLAG_TC: Transmission Complete flag
* @arg USART_FLAG_RXNE: Receive data register not empty flag
@@ -378,9 +327,57 @@
*/
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+/** @brief Clear the specified USART pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg USART_CLEAR_PEF
+ * @arg USART_CLEAR_FEF
+ * @arg USART_CLEAR_NEF
+ * @arg USART_CLEAR_OREF
+ * @arg USART_CLEAR_IDLEF
+ * @arg USART_CLEAR_TCF
+ * @arg USART_CLEAR_CTSF
+ * @arg USART_CLEAR_RTOF
+ * @arg USART_CLEAR_EOBF
+ * @arg USART_CLEAR_CMF
+ * @arg USART_CLEAR_WUF
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-/** @brief Enables the specified USART interrupt.
- * @param __HANDLE__: specifies the USART Handle
+/** @brief Clear the USART PE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
+
+/** @brief Clear the USART FE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
+
+/** @brief Clear the USART NE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
+
+/** @brief Clear the USART ORE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
+
+/** @brief Clear the USART IDLE pending flag.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
+
+/** @brief Enable the specified USART interrupt.
+ * @param __HANDLE__: specifies the USART Handle.
* @param __INTERRUPT__: specifies the USART interrupt source to enable.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
@@ -395,7 +392,7 @@
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
-/** @brief Disables the specified USART interrupt.
+/** @brief Disable the specified USART interrupt.
* @param __HANDLE__: specifies the USART Handle.
* @param __INTERRUPT__: specifies the USART interrupt source to disable.
* This parameter can be one of the following values:
@@ -411,9 +408,9 @@
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
-
-/** @brief Checks whether the specified USART interrupt has occurred or not.
- * @param __HANDLE__: specifies the USART Handle
+
+/** @brief Check whether the specified USART interrupt has occurred or not.
+ * @param __HANDLE__: specifies the USART Handle.
* @param __IT__: specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
@@ -426,9 +423,9 @@
* @arg USART_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
-/** @brief Checks whether the specified USART interrupt source is enabled.
+/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__: specifies the USART Handle.
* @param __IT__: specifies the USART interrupt source to check.
* This parameter can be one of the following values:
@@ -447,48 +444,60 @@
(((uint16_t)(__IT__)) & USART_IT_MASK)))
-/** @brief Clears the specified USART ISR flag, in setting the proper ICR register flag.
+/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__: specifies the USART Handle.
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt
+ * to clear the corresponding interrupt.
* This parameter can be one of the following values:
- * @arg USART_CLEAR_PEF: Parity Error Clear Flag
- * @arg USART_CLEAR_FEF: Framing Error Clear Flag
- * @arg USART_CLEAR_NEF: Noise detected Clear Flag
- * @arg USART_CLEAR_OREF: OverRun Error Clear Flag
- * @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag
- * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
- * @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag
+ * @arg USART_CLEAR_PEF: Parity Error Clear Flag
+ * @arg USART_CLEAR_FEF: Framing Error Clear Flag
+ * @arg USART_CLEAR_NEF: Noise detected Clear Flag
+ * @arg USART_CLEAR_OREF: OverRun Error Clear Flag
+ * @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag
+ * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
+ * @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag
* @retval None
*/
-#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific USART request flag.
* @param __HANDLE__: specifies the USART Handle.
- * @param __REQ__: specifies the request flag to set
+ * @param __REQ__: specifies the request flag to set.
* This parameter can be one of the following values:
- * @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
- * @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ * @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
+ * @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
*
* @retval None
- */
-#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+ */
+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
-/** @brief Enable USART
+/** @brief Enable the USART one bit sample method.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the USART one bit sample method.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief Enable USART.
* @param __HANDLE__: specifies the USART Handle.
* @retval None
- */
-#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+ */
+#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-/** @brief Disable USART
+/** @brief Disable USART.
* @param __HANDLE__: specifies the USART Handle.
* @retval None
- */
-#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+ */
+#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
- */
+ */
/* Private macros --------------------------------------------------------*/
/** @defgroup USART_Private_Macros USART Private Macros
@@ -496,45 +505,99 @@
*/
/** @brief Check USART Baud rate
- * @param BAUDRATE: Baudrate specified by the user
+ * @param __BAUDRATE__: Baudrate specified by the user.
* The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz)
- * divided by the smallest oversampling used on the USART (i.e. 8)
- * @retval Test result (TRUE or FALSE)
+ * divided by the smallest oversampling used on the USART (i.e. 8)
+ * @retval Test result (TRUE or FALSE).
*/
-#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)
+
/**
- * @}
+ * @brief Ensure that USART frame number of stop bits is valid.
+ * @param __STOPBITS__: USART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
*/
-
-/* Include USART HAL Extension module */
-#include "stm32f0xx_hal_usart_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
+#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \
+ ((__STOPBITS__) == USART_STOPBITS_1_5) || \
+ ((__STOPBITS__) == USART_STOPBITS_2))
+
+/**
+ * @brief Ensure that USART frame parity is valid.
+ * @param __PARITY__: USART frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
+ ((__PARITY__) == USART_PARITY_EVEN) || \
+ ((__PARITY__) == USART_PARITY_ODD))
-/** @addtogroup USART_Exported_Functions USART Exported Functions
- * @{
- */
-
-/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
+/**
+ * @brief Ensure that USART communication mode is valid.
+ * @param __MODE__: USART communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3) == 0x00) && ((__MODE__) != (uint32_t)0x00))
+
+/**
+ * @brief Ensure that USART clock state is valid.
+ * @param __CLOCK__: USART clock state.
+ * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
+ */
+#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
+ ((__CLOCK__) == USART_CLOCK_ENABLE))
+
+/**
+ * @brief Ensure that USART frame polarity is valid.
+ * @param __CPOL__: USART frame polarity.
+ * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+ */
+#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
+
+/**
+ * @brief Ensure that USART frame phase is valid.
+ * @param __CPHA__: USART frame phase.
+ * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
*/
+#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
-/* Initialization and de-initialization functions ******************************/
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_CheckIdleState(USART_HandleTypeDef *husart);
+/**
+ * @brief Ensure that USART frame last bit clock pulse setting is valid.
+ * @param __LASTBIT__: USART frame last bit clock pulse setting.
+ * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+ */
+#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
+ ((__LASTBIT__) == USART_LASTBIT_ENABLE))
/**
* @}
*/
-/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
+/* Include USART HAL Extension module */
+#include "stm32f0xx_hal_usart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-/* IO operation functions *******************************************************/
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspInit(USART_HandleTypeDef *husart);
+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
@@ -561,25 +624,25 @@
/* Peripheral Control functions ***********************************************/
-/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
+/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Error functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
-
-/**
- * @}
- */
+uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
/**
* @}
*/
-
+
/**
* @}
- */
+ */
+
+/**
+ * @}
+ */
/**
* @}
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_usart_ex.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_usart_ex.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of USART HAL Extension module.
******************************************************************************
* @attention
- *
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -32,7 +32,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -50,7 +50,7 @@
* @{
*/
-/** @defgroup USARTEx USARTEx Extended HAL module driver
+/** @defgroup USARTEx USARTEx
* @{
*/
@@ -59,38 +59,94 @@
/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
* @{
*/
-
+
/** @defgroup USARTEx_Word_Length USARTEx Word Length
* @{
*/
#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
-#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
-#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_7B) || \
- ((LENGTH) == USART_WORDLENGTH_8B) || \
- ((LENGTH) == USART_WORDLENGTH_9B))
+#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
+#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
#else
-#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
- ((LENGTH) == USART_WORDLENGTH_9B))
+#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long USART frame */
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || defined (STM32F070xB) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
/**
* @}
*/
-
+
+/** @defgroup USART_Request_Parameters USARTEx Request Parameters
+ * @{
+ */
+#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+#else
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags USART Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define USART_FLAG_REACK ((uint32_t)0x00400000) /*!< USART receive enable acknowledge flag */
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#define USART_FLAG_TEACK ((uint32_t)0x00200000) /*!< USART transmit enable acknowledge flag */
+#define USART_FLAG_BUSY ((uint32_t)0x00010000) /*!< USART busy flag */
+#define USART_FLAG_CTS ((uint32_t)0x00000400) /*!< USART clear to send flag */
+#define USART_FLAG_CTSIF ((uint32_t)0x00000200) /*!< USART clear to send interrupt flag */
+#define USART_FLAG_TXE ((uint32_t)0x00000080) /*!< USART transmit data register empty */
+#define USART_FLAG_TC ((uint32_t)0x00000040) /*!< USART transmission complete */
+#define USART_FLAG_RXNE ((uint32_t)0x00000020) /*!< USART read data register not empty */
+#define USART_FLAG_IDLE ((uint32_t)0x00000010) /*!< USART idle flag */
+#define USART_FLAG_ORE ((uint32_t)0x00000008) /*!< USART overrun error */
+#define USART_FLAG_NE ((uint32_t)0x00000004) /*!< USART noise error */
+#define USART_FLAG_FE ((uint32_t)0x00000002) /*!< USART frame error */
+#define USART_FLAG_PE ((uint32_t)0x00000001) /*!< USART parity error */
/**
* @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup USARTEx_Exported_Macros USARTEx Exported Macros
+ * @{
+ */
-/** @defgroup USARTEx_Exported_Macros USARTEx Exported Macros
+/** @brief Flush the USART Data registers.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None
+ */
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
+ } while(0)
+#else
+#define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
+ } while(0)
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
* @{
*/
@@ -100,7 +156,7 @@
* @retval the USART clocking source, written in __CLOCKSOURCE__.
*/
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
-#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
@@ -124,7 +180,7 @@
#elif defined (STM32F030x8) || defined (STM32F070x6) || \
defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F051x8) || defined (STM32F058xx)
-#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -155,9 +211,9 @@
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0)
#elif defined (STM32F070xB)
-#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -196,9 +252,9 @@
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0)
#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
-#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -254,9 +310,9 @@
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0)
#elif defined(STM32F091xC) || defined (STM32F098xx)
-#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -347,7 +403,7 @@
} \
} while(0)
#elif defined(STM32F030xC)
-#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -394,23 +450,23 @@
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0)
#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
-
-/** @brief Reports the USART mask to apply to retrieve the received data
+
+/** @brief Compute the USART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
- * If PCE = 1, the parity bit is not included in the data extracted
+ * @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
- * DMA transfers.
- * @param __HANDLE__: specifies the USART Handle
- * @retval none
- */
+ * DMA transfers.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
+ */
#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
-#define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \
+#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
@@ -445,9 +501,9 @@
(__HANDLE__)->Mask = 0x003F ; \
} \
} \
-} while(0)
+} while(0)
#else
-#define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \
+#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
@@ -471,28 +527,56 @@
(__HANDLE__)->Mask = 0x007F ; \
} \
} \
-} while(0)
+} while(0)
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+
+
+/**
+ * @brief Ensure that USART frame length is valid.
+ * @param __LENGTH__: USART frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
+ ((__LENGTH__) == USART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == USART_WORDLENGTH_9B))
+#else
+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == USART_WORDLENGTH_9B))
+#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || defined (STM32F070xB) || \
+ defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
+ defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+
+/**
+ * @brief Ensure that USART request parameter is valid.
+ * @param __PARAM__: USART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
+#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
+#else
+#define IS_USART_REQUEST_PARAMETER(__PARAM__) ((__PARAM__) == USART_RXDATA_FLUSH_REQUEST)
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions ****************************/
-/* I/O operation functions ***************************************************/
-/* Peripheral Control functions **********************************************/
-/* Peripheral State functions ************************************************/
/**
* @}
- */
+ */
/**
* @}
- */
-
+ */
+
#ifdef __cplusplus
}
#endif
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,22 +2,21 @@
******************************************************************************
* @file stm32f0xx_hal_wwdg.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State functions
- *
@verbatim
==============================================================================
##### WWDG specific features #####
==============================================================================
[..]
Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the Counter (T[6;0] downcounter)
+ time period, unless the program refreshes the counter (T[6;0] downcounter)
before reaching 0x3F value (i.e. a reset is generated when the counter
value rolls over from 0x40 to 0x3F).
@@ -25,8 +24,8 @@
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
(+) Once enabled the WWDG cannot be disabled except by a system reset.
- (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
- reset occurs.
+ (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
+ occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).
(+) The WWDG counter input clock is derived from the APB clock divided
by a programmable prescaler.
(+) WWDG clock (Hz) = PCLK / (4096 * Prescaler)
@@ -35,13 +34,12 @@
(+) WWDG Counter refresh is allowed between the following limits :
(++) min time (mS) = 1000 * (Counter-Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter-0x40) / WWDG clock
-
(+) Min-max timeout value @48 MHz(PCLK): ~85,3us / ~5,46 ms
##### How to use this driver #####
===============================================================================
[..]
- (+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE().
+ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Set the WWDG prescaler, refresh window and counter value
using HAL_WWDG_Init() function.
(+) Start the WWDG using HAL_WWDG_Start() function.
@@ -49,11 +47,11 @@
a value greater than 0x40 to prevent generating an immediate reset.
(+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
generated when the counter reaches 0x40, and then start the WWDG using
- HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
- add his own code by customization of function pointer HAL_WWDG_WakeupCallback
+ HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback() is executed and user can
+ add his own code by customization of function pointer HAL_WWDG_WakeupCallback().
Once enabled, EWI interrupt cannot be disabled except by a system reset.
- (+) Then the application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
+ (+) The application program must refresh the WWDG counter at regular
+ intervals during normal operation to prevent an MCU reset using
HAL_WWDG_Refresh() function. This operation must occur only when
the counter is lower than the refresh window value already programmed.
@@ -63,15 +61,16 @@
Below the list of most used macros in WWDG HAL driver.
(+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
+ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
+ (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
- (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wakeup interrupt
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -105,7 +104,7 @@
* @{
*/
-/** @defgroup WWDG WWDG HAL module driver
+/** @defgroup WWDG WWDG
* @brief WWDG HAL module driver.
* @{
*/
@@ -133,18 +132,18 @@
[..]
This section provides functions allowing to:
(+) Initialize the WWDG according to the specified parameters
- in the WWDG_InitTypeDef and create the associated handle
- (+) DeInitialize the WWDG peripheral
- (+) Initialize the WWDG MSP
- (+) DeInitialize the WWDG MSP
+ in the WWDG_InitTypeDef and initialize the associated handle.
+ (+) DeInitialize the WWDG peripheral.
+ (+) Initialize the WWDG MSP.
+ (+) DeInitialize the WWDG MSP.
@endverbatim
* @{
*/
/**
- * @brief Initializes the WWDG according to the specified
- * parameters in the WWDG_InitTypeDef and creates the associated handle.
+ * @brief Initialize the WWDG according to the specified
+ * parameters in the WWDG_InitTypeDef and initialize the associated handle.
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval HAL status
@@ -165,6 +164,9 @@
if(hwwdg->State == HAL_WWDG_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ hwwdg->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
}
@@ -186,13 +188,19 @@
}
/**
- * @brief DeInitializes the WWDG peripheral.
+ * @brief DeInitialize the WWDG peripheral.
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
{
+ /* Check the WWDG handle allocation */
+ if(hwwdg == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
@@ -222,27 +230,27 @@
}
/**
- * @brief Initializes the WWDG MSP.
+ * @brief Initialize the WWDG MSP.
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval None
*/
__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_WWDG_MspInit could be implemented in the user file
*/
}
/**
- * @brief DeInitializes the WWDG MSP.
+ * @brief DeInitialize the WWDG MSP.
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval None
*/
__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_WWDG_MspDeInit could be implemented in the user file
*/
}
@@ -262,14 +270,14 @@
This section provides functions allowing to:
(+) Start the WWDG.
(+) Refresh the WWDG.
- (+) Handle WWDG interrupt request.
+ (+) Handle WWDG interrupt request and associated function callback.
@endverbatim
* @{
*/
/**
- * @brief Starts the WWDG.
+ * @brief Start the WWDG.
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval HAL status
@@ -296,7 +304,7 @@
}
/**
- * @brief Starts the WWDG with interrupt enabled.
+ * @brief Start the WWDG with interrupt enabled.
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval HAL status
@@ -320,7 +328,7 @@
}
/**
- * @brief Refreshes the WWDG.
+ * @brief Refresh the WWDG.
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @param Counter: value of counter to put in WWDG counter
@@ -351,7 +359,7 @@
}
/**
- * @brief Handles WWDG interrupt request.
+ * @brief Handle WWDG interrupt request.
* @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
* or data logging must be performed before the actual reset is generated.
* The EWI interrupt is enabled when calling HAL_WWDG_Start_IT function.
@@ -368,7 +376,7 @@
/* Check if Early Wakeup Interrupt is enable */
if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
{
- /* Wheck if WWDG Early Wakeup Interrupt occurred */
+ /* Check if WWDG Early Wakeup Interrupt occurred */
if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
{
/* Early Wakeup callback */
@@ -394,7 +402,7 @@
*/
__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_WWDG_WakeupCallback could be implemented in the user file
*/
}
@@ -419,7 +427,7 @@
*/
/**
- * @brief Returns the WWDG state.
+ * @brief Return the WWDG handle state.
* @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval HAL state
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_wwdg.h Mon Sep 28 10:45:10 2015 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f0xx_hal_wwdg.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,7 +102,6 @@
__IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */
} WWDG_HandleTypeDef;
-
/**
* @}
*/
@@ -137,56 +136,52 @@
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
+/**
+ * @}
+ */
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
- ((__PRESCALER__) == WWDG_PRESCALER_2) || \
- ((__PRESCALER__) == WWDG_PRESCALER_4) || \
- ((__PRESCALER__) == WWDG_PRESCALER_8))
/**
* @}
*/
-/** @defgroup WWDG_Window WWDG Window
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup WWDG_Private_Macros WWDG Private Macros
* @{
*/
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_8))
+
#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
-/**
- * @}
- */
-/** @defgroup WWDG_Counter WWDG Counter
- * @{
- */
#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
/**
* @}
*/
-/**
- * @}
- */
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
* @{
*/
-/** @brief Reset WWDG handle state
+/** @brief Reset WWDG handle state.
* @param __HANDLE__: WWDG handle
* @retval None
*/
#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
/**
- * @brief Enables the WWDG peripheral.
+ * @brief Enable the WWDG peripheral.
* @param __HANDLE__: WWDG handle
* @retval None
*/
#define __HAL_WWDG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= WWDG_CR_WDGA)
/**
- * @brief Disables the WWDG peripheral.
+ * @brief Disable the WWDG peripheral.
* @param __HANDLE__: WWDG handle
* @note WARNING: This is a dummy macro for HAL code alignment.
* Once enable, WWDG Peripheral cannot be disabled except by a system reset.
@@ -195,7 +190,7 @@
#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */
/**
- * @brief Enables the WWDG early wakeup interrupt.
+ * @brief Enable the WWDG early wakeup interrupt.
* @param __HANDLE__: WWDG handle
* @param __INTERRUPT__: specifies the interrupt to enable.
* This parameter can be one of the following values:
@@ -206,7 +201,7 @@
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CFR |= (__INTERRUPT__))
/**
- * @brief Disables the WWDG early wakeup interrupt.
+ * @brief Disable the WWDG early wakeup interrupt.
* @param __HANDLE__: WWDG handle
* @param __INTERRUPT__: specifies the interrupt to disable.
* This parameter can be one of the following values:
@@ -218,7 +213,7 @@
#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */
/**
- * @brief Gets the selected WWDG's it status.
+ * @brief Check whether the selected WWDG interrupt has occurred or not.
* @param __HANDLE__: WWDG handle
* @param __INTERRUPT__: specifies the it to check.
* This parameter can be one of the following values:
@@ -227,7 +222,7 @@
*/
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
-/** @brief Clear the WWDG's interrupt pending bits
+/** @brief Clear the WWDG interrupt pending bits.
* bits to clear the selected interrupt pending bits.
* @param __HANDLE__: WWDG handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
@@ -237,7 +232,7 @@
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
/**
- * @brief Gets the selected WWDG's flag status.
+ * @brief Check whether the specified WWDG flag is set or not.
* @param __HANDLE__: WWDG handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
@@ -247,7 +242,7 @@
#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
- * @brief Clears the WWDG's pending flags.
+ * @brief Clear the WWDG's pending flags.
* @param __HANDLE__: WWDG handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
@@ -256,7 +251,7 @@
*/
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-/** @brief Checks if the specified WWDG interrupt source is enabled or disabled.
+/** @brief Check whether the specified WWDG interrupt source is enabled or not.
* @param __HANDLE__: WWDG Handle.
* @param __INTERRUPT__: specifies the WWDG interrupt source to check.
* This parameter can be one of the following values:
@@ -283,8 +278,6 @@
HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
-
/**
* @}
*/
@@ -297,7 +290,7 @@
HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-
+void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
/**
* @}
*/
@@ -307,7 +300,6 @@
*/
/* Peripheral State functions **************************************************/
HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
-
/**
* @}
*/
@@ -331,4 +323,3 @@
#endif /* __STM32F0xx_HAL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
--- a/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/analogin_api.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/analogin_api.c Mon Sep 28 10:45:10 2015 +0100
@@ -44,7 +44,7 @@
void analogin_init(analogin_t *obj, PinName pin) {
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
- MBED_ASSERT(obj->adc != (uint32_t)NC);
+ MBED_ASSERT(obj->adc != (ADCName)NC);
// Power up ADC
LPC_SYSCON->PDRUNCFG &= ~ (1 << 4);
--- a/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/pwmout_api.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/pwmout_api.c Mon Sep 28 10:45:10 2015 +0100
@@ -64,7 +64,7 @@
void pwmout_init(pwmout_t* obj, PinName pin) {
// determine the channel
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
- MBED_ASSERT(pwm != (uint32_t)NC);
+ MBED_ASSERT(pwm != (PWMName)NC);
obj->pwm = pwm;
--- a/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c Mon Sep 28 10:45:10 2015 +0100
@@ -201,6 +201,7 @@
case ParityForced1: parity_enable = 1; parity_select = 2; break;
case ParityForced0: parity_enable = 1; parity_select = 3; break;
default:
+ parity_enable = 0, parity_select = 0;
break;
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralNames.h Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,72 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX PA_2
+#define STDIO_UART_RX PA_15
+#define STDIO_UART UART_1
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_14 = (int)TIM14_BASE,
+ PWM_16 = (int)TIM16_BASE,
+ PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PeripheralPins.c Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,142 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+// If you change them, you will have also to modify the corresponding xxx_api.c file
+// for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC1_IN9
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+ {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM2 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+// {PA_1, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2)}, // TIM2_CH2
+// {PA_2, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2)}, // TIM2_CH3
+// {PA_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2)}, // TIM2_CH4
+ {PA_4, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14)}, // TIM14_CH1
+ {PA_6, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH1
+// {PA_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM16)}, // TIM16_CH1
+ {PA_7, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH2
+// {PA_7, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH1N
+// {PA_7, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14)}, // TIM14_CH1
+// {PA_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM17)}, // TIM17_CH1
+ {PA_8, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH1
+ {PA_9, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH2
+ {PA_10, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH3
+ {PA_11, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH4
+ {PB_0, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH3
+// {PB_0, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH2N
+// {PB_1, PWM_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_TIM14)}, // TIM14_CH1
+ {PB_1, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH4
+// {PB_1, PWM_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1)}, // TIM1_CH3N
+// {PB_3, PWM_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3)}, // TIM3_CH2
+ {PB_6, PWM_16, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16)}, // TIM16_CH1N
+ {PB_7, PWM_17, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM17)}, // TIM17_CH1N
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+ {PA_1, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_2, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, // STDIO TX
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+// {PA_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, // SWCLK
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
+ {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, // STDIO RX
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+// {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+ {NC, NC, 0}
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,156 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// See stm32f0xx_hal_gpio.h and stm32f0xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
+#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
+#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
+#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
+#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
+#define STM_MODE_INPUT (0)
+#define STM_MODE_OUTPUT_PP (1)
+#define STM_MODE_OUTPUT_OD (2)
+#define STM_MODE_AF_PP (3)
+#define STM_MODE_AF_OD (4)
+#define STM_MODE_ANALOG (5)
+#define STM_MODE_IT_RISING (6)
+#define STM_MODE_IT_FALLING (7)
+#define STM_MODE_IT_RISING_FALLING (8)
+#define STM_MODE_EVT_RISING (9)
+#define STM_MODE_EVT_FALLING (10)
+#define STM_MODE_EVT_RISING_FALLING (11)
+#define STM_MODE_IT_EVT_RESET (12)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X) ((uint32_t)(X) & 0xF)
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+
+ PF_0 = 0x50,
+ PF_1 = 0x51,
+
+ // Arduino connector namings
+ A0 = PA_0,
+ A1 = PA_1,
+ A2 = PA_3,
+ A3 = PA_4,
+ A4 = PA_5,
+ A5 = PA_6,
+ A6 = PA_7,
+ A7 = PA_2,
+ D0 = PA_10,
+ D1 = PA_9,
+ D2 = PA_12,
+ D3 = PB_0,
+ D4 = PB_7,
+ D5 = PB_6,
+ D6 = PB_1,
+ D7 = PF_0,
+ D8 = PF_1,
+ D9 = PA_8,
+ D10 = PA_11,
+ D11 = PB_5,
+ D12 = PB_4,
+ D13 = PB_3,
+
+ // Generic signals namings
+ LED1 = PB_3,
+ LED2 = PB_3,
+ LED3 = PB_3,
+ LED4 = PB_3,
+ SERIAL_TX = PA_2,
+ SERIAL_RX = PA_15,
+ USBTX = PA_2,
+ USBRX = PA_15,
+ I2C_SCL = PA_9,
+ I2C_SDA = PA_10,
+ SPI_MOSI = PB_5,
+ SPI_MISO = PB_4,
+ SPI_SCK = PB_3,
+ SPI_CS = PB_1,
+ PWM_OUT = PB_0,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ OpenDrain = 3,
+ PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PortNames.h Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2, /* used for compilation needs */
+ PortF = 5
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device.h Mon Sep 28 10:45:10 2015 +0100 @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 1 + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/objects.h Mon Sep 28 10:45:10 2015 +0100
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ IRQn_Type irq_n;
+ uint32_t irq_index;
+ uint32_t event;
+ PinName pin;
+};
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ PinDirection direction;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_out;
+};
+
+struct analogin_s {
+ ADCName adc;
+ PinName pin;
+};
+
+struct serial_s {
+ UARTName uart;
+ int index; // Used by irq
+ uint32_t baudrate;
+ uint32_t databits;
+ uint32_t stopbits;
+ uint32_t parity;
+ PinName pin_tx;
+ PinName pin_rx;
+};
+
+struct spi_s {
+ SPIName spi;
+ uint32_t bits;
+ uint32_t cpol;
+ uint32_t cpha;
+ uint32_t mode;
+ uint32_t nss;
+ uint32_t br_presc;
+ PinName pin_miso;
+ PinName pin_mosi;
+ PinName pin_sclk;
+ PinName pin_ssel;
+};
+
+struct i2c_s {
+ I2CName i2c;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+ PinName pin;
+ uint32_t period;
+ uint32_t pulse;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/analogin_api.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/analogin_api.c Mon Sep 28 10:45:10 2015 +0100
@@ -1,5 +1,5 @@
/* mbed Microcontroller Library
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -34,13 +34,13 @@
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
+#include "mbed_error.h"
ADC_HandleTypeDef AdcHandle;
int adc_inited = 0;
-void analogin_init(analogin_t *obj, PinName pin)
-{
+void analogin_init(analogin_t *obj, PinName pin) {
// Get the peripheral name from the pin and assign it to the object
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
@@ -73,15 +73,17 @@
AdcHandle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
AdcHandle.Init.DMAContinuousRequests = DISABLE;
AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN;
- HAL_ADC_Init(&AdcHandle);
-
+ if (HAL_ADC_Init(&AdcHandle) != HAL_OK) {
+ error("Cannot initialize ADC");
+ }
// Run the ADC calibration
- HAL_ADCEx_Calibration_Start(&AdcHandle);
+ if (HAL_ADCEx_Calibration_Start(&AdcHandle) != HAL_OK) {
+ error("Cannot Start ADC_Calibration");
+ }
}
}
-static inline uint16_t adc_read(analogin_t *obj)
-{
+static inline uint16_t adc_read(analogin_t *obj) {
ADC_ChannelConfTypeDef sConfig;
AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
@@ -125,6 +127,7 @@
case PB_1:
sConfig.Channel = ADC_CHANNEL_9;
break;
+#if !defined (TARGET_STM32F031K6)
case PC_0:
sConfig.Channel = ADC_CHANNEL_10;
break;
@@ -143,6 +146,7 @@
case PC_5:
sConfig.Channel = ADC_CHANNEL_15;
break;
+#endif
default:
return 0;
}
@@ -162,16 +166,14 @@
}
}
-uint16_t analogin_read_u16(analogin_t *obj)
-{
+uint16_t analogin_read_u16(analogin_t *obj) {
uint16_t value = adc_read(obj);
// 12-bit to 16-bit conversion
value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
return value;
}
-float analogin_read(analogin_t *obj)
-{
+float analogin_read(analogin_t *obj) {
uint16_t value = adc_read(obj);
return (float)value * (1.0f / (float)0xFFF); // 12 bits range
}
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/analogout_api.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/analogout_api.c Mon Sep 28 10:45:10 2015 +0100
@@ -39,8 +39,7 @@
static DAC_HandleTypeDef DacHandle;
-void analogout_init(dac_t *obj, PinName pin)
-{
+void analogout_init(dac_t *obj, PinName pin) {
DAC_ChannelConfTypeDef sConfig;
DacHandle.Instance = DAC;
@@ -71,8 +70,7 @@
analogout_write_u16(obj, 0);
}
-void analogout_free(dac_t *obj)
-{
+void analogout_free(dac_t *obj) {
// Reset DAC and disable clock
__DAC1_FORCE_RESET();
__DAC1_RELEASE_RESET();
@@ -82,8 +80,7 @@
pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
}
-static inline void dac_write(dac_t *obj, uint16_t value)
-{
+static inline void dac_write(dac_t *obj, uint16_t value) {
if (obj->pin == PA_4) {
HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value);
HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1);
@@ -93,8 +90,7 @@
}
}
-static inline int dac_read(dac_t *obj)
-{
+static inline int dac_read(dac_t *obj) {
if (obj->pin == PA_4) {
return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1);
} else { // PA_5
@@ -102,8 +98,7 @@
}
}
-void analogout_write(dac_t *obj, float value)
-{
+void analogout_write(dac_t *obj, float value) {
if (value < 0.0f) {
dac_write(obj, 0); // Min value
} else if (value > 1.0f) {
@@ -113,8 +108,7 @@
}
}
-void analogout_write_u16(dac_t *obj, uint16_t value)
-{
+void analogout_write_u16(dac_t *obj, uint16_t value) {
if (value > (uint16_t)DAC_RANGE) {
dac_write(obj, (uint16_t)DAC_RANGE); // Max value
} else {
@@ -122,14 +116,12 @@
}
}
-float analogout_read(dac_t *obj)
-{
+float analogout_read(dac_t *obj) {
uint32_t value = dac_read(obj);
return (float)((float)value * (1.0f / (float)DAC_RANGE));
}
-uint16_t analogout_read_u16(dac_t *obj)
-{
+uint16_t analogout_read_u16(dac_t *obj) {
return (uint16_t)dac_read(obj);
}
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_api.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_api.c Mon Sep 28 10:45:10 2015 +0100
@@ -1,6 +1,6 @@
/* mbed Microcontroller Library
*******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -34,8 +34,7 @@
extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-uint32_t gpio_set(PinName pin)
-{
+uint32_t gpio_set(PinName pin) {
MBED_ASSERT(pin != (PinName)NC);
pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
@@ -43,8 +42,7 @@
return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
}
-void gpio_init(gpio_t *obj, PinName pin)
-{
+void gpio_init(gpio_t *obj, PinName pin) {
obj->pin = pin;
if (pin == (PinName)NC) {
return;
@@ -63,13 +61,11 @@
obj->reg_clr = &gpio->BRR;
}
-void gpio_mode(gpio_t *obj, PinMode mode)
-{
+void gpio_mode(gpio_t *obj, PinMode mode) {
pin_mode(obj->pin, mode);
}
-void gpio_dir(gpio_t *obj, PinDirection direction)
-{
+void gpio_dir(gpio_t *obj, PinDirection direction) {
MBED_ASSERT(obj->pin != (PinName)NC);
if (direction == PIN_OUTPUT) {
pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_irq_api.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/gpio_irq_api.c Mon Sep 28 10:45:10 2015 +0100
@@ -82,8 +82,7 @@
static gpio_irq_handler irq_handler;
-static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
-{
+static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) {
gpio_channel_t *gpio_channel = &channels[irq_index];
uint32_t gpio_idx;
@@ -113,27 +112,23 @@
}
// EXTI lines 0 to 1
-static void gpio_irq0(void)
-{
+static void gpio_irq0(void) {
handle_interrupt_in(0, 2);
}
// EXTI lines 2 to 3
-static void gpio_irq1(void)
-{
+static void gpio_irq1(void) {
handle_interrupt_in(1, 2);
}
// EXTI lines 4 to 15
-static void gpio_irq2(void)
-{
+static void gpio_irq2(void) {
handle_interrupt_in(2, 12);
}
extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
-{
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
uint32_t irq_index;
@@ -191,8 +186,7 @@
return 0;
}
-void gpio_irq_free(gpio_irq_t *obj)
-{
+void gpio_irq_free(gpio_irq_t *obj) {
gpio_channel_t *gpio_channel = &channels[obj->irq_index];
uint32_t pin_index = STM_PIN(obj->pin);
uint32_t gpio_idx = pin_base_nr[pin_index];
@@ -207,8 +201,7 @@
obj->event = EDGE_NONE;
}
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
-{
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
uint32_t mode = STM_MODE_IT_EVT_RESET;
uint32_t pull = GPIO_NOPULL;
@@ -255,13 +248,11 @@
pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0));
}
-void gpio_irq_enable(gpio_irq_t *obj)
-{
+void gpio_irq_enable(gpio_irq_t *obj) {
NVIC_EnableIRQ(obj->irq_n);
}
-void gpio_irq_disable(gpio_irq_t *obj)
-{
+void gpio_irq_disable(gpio_irq_t *obj) {
NVIC_DisableIRQ(obj->irq_n);
obj->event = EDGE_NONE;
}
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/i2c_api.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/i2c_api.c Mon Sep 28 10:45:10 2015 +0100
@@ -45,10 +45,11 @@
I2C_HandleTypeDef I2cHandle;
int i2c1_inited = 0;
+#if defined(I2C2_BASE)
int i2c2_inited = 0;
+#endif
-void i2c_init(i2c_t *obj, PinName sda, PinName scl)
-{
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
// Determine the I2C to use
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
@@ -68,6 +69,7 @@
pin_mode(scl, OpenDrain);
}
+#if defined(I2C2_BASE)
// Enable I2C2 clock and pinout if not done
if ((obj->i2c == I2C_2) && !i2c2_inited) {
i2c2_inited = 1;
@@ -78,6 +80,7 @@
pin_mode(sda, OpenDrain);
pin_mode(scl, OpenDrain);
}
+#endif
// Reset to clear pending flags if any
i2c_reset(obj);
@@ -86,8 +89,7 @@
i2c_frequency(obj, 100000); // 100 kHz per default
}
-void i2c_frequency(i2c_t *obj, int hz)
-{
+void i2c_frequency(i2c_t *obj, int hz) {
MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
int timeout;
@@ -122,8 +124,7 @@
HAL_I2C_Init(&I2cHandle);
}
-inline int i2c_start(i2c_t *obj)
-{
+inline int i2c_start(i2c_t *obj) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
int timeout;
@@ -146,8 +147,7 @@
return 0;
}
-inline int i2c_stop(i2c_t *obj)
-{
+inline int i2c_stop(i2c_t *obj) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
// Generate the STOP condition
@@ -156,8 +156,7 @@
return 0;
}
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
-{
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
int timeout;
@@ -202,8 +201,7 @@
return length;
}
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
-{
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
int timeout;
@@ -245,8 +243,7 @@
return count;
}
-int i2c_byte_read(i2c_t *obj, int last)
-{
+int i2c_byte_read(i2c_t *obj, int last) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
int timeout;
@@ -261,8 +258,7 @@
return (int)i2c->RXDR;
}
-int i2c_byte_write(i2c_t *obj, int data)
-{
+int i2c_byte_write(i2c_t *obj, int data) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
int timeout;
@@ -279,8 +275,7 @@
return 1;
}
-void i2c_reset(i2c_t *obj)
-{
+void i2c_reset(i2c_t *obj) {
int timeout;
// Wait before reset
@@ -291,16 +286,17 @@
__I2C1_FORCE_RESET();
__I2C1_RELEASE_RESET();
}
+#if defined(I2C2_BASE)
if (obj->i2c == I2C_2) {
__I2C2_FORCE_RESET();
__I2C2_RELEASE_RESET();
}
+#endif
}
#if DEVICE_I2CSLAVE
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
-{
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
uint16_t tmpreg = 0;
@@ -318,8 +314,7 @@
i2c->OAR1 |= I2C_OAR1_OA1EN;
}
-void i2c_slave_mode(i2c_t *obj, int enable_slave)
-{
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
uint16_t tmpreg;
@@ -343,8 +338,7 @@
#define WriteGeneral 2 // the master is writing to all slave
#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
-int i2c_slave_receive(i2c_t *obj)
-{
+int i2c_slave_receive(i2c_t *obj) {
I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
int retValue = NoData;
@@ -362,8 +356,7 @@
return (retValue);
}
-int i2c_slave_read(i2c_t *obj, char *data, int length)
-{
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
char size = 0;
while (size < length) data[size++] = (char)i2c_byte_read(obj, 0);
@@ -371,8 +364,7 @@
return size;
}
-int i2c_slave_write(i2c_t *obj, const char *data, int length)
-{
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
char size = 0;
I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/mbed_overrides.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/mbed_overrides.c Mon Sep 28 10:45:10 2015 +0100
@@ -1,5 +1,5 @@
/* mbed Microcontroller Library
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -27,14 +27,23 @@
*/
#include "cmsis.h"
+extern int stdio_uart_inited;
+
// This function is called after RAM initialization and before main.
-void mbed_sdk_init()
-{
+void mbed_sdk_init() {
+ /* Configure the Cube driver */
+ SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
+
+ HAL_Init();
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+
// Update the SystemCoreClock variable.
SystemCoreClockUpdate();
-#if defined(TARGET_STM32F070RB) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC)
- // Need to restart HAL driver after the RAM is initialized
- HAL_Init();
-#endif
+ // reset serial next time it is called, now that system clock is set
+ stdio_uart_inited = 0;
+
}
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/pinmap.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/pinmap.c Mon Sep 28 10:45:10 2015 +0100
@@ -50,8 +50,7 @@
};
// Enable GPIO clock and return GPIO base address
-uint32_t Set_GPIO_Clock(uint32_t port_idx)
-{
+uint32_t Set_GPIO_Clock(uint32_t port_idx) {
uint32_t gpio_add = 0;
switch (port_idx) {
case PortA:
@@ -62,18 +61,24 @@
gpio_add = GPIOB_BASE;
__GPIOB_CLK_ENABLE();
break;
+#if defined(GPIOC_BASE)
case PortC:
gpio_add = GPIOC_BASE;
__GPIOC_CLK_ENABLE();
break;
+#endif
+#if defined(GPIOD_BASE)
case PortD:
gpio_add = GPIOD_BASE;
__GPIOD_CLK_ENABLE();
break;
+#endif
+#if defined(GPIOF_BASE)
case PortF:
gpio_add = GPIOF_BASE;
__GPIOF_CLK_ENABLE();
break;
+#endif
default:
error("Pinmap error: wrong port number.");
break;
@@ -84,8 +89,7 @@
/**
* Configure pin (mode, speed, output type and pull-up/pull-down)
*/
-void pin_function(PinName pin, int data)
-{
+void pin_function(PinName pin, int data) {
MBED_ASSERT(pin != (PinName)NC);
// Get the pin informations
@@ -119,8 +123,7 @@
/**
* Configure pin pull-up/pull-down
*/
-void pin_mode(PinName pin, PinMode mode)
-{
+void pin_mode(PinName pin, PinMode mode) {
MBED_ASSERT(pin != (PinName)NC);
uint32_t port_index = STM_PORT(pin);
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/port_api.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/port_api.c Mon Sep 28 10:45:10 2015 +0100
@@ -1,6 +1,6 @@
/* mbed Microcontroller Library
*******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -38,13 +38,11 @@
// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
// low nibble = pin number
-PinName port_pin(PortName port, int pin_n)
-{
+PinName port_pin(PortName port, int pin_n) {
return (PinName)(pin_n + (port << 4));
}
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
-{
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
uint32_t port_index = (uint32_t)port;
// Enable GPIO clock
@@ -61,8 +59,7 @@
port_dir(obj, dir);
}
-void port_dir(port_t *obj, PinDirection dir)
-{
+void port_dir(port_t *obj, PinDirection dir) {
uint32_t i;
obj->direction = dir;
for (i = 0; i < 16; i++) { // Process all pins
@@ -76,8 +73,7 @@
}
}
-void port_mode(port_t *obj, PinMode mode)
-{
+void port_mode(port_t *obj, PinMode mode) {
uint32_t i;
for (i = 0; i < 16; i++) { // Process all pins
if (obj->mask & (1 << i)) { // If the pin is used
@@ -86,13 +82,11 @@
}
}
-void port_write(port_t *obj, int value)
-{
+void port_write(port_t *obj, int value) {
*obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
}
-int port_read(port_t *obj)
-{
+int port_read(port_t *obj) {
if (obj->direction == PIN_OUTPUT) {
return (*obj->reg_out & obj->mask);
} else { // PIN_INPUT
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/pwmout_api.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/pwmout_api.c Mon Sep 28 10:45:10 2015 +0100
@@ -38,8 +38,7 @@
static TIM_HandleTypeDef TimHandle;
-void pwmout_init(pwmout_t* obj, PinName pin)
-{
+void pwmout_init(pwmout_t* obj, PinName pin) {
// Get the peripheral name from the pin and assign it to the object
obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
@@ -54,11 +53,21 @@
#if defined(TIM2_BASE)
if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE();
#endif
+#if defined(TIM3_BASE)
if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE();
+#endif
+#if defined(TIM14_BASE)
if (obj->pwm == PWM_14) __TIM14_CLK_ENABLE();
+#endif
+#if defined(TIM15_BASE)
if (obj->pwm == PWM_15) __TIM15_CLK_ENABLE();
+#endif
+#if defined(TIM16_BASE)
if (obj->pwm == PWM_16) __TIM16_CLK_ENABLE();
+#endif
+#if defined(TIM17_BASE)
if (obj->pwm == PWM_17) __TIM17_CLK_ENABLE();
+#endif
// Configure GPIO
pinmap_pinout(pin, PinMap_PWM);
@@ -70,14 +79,12 @@
pwmout_period_us(obj, 20000); // 20 ms per default
}
-void pwmout_free(pwmout_t* obj)
-{
+void pwmout_free(pwmout_t* obj) {
// Configure GPIO
pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
}
-void pwmout_write(pwmout_t* obj, float value)
-{
+void pwmout_write(pwmout_t* obj, float value) {
TIM_OC_InitTypeDef sConfig;
int channel = 0;
int complementary_channel = 0;
@@ -101,7 +108,41 @@
sConfig.OCIdleState = TIM_OCIDLESTATE_RESET;
sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET;
-#if defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8)
+#if defined (TARGET_STM32F031K6)
+ switch (obj->pin) {
+ // Channels 1
+ case PA_4:
+ case PA_6:
+ case PA_8:
+ case PB_4:
+ channel = TIM_CHANNEL_1;
+ break;
+ // Channels 1N
+ case PB_6:
+ case PB_7:
+ channel = TIM_CHANNEL_1;
+ complementary_channel = 1;
+ break;
+ // Channels 2
+ case PA_7:
+ case PA_9:
+ case PB_5:
+ channel = TIM_CHANNEL_2;
+ break;
+ // Channels 3
+ case PA_10:
+ case PB_0:
+ channel = TIM_CHANNEL_3;
+ break;
+ // Channels 4
+ case PA_11:
+ case PB_1:
+ channel = TIM_CHANNEL_4;
+ break;
+ default:
+ return;
+ }
+#elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8)
switch (obj->pin) {
// Channels 1
case PA_4:
@@ -198,8 +239,7 @@
}
}
-float pwmout_read(pwmout_t* obj)
-{
+float pwmout_read(pwmout_t* obj) {
float value = 0;
if (obj->period > 0) {
value = (float)(obj->pulse) / (float)(obj->period);
@@ -207,18 +247,15 @@
return ((value > (float)1.0) ? (float)(1.0) : (value));
}
-void pwmout_period(pwmout_t* obj, float seconds)
-{
+void pwmout_period(pwmout_t* obj, float seconds) {
pwmout_period_us(obj, seconds * 1000000.0f);
}
-void pwmout_period_ms(pwmout_t* obj, int ms)
-{
+void pwmout_period_ms(pwmout_t* obj, int ms) {
pwmout_period_us(obj, ms * 1000);
}
-void pwmout_period_us(pwmout_t* obj, int us)
-{
+void pwmout_period_us(pwmout_t* obj, int us) {
TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
float dc = pwmout_read(obj);
@@ -243,18 +280,15 @@
__HAL_TIM_ENABLE(&TimHandle);
}
-void pwmout_pulsewidth(pwmout_t* obj, float seconds)
-{
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
-{
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
pwmout_pulsewidth_us(obj, ms * 1000);
}
-void pwmout_pulsewidth_us(pwmout_t* obj, int us)
-{
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
float value = (float)us / (float)obj->period;
pwmout_write(obj, value);
}
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/rtc_api.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/rtc_api.c Mon Sep 28 10:45:10 2015 +0100
@@ -1,6 +1,6 @@
/* mbed Microcontroller Library
*******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -37,8 +37,7 @@
static RTC_HandleTypeDef RtcHandle;
-void rtc_init(void)
-{
+void rtc_init(void) {
RCC_OscInitTypeDef RCC_OscInitStruct;
uint32_t rtc_freq = 0;
@@ -95,8 +94,7 @@
}
}
-void rtc_free(void)
-{
+void rtc_free(void) {
// Enable Power clock
__PWR_CLK_ENABLE();
@@ -121,8 +119,7 @@
rtc_inited = 0;
}
-int rtc_isenabled(void)
-{
+int rtc_isenabled(void) {
return rtc_inited;
}
@@ -143,8 +140,7 @@
tm_yday days since January 1 0-365
tm_isdst Daylight Saving Time flag
*/
-time_t rtc_read(void)
-{
+time_t rtc_read(void) {
RTC_DateTypeDef dateStruct;
RTC_TimeTypeDef timeStruct;
struct tm timeinfo;
@@ -171,8 +167,7 @@
return t;
}
-void rtc_write(time_t t)
-{
+void rtc_write(time_t t) {
RTC_DateTypeDef dateStruct;
RTC_TimeTypeDef timeStruct;
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/serial_api.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/serial_api.c Mon Sep 28 10:45:10 2015 +0100
@@ -1,6 +1,6 @@
/* mbed Microcontroller Library
*******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -47,6 +47,11 @@
static uint32_t serial_irq_ids[UART_NUM] = {0, 0};
+#elif defined (TARGET_STM32F031K6)
+#define UART_NUM (1)
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+
#else
#define UART_NUM (4)
@@ -61,8 +66,7 @@
int stdio_uart_inited = 0;
serial_t stdio_uart;
-static void init_uart(serial_t *obj)
-{
+static void init_uart(serial_t *obj) {
UartHandle.Instance = (USART_TypeDef *)(obj->uart);
UartHandle.Init.BaudRate = obj->baudrate;
@@ -86,8 +90,7 @@
HAL_UART_Init(&UartHandle);
}
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
// Determine the UART to use (UART_1, UART_2, ...)
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
@@ -102,10 +105,12 @@
obj->index = 0;
}
+#if defined USART2_BASE
if (obj->uart == UART_2) {
__USART2_CLK_ENABLE();
obj->index = 1;
}
+#endif
#if defined USART3_BASE
if (obj->uart == UART_3) {
@@ -177,8 +182,7 @@
}
}
-void serial_free(serial_t *obj)
-{
+void serial_free(serial_t *obj) {
// Reset UART and disable clock
if (obj->uart == UART_1) {
__USART1_FORCE_RESET();
@@ -186,11 +190,13 @@
__USART1_CLK_DISABLE();
}
+#if defined(USART2_BASE)
if (obj->uart == UART_2) {
__USART2_FORCE_RESET();
__USART2_RELEASE_RESET();
__USART2_CLK_DISABLE();
}
+#endif
#if defined USART3_BASE
if (obj->uart == UART_3) {
@@ -248,14 +254,12 @@
serial_irq_ids[obj->index] = 0;
}
-void serial_baud(serial_t *obj, int baudrate)
-{
+void serial_baud(serial_t *obj, int baudrate) {
obj->baudrate = baudrate;
init_uart(obj);
}
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
-{
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
if (data_bits == 9) {
obj->databits = UART_WORDLENGTH_9B;
} else {
@@ -289,8 +293,7 @@
* INTERRUPTS HANDLING
******************************************************************************/
-static void uart_irq(UARTName name, int id)
-{
+static void uart_irq(UARTName name, int id) {
UartHandle.Instance = (USART_TypeDef *)name;
if (serial_irq_ids[id] != 0) {
if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) {
@@ -304,66 +307,58 @@
}
}
-static void uart1_irq(void)
-{
+static void uart1_irq(void) {
uart_irq(UART_1, 0);
}
-static void uart2_irq(void)
-{
+#if defined(USART2_BASE)
+static void uart2_irq(void) {
uart_irq(UART_2, 1);
}
+#endif
#if defined USART3_BASE
-static void uart3_irq(void)
-{
+static void uart3_irq(void) {
uart_irq(UART_3, 2);
}
#endif
#if defined USART4_BASE
-static void uart4_irq(void)
-{
+static void uart4_irq(void) {
uart_irq(UART_4, 3);
}
#endif
#if defined USART5_BASE
-static void uart5_irq(void)
-{
+static void uart5_irq(void) {
uart_irq(UART_5, 4);
}
#endif
#if defined USART6_BASE
-static void uart6_irq(void)
-{
+static void uart6_irq(void) {
uart_irq(UART_6, 5);
}
#endif
#if defined USART7_BASE
-static void uart7_irq(void)
-{
+static void uart7_irq(void) {
uart_irq(UART_7, 6);
}
#endif
#if defined USART8_BASE
-static void uart8_irq(void)
-{
+static void uart8_irq(void) {
uart_irq(UART_8, 7);
}
#endif
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
-{
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
-{
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
@@ -374,10 +369,12 @@
vector = (uint32_t)&uart1_irq;
}
+#if defined(USART2_BASE)
if (obj->uart == UART_2) {
irq_n = USART2_IRQn;
vector = (uint32_t)&uart2_irq;
}
+#endif
#if defined (TARGET_STM32F091RC)
if (obj->uart == UART_3) {
@@ -413,16 +410,20 @@
#elif defined (TARGET_STM32F030R8) || defined (TARGET_STM32F051R8)
#else
+#if defined(USART3_BASE)
if (obj->uart == UART_3) {
irq_n = USART3_4_IRQn;
vector = (uint32_t)&uart3_irq;
}
+#endif
+#if defined(USART4_BASE)
if (obj->uart == UART_4) {
irq_n = USART3_4_IRQn;
vector = (uint32_t)&uart4_irq;
}
#endif
+#endif
if (enable) {
@@ -458,22 +459,19 @@
* READ/WRITE
******************************************************************************/
-int serial_getc(serial_t *obj)
-{
+int serial_getc(serial_t *obj) {
USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
while (!serial_readable(obj));
return (int)(uart->RDR & (uint16_t)0xFF);
}
-void serial_putc(serial_t *obj, int c)
-{
+void serial_putc(serial_t *obj, int c) {
USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
while (!serial_writable(obj));
uart->TDR = (uint32_t)(c & (uint16_t)0xFF);
}
-int serial_readable(serial_t *obj)
-{
+int serial_readable(serial_t *obj) {
int status;
UartHandle.Instance = (USART_TypeDef *)(obj->uart);
// Check if data is received
@@ -481,8 +479,7 @@
return status;
}
-int serial_writable(serial_t *obj)
-{
+int serial_writable(serial_t *obj) {
int status;
UartHandle.Instance = (USART_TypeDef *)(obj->uart);
// Check if data is transmitted
@@ -490,25 +487,21 @@
return status;
}
-void serial_clear(serial_t *obj)
-{
+void serial_clear(serial_t *obj) {
UartHandle.Instance = (USART_TypeDef *)(obj->uart);
__HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC);
__HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST);
}
-void serial_pinout_tx(PinName tx)
-{
+void serial_pinout_tx(PinName tx) {
pinmap_pinout(tx, PinMap_UART_TX);
}
-void serial_break_set(serial_t *obj)
-{
+void serial_break_set(serial_t *obj) {
// [TODO]
}
-void serial_break_clear(serial_t *obj)
-{
+void serial_break_clear(serial_t *obj) {
// [TODO]
}
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/sleep.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/sleep.c Mon Sep 28 10:45:10 2015 +0100
@@ -1,6 +1,6 @@
/* mbed Microcontroller Library
*******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -34,8 +34,7 @@
#include "cmsis.h"
#if defined(TARGET_STM32F070RB)
-void sleep(void)
-{
+void sleep(void) {
TIM_HandleTypeDef TimMasterHandle;
TimMasterHandle.Instance = TIM1;
@@ -51,8 +50,7 @@
}
#elif defined(TARGET_STM32F030R8) || defined (TARGET_STM32F051R8)
-void sleep(void)
-{
+void sleep(void) {
// Stop HAL systick
HAL_SuspendTick();
// Request to enter SLEEP mode
@@ -64,8 +62,7 @@
#else
static TIM_HandleTypeDef TimMasterHandle;
-void sleep(void)
-{
+void sleep(void) {
TimMasterHandle.Instance = TIM2;
// Disable HAL tick interrupt
@@ -80,8 +77,7 @@
#endif
#if defined(TARGET_STM32F030R8) || defined (TARGET_STM32F051R8)
-void deepsleep(void)
-{
+void deepsleep(void) {
// Request to enter STOP mode with regulator in low power mode
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
@@ -94,8 +90,7 @@
}
#else
-void deepsleep(void)
-{
+void deepsleep(void) {
// Request to enter STOP mode with regulator in low power mode
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/spi_api.c Mon Sep 28 10:45:10 2015 +0100
@@ -1,6 +1,6 @@
/* mbed Microcontroller Library
*******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
+ * Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,8 +39,7 @@
static SPI_HandleTypeDef SpiHandle;
-static void init_spi(spi_t *obj)
-{
+static void init_spi(spi_t *obj) {
SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
__HAL_SPI_DISABLE(&SpiHandle);
@@ -62,8 +61,7 @@
__HAL_SPI_ENABLE(&SpiHandle);
}
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
-{
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// Determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
@@ -80,9 +78,11 @@
if (obj->spi == SPI_1) {
__SPI1_CLK_ENABLE();
}
+#if defined(SPI2_BASE)
if (obj->spi == SPI_2) {
__SPI2_CLK_ENABLE();
}
+#endif
// Configure the SPI pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
@@ -109,8 +109,7 @@
init_spi(obj);
}
-void spi_free(spi_t *obj)
-{
+void spi_free(spi_t *obj) {
// Reset SPI and disable clock
if (obj->spi == SPI_1) {
__SPI1_FORCE_RESET();
@@ -118,11 +117,13 @@
__SPI1_CLK_DISABLE();
}
+#if defined(SPI2_BASE)
if (obj->spi == SPI_2) {
__SPI2_FORCE_RESET();
__SPI2_RELEASE_RESET();
__SPI2_CLK_DISABLE();
}
+#endif
// Configure GPIOs
pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
@@ -131,8 +132,7 @@
pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
}
-void spi_format(spi_t *obj, int bits, int mode, int slave)
-{
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
// Save new values
if (bits == 16) {
obj->bits = SPI_DATASIZE_16BIT;
@@ -168,8 +168,7 @@
init_spi(obj);
}
-void spi_frequency(spi_t *obj, int hz)
-{
+void spi_frequency(spi_t *obj, int hz) {
// Note: The frequencies are obtained with SPI clock = 48 MHz (APB clock)
if (hz < 375000) {
obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 188 kHz
@@ -192,8 +191,7 @@
init_spi(obj);
}
-static inline int ssp_readable(spi_t *obj)
-{
+static inline int ssp_readable(spi_t *obj) {
int status;
SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
// Check if data is received
@@ -201,8 +199,7 @@
return status;
}
-static inline int ssp_writeable(spi_t *obj)
-{
+static inline int ssp_writeable(spi_t *obj) {
int status;
SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
// Check if data is transmitted
@@ -210,8 +207,7 @@
return status;
}
-static inline void ssp_write(spi_t *obj, int value)
-{
+static inline void ssp_write(spi_t *obj, int value) {
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_writeable(obj));
if (obj->bits == SPI_DATASIZE_8BIT) {
@@ -224,8 +220,7 @@
}
}
-static inline int ssp_read(spi_t *obj)
-{
+static inline int ssp_read(spi_t *obj) {
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_readable(obj));
if (obj->bits == SPI_DATASIZE_8BIT) {
@@ -238,27 +233,23 @@
}
}
-static inline int ssp_busy(spi_t *obj)
-{
+static inline int ssp_busy(spi_t *obj) {
int status;
SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
return status;
}
-int spi_master_write(spi_t *obj, int value)
-{
+int spi_master_write(spi_t *obj, int value) {
ssp_write(obj, value);
return ssp_read(obj);
}
-int spi_slave_receive(spi_t *obj)
-{
+int spi_slave_receive(spi_t *obj) {
return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
};
-int spi_slave_read(spi_t *obj)
-{
+int spi_slave_read(spi_t *obj) {
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_readable(obj));
if (obj->bits == SPI_DATASIZE_8BIT) {
@@ -271,8 +262,7 @@
}
}
-void spi_slave_write(spi_t *obj, int value)
-{
+void spi_slave_write(spi_t *obj, int value) {
SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
while (!ssp_writeable(obj));
if (obj->bits == SPI_DATASIZE_8BIT) {
@@ -285,8 +275,7 @@
}
}
-int spi_busy(spi_t *obj)
-{
+int spi_busy(spi_t *obj) {
return ssp_busy(obj);
}
--- a/targets/hal/TARGET_STM/TARGET_STM32F0/us_ticker.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F0/us_ticker.c Mon Sep 28 10:45:10 2015 +0100
@@ -42,8 +42,7 @@
volatile uint32_t oc_int_part = 0;
volatile uint16_t oc_rem_part = 0;
-void set_compare(uint16_t count)
-{
+void set_compare(uint16_t count) {
TimMasterHandle.Instance = TIM_MST;
// Set new output compare value
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count);
@@ -51,16 +50,14 @@
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
}
-void us_ticker_init(void)
-{
+void us_ticker_init(void) {
if (us_ticker_inited) return;
us_ticker_inited = 1;
HAL_InitTick(0); // The passed value is not used
}
-uint32_t us_ticker_read()
-{
+uint32_t us_ticker_read() {
uint32_t counter, counter2;
if (!us_ticker_inited) us_ticker_init();
// A situation might appear when Master overflows right after Slave is read and before the
@@ -81,8 +78,7 @@
return counter2;
}
-void us_ticker_set_interrupt(timestamp_t timestamp)
-{
+void us_ticker_set_interrupt(timestamp_t timestamp) {
int delta = (int)((uint32_t)timestamp - us_ticker_read());
uint16_t cval = TIM_MST->CNT;
@@ -101,14 +97,12 @@
}
}
-void us_ticker_disable_interrupt(void)
-{
+void us_ticker_disable_interrupt(void) {
TimMasterHandle.Instance = TIM_MST;
__HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
}
-void us_ticker_clear_interrupt(void)
-{
+void us_ticker_clear_interrupt(void) {
TimMasterHandle.Instance = TIM_MST;
if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
__HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
@@ -131,8 +125,7 @@
static volatile uint32_t oc_int_part = 0;
static volatile uint16_t oc_rem_part = 0;
-void set_compare(uint16_t count)
-{
+void set_compare(uint16_t count) {
TimMasterHandle.Instance = TIM_MST;
// Set new output compare value
@@ -142,8 +135,7 @@
}
// Used to increment the slave counter
-static void tim_update_irq_handler(void)
-{
+static void tim_update_irq_handler(void) {
TimMasterHandle.Instance = TIM_MST;
// Clear Update interrupt flag
@@ -154,8 +146,7 @@
}
// Used by interrupt system
-static void tim_oc_irq_handler(void)
-{
+static void tim_oc_irq_handler(void) {
uint16_t cval = TIM_MST->CNT;
TimMasterHandle.Instance = TIM_MST;
@@ -178,8 +169,7 @@
}
-void us_ticker_init(void)
-{
+void us_ticker_init(void) {
if (us_ticker_inited) return;
us_ticker_inited = 1;
@@ -210,8 +200,7 @@
HAL_TIM_Base_Start(&TimMasterHandle);
}
-uint32_t us_ticker_read()
-{
+uint32_t us_ticker_read() {
uint32_t counter, counter2;
if (!us_ticker_inited) us_ticker_init();
// A situation might appear when Master overflows right after Slave is read and before the
@@ -232,8 +221,7 @@
return counter2;
}
-void us_ticker_set_interrupt(timestamp_t timestamp)
-{
+void us_ticker_set_interrupt(timestamp_t timestamp) {
int delta = (int)((uint32_t)timestamp - us_ticker_read());
uint16_t cval = TIM_MST->CNT;
@@ -252,14 +240,12 @@
}
}
-void us_ticker_disable_interrupt(void)
-{
+void us_ticker_disable_interrupt(void) {
TimMasterHandle.Instance = TIM_MST;
__HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
}
-void us_ticker_clear_interrupt(void)
-{
+void us_ticker_clear_interrupt(void) {
TimMasterHandle.Instance = TIM_MST;
if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
__HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
@@ -274,8 +260,7 @@
static TIM_HandleTypeDef TimMasterHandle;
static int us_ticker_inited = 0;
-void us_ticker_init(void)
-{
+void us_ticker_init(void) {
if (us_ticker_inited) return;
us_ticker_inited = 1;
@@ -284,27 +269,23 @@
HAL_InitTick(0); // The passed value is not used
}
-uint32_t us_ticker_read()
-{
+uint32_t us_ticker_read() {
if (!us_ticker_inited) us_ticker_init();
return TIM_MST->CNT;
}
-void us_ticker_set_interrupt(timestamp_t timestamp)
-{
+void us_ticker_set_interrupt(timestamp_t timestamp) {
// Set new output compare value
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp);
// Enable IT
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
}
-void us_ticker_disable_interrupt(void)
-{
+void us_ticker_disable_interrupt(void) {
__HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
}
-void us_ticker_clear_interrupt(void)
-{
+void us_ticker_clear_interrupt(void) {
__HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
}
#endif
