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Last commit 20 Feb 2019 by 
mbed official
Diff: targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c
- Revision:
- 630:825f75ca301e
- Parent:
- 441:d2c15dda23c1
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c Mon Sep 28 10:30:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c Mon Sep 28 10:45:10 2015 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_tim.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 11-December-2014
+ * @version V1.3.0
+ * @date 26-June-2015
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -35,7 +35,7 @@
==============================================================================
##### TIMER Generic features #####
==============================================================================
- [..] The Timer features include:
+ [..] The Timer features include:
(#) 16-bit up, down, up/down auto-reload counter.
(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
counter clock frequency either by any factor between 1 and 65536.
@@ -43,32 +43,32 @@
(++) Input Capture
(++) Output Compare
(++) PWM generation (Edge and Center-aligned Mode)
- (++) One-pulse mode output
-
+ (++) One-pulse mode output
+
##### How to use this driver #####
==============================================================================
[..]
(#) Initialize the TIM low level resources by implementing the following functions
depending from feature used :
- (++) Time Base : HAL_TIM_Base_MspInit()
+ (++) Time Base : HAL_TIM_Base_MspInit()
(++) Input Capture : HAL_TIM_IC_MspInit()
(++) Output Compare : HAL_TIM_OC_MspInit()
(++) PWM generation : HAL_TIM_PWM_MspInit()
(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-
+
(#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
(##) TIM pins configuration
(+++) Enable the clock for the TIM GPIOs using the following function:
- __GPIOx_CLK_ENABLE();
- (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
(#) The external Clock can be configured, if needed (the default clock is the
internal clock from the APBx), using the following function:
HAL_TIM_ConfigClockSource, the clock configuration should be done before
any start function.
-
+
(#) Configure the TIM in the desired functioning mode using one of the
Initialization function of this driver:
(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
@@ -82,7 +82,7 @@
in One Pulse Mode.
(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
- (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
@@ -93,12 +93,12 @@
(#) The DMA Burst is managed with the two following functions:
HAL_TIM_DMABurst_WriteStart()
HAL_TIM_DMABurst_ReadStart()
-
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -122,8 +122,8 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
- */
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@@ -132,7 +132,7 @@
* @{
*/
-/** @defgroup TIM TIM HAL module driver
+/** @defgroup TIM TIM
* @brief TIM HAL module driver
* @{
*/
@@ -180,13 +180,13 @@
/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
* @brief Time Base functions
*
-@verbatim
+@verbatim
==============================================================================
##### Time Base functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM base.
+ (+) Initialize and configure the TIM base.
(+) De-initialize the TIM base.
(+) Start the Time Base.
(+) Stop the Time Base.
@@ -194,7 +194,7 @@
(+) Stop the Time Base and disable interrupt.
(+) Start the Time Base and enable DMA transfer.
(+) Stop the Time Base and disable DMA transfer.
-
+
@endverbatim
* @{
*/
@@ -205,33 +205,36 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
+{
/* Check the TIM handle allocation */
if(htim == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
- assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
+
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
}
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
+
/* Set the Time Base configuration */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
/* Initialize the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
return HAL_OK;
}
@@ -244,18 +247,18 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
/* Release Lock */
__HAL_UNLOCK(htim);
@@ -296,16 +299,16 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Change the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -319,16 +322,16 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -342,13 +345,13 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -364,10 +367,10 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Disable the TIM Update interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -380,40 +383,40 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
+{
/* Check the parameters */
- assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((pData == 0 ) && (Length > 0))
+ if((pData == 0 ) && (Length > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
+ }
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
-
+
/* Enable the TIM Update DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
+ __HAL_TIM_ENABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -427,16 +430,16 @@
{
/* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
+
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -444,17 +447,17 @@
/**
* @}
*/
-
+
/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
* @brief Time Output Compare functions
*
-@verbatim
+@verbatim
==============================================================================
##### Time Output Compare functions #####
==============================================================================
[..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM Output Compare.
+ (+) Initialize and configure the TIM Output Compare.
(+) De-initialize the TIM Output Compare.
(+) Start the Time Output Compare.
(+) Stop the Time Output Compare.
@@ -462,7 +465,7 @@
(+) Stop the Time Output Compare and disable interrupt.
(+) Start the Time Output Compare and enable DMA transfer.
(+) Stop the Time Output Compare and disable DMA transfer.
-
+
@endverbatim
* @{
*/
@@ -484,22 +487,25 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
+
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspInit(htim);
}
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
- /* Init the base time for the Output Compare */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
+ /* Init the base time for the Output Compare */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
/* Initialize the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
return HAL_OK;
}
@@ -512,18 +518,18 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
/* Release Lock */
__HAL_UNLOCK(htim);
@@ -556,32 +562,32 @@
/**
* @brief Starts the TIM Output Compare signal generation.
- * @param htim : TIM Output Compare handle
+ * @param htim : TIM Output Compare handle
* @param Channel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
-
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
+ __HAL_TIM_ENABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -601,22 +607,22 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
- }
-
+ }
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode.
@@ -633,45 +639,45 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
break;
- }
+ }
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -679,7 +685,7 @@
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -699,53 +705,53 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
- break;
- }
-
+ break;
+ }
+
/* Disable the Output compare channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -767,104 +773,104 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0 ) && (Length > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
+
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
+
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
+
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
}
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
- }
-
+ }
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
+ __HAL_TIM_ENABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -884,56 +890,56 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
- }
-
+ }
+
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -945,13 +951,13 @@
/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
* @brief Time PWM functions
*
-@verbatim
+@verbatim
==============================================================================
##### Time PWM functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM OPWM.
+ (+) Initialize and configure the TIM OPWM.
(+) De-initialize the TIM PWM.
(+) Start the Time PWM.
(+) Stop the Time PWM.
@@ -959,7 +965,7 @@
(+) Stop the Time PWM and disable interrupt.
(+) Start the Time PWM and enable DMA transfer.
(+) Stop the Time PWM and disable DMA transfer.
-
+
@endverbatim
* @{
*/
@@ -984,19 +990,22 @@
if(htim->State == HAL_TIM_STATE_RESET)
{
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
}
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the PWM */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
+
+ /* Init the base time for the PWM */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
/* Initialize the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
return HAL_OK;
}
@@ -1009,18 +1018,18 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
/* Release Lock */
__HAL_UNLOCK(htim);
@@ -1066,22 +1075,22 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Stops the PWM signal generation.
@@ -1095,28 +1104,28 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
+{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Starts the PWM signal generation in interrupt mode.
@@ -1133,45 +1142,45 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
break;
- }
-
+ }
+
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -1179,10 +1188,10 @@
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Stops the PWM signal generation in interrupt mode.
@@ -1199,56 +1208,56 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
- break;
+ break;
}
-
+
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Return function status */
return HAL_OK;
-}
+}
/**
* @brief Starts the TIM PWM signal generation in DMA mode.
@@ -1267,104 +1276,104 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0 ) && (Length > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
+
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
+
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+
/* Enable the TIM Output Capture/Compare 3 request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
+
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
}
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
-
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
+ __HAL_TIM_ENABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -1384,56 +1393,56 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
- }
-
+ }
+
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -1445,13 +1454,13 @@
/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
* @brief Time Input Capture functions
*
-@verbatim
+@verbatim
==============================================================================
##### Time Input Capture functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM Input Capture.
+ (+) Initialize and configure the TIM Input Capture.
(+) De-initialize the TIM Input Capture.
(+) Start the Time Input Capture.
(+) Stop the Time Input Capture.
@@ -1459,7 +1468,7 @@
(+) Stop the Time Input Capture and disable interrupt.
(+) Start the Time Input Capture and enable DMA transfer.
(+) Stop the Time Input Capture and disable DMA transfer.
-
+
@endverbatim
* @{
*/
@@ -1480,23 +1489,26 @@
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
- assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspInit(htim);
}
-
+
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the base time for the input capture */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
+ htim->State= HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the input capture */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
/* Initialize the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
return HAL_OK;
}
@@ -1509,18 +1521,18 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspDeInit(htim);
-
- /* Change TIM state */
+
+ /* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
-
+
/* Release Lock */
__HAL_UNLOCK(htim);
@@ -1566,16 +1578,16 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ __HAL_TIM_ENABLE(htim);
/* Return function status */
- return HAL_OK;
-}
+ return HAL_OK;
+}
/**
* @brief Stops the TIM Input Capture measurement.
@@ -1589,16 +1601,16 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
+{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
/* Disable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -1618,49 +1630,49 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
break;
- }
+ }
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ __HAL_TIM_ENABLE(htim);
/* Return function status */
- return HAL_OK;
-}
+ return HAL_OK;
+}
/**
* @brief Stops the TIM Input Capture measurement in interrupt mode.
@@ -1677,47 +1689,47 @@
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
}
break;
-
+
default:
- break;
- }
-
+ break;
+ }
+
/* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -1740,99 +1752,99 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((pData == 0 ) && (Length > 0))
+ if((pData == 0 ) && (Length > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
-
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
- /* Enable the TIM Capture/Compare 1 DMA request */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
-
+
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
-
+
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
-
+
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
}
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
+
/* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
-
+ __HAL_TIM_ENABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -1853,50 +1865,50 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
- {
+ {
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
}
break;
-
+
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
}
break;
-
+
default:
break;
}
/* Disable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -1907,13 +1919,13 @@
/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
* @brief Time One Pulse functions
*
-@verbatim
+@verbatim
==============================================================================
##### Time One Pulse functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM One Pulse.
+ (+) Initialize and configure the TIM One Pulse.
(+) De-initialize the TIM One Pulse.
(+) Start the Time One Pulse.
(+) Stop the Time One Pulse.
@@ -1921,7 +1933,7 @@
(+) Stop the Time One Pulse and disable interrupt.
(+) Start the Time One Pulse and enable DMA transfer.
(+) Stop the Time One Pulse and disable DMA transfer.
-
+
@endverbatim
* @{
*/
@@ -1948,33 +1960,36 @@
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
-
+
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OnePulse_MspInit(htim);
}
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
+
/* Configure the Time base in the One Pulse Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
+
/* Reset the OPM Bit */
htim->Instance->CR1 &= ~TIM_CR1_OPM;
/* Configure the OPM Mode */
htim->Instance->CR1 |= OnePulseMode;
-
+
/* Initialize the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
return HAL_OK;
}
/**
- * @brief DeInitializes the TIM One Pulse
+ * @brief DeInitializes the TIM One Pulse
* @param htim : TIM One Pulse handle
* @retval HAL status
*/
@@ -1982,18 +1997,18 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_OnePulse_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
/* Release Lock */
__HAL_UNLOCK(htim);
@@ -2040,19 +2055,19 @@
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
+
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
-
+
/* Return function status */
return HAL_OK;
}
@@ -2073,19 +2088,19 @@
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -2106,25 +2121,25 @@
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
+
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
-
+
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
+
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
-
+
/* Return function status */
return HAL_OK;
}
@@ -2141,28 +2156,28 @@
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
/* Disable the TIM Capture/Compare 1 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
+
/* Disable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Disable the Main Ouput */
__HAL_TIM_MOE_DISABLE(htim);
}
-
+
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
-
+ __HAL_TIM_DISABLE(htim);
+
/* Return function status */
return HAL_OK;
}
@@ -2174,13 +2189,13 @@
/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
* @brief Time Encoder functions
*
-@verbatim
+@verbatim
==============================================================================
##### Time Encoder functions #####
==============================================================================
[..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM Encoder.
+ (+) Initialize and configure the TIM Encoder.
(+) De-initialize the TIM Encoder.
(+) Start the Time Encoder.
(+) Stop the Time Encoder.
@@ -2188,7 +2203,7 @@
(+) Stop the Time Encoder and disable interrupt.
(+) Start the Time Encoder and enable DMA transfer.
(+) Stop the Time Encoder and disable DMA transfer.
-
+
@endverbatim
* @{
*/
@@ -2203,13 +2218,13 @@
uint32_t tmpsmcr = 0;
uint32_t tmpccmr1 = 0;
uint32_t tmpccer = 0;
-
+
/* Check the TIM handle allocation */
if(htim == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
@@ -2223,20 +2238,23 @@
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
}
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
+
/* Reset the SMS bits */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-
+
/* Configure the Time base in the Encoder Mode */
- TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
@@ -2252,7 +2270,7 @@
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
-
+
/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
@@ -2263,7 +2281,7 @@
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
-
+
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
@@ -2272,16 +2290,16 @@
/* Write to TIMx CCER */
htim->Instance->CCER = tmpccer;
-
+
/* Initialize the TIM state*/
htim->State= HAL_TIM_STATE_READY;
-
+
return HAL_OK;
}
/**
- * @brief DeInitializes the TIM Encoder interface
+ * @brief DeInitializes the TIM Encoder interface
* @param htim : TIM Encoder handle
* @retval HAL status
*/
@@ -2289,18 +2307,18 @@
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_Encoder_MspDeInit(htim);
-
- /* Change TIM state */
- htim->State = HAL_TIM_STATE_RESET;
-
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
/* Release Lock */
__HAL_UNLOCK(htim);
@@ -2338,36 +2356,37 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
/* Enable the encoder interface channels */
switch (Channel)
{
case TIM_CHANNEL_1:
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- break;
- }
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
break;
- }
+ }
default :
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
}
- }
+ }
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -2379,38 +2398,39 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
/* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
switch (Channel)
{
case TIM_CHANNEL_1:
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- break;
- }
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ break;
+ }
case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
break;
- }
+ }
default :
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
}
}
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -2422,42 +2442,43 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
/* Enable the encoder interface channels */
/* Enable the capture compare Interrupts 1 and/or 2 */
switch (Channel)
{
case TIM_CHANNEL_1:
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- break;
- }
+ break;
+ }
case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
break;
- }
+ }
default :
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
+ break;
}
- }
-
+ }
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Return function status */
return HAL_OK;
}
@@ -2469,45 +2490,46 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
/* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
if(Channel == TIM_CHANNEL_1)
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
/* Disable the capture compare Interrupts 1 */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
- }
+ }
else if(Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
/* Disable the capture compare Interrupts 2 */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- }
+ }
else
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
/* Disable the capture compare Interrupts 1 and 2 */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -2519,6 +2541,7 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @param pData1 : The destination Buffer address for IC1.
* @param pData2 : The destination Buffer address for IC2.
* @param Length : The length of data to be transferred from TIM peripheral to memory.
@@ -2528,105 +2551,105 @@
{
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
+ if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
-
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
-
- /* Enable the TIM Input Capture DMA request */
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
+
+ /* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
}
break;
-
+
case TIM_CHANNEL_2:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
+
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
}
break;
-
+
case TIM_CHANNEL_ALL:
{
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
-
+
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
+
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
-
+
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
+
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
}
break;
-
+
default:
break;
- }
+ }
/* Return function status */
return HAL_OK;
}
@@ -2638,45 +2661,46 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
+
/* Disable the Input Capture channels 1 and 2
- (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
if(Channel == TIM_CHANNEL_1)
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
/* Disable the capture compare DMA Request 1 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
- }
+ }
else if(Channel == TIM_CHANNEL_2)
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
/* Disable the capture compare DMA Request 2 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
- }
+ }
else
{
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
/* Disable the capture compare DMA Request 1 and 2 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
-
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
-
+
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -2687,13 +2711,13 @@
/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
* @brief IRQ handler management
*
-@verbatim
+@verbatim
==============================================================================
##### IRQ handler management #####
- ==============================================================================
- [..]
+ ==============================================================================
+ [..]
This section provides Timer IRQ handler function.
-
+
@endverbatim
* @{
*/
@@ -2707,12 +2731,12 @@
/* Capture compare 1 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
+
/* Input capture event */
if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
{
@@ -2731,13 +2755,34 @@
/* Capture compare 2 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
- {
+ {
+ HAL_TIM_IC_CaptureCallback(htim);
+ }
+ /* Output compare event */
+ else
+ {
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 3 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ /* Input capture event */
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
+ {
HAL_TIM_IC_CaptureCallback(htim);
}
/* Output compare event */
@@ -2747,39 +2792,18 @@
HAL_TIM_PWM_PulseFinishedCallback(htim);
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
- }
- /* Capture compare 3 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
- {
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
- {
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- /* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
- {
- HAL_TIM_IC_CaptureCallback(htim);
- }
- /* Output compare event */
- else
- {
- HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
- }
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* Capture compare 4 event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
- {
+ {
HAL_TIM_IC_CaptureCallback(htim);
}
/* Output compare event */
@@ -2789,13 +2813,13 @@
HAL_TIM_PWM_PulseFinishedCallback(htim);
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- }
+ }
}
/* TIM Update event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
- {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
+ {
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
HAL_TIM_PeriodElapsedCallback(htim);
}
@@ -2803,8 +2827,8 @@
/* TIM Break input event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
- {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+ {
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
HAL_TIMEx_BreakCallback(htim);
}
@@ -2812,8 +2836,8 @@
/* TIM Trigger detection event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
- {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
+ {
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
HAL_TIM_TriggerCallback(htim);
}
@@ -2821,8 +2845,8 @@
/* TIM commutation event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
{
- if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
- {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
+ {
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
HAL_TIMEx_CommutationCallback(htim);
}
@@ -2836,22 +2860,22 @@
/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
* @brief Peripheral Control functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral Control functions #####
- ==============================================================================
- [..]
+ ==============================================================================
+ [..]
This section provides functions allowing to:
- (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
(+) Configure External Clock source.
(+) Configure Complementary channels, break features and dead time.
(+) Configure Master and the Slave synchronization.
(+) Configure the DMA Burst Mode.
-
+
@endverbatim
* @{
*/
-
+
/**
* @brief Initializes the TIM Output Compare Channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
@@ -2868,18 +2892,18 @@
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
-
+
/* Check input state */
- __HAL_LOCK(htim);
-
+ __HAL_LOCK(htim);
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -2889,7 +2913,7 @@
TIM_OC1_SetConfig(htim->Instance, sConfig);
}
break;
-
+
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
@@ -2897,7 +2921,7 @@
TIM_OC2_SetConfig(htim->Instance, sConfig);
}
break;
-
+
case TIM_CHANNEL_3:
{
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
@@ -2905,7 +2929,7 @@
TIM_OC3_SetConfig(htim->Instance, sConfig);
}
break;
-
+
case TIM_CHANNEL_4:
{
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
@@ -2913,14 +2937,14 @@
TIM_OC4_SetConfig(htim->Instance, sConfig);
}
break;
-
+
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
+
+ __HAL_UNLOCK(htim);
+
return HAL_OK;
}
@@ -2945,11 +2969,11 @@
assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-
+
__HAL_LOCK(htim);
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
if (Channel == TIM_CHANNEL_1)
{
/* TI1 Configuration */
@@ -2957,7 +2981,7 @@
sConfig->ICPolarity,
sConfig->ICSelection,
sConfig->ICFilter);
-
+
/* Reset the IC1PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
@@ -2968,12 +2992,12 @@
{
/* TI2 Configuration */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
- TIM_TI2_SetConfig(htim->Instance,
+
+ TIM_TI2_SetConfig(htim->Instance,
sConfig->ICPolarity,
sConfig->ICSelection,
sConfig->ICFilter);
-
+
/* Reset the IC2PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
@@ -2984,12 +3008,12 @@
{
/* TI3 Configuration */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
- TIM_TI3_SetConfig(htim->Instance,
+
+ TIM_TI3_SetConfig(htim->Instance,
sConfig->ICPolarity,
sConfig->ICSelection,
sConfig->ICFilter);
-
+
/* Reset the IC3PSC Bits */
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
@@ -3000,24 +3024,24 @@
{
/* TI4 Configuration */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
- TIM_TI4_SetConfig(htim->Instance,
+
+ TIM_TI4_SetConfig(htim->Instance,
sConfig->ICPolarity,
sConfig->ICSelection,
sConfig->ICFilter);
-
+
/* Reset the IC4PSC Bits */
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
/* Set the IC4PSC value */
htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
}
-
+
htim->State = HAL_TIM_STATE_READY;
-
+
__HAL_UNLOCK(htim);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
@@ -3036,18 +3060,18 @@
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
{
__HAL_LOCK(htim);
-
- /* Check the parameters */
- assert_param(IS_TIM_CHANNELS(Channel));
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
- assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -3055,69 +3079,69 @@
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
-
+
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
+
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
htim->Instance->CCMR1 |= sConfig->OCFastMode;
}
break;
-
+
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
-
+
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
+
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
}
break;
-
+
case TIM_CHANNEL_3:
{
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
-
+
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
+
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
}
break;
-
+
case TIM_CHANNEL_4:
{
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
-
+
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
+
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
}
break;
-
+
default:
- break;
+ break;
}
-
+
htim->State = HAL_TIM_STATE_READY;
-
+
__HAL_UNLOCK(htim);
-
+
return HAL_OK;
}
@@ -3139,61 +3163,61 @@
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
{
TIM_OC_InitTypeDef temp1;
-
+
/* Check the parameters */
assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
- if(OutputChannel != InputChannel)
+ if(OutputChannel != InputChannel)
{
__HAL_LOCK(htim);
-
+
htim->State = HAL_TIM_STATE_BUSY;
- /* Extract the Ouput compare configuration from sConfig structure */
+ /* Extract the Ouput compare configuration from sConfig structure */
temp1.OCMode = sConfig->OCMode;
temp1.Pulse = sConfig->Pulse;
temp1.OCPolarity = sConfig->OCPolarity;
temp1.OCNPolarity = sConfig->OCNPolarity;
temp1.OCIdleState = sConfig->OCIdleState;
- temp1.OCNIdleState = sConfig->OCNIdleState;
-
+ temp1.OCNIdleState = sConfig->OCNIdleState;
+
switch (OutputChannel)
{
case TIM_CHANNEL_1:
{
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
- TIM_OC1_SetConfig(htim->Instance, &temp1);
+
+ TIM_OC1_SetConfig(htim->Instance, &temp1);
}
break;
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
TIM_OC2_SetConfig(htim->Instance, &temp1);
}
break;
default:
- break;
- }
+ break;
+ }
switch (InputChannel)
{
case TIM_CHANNEL_1:
{
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
+
TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
sConfig->ICSelection, sConfig->ICFilter);
-
+
/* Reset the IC1PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
/* Select the Trigger source */
htim->Instance->SMCR &= ~TIM_SMCR_TS;
htim->Instance->SMCR |= TIM_TS_TI1FP1;
-
- /* Select the Slave Mode */
+
+ /* Select the Slave Mode */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
}
@@ -3201,63 +3225,63 @@
case TIM_CHANNEL_2:
{
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
sConfig->ICSelection, sConfig->ICFilter);
-
+
/* Reset the IC2PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
+
/* Select the Trigger source */
htim->Instance->SMCR &= ~TIM_SMCR_TS;
htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
- /* Select the Slave Mode */
+
+ /* Select the Slave Mode */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
}
break;
-
+
default:
- break;
+ break;
}
-
+
htim->State = HAL_TIM_STATE_READY;
-
+
__HAL_UNLOCK(htim);
-
+
return HAL_OK;
-}
+}
else
{
return HAL_ERROR;
}
-}
+}
/**
- * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
* @param htim : TIM handle
* @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
* This parameter can be one of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_RCR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_BDTR
- * @arg TIM_DMABase_DCR
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
* @param BurstRequestSrc : TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -3269,7 +3293,7 @@
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer : The Buffer address.
* @param BurstLength : DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
@@ -3280,16 +3304,16 @@
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((BurstBuffer == 0 ) && (BurstLength > 0))
+ if((BurstBuffer == 0 ) && (BurstLength > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
@@ -3299,100 +3323,100 @@
switch(BurstRequestSrc)
{
case TIM_DMA_UPDATE:
- {
+ {
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC1:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC2:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC3:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC4:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_COM:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
-
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_TRIGGER:
- {
+ {
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
}
break;
default:
- break;
+ break;
}
/* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
/* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -3407,54 +3431,54 @@
{
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
+
/* Abort the DMA transfer (at least disable the DMA channel) */
switch(BurstRequestSrc)
{
case TIM_DMA_UPDATE:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
}
break;
case TIM_DMA_CC1:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
}
break;
case TIM_DMA_CC2:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
}
break;
case TIM_DMA_CC3:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
}
break;
case TIM_DMA_CC4:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
}
break;
case TIM_DMA_COM:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
}
break;
case TIM_DMA_TRIGGER:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
}
break;
default:
- break;
+ break;
}
-
+
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -3462,25 +3486,25 @@
* @param htim : TIM handle
* @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
* This parameter can be one of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_RCR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_BDTR
- * @arg TIM_DMABase_DCR
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
* @param BurstRequestSrc : TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -3492,7 +3516,7 @@
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
* @param BurstBuffer : The Buffer address.
* @param BurstLength : DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
@@ -3503,120 +3527,120 @@
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((BurstBuffer == 0 ) && (BurstLength > 0))
+ if((BurstBuffer == 0 ) && (BurstLength > 0))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
}
- }
+ }
switch(BurstRequestSrc)
{
case TIM_DMA_UPDATE:
- {
+ {
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC1:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC2:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC3:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_CC4:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_COM:
- {
+ {
/* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
-
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
case TIM_DMA_TRIGGER:
- {
+ {
/* Set the DMA Period elapsed callback */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
+
/* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
-
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
}
break;
default:
- break;
+ break;
}
/* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
+ htim->Instance->DCR = BurstBaseAddress | BurstLength;
+
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
+
htim->State = HAL_TIM_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -3631,54 +3655,54 @@
{
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
+
/* Abort the DMA transfer (at least disable the DMA channel) */
switch(BurstRequestSrc)
{
case TIM_DMA_UPDATE:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
}
break;
case TIM_DMA_CC1:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
}
break;
case TIM_DMA_CC2:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
}
break;
case TIM_DMA_CC3:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
}
break;
case TIM_DMA_CC4:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
}
break;
case TIM_DMA_COM:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
}
break;
case TIM_DMA_TRIGGER:
- {
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ {
+ HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
}
break;
default:
- break;
+ break;
}
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -3686,104 +3710,104 @@
* @param htim : TIM handle
* @param EventSource : specifies the event source.
* This parameter can be one of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_COM: Timer COM event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @arg TIM_EventSource_Break: Timer Break event source
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1, TIM15, TIM16 and TIM17.
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+ * @note TIM6 and TIM7 can only generate an update event.
+ * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
* @retval HAL status
- */
+ */
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-
+
/* Process Locked */
__HAL_LOCK(htim);
-
+
/* Change the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Set the event sources */
htim->Instance->EGR = EventSource;
-
+
/* Change the TIM state */
htim->State = HAL_TIM_STATE_READY;
-
+
__HAL_UNLOCK(htim);
-
+
/* Return function status */
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Configures the OCRef clear feature
* @param htim : TIM handle
* @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
- * contains the OCREF clear feature and parameters for the TIM peripheral.
+ * contains the OCREF clear feature and parameters for the TIM peripheral.
* @param Channel : specifies the TIM Channel
* This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
{
uint32_t tmpsmcr = 0;
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
+
/* Process Locked */
__HAL_LOCK(htim);
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
switch (sClearInputConfig->ClearInputSource)
{
case TIM_CLEARINPUTSOURCE_NONE:
{
/* Clear the OCREF clear selection bit */
tmpsmcr &= ~TIM_SMCR_OCCS;
-
+
/* Clear the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
+
/* Set TIMx_SMCR */
htim->Instance->SMCR = tmpsmcr;
}
break;
-
+
case TIM_CLEARINPUTSOURCE_ETR:
{
TIM_ETR_SetConfig(htim->Instance,
sClearInputConfig->ClearInputPrescaler,
sClearInputConfig->ClearInputPolarity,
sClearInputConfig->ClearInputFilter);
-
+
/* Set the OCREF clear selection bit */
htim->Instance->SMCR |= TIM_SMCR_OCCS;
}
break;
- default:
- break;
+ default:
+ break;
}
-
+
switch (Channel)
- {
+ {
case TIM_CHANNEL_1:
{
if(sClearInputConfig->ClearInputState != RESET)
@@ -3794,13 +3818,13 @@
else
{
/* Disable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
}
- }
+ }
break;
- case TIM_CHANNEL_2:
+ case TIM_CHANNEL_2:
{
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
if(sClearInputConfig->ClearInputState != RESET)
{
/* Enable the Ocref clear feature for Channel 2 */
@@ -3809,13 +3833,13 @@
else
{
/* Disable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
}
- }
+ }
break;
- case TIM_CHANNEL_3:
+ case TIM_CHANNEL_3:
{
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
if(sClearInputConfig->ClearInputState != RESET)
{
/* Enable the Ocref clear feature for Channel 3 */
@@ -3824,13 +3848,13 @@
else
{
/* Disable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
}
- }
+ }
break;
- case TIM_CHANNEL_4:
+ case TIM_CHANNEL_4:
{
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
if(sClearInputConfig->ClearInputState != RESET)
{
/* Enable the Ocref clear feature for Channel 4 */
@@ -3839,68 +3863,68 @@
else
{
/* Disable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
}
- }
+ }
break;
- default:
+ default:
break;
}
-
- htim->State = HAL_TIM_STATE_READY;
-
+
+ htim->State = HAL_TIM_STATE_READY;
+
__HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
+
+ return HAL_OK;
+}
/**
* @brief Configures the clock source to be used
* @param htim : TIM handle
* @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
- * contains the clock source information for the TIM peripheral.
+ * contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
{
uint32_t tmpsmcr = 0;
-
+
/* Process Locked */
__HAL_LOCK(htim);
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
+
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
htim->Instance->SMCR = tmpsmcr;
-
+
switch (sClockSourceConfig->ClockSource)
{
case TIM_CLOCKSOURCE_INTERNAL:
{
- assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Disable slave mode to clock the prescaler directly with the internal clock */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
}
break;
-
+
case TIM_CLOCKSOURCE_ETRMODE1:
{
/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-
+
/* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
- sClockSourceConfig->ClockPolarity,
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
@@ -3912,29 +3936,29 @@
htim->Instance->SMCR = tmpsmcr;
}
break;
-
+
case TIM_CLOCKSOURCE_ETRMODE2:
{
/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
-
+
/* Configure the ETR Clock source */
- TIM_ETR_SetConfig(htim->Instance,
- sClockSourceConfig->ClockPrescaler,
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
}
break;
-
+
case TIM_CLOCKSOURCE_TI1:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
}
@@ -3943,9 +3967,9 @@
{
/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- TIM_TI2_ConfigInputStage(htim->Instance,
- sClockSourceConfig->ClockPolarity,
+
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
}
@@ -3954,8 +3978,8 @@
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
- TIM_TI1_ConfigInputStage(htim->Instance,
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
@@ -3965,7 +3989,7 @@
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
+
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
}
break;
@@ -3973,7 +3997,7 @@
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
+
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
}
break;
@@ -3981,7 +4005,7 @@
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
+
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
}
break;
@@ -3989,18 +4013,18 @@
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
+
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
}
break;
-
+
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
-
+
__HAL_UNLOCK(htim);
-
+
return HAL_OK;
}
@@ -4019,9 +4043,9 @@
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
{
uint32_t tmpcr2 = 0;
-
+
/* Check the parameters */
- assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
/* Get the TIMx CR2 register value */
@@ -4032,7 +4056,7 @@
/* Set the the TI1 selection */
tmpcr2 |= TI1_Selection;
-
+
/* Write to TIMxCR2 */
htim->Instance->CR2 = tmpcr2;
@@ -4045,7 +4069,7 @@
* @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
* timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
@@ -4054,61 +4078,61 @@
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
+
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-
+
/* Disable Trigger Interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
-
+
/* Disable Trigger DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
+
htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
+
+ __HAL_UNLOCK(htim);
+
return HAL_OK;
}
-
+
/**
* @brief Configures the TIM in Slave mode in interrupt mode
* @param htim: TIM handle.
* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
* timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef * sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
+
__HAL_LOCK(htim);
-
+
htim->State = HAL_TIM_STATE_BUSY;
-
+
TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
-
+
/* Enable Trigger Interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
-
+
/* Disable Trigger DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
-
+
htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
+
+ __HAL_UNLOCK(htim);
+
return HAL_OK;
-}
+}
/**
* @brief Read the captured value from Capture Compare unit
@@ -4124,74 +4148,74 @@
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpreg = 0;
-
+
__HAL_LOCK(htim);
-
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
+
/* Return the capture 1 value */
tmpreg = htim->Instance->CCR1;
-
+
break;
}
case TIM_CHANNEL_2:
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
+
/* Return the capture 2 value */
tmpreg = htim->Instance->CCR2;
-
+
break;
}
-
+
case TIM_CHANNEL_3:
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
+
/* Return the capture 3 value */
tmpreg = htim->Instance->CCR3;
-
+
break;
}
-
+
case TIM_CHANNEL_4:
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
+
/* Return the capture 4 value */
tmpreg = htim->Instance->CCR4;
-
+
break;
}
-
+
default:
- break;
+ break;
}
-
- __HAL_UNLOCK(htim);
+
+ __HAL_UNLOCK(htim);
return tmpreg;
}
/**
* @}
*/
-
+
/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
* @brief TIM Callbacks functions
*
-@verbatim
+@verbatim
==============================================================================
##### TIM Callbacks functions #####
- ==============================================================================
- [..]
+ ==============================================================================
+ [..]
This section provides TIM callback functions:
(+) Timer Period elapsed callback
(+) Timer Output Compare callback
@@ -4213,7 +4237,7 @@
/* NOTE : This function Should not be modified, when the callback is needed,
the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
-
+
}
/**
* @brief Output Compare callback in non blocking mode
@@ -4281,10 +4305,10 @@
/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
* @brief Peripheral State functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral State functions #####
- ==============================================================================
+ ==============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
and the data flow.
@@ -4359,37 +4383,37 @@
/**
* @}
- */
+ */
/** @addtogroup TIM_Private_Functions TIM_Private_Functions
* @{
- */
-
+ */
+
/**
* @brief TIM DMA error callback
* @param hdma : pointer to DMA handle.
* @retval None
*/
-void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
htim->State= HAL_TIM_STATE_READY;
-
+
HAL_TIM_ErrorCallback(htim);
}
/**
- * @brief TIM DMA Delay Pulse complete callback.
+ * @brief TIM DMA Delay Pulse complete callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
-void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
+
+ htim->State= HAL_TIM_STATE_READY;
+
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
@@ -4412,16 +4436,16 @@
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
- * @brief TIM DMA Capture complete callback.
+ * @brief TIM DMA Capture complete callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
-void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
htim->State= HAL_TIM_STATE_READY;
-
+
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
@@ -4438,37 +4462,37 @@
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
}
-
- HAL_TIM_IC_CaptureCallback(htim);
-
+
+ HAL_TIM_IC_CaptureCallback(htim);
+
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
-
+
/**
- * @brief TIM DMA Period Elapse complete callback.
+ * @brief TIM DMA Period Elapse complete callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
htim->State= HAL_TIM_STATE_READY;
-
+
HAL_TIM_PeriodElapsedCallback(htim);
}
/**
- * @brief TIM DMA Trigger callback.
+ * @brief TIM DMA Trigger callback.
* @param hdma : pointer to DMA handle.
* @retval None
*/
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
+ TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ htim->State= HAL_TIM_STATE_READY;
+
HAL_TIM_TriggerCallback(htim);
}
@@ -4482,7 +4506,7 @@
{
uint32_t tmpcr1 = 0;
tmpcr1 = TIMx->CR1;
-
+
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
{
@@ -4490,7 +4514,7 @@
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
tmpcr1 |= Structure->CounterMode;
}
-
+
if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
{
/* Set the clock division */
@@ -4502,11 +4526,11 @@
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
-
+
/* Set the Prescaler value */
TIMx->PSC = (uint32_t)Structure->Prescaler;
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
@@ -4527,16 +4551,16 @@
{
uint32_t tmpccmrx = 0;
uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpcr2 = 0;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
-
+
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
+ tmpcr2 = TIMx->CR2;
+
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
@@ -4545,7 +4569,7 @@
tmpccmrx &= ~TIM_CCMR1_CC1S;
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
-
+
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
/* Set the Output Compare Polarity */
@@ -4555,7 +4579,7 @@
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
+
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
/* Set the Output N Polarity */
@@ -4563,7 +4587,7 @@
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
}
-
+
if(IS_TIM_BREAK_INSTANCE(TIMx))
{
/* Check parameters */
@@ -4580,16 +4604,16 @@
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
-
+
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
-
+
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
-
+
/* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
+ TIMx->CCER = tmpccer;
+}
/**
* @brief Time Ouput Compare 2 configuration
@@ -4601,33 +4625,33 @@
{
uint32_t tmpccmrx = 0;
uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpcr2 = 0;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
-
+
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
+ tmpcr2 = TIMx->CR2;
+
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
tmpccmrx &= ~TIM_CCMR1_CC2S;
-
+
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8);
-
+
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4);
if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- {
+ {
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
@@ -4638,7 +4662,7 @@
tmpccer |= (OC_Config->OCNPolarity << 4);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
-
+
}
if(IS_TIM_BREAK_INSTANCE(TIMx))
@@ -4658,15 +4682,15 @@
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
-
+
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
-
+
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
-
+
/* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
+ TIMx->CCER = tmpccer;
}
/**
@@ -4679,32 +4703,32 @@
{
uint32_t tmpccmrx = 0;
uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpcr2 = 0;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
-
+
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
+ tmpcr2 = TIMx->CR2;
+
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
- tmpccmrx &= ~TIM_CCMR2_CC3S;
+ tmpccmrx &= ~TIM_CCMR2_CC3S;
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
-
+
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8);
if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- {
+ {
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
@@ -4716,7 +4740,7 @@
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
}
-
+
if(IS_TIM_BREAK_INSTANCE(TIMx))
{
/* Check parameters */
@@ -4734,15 +4758,15 @@
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
-
+
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
-
+
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
-
+
/* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
+ TIMx->CCER = tmpccer;
}
/**
@@ -4755,26 +4779,26 @@
{
uint32_t tmpccmrx = 0;
uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpcr2 = 0;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
-
+
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
+ tmpcr2 = TIMx->CR2;
+
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
tmpccmrx &= ~TIM_CCMR2_CC4S;
-
+
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8);
-
+
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
/* Set the Output Compare Polarity */
@@ -4792,15 +4816,15 @@
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
-
+
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
-
+
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
-
+
/* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
+ TIMx->CCER = tmpccer;
}
void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
@@ -4825,7 +4849,7 @@
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
-
+
/* Configure the trigger prescaler, filter, and polarity */
switch (sSlaveConfig->InputTrigger)
{
@@ -4837,92 +4861,91 @@
assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
/* Configure the ETR Trigger source */
- TIM_ETR_SetConfig(htim->Instance,
- sSlaveConfig->TriggerPrescaler,
- sSlaveConfig->TriggerPolarity,
+ TIM_ETR_SetConfig(htim->Instance,
+ sSlaveConfig->TriggerPrescaler,
+ sSlaveConfig->TriggerPolarity,
sSlaveConfig->TriggerFilter);
}
break;
-
+
case TIM_TS_TI1F_ED:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
+
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = htim->Instance->CCER;
htim->Instance->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = htim->Instance->CCMR1;
-
+ tmpccmr1 = htim->Instance->CCMR1;
+
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
-
+
/* Write to TIMx CCMR1 and CCER registers */
htim->Instance->CCMR1 = tmpccmr1;
- htim->Instance->CCER = tmpccer;
-
+ htim->Instance->CCER = tmpccer;
+
}
break;
-
+
case TIM_TS_TI1FP1:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
+
/* Configure TI1 Filter and Polarity */
TIM_TI1_ConfigInputStage(htim->Instance,
sSlaveConfig->TriggerPolarity,
sSlaveConfig->TriggerFilter);
}
break;
-
+
case TIM_TS_TI2FP2:
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
+
/* Configure TI2 Filter and Polarity */
TIM_TI2_ConfigInputStage(htim->Instance,
sSlaveConfig->TriggerPolarity,
sSlaveConfig->TriggerFilter);
}
break;
-
+
case TIM_TS_ITR0:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
}
break;
-
+
case TIM_TS_ITR1:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
}
break;
-
+
case TIM_TS_ITR2:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
}
break;
-
+
case TIM_TS_ITR3:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
}
break;
-
+
default:
break;
}
@@ -4933,14 +4956,14 @@
* @param TIMx to select the TIM peripheral.
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI : TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI : TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC : TIM Input 1 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC.
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -4964,12 +4987,12 @@
{
tmpccmr1 &= ~TIM_CCMR1_CC1S;
tmpccmr1 |= TIM_ICSelection;
- }
+ }
else
{
tmpccmr1 |= TIM_CCMR1_CC1S_0;
}
-
+
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
@@ -4988,9 +5011,9 @@
* @param TIMx to select the TIM peripheral.
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -4999,20 +5022,20 @@
{
uint32_t tmpccmr1 = 0;
uint32_t tmpccer = 0;
-
+
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC1E;
- tmpccmr1 = TIMx->CCMR1;
-
+ tmpccmr1 = TIMx->CCMR1;
+
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
tmpccmr1 |= (TIM_ICFilter << 4);
-
+
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
tmpccer |= TIM_ICPolarity;
-
+
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
TIMx->CCER = tmpccer;
@@ -5023,14 +5046,14 @@
* @param TIMx to select the TIM peripheral
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI : TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI : TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC : TIM Input 2 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC.
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -5071,9 +5094,9 @@
* @param TIMx to select the TIM peripheral.
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -5082,12 +5105,12 @@
{
uint32_t tmpccmr1 = 0;
uint32_t tmpccer = 0;
-
+
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1;
tmpccer = TIMx->CCER;
-
+
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
tmpccmr1 |= (TIM_ICFilter << 12);
@@ -5106,14 +5129,14 @@
* @param TIMx to select the TIM peripheral
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI : TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI : TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC : TIM Input 3 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC.
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
@@ -5154,14 +5177,14 @@
* @param TIMx to select the TIM peripheral
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @arg TIM_ICPolarity_BothEdge
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI : TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI : TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC : TIM Input 4 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC.
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
@@ -5215,7 +5238,7 @@
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
{
uint32_t tmpsmcr = 0;
-
+
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
/* Reset the TS Bits */
@@ -5257,19 +5280,19 @@
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
-}
+}
/**
* @brief Enables or disables the TIM Capture Compare Channel x.
* @param TIMx to select the TIM peripheral
* @param Channel : specifies the TIM Channel
* This parameter can be one of the following values:
- * @arg TIM_Channel_1 : TIM Channel 1
- * @arg TIM_Channel_2 : TIM Channel 2
- * @arg TIM_Channel_3 : TIM Channel 3
- * @arg TIM_Channel_4 : TIM Channel 4
+ * @arg TIM_CHANNEL_1 : TIM Channel 1
+ * @arg TIM_CHANNEL_2 : TIM Channel 2
+ * @arg TIM_CHANNEL_3 : TIM Channel 3
+ * @arg TIM_CHANNEL_4 : TIM Channel 4
* @param ChannelState : specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
@@ -5277,7 +5300,7 @@
uint32_t tmp = 0;
/* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << Channel;
@@ -5285,7 +5308,7 @@
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
- /* Set or reset the CCxE Bit */
+ /* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << Channel);
}
@@ -5297,9 +5320,9 @@
#endif /* HAL_TIM_MODULE_ENABLED */
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
