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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c@630:825f75ca301e, 2015-09-28 (annotated)

Committer:
mbed_official
Date:
Mon Sep 28 10:45:10 2015 +0100
Revision:
630:825f75ca301e
Parent:
441:d2c15dda23c1 
Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10



Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/



NUCLEO_F031K6 : Add new target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 340:28d1f895c6fe 1 /**
mbed_official 340:28d1f895c6fe 2 ******************************************************************************
mbed_official 340:28d1f895c6fe 3 * @file stm32f0xx_hal_tim.c
mbed_official 340:28d1f895c6fe 4 * @author MCD Application Team
mbed_official 630:825f75ca301e 5 * @version V1.3.0
mbed_official 630:825f75ca301e 6 * @date 26-June-2015
mbed_official 340:28d1f895c6fe 7 * @brief TIM HAL module driver.
mbed_official 340:28d1f895c6fe 8 * This file provides firmware functions to manage the following
mbed_official 340:28d1f895c6fe 9 * functionalities of the Timer (TIM) peripheral:
mbed_official 340:28d1f895c6fe 10 * + Time Base Initialization
mbed_official 340:28d1f895c6fe 11 * + Time Base Start
mbed_official 340:28d1f895c6fe 12 * + Time Base Start Interruption
mbed_official 340:28d1f895c6fe 13 * + Time Base Start DMA
mbed_official 340:28d1f895c6fe 14 * + Time Output Compare/PWM Initialization
mbed_official 340:28d1f895c6fe 15 * + Time Output Compare/PWM Channel Configuration
mbed_official 340:28d1f895c6fe 16 * + Time Output Compare/PWM Start
mbed_official 340:28d1f895c6fe 17 * + Time Output Compare/PWM Start Interruption
mbed_official 340:28d1f895c6fe 18 * + Time Output Compare/PWM Start DMA
mbed_official 340:28d1f895c6fe 19 * + Time Input Capture Initialization
mbed_official 340:28d1f895c6fe 20 * + Time Input Capture Channel Configuration
mbed_official 340:28d1f895c6fe 21 * + Time Input Capture Start
mbed_official 340:28d1f895c6fe 22 * + Time Input Capture Start Interruption
mbed_official 340:28d1f895c6fe 23 * + Time Input Capture Start DMA
mbed_official 340:28d1f895c6fe 24 * + Time One Pulse Initialization
mbed_official 340:28d1f895c6fe 25 * + Time One Pulse Channel Configuration
mbed_official 340:28d1f895c6fe 26 * + Time One Pulse Start
mbed_official 340:28d1f895c6fe 27 * + Time Encoder Interface Initialization
mbed_official 340:28d1f895c6fe 28 * + Time Encoder Interface Start
mbed_official 340:28d1f895c6fe 29 * + Time Encoder Interface Start Interruption
mbed_official 340:28d1f895c6fe 30 * + Time Encoder Interface Start DMA
mbed_official 340:28d1f895c6fe 31 * + Commutation Event configuration with Interruption and DMA
mbed_official 340:28d1f895c6fe 32 * + Time OCRef clear configuration
mbed_official 340:28d1f895c6fe 33 * + Time External Clock configuration
mbed_official 340:28d1f895c6fe 34 @verbatim
mbed_official 340:28d1f895c6fe 35 ==============================================================================
mbed_official 340:28d1f895c6fe 36 ##### TIMER Generic features #####
mbed_official 340:28d1f895c6fe 37 ==============================================================================
mbed_official 630:825f75ca301e 38 [..] The Timer features include:
mbed_official 340:28d1f895c6fe 39 (#) 16-bit up, down, up/down auto-reload counter.
mbed_official 340:28d1f895c6fe 40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
mbed_official 340:28d1f895c6fe 41 counter clock frequency either by any factor between 1 and 65536.
mbed_official 340:28d1f895c6fe 42 (#) Up to 4 independent channels for:
mbed_official 340:28d1f895c6fe 43 (++) Input Capture
mbed_official 340:28d1f895c6fe 44 (++) Output Compare
mbed_official 340:28d1f895c6fe 45 (++) PWM generation (Edge and Center-aligned Mode)
mbed_official 630:825f75ca301e 46 (++) One-pulse mode output
mbed_official 630:825f75ca301e 47
mbed_official 340:28d1f895c6fe 48 ##### How to use this driver #####
mbed_official 340:28d1f895c6fe 49 ==============================================================================
mbed_official 340:28d1f895c6fe 50 [..]
mbed_official 340:28d1f895c6fe 51 (#) Initialize the TIM low level resources by implementing the following functions
mbed_official 340:28d1f895c6fe 52 depending from feature used :
mbed_official 630:825f75ca301e 53 (++) Time Base : HAL_TIM_Base_MspInit()
mbed_official 340:28d1f895c6fe 54 (++) Input Capture : HAL_TIM_IC_MspInit()
mbed_official 340:28d1f895c6fe 55 (++) Output Compare : HAL_TIM_OC_MspInit()
mbed_official 340:28d1f895c6fe 56 (++) PWM generation : HAL_TIM_PWM_MspInit()
mbed_official 340:28d1f895c6fe 57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
mbed_official 340:28d1f895c6fe 58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
mbed_official 630:825f75ca301e 59
mbed_official 340:28d1f895c6fe 60 (#) Initialize the TIM low level resources :
mbed_official 630:825f75ca301e 61 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
mbed_official 340:28d1f895c6fe 62 (##) TIM pins configuration
mbed_official 340:28d1f895c6fe 63 (+++) Enable the clock for the TIM GPIOs using the following function:
mbed_official 630:825f75ca301e 64 __HAL_RCC_GPIOx_CLK_ENABLE();
mbed_official 630:825f75ca301e 65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
mbed_official 340:28d1f895c6fe 66
mbed_official 340:28d1f895c6fe 67 (#) The external Clock can be configured, if needed (the default clock is the
mbed_official 340:28d1f895c6fe 68 internal clock from the APBx), using the following function:
mbed_official 340:28d1f895c6fe 69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
mbed_official 340:28d1f895c6fe 70 any start function.
mbed_official 630:825f75ca301e 71
mbed_official 340:28d1f895c6fe 72 (#) Configure the TIM in the desired functioning mode using one of the
mbed_official 340:28d1f895c6fe 73 Initialization function of this driver:
mbed_official 340:28d1f895c6fe 74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
mbed_official 340:28d1f895c6fe 75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
mbed_official 340:28d1f895c6fe 76 Output Compare signal.
mbed_official 340:28d1f895c6fe 77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
mbed_official 340:28d1f895c6fe 78 PWM signal.
mbed_official 340:28d1f895c6fe 79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
mbed_official 340:28d1f895c6fe 80 external signal.
mbed_official 340:28d1f895c6fe 81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
mbed_official 340:28d1f895c6fe 82 in One Pulse Mode.
mbed_official 340:28d1f895c6fe 83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
mbed_official 340:28d1f895c6fe 84
mbed_official 630:825f75ca301e 85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
mbed_official 340:28d1f895c6fe 86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
mbed_official 340:28d1f895c6fe 87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
mbed_official 340:28d1f895c6fe 88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
mbed_official 340:28d1f895c6fe 89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
mbed_official 340:28d1f895c6fe 90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
mbed_official 340:28d1f895c6fe 91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
mbed_official 340:28d1f895c6fe 92
mbed_official 340:28d1f895c6fe 93 (#) The DMA Burst is managed with the two following functions:
mbed_official 340:28d1f895c6fe 94 HAL_TIM_DMABurst_WriteStart()
mbed_official 340:28d1f895c6fe 95 HAL_TIM_DMABurst_ReadStart()
mbed_official 630:825f75ca301e 96
mbed_official 340:28d1f895c6fe 97 @endverbatim
mbed_official 340:28d1f895c6fe 98 ******************************************************************************
mbed_official 340:28d1f895c6fe 99 * @attention
mbed_official 340:28d1f895c6fe 100 *
mbed_official 630:825f75ca301e 101 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 340:28d1f895c6fe 102 *
mbed_official 340:28d1f895c6fe 103 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 340:28d1f895c6fe 104 * are permitted provided that the following conditions are met:
mbed_official 340:28d1f895c6fe 105 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 340:28d1f895c6fe 106 * this list of conditions and the following disclaimer.
mbed_official 340:28d1f895c6fe 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 340:28d1f895c6fe 108 * this list of conditions and the following disclaimer in the documentation
mbed_official 340:28d1f895c6fe 109 * and/or other materials provided with the distribution.
mbed_official 340:28d1f895c6fe 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 340:28d1f895c6fe 111 * may be used to endorse or promote products derived from this software
mbed_official 340:28d1f895c6fe 112 * without specific prior written permission.
mbed_official 340:28d1f895c6fe 113 *
mbed_official 340:28d1f895c6fe 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 340:28d1f895c6fe 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 340:28d1f895c6fe 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 340:28d1f895c6fe 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 340:28d1f895c6fe 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 340:28d1f895c6fe 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 340:28d1f895c6fe 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 340:28d1f895c6fe 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 340:28d1f895c6fe 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 340:28d1f895c6fe 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 340:28d1f895c6fe 124 *
mbed_official 630:825f75ca301e 125 ******************************************************************************
mbed_official 630:825f75ca301e 126 */
mbed_official 340:28d1f895c6fe 127
mbed_official 340:28d1f895c6fe 128 /* Includes ------------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 129 #include "stm32f0xx_hal.h"
mbed_official 340:28d1f895c6fe 130
mbed_official 340:28d1f895c6fe 131 /** @addtogroup STM32F0xx_HAL_Driver
mbed_official 340:28d1f895c6fe 132 * @{
mbed_official 340:28d1f895c6fe 133 */
mbed_official 340:28d1f895c6fe 134
mbed_official 630:825f75ca301e 135 /** @defgroup TIM TIM
mbed_official 340:28d1f895c6fe 136 * @brief TIM HAL module driver
mbed_official 340:28d1f895c6fe 137 * @{
mbed_official 340:28d1f895c6fe 138 */
mbed_official 340:28d1f895c6fe 139
mbed_official 340:28d1f895c6fe 140 #ifdef HAL_TIM_MODULE_ENABLED
mbed_official 340:28d1f895c6fe 141
mbed_official 340:28d1f895c6fe 142 /* Private typedef -----------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 143 /* Private define ------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 144 /* Private macro -------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 145 /* Private variables ---------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 146 /* Private function prototypes -----------------------------------------------*/
mbed_official 340:28d1f895c6fe 147
mbed_official 340:28d1f895c6fe 148 /** @defgroup TIM_Private_Functions TIM_Private_Functions
mbed_official 340:28d1f895c6fe 149 * @{
mbed_official 340:28d1f895c6fe 150 */
mbed_official 340:28d1f895c6fe 151 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 340:28d1f895c6fe 152 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 340:28d1f895c6fe 153 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 340:28d1f895c6fe 154 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official 340:28d1f895c6fe 155 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 340:28d1f895c6fe 156 uint32_t TIM_ICFilter);
mbed_official 340:28d1f895c6fe 157 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official 340:28d1f895c6fe 158 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 340:28d1f895c6fe 159 uint32_t TIM_ICFilter);
mbed_official 340:28d1f895c6fe 160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 340:28d1f895c6fe 161 uint32_t TIM_ICFilter);
mbed_official 340:28d1f895c6fe 162 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official 340:28d1f895c6fe 163 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
mbed_official 340:28d1f895c6fe 164 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
mbed_official 340:28d1f895c6fe 165 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 166 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 167 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
mbed_official 340:28d1f895c6fe 168 TIM_SlaveConfigTypeDef * sSlaveConfig);
mbed_official 340:28d1f895c6fe 169
mbed_official 340:28d1f895c6fe 170 /**
mbed_official 340:28d1f895c6fe 171 * @}
mbed_official 340:28d1f895c6fe 172 */
mbed_official 340:28d1f895c6fe 173
mbed_official 340:28d1f895c6fe 174 /* Exported functions ---------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 175
mbed_official 340:28d1f895c6fe 176 /** @defgroup TIM_Exported_Functions TIM Exported Functions
mbed_official 340:28d1f895c6fe 177 * @{
mbed_official 340:28d1f895c6fe 178 */
mbed_official 340:28d1f895c6fe 179
mbed_official 340:28d1f895c6fe 180 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
mbed_official 340:28d1f895c6fe 181 * @brief Time Base functions
mbed_official 340:28d1f895c6fe 182 *
mbed_official 630:825f75ca301e 183 @verbatim
mbed_official 340:28d1f895c6fe 184 ==============================================================================
mbed_official 340:28d1f895c6fe 185 ##### Time Base functions #####
mbed_official 340:28d1f895c6fe 186 ==============================================================================
mbed_official 630:825f75ca301e 187 [..]
mbed_official 340:28d1f895c6fe 188 This section provides functions allowing to:
mbed_official 630:825f75ca301e 189 (+) Initialize and configure the TIM base.
mbed_official 340:28d1f895c6fe 190 (+) De-initialize the TIM base.
mbed_official 340:28d1f895c6fe 191 (+) Start the Time Base.
mbed_official 340:28d1f895c6fe 192 (+) Stop the Time Base.
mbed_official 340:28d1f895c6fe 193 (+) Start the Time Base and enable interrupt.
mbed_official 340:28d1f895c6fe 194 (+) Stop the Time Base and disable interrupt.
mbed_official 340:28d1f895c6fe 195 (+) Start the Time Base and enable DMA transfer.
mbed_official 340:28d1f895c6fe 196 (+) Stop the Time Base and disable DMA transfer.
mbed_official 630:825f75ca301e 197
mbed_official 340:28d1f895c6fe 198 @endverbatim
mbed_official 340:28d1f895c6fe 199 * @{
mbed_official 340:28d1f895c6fe 200 */
mbed_official 340:28d1f895c6fe 201 /**
mbed_official 340:28d1f895c6fe 202 * @brief Initializes the TIM Time base Unit according to the specified
mbed_official 340:28d1f895c6fe 203 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 340:28d1f895c6fe 204 * @param htim : TIM Base handle
mbed_official 340:28d1f895c6fe 205 * @retval HAL status
mbed_official 340:28d1f895c6fe 206 */
mbed_official 340:28d1f895c6fe 207 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
mbed_official 630:825f75ca301e 208 {
mbed_official 340:28d1f895c6fe 209 /* Check the TIM handle allocation */
mbed_official 441:d2c15dda23c1 210 if(htim == NULL)
mbed_official 340:28d1f895c6fe 211 {
mbed_official 340:28d1f895c6fe 212 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 213 }
mbed_official 630:825f75ca301e 214
mbed_official 340:28d1f895c6fe 215 /* Check the parameters */
mbed_official 630:825f75ca301e 216 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 217 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 340:28d1f895c6fe 218 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 630:825f75ca301e 219
mbed_official 340:28d1f895c6fe 220 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 630:825f75ca301e 221 {
mbed_official 630:825f75ca301e 222 /* Allocate lock resource and initialize it */
mbed_official 630:825f75ca301e 223 htim->Lock = HAL_UNLOCKED;
mbed_official 630:825f75ca301e 224
mbed_official 340:28d1f895c6fe 225 /* Init the low level hardware : GPIO, CLOCK, NVIC */
mbed_official 340:28d1f895c6fe 226 HAL_TIM_Base_MspInit(htim);
mbed_official 340:28d1f895c6fe 227 }
mbed_official 630:825f75ca301e 228
mbed_official 340:28d1f895c6fe 229 /* Set the TIM state */
mbed_official 340:28d1f895c6fe 230 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 231
mbed_official 340:28d1f895c6fe 232 /* Set the Time Base configuration */
mbed_official 630:825f75ca301e 233 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 630:825f75ca301e 234
mbed_official 340:28d1f895c6fe 235 /* Initialize the TIM state*/
mbed_official 340:28d1f895c6fe 236 htim->State= HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 237
mbed_official 340:28d1f895c6fe 238 return HAL_OK;
mbed_official 340:28d1f895c6fe 239 }
mbed_official 340:28d1f895c6fe 240
mbed_official 340:28d1f895c6fe 241 /**
mbed_official 340:28d1f895c6fe 242 * @brief DeInitializes the TIM Base peripheral
mbed_official 340:28d1f895c6fe 243 * @param htim : TIM Base handle
mbed_official 340:28d1f895c6fe 244 * @retval HAL status
mbed_official 340:28d1f895c6fe 245 */
mbed_official 340:28d1f895c6fe 246 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 247 {
mbed_official 340:28d1f895c6fe 248 /* Check the parameters */
mbed_official 340:28d1f895c6fe 249 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 250
mbed_official 340:28d1f895c6fe 251 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 252
mbed_official 340:28d1f895c6fe 253 /* Disable the TIM Peripheral Clock */
mbed_official 340:28d1f895c6fe 254 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 255
mbed_official 340:28d1f895c6fe 256 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 340:28d1f895c6fe 257 HAL_TIM_Base_MspDeInit(htim);
mbed_official 630:825f75ca301e 258
mbed_official 630:825f75ca301e 259 /* Change TIM state */
mbed_official 630:825f75ca301e 260 htim->State = HAL_TIM_STATE_RESET;
mbed_official 630:825f75ca301e 261
mbed_official 340:28d1f895c6fe 262 /* Release Lock */
mbed_official 340:28d1f895c6fe 263 __HAL_UNLOCK(htim);
mbed_official 340:28d1f895c6fe 264
mbed_official 340:28d1f895c6fe 265 return HAL_OK;
mbed_official 340:28d1f895c6fe 266 }
mbed_official 340:28d1f895c6fe 267
mbed_official 340:28d1f895c6fe 268 /**
mbed_official 340:28d1f895c6fe 269 * @brief Initializes the TIM Base MSP.
mbed_official 340:28d1f895c6fe 270 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 271 * @retval None
mbed_official 340:28d1f895c6fe 272 */
mbed_official 340:28d1f895c6fe 273 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 274 {
mbed_official 340:28d1f895c6fe 275 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 276 the HAL_TIM_Base_MspInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 277 */
mbed_official 340:28d1f895c6fe 278 }
mbed_official 340:28d1f895c6fe 279
mbed_official 340:28d1f895c6fe 280 /**
mbed_official 340:28d1f895c6fe 281 * @brief DeInitializes TIM Base MSP.
mbed_official 340:28d1f895c6fe 282 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 283 * @retval None
mbed_official 340:28d1f895c6fe 284 */
mbed_official 340:28d1f895c6fe 285 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 286 {
mbed_official 340:28d1f895c6fe 287 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 288 the HAL_TIM_Base_MspDeInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 289 */
mbed_official 340:28d1f895c6fe 290 }
mbed_official 340:28d1f895c6fe 291
mbed_official 340:28d1f895c6fe 292
mbed_official 340:28d1f895c6fe 293 /**
mbed_official 340:28d1f895c6fe 294 * @brief Starts the TIM Base generation.
mbed_official 340:28d1f895c6fe 295 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 296 * @retval HAL status
mbed_official 340:28d1f895c6fe 297 */
mbed_official 340:28d1f895c6fe 298 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 299 {
mbed_official 340:28d1f895c6fe 300 /* Check the parameters */
mbed_official 340:28d1f895c6fe 301 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 302
mbed_official 340:28d1f895c6fe 303 /* Set the TIM state */
mbed_official 340:28d1f895c6fe 304 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 305
mbed_official 340:28d1f895c6fe 306 /* Enable the Peripheral */
mbed_official 340:28d1f895c6fe 307 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 308
mbed_official 340:28d1f895c6fe 309 /* Change the TIM state*/
mbed_official 340:28d1f895c6fe 310 htim->State= HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 311
mbed_official 340:28d1f895c6fe 312 /* Return function status */
mbed_official 340:28d1f895c6fe 313 return HAL_OK;
mbed_official 340:28d1f895c6fe 314 }
mbed_official 340:28d1f895c6fe 315
mbed_official 340:28d1f895c6fe 316 /**
mbed_official 340:28d1f895c6fe 317 * @brief Stops the TIM Base generation.
mbed_official 340:28d1f895c6fe 318 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 319 * @retval HAL status
mbed_official 340:28d1f895c6fe 320 */
mbed_official 340:28d1f895c6fe 321 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 322 {
mbed_official 340:28d1f895c6fe 323 /* Check the parameters */
mbed_official 340:28d1f895c6fe 324 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 325
mbed_official 340:28d1f895c6fe 326 /* Set the TIM state */
mbed_official 340:28d1f895c6fe 327 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 328
mbed_official 340:28d1f895c6fe 329 /* Disable the Peripheral */
mbed_official 340:28d1f895c6fe 330 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 331
mbed_official 340:28d1f895c6fe 332 /* Change the TIM state*/
mbed_official 340:28d1f895c6fe 333 htim->State= HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 334
mbed_official 340:28d1f895c6fe 335 /* Return function status */
mbed_official 340:28d1f895c6fe 336 return HAL_OK;
mbed_official 340:28d1f895c6fe 337 }
mbed_official 340:28d1f895c6fe 338
mbed_official 340:28d1f895c6fe 339 /**
mbed_official 340:28d1f895c6fe 340 * @brief Starts the TIM Base generation in interrupt mode.
mbed_official 340:28d1f895c6fe 341 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 342 * @retval HAL status
mbed_official 340:28d1f895c6fe 343 */
mbed_official 340:28d1f895c6fe 344 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 345 {
mbed_official 340:28d1f895c6fe 346 /* Check the parameters */
mbed_official 340:28d1f895c6fe 347 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 348
mbed_official 340:28d1f895c6fe 349 /* Enable the TIM Update interrupt */
mbed_official 340:28d1f895c6fe 350 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
mbed_official 630:825f75ca301e 351
mbed_official 340:28d1f895c6fe 352 /* Enable the Peripheral */
mbed_official 340:28d1f895c6fe 353 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 354
mbed_official 340:28d1f895c6fe 355 /* Return function status */
mbed_official 340:28d1f895c6fe 356 return HAL_OK;
mbed_official 340:28d1f895c6fe 357 }
mbed_official 340:28d1f895c6fe 358
mbed_official 340:28d1f895c6fe 359 /**
mbed_official 340:28d1f895c6fe 360 * @brief Stops the TIM Base generation in interrupt mode.
mbed_official 340:28d1f895c6fe 361 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 362 * @retval HAL status
mbed_official 340:28d1f895c6fe 363 */
mbed_official 340:28d1f895c6fe 364 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 365 {
mbed_official 340:28d1f895c6fe 366 /* Check the parameters */
mbed_official 340:28d1f895c6fe 367 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 368 /* Disable the TIM Update interrupt */
mbed_official 340:28d1f895c6fe 369 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
mbed_official 630:825f75ca301e 370
mbed_official 340:28d1f895c6fe 371 /* Disable the Peripheral */
mbed_official 340:28d1f895c6fe 372 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 373
mbed_official 340:28d1f895c6fe 374 /* Return function status */
mbed_official 340:28d1f895c6fe 375 return HAL_OK;
mbed_official 340:28d1f895c6fe 376 }
mbed_official 340:28d1f895c6fe 377
mbed_official 340:28d1f895c6fe 378 /**
mbed_official 340:28d1f895c6fe 379 * @brief Starts the TIM Base generation in DMA mode.
mbed_official 340:28d1f895c6fe 380 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 381 * @param pData : The source Buffer address.
mbed_official 340:28d1f895c6fe 382 * @param Length : The length of data to be transferred from memory to peripheral.
mbed_official 340:28d1f895c6fe 383 * @retval HAL status
mbed_official 340:28d1f895c6fe 384 */
mbed_official 340:28d1f895c6fe 385 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
mbed_official 630:825f75ca301e 386 {
mbed_official 340:28d1f895c6fe 387 /* Check the parameters */
mbed_official 630:825f75ca301e 388 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 389
mbed_official 340:28d1f895c6fe 390 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 340:28d1f895c6fe 391 {
mbed_official 340:28d1f895c6fe 392 return HAL_BUSY;
mbed_official 340:28d1f895c6fe 393 }
mbed_official 340:28d1f895c6fe 394 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 340:28d1f895c6fe 395 {
mbed_official 630:825f75ca301e 396 if((pData == 0 ) && (Length > 0))
mbed_official 340:28d1f895c6fe 397 {
mbed_official 630:825f75ca301e 398 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 399 }
mbed_official 340:28d1f895c6fe 400 else
mbed_official 340:28d1f895c6fe 401 {
mbed_official 340:28d1f895c6fe 402 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 403 }
mbed_official 630:825f75ca301e 404 }
mbed_official 340:28d1f895c6fe 405 /* Set the DMA Period elapsed callback */
mbed_official 340:28d1f895c6fe 406 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 630:825f75ca301e 407
mbed_official 340:28d1f895c6fe 408 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 409 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 410
mbed_official 340:28d1f895c6fe 411 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 412 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
mbed_official 630:825f75ca301e 413
mbed_official 340:28d1f895c6fe 414 /* Enable the TIM Update DMA request */
mbed_official 340:28d1f895c6fe 415 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official 340:28d1f895c6fe 416
mbed_official 340:28d1f895c6fe 417 /* Enable the Peripheral */
mbed_official 630:825f75ca301e 418 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 419
mbed_official 340:28d1f895c6fe 420 /* Return function status */
mbed_official 340:28d1f895c6fe 421 return HAL_OK;
mbed_official 340:28d1f895c6fe 422 }
mbed_official 340:28d1f895c6fe 423
mbed_official 340:28d1f895c6fe 424 /**
mbed_official 340:28d1f895c6fe 425 * @brief Stops the TIM Base generation in DMA mode.
mbed_official 340:28d1f895c6fe 426 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 427 * @retval HAL status
mbed_official 340:28d1f895c6fe 428 */
mbed_official 340:28d1f895c6fe 429 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 430 {
mbed_official 340:28d1f895c6fe 431 /* Check the parameters */
mbed_official 340:28d1f895c6fe 432 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 433
mbed_official 340:28d1f895c6fe 434 /* Disable the TIM Update DMA request */
mbed_official 340:28d1f895c6fe 435 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official 630:825f75ca301e 436
mbed_official 340:28d1f895c6fe 437 /* Disable the Peripheral */
mbed_official 340:28d1f895c6fe 438 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 439
mbed_official 340:28d1f895c6fe 440 /* Change the htim state */
mbed_official 340:28d1f895c6fe 441 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 442
mbed_official 340:28d1f895c6fe 443 /* Return function status */
mbed_official 340:28d1f895c6fe 444 return HAL_OK;
mbed_official 340:28d1f895c6fe 445 }
mbed_official 340:28d1f895c6fe 446
mbed_official 340:28d1f895c6fe 447 /**
mbed_official 340:28d1f895c6fe 448 * @}
mbed_official 340:28d1f895c6fe 449 */
mbed_official 630:825f75ca301e 450
mbed_official 340:28d1f895c6fe 451 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
mbed_official 340:28d1f895c6fe 452 * @brief Time Output Compare functions
mbed_official 340:28d1f895c6fe 453 *
mbed_official 630:825f75ca301e 454 @verbatim
mbed_official 340:28d1f895c6fe 455 ==============================================================================
mbed_official 340:28d1f895c6fe 456 ##### Time Output Compare functions #####
mbed_official 340:28d1f895c6fe 457 ==============================================================================
mbed_official 340:28d1f895c6fe 458 [..]
mbed_official 340:28d1f895c6fe 459 This section provides functions allowing to:
mbed_official 630:825f75ca301e 460 (+) Initialize and configure the TIM Output Compare.
mbed_official 340:28d1f895c6fe 461 (+) De-initialize the TIM Output Compare.
mbed_official 340:28d1f895c6fe 462 (+) Start the Time Output Compare.
mbed_official 340:28d1f895c6fe 463 (+) Stop the Time Output Compare.
mbed_official 340:28d1f895c6fe 464 (+) Start the Time Output Compare and enable interrupt.
mbed_official 340:28d1f895c6fe 465 (+) Stop the Time Output Compare and disable interrupt.
mbed_official 340:28d1f895c6fe 466 (+) Start the Time Output Compare and enable DMA transfer.
mbed_official 340:28d1f895c6fe 467 (+) Stop the Time Output Compare and disable DMA transfer.
mbed_official 630:825f75ca301e 468
mbed_official 340:28d1f895c6fe 469 @endverbatim
mbed_official 340:28d1f895c6fe 470 * @{
mbed_official 340:28d1f895c6fe 471 */
mbed_official 340:28d1f895c6fe 472 /**
mbed_official 340:28d1f895c6fe 473 * @brief Initializes the TIM Output Compare according to the specified
mbed_official 340:28d1f895c6fe 474 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 340:28d1f895c6fe 475 * @param htim : TIM Output Compare handle
mbed_official 340:28d1f895c6fe 476 * @retval HAL status
mbed_official 340:28d1f895c6fe 477 */
mbed_official 340:28d1f895c6fe 478 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
mbed_official 340:28d1f895c6fe 479 {
mbed_official 340:28d1f895c6fe 480 /* Check the TIM handle allocation */
mbed_official 441:d2c15dda23c1 481 if(htim == NULL)
mbed_official 340:28d1f895c6fe 482 {
mbed_official 340:28d1f895c6fe 483 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 484 }
mbed_official 340:28d1f895c6fe 485
mbed_official 340:28d1f895c6fe 486 /* Check the parameters */
mbed_official 340:28d1f895c6fe 487 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 488 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 340:28d1f895c6fe 489 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 630:825f75ca301e 490
mbed_official 340:28d1f895c6fe 491 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 630:825f75ca301e 492 {
mbed_official 630:825f75ca301e 493 /* Allocate lock resource and initialize it */
mbed_official 630:825f75ca301e 494 htim->Lock = HAL_UNLOCKED;
mbed_official 630:825f75ca301e 495
mbed_official 340:28d1f895c6fe 496 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 340:28d1f895c6fe 497 HAL_TIM_OC_MspInit(htim);
mbed_official 340:28d1f895c6fe 498 }
mbed_official 630:825f75ca301e 499
mbed_official 340:28d1f895c6fe 500 /* Set the TIM state */
mbed_official 340:28d1f895c6fe 501 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 502
mbed_official 630:825f75ca301e 503 /* Init the base time for the Output Compare */
mbed_official 630:825f75ca301e 504 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 630:825f75ca301e 505
mbed_official 340:28d1f895c6fe 506 /* Initialize the TIM state*/
mbed_official 340:28d1f895c6fe 507 htim->State= HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 508
mbed_official 340:28d1f895c6fe 509 return HAL_OK;
mbed_official 340:28d1f895c6fe 510 }
mbed_official 340:28d1f895c6fe 511
mbed_official 340:28d1f895c6fe 512 /**
mbed_official 340:28d1f895c6fe 513 * @brief DeInitializes the TIM peripheral
mbed_official 340:28d1f895c6fe 514 * @param htim : TIM Output Compare handle
mbed_official 340:28d1f895c6fe 515 * @retval HAL status
mbed_official 340:28d1f895c6fe 516 */
mbed_official 340:28d1f895c6fe 517 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 518 {
mbed_official 340:28d1f895c6fe 519 /* Check the parameters */
mbed_official 340:28d1f895c6fe 520 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 521
mbed_official 340:28d1f895c6fe 522 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 523
mbed_official 340:28d1f895c6fe 524 /* Disable the TIM Peripheral Clock */
mbed_official 340:28d1f895c6fe 525 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 526
mbed_official 340:28d1f895c6fe 527 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 340:28d1f895c6fe 528 HAL_TIM_OC_MspDeInit(htim);
mbed_official 630:825f75ca301e 529
mbed_official 630:825f75ca301e 530 /* Change TIM state */
mbed_official 630:825f75ca301e 531 htim->State = HAL_TIM_STATE_RESET;
mbed_official 630:825f75ca301e 532
mbed_official 340:28d1f895c6fe 533 /* Release Lock */
mbed_official 340:28d1f895c6fe 534 __HAL_UNLOCK(htim);
mbed_official 340:28d1f895c6fe 535
mbed_official 340:28d1f895c6fe 536 return HAL_OK;
mbed_official 340:28d1f895c6fe 537 }
mbed_official 340:28d1f895c6fe 538
mbed_official 340:28d1f895c6fe 539 /**
mbed_official 340:28d1f895c6fe 540 * @brief Initializes the TIM Output Compare MSP.
mbed_official 340:28d1f895c6fe 541 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 542 * @retval None
mbed_official 340:28d1f895c6fe 543 */
mbed_official 340:28d1f895c6fe 544 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 545 {
mbed_official 340:28d1f895c6fe 546 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 547 the HAL_TIM_OC_MspInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 548 */
mbed_official 340:28d1f895c6fe 549 }
mbed_official 340:28d1f895c6fe 550
mbed_official 340:28d1f895c6fe 551 /**
mbed_official 340:28d1f895c6fe 552 * @brief DeInitializes TIM Output Compare MSP.
mbed_official 340:28d1f895c6fe 553 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 554 * @retval None
mbed_official 340:28d1f895c6fe 555 */
mbed_official 340:28d1f895c6fe 556 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 557 {
mbed_official 340:28d1f895c6fe 558 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 559 the HAL_TIM_OC_MspDeInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 560 */
mbed_official 340:28d1f895c6fe 561 }
mbed_official 340:28d1f895c6fe 562
mbed_official 340:28d1f895c6fe 563 /**
mbed_official 340:28d1f895c6fe 564 * @brief Starts the TIM Output Compare signal generation.
mbed_official 630:825f75ca301e 565 * @param htim : TIM Output Compare handle
mbed_official 340:28d1f895c6fe 566 * @param Channel : TIM Channel to be enabled
mbed_official 340:28d1f895c6fe 567 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 568 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 569 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 570 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 630:825f75ca301e 571 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 572 * @retval HAL status
mbed_official 340:28d1f895c6fe 573 */
mbed_official 340:28d1f895c6fe 574 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 575 {
mbed_official 340:28d1f895c6fe 576 /* Check the parameters */
mbed_official 340:28d1f895c6fe 577 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 578
mbed_official 340:28d1f895c6fe 579 /* Enable the Output compare channel */
mbed_official 340:28d1f895c6fe 580 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 581
mbed_official 630:825f75ca301e 582 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 583 {
mbed_official 340:28d1f895c6fe 584 /* Enable the main output */
mbed_official 340:28d1f895c6fe 585 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 340:28d1f895c6fe 586 }
mbed_official 630:825f75ca301e 587
mbed_official 340:28d1f895c6fe 588 /* Enable the Peripheral */
mbed_official 630:825f75ca301e 589 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 590
mbed_official 340:28d1f895c6fe 591 /* Return function status */
mbed_official 340:28d1f895c6fe 592 return HAL_OK;
mbed_official 340:28d1f895c6fe 593 }
mbed_official 340:28d1f895c6fe 594
mbed_official 340:28d1f895c6fe 595 /**
mbed_official 340:28d1f895c6fe 596 * @brief Stops the TIM Output Compare signal generation.
mbed_official 340:28d1f895c6fe 597 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 598 * @param Channel : TIM Channel to be disabled
mbed_official 340:28d1f895c6fe 599 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 600 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 601 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 602 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 603 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 604 * @retval HAL status
mbed_official 340:28d1f895c6fe 605 */
mbed_official 340:28d1f895c6fe 606 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 607 {
mbed_official 340:28d1f895c6fe 608 /* Check the parameters */
mbed_official 340:28d1f895c6fe 609 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 610
mbed_official 340:28d1f895c6fe 611 /* Disable the Output compare channel */
mbed_official 340:28d1f895c6fe 612 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 613
mbed_official 630:825f75ca301e 614 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 615 {
mbed_official 340:28d1f895c6fe 616 /* Disable the Main Ouput */
mbed_official 340:28d1f895c6fe 617 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 630:825f75ca301e 618 }
mbed_official 630:825f75ca301e 619
mbed_official 340:28d1f895c6fe 620 /* Disable the Peripheral */
mbed_official 630:825f75ca301e 621 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 622
mbed_official 340:28d1f895c6fe 623 /* Return function status */
mbed_official 340:28d1f895c6fe 624 return HAL_OK;
mbed_official 630:825f75ca301e 625 }
mbed_official 340:28d1f895c6fe 626
mbed_official 340:28d1f895c6fe 627 /**
mbed_official 340:28d1f895c6fe 628 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
mbed_official 340:28d1f895c6fe 629 * @param htim : TIM OC handle
mbed_official 340:28d1f895c6fe 630 * @param Channel : TIM Channel to be enabled
mbed_official 340:28d1f895c6fe 631 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 632 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 633 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 634 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 635 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 636 * @retval HAL status
mbed_official 340:28d1f895c6fe 637 */
mbed_official 340:28d1f895c6fe 638 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 639 {
mbed_official 340:28d1f895c6fe 640 /* Check the parameters */
mbed_official 340:28d1f895c6fe 641 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 642
mbed_official 340:28d1f895c6fe 643 switch (Channel)
mbed_official 340:28d1f895c6fe 644 {
mbed_official 340:28d1f895c6fe 645 case TIM_CHANNEL_1:
mbed_official 630:825f75ca301e 646 {
mbed_official 340:28d1f895c6fe 647 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 340:28d1f895c6fe 648 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 340:28d1f895c6fe 649 }
mbed_official 340:28d1f895c6fe 650 break;
mbed_official 630:825f75ca301e 651
mbed_official 340:28d1f895c6fe 652 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 653 {
mbed_official 340:28d1f895c6fe 654 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 340:28d1f895c6fe 655 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 340:28d1f895c6fe 656 }
mbed_official 340:28d1f895c6fe 657 break;
mbed_official 630:825f75ca301e 658
mbed_official 340:28d1f895c6fe 659 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 660 {
mbed_official 340:28d1f895c6fe 661 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 340:28d1f895c6fe 662 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 340:28d1f895c6fe 663 }
mbed_official 340:28d1f895c6fe 664 break;
mbed_official 630:825f75ca301e 665
mbed_official 340:28d1f895c6fe 666 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 667 {
mbed_official 340:28d1f895c6fe 668 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 340:28d1f895c6fe 669 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 340:28d1f895c6fe 670 }
mbed_official 340:28d1f895c6fe 671 break;
mbed_official 630:825f75ca301e 672
mbed_official 340:28d1f895c6fe 673 default:
mbed_official 340:28d1f895c6fe 674 break;
mbed_official 630:825f75ca301e 675 }
mbed_official 340:28d1f895c6fe 676
mbed_official 340:28d1f895c6fe 677 /* Enable the Output compare channel */
mbed_official 340:28d1f895c6fe 678 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 679
mbed_official 630:825f75ca301e 680 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 681 {
mbed_official 340:28d1f895c6fe 682 /* Enable the main output */
mbed_official 340:28d1f895c6fe 683 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 340:28d1f895c6fe 684 }
mbed_official 340:28d1f895c6fe 685
mbed_official 340:28d1f895c6fe 686 /* Enable the Peripheral */
mbed_official 340:28d1f895c6fe 687 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 688
mbed_official 340:28d1f895c6fe 689 /* Return function status */
mbed_official 340:28d1f895c6fe 690 return HAL_OK;
mbed_official 340:28d1f895c6fe 691 }
mbed_official 340:28d1f895c6fe 692
mbed_official 340:28d1f895c6fe 693 /**
mbed_official 340:28d1f895c6fe 694 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
mbed_official 340:28d1f895c6fe 695 * @param htim : TIM Output Compare handle
mbed_official 340:28d1f895c6fe 696 * @param Channel : TIM Channel to be disabled
mbed_official 340:28d1f895c6fe 697 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 698 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 699 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 700 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 701 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 702 * @retval HAL status
mbed_official 340:28d1f895c6fe 703 */
mbed_official 340:28d1f895c6fe 704 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 705 {
mbed_official 340:28d1f895c6fe 706 /* Check the parameters */
mbed_official 340:28d1f895c6fe 707 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 708
mbed_official 340:28d1f895c6fe 709 switch (Channel)
mbed_official 340:28d1f895c6fe 710 {
mbed_official 340:28d1f895c6fe 711 case TIM_CHANNEL_1:
mbed_official 630:825f75ca301e 712 {
mbed_official 340:28d1f895c6fe 713 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 340:28d1f895c6fe 714 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 340:28d1f895c6fe 715 }
mbed_official 340:28d1f895c6fe 716 break;
mbed_official 630:825f75ca301e 717
mbed_official 340:28d1f895c6fe 718 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 719 {
mbed_official 340:28d1f895c6fe 720 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 340:28d1f895c6fe 721 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 340:28d1f895c6fe 722 }
mbed_official 340:28d1f895c6fe 723 break;
mbed_official 630:825f75ca301e 724
mbed_official 340:28d1f895c6fe 725 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 726 {
mbed_official 340:28d1f895c6fe 727 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 340:28d1f895c6fe 728 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 340:28d1f895c6fe 729 }
mbed_official 340:28d1f895c6fe 730 break;
mbed_official 630:825f75ca301e 731
mbed_official 340:28d1f895c6fe 732 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 733 {
mbed_official 340:28d1f895c6fe 734 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 340:28d1f895c6fe 735 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 340:28d1f895c6fe 736 }
mbed_official 340:28d1f895c6fe 737 break;
mbed_official 630:825f75ca301e 738
mbed_official 340:28d1f895c6fe 739 default:
mbed_official 630:825f75ca301e 740 break;
mbed_official 630:825f75ca301e 741 }
mbed_official 630:825f75ca301e 742
mbed_official 340:28d1f895c6fe 743 /* Disable the Output compare channel */
mbed_official 630:825f75ca301e 744 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 745
mbed_official 630:825f75ca301e 746 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 747 {
mbed_official 340:28d1f895c6fe 748 /* Disable the Main Ouput */
mbed_official 340:28d1f895c6fe 749 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 340:28d1f895c6fe 750 }
mbed_official 630:825f75ca301e 751
mbed_official 340:28d1f895c6fe 752 /* Disable the Peripheral */
mbed_official 630:825f75ca301e 753 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 754
mbed_official 340:28d1f895c6fe 755 /* Return function status */
mbed_official 340:28d1f895c6fe 756 return HAL_OK;
mbed_official 340:28d1f895c6fe 757 }
mbed_official 340:28d1f895c6fe 758
mbed_official 340:28d1f895c6fe 759 /**
mbed_official 340:28d1f895c6fe 760 * @brief Starts the TIM Output Compare signal generation in DMA mode.
mbed_official 340:28d1f895c6fe 761 * @param htim : TIM Output Compare handle
mbed_official 340:28d1f895c6fe 762 * @param Channel : TIM Channel to be enabled
mbed_official 340:28d1f895c6fe 763 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 764 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 765 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 766 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 767 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 768 * @param pData : The source Buffer address.
mbed_official 340:28d1f895c6fe 769 * @param Length : The length of data to be transferred from memory to TIM peripheral
mbed_official 340:28d1f895c6fe 770 * @retval HAL status
mbed_official 340:28d1f895c6fe 771 */
mbed_official 340:28d1f895c6fe 772 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 340:28d1f895c6fe 773 {
mbed_official 340:28d1f895c6fe 774 /* Check the parameters */
mbed_official 340:28d1f895c6fe 775 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 776
mbed_official 340:28d1f895c6fe 777 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 340:28d1f895c6fe 778 {
mbed_official 340:28d1f895c6fe 779 return HAL_BUSY;
mbed_official 340:28d1f895c6fe 780 }
mbed_official 340:28d1f895c6fe 781 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 340:28d1f895c6fe 782 {
mbed_official 630:825f75ca301e 783 if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official 340:28d1f895c6fe 784 {
mbed_official 630:825f75ca301e 785 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 786 }
mbed_official 340:28d1f895c6fe 787 else
mbed_official 340:28d1f895c6fe 788 {
mbed_official 340:28d1f895c6fe 789 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 790 }
mbed_official 630:825f75ca301e 791 }
mbed_official 340:28d1f895c6fe 792 switch (Channel)
mbed_official 340:28d1f895c6fe 793 {
mbed_official 340:28d1f895c6fe 794 case TIM_CHANNEL_1:
mbed_official 340:28d1f895c6fe 795 {
mbed_official 340:28d1f895c6fe 796 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 797 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 630:825f75ca301e 798
mbed_official 340:28d1f895c6fe 799 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 800 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 801
mbed_official 340:28d1f895c6fe 802 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 803 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official 630:825f75ca301e 804
mbed_official 340:28d1f895c6fe 805 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 340:28d1f895c6fe 806 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 340:28d1f895c6fe 807 }
mbed_official 340:28d1f895c6fe 808 break;
mbed_official 630:825f75ca301e 809
mbed_official 340:28d1f895c6fe 810 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 811 {
mbed_official 340:28d1f895c6fe 812 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 813 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 630:825f75ca301e 814
mbed_official 340:28d1f895c6fe 815 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 816 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 817
mbed_official 340:28d1f895c6fe 818 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 819 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official 630:825f75ca301e 820
mbed_official 340:28d1f895c6fe 821 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 340:28d1f895c6fe 822 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 340:28d1f895c6fe 823 }
mbed_official 340:28d1f895c6fe 824 break;
mbed_official 630:825f75ca301e 825
mbed_official 340:28d1f895c6fe 826 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 827 {
mbed_official 340:28d1f895c6fe 828 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 829 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 630:825f75ca301e 830
mbed_official 340:28d1f895c6fe 831 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 832 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 833
mbed_official 340:28d1f895c6fe 834 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 835 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official 630:825f75ca301e 836
mbed_official 340:28d1f895c6fe 837 /* Enable the TIM Capture/Compare 3 DMA request */
mbed_official 340:28d1f895c6fe 838 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 340:28d1f895c6fe 839 }
mbed_official 340:28d1f895c6fe 840 break;
mbed_official 630:825f75ca301e 841
mbed_official 340:28d1f895c6fe 842 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 843 {
mbed_official 340:28d1f895c6fe 844 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 845 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 630:825f75ca301e 846
mbed_official 340:28d1f895c6fe 847 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 848 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 849
mbed_official 340:28d1f895c6fe 850 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 851 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official 630:825f75ca301e 852
mbed_official 340:28d1f895c6fe 853 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 340:28d1f895c6fe 854 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 340:28d1f895c6fe 855 }
mbed_official 340:28d1f895c6fe 856 break;
mbed_official 630:825f75ca301e 857
mbed_official 340:28d1f895c6fe 858 default:
mbed_official 340:28d1f895c6fe 859 break;
mbed_official 340:28d1f895c6fe 860 }
mbed_official 340:28d1f895c6fe 861
mbed_official 340:28d1f895c6fe 862 /* Enable the Output compare channel */
mbed_official 340:28d1f895c6fe 863 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 864
mbed_official 630:825f75ca301e 865 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 866 {
mbed_official 340:28d1f895c6fe 867 /* Enable the main output */
mbed_official 340:28d1f895c6fe 868 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 630:825f75ca301e 869 }
mbed_official 630:825f75ca301e 870
mbed_official 340:28d1f895c6fe 871 /* Enable the Peripheral */
mbed_official 630:825f75ca301e 872 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 873
mbed_official 340:28d1f895c6fe 874 /* Return function status */
mbed_official 340:28d1f895c6fe 875 return HAL_OK;
mbed_official 340:28d1f895c6fe 876 }
mbed_official 340:28d1f895c6fe 877
mbed_official 340:28d1f895c6fe 878 /**
mbed_official 340:28d1f895c6fe 879 * @brief Stops the TIM Output Compare signal generation in DMA mode.
mbed_official 340:28d1f895c6fe 880 * @param htim : TIM Output Compare handle
mbed_official 340:28d1f895c6fe 881 * @param Channel : TIM Channel to be disabled
mbed_official 340:28d1f895c6fe 882 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 883 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 884 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 885 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 886 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 887 * @retval HAL status
mbed_official 340:28d1f895c6fe 888 */
mbed_official 340:28d1f895c6fe 889 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 890 {
mbed_official 340:28d1f895c6fe 891 /* Check the parameters */
mbed_official 340:28d1f895c6fe 892 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 893
mbed_official 340:28d1f895c6fe 894 switch (Channel)
mbed_official 340:28d1f895c6fe 895 {
mbed_official 340:28d1f895c6fe 896 case TIM_CHANNEL_1:
mbed_official 630:825f75ca301e 897 {
mbed_official 340:28d1f895c6fe 898 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 340:28d1f895c6fe 899 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 340:28d1f895c6fe 900 }
mbed_official 340:28d1f895c6fe 901 break;
mbed_official 630:825f75ca301e 902
mbed_official 340:28d1f895c6fe 903 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 904 {
mbed_official 340:28d1f895c6fe 905 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 340:28d1f895c6fe 906 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 340:28d1f895c6fe 907 }
mbed_official 340:28d1f895c6fe 908 break;
mbed_official 630:825f75ca301e 909
mbed_official 340:28d1f895c6fe 910 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 911 {
mbed_official 340:28d1f895c6fe 912 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 340:28d1f895c6fe 913 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 340:28d1f895c6fe 914 }
mbed_official 340:28d1f895c6fe 915 break;
mbed_official 630:825f75ca301e 916
mbed_official 340:28d1f895c6fe 917 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 918 {
mbed_official 340:28d1f895c6fe 919 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 340:28d1f895c6fe 920 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 340:28d1f895c6fe 921 }
mbed_official 340:28d1f895c6fe 922 break;
mbed_official 630:825f75ca301e 923
mbed_official 340:28d1f895c6fe 924 default:
mbed_official 340:28d1f895c6fe 925 break;
mbed_official 630:825f75ca301e 926 }
mbed_official 630:825f75ca301e 927
mbed_official 340:28d1f895c6fe 928 /* Disable the Output compare channel */
mbed_official 340:28d1f895c6fe 929 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 930
mbed_official 630:825f75ca301e 931 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 932 {
mbed_official 340:28d1f895c6fe 933 /* Disable the Main Ouput */
mbed_official 340:28d1f895c6fe 934 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 340:28d1f895c6fe 935 }
mbed_official 630:825f75ca301e 936
mbed_official 340:28d1f895c6fe 937 /* Disable the Peripheral */
mbed_official 340:28d1f895c6fe 938 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 939
mbed_official 340:28d1f895c6fe 940 /* Change the htim state */
mbed_official 340:28d1f895c6fe 941 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 942
mbed_official 340:28d1f895c6fe 943 /* Return function status */
mbed_official 340:28d1f895c6fe 944 return HAL_OK;
mbed_official 340:28d1f895c6fe 945 }
mbed_official 340:28d1f895c6fe 946
mbed_official 340:28d1f895c6fe 947 /**
mbed_official 340:28d1f895c6fe 948 * @}
mbed_official 340:28d1f895c6fe 949 */
mbed_official 340:28d1f895c6fe 950
mbed_official 340:28d1f895c6fe 951 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
mbed_official 340:28d1f895c6fe 952 * @brief Time PWM functions
mbed_official 340:28d1f895c6fe 953 *
mbed_official 630:825f75ca301e 954 @verbatim
mbed_official 340:28d1f895c6fe 955 ==============================================================================
mbed_official 340:28d1f895c6fe 956 ##### Time PWM functions #####
mbed_official 340:28d1f895c6fe 957 ==============================================================================
mbed_official 630:825f75ca301e 958 [..]
mbed_official 340:28d1f895c6fe 959 This section provides functions allowing to:
mbed_official 630:825f75ca301e 960 (+) Initialize and configure the TIM OPWM.
mbed_official 340:28d1f895c6fe 961 (+) De-initialize the TIM PWM.
mbed_official 340:28d1f895c6fe 962 (+) Start the Time PWM.
mbed_official 340:28d1f895c6fe 963 (+) Stop the Time PWM.
mbed_official 340:28d1f895c6fe 964 (+) Start the Time PWM and enable interrupt.
mbed_official 340:28d1f895c6fe 965 (+) Stop the Time PWM and disable interrupt.
mbed_official 340:28d1f895c6fe 966 (+) Start the Time PWM and enable DMA transfer.
mbed_official 340:28d1f895c6fe 967 (+) Stop the Time PWM and disable DMA transfer.
mbed_official 630:825f75ca301e 968
mbed_official 340:28d1f895c6fe 969 @endverbatim
mbed_official 340:28d1f895c6fe 970 * @{
mbed_official 340:28d1f895c6fe 971 */
mbed_official 340:28d1f895c6fe 972 /**
mbed_official 340:28d1f895c6fe 973 * @brief Initializes the TIM PWM Time Base according to the specified
mbed_official 340:28d1f895c6fe 974 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 340:28d1f895c6fe 975 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 976 * @retval HAL status
mbed_official 340:28d1f895c6fe 977 */
mbed_official 340:28d1f895c6fe 978 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 979 {
mbed_official 340:28d1f895c6fe 980 /* Check the TIM handle allocation */
mbed_official 441:d2c15dda23c1 981 if(htim == NULL)
mbed_official 340:28d1f895c6fe 982 {
mbed_official 340:28d1f895c6fe 983 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 984 }
mbed_official 340:28d1f895c6fe 985
mbed_official 340:28d1f895c6fe 986 /* Check the parameters */
mbed_official 340:28d1f895c6fe 987 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 988 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 340:28d1f895c6fe 989 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 340:28d1f895c6fe 990
mbed_official 340:28d1f895c6fe 991 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 340:28d1f895c6fe 992 {
mbed_official 630:825f75ca301e 993 /* Allocate lock resource and initialize it */
mbed_official 630:825f75ca301e 994 htim->Lock = HAL_UNLOCKED;
mbed_official 630:825f75ca301e 995
mbed_official 340:28d1f895c6fe 996 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 340:28d1f895c6fe 997 HAL_TIM_PWM_MspInit(htim);
mbed_official 340:28d1f895c6fe 998 }
mbed_official 340:28d1f895c6fe 999
mbed_official 340:28d1f895c6fe 1000 /* Set the TIM state */
mbed_official 340:28d1f895c6fe 1001 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 1002
mbed_official 630:825f75ca301e 1003 /* Init the base time for the PWM */
mbed_official 630:825f75ca301e 1004 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 630:825f75ca301e 1005
mbed_official 340:28d1f895c6fe 1006 /* Initialize the TIM state*/
mbed_official 340:28d1f895c6fe 1007 htim->State= HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 1008
mbed_official 340:28d1f895c6fe 1009 return HAL_OK;
mbed_official 340:28d1f895c6fe 1010 }
mbed_official 340:28d1f895c6fe 1011
mbed_official 340:28d1f895c6fe 1012 /**
mbed_official 340:28d1f895c6fe 1013 * @brief DeInitializes the TIM peripheral
mbed_official 340:28d1f895c6fe 1014 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 1015 * @retval HAL status
mbed_official 340:28d1f895c6fe 1016 */
mbed_official 340:28d1f895c6fe 1017 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 1018 {
mbed_official 340:28d1f895c6fe 1019 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1020 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 1021
mbed_official 340:28d1f895c6fe 1022 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 1023
mbed_official 340:28d1f895c6fe 1024 /* Disable the TIM Peripheral Clock */
mbed_official 340:28d1f895c6fe 1025 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 1026
mbed_official 340:28d1f895c6fe 1027 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 340:28d1f895c6fe 1028 HAL_TIM_PWM_MspDeInit(htim);
mbed_official 630:825f75ca301e 1029
mbed_official 630:825f75ca301e 1030 /* Change TIM state */
mbed_official 630:825f75ca301e 1031 htim->State = HAL_TIM_STATE_RESET;
mbed_official 630:825f75ca301e 1032
mbed_official 340:28d1f895c6fe 1033 /* Release Lock */
mbed_official 340:28d1f895c6fe 1034 __HAL_UNLOCK(htim);
mbed_official 340:28d1f895c6fe 1035
mbed_official 340:28d1f895c6fe 1036 return HAL_OK;
mbed_official 340:28d1f895c6fe 1037 }
mbed_official 340:28d1f895c6fe 1038
mbed_official 340:28d1f895c6fe 1039 /**
mbed_official 340:28d1f895c6fe 1040 * @brief Initializes the TIM PWM MSP.
mbed_official 340:28d1f895c6fe 1041 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 1042 * @retval None
mbed_official 340:28d1f895c6fe 1043 */
mbed_official 340:28d1f895c6fe 1044 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 1045 {
mbed_official 340:28d1f895c6fe 1046 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 1047 the HAL_TIM_PWM_MspInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 1048 */
mbed_official 340:28d1f895c6fe 1049 }
mbed_official 340:28d1f895c6fe 1050
mbed_official 340:28d1f895c6fe 1051 /**
mbed_official 340:28d1f895c6fe 1052 * @brief DeInitializes TIM PWM MSP.
mbed_official 340:28d1f895c6fe 1053 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 1054 * @retval None
mbed_official 340:28d1f895c6fe 1055 */
mbed_official 340:28d1f895c6fe 1056 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 1057 {
mbed_official 340:28d1f895c6fe 1058 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 1059 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 1060 */
mbed_official 340:28d1f895c6fe 1061 }
mbed_official 340:28d1f895c6fe 1062
mbed_official 340:28d1f895c6fe 1063 /**
mbed_official 340:28d1f895c6fe 1064 * @brief Starts the PWM signal generation.
mbed_official 340:28d1f895c6fe 1065 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 1066 * @param Channel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 1067 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 1068 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 1069 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 1070 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 1071 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 1072 * @retval HAL status
mbed_official 340:28d1f895c6fe 1073 */
mbed_official 340:28d1f895c6fe 1074 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 1075 {
mbed_official 340:28d1f895c6fe 1076 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1077 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 1078
mbed_official 340:28d1f895c6fe 1079 /* Enable the Capture compare channel */
mbed_official 340:28d1f895c6fe 1080 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 1081
mbed_official 630:825f75ca301e 1082 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 1083 {
mbed_official 340:28d1f895c6fe 1084 /* Enable the main output */
mbed_official 340:28d1f895c6fe 1085 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 340:28d1f895c6fe 1086 }
mbed_official 630:825f75ca301e 1087
mbed_official 340:28d1f895c6fe 1088 /* Enable the Peripheral */
mbed_official 340:28d1f895c6fe 1089 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 1090
mbed_official 340:28d1f895c6fe 1091 /* Return function status */
mbed_official 340:28d1f895c6fe 1092 return HAL_OK;
mbed_official 630:825f75ca301e 1093 }
mbed_official 340:28d1f895c6fe 1094
mbed_official 340:28d1f895c6fe 1095 /**
mbed_official 340:28d1f895c6fe 1096 * @brief Stops the PWM signal generation.
mbed_official 340:28d1f895c6fe 1097 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 1098 * @param Channel : TIM Channels to be disabled
mbed_official 340:28d1f895c6fe 1099 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 1100 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 1101 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 1102 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 1103 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 1104 * @retval HAL status
mbed_official 340:28d1f895c6fe 1105 */
mbed_official 340:28d1f895c6fe 1106 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 630:825f75ca301e 1107 {
mbed_official 340:28d1f895c6fe 1108 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1109 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 1110
mbed_official 340:28d1f895c6fe 1111 /* Disable the Capture compare channel */
mbed_official 340:28d1f895c6fe 1112 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 1113
mbed_official 630:825f75ca301e 1114 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 1115 {
mbed_official 340:28d1f895c6fe 1116 /* Disable the Main Ouput */
mbed_official 340:28d1f895c6fe 1117 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 340:28d1f895c6fe 1118 }
mbed_official 630:825f75ca301e 1119
mbed_official 340:28d1f895c6fe 1120 /* Disable the Peripheral */
mbed_official 340:28d1f895c6fe 1121 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 1122
mbed_official 340:28d1f895c6fe 1123 /* Change the htim state */
mbed_official 340:28d1f895c6fe 1124 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 1125
mbed_official 340:28d1f895c6fe 1126 /* Return function status */
mbed_official 340:28d1f895c6fe 1127 return HAL_OK;
mbed_official 630:825f75ca301e 1128 }
mbed_official 340:28d1f895c6fe 1129
mbed_official 340:28d1f895c6fe 1130 /**
mbed_official 340:28d1f895c6fe 1131 * @brief Starts the PWM signal generation in interrupt mode.
mbed_official 340:28d1f895c6fe 1132 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 1133 * @param Channel : TIM Channel to be disabled
mbed_official 340:28d1f895c6fe 1134 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 1135 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 1136 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 1137 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 1138 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 1139 * @retval HAL status
mbed_official 340:28d1f895c6fe 1140 */
mbed_official 340:28d1f895c6fe 1141 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 1142 {
mbed_official 340:28d1f895c6fe 1143 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1144 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 1145
mbed_official 340:28d1f895c6fe 1146 switch (Channel)
mbed_official 340:28d1f895c6fe 1147 {
mbed_official 340:28d1f895c6fe 1148 case TIM_CHANNEL_1:
mbed_official 630:825f75ca301e 1149 {
mbed_official 340:28d1f895c6fe 1150 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 340:28d1f895c6fe 1151 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 340:28d1f895c6fe 1152 }
mbed_official 340:28d1f895c6fe 1153 break;
mbed_official 630:825f75ca301e 1154
mbed_official 340:28d1f895c6fe 1155 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 1156 {
mbed_official 340:28d1f895c6fe 1157 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 340:28d1f895c6fe 1158 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 340:28d1f895c6fe 1159 }
mbed_official 340:28d1f895c6fe 1160 break;
mbed_official 630:825f75ca301e 1161
mbed_official 340:28d1f895c6fe 1162 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 1163 {
mbed_official 340:28d1f895c6fe 1164 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 340:28d1f895c6fe 1165 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 340:28d1f895c6fe 1166 }
mbed_official 340:28d1f895c6fe 1167 break;
mbed_official 630:825f75ca301e 1168
mbed_official 340:28d1f895c6fe 1169 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 1170 {
mbed_official 340:28d1f895c6fe 1171 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 340:28d1f895c6fe 1172 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 340:28d1f895c6fe 1173 }
mbed_official 340:28d1f895c6fe 1174 break;
mbed_official 630:825f75ca301e 1175
mbed_official 340:28d1f895c6fe 1176 default:
mbed_official 340:28d1f895c6fe 1177 break;
mbed_official 630:825f75ca301e 1178 }
mbed_official 630:825f75ca301e 1179
mbed_official 340:28d1f895c6fe 1180 /* Enable the Capture compare channel */
mbed_official 340:28d1f895c6fe 1181 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 1182
mbed_official 630:825f75ca301e 1183 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 1184 {
mbed_official 340:28d1f895c6fe 1185 /* Enable the main output */
mbed_official 340:28d1f895c6fe 1186 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 340:28d1f895c6fe 1187 }
mbed_official 340:28d1f895c6fe 1188
mbed_official 340:28d1f895c6fe 1189 /* Enable the Peripheral */
mbed_official 340:28d1f895c6fe 1190 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 1191
mbed_official 340:28d1f895c6fe 1192 /* Return function status */
mbed_official 340:28d1f895c6fe 1193 return HAL_OK;
mbed_official 630:825f75ca301e 1194 }
mbed_official 340:28d1f895c6fe 1195
mbed_official 340:28d1f895c6fe 1196 /**
mbed_official 340:28d1f895c6fe 1197 * @brief Stops the PWM signal generation in interrupt mode.
mbed_official 340:28d1f895c6fe 1198 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 1199 * @param Channel : TIM Channels to be disabled
mbed_official 340:28d1f895c6fe 1200 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 1201 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 1202 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 1203 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 1204 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 1205 * @retval HAL status
mbed_official 340:28d1f895c6fe 1206 */
mbed_official 340:28d1f895c6fe 1207 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 1208 {
mbed_official 340:28d1f895c6fe 1209 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1210 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 1211
mbed_official 340:28d1f895c6fe 1212 switch (Channel)
mbed_official 340:28d1f895c6fe 1213 {
mbed_official 340:28d1f895c6fe 1214 case TIM_CHANNEL_1:
mbed_official 630:825f75ca301e 1215 {
mbed_official 340:28d1f895c6fe 1216 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 340:28d1f895c6fe 1217 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 340:28d1f895c6fe 1218 }
mbed_official 340:28d1f895c6fe 1219 break;
mbed_official 630:825f75ca301e 1220
mbed_official 340:28d1f895c6fe 1221 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 1222 {
mbed_official 340:28d1f895c6fe 1223 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 340:28d1f895c6fe 1224 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 340:28d1f895c6fe 1225 }
mbed_official 340:28d1f895c6fe 1226 break;
mbed_official 630:825f75ca301e 1227
mbed_official 340:28d1f895c6fe 1228 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 1229 {
mbed_official 340:28d1f895c6fe 1230 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 340:28d1f895c6fe 1231 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 340:28d1f895c6fe 1232 }
mbed_official 340:28d1f895c6fe 1233 break;
mbed_official 630:825f75ca301e 1234
mbed_official 340:28d1f895c6fe 1235 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 1236 {
mbed_official 340:28d1f895c6fe 1237 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 340:28d1f895c6fe 1238 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 340:28d1f895c6fe 1239 }
mbed_official 340:28d1f895c6fe 1240 break;
mbed_official 630:825f75ca301e 1241
mbed_official 340:28d1f895c6fe 1242 default:
mbed_official 630:825f75ca301e 1243 break;
mbed_official 340:28d1f895c6fe 1244 }
mbed_official 630:825f75ca301e 1245
mbed_official 340:28d1f895c6fe 1246 /* Disable the Capture compare channel */
mbed_official 340:28d1f895c6fe 1247 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 1248
mbed_official 630:825f75ca301e 1249 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 1250 {
mbed_official 340:28d1f895c6fe 1251 /* Disable the Main Ouput */
mbed_official 340:28d1f895c6fe 1252 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 340:28d1f895c6fe 1253 }
mbed_official 630:825f75ca301e 1254
mbed_official 340:28d1f895c6fe 1255 /* Disable the Peripheral */
mbed_official 340:28d1f895c6fe 1256 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 1257
mbed_official 340:28d1f895c6fe 1258 /* Return function status */
mbed_official 340:28d1f895c6fe 1259 return HAL_OK;
mbed_official 630:825f75ca301e 1260 }
mbed_official 340:28d1f895c6fe 1261
mbed_official 340:28d1f895c6fe 1262 /**
mbed_official 340:28d1f895c6fe 1263 * @brief Starts the TIM PWM signal generation in DMA mode.
mbed_official 340:28d1f895c6fe 1264 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 1265 * @param Channel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 1266 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 1267 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 1268 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 1269 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 1270 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 1271 * @param pData : The source Buffer address.
mbed_official 340:28d1f895c6fe 1272 * @param Length : The length of data to be transferred from memory to TIM peripheral
mbed_official 340:28d1f895c6fe 1273 * @retval HAL status
mbed_official 340:28d1f895c6fe 1274 */
mbed_official 340:28d1f895c6fe 1275 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 340:28d1f895c6fe 1276 {
mbed_official 340:28d1f895c6fe 1277 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1278 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 1279
mbed_official 340:28d1f895c6fe 1280 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 340:28d1f895c6fe 1281 {
mbed_official 340:28d1f895c6fe 1282 return HAL_BUSY;
mbed_official 340:28d1f895c6fe 1283 }
mbed_official 340:28d1f895c6fe 1284 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 340:28d1f895c6fe 1285 {
mbed_official 630:825f75ca301e 1286 if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official 340:28d1f895c6fe 1287 {
mbed_official 630:825f75ca301e 1288 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 1289 }
mbed_official 340:28d1f895c6fe 1290 else
mbed_official 340:28d1f895c6fe 1291 {
mbed_official 340:28d1f895c6fe 1292 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 1293 }
mbed_official 630:825f75ca301e 1294 }
mbed_official 340:28d1f895c6fe 1295 switch (Channel)
mbed_official 340:28d1f895c6fe 1296 {
mbed_official 340:28d1f895c6fe 1297 case TIM_CHANNEL_1:
mbed_official 340:28d1f895c6fe 1298 {
mbed_official 340:28d1f895c6fe 1299 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 1300 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 630:825f75ca301e 1301
mbed_official 340:28d1f895c6fe 1302 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 1303 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 1304
mbed_official 340:28d1f895c6fe 1305 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 1306 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official 630:825f75ca301e 1307
mbed_official 340:28d1f895c6fe 1308 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 340:28d1f895c6fe 1309 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 340:28d1f895c6fe 1310 }
mbed_official 340:28d1f895c6fe 1311 break;
mbed_official 630:825f75ca301e 1312
mbed_official 340:28d1f895c6fe 1313 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 1314 {
mbed_official 340:28d1f895c6fe 1315 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 1316 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 630:825f75ca301e 1317
mbed_official 340:28d1f895c6fe 1318 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 1319 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 1320
mbed_official 340:28d1f895c6fe 1321 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 1322 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official 630:825f75ca301e 1323
mbed_official 340:28d1f895c6fe 1324 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 340:28d1f895c6fe 1325 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 340:28d1f895c6fe 1326 }
mbed_official 340:28d1f895c6fe 1327 break;
mbed_official 630:825f75ca301e 1328
mbed_official 340:28d1f895c6fe 1329 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 1330 {
mbed_official 340:28d1f895c6fe 1331 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 1332 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 630:825f75ca301e 1333
mbed_official 340:28d1f895c6fe 1334 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 1335 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 1336
mbed_official 340:28d1f895c6fe 1337 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 1338 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official 630:825f75ca301e 1339
mbed_official 340:28d1f895c6fe 1340 /* Enable the TIM Output Capture/Compare 3 request */
mbed_official 340:28d1f895c6fe 1341 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 340:28d1f895c6fe 1342 }
mbed_official 340:28d1f895c6fe 1343 break;
mbed_official 630:825f75ca301e 1344
mbed_official 340:28d1f895c6fe 1345 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 1346 {
mbed_official 340:28d1f895c6fe 1347 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 1348 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 630:825f75ca301e 1349
mbed_official 340:28d1f895c6fe 1350 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 1351 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 1352
mbed_official 340:28d1f895c6fe 1353 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 1354 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official 630:825f75ca301e 1355
mbed_official 340:28d1f895c6fe 1356 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 340:28d1f895c6fe 1357 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 340:28d1f895c6fe 1358 }
mbed_official 340:28d1f895c6fe 1359 break;
mbed_official 630:825f75ca301e 1360
mbed_official 340:28d1f895c6fe 1361 default:
mbed_official 340:28d1f895c6fe 1362 break;
mbed_official 340:28d1f895c6fe 1363 }
mbed_official 340:28d1f895c6fe 1364
mbed_official 340:28d1f895c6fe 1365 /* Enable the Capture compare channel */
mbed_official 340:28d1f895c6fe 1366 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 1367
mbed_official 630:825f75ca301e 1368 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 1369 {
mbed_official 340:28d1f895c6fe 1370 /* Enable the main output */
mbed_official 340:28d1f895c6fe 1371 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 340:28d1f895c6fe 1372 }
mbed_official 630:825f75ca301e 1373
mbed_official 340:28d1f895c6fe 1374 /* Enable the Peripheral */
mbed_official 630:825f75ca301e 1375 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 1376
mbed_official 340:28d1f895c6fe 1377 /* Return function status */
mbed_official 340:28d1f895c6fe 1378 return HAL_OK;
mbed_official 340:28d1f895c6fe 1379 }
mbed_official 340:28d1f895c6fe 1380
mbed_official 340:28d1f895c6fe 1381 /**
mbed_official 340:28d1f895c6fe 1382 * @brief Stops the TIM PWM signal generation in DMA mode.
mbed_official 340:28d1f895c6fe 1383 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 1384 * @param Channel : TIM Channels to be disabled
mbed_official 340:28d1f895c6fe 1385 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 1386 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 1387 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 1388 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 1389 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 1390 * @retval HAL status
mbed_official 340:28d1f895c6fe 1391 */
mbed_official 340:28d1f895c6fe 1392 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 1393 {
mbed_official 340:28d1f895c6fe 1394 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1395 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 1396
mbed_official 340:28d1f895c6fe 1397 switch (Channel)
mbed_official 340:28d1f895c6fe 1398 {
mbed_official 340:28d1f895c6fe 1399 case TIM_CHANNEL_1:
mbed_official 630:825f75ca301e 1400 {
mbed_official 340:28d1f895c6fe 1401 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 340:28d1f895c6fe 1402 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 340:28d1f895c6fe 1403 }
mbed_official 340:28d1f895c6fe 1404 break;
mbed_official 630:825f75ca301e 1405
mbed_official 340:28d1f895c6fe 1406 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 1407 {
mbed_official 340:28d1f895c6fe 1408 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 340:28d1f895c6fe 1409 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 340:28d1f895c6fe 1410 }
mbed_official 340:28d1f895c6fe 1411 break;
mbed_official 630:825f75ca301e 1412
mbed_official 340:28d1f895c6fe 1413 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 1414 {
mbed_official 340:28d1f895c6fe 1415 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 340:28d1f895c6fe 1416 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 340:28d1f895c6fe 1417 }
mbed_official 340:28d1f895c6fe 1418 break;
mbed_official 630:825f75ca301e 1419
mbed_official 340:28d1f895c6fe 1420 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 1421 {
mbed_official 340:28d1f895c6fe 1422 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 340:28d1f895c6fe 1423 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 340:28d1f895c6fe 1424 }
mbed_official 340:28d1f895c6fe 1425 break;
mbed_official 630:825f75ca301e 1426
mbed_official 340:28d1f895c6fe 1427 default:
mbed_official 340:28d1f895c6fe 1428 break;
mbed_official 630:825f75ca301e 1429 }
mbed_official 630:825f75ca301e 1430
mbed_official 340:28d1f895c6fe 1431 /* Disable the Capture compare channel */
mbed_official 340:28d1f895c6fe 1432 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 1433
mbed_official 630:825f75ca301e 1434 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 1435 {
mbed_official 340:28d1f895c6fe 1436 /* Disable the Main Ouput */
mbed_official 340:28d1f895c6fe 1437 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 340:28d1f895c6fe 1438 }
mbed_official 630:825f75ca301e 1439
mbed_official 340:28d1f895c6fe 1440 /* Disable the Peripheral */
mbed_official 340:28d1f895c6fe 1441 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 1442
mbed_official 340:28d1f895c6fe 1443 /* Change the htim state */
mbed_official 340:28d1f895c6fe 1444 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 1445
mbed_official 340:28d1f895c6fe 1446 /* Return function status */
mbed_official 340:28d1f895c6fe 1447 return HAL_OK;
mbed_official 340:28d1f895c6fe 1448 }
mbed_official 340:28d1f895c6fe 1449
mbed_official 340:28d1f895c6fe 1450 /**
mbed_official 340:28d1f895c6fe 1451 * @}
mbed_official 340:28d1f895c6fe 1452 */
mbed_official 340:28d1f895c6fe 1453
mbed_official 340:28d1f895c6fe 1454 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
mbed_official 340:28d1f895c6fe 1455 * @brief Time Input Capture functions
mbed_official 340:28d1f895c6fe 1456 *
mbed_official 630:825f75ca301e 1457 @verbatim
mbed_official 340:28d1f895c6fe 1458 ==============================================================================
mbed_official 340:28d1f895c6fe 1459 ##### Time Input Capture functions #####
mbed_official 340:28d1f895c6fe 1460 ==============================================================================
mbed_official 630:825f75ca301e 1461 [..]
mbed_official 340:28d1f895c6fe 1462 This section provides functions allowing to:
mbed_official 630:825f75ca301e 1463 (+) Initialize and configure the TIM Input Capture.
mbed_official 340:28d1f895c6fe 1464 (+) De-initialize the TIM Input Capture.
mbed_official 340:28d1f895c6fe 1465 (+) Start the Time Input Capture.
mbed_official 340:28d1f895c6fe 1466 (+) Stop the Time Input Capture.
mbed_official 340:28d1f895c6fe 1467 (+) Start the Time Input Capture and enable interrupt.
mbed_official 340:28d1f895c6fe 1468 (+) Stop the Time Input Capture and disable interrupt.
mbed_official 340:28d1f895c6fe 1469 (+) Start the Time Input Capture and enable DMA transfer.
mbed_official 340:28d1f895c6fe 1470 (+) Stop the Time Input Capture and disable DMA transfer.
mbed_official 630:825f75ca301e 1471
mbed_official 340:28d1f895c6fe 1472 @endverbatim
mbed_official 340:28d1f895c6fe 1473 * @{
mbed_official 340:28d1f895c6fe 1474 */
mbed_official 340:28d1f895c6fe 1475 /**
mbed_official 340:28d1f895c6fe 1476 * @brief Initializes the TIM Input Capture Time base according to the specified
mbed_official 340:28d1f895c6fe 1477 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 340:28d1f895c6fe 1478 * @param htim : TIM Input Capture handle
mbed_official 340:28d1f895c6fe 1479 * @retval HAL status
mbed_official 340:28d1f895c6fe 1480 */
mbed_official 340:28d1f895c6fe 1481 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 1482 {
mbed_official 340:28d1f895c6fe 1483 /* Check the TIM handle allocation */
mbed_official 441:d2c15dda23c1 1484 if(htim == NULL)
mbed_official 340:28d1f895c6fe 1485 {
mbed_official 340:28d1f895c6fe 1486 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 1487 }
mbed_official 340:28d1f895c6fe 1488
mbed_official 340:28d1f895c6fe 1489 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1490 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 1491 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 630:825f75ca301e 1492 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 340:28d1f895c6fe 1493
mbed_official 340:28d1f895c6fe 1494 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 630:825f75ca301e 1495 {
mbed_official 630:825f75ca301e 1496 /* Allocate lock resource and initialize it */
mbed_official 630:825f75ca301e 1497 htim->Lock = HAL_UNLOCKED;
mbed_official 630:825f75ca301e 1498
mbed_official 340:28d1f895c6fe 1499 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 340:28d1f895c6fe 1500 HAL_TIM_IC_MspInit(htim);
mbed_official 340:28d1f895c6fe 1501 }
mbed_official 630:825f75ca301e 1502
mbed_official 340:28d1f895c6fe 1503 /* Set the TIM state */
mbed_official 630:825f75ca301e 1504 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 1505
mbed_official 630:825f75ca301e 1506 /* Init the base time for the input capture */
mbed_official 630:825f75ca301e 1507 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 630:825f75ca301e 1508
mbed_official 340:28d1f895c6fe 1509 /* Initialize the TIM state*/
mbed_official 340:28d1f895c6fe 1510 htim->State= HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 1511
mbed_official 340:28d1f895c6fe 1512 return HAL_OK;
mbed_official 340:28d1f895c6fe 1513 }
mbed_official 340:28d1f895c6fe 1514
mbed_official 340:28d1f895c6fe 1515 /**
mbed_official 340:28d1f895c6fe 1516 * @brief DeInitializes the TIM peripheral
mbed_official 340:28d1f895c6fe 1517 * @param htim : TIM Input Capture handle
mbed_official 340:28d1f895c6fe 1518 * @retval HAL status
mbed_official 340:28d1f895c6fe 1519 */
mbed_official 340:28d1f895c6fe 1520 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 1521 {
mbed_official 340:28d1f895c6fe 1522 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1523 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 1524
mbed_official 340:28d1f895c6fe 1525 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 1526
mbed_official 340:28d1f895c6fe 1527 /* Disable the TIM Peripheral Clock */
mbed_official 340:28d1f895c6fe 1528 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 1529
mbed_official 340:28d1f895c6fe 1530 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 340:28d1f895c6fe 1531 HAL_TIM_IC_MspDeInit(htim);
mbed_official 630:825f75ca301e 1532
mbed_official 630:825f75ca301e 1533 /* Change TIM state */
mbed_official 340:28d1f895c6fe 1534 htim->State = HAL_TIM_STATE_RESET;
mbed_official 630:825f75ca301e 1535
mbed_official 340:28d1f895c6fe 1536 /* Release Lock */
mbed_official 340:28d1f895c6fe 1537 __HAL_UNLOCK(htim);
mbed_official 340:28d1f895c6fe 1538
mbed_official 340:28d1f895c6fe 1539 return HAL_OK;
mbed_official 340:28d1f895c6fe 1540 }
mbed_official 340:28d1f895c6fe 1541
mbed_official 340:28d1f895c6fe 1542 /**
mbed_official 340:28d1f895c6fe 1543 * @brief Initializes the TIM Input Capture MSP.
mbed_official 340:28d1f895c6fe 1544 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 1545 * @retval None
mbed_official 340:28d1f895c6fe 1546 */
mbed_official 340:28d1f895c6fe 1547 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 1548 {
mbed_official 340:28d1f895c6fe 1549 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 1550 the HAL_TIM_IC_MspInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 1551 */
mbed_official 340:28d1f895c6fe 1552 }
mbed_official 340:28d1f895c6fe 1553
mbed_official 340:28d1f895c6fe 1554 /**
mbed_official 340:28d1f895c6fe 1555 * @brief DeInitializes TIM Input Capture MSP.
mbed_official 340:28d1f895c6fe 1556 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 1557 * @retval None
mbed_official 340:28d1f895c6fe 1558 */
mbed_official 340:28d1f895c6fe 1559 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 1560 {
mbed_official 340:28d1f895c6fe 1561 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 1562 the HAL_TIM_IC_MspDeInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 1563 */
mbed_official 340:28d1f895c6fe 1564 }
mbed_official 340:28d1f895c6fe 1565
mbed_official 340:28d1f895c6fe 1566 /**
mbed_official 340:28d1f895c6fe 1567 * @brief Starts the TIM Input Capture measurement.
mbed_official 340:28d1f895c6fe 1568 * @param htim : TIM Input Capture handle
mbed_official 340:28d1f895c6fe 1569 * @param Channel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 1570 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 1571 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 1572 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 1573 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 1574 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 1575 * @retval HAL status
mbed_official 340:28d1f895c6fe 1576 */
mbed_official 340:28d1f895c6fe 1577 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 1578 {
mbed_official 340:28d1f895c6fe 1579 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1580 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 1581
mbed_official 340:28d1f895c6fe 1582 /* Enable the Input Capture channel */
mbed_official 340:28d1f895c6fe 1583 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 1584
mbed_official 340:28d1f895c6fe 1585 /* Enable the Peripheral */
mbed_official 630:825f75ca301e 1586 __HAL_TIM_ENABLE(htim);
mbed_official 340:28d1f895c6fe 1587
mbed_official 340:28d1f895c6fe 1588 /* Return function status */
mbed_official 630:825f75ca301e 1589 return HAL_OK;
mbed_official 630:825f75ca301e 1590 }
mbed_official 340:28d1f895c6fe 1591
mbed_official 340:28d1f895c6fe 1592 /**
mbed_official 340:28d1f895c6fe 1593 * @brief Stops the TIM Input Capture measurement.
mbed_official 340:28d1f895c6fe 1594 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 1595 * @param Channel : TIM Channels to be disabled
mbed_official 340:28d1f895c6fe 1596 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 1597 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 1598 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 1599 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 1600 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 1601 * @retval HAL status
mbed_official 340:28d1f895c6fe 1602 */
mbed_official 340:28d1f895c6fe 1603 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 630:825f75ca301e 1604 {
mbed_official 340:28d1f895c6fe 1605 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1606 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 1607
mbed_official 340:28d1f895c6fe 1608 /* Disable the Input Capture channel */
mbed_official 340:28d1f895c6fe 1609 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 1610
mbed_official 340:28d1f895c6fe 1611 /* Disable the Peripheral */
mbed_official 630:825f75ca301e 1612 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 1613
mbed_official 340:28d1f895c6fe 1614 /* Return function status */
mbed_official 340:28d1f895c6fe 1615 return HAL_OK;
mbed_official 340:28d1f895c6fe 1616 }
mbed_official 340:28d1f895c6fe 1617
mbed_official 340:28d1f895c6fe 1618 /**
mbed_official 340:28d1f895c6fe 1619 * @brief Starts the TIM Input Capture measurement in interrupt mode.
mbed_official 340:28d1f895c6fe 1620 * @param htim : TIM Input Capture handle
mbed_official 340:28d1f895c6fe 1621 * @param Channel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 1622 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 1623 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 1624 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 1625 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 1626 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 1627 * @retval HAL status
mbed_official 340:28d1f895c6fe 1628 */
mbed_official 340:28d1f895c6fe 1629 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 1630 {
mbed_official 340:28d1f895c6fe 1631 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1632 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 1633
mbed_official 340:28d1f895c6fe 1634 switch (Channel)
mbed_official 340:28d1f895c6fe 1635 {
mbed_official 340:28d1f895c6fe 1636 case TIM_CHANNEL_1:
mbed_official 630:825f75ca301e 1637 {
mbed_official 340:28d1f895c6fe 1638 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 340:28d1f895c6fe 1639 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 340:28d1f895c6fe 1640 }
mbed_official 340:28d1f895c6fe 1641 break;
mbed_official 630:825f75ca301e 1642
mbed_official 340:28d1f895c6fe 1643 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 1644 {
mbed_official 340:28d1f895c6fe 1645 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 340:28d1f895c6fe 1646 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 340:28d1f895c6fe 1647 }
mbed_official 340:28d1f895c6fe 1648 break;
mbed_official 630:825f75ca301e 1649
mbed_official 340:28d1f895c6fe 1650 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 1651 {
mbed_official 340:28d1f895c6fe 1652 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 340:28d1f895c6fe 1653 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 340:28d1f895c6fe 1654 }
mbed_official 340:28d1f895c6fe 1655 break;
mbed_official 630:825f75ca301e 1656
mbed_official 340:28d1f895c6fe 1657 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 1658 {
mbed_official 340:28d1f895c6fe 1659 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 340:28d1f895c6fe 1660 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 340:28d1f895c6fe 1661 }
mbed_official 340:28d1f895c6fe 1662 break;
mbed_official 630:825f75ca301e 1663
mbed_official 340:28d1f895c6fe 1664 default:
mbed_official 340:28d1f895c6fe 1665 break;
mbed_official 630:825f75ca301e 1666 }
mbed_official 340:28d1f895c6fe 1667 /* Enable the Input Capture channel */
mbed_official 340:28d1f895c6fe 1668 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 1669
mbed_official 340:28d1f895c6fe 1670 /* Enable the Peripheral */
mbed_official 630:825f75ca301e 1671 __HAL_TIM_ENABLE(htim);
mbed_official 340:28d1f895c6fe 1672
mbed_official 340:28d1f895c6fe 1673 /* Return function status */
mbed_official 630:825f75ca301e 1674 return HAL_OK;
mbed_official 630:825f75ca301e 1675 }
mbed_official 340:28d1f895c6fe 1676
mbed_official 340:28d1f895c6fe 1677 /**
mbed_official 340:28d1f895c6fe 1678 * @brief Stops the TIM Input Capture measurement in interrupt mode.
mbed_official 340:28d1f895c6fe 1679 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 1680 * @param Channel : TIM Channels to be disabled
mbed_official 340:28d1f895c6fe 1681 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 1682 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 1683 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 1684 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 1685 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 1686 * @retval HAL status
mbed_official 340:28d1f895c6fe 1687 */
mbed_official 340:28d1f895c6fe 1688 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 1689 {
mbed_official 340:28d1f895c6fe 1690 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1691 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 630:825f75ca301e 1692
mbed_official 340:28d1f895c6fe 1693 switch (Channel)
mbed_official 340:28d1f895c6fe 1694 {
mbed_official 340:28d1f895c6fe 1695 case TIM_CHANNEL_1:
mbed_official 630:825f75ca301e 1696 {
mbed_official 340:28d1f895c6fe 1697 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 340:28d1f895c6fe 1698 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 340:28d1f895c6fe 1699 }
mbed_official 340:28d1f895c6fe 1700 break;
mbed_official 630:825f75ca301e 1701
mbed_official 340:28d1f895c6fe 1702 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 1703 {
mbed_official 340:28d1f895c6fe 1704 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 340:28d1f895c6fe 1705 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 340:28d1f895c6fe 1706 }
mbed_official 340:28d1f895c6fe 1707 break;
mbed_official 630:825f75ca301e 1708
mbed_official 340:28d1f895c6fe 1709 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 1710 {
mbed_official 340:28d1f895c6fe 1711 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 340:28d1f895c6fe 1712 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 340:28d1f895c6fe 1713 }
mbed_official 340:28d1f895c6fe 1714 break;
mbed_official 630:825f75ca301e 1715
mbed_official 340:28d1f895c6fe 1716 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 1717 {
mbed_official 340:28d1f895c6fe 1718 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 340:28d1f895c6fe 1719 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 340:28d1f895c6fe 1720 }
mbed_official 340:28d1f895c6fe 1721 break;
mbed_official 630:825f75ca301e 1722
mbed_official 340:28d1f895c6fe 1723 default:
mbed_official 630:825f75ca301e 1724 break;
mbed_official 630:825f75ca301e 1725 }
mbed_official 630:825f75ca301e 1726
mbed_official 340:28d1f895c6fe 1727 /* Disable the Input Capture channel */
mbed_official 630:825f75ca301e 1728 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 1729
mbed_official 340:28d1f895c6fe 1730 /* Disable the Peripheral */
mbed_official 630:825f75ca301e 1731 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 1732
mbed_official 340:28d1f895c6fe 1733 /* Return function status */
mbed_official 340:28d1f895c6fe 1734 return HAL_OK;
mbed_official 340:28d1f895c6fe 1735 }
mbed_official 340:28d1f895c6fe 1736
mbed_official 340:28d1f895c6fe 1737 /**
mbed_official 340:28d1f895c6fe 1738 * @brief Starts the TIM Input Capture measurement in DMA mode.
mbed_official 340:28d1f895c6fe 1739 * @param htim : TIM Input Capture handle
mbed_official 340:28d1f895c6fe 1740 * @param Channel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 1741 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 1742 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 1743 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 1744 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 1745 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 1746 * @param pData : The destination Buffer address.
mbed_official 340:28d1f895c6fe 1747 * @param Length : The length of data to be transferred from TIM peripheral to memory.
mbed_official 340:28d1f895c6fe 1748 * @retval HAL status
mbed_official 340:28d1f895c6fe 1749 */
mbed_official 340:28d1f895c6fe 1750 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 340:28d1f895c6fe 1751 {
mbed_official 340:28d1f895c6fe 1752 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1753 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 340:28d1f895c6fe 1754 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 1755
mbed_official 340:28d1f895c6fe 1756 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 340:28d1f895c6fe 1757 {
mbed_official 340:28d1f895c6fe 1758 return HAL_BUSY;
mbed_official 340:28d1f895c6fe 1759 }
mbed_official 340:28d1f895c6fe 1760 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 340:28d1f895c6fe 1761 {
mbed_official 630:825f75ca301e 1762 if((pData == 0 ) && (Length > 0))
mbed_official 340:28d1f895c6fe 1763 {
mbed_official 630:825f75ca301e 1764 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 1765 }
mbed_official 340:28d1f895c6fe 1766 else
mbed_official 340:28d1f895c6fe 1767 {
mbed_official 340:28d1f895c6fe 1768 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 1769 }
mbed_official 630:825f75ca301e 1770 }
mbed_official 630:825f75ca301e 1771
mbed_official 340:28d1f895c6fe 1772 switch (Channel)
mbed_official 340:28d1f895c6fe 1773 {
mbed_official 340:28d1f895c6fe 1774 case TIM_CHANNEL_1:
mbed_official 340:28d1f895c6fe 1775 {
mbed_official 340:28d1f895c6fe 1776 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 1777 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 630:825f75ca301e 1778
mbed_official 340:28d1f895c6fe 1779 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 1780 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 1781
mbed_official 340:28d1f895c6fe 1782 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 1783 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
mbed_official 630:825f75ca301e 1784
mbed_official 630:825f75ca301e 1785 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 340:28d1f895c6fe 1786 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 340:28d1f895c6fe 1787 }
mbed_official 340:28d1f895c6fe 1788 break;
mbed_official 630:825f75ca301e 1789
mbed_official 340:28d1f895c6fe 1790 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 1791 {
mbed_official 340:28d1f895c6fe 1792 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 1793 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 630:825f75ca301e 1794
mbed_official 340:28d1f895c6fe 1795 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 1796 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 1797
mbed_official 340:28d1f895c6fe 1798 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 1799 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
mbed_official 630:825f75ca301e 1800
mbed_official 340:28d1f895c6fe 1801 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 340:28d1f895c6fe 1802 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 340:28d1f895c6fe 1803 }
mbed_official 340:28d1f895c6fe 1804 break;
mbed_official 630:825f75ca301e 1805
mbed_official 340:28d1f895c6fe 1806 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 1807 {
mbed_official 340:28d1f895c6fe 1808 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 1809 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 630:825f75ca301e 1810
mbed_official 340:28d1f895c6fe 1811 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 1812 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 1813
mbed_official 340:28d1f895c6fe 1814 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 1815 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
mbed_official 630:825f75ca301e 1816
mbed_official 340:28d1f895c6fe 1817 /* Enable the TIM Capture/Compare 3 DMA request */
mbed_official 340:28d1f895c6fe 1818 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 340:28d1f895c6fe 1819 }
mbed_official 340:28d1f895c6fe 1820 break;
mbed_official 630:825f75ca301e 1821
mbed_official 340:28d1f895c6fe 1822 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 1823 {
mbed_official 340:28d1f895c6fe 1824 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 1825 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 630:825f75ca301e 1826
mbed_official 340:28d1f895c6fe 1827 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 1828 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 1829
mbed_official 340:28d1f895c6fe 1830 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 1831 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
mbed_official 630:825f75ca301e 1832
mbed_official 340:28d1f895c6fe 1833 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 340:28d1f895c6fe 1834 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 340:28d1f895c6fe 1835 }
mbed_official 340:28d1f895c6fe 1836 break;
mbed_official 630:825f75ca301e 1837
mbed_official 340:28d1f895c6fe 1838 default:
mbed_official 340:28d1f895c6fe 1839 break;
mbed_official 340:28d1f895c6fe 1840 }
mbed_official 340:28d1f895c6fe 1841
mbed_official 340:28d1f895c6fe 1842 /* Enable the Input Capture channel */
mbed_official 340:28d1f895c6fe 1843 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 1844
mbed_official 340:28d1f895c6fe 1845 /* Enable the Peripheral */
mbed_official 630:825f75ca301e 1846 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 1847
mbed_official 340:28d1f895c6fe 1848 /* Return function status */
mbed_official 340:28d1f895c6fe 1849 return HAL_OK;
mbed_official 340:28d1f895c6fe 1850 }
mbed_official 340:28d1f895c6fe 1851
mbed_official 340:28d1f895c6fe 1852 /**
mbed_official 340:28d1f895c6fe 1853 * @brief Stops the TIM Input Capture measurement in DMA mode.
mbed_official 340:28d1f895c6fe 1854 * @param htim : TIM Input Capture handle
mbed_official 340:28d1f895c6fe 1855 * @param Channel : TIM Channels to be disabled
mbed_official 340:28d1f895c6fe 1856 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 1857 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 1858 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 1859 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 1860 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 1861 * @retval HAL status
mbed_official 340:28d1f895c6fe 1862 */
mbed_official 340:28d1f895c6fe 1863 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 1864 {
mbed_official 340:28d1f895c6fe 1865 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1866 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 340:28d1f895c6fe 1867 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 1868
mbed_official 340:28d1f895c6fe 1869 switch (Channel)
mbed_official 340:28d1f895c6fe 1870 {
mbed_official 340:28d1f895c6fe 1871 case TIM_CHANNEL_1:
mbed_official 630:825f75ca301e 1872 {
mbed_official 340:28d1f895c6fe 1873 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 340:28d1f895c6fe 1874 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 340:28d1f895c6fe 1875 }
mbed_official 340:28d1f895c6fe 1876 break;
mbed_official 630:825f75ca301e 1877
mbed_official 340:28d1f895c6fe 1878 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 1879 {
mbed_official 340:28d1f895c6fe 1880 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 340:28d1f895c6fe 1881 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 340:28d1f895c6fe 1882 }
mbed_official 340:28d1f895c6fe 1883 break;
mbed_official 630:825f75ca301e 1884
mbed_official 340:28d1f895c6fe 1885 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 1886 {
mbed_official 340:28d1f895c6fe 1887 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 340:28d1f895c6fe 1888 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 340:28d1f895c6fe 1889 }
mbed_official 340:28d1f895c6fe 1890 break;
mbed_official 630:825f75ca301e 1891
mbed_official 340:28d1f895c6fe 1892 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 1893 {
mbed_official 340:28d1f895c6fe 1894 /* Disable the TIM Capture/Compare 4 DMA request */
mbed_official 340:28d1f895c6fe 1895 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 340:28d1f895c6fe 1896 }
mbed_official 340:28d1f895c6fe 1897 break;
mbed_official 630:825f75ca301e 1898
mbed_official 340:28d1f895c6fe 1899 default:
mbed_official 340:28d1f895c6fe 1900 break;
mbed_official 340:28d1f895c6fe 1901 }
mbed_official 340:28d1f895c6fe 1902
mbed_official 340:28d1f895c6fe 1903 /* Disable the Input Capture channel */
mbed_official 340:28d1f895c6fe 1904 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 1905
mbed_official 340:28d1f895c6fe 1906 /* Disable the Peripheral */
mbed_official 630:825f75ca301e 1907 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 1908
mbed_official 340:28d1f895c6fe 1909 /* Change the htim state */
mbed_official 340:28d1f895c6fe 1910 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 1911
mbed_official 340:28d1f895c6fe 1912 /* Return function status */
mbed_official 340:28d1f895c6fe 1913 return HAL_OK;
mbed_official 340:28d1f895c6fe 1914 }
mbed_official 340:28d1f895c6fe 1915 /**
mbed_official 340:28d1f895c6fe 1916 * @}
mbed_official 340:28d1f895c6fe 1917 */
mbed_official 340:28d1f895c6fe 1918
mbed_official 340:28d1f895c6fe 1919 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
mbed_official 340:28d1f895c6fe 1920 * @brief Time One Pulse functions
mbed_official 340:28d1f895c6fe 1921 *
mbed_official 630:825f75ca301e 1922 @verbatim
mbed_official 340:28d1f895c6fe 1923 ==============================================================================
mbed_official 340:28d1f895c6fe 1924 ##### Time One Pulse functions #####
mbed_official 340:28d1f895c6fe 1925 ==============================================================================
mbed_official 630:825f75ca301e 1926 [..]
mbed_official 340:28d1f895c6fe 1927 This section provides functions allowing to:
mbed_official 630:825f75ca301e 1928 (+) Initialize and configure the TIM One Pulse.
mbed_official 340:28d1f895c6fe 1929 (+) De-initialize the TIM One Pulse.
mbed_official 340:28d1f895c6fe 1930 (+) Start the Time One Pulse.
mbed_official 340:28d1f895c6fe 1931 (+) Stop the Time One Pulse.
mbed_official 340:28d1f895c6fe 1932 (+) Start the Time One Pulse and enable interrupt.
mbed_official 340:28d1f895c6fe 1933 (+) Stop the Time One Pulse and disable interrupt.
mbed_official 340:28d1f895c6fe 1934 (+) Start the Time One Pulse and enable DMA transfer.
mbed_official 340:28d1f895c6fe 1935 (+) Stop the Time One Pulse and disable DMA transfer.
mbed_official 630:825f75ca301e 1936
mbed_official 340:28d1f895c6fe 1937 @endverbatim
mbed_official 340:28d1f895c6fe 1938 * @{
mbed_official 340:28d1f895c6fe 1939 */
mbed_official 340:28d1f895c6fe 1940 /**
mbed_official 340:28d1f895c6fe 1941 * @brief Initializes the TIM One Pulse Time Base according to the specified
mbed_official 340:28d1f895c6fe 1942 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 340:28d1f895c6fe 1943 * @param htim : TIM OnePulse handle
mbed_official 340:28d1f895c6fe 1944 * @param OnePulseMode : Select the One pulse mode.
mbed_official 340:28d1f895c6fe 1945 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 1946 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
mbed_official 340:28d1f895c6fe 1947 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
mbed_official 340:28d1f895c6fe 1948 * @retval HAL status
mbed_official 340:28d1f895c6fe 1949 */
mbed_official 340:28d1f895c6fe 1950 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
mbed_official 340:28d1f895c6fe 1951 {
mbed_official 340:28d1f895c6fe 1952 /* Check the TIM handle allocation */
mbed_official 441:d2c15dda23c1 1953 if(htim == NULL)
mbed_official 340:28d1f895c6fe 1954 {
mbed_official 340:28d1f895c6fe 1955 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 1956 }
mbed_official 340:28d1f895c6fe 1957
mbed_official 340:28d1f895c6fe 1958 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1959 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 1960 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 340:28d1f895c6fe 1961 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 340:28d1f895c6fe 1962 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
mbed_official 630:825f75ca301e 1963
mbed_official 340:28d1f895c6fe 1964 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 630:825f75ca301e 1965 {
mbed_official 630:825f75ca301e 1966 /* Allocate lock resource and initialize it */
mbed_official 630:825f75ca301e 1967 htim->Lock = HAL_UNLOCKED;
mbed_official 630:825f75ca301e 1968
mbed_official 340:28d1f895c6fe 1969 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 340:28d1f895c6fe 1970 HAL_TIM_OnePulse_MspInit(htim);
mbed_official 340:28d1f895c6fe 1971 }
mbed_official 630:825f75ca301e 1972
mbed_official 340:28d1f895c6fe 1973 /* Set the TIM state */
mbed_official 340:28d1f895c6fe 1974 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 1975
mbed_official 340:28d1f895c6fe 1976 /* Configure the Time base in the One Pulse Mode */
mbed_official 340:28d1f895c6fe 1977 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 630:825f75ca301e 1978
mbed_official 340:28d1f895c6fe 1979 /* Reset the OPM Bit */
mbed_official 340:28d1f895c6fe 1980 htim->Instance->CR1 &= ~TIM_CR1_OPM;
mbed_official 340:28d1f895c6fe 1981
mbed_official 340:28d1f895c6fe 1982 /* Configure the OPM Mode */
mbed_official 340:28d1f895c6fe 1983 htim->Instance->CR1 |= OnePulseMode;
mbed_official 630:825f75ca301e 1984
mbed_official 340:28d1f895c6fe 1985 /* Initialize the TIM state*/
mbed_official 340:28d1f895c6fe 1986 htim->State= HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 1987
mbed_official 340:28d1f895c6fe 1988 return HAL_OK;
mbed_official 340:28d1f895c6fe 1989 }
mbed_official 340:28d1f895c6fe 1990
mbed_official 340:28d1f895c6fe 1991 /**
mbed_official 630:825f75ca301e 1992 * @brief DeInitializes the TIM One Pulse
mbed_official 340:28d1f895c6fe 1993 * @param htim : TIM One Pulse handle
mbed_official 340:28d1f895c6fe 1994 * @retval HAL status
mbed_official 340:28d1f895c6fe 1995 */
mbed_official 340:28d1f895c6fe 1996 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 1997 {
mbed_official 340:28d1f895c6fe 1998 /* Check the parameters */
mbed_official 340:28d1f895c6fe 1999 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 2000
mbed_official 340:28d1f895c6fe 2001 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 2002
mbed_official 340:28d1f895c6fe 2003 /* Disable the TIM Peripheral Clock */
mbed_official 340:28d1f895c6fe 2004 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 2005
mbed_official 340:28d1f895c6fe 2006 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 340:28d1f895c6fe 2007 HAL_TIM_OnePulse_MspDeInit(htim);
mbed_official 630:825f75ca301e 2008
mbed_official 630:825f75ca301e 2009 /* Change TIM state */
mbed_official 630:825f75ca301e 2010 htim->State = HAL_TIM_STATE_RESET;
mbed_official 630:825f75ca301e 2011
mbed_official 340:28d1f895c6fe 2012 /* Release Lock */
mbed_official 340:28d1f895c6fe 2013 __HAL_UNLOCK(htim);
mbed_official 340:28d1f895c6fe 2014
mbed_official 340:28d1f895c6fe 2015 return HAL_OK;
mbed_official 340:28d1f895c6fe 2016 }
mbed_official 340:28d1f895c6fe 2017
mbed_official 340:28d1f895c6fe 2018 /**
mbed_official 340:28d1f895c6fe 2019 * @brief Initializes the TIM One Pulse MSP.
mbed_official 340:28d1f895c6fe 2020 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 2021 * @retval None
mbed_official 340:28d1f895c6fe 2022 */
mbed_official 340:28d1f895c6fe 2023 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 2024 {
mbed_official 340:28d1f895c6fe 2025 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 2026 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 2027 */
mbed_official 340:28d1f895c6fe 2028 }
mbed_official 340:28d1f895c6fe 2029
mbed_official 340:28d1f895c6fe 2030 /**
mbed_official 340:28d1f895c6fe 2031 * @brief DeInitializes TIM One Pulse MSP.
mbed_official 340:28d1f895c6fe 2032 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 2033 * @retval None
mbed_official 340:28d1f895c6fe 2034 */
mbed_official 340:28d1f895c6fe 2035 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 2036 {
mbed_official 340:28d1f895c6fe 2037 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 2038 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 2039 */
mbed_official 340:28d1f895c6fe 2040 }
mbed_official 340:28d1f895c6fe 2041
mbed_official 340:28d1f895c6fe 2042 /**
mbed_official 340:28d1f895c6fe 2043 * @brief Starts the TIM One Pulse signal generation.
mbed_official 340:28d1f895c6fe 2044 * @param htim : TIM One Pulse handle
mbed_official 340:28d1f895c6fe 2045 * @param OutputChannel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 2046 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 2047 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 2048 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 2049 * @retval HAL status
mbed_official 340:28d1f895c6fe 2050 */
mbed_official 340:28d1f895c6fe 2051 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 340:28d1f895c6fe 2052 {
mbed_official 340:28d1f895c6fe 2053 /* Enable the Capture compare and the Input Capture channels
mbed_official 340:28d1f895c6fe 2054 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 340:28d1f895c6fe 2055 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 340:28d1f895c6fe 2056 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 340:28d1f895c6fe 2057 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official 630:825f75ca301e 2058
mbed_official 340:28d1f895c6fe 2059 No need to enable the counter, it's enabled automatically by hardware
mbed_official 340:28d1f895c6fe 2060 (the counter starts in response to a stimulus and generate a pulse */
mbed_official 630:825f75ca301e 2061
mbed_official 630:825f75ca301e 2062 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 2063 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 2064
mbed_official 630:825f75ca301e 2065 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 2066 {
mbed_official 340:28d1f895c6fe 2067 /* Enable the main output */
mbed_official 340:28d1f895c6fe 2068 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 340:28d1f895c6fe 2069 }
mbed_official 630:825f75ca301e 2070
mbed_official 340:28d1f895c6fe 2071 /* Return function status */
mbed_official 340:28d1f895c6fe 2072 return HAL_OK;
mbed_official 340:28d1f895c6fe 2073 }
mbed_official 340:28d1f895c6fe 2074
mbed_official 340:28d1f895c6fe 2075 /**
mbed_official 340:28d1f895c6fe 2076 * @brief Stops the TIM One Pulse signal generation.
mbed_official 340:28d1f895c6fe 2077 * @param htim : TIM One Pulse handle
mbed_official 340:28d1f895c6fe 2078 * @param OutputChannel : TIM Channels to be disable
mbed_official 340:28d1f895c6fe 2079 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 2080 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 2081 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 2082 * @retval HAL status
mbed_official 340:28d1f895c6fe 2083 */
mbed_official 340:28d1f895c6fe 2084 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 340:28d1f895c6fe 2085 {
mbed_official 340:28d1f895c6fe 2086 /* Disable the Capture compare and the Input Capture channels
mbed_official 340:28d1f895c6fe 2087 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 340:28d1f895c6fe 2088 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 340:28d1f895c6fe 2089 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 340:28d1f895c6fe 2090 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official 630:825f75ca301e 2091
mbed_official 630:825f75ca301e 2092 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2093 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2094
mbed_official 630:825f75ca301e 2095 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 2096 {
mbed_official 340:28d1f895c6fe 2097 /* Disable the Main Ouput */
mbed_official 340:28d1f895c6fe 2098 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 340:28d1f895c6fe 2099 }
mbed_official 630:825f75ca301e 2100
mbed_official 340:28d1f895c6fe 2101 /* Disable the Peripheral */
mbed_official 630:825f75ca301e 2102 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 2103
mbed_official 340:28d1f895c6fe 2104 /* Return function status */
mbed_official 340:28d1f895c6fe 2105 return HAL_OK;
mbed_official 340:28d1f895c6fe 2106 }
mbed_official 340:28d1f895c6fe 2107
mbed_official 340:28d1f895c6fe 2108 /**
mbed_official 340:28d1f895c6fe 2109 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
mbed_official 340:28d1f895c6fe 2110 * @param htim : TIM One Pulse handle
mbed_official 340:28d1f895c6fe 2111 * @param OutputChannel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 2112 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 2113 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 2114 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 2115 * @retval HAL status
mbed_official 340:28d1f895c6fe 2116 */
mbed_official 340:28d1f895c6fe 2117 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 340:28d1f895c6fe 2118 {
mbed_official 340:28d1f895c6fe 2119 /* Enable the Capture compare and the Input Capture channels
mbed_official 340:28d1f895c6fe 2120 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 340:28d1f895c6fe 2121 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 340:28d1f895c6fe 2122 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 340:28d1f895c6fe 2123 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official 630:825f75ca301e 2124
mbed_official 340:28d1f895c6fe 2125 No need to enable the counter, it's enabled automatically by hardware
mbed_official 340:28d1f895c6fe 2126 (the counter starts in response to a stimulus and generate a pulse */
mbed_official 630:825f75ca301e 2127
mbed_official 340:28d1f895c6fe 2128 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 340:28d1f895c6fe 2129 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 630:825f75ca301e 2130
mbed_official 340:28d1f895c6fe 2131 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 340:28d1f895c6fe 2132 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 630:825f75ca301e 2133
mbed_official 630:825f75ca301e 2134 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 2135 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 2136
mbed_official 630:825f75ca301e 2137 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 2138 {
mbed_official 340:28d1f895c6fe 2139 /* Enable the main output */
mbed_official 340:28d1f895c6fe 2140 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 340:28d1f895c6fe 2141 }
mbed_official 630:825f75ca301e 2142
mbed_official 340:28d1f895c6fe 2143 /* Return function status */
mbed_official 340:28d1f895c6fe 2144 return HAL_OK;
mbed_official 340:28d1f895c6fe 2145 }
mbed_official 340:28d1f895c6fe 2146
mbed_official 340:28d1f895c6fe 2147 /**
mbed_official 340:28d1f895c6fe 2148 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
mbed_official 340:28d1f895c6fe 2149 * @param htim : TIM One Pulse handle
mbed_official 340:28d1f895c6fe 2150 * @param OutputChannel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 2151 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 2152 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 2153 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 2154 * @retval HAL status
mbed_official 340:28d1f895c6fe 2155 */
mbed_official 340:28d1f895c6fe 2156 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 340:28d1f895c6fe 2157 {
mbed_official 340:28d1f895c6fe 2158 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 630:825f75ca301e 2159 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 630:825f75ca301e 2160
mbed_official 340:28d1f895c6fe 2161 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 340:28d1f895c6fe 2162 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 630:825f75ca301e 2163
mbed_official 340:28d1f895c6fe 2164 /* Disable the Capture compare and the Input Capture channels
mbed_official 340:28d1f895c6fe 2165 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 340:28d1f895c6fe 2166 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 340:28d1f895c6fe 2167 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 630:825f75ca301e 2168 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official 630:825f75ca301e 2169 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2170 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2171
mbed_official 630:825f75ca301e 2172 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official 340:28d1f895c6fe 2173 {
mbed_official 340:28d1f895c6fe 2174 /* Disable the Main Ouput */
mbed_official 340:28d1f895c6fe 2175 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 340:28d1f895c6fe 2176 }
mbed_official 630:825f75ca301e 2177
mbed_official 340:28d1f895c6fe 2178 /* Disable the Peripheral */
mbed_official 630:825f75ca301e 2179 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 2180
mbed_official 340:28d1f895c6fe 2181 /* Return function status */
mbed_official 340:28d1f895c6fe 2182 return HAL_OK;
mbed_official 340:28d1f895c6fe 2183 }
mbed_official 340:28d1f895c6fe 2184
mbed_official 340:28d1f895c6fe 2185 /**
mbed_official 340:28d1f895c6fe 2186 * @}
mbed_official 340:28d1f895c6fe 2187 */
mbed_official 340:28d1f895c6fe 2188
mbed_official 340:28d1f895c6fe 2189 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
mbed_official 340:28d1f895c6fe 2190 * @brief Time Encoder functions
mbed_official 340:28d1f895c6fe 2191 *
mbed_official 630:825f75ca301e 2192 @verbatim
mbed_official 340:28d1f895c6fe 2193 ==============================================================================
mbed_official 340:28d1f895c6fe 2194 ##### Time Encoder functions #####
mbed_official 340:28d1f895c6fe 2195 ==============================================================================
mbed_official 340:28d1f895c6fe 2196 [..]
mbed_official 340:28d1f895c6fe 2197 This section provides functions allowing to:
mbed_official 630:825f75ca301e 2198 (+) Initialize and configure the TIM Encoder.
mbed_official 340:28d1f895c6fe 2199 (+) De-initialize the TIM Encoder.
mbed_official 340:28d1f895c6fe 2200 (+) Start the Time Encoder.
mbed_official 340:28d1f895c6fe 2201 (+) Stop the Time Encoder.
mbed_official 340:28d1f895c6fe 2202 (+) Start the Time Encoder and enable interrupt.
mbed_official 340:28d1f895c6fe 2203 (+) Stop the Time Encoder and disable interrupt.
mbed_official 340:28d1f895c6fe 2204 (+) Start the Time Encoder and enable DMA transfer.
mbed_official 340:28d1f895c6fe 2205 (+) Stop the Time Encoder and disable DMA transfer.
mbed_official 630:825f75ca301e 2206
mbed_official 340:28d1f895c6fe 2207 @endverbatim
mbed_official 340:28d1f895c6fe 2208 * @{
mbed_official 340:28d1f895c6fe 2209 */
mbed_official 340:28d1f895c6fe 2210 /**
mbed_official 340:28d1f895c6fe 2211 * @brief Initializes the TIM Encoder Interface and create the associated handle.
mbed_official 340:28d1f895c6fe 2212 * @param htim : TIM Encoder Interface handle
mbed_official 340:28d1f895c6fe 2213 * @param sConfig : TIM Encoder Interface configuration structure
mbed_official 340:28d1f895c6fe 2214 * @retval HAL status
mbed_official 340:28d1f895c6fe 2215 */
mbed_official 340:28d1f895c6fe 2216 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
mbed_official 340:28d1f895c6fe 2217 {
mbed_official 340:28d1f895c6fe 2218 uint32_t tmpsmcr = 0;
mbed_official 340:28d1f895c6fe 2219 uint32_t tmpccmr1 = 0;
mbed_official 340:28d1f895c6fe 2220 uint32_t tmpccer = 0;
mbed_official 630:825f75ca301e 2221
mbed_official 340:28d1f895c6fe 2222 /* Check the TIM handle allocation */
mbed_official 441:d2c15dda23c1 2223 if(htim == NULL)
mbed_official 340:28d1f895c6fe 2224 {
mbed_official 340:28d1f895c6fe 2225 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 2226 }
mbed_official 630:825f75ca301e 2227
mbed_official 340:28d1f895c6fe 2228 /* Check the parameters */
mbed_official 340:28d1f895c6fe 2229 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 2230 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
mbed_official 340:28d1f895c6fe 2231 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
mbed_official 340:28d1f895c6fe 2232 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
mbed_official 340:28d1f895c6fe 2233 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
mbed_official 340:28d1f895c6fe 2234 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
mbed_official 340:28d1f895c6fe 2235 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
mbed_official 340:28d1f895c6fe 2236 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
mbed_official 340:28d1f895c6fe 2237 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
mbed_official 340:28d1f895c6fe 2238 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
mbed_official 340:28d1f895c6fe 2239
mbed_official 340:28d1f895c6fe 2240 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 630:825f75ca301e 2241 {
mbed_official 630:825f75ca301e 2242 /* Allocate lock resource and initialize it */
mbed_official 630:825f75ca301e 2243 htim->Lock = HAL_UNLOCKED;
mbed_official 630:825f75ca301e 2244
mbed_official 340:28d1f895c6fe 2245 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 340:28d1f895c6fe 2246 HAL_TIM_Encoder_MspInit(htim);
mbed_official 340:28d1f895c6fe 2247 }
mbed_official 630:825f75ca301e 2248
mbed_official 340:28d1f895c6fe 2249 /* Set the TIM state */
mbed_official 340:28d1f895c6fe 2250 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 2251
mbed_official 340:28d1f895c6fe 2252 /* Reset the SMS bits */
mbed_official 340:28d1f895c6fe 2253 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 630:825f75ca301e 2254
mbed_official 340:28d1f895c6fe 2255 /* Configure the Time base in the Encoder Mode */
mbed_official 630:825f75ca301e 2256 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 630:825f75ca301e 2257
mbed_official 340:28d1f895c6fe 2258 /* Get the TIMx SMCR register value */
mbed_official 340:28d1f895c6fe 2259 tmpsmcr = htim->Instance->SMCR;
mbed_official 340:28d1f895c6fe 2260
mbed_official 340:28d1f895c6fe 2261 /* Get the TIMx CCMR1 register value */
mbed_official 340:28d1f895c6fe 2262 tmpccmr1 = htim->Instance->CCMR1;
mbed_official 340:28d1f895c6fe 2263
mbed_official 340:28d1f895c6fe 2264 /* Get the TIMx CCER register value */
mbed_official 340:28d1f895c6fe 2265 tmpccer = htim->Instance->CCER;
mbed_official 340:28d1f895c6fe 2266
mbed_official 340:28d1f895c6fe 2267 /* Set the encoder Mode */
mbed_official 340:28d1f895c6fe 2268 tmpsmcr |= sConfig->EncoderMode;
mbed_official 340:28d1f895c6fe 2269
mbed_official 340:28d1f895c6fe 2270 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
mbed_official 340:28d1f895c6fe 2271 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
mbed_official 340:28d1f895c6fe 2272 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
mbed_official 630:825f75ca301e 2273
mbed_official 340:28d1f895c6fe 2274 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
mbed_official 340:28d1f895c6fe 2275 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
mbed_official 340:28d1f895c6fe 2276 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
mbed_official 340:28d1f895c6fe 2277 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
mbed_official 340:28d1f895c6fe 2278 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
mbed_official 340:28d1f895c6fe 2279
mbed_official 340:28d1f895c6fe 2280 /* Set the TI1 and the TI2 Polarities */
mbed_official 340:28d1f895c6fe 2281 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
mbed_official 340:28d1f895c6fe 2282 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
mbed_official 340:28d1f895c6fe 2283 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
mbed_official 630:825f75ca301e 2284
mbed_official 340:28d1f895c6fe 2285 /* Write to TIMx SMCR */
mbed_official 340:28d1f895c6fe 2286 htim->Instance->SMCR = tmpsmcr;
mbed_official 340:28d1f895c6fe 2287
mbed_official 340:28d1f895c6fe 2288 /* Write to TIMx CCMR1 */
mbed_official 340:28d1f895c6fe 2289 htim->Instance->CCMR1 = tmpccmr1;
mbed_official 340:28d1f895c6fe 2290
mbed_official 340:28d1f895c6fe 2291 /* Write to TIMx CCER */
mbed_official 340:28d1f895c6fe 2292 htim->Instance->CCER = tmpccer;
mbed_official 630:825f75ca301e 2293
mbed_official 340:28d1f895c6fe 2294 /* Initialize the TIM state*/
mbed_official 340:28d1f895c6fe 2295 htim->State= HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 2296
mbed_official 340:28d1f895c6fe 2297 return HAL_OK;
mbed_official 340:28d1f895c6fe 2298 }
mbed_official 340:28d1f895c6fe 2299
mbed_official 340:28d1f895c6fe 2300
mbed_official 340:28d1f895c6fe 2301 /**
mbed_official 630:825f75ca301e 2302 * @brief DeInitializes the TIM Encoder interface
mbed_official 340:28d1f895c6fe 2303 * @param htim : TIM Encoder handle
mbed_official 340:28d1f895c6fe 2304 * @retval HAL status
mbed_official 340:28d1f895c6fe 2305 */
mbed_official 340:28d1f895c6fe 2306 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 2307 {
mbed_official 340:28d1f895c6fe 2308 /* Check the parameters */
mbed_official 340:28d1f895c6fe 2309 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 2310
mbed_official 340:28d1f895c6fe 2311 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 2312
mbed_official 340:28d1f895c6fe 2313 /* Disable the TIM Peripheral Clock */
mbed_official 340:28d1f895c6fe 2314 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 2315
mbed_official 340:28d1f895c6fe 2316 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 340:28d1f895c6fe 2317 HAL_TIM_Encoder_MspDeInit(htim);
mbed_official 630:825f75ca301e 2318
mbed_official 630:825f75ca301e 2319 /* Change TIM state */
mbed_official 630:825f75ca301e 2320 htim->State = HAL_TIM_STATE_RESET;
mbed_official 630:825f75ca301e 2321
mbed_official 340:28d1f895c6fe 2322 /* Release Lock */
mbed_official 340:28d1f895c6fe 2323 __HAL_UNLOCK(htim);
mbed_official 340:28d1f895c6fe 2324
mbed_official 340:28d1f895c6fe 2325 return HAL_OK;
mbed_official 340:28d1f895c6fe 2326 }
mbed_official 340:28d1f895c6fe 2327
mbed_official 340:28d1f895c6fe 2328 /**
mbed_official 340:28d1f895c6fe 2329 * @brief Initializes the TIM Encoder Interface MSP.
mbed_official 340:28d1f895c6fe 2330 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 2331 * @retval None
mbed_official 340:28d1f895c6fe 2332 */
mbed_official 340:28d1f895c6fe 2333 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 2334 {
mbed_official 340:28d1f895c6fe 2335 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 2336 the HAL_TIM_Encoder_MspInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 2337 */
mbed_official 340:28d1f895c6fe 2338 }
mbed_official 340:28d1f895c6fe 2339
mbed_official 340:28d1f895c6fe 2340 /**
mbed_official 340:28d1f895c6fe 2341 * @brief DeInitializes TIM Encoder Interface MSP.
mbed_official 340:28d1f895c6fe 2342 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 2343 * @retval None
mbed_official 340:28d1f895c6fe 2344 */
mbed_official 340:28d1f895c6fe 2345 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 2346 {
mbed_official 340:28d1f895c6fe 2347 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 2348 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 2349 */
mbed_official 340:28d1f895c6fe 2350 }
mbed_official 340:28d1f895c6fe 2351
mbed_official 340:28d1f895c6fe 2352 /**
mbed_official 340:28d1f895c6fe 2353 * @brief Starts the TIM Encoder Interface.
mbed_official 340:28d1f895c6fe 2354 * @param htim : TIM Encoder Interface handle
mbed_official 340:28d1f895c6fe 2355 * @param Channel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 2356 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 2357 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 2358 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 630:825f75ca301e 2359 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 340:28d1f895c6fe 2360 * @retval HAL status
mbed_official 340:28d1f895c6fe 2361 */
mbed_official 340:28d1f895c6fe 2362 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 2363 {
mbed_official 340:28d1f895c6fe 2364 /* Check the parameters */
mbed_official 340:28d1f895c6fe 2365 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 2366
mbed_official 340:28d1f895c6fe 2367 /* Enable the encoder interface channels */
mbed_official 340:28d1f895c6fe 2368 switch (Channel)
mbed_official 340:28d1f895c6fe 2369 {
mbed_official 340:28d1f895c6fe 2370 case TIM_CHANNEL_1:
mbed_official 340:28d1f895c6fe 2371 {
mbed_official 630:825f75ca301e 2372 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 2373 break;
mbed_official 630:825f75ca301e 2374 }
mbed_official 340:28d1f895c6fe 2375 case TIM_CHANNEL_2:
mbed_official 630:825f75ca301e 2376 {
mbed_official 630:825f75ca301e 2377 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 340:28d1f895c6fe 2378 break;
mbed_official 630:825f75ca301e 2379 }
mbed_official 340:28d1f895c6fe 2380 default :
mbed_official 340:28d1f895c6fe 2381 {
mbed_official 340:28d1f895c6fe 2382 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 2383 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 2384 break;
mbed_official 340:28d1f895c6fe 2385 }
mbed_official 630:825f75ca301e 2386 }
mbed_official 340:28d1f895c6fe 2387 /* Enable the Peripheral */
mbed_official 340:28d1f895c6fe 2388 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 2389
mbed_official 340:28d1f895c6fe 2390 /* Return function status */
mbed_official 340:28d1f895c6fe 2391 return HAL_OK;
mbed_official 340:28d1f895c6fe 2392 }
mbed_official 340:28d1f895c6fe 2393
mbed_official 340:28d1f895c6fe 2394 /**
mbed_official 340:28d1f895c6fe 2395 * @brief Stops the TIM Encoder Interface.
mbed_official 340:28d1f895c6fe 2396 * @param htim : TIM Encoder Interface handle
mbed_official 340:28d1f895c6fe 2397 * @param Channel : TIM Channels to be disabled
mbed_official 340:28d1f895c6fe 2398 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 2399 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 2400 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 630:825f75ca301e 2401 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 340:28d1f895c6fe 2402 * @retval HAL status
mbed_official 340:28d1f895c6fe 2403 */
mbed_official 340:28d1f895c6fe 2404 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 2405 {
mbed_official 340:28d1f895c6fe 2406 /* Check the parameters */
mbed_official 340:28d1f895c6fe 2407 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 2408
mbed_official 340:28d1f895c6fe 2409 /* Disable the Input Capture channels 1 and 2
mbed_official 630:825f75ca301e 2410 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 340:28d1f895c6fe 2411 switch (Channel)
mbed_official 340:28d1f895c6fe 2412 {
mbed_official 340:28d1f895c6fe 2413 case TIM_CHANNEL_1:
mbed_official 340:28d1f895c6fe 2414 {
mbed_official 630:825f75ca301e 2415 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2416 break;
mbed_official 630:825f75ca301e 2417 }
mbed_official 340:28d1f895c6fe 2418 case TIM_CHANNEL_2:
mbed_official 630:825f75ca301e 2419 {
mbed_official 630:825f75ca301e 2420 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 340:28d1f895c6fe 2421 break;
mbed_official 630:825f75ca301e 2422 }
mbed_official 340:28d1f895c6fe 2423 default :
mbed_official 340:28d1f895c6fe 2424 {
mbed_official 630:825f75ca301e 2425 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2426 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2427 break;
mbed_official 340:28d1f895c6fe 2428 }
mbed_official 340:28d1f895c6fe 2429 }
mbed_official 340:28d1f895c6fe 2430
mbed_official 340:28d1f895c6fe 2431 /* Disable the Peripheral */
mbed_official 340:28d1f895c6fe 2432 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 2433
mbed_official 340:28d1f895c6fe 2434 /* Return function status */
mbed_official 340:28d1f895c6fe 2435 return HAL_OK;
mbed_official 340:28d1f895c6fe 2436 }
mbed_official 340:28d1f895c6fe 2437
mbed_official 340:28d1f895c6fe 2438 /**
mbed_official 340:28d1f895c6fe 2439 * @brief Starts the TIM Encoder Interface in interrupt mode.
mbed_official 340:28d1f895c6fe 2440 * @param htim : TIM Encoder Interface handle
mbed_official 340:28d1f895c6fe 2441 * @param Channel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 2442 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 2443 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 2444 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 630:825f75ca301e 2445 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 340:28d1f895c6fe 2446 * @retval HAL status
mbed_official 340:28d1f895c6fe 2447 */
mbed_official 340:28d1f895c6fe 2448 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 2449 {
mbed_official 340:28d1f895c6fe 2450 /* Check the parameters */
mbed_official 340:28d1f895c6fe 2451 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 2452
mbed_official 340:28d1f895c6fe 2453 /* Enable the encoder interface channels */
mbed_official 340:28d1f895c6fe 2454 /* Enable the capture compare Interrupts 1 and/or 2 */
mbed_official 340:28d1f895c6fe 2455 switch (Channel)
mbed_official 340:28d1f895c6fe 2456 {
mbed_official 340:28d1f895c6fe 2457 case TIM_CHANNEL_1:
mbed_official 340:28d1f895c6fe 2458 {
mbed_official 630:825f75ca301e 2459 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 340:28d1f895c6fe 2460 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 630:825f75ca301e 2461 break;
mbed_official 630:825f75ca301e 2462 }
mbed_official 340:28d1f895c6fe 2463 case TIM_CHANNEL_2:
mbed_official 630:825f75ca301e 2464 {
mbed_official 630:825f75ca301e 2465 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 340:28d1f895c6fe 2466 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 340:28d1f895c6fe 2467 break;
mbed_official 630:825f75ca301e 2468 }
mbed_official 340:28d1f895c6fe 2469 default :
mbed_official 340:28d1f895c6fe 2470 {
mbed_official 340:28d1f895c6fe 2471 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 2472 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 340:28d1f895c6fe 2473 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 340:28d1f895c6fe 2474 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 630:825f75ca301e 2475 break;
mbed_official 340:28d1f895c6fe 2476 }
mbed_official 630:825f75ca301e 2477 }
mbed_official 630:825f75ca301e 2478
mbed_official 340:28d1f895c6fe 2479 /* Enable the Peripheral */
mbed_official 340:28d1f895c6fe 2480 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 2481
mbed_official 340:28d1f895c6fe 2482 /* Return function status */
mbed_official 340:28d1f895c6fe 2483 return HAL_OK;
mbed_official 340:28d1f895c6fe 2484 }
mbed_official 340:28d1f895c6fe 2485
mbed_official 340:28d1f895c6fe 2486 /**
mbed_official 340:28d1f895c6fe 2487 * @brief Stops the TIM Encoder Interface in interrupt mode.
mbed_official 340:28d1f895c6fe 2488 * @param htim : TIM Encoder Interface handle
mbed_official 340:28d1f895c6fe 2489 * @param Channel : TIM Channels to be disabled
mbed_official 340:28d1f895c6fe 2490 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 2491 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 2492 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 630:825f75ca301e 2493 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 340:28d1f895c6fe 2494 * @retval HAL status
mbed_official 340:28d1f895c6fe 2495 */
mbed_official 340:28d1f895c6fe 2496 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 2497 {
mbed_official 340:28d1f895c6fe 2498 /* Check the parameters */
mbed_official 340:28d1f895c6fe 2499 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 2500
mbed_official 340:28d1f895c6fe 2501 /* Disable the Input Capture channels 1 and 2
mbed_official 630:825f75ca301e 2502 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 340:28d1f895c6fe 2503 if(Channel == TIM_CHANNEL_1)
mbed_official 340:28d1f895c6fe 2504 {
mbed_official 630:825f75ca301e 2505 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2506
mbed_official 340:28d1f895c6fe 2507 /* Disable the capture compare Interrupts 1 */
mbed_official 340:28d1f895c6fe 2508 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 630:825f75ca301e 2509 }
mbed_official 340:28d1f895c6fe 2510 else if(Channel == TIM_CHANNEL_2)
mbed_official 630:825f75ca301e 2511 {
mbed_official 630:825f75ca301e 2512 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2513
mbed_official 340:28d1f895c6fe 2514 /* Disable the capture compare Interrupts 2 */
mbed_official 340:28d1f895c6fe 2515 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 630:825f75ca301e 2516 }
mbed_official 340:28d1f895c6fe 2517 else
mbed_official 340:28d1f895c6fe 2518 {
mbed_official 630:825f75ca301e 2519 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2520 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2521
mbed_official 340:28d1f895c6fe 2522 /* Disable the capture compare Interrupts 1 and 2 */
mbed_official 340:28d1f895c6fe 2523 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 340:28d1f895c6fe 2524 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 340:28d1f895c6fe 2525 }
mbed_official 630:825f75ca301e 2526
mbed_official 340:28d1f895c6fe 2527 /* Disable the Peripheral */
mbed_official 340:28d1f895c6fe 2528 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 2529
mbed_official 340:28d1f895c6fe 2530 /* Change the htim state */
mbed_official 340:28d1f895c6fe 2531 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 2532
mbed_official 340:28d1f895c6fe 2533 /* Return function status */
mbed_official 340:28d1f895c6fe 2534 return HAL_OK;
mbed_official 340:28d1f895c6fe 2535 }
mbed_official 340:28d1f895c6fe 2536
mbed_official 340:28d1f895c6fe 2537 /**
mbed_official 340:28d1f895c6fe 2538 * @brief Starts the TIM Encoder Interface in DMA mode.
mbed_official 340:28d1f895c6fe 2539 * @param htim : TIM Encoder Interface handle
mbed_official 340:28d1f895c6fe 2540 * @param Channel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 2541 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 2542 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 2543 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 630:825f75ca301e 2544 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 340:28d1f895c6fe 2545 * @param pData1 : The destination Buffer address for IC1.
mbed_official 340:28d1f895c6fe 2546 * @param pData2 : The destination Buffer address for IC2.
mbed_official 340:28d1f895c6fe 2547 * @param Length : The length of data to be transferred from TIM peripheral to memory.
mbed_official 340:28d1f895c6fe 2548 * @retval HAL status
mbed_official 340:28d1f895c6fe 2549 */
mbed_official 340:28d1f895c6fe 2550 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
mbed_official 340:28d1f895c6fe 2551 {
mbed_official 340:28d1f895c6fe 2552 /* Check the parameters */
mbed_official 340:28d1f895c6fe 2553 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 2554
mbed_official 340:28d1f895c6fe 2555 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 340:28d1f895c6fe 2556 {
mbed_official 340:28d1f895c6fe 2557 return HAL_BUSY;
mbed_official 340:28d1f895c6fe 2558 }
mbed_official 340:28d1f895c6fe 2559 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 340:28d1f895c6fe 2560 {
mbed_official 630:825f75ca301e 2561 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
mbed_official 340:28d1f895c6fe 2562 {
mbed_official 630:825f75ca301e 2563 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 2564 }
mbed_official 340:28d1f895c6fe 2565 else
mbed_official 340:28d1f895c6fe 2566 {
mbed_official 340:28d1f895c6fe 2567 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 2568 }
mbed_official 630:825f75ca301e 2569 }
mbed_official 630:825f75ca301e 2570
mbed_official 340:28d1f895c6fe 2571 switch (Channel)
mbed_official 340:28d1f895c6fe 2572 {
mbed_official 340:28d1f895c6fe 2573 case TIM_CHANNEL_1:
mbed_official 340:28d1f895c6fe 2574 {
mbed_official 340:28d1f895c6fe 2575 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 2576 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 630:825f75ca301e 2577
mbed_official 340:28d1f895c6fe 2578 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 2579 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 2580
mbed_official 340:28d1f895c6fe 2581 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 2582 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
mbed_official 630:825f75ca301e 2583
mbed_official 630:825f75ca301e 2584 /* Enable the TIM Input Capture DMA request */
mbed_official 340:28d1f895c6fe 2585 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 630:825f75ca301e 2586
mbed_official 340:28d1f895c6fe 2587 /* Enable the Peripheral */
mbed_official 340:28d1f895c6fe 2588 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 2589
mbed_official 340:28d1f895c6fe 2590 /* Enable the Capture compare channel */
mbed_official 340:28d1f895c6fe 2591 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 340:28d1f895c6fe 2592 }
mbed_official 340:28d1f895c6fe 2593 break;
mbed_official 630:825f75ca301e 2594
mbed_official 340:28d1f895c6fe 2595 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 2596 {
mbed_official 340:28d1f895c6fe 2597 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 2598 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 630:825f75ca301e 2599
mbed_official 340:28d1f895c6fe 2600 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 2601 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
mbed_official 340:28d1f895c6fe 2602 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 2603 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official 630:825f75ca301e 2604
mbed_official 340:28d1f895c6fe 2605 /* Enable the TIM Input Capture DMA request */
mbed_official 340:28d1f895c6fe 2606 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 630:825f75ca301e 2607
mbed_official 340:28d1f895c6fe 2608 /* Enable the Peripheral */
mbed_official 340:28d1f895c6fe 2609 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 2610
mbed_official 340:28d1f895c6fe 2611 /* Enable the Capture compare channel */
mbed_official 340:28d1f895c6fe 2612 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 340:28d1f895c6fe 2613 }
mbed_official 340:28d1f895c6fe 2614 break;
mbed_official 630:825f75ca301e 2615
mbed_official 340:28d1f895c6fe 2616 case TIM_CHANNEL_ALL:
mbed_official 340:28d1f895c6fe 2617 {
mbed_official 340:28d1f895c6fe 2618 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 2619 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 630:825f75ca301e 2620
mbed_official 340:28d1f895c6fe 2621 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 2622 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 2623
mbed_official 340:28d1f895c6fe 2624 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 2625 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
mbed_official 630:825f75ca301e 2626
mbed_official 340:28d1f895c6fe 2627 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 2628 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 630:825f75ca301e 2629
mbed_official 340:28d1f895c6fe 2630 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 2631 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 2632
mbed_official 340:28d1f895c6fe 2633 /* Enable the DMA channel */
mbed_official 340:28d1f895c6fe 2634 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official 630:825f75ca301e 2635
mbed_official 340:28d1f895c6fe 2636 /* Enable the Peripheral */
mbed_official 340:28d1f895c6fe 2637 __HAL_TIM_ENABLE(htim);
mbed_official 630:825f75ca301e 2638
mbed_official 340:28d1f895c6fe 2639 /* Enable the Capture compare channel */
mbed_official 340:28d1f895c6fe 2640 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 340:28d1f895c6fe 2641 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 630:825f75ca301e 2642
mbed_official 340:28d1f895c6fe 2643 /* Enable the TIM Input Capture DMA request */
mbed_official 340:28d1f895c6fe 2644 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 340:28d1f895c6fe 2645 /* Enable the TIM Input Capture DMA request */
mbed_official 340:28d1f895c6fe 2646 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 340:28d1f895c6fe 2647 }
mbed_official 340:28d1f895c6fe 2648 break;
mbed_official 630:825f75ca301e 2649
mbed_official 340:28d1f895c6fe 2650 default:
mbed_official 340:28d1f895c6fe 2651 break;
mbed_official 630:825f75ca301e 2652 }
mbed_official 340:28d1f895c6fe 2653 /* Return function status */
mbed_official 340:28d1f895c6fe 2654 return HAL_OK;
mbed_official 340:28d1f895c6fe 2655 }
mbed_official 340:28d1f895c6fe 2656
mbed_official 340:28d1f895c6fe 2657 /**
mbed_official 340:28d1f895c6fe 2658 * @brief Stops the TIM Encoder Interface in DMA mode.
mbed_official 340:28d1f895c6fe 2659 * @param htim : TIM Encoder Interface handle
mbed_official 340:28d1f895c6fe 2660 * @param Channel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 2661 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 2662 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 2663 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 630:825f75ca301e 2664 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 340:28d1f895c6fe 2665 * @retval HAL status
mbed_official 340:28d1f895c6fe 2666 */
mbed_official 340:28d1f895c6fe 2667 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 2668 {
mbed_official 340:28d1f895c6fe 2669 /* Check the parameters */
mbed_official 340:28d1f895c6fe 2670 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 2671
mbed_official 340:28d1f895c6fe 2672 /* Disable the Input Capture channels 1 and 2
mbed_official 630:825f75ca301e 2673 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 340:28d1f895c6fe 2674 if(Channel == TIM_CHANNEL_1)
mbed_official 340:28d1f895c6fe 2675 {
mbed_official 630:825f75ca301e 2676 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2677
mbed_official 340:28d1f895c6fe 2678 /* Disable the capture compare DMA Request 1 */
mbed_official 340:28d1f895c6fe 2679 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 630:825f75ca301e 2680 }
mbed_official 340:28d1f895c6fe 2681 else if(Channel == TIM_CHANNEL_2)
mbed_official 630:825f75ca301e 2682 {
mbed_official 630:825f75ca301e 2683 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2684
mbed_official 340:28d1f895c6fe 2685 /* Disable the capture compare DMA Request 2 */
mbed_official 340:28d1f895c6fe 2686 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 630:825f75ca301e 2687 }
mbed_official 340:28d1f895c6fe 2688 else
mbed_official 340:28d1f895c6fe 2689 {
mbed_official 630:825f75ca301e 2690 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2691 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 630:825f75ca301e 2692
mbed_official 340:28d1f895c6fe 2693 /* Disable the capture compare DMA Request 1 and 2 */
mbed_official 340:28d1f895c6fe 2694 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 340:28d1f895c6fe 2695 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 340:28d1f895c6fe 2696 }
mbed_official 630:825f75ca301e 2697
mbed_official 340:28d1f895c6fe 2698 /* Disable the Peripheral */
mbed_official 340:28d1f895c6fe 2699 __HAL_TIM_DISABLE(htim);
mbed_official 630:825f75ca301e 2700
mbed_official 340:28d1f895c6fe 2701 /* Change the htim state */
mbed_official 340:28d1f895c6fe 2702 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 2703
mbed_official 340:28d1f895c6fe 2704 /* Return function status */
mbed_official 340:28d1f895c6fe 2705 return HAL_OK;
mbed_official 340:28d1f895c6fe 2706 }
mbed_official 340:28d1f895c6fe 2707
mbed_official 340:28d1f895c6fe 2708 /**
mbed_official 340:28d1f895c6fe 2709 * @}
mbed_official 340:28d1f895c6fe 2710 */
mbed_official 340:28d1f895c6fe 2711 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
mbed_official 340:28d1f895c6fe 2712 * @brief IRQ handler management
mbed_official 340:28d1f895c6fe 2713 *
mbed_official 630:825f75ca301e 2714 @verbatim
mbed_official 340:28d1f895c6fe 2715 ==============================================================================
mbed_official 340:28d1f895c6fe 2716 ##### IRQ handler management #####
mbed_official 630:825f75ca301e 2717 ==============================================================================
mbed_official 630:825f75ca301e 2718 [..]
mbed_official 340:28d1f895c6fe 2719 This section provides Timer IRQ handler function.
mbed_official 630:825f75ca301e 2720
mbed_official 340:28d1f895c6fe 2721 @endverbatim
mbed_official 340:28d1f895c6fe 2722 * @{
mbed_official 340:28d1f895c6fe 2723 */
mbed_official 340:28d1f895c6fe 2724 /**
mbed_official 340:28d1f895c6fe 2725 * @brief This function handles TIM interrupts requests.
mbed_official 340:28d1f895c6fe 2726 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 2727 * @retval None
mbed_official 340:28d1f895c6fe 2728 */
mbed_official 340:28d1f895c6fe 2729 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 2730 {
mbed_official 340:28d1f895c6fe 2731 /* Capture compare 1 event */
mbed_official 340:28d1f895c6fe 2732 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
mbed_official 340:28d1f895c6fe 2733 {
mbed_official 630:825f75ca301e 2734 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
mbed_official 340:28d1f895c6fe 2735 {
mbed_official 340:28d1f895c6fe 2736 {
mbed_official 340:28d1f895c6fe 2737 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
mbed_official 340:28d1f895c6fe 2738 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 630:825f75ca301e 2739
mbed_official 340:28d1f895c6fe 2740 /* Input capture event */
mbed_official 340:28d1f895c6fe 2741 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
mbed_official 340:28d1f895c6fe 2742 {
mbed_official 340:28d1f895c6fe 2743 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 340:28d1f895c6fe 2744 }
mbed_official 340:28d1f895c6fe 2745 /* Output compare event */
mbed_official 340:28d1f895c6fe 2746 else
mbed_official 340:28d1f895c6fe 2747 {
mbed_official 340:28d1f895c6fe 2748 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 340:28d1f895c6fe 2749 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 340:28d1f895c6fe 2750 }
mbed_official 340:28d1f895c6fe 2751 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 340:28d1f895c6fe 2752 }
mbed_official 340:28d1f895c6fe 2753 }
mbed_official 340:28d1f895c6fe 2754 }
mbed_official 340:28d1f895c6fe 2755 /* Capture compare 2 event */
mbed_official 340:28d1f895c6fe 2756 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
mbed_official 340:28d1f895c6fe 2757 {
mbed_official 630:825f75ca301e 2758 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
mbed_official 340:28d1f895c6fe 2759 {
mbed_official 340:28d1f895c6fe 2760 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
mbed_official 340:28d1f895c6fe 2761 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 340:28d1f895c6fe 2762 /* Input capture event */
mbed_official 340:28d1f895c6fe 2763 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
mbed_official 630:825f75ca301e 2764 {
mbed_official 630:825f75ca301e 2765 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 630:825f75ca301e 2766 }
mbed_official 630:825f75ca301e 2767 /* Output compare event */
mbed_official 630:825f75ca301e 2768 else
mbed_official 630:825f75ca301e 2769 {
mbed_official 630:825f75ca301e 2770 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 630:825f75ca301e 2771 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 630:825f75ca301e 2772 }
mbed_official 630:825f75ca301e 2773 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 630:825f75ca301e 2774 }
mbed_official 630:825f75ca301e 2775 }
mbed_official 630:825f75ca301e 2776 /* Capture compare 3 event */
mbed_official 630:825f75ca301e 2777 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
mbed_official 630:825f75ca301e 2778 {
mbed_official 630:825f75ca301e 2779 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
mbed_official 630:825f75ca301e 2780 {
mbed_official 630:825f75ca301e 2781 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
mbed_official 630:825f75ca301e 2782 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 630:825f75ca301e 2783 /* Input capture event */
mbed_official 630:825f75ca301e 2784 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
mbed_official 630:825f75ca301e 2785 {
mbed_official 340:28d1f895c6fe 2786 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 340:28d1f895c6fe 2787 }
mbed_official 340:28d1f895c6fe 2788 /* Output compare event */
mbed_official 340:28d1f895c6fe 2789 else
mbed_official 340:28d1f895c6fe 2790 {
mbed_official 340:28d1f895c6fe 2791 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 340:28d1f895c6fe 2792 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 340:28d1f895c6fe 2793 }
mbed_official 340:28d1f895c6fe 2794 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 340:28d1f895c6fe 2795 }
mbed_official 340:28d1f895c6fe 2796 }
mbed_official 340:28d1f895c6fe 2797 /* Capture compare 4 event */
mbed_official 340:28d1f895c6fe 2798 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
mbed_official 340:28d1f895c6fe 2799 {
mbed_official 630:825f75ca301e 2800 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
mbed_official 340:28d1f895c6fe 2801 {
mbed_official 340:28d1f895c6fe 2802 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
mbed_official 340:28d1f895c6fe 2803 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 340:28d1f895c6fe 2804 /* Input capture event */
mbed_official 340:28d1f895c6fe 2805 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
mbed_official 630:825f75ca301e 2806 {
mbed_official 340:28d1f895c6fe 2807 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 340:28d1f895c6fe 2808 }
mbed_official 340:28d1f895c6fe 2809 /* Output compare event */
mbed_official 340:28d1f895c6fe 2810 else
mbed_official 340:28d1f895c6fe 2811 {
mbed_official 340:28d1f895c6fe 2812 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 340:28d1f895c6fe 2813 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 340:28d1f895c6fe 2814 }
mbed_official 340:28d1f895c6fe 2815 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 630:825f75ca301e 2816 }
mbed_official 340:28d1f895c6fe 2817 }
mbed_official 340:28d1f895c6fe 2818 /* TIM Update event */
mbed_official 340:28d1f895c6fe 2819 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
mbed_official 340:28d1f895c6fe 2820 {
mbed_official 630:825f75ca301e 2821 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
mbed_official 630:825f75ca301e 2822 {
mbed_official 340:28d1f895c6fe 2823 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
mbed_official 340:28d1f895c6fe 2824 HAL_TIM_PeriodElapsedCallback(htim);
mbed_official 340:28d1f895c6fe 2825 }
mbed_official 340:28d1f895c6fe 2826 }
mbed_official 340:28d1f895c6fe 2827 /* TIM Break input event */
mbed_official 340:28d1f895c6fe 2828 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
mbed_official 340:28d1f895c6fe 2829 {
mbed_official 630:825f75ca301e 2830 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
mbed_official 630:825f75ca301e 2831 {
mbed_official 340:28d1f895c6fe 2832 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
mbed_official 340:28d1f895c6fe 2833 HAL_TIMEx_BreakCallback(htim);
mbed_official 340:28d1f895c6fe 2834 }
mbed_official 340:28d1f895c6fe 2835 }
mbed_official 340:28d1f895c6fe 2836 /* TIM Trigger detection event */
mbed_official 340:28d1f895c6fe 2837 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
mbed_official 340:28d1f895c6fe 2838 {
mbed_official 630:825f75ca301e 2839 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
mbed_official 630:825f75ca301e 2840 {
mbed_official 340:28d1f895c6fe 2841 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
mbed_official 340:28d1f895c6fe 2842 HAL_TIM_TriggerCallback(htim);
mbed_official 340:28d1f895c6fe 2843 }
mbed_official 340:28d1f895c6fe 2844 }
mbed_official 340:28d1f895c6fe 2845 /* TIM commutation event */
mbed_official 340:28d1f895c6fe 2846 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
mbed_official 340:28d1f895c6fe 2847 {
mbed_official 630:825f75ca301e 2848 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
mbed_official 630:825f75ca301e 2849 {
mbed_official 340:28d1f895c6fe 2850 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
mbed_official 340:28d1f895c6fe 2851 HAL_TIMEx_CommutationCallback(htim);
mbed_official 340:28d1f895c6fe 2852 }
mbed_official 340:28d1f895c6fe 2853 }
mbed_official 340:28d1f895c6fe 2854 }
mbed_official 340:28d1f895c6fe 2855
mbed_official 340:28d1f895c6fe 2856 /**
mbed_official 340:28d1f895c6fe 2857 * @}
mbed_official 340:28d1f895c6fe 2858 */
mbed_official 340:28d1f895c6fe 2859
mbed_official 340:28d1f895c6fe 2860 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
mbed_official 340:28d1f895c6fe 2861 * @brief Peripheral Control functions
mbed_official 340:28d1f895c6fe 2862 *
mbed_official 630:825f75ca301e 2863 @verbatim
mbed_official 340:28d1f895c6fe 2864 ==============================================================================
mbed_official 340:28d1f895c6fe 2865 ##### Peripheral Control functions #####
mbed_official 630:825f75ca301e 2866 ==============================================================================
mbed_official 630:825f75ca301e 2867 [..]
mbed_official 340:28d1f895c6fe 2868 This section provides functions allowing to:
mbed_official 630:825f75ca301e 2869 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
mbed_official 340:28d1f895c6fe 2870 (+) Configure External Clock source.
mbed_official 340:28d1f895c6fe 2871 (+) Configure Complementary channels, break features and dead time.
mbed_official 340:28d1f895c6fe 2872 (+) Configure Master and the Slave synchronization.
mbed_official 340:28d1f895c6fe 2873 (+) Configure the DMA Burst Mode.
mbed_official 630:825f75ca301e 2874
mbed_official 340:28d1f895c6fe 2875 @endverbatim
mbed_official 340:28d1f895c6fe 2876 * @{
mbed_official 340:28d1f895c6fe 2877 */
mbed_official 630:825f75ca301e 2878
mbed_official 340:28d1f895c6fe 2879 /**
mbed_official 340:28d1f895c6fe 2880 * @brief Initializes the TIM Output Compare Channels according to the specified
mbed_official 340:28d1f895c6fe 2881 * parameters in the TIM_OC_InitTypeDef.
mbed_official 340:28d1f895c6fe 2882 * @param htim : TIM Output Compare handle
mbed_official 340:28d1f895c6fe 2883 * @param sConfig : TIM Output Compare configuration structure
mbed_official 340:28d1f895c6fe 2884 * @param Channel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 2885 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 2886 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 2887 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 2888 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 2889 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 2890 * @retval HAL status
mbed_official 340:28d1f895c6fe 2891 */
mbed_official 340:28d1f895c6fe 2892 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 340:28d1f895c6fe 2893 {
mbed_official 340:28d1f895c6fe 2894 /* Check the parameters */
mbed_official 630:825f75ca301e 2895 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 340:28d1f895c6fe 2896 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
mbed_official 340:28d1f895c6fe 2897 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official 340:28d1f895c6fe 2898 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official 340:28d1f895c6fe 2899 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official 340:28d1f895c6fe 2900 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official 630:825f75ca301e 2901
mbed_official 340:28d1f895c6fe 2902 /* Check input state */
mbed_official 630:825f75ca301e 2903 __HAL_LOCK(htim);
mbed_official 630:825f75ca301e 2904
mbed_official 340:28d1f895c6fe 2905 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 2906
mbed_official 340:28d1f895c6fe 2907 switch (Channel)
mbed_official 340:28d1f895c6fe 2908 {
mbed_official 340:28d1f895c6fe 2909 case TIM_CHANNEL_1:
mbed_official 340:28d1f895c6fe 2910 {
mbed_official 340:28d1f895c6fe 2911 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 2912 /* Configure the TIM Channel 1 in Output Compare */
mbed_official 340:28d1f895c6fe 2913 TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official 340:28d1f895c6fe 2914 }
mbed_official 340:28d1f895c6fe 2915 break;
mbed_official 630:825f75ca301e 2916
mbed_official 340:28d1f895c6fe 2917 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 2918 {
mbed_official 340:28d1f895c6fe 2919 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 2920 /* Configure the TIM Channel 2 in Output Compare */
mbed_official 340:28d1f895c6fe 2921 TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official 340:28d1f895c6fe 2922 }
mbed_official 340:28d1f895c6fe 2923 break;
mbed_official 630:825f75ca301e 2924
mbed_official 340:28d1f895c6fe 2925 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 2926 {
mbed_official 340:28d1f895c6fe 2927 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 2928 /* Configure the TIM Channel 3 in Output Compare */
mbed_official 340:28d1f895c6fe 2929 TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official 340:28d1f895c6fe 2930 }
mbed_official 340:28d1f895c6fe 2931 break;
mbed_official 630:825f75ca301e 2932
mbed_official 340:28d1f895c6fe 2933 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 2934 {
mbed_official 340:28d1f895c6fe 2935 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 2936 /* Configure the TIM Channel 4 in Output Compare */
mbed_official 340:28d1f895c6fe 2937 TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official 340:28d1f895c6fe 2938 }
mbed_official 340:28d1f895c6fe 2939 break;
mbed_official 630:825f75ca301e 2940
mbed_official 340:28d1f895c6fe 2941 default:
mbed_official 630:825f75ca301e 2942 break;
mbed_official 340:28d1f895c6fe 2943 }
mbed_official 340:28d1f895c6fe 2944 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 2945
mbed_official 630:825f75ca301e 2946 __HAL_UNLOCK(htim);
mbed_official 630:825f75ca301e 2947
mbed_official 340:28d1f895c6fe 2948 return HAL_OK;
mbed_official 340:28d1f895c6fe 2949 }
mbed_official 340:28d1f895c6fe 2950
mbed_official 340:28d1f895c6fe 2951 /**
mbed_official 340:28d1f895c6fe 2952 * @brief Initializes the TIM Input Capture Channels according to the specified
mbed_official 340:28d1f895c6fe 2953 * parameters in the TIM_IC_InitTypeDef.
mbed_official 340:28d1f895c6fe 2954 * @param htim : TIM IC handle
mbed_official 340:28d1f895c6fe 2955 * @param sConfig : TIM Input Capture configuration structure
mbed_official 340:28d1f895c6fe 2956 * @param Channel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 2957 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 2958 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 2959 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 2960 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 2961 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 2962 * @retval HAL status
mbed_official 340:28d1f895c6fe 2963 */
mbed_official 340:28d1f895c6fe 2964 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 340:28d1f895c6fe 2965 {
mbed_official 340:28d1f895c6fe 2966 /* Check the parameters */
mbed_official 340:28d1f895c6fe 2967 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 2968 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
mbed_official 340:28d1f895c6fe 2969 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
mbed_official 340:28d1f895c6fe 2970 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
mbed_official 340:28d1f895c6fe 2971 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
mbed_official 630:825f75ca301e 2972
mbed_official 340:28d1f895c6fe 2973 __HAL_LOCK(htim);
mbed_official 630:825f75ca301e 2974
mbed_official 340:28d1f895c6fe 2975 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 2976
mbed_official 340:28d1f895c6fe 2977 if (Channel == TIM_CHANNEL_1)
mbed_official 340:28d1f895c6fe 2978 {
mbed_official 340:28d1f895c6fe 2979 /* TI1 Configuration */
mbed_official 340:28d1f895c6fe 2980 TIM_TI1_SetConfig(htim->Instance,
mbed_official 340:28d1f895c6fe 2981 sConfig->ICPolarity,
mbed_official 340:28d1f895c6fe 2982 sConfig->ICSelection,
mbed_official 340:28d1f895c6fe 2983 sConfig->ICFilter);
mbed_official 630:825f75ca301e 2984
mbed_official 340:28d1f895c6fe 2985 /* Reset the IC1PSC Bits */
mbed_official 340:28d1f895c6fe 2986 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official 340:28d1f895c6fe 2987
mbed_official 340:28d1f895c6fe 2988 /* Set the IC1PSC value */
mbed_official 340:28d1f895c6fe 2989 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
mbed_official 340:28d1f895c6fe 2990 }
mbed_official 340:28d1f895c6fe 2991 else if (Channel == TIM_CHANNEL_2)
mbed_official 340:28d1f895c6fe 2992 {
mbed_official 340:28d1f895c6fe 2993 /* TI2 Configuration */
mbed_official 340:28d1f895c6fe 2994 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 2995
mbed_official 630:825f75ca301e 2996 TIM_TI2_SetConfig(htim->Instance,
mbed_official 340:28d1f895c6fe 2997 sConfig->ICPolarity,
mbed_official 340:28d1f895c6fe 2998 sConfig->ICSelection,
mbed_official 340:28d1f895c6fe 2999 sConfig->ICFilter);
mbed_official 630:825f75ca301e 3000
mbed_official 340:28d1f895c6fe 3001 /* Reset the IC2PSC Bits */
mbed_official 340:28d1f895c6fe 3002 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official 340:28d1f895c6fe 3003
mbed_official 340:28d1f895c6fe 3004 /* Set the IC2PSC value */
mbed_official 340:28d1f895c6fe 3005 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
mbed_official 340:28d1f895c6fe 3006 }
mbed_official 340:28d1f895c6fe 3007 else if (Channel == TIM_CHANNEL_3)
mbed_official 340:28d1f895c6fe 3008 {
mbed_official 340:28d1f895c6fe 3009 /* TI3 Configuration */
mbed_official 340:28d1f895c6fe 3010 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 3011
mbed_official 630:825f75ca301e 3012 TIM_TI3_SetConfig(htim->Instance,
mbed_official 340:28d1f895c6fe 3013 sConfig->ICPolarity,
mbed_official 340:28d1f895c6fe 3014 sConfig->ICSelection,
mbed_official 340:28d1f895c6fe 3015 sConfig->ICFilter);
mbed_official 630:825f75ca301e 3016
mbed_official 340:28d1f895c6fe 3017 /* Reset the IC3PSC Bits */
mbed_official 340:28d1f895c6fe 3018 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
mbed_official 340:28d1f895c6fe 3019
mbed_official 340:28d1f895c6fe 3020 /* Set the IC3PSC value */
mbed_official 340:28d1f895c6fe 3021 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
mbed_official 340:28d1f895c6fe 3022 }
mbed_official 340:28d1f895c6fe 3023 else
mbed_official 340:28d1f895c6fe 3024 {
mbed_official 340:28d1f895c6fe 3025 /* TI4 Configuration */
mbed_official 340:28d1f895c6fe 3026 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 3027
mbed_official 630:825f75ca301e 3028 TIM_TI4_SetConfig(htim->Instance,
mbed_official 340:28d1f895c6fe 3029 sConfig->ICPolarity,
mbed_official 340:28d1f895c6fe 3030 sConfig->ICSelection,
mbed_official 340:28d1f895c6fe 3031 sConfig->ICFilter);
mbed_official 630:825f75ca301e 3032
mbed_official 340:28d1f895c6fe 3033 /* Reset the IC4PSC Bits */
mbed_official 340:28d1f895c6fe 3034 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
mbed_official 340:28d1f895c6fe 3035
mbed_official 340:28d1f895c6fe 3036 /* Set the IC4PSC value */
mbed_official 340:28d1f895c6fe 3037 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
mbed_official 340:28d1f895c6fe 3038 }
mbed_official 630:825f75ca301e 3039
mbed_official 340:28d1f895c6fe 3040 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 3041
mbed_official 340:28d1f895c6fe 3042 __HAL_UNLOCK(htim);
mbed_official 630:825f75ca301e 3043
mbed_official 630:825f75ca301e 3044 return HAL_OK;
mbed_official 340:28d1f895c6fe 3045 }
mbed_official 340:28d1f895c6fe 3046
mbed_official 340:28d1f895c6fe 3047 /**
mbed_official 340:28d1f895c6fe 3048 * @brief Initializes the TIM PWM channels according to the specified
mbed_official 340:28d1f895c6fe 3049 * parameters in the TIM_OC_InitTypeDef.
mbed_official 340:28d1f895c6fe 3050 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 3051 * @param sConfig : TIM PWM configuration structure
mbed_official 340:28d1f895c6fe 3052 * @param Channel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 3053 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 3054 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 3055 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 3056 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 3057 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 3058 * @retval HAL status
mbed_official 340:28d1f895c6fe 3059 */
mbed_official 340:28d1f895c6fe 3060 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 340:28d1f895c6fe 3061 {
mbed_official 340:28d1f895c6fe 3062 __HAL_LOCK(htim);
mbed_official 630:825f75ca301e 3063
mbed_official 630:825f75ca301e 3064 /* Check the parameters */
mbed_official 630:825f75ca301e 3065 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 340:28d1f895c6fe 3066 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
mbed_official 340:28d1f895c6fe 3067 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official 340:28d1f895c6fe 3068 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official 630:825f75ca301e 3069 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
mbed_official 340:28d1f895c6fe 3070 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official 340:28d1f895c6fe 3071 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official 630:825f75ca301e 3072
mbed_official 340:28d1f895c6fe 3073 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 3074
mbed_official 340:28d1f895c6fe 3075 switch (Channel)
mbed_official 340:28d1f895c6fe 3076 {
mbed_official 340:28d1f895c6fe 3077 case TIM_CHANNEL_1:
mbed_official 340:28d1f895c6fe 3078 {
mbed_official 340:28d1f895c6fe 3079 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 3080 /* Configure the Channel 1 in PWM mode */
mbed_official 340:28d1f895c6fe 3081 TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official 630:825f75ca301e 3082
mbed_official 340:28d1f895c6fe 3083 /* Set the Preload enable bit for channel1 */
mbed_official 340:28d1f895c6fe 3084 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
mbed_official 630:825f75ca301e 3085
mbed_official 340:28d1f895c6fe 3086 /* Configure the Output Fast mode */
mbed_official 340:28d1f895c6fe 3087 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
mbed_official 340:28d1f895c6fe 3088 htim->Instance->CCMR1 |= sConfig->OCFastMode;
mbed_official 340:28d1f895c6fe 3089 }
mbed_official 340:28d1f895c6fe 3090 break;
mbed_official 630:825f75ca301e 3091
mbed_official 340:28d1f895c6fe 3092 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 3093 {
mbed_official 340:28d1f895c6fe 3094 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 3095 /* Configure the Channel 2 in PWM mode */
mbed_official 340:28d1f895c6fe 3096 TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official 630:825f75ca301e 3097
mbed_official 340:28d1f895c6fe 3098 /* Set the Preload enable bit for channel2 */
mbed_official 340:28d1f895c6fe 3099 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
mbed_official 630:825f75ca301e 3100
mbed_official 340:28d1f895c6fe 3101 /* Configure the Output Fast mode */
mbed_official 340:28d1f895c6fe 3102 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
mbed_official 340:28d1f895c6fe 3103 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
mbed_official 340:28d1f895c6fe 3104 }
mbed_official 340:28d1f895c6fe 3105 break;
mbed_official 630:825f75ca301e 3106
mbed_official 340:28d1f895c6fe 3107 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 3108 {
mbed_official 340:28d1f895c6fe 3109 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 3110 /* Configure the Channel 3 in PWM mode */
mbed_official 340:28d1f895c6fe 3111 TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official 630:825f75ca301e 3112
mbed_official 340:28d1f895c6fe 3113 /* Set the Preload enable bit for channel3 */
mbed_official 340:28d1f895c6fe 3114 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
mbed_official 630:825f75ca301e 3115
mbed_official 340:28d1f895c6fe 3116 /* Configure the Output Fast mode */
mbed_official 340:28d1f895c6fe 3117 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
mbed_official 630:825f75ca301e 3118 htim->Instance->CCMR2 |= sConfig->OCFastMode;
mbed_official 340:28d1f895c6fe 3119 }
mbed_official 340:28d1f895c6fe 3120 break;
mbed_official 630:825f75ca301e 3121
mbed_official 340:28d1f895c6fe 3122 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 3123 {
mbed_official 340:28d1f895c6fe 3124 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 3125 /* Configure the Channel 4 in PWM mode */
mbed_official 340:28d1f895c6fe 3126 TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official 630:825f75ca301e 3127
mbed_official 340:28d1f895c6fe 3128 /* Set the Preload enable bit for channel4 */
mbed_official 340:28d1f895c6fe 3129 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
mbed_official 630:825f75ca301e 3130
mbed_official 340:28d1f895c6fe 3131 /* Configure the Output Fast mode */
mbed_official 340:28d1f895c6fe 3132 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
mbed_official 630:825f75ca301e 3133 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
mbed_official 340:28d1f895c6fe 3134 }
mbed_official 340:28d1f895c6fe 3135 break;
mbed_official 630:825f75ca301e 3136
mbed_official 340:28d1f895c6fe 3137 default:
mbed_official 630:825f75ca301e 3138 break;
mbed_official 340:28d1f895c6fe 3139 }
mbed_official 630:825f75ca301e 3140
mbed_official 340:28d1f895c6fe 3141 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 3142
mbed_official 340:28d1f895c6fe 3143 __HAL_UNLOCK(htim);
mbed_official 630:825f75ca301e 3144
mbed_official 340:28d1f895c6fe 3145 return HAL_OK;
mbed_official 340:28d1f895c6fe 3146 }
mbed_official 340:28d1f895c6fe 3147
mbed_official 340:28d1f895c6fe 3148 /**
mbed_official 340:28d1f895c6fe 3149 * @brief Initializes the TIM One Pulse Channels according to the specified
mbed_official 340:28d1f895c6fe 3150 * parameters in the TIM_OnePulse_InitTypeDef.
mbed_official 340:28d1f895c6fe 3151 * @param htim : TIM One Pulse handle
mbed_official 340:28d1f895c6fe 3152 * @param sConfig : TIM One Pulse configuration structure
mbed_official 340:28d1f895c6fe 3153 * @param OutputChannel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 3154 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 3155 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 3156 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 3157 * @param InputChannel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 3158 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 3159 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 3160 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 3161 * @retval HAL status
mbed_official 340:28d1f895c6fe 3162 */
mbed_official 340:28d1f895c6fe 3163 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
mbed_official 340:28d1f895c6fe 3164 {
mbed_official 340:28d1f895c6fe 3165 TIM_OC_InitTypeDef temp1;
mbed_official 630:825f75ca301e 3166
mbed_official 340:28d1f895c6fe 3167 /* Check the parameters */
mbed_official 340:28d1f895c6fe 3168 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
mbed_official 340:28d1f895c6fe 3169 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
mbed_official 340:28d1f895c6fe 3170
mbed_official 630:825f75ca301e 3171 if(OutputChannel != InputChannel)
mbed_official 340:28d1f895c6fe 3172 {
mbed_official 340:28d1f895c6fe 3173 __HAL_LOCK(htim);
mbed_official 630:825f75ca301e 3174
mbed_official 340:28d1f895c6fe 3175 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 3176
mbed_official 630:825f75ca301e 3177 /* Extract the Ouput compare configuration from sConfig structure */
mbed_official 340:28d1f895c6fe 3178 temp1.OCMode = sConfig->OCMode;
mbed_official 340:28d1f895c6fe 3179 temp1.Pulse = sConfig->Pulse;
mbed_official 340:28d1f895c6fe 3180 temp1.OCPolarity = sConfig->OCPolarity;
mbed_official 340:28d1f895c6fe 3181 temp1.OCNPolarity = sConfig->OCNPolarity;
mbed_official 340:28d1f895c6fe 3182 temp1.OCIdleState = sConfig->OCIdleState;
mbed_official 630:825f75ca301e 3183 temp1.OCNIdleState = sConfig->OCNIdleState;
mbed_official 630:825f75ca301e 3184
mbed_official 340:28d1f895c6fe 3185 switch (OutputChannel)
mbed_official 340:28d1f895c6fe 3186 {
mbed_official 340:28d1f895c6fe 3187 case TIM_CHANNEL_1:
mbed_official 340:28d1f895c6fe 3188 {
mbed_official 340:28d1f895c6fe 3189 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 3190
mbed_official 630:825f75ca301e 3191 TIM_OC1_SetConfig(htim->Instance, &temp1);
mbed_official 340:28d1f895c6fe 3192 }
mbed_official 340:28d1f895c6fe 3193 break;
mbed_official 340:28d1f895c6fe 3194 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 3195 {
mbed_official 340:28d1f895c6fe 3196 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 3197
mbed_official 340:28d1f895c6fe 3198 TIM_OC2_SetConfig(htim->Instance, &temp1);
mbed_official 340:28d1f895c6fe 3199 }
mbed_official 340:28d1f895c6fe 3200 break;
mbed_official 340:28d1f895c6fe 3201 default:
mbed_official 630:825f75ca301e 3202 break;
mbed_official 630:825f75ca301e 3203 }
mbed_official 340:28d1f895c6fe 3204 switch (InputChannel)
mbed_official 340:28d1f895c6fe 3205 {
mbed_official 340:28d1f895c6fe 3206 case TIM_CHANNEL_1:
mbed_official 340:28d1f895c6fe 3207 {
mbed_official 340:28d1f895c6fe 3208 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 3209
mbed_official 340:28d1f895c6fe 3210 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official 340:28d1f895c6fe 3211 sConfig->ICSelection, sConfig->ICFilter);
mbed_official 630:825f75ca301e 3212
mbed_official 340:28d1f895c6fe 3213 /* Reset the IC1PSC Bits */
mbed_official 340:28d1f895c6fe 3214 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official 340:28d1f895c6fe 3215
mbed_official 340:28d1f895c6fe 3216 /* Select the Trigger source */
mbed_official 340:28d1f895c6fe 3217 htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official 340:28d1f895c6fe 3218 htim->Instance->SMCR |= TIM_TS_TI1FP1;
mbed_official 630:825f75ca301e 3219
mbed_official 630:825f75ca301e 3220 /* Select the Slave Mode */
mbed_official 340:28d1f895c6fe 3221 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 340:28d1f895c6fe 3222 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
mbed_official 340:28d1f895c6fe 3223 }
mbed_official 340:28d1f895c6fe 3224 break;
mbed_official 340:28d1f895c6fe 3225 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 3226 {
mbed_official 340:28d1f895c6fe 3227 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 3228
mbed_official 340:28d1f895c6fe 3229 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official 340:28d1f895c6fe 3230 sConfig->ICSelection, sConfig->ICFilter);
mbed_official 630:825f75ca301e 3231
mbed_official 340:28d1f895c6fe 3232 /* Reset the IC2PSC Bits */
mbed_official 340:28d1f895c6fe 3233 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official 630:825f75ca301e 3234
mbed_official 340:28d1f895c6fe 3235 /* Select the Trigger source */
mbed_official 340:28d1f895c6fe 3236 htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official 340:28d1f895c6fe 3237 htim->Instance->SMCR |= TIM_TS_TI2FP2;
mbed_official 630:825f75ca301e 3238
mbed_official 630:825f75ca301e 3239 /* Select the Slave Mode */
mbed_official 340:28d1f895c6fe 3240 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 340:28d1f895c6fe 3241 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
mbed_official 340:28d1f895c6fe 3242 }
mbed_official 340:28d1f895c6fe 3243 break;
mbed_official 630:825f75ca301e 3244
mbed_official 340:28d1f895c6fe 3245 default:
mbed_official 630:825f75ca301e 3246 break;
mbed_official 340:28d1f895c6fe 3247 }
mbed_official 630:825f75ca301e 3248
mbed_official 340:28d1f895c6fe 3249 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 3250
mbed_official 340:28d1f895c6fe 3251 __HAL_UNLOCK(htim);
mbed_official 630:825f75ca301e 3252
mbed_official 340:28d1f895c6fe 3253 return HAL_OK;
mbed_official 630:825f75ca301e 3254 }
mbed_official 340:28d1f895c6fe 3255 else
mbed_official 340:28d1f895c6fe 3256 {
mbed_official 340:28d1f895c6fe 3257 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 3258 }
mbed_official 630:825f75ca301e 3259 }
mbed_official 340:28d1f895c6fe 3260
mbed_official 340:28d1f895c6fe 3261 /**
mbed_official 630:825f75ca301e 3262 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
mbed_official 340:28d1f895c6fe 3263 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 3264 * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
mbed_official 340:28d1f895c6fe 3265 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 3266 * @arg TIM_DMABASE_CR1
mbed_official 630:825f75ca301e 3267 * @arg TIM_DMABASE_CR2
mbed_official 630:825f75ca301e 3268 * @arg TIM_DMABASE_SMCR
mbed_official 630:825f75ca301e 3269 * @arg TIM_DMABASE_DIER
mbed_official 630:825f75ca301e 3270 * @arg TIM_DMABASE_SR
mbed_official 630:825f75ca301e 3271 * @arg TIM_DMABASE_EGR
mbed_official 630:825f75ca301e 3272 * @arg TIM_DMABASE_CCMR1
mbed_official 630:825f75ca301e 3273 * @arg TIM_DMABASE_CCMR2
mbed_official 630:825f75ca301e 3274 * @arg TIM_DMABASE_CCER
mbed_official 630:825f75ca301e 3275 * @arg TIM_DMABASE_CNT
mbed_official 630:825f75ca301e 3276 * @arg TIM_DMABASE_PSC
mbed_official 630:825f75ca301e 3277 * @arg TIM_DMABASE_ARR
mbed_official 630:825f75ca301e 3278 * @arg TIM_DMABASE_RCR
mbed_official 630:825f75ca301e 3279 * @arg TIM_DMABASE_CCR1
mbed_official 630:825f75ca301e 3280 * @arg TIM_DMABASE_CCR2
mbed_official 630:825f75ca301e 3281 * @arg TIM_DMABASE_CCR3
mbed_official 630:825f75ca301e 3282 * @arg TIM_DMABASE_CCR4
mbed_official 630:825f75ca301e 3283 * @arg TIM_DMABASE_BDTR
mbed_official 630:825f75ca301e 3284 * @arg TIM_DMABASE_DCR
mbed_official 340:28d1f895c6fe 3285 * @param BurstRequestSrc : TIM DMA Request sources
mbed_official 340:28d1f895c6fe 3286 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 3287 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official 340:28d1f895c6fe 3288 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official 340:28d1f895c6fe 3289 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official 340:28d1f895c6fe 3290 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official 340:28d1f895c6fe 3291 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official 340:28d1f895c6fe 3292 * @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official 340:28d1f895c6fe 3293 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official 340:28d1f895c6fe 3294 * @param BurstBuffer : The Buffer address.
mbed_official 340:28d1f895c6fe 3295 * @param BurstLength : DMA Burst length. This parameter can be one value
mbed_official 630:825f75ca301e 3296 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
mbed_official 340:28d1f895c6fe 3297 * @retval HAL status
mbed_official 340:28d1f895c6fe 3298 */
mbed_official 340:28d1f895c6fe 3299 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official 340:28d1f895c6fe 3300 uint32_t* BurstBuffer, uint32_t BurstLength)
mbed_official 340:28d1f895c6fe 3301 {
mbed_official 340:28d1f895c6fe 3302 /* Check the parameters */
mbed_official 340:28d1f895c6fe 3303 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 3304 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official 340:28d1f895c6fe 3305 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 340:28d1f895c6fe 3306 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official 630:825f75ca301e 3307
mbed_official 340:28d1f895c6fe 3308 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 340:28d1f895c6fe 3309 {
mbed_official 340:28d1f895c6fe 3310 return HAL_BUSY;
mbed_official 340:28d1f895c6fe 3311 }
mbed_official 340:28d1f895c6fe 3312 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 340:28d1f895c6fe 3313 {
mbed_official 630:825f75ca301e 3314 if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official 340:28d1f895c6fe 3315 {
mbed_official 630:825f75ca301e 3316 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 3317 }
mbed_official 340:28d1f895c6fe 3318 else
mbed_official 340:28d1f895c6fe 3319 {
mbed_official 340:28d1f895c6fe 3320 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 3321 }
mbed_official 340:28d1f895c6fe 3322 }
mbed_official 340:28d1f895c6fe 3323 switch(BurstRequestSrc)
mbed_official 340:28d1f895c6fe 3324 {
mbed_official 340:28d1f895c6fe 3325 case TIM_DMA_UPDATE:
mbed_official 630:825f75ca301e 3326 {
mbed_official 340:28d1f895c6fe 3327 /* Set the DMA Period elapsed callback */
mbed_official 340:28d1f895c6fe 3328 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 630:825f75ca301e 3329
mbed_official 340:28d1f895c6fe 3330 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3331 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3332
mbed_official 340:28d1f895c6fe 3333 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3334 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3335 }
mbed_official 340:28d1f895c6fe 3336 break;
mbed_official 340:28d1f895c6fe 3337 case TIM_DMA_CC1:
mbed_official 630:825f75ca301e 3338 {
mbed_official 340:28d1f895c6fe 3339 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 3340 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 630:825f75ca301e 3341
mbed_official 340:28d1f895c6fe 3342 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3343 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3344
mbed_official 340:28d1f895c6fe 3345 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3346 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3347 }
mbed_official 340:28d1f895c6fe 3348 break;
mbed_official 340:28d1f895c6fe 3349 case TIM_DMA_CC2:
mbed_official 630:825f75ca301e 3350 {
mbed_official 340:28d1f895c6fe 3351 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 3352 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 630:825f75ca301e 3353
mbed_official 340:28d1f895c6fe 3354 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3355 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3356
mbed_official 340:28d1f895c6fe 3357 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3358 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3359 }
mbed_official 340:28d1f895c6fe 3360 break;
mbed_official 340:28d1f895c6fe 3361 case TIM_DMA_CC3:
mbed_official 630:825f75ca301e 3362 {
mbed_official 340:28d1f895c6fe 3363 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 3364 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 630:825f75ca301e 3365
mbed_official 340:28d1f895c6fe 3366 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3367 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3368
mbed_official 340:28d1f895c6fe 3369 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3370 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3371 }
mbed_official 340:28d1f895c6fe 3372 break;
mbed_official 340:28d1f895c6fe 3373 case TIM_DMA_CC4:
mbed_official 630:825f75ca301e 3374 {
mbed_official 340:28d1f895c6fe 3375 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 3376 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 630:825f75ca301e 3377
mbed_official 340:28d1f895c6fe 3378 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3379 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3380
mbed_official 340:28d1f895c6fe 3381 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3382 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3383 }
mbed_official 340:28d1f895c6fe 3384 break;
mbed_official 340:28d1f895c6fe 3385 case TIM_DMA_COM:
mbed_official 630:825f75ca301e 3386 {
mbed_official 340:28d1f895c6fe 3387 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 3388 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
mbed_official 630:825f75ca301e 3389
mbed_official 340:28d1f895c6fe 3390 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3391 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3392
mbed_official 340:28d1f895c6fe 3393 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3394 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3395 }
mbed_official 340:28d1f895c6fe 3396 break;
mbed_official 340:28d1f895c6fe 3397 case TIM_DMA_TRIGGER:
mbed_official 630:825f75ca301e 3398 {
mbed_official 340:28d1f895c6fe 3399 /* Set the DMA Period elapsed callback */
mbed_official 340:28d1f895c6fe 3400 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official 630:825f75ca301e 3401
mbed_official 340:28d1f895c6fe 3402 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3403 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3404
mbed_official 340:28d1f895c6fe 3405 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3406 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3407 }
mbed_official 340:28d1f895c6fe 3408 break;
mbed_official 340:28d1f895c6fe 3409 default:
mbed_official 630:825f75ca301e 3410 break;
mbed_official 340:28d1f895c6fe 3411 }
mbed_official 340:28d1f895c6fe 3412 /* configure the DMA Burst Mode */
mbed_official 630:825f75ca301e 3413 htim->Instance->DCR = BurstBaseAddress | BurstLength;
mbed_official 630:825f75ca301e 3414
mbed_official 340:28d1f895c6fe 3415 /* Enable the TIM DMA Request */
mbed_official 630:825f75ca301e 3416 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official 630:825f75ca301e 3417
mbed_official 340:28d1f895c6fe 3418 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 3419
mbed_official 340:28d1f895c6fe 3420 /* Return function status */
mbed_official 340:28d1f895c6fe 3421 return HAL_OK;
mbed_official 340:28d1f895c6fe 3422 }
mbed_official 340:28d1f895c6fe 3423
mbed_official 340:28d1f895c6fe 3424 /**
mbed_official 340:28d1f895c6fe 3425 * @brief Stops the TIM DMA Burst mode
mbed_official 340:28d1f895c6fe 3426 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 3427 * @param BurstRequestSrc : TIM DMA Request sources to disable
mbed_official 340:28d1f895c6fe 3428 * @retval HAL status
mbed_official 340:28d1f895c6fe 3429 */
mbed_official 340:28d1f895c6fe 3430 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official 340:28d1f895c6fe 3431 {
mbed_official 340:28d1f895c6fe 3432 /* Check the parameters */
mbed_official 340:28d1f895c6fe 3433 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 630:825f75ca301e 3434
mbed_official 340:28d1f895c6fe 3435 /* Abort the DMA transfer (at least disable the DMA channel) */
mbed_official 340:28d1f895c6fe 3436 switch(BurstRequestSrc)
mbed_official 340:28d1f895c6fe 3437 {
mbed_official 340:28d1f895c6fe 3438 case TIM_DMA_UPDATE:
mbed_official 630:825f75ca301e 3439 {
mbed_official 630:825f75ca301e 3440 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
mbed_official 340:28d1f895c6fe 3441 }
mbed_official 340:28d1f895c6fe 3442 break;
mbed_official 340:28d1f895c6fe 3443 case TIM_DMA_CC1:
mbed_official 630:825f75ca301e 3444 {
mbed_official 630:825f75ca301e 3445 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
mbed_official 340:28d1f895c6fe 3446 }
mbed_official 340:28d1f895c6fe 3447 break;
mbed_official 340:28d1f895c6fe 3448 case TIM_DMA_CC2:
mbed_official 630:825f75ca301e 3449 {
mbed_official 630:825f75ca301e 3450 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
mbed_official 340:28d1f895c6fe 3451 }
mbed_official 340:28d1f895c6fe 3452 break;
mbed_official 340:28d1f895c6fe 3453 case TIM_DMA_CC3:
mbed_official 630:825f75ca301e 3454 {
mbed_official 630:825f75ca301e 3455 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
mbed_official 340:28d1f895c6fe 3456 }
mbed_official 340:28d1f895c6fe 3457 break;
mbed_official 340:28d1f895c6fe 3458 case TIM_DMA_CC4:
mbed_official 630:825f75ca301e 3459 {
mbed_official 630:825f75ca301e 3460 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
mbed_official 340:28d1f895c6fe 3461 }
mbed_official 340:28d1f895c6fe 3462 break;
mbed_official 340:28d1f895c6fe 3463 case TIM_DMA_COM:
mbed_official 630:825f75ca301e 3464 {
mbed_official 630:825f75ca301e 3465 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
mbed_official 340:28d1f895c6fe 3466 }
mbed_official 340:28d1f895c6fe 3467 break;
mbed_official 340:28d1f895c6fe 3468 case TIM_DMA_TRIGGER:
mbed_official 630:825f75ca301e 3469 {
mbed_official 630:825f75ca301e 3470 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
mbed_official 340:28d1f895c6fe 3471 }
mbed_official 340:28d1f895c6fe 3472 break;
mbed_official 340:28d1f895c6fe 3473 default:
mbed_official 630:825f75ca301e 3474 break;
mbed_official 340:28d1f895c6fe 3475 }
mbed_official 630:825f75ca301e 3476
mbed_official 340:28d1f895c6fe 3477 /* Disable the TIM Update DMA request */
mbed_official 340:28d1f895c6fe 3478 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official 630:825f75ca301e 3479
mbed_official 340:28d1f895c6fe 3480 /* Return function status */
mbed_official 630:825f75ca301e 3481 return HAL_OK;
mbed_official 340:28d1f895c6fe 3482 }
mbed_official 340:28d1f895c6fe 3483
mbed_official 340:28d1f895c6fe 3484 /**
mbed_official 340:28d1f895c6fe 3485 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
mbed_official 340:28d1f895c6fe 3486 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 3487 * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
mbed_official 340:28d1f895c6fe 3488 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 3489 * @arg TIM_DMABASE_CR1
mbed_official 630:825f75ca301e 3490 * @arg TIM_DMABASE_CR2
mbed_official 630:825f75ca301e 3491 * @arg TIM_DMABASE_SMCR
mbed_official 630:825f75ca301e 3492 * @arg TIM_DMABASE_DIER
mbed_official 630:825f75ca301e 3493 * @arg TIM_DMABASE_SR
mbed_official 630:825f75ca301e 3494 * @arg TIM_DMABASE_EGR
mbed_official 630:825f75ca301e 3495 * @arg TIM_DMABASE_CCMR1
mbed_official 630:825f75ca301e 3496 * @arg TIM_DMABASE_CCMR2
mbed_official 630:825f75ca301e 3497 * @arg TIM_DMABASE_CCER
mbed_official 630:825f75ca301e 3498 * @arg TIM_DMABASE_CNT
mbed_official 630:825f75ca301e 3499 * @arg TIM_DMABASE_PSC
mbed_official 630:825f75ca301e 3500 * @arg TIM_DMABASE_ARR
mbed_official 630:825f75ca301e 3501 * @arg TIM_DMABASE_RCR
mbed_official 630:825f75ca301e 3502 * @arg TIM_DMABASE_CCR1
mbed_official 630:825f75ca301e 3503 * @arg TIM_DMABASE_CCR2
mbed_official 630:825f75ca301e 3504 * @arg TIM_DMABASE_CCR3
mbed_official 630:825f75ca301e 3505 * @arg TIM_DMABASE_CCR4
mbed_official 630:825f75ca301e 3506 * @arg TIM_DMABASE_BDTR
mbed_official 630:825f75ca301e 3507 * @arg TIM_DMABASE_DCR
mbed_official 340:28d1f895c6fe 3508 * @param BurstRequestSrc : TIM DMA Request sources
mbed_official 340:28d1f895c6fe 3509 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 3510 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official 340:28d1f895c6fe 3511 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official 340:28d1f895c6fe 3512 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official 340:28d1f895c6fe 3513 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official 340:28d1f895c6fe 3514 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official 340:28d1f895c6fe 3515 * @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official 340:28d1f895c6fe 3516 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official 340:28d1f895c6fe 3517 * @param BurstBuffer : The Buffer address.
mbed_official 340:28d1f895c6fe 3518 * @param BurstLength : DMA Burst length. This parameter can be one value
mbed_official 630:825f75ca301e 3519 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
mbed_official 340:28d1f895c6fe 3520 * @retval HAL status
mbed_official 340:28d1f895c6fe 3521 */
mbed_official 340:28d1f895c6fe 3522 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official 340:28d1f895c6fe 3523 uint32_t *BurstBuffer, uint32_t BurstLength)
mbed_official 340:28d1f895c6fe 3524 {
mbed_official 340:28d1f895c6fe 3525 /* Check the parameters */
mbed_official 340:28d1f895c6fe 3526 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 3527 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official 340:28d1f895c6fe 3528 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 340:28d1f895c6fe 3529 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official 630:825f75ca301e 3530
mbed_official 340:28d1f895c6fe 3531 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 340:28d1f895c6fe 3532 {
mbed_official 340:28d1f895c6fe 3533 return HAL_BUSY;
mbed_official 340:28d1f895c6fe 3534 }
mbed_official 340:28d1f895c6fe 3535 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 340:28d1f895c6fe 3536 {
mbed_official 630:825f75ca301e 3537 if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official 340:28d1f895c6fe 3538 {
mbed_official 630:825f75ca301e 3539 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 3540 }
mbed_official 340:28d1f895c6fe 3541 else
mbed_official 340:28d1f895c6fe 3542 {
mbed_official 340:28d1f895c6fe 3543 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 3544 }
mbed_official 630:825f75ca301e 3545 }
mbed_official 340:28d1f895c6fe 3546 switch(BurstRequestSrc)
mbed_official 340:28d1f895c6fe 3547 {
mbed_official 340:28d1f895c6fe 3548 case TIM_DMA_UPDATE:
mbed_official 630:825f75ca301e 3549 {
mbed_official 340:28d1f895c6fe 3550 /* Set the DMA Period elapsed callback */
mbed_official 340:28d1f895c6fe 3551 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 630:825f75ca301e 3552
mbed_official 340:28d1f895c6fe 3553 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3554 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3555
mbed_official 340:28d1f895c6fe 3556 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3557 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3558 }
mbed_official 340:28d1f895c6fe 3559 break;
mbed_official 340:28d1f895c6fe 3560 case TIM_DMA_CC1:
mbed_official 630:825f75ca301e 3561 {
mbed_official 340:28d1f895c6fe 3562 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 3563 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 630:825f75ca301e 3564
mbed_official 340:28d1f895c6fe 3565 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3566 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3567
mbed_official 340:28d1f895c6fe 3568 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3569 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3570 }
mbed_official 340:28d1f895c6fe 3571 break;
mbed_official 340:28d1f895c6fe 3572 case TIM_DMA_CC2:
mbed_official 630:825f75ca301e 3573 {
mbed_official 340:28d1f895c6fe 3574 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 3575 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 630:825f75ca301e 3576
mbed_official 340:28d1f895c6fe 3577 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3578 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3579
mbed_official 340:28d1f895c6fe 3580 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3581 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3582 }
mbed_official 340:28d1f895c6fe 3583 break;
mbed_official 340:28d1f895c6fe 3584 case TIM_DMA_CC3:
mbed_official 630:825f75ca301e 3585 {
mbed_official 340:28d1f895c6fe 3586 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 3587 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 630:825f75ca301e 3588
mbed_official 340:28d1f895c6fe 3589 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3590 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3591
mbed_official 340:28d1f895c6fe 3592 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3593 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3594 }
mbed_official 340:28d1f895c6fe 3595 break;
mbed_official 340:28d1f895c6fe 3596 case TIM_DMA_CC4:
mbed_official 630:825f75ca301e 3597 {
mbed_official 340:28d1f895c6fe 3598 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 3599 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 630:825f75ca301e 3600
mbed_official 340:28d1f895c6fe 3601 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3602 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3603
mbed_official 340:28d1f895c6fe 3604 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3605 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3606 }
mbed_official 340:28d1f895c6fe 3607 break;
mbed_official 340:28d1f895c6fe 3608 case TIM_DMA_COM:
mbed_official 630:825f75ca301e 3609 {
mbed_official 340:28d1f895c6fe 3610 /* Set the DMA Period elapsed callback */
mbed_official 630:825f75ca301e 3611 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
mbed_official 630:825f75ca301e 3612
mbed_official 340:28d1f895c6fe 3613 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3614 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3615
mbed_official 340:28d1f895c6fe 3616 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3617 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3618 }
mbed_official 340:28d1f895c6fe 3619 break;
mbed_official 340:28d1f895c6fe 3620 case TIM_DMA_TRIGGER:
mbed_official 630:825f75ca301e 3621 {
mbed_official 340:28d1f895c6fe 3622 /* Set the DMA Period elapsed callback */
mbed_official 340:28d1f895c6fe 3623 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official 630:825f75ca301e 3624
mbed_official 340:28d1f895c6fe 3625 /* Set the DMA error callback */
mbed_official 630:825f75ca301e 3626 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
mbed_official 630:825f75ca301e 3627
mbed_official 340:28d1f895c6fe 3628 /* Enable the DMA channel */
mbed_official 630:825f75ca301e 3629 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 340:28d1f895c6fe 3630 }
mbed_official 340:28d1f895c6fe 3631 break;
mbed_official 340:28d1f895c6fe 3632 default:
mbed_official 630:825f75ca301e 3633 break;
mbed_official 340:28d1f895c6fe 3634 }
mbed_official 340:28d1f895c6fe 3635
mbed_official 340:28d1f895c6fe 3636 /* configure the DMA Burst Mode */
mbed_official 630:825f75ca301e 3637 htim->Instance->DCR = BurstBaseAddress | BurstLength;
mbed_official 630:825f75ca301e 3638
mbed_official 340:28d1f895c6fe 3639 /* Enable the TIM DMA Request */
mbed_official 340:28d1f895c6fe 3640 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official 630:825f75ca301e 3641
mbed_official 340:28d1f895c6fe 3642 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 3643
mbed_official 340:28d1f895c6fe 3644 /* Return function status */
mbed_official 340:28d1f895c6fe 3645 return HAL_OK;
mbed_official 340:28d1f895c6fe 3646 }
mbed_official 340:28d1f895c6fe 3647
mbed_official 340:28d1f895c6fe 3648 /**
mbed_official 340:28d1f895c6fe 3649 * @brief Stop the DMA burst reading
mbed_official 340:28d1f895c6fe 3650 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 3651 * @param BurstRequestSrc : TIM DMA Request sources to disable.
mbed_official 340:28d1f895c6fe 3652 * @retval HAL status
mbed_official 340:28d1f895c6fe 3653 */
mbed_official 340:28d1f895c6fe 3654 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official 340:28d1f895c6fe 3655 {
mbed_official 340:28d1f895c6fe 3656 /* Check the parameters */
mbed_official 340:28d1f895c6fe 3657 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 630:825f75ca301e 3658
mbed_official 340:28d1f895c6fe 3659 /* Abort the DMA transfer (at least disable the DMA channel) */
mbed_official 340:28d1f895c6fe 3660 switch(BurstRequestSrc)
mbed_official 340:28d1f895c6fe 3661 {
mbed_official 340:28d1f895c6fe 3662 case TIM_DMA_UPDATE:
mbed_official 630:825f75ca301e 3663 {
mbed_official 630:825f75ca301e 3664 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
mbed_official 340:28d1f895c6fe 3665 }
mbed_official 340:28d1f895c6fe 3666 break;
mbed_official 340:28d1f895c6fe 3667 case TIM_DMA_CC1:
mbed_official 630:825f75ca301e 3668 {
mbed_official 630:825f75ca301e 3669 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
mbed_official 340:28d1f895c6fe 3670 }
mbed_official 340:28d1f895c6fe 3671 break;
mbed_official 340:28d1f895c6fe 3672 case TIM_DMA_CC2:
mbed_official 630:825f75ca301e 3673 {
mbed_official 630:825f75ca301e 3674 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
mbed_official 340:28d1f895c6fe 3675 }
mbed_official 340:28d1f895c6fe 3676 break;
mbed_official 340:28d1f895c6fe 3677 case TIM_DMA_CC3:
mbed_official 630:825f75ca301e 3678 {
mbed_official 630:825f75ca301e 3679 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
mbed_official 340:28d1f895c6fe 3680 }
mbed_official 340:28d1f895c6fe 3681 break;
mbed_official 340:28d1f895c6fe 3682 case TIM_DMA_CC4:
mbed_official 630:825f75ca301e 3683 {
mbed_official 630:825f75ca301e 3684 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
mbed_official 340:28d1f895c6fe 3685 }
mbed_official 340:28d1f895c6fe 3686 break;
mbed_official 340:28d1f895c6fe 3687 case TIM_DMA_COM:
mbed_official 630:825f75ca301e 3688 {
mbed_official 630:825f75ca301e 3689 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
mbed_official 340:28d1f895c6fe 3690 }
mbed_official 340:28d1f895c6fe 3691 break;
mbed_official 340:28d1f895c6fe 3692 case TIM_DMA_TRIGGER:
mbed_official 630:825f75ca301e 3693 {
mbed_official 630:825f75ca301e 3694 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
mbed_official 340:28d1f895c6fe 3695 }
mbed_official 340:28d1f895c6fe 3696 break;
mbed_official 340:28d1f895c6fe 3697 default:
mbed_official 630:825f75ca301e 3698 break;
mbed_official 340:28d1f895c6fe 3699 }
mbed_official 340:28d1f895c6fe 3700
mbed_official 340:28d1f895c6fe 3701 /* Disable the TIM Update DMA request */
mbed_official 340:28d1f895c6fe 3702 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official 630:825f75ca301e 3703
mbed_official 340:28d1f895c6fe 3704 /* Return function status */
mbed_official 630:825f75ca301e 3705 return HAL_OK;
mbed_official 340:28d1f895c6fe 3706 }
mbed_official 340:28d1f895c6fe 3707
mbed_official 340:28d1f895c6fe 3708 /**
mbed_official 340:28d1f895c6fe 3709 * @brief Generate a software event
mbed_official 340:28d1f895c6fe 3710 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 3711 * @param EventSource : specifies the event source.
mbed_official 340:28d1f895c6fe 3712 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 3713 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
mbed_official 630:825f75ca301e 3714 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
mbed_official 630:825f75ca301e 3715 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
mbed_official 630:825f75ca301e 3716 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
mbed_official 630:825f75ca301e 3717 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
mbed_official 630:825f75ca301e 3718 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
mbed_official 630:825f75ca301e 3719 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
mbed_official 630:825f75ca301e 3720 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
mbed_official 630:825f75ca301e 3721 * @note TIM6 and TIM7 can only generate an update event.
mbed_official 630:825f75ca301e 3722 * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
mbed_official 340:28d1f895c6fe 3723 * @retval HAL status
mbed_official 630:825f75ca301e 3724 */
mbed_official 340:28d1f895c6fe 3725
mbed_official 340:28d1f895c6fe 3726 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
mbed_official 340:28d1f895c6fe 3727 {
mbed_official 340:28d1f895c6fe 3728 /* Check the parameters */
mbed_official 340:28d1f895c6fe 3729 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 3730 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
mbed_official 630:825f75ca301e 3731
mbed_official 340:28d1f895c6fe 3732 /* Process Locked */
mbed_official 340:28d1f895c6fe 3733 __HAL_LOCK(htim);
mbed_official 630:825f75ca301e 3734
mbed_official 340:28d1f895c6fe 3735 /* Change the TIM state */
mbed_official 340:28d1f895c6fe 3736 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 3737
mbed_official 340:28d1f895c6fe 3738 /* Set the event sources */
mbed_official 340:28d1f895c6fe 3739 htim->Instance->EGR = EventSource;
mbed_official 630:825f75ca301e 3740
mbed_official 340:28d1f895c6fe 3741 /* Change the TIM state */
mbed_official 340:28d1f895c6fe 3742 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 3743
mbed_official 340:28d1f895c6fe 3744 __HAL_UNLOCK(htim);
mbed_official 630:825f75ca301e 3745
mbed_official 340:28d1f895c6fe 3746 /* Return function status */
mbed_official 630:825f75ca301e 3747 return HAL_OK;
mbed_official 340:28d1f895c6fe 3748 }
mbed_official 340:28d1f895c6fe 3749
mbed_official 340:28d1f895c6fe 3750 /**
mbed_official 340:28d1f895c6fe 3751 * @brief Configures the OCRef clear feature
mbed_official 340:28d1f895c6fe 3752 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 3753 * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
mbed_official 630:825f75ca301e 3754 * contains the OCREF clear feature and parameters for the TIM peripheral.
mbed_official 340:28d1f895c6fe 3755 * @param Channel : specifies the TIM Channel
mbed_official 340:28d1f895c6fe 3756 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 3757 * @arg TIM_CHANNEL_1: TIM Channel 1
mbed_official 630:825f75ca301e 3758 * @arg TIM_CHANNEL_2: TIM Channel 2
mbed_official 630:825f75ca301e 3759 * @arg TIM_CHANNEL_3: TIM Channel 3
mbed_official 630:825f75ca301e 3760 * @arg TIM_CHANNEL_4: TIM Channel 4
mbed_official 340:28d1f895c6fe 3761 * @retval HAL status
mbed_official 340:28d1f895c6fe 3762 */
mbed_official 340:28d1f895c6fe 3763 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
mbed_official 340:28d1f895c6fe 3764 {
mbed_official 340:28d1f895c6fe 3765 uint32_t tmpsmcr = 0;
mbed_official 340:28d1f895c6fe 3766
mbed_official 630:825f75ca301e 3767 /* Check the parameters */
mbed_official 340:28d1f895c6fe 3768 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 3769 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
mbed_official 340:28d1f895c6fe 3770 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
mbed_official 340:28d1f895c6fe 3771 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
mbed_official 340:28d1f895c6fe 3772 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
mbed_official 630:825f75ca301e 3773
mbed_official 340:28d1f895c6fe 3774 /* Process Locked */
mbed_official 340:28d1f895c6fe 3775 __HAL_LOCK(htim);
mbed_official 630:825f75ca301e 3776
mbed_official 340:28d1f895c6fe 3777 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 3778
mbed_official 340:28d1f895c6fe 3779 switch (sClearInputConfig->ClearInputSource)
mbed_official 340:28d1f895c6fe 3780 {
mbed_official 340:28d1f895c6fe 3781 case TIM_CLEARINPUTSOURCE_NONE:
mbed_official 340:28d1f895c6fe 3782 {
mbed_official 340:28d1f895c6fe 3783 /* Clear the OCREF clear selection bit */
mbed_official 340:28d1f895c6fe 3784 tmpsmcr &= ~TIM_SMCR_OCCS;
mbed_official 630:825f75ca301e 3785
mbed_official 340:28d1f895c6fe 3786 /* Clear the ETR Bits */
mbed_official 340:28d1f895c6fe 3787 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
mbed_official 630:825f75ca301e 3788
mbed_official 340:28d1f895c6fe 3789 /* Set TIMx_SMCR */
mbed_official 340:28d1f895c6fe 3790 htim->Instance->SMCR = tmpsmcr;
mbed_official 340:28d1f895c6fe 3791 }
mbed_official 340:28d1f895c6fe 3792 break;
mbed_official 630:825f75ca301e 3793
mbed_official 340:28d1f895c6fe 3794 case TIM_CLEARINPUTSOURCE_ETR:
mbed_official 340:28d1f895c6fe 3795 {
mbed_official 340:28d1f895c6fe 3796 TIM_ETR_SetConfig(htim->Instance,
mbed_official 340:28d1f895c6fe 3797 sClearInputConfig->ClearInputPrescaler,
mbed_official 340:28d1f895c6fe 3798 sClearInputConfig->ClearInputPolarity,
mbed_official 340:28d1f895c6fe 3799 sClearInputConfig->ClearInputFilter);
mbed_official 630:825f75ca301e 3800
mbed_official 340:28d1f895c6fe 3801 /* Set the OCREF clear selection bit */
mbed_official 340:28d1f895c6fe 3802 htim->Instance->SMCR |= TIM_SMCR_OCCS;
mbed_official 340:28d1f895c6fe 3803 }
mbed_official 340:28d1f895c6fe 3804 break;
mbed_official 630:825f75ca301e 3805 default:
mbed_official 630:825f75ca301e 3806 break;
mbed_official 340:28d1f895c6fe 3807 }
mbed_official 630:825f75ca301e 3808
mbed_official 340:28d1f895c6fe 3809 switch (Channel)
mbed_official 630:825f75ca301e 3810 {
mbed_official 340:28d1f895c6fe 3811 case TIM_CHANNEL_1:
mbed_official 340:28d1f895c6fe 3812 {
mbed_official 340:28d1f895c6fe 3813 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 340:28d1f895c6fe 3814 {
mbed_official 340:28d1f895c6fe 3815 /* Enable the Ocref clear feature for Channel 1 */
mbed_official 340:28d1f895c6fe 3816 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
mbed_official 340:28d1f895c6fe 3817 }
mbed_official 340:28d1f895c6fe 3818 else
mbed_official 340:28d1f895c6fe 3819 {
mbed_official 340:28d1f895c6fe 3820 /* Disable the Ocref clear feature for Channel 1 */
mbed_official 630:825f75ca301e 3821 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
mbed_official 340:28d1f895c6fe 3822 }
mbed_official 630:825f75ca301e 3823 }
mbed_official 340:28d1f895c6fe 3824 break;
mbed_official 630:825f75ca301e 3825 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 3826 {
mbed_official 630:825f75ca301e 3827 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 3828 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 340:28d1f895c6fe 3829 {
mbed_official 340:28d1f895c6fe 3830 /* Enable the Ocref clear feature for Channel 2 */
mbed_official 340:28d1f895c6fe 3831 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
mbed_official 340:28d1f895c6fe 3832 }
mbed_official 340:28d1f895c6fe 3833 else
mbed_official 340:28d1f895c6fe 3834 {
mbed_official 340:28d1f895c6fe 3835 /* Disable the Ocref clear feature for Channel 2 */
mbed_official 630:825f75ca301e 3836 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
mbed_official 340:28d1f895c6fe 3837 }
mbed_official 630:825f75ca301e 3838 }
mbed_official 340:28d1f895c6fe 3839 break;
mbed_official 630:825f75ca301e 3840 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 3841 {
mbed_official 630:825f75ca301e 3842 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 3843 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 340:28d1f895c6fe 3844 {
mbed_official 340:28d1f895c6fe 3845 /* Enable the Ocref clear feature for Channel 3 */
mbed_official 340:28d1f895c6fe 3846 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
mbed_official 340:28d1f895c6fe 3847 }
mbed_official 340:28d1f895c6fe 3848 else
mbed_official 340:28d1f895c6fe 3849 {
mbed_official 340:28d1f895c6fe 3850 /* Disable the Ocref clear feature for Channel 3 */
mbed_official 630:825f75ca301e 3851 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
mbed_official 340:28d1f895c6fe 3852 }
mbed_official 630:825f75ca301e 3853 }
mbed_official 340:28d1f895c6fe 3854 break;
mbed_official 630:825f75ca301e 3855 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 3856 {
mbed_official 630:825f75ca301e 3857 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 3858 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 340:28d1f895c6fe 3859 {
mbed_official 340:28d1f895c6fe 3860 /* Enable the Ocref clear feature for Channel 4 */
mbed_official 340:28d1f895c6fe 3861 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
mbed_official 340:28d1f895c6fe 3862 }
mbed_official 340:28d1f895c6fe 3863 else
mbed_official 340:28d1f895c6fe 3864 {
mbed_official 340:28d1f895c6fe 3865 /* Disable the Ocref clear feature for Channel 4 */
mbed_official 630:825f75ca301e 3866 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
mbed_official 340:28d1f895c6fe 3867 }
mbed_official 630:825f75ca301e 3868 }
mbed_official 340:28d1f895c6fe 3869 break;
mbed_official 630:825f75ca301e 3870 default:
mbed_official 340:28d1f895c6fe 3871 break;
mbed_official 340:28d1f895c6fe 3872 }
mbed_official 630:825f75ca301e 3873
mbed_official 630:825f75ca301e 3874 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 3875
mbed_official 340:28d1f895c6fe 3876 __HAL_UNLOCK(htim);
mbed_official 630:825f75ca301e 3877
mbed_official 630:825f75ca301e 3878 return HAL_OK;
mbed_official 630:825f75ca301e 3879 }
mbed_official 340:28d1f895c6fe 3880
mbed_official 340:28d1f895c6fe 3881 /**
mbed_official 340:28d1f895c6fe 3882 * @brief Configures the clock source to be used
mbed_official 340:28d1f895c6fe 3883 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 3884 * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
mbed_official 630:825f75ca301e 3885 * contains the clock source information for the TIM peripheral.
mbed_official 340:28d1f895c6fe 3886 * @retval HAL status
mbed_official 340:28d1f895c6fe 3887 */
mbed_official 630:825f75ca301e 3888 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
mbed_official 340:28d1f895c6fe 3889 {
mbed_official 340:28d1f895c6fe 3890 uint32_t tmpsmcr = 0;
mbed_official 630:825f75ca301e 3891
mbed_official 340:28d1f895c6fe 3892 /* Process Locked */
mbed_official 340:28d1f895c6fe 3893 __HAL_LOCK(htim);
mbed_official 630:825f75ca301e 3894
mbed_official 340:28d1f895c6fe 3895 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 3896
mbed_official 340:28d1f895c6fe 3897 /* Check the parameters */
mbed_official 340:28d1f895c6fe 3898 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
mbed_official 340:28d1f895c6fe 3899 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official 340:28d1f895c6fe 3900 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official 340:28d1f895c6fe 3901 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official 630:825f75ca301e 3902
mbed_official 340:28d1f895c6fe 3903 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
mbed_official 340:28d1f895c6fe 3904 tmpsmcr = htim->Instance->SMCR;
mbed_official 340:28d1f895c6fe 3905 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
mbed_official 340:28d1f895c6fe 3906 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
mbed_official 340:28d1f895c6fe 3907 htim->Instance->SMCR = tmpsmcr;
mbed_official 630:825f75ca301e 3908
mbed_official 340:28d1f895c6fe 3909 switch (sClockSourceConfig->ClockSource)
mbed_official 340:28d1f895c6fe 3910 {
mbed_official 340:28d1f895c6fe 3911 case TIM_CLOCKSOURCE_INTERNAL:
mbed_official 340:28d1f895c6fe 3912 {
mbed_official 630:825f75ca301e 3913 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 3914 /* Disable slave mode to clock the prescaler directly with the internal clock */
mbed_official 340:28d1f895c6fe 3915 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 340:28d1f895c6fe 3916 }
mbed_official 340:28d1f895c6fe 3917 break;
mbed_official 630:825f75ca301e 3918
mbed_official 340:28d1f895c6fe 3919 case TIM_CLOCKSOURCE_ETRMODE1:
mbed_official 340:28d1f895c6fe 3920 {
mbed_official 340:28d1f895c6fe 3921 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
mbed_official 340:28d1f895c6fe 3922 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 3923
mbed_official 340:28d1f895c6fe 3924 /* Configure the ETR Clock source */
mbed_official 630:825f75ca301e 3925 TIM_ETR_SetConfig(htim->Instance,
mbed_official 630:825f75ca301e 3926 sClockSourceConfig->ClockPrescaler,
mbed_official 630:825f75ca301e 3927 sClockSourceConfig->ClockPolarity,
mbed_official 340:28d1f895c6fe 3928 sClockSourceConfig->ClockFilter);
mbed_official 340:28d1f895c6fe 3929 /* Get the TIMx SMCR register value */
mbed_official 340:28d1f895c6fe 3930 tmpsmcr = htim->Instance->SMCR;
mbed_official 340:28d1f895c6fe 3931 /* Reset the SMS and TS Bits */
mbed_official 340:28d1f895c6fe 3932 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
mbed_official 340:28d1f895c6fe 3933 /* Select the External clock mode1 and the ETRF trigger */
mbed_official 340:28d1f895c6fe 3934 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
mbed_official 340:28d1f895c6fe 3935 /* Write to TIMx SMCR */
mbed_official 340:28d1f895c6fe 3936 htim->Instance->SMCR = tmpsmcr;
mbed_official 340:28d1f895c6fe 3937 }
mbed_official 340:28d1f895c6fe 3938 break;
mbed_official 630:825f75ca301e 3939
mbed_official 340:28d1f895c6fe 3940 case TIM_CLOCKSOURCE_ETRMODE2:
mbed_official 340:28d1f895c6fe 3941 {
mbed_official 340:28d1f895c6fe 3942 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
mbed_official 340:28d1f895c6fe 3943 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 3944
mbed_official 340:28d1f895c6fe 3945 /* Configure the ETR Clock source */
mbed_official 630:825f75ca301e 3946 TIM_ETR_SetConfig(htim->Instance,
mbed_official 630:825f75ca301e 3947 sClockSourceConfig->ClockPrescaler,
mbed_official 340:28d1f895c6fe 3948 sClockSourceConfig->ClockPolarity,
mbed_official 340:28d1f895c6fe 3949 sClockSourceConfig->ClockFilter);
mbed_official 340:28d1f895c6fe 3950 /* Enable the External clock mode2 */
mbed_official 340:28d1f895c6fe 3951 htim->Instance->SMCR |= TIM_SMCR_ECE;
mbed_official 340:28d1f895c6fe 3952 }
mbed_official 340:28d1f895c6fe 3953 break;
mbed_official 630:825f75ca301e 3954
mbed_official 340:28d1f895c6fe 3955 case TIM_CLOCKSOURCE_TI1:
mbed_official 340:28d1f895c6fe 3956 {
mbed_official 340:28d1f895c6fe 3957 /* Check whether or not the timer instance supports external clock mode 1 */
mbed_official 340:28d1f895c6fe 3958 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 3959
mbed_official 630:825f75ca301e 3960 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 630:825f75ca301e 3961 sClockSourceConfig->ClockPolarity,
mbed_official 340:28d1f895c6fe 3962 sClockSourceConfig->ClockFilter);
mbed_official 340:28d1f895c6fe 3963 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
mbed_official 340:28d1f895c6fe 3964 }
mbed_official 340:28d1f895c6fe 3965 break;
mbed_official 340:28d1f895c6fe 3966 case TIM_CLOCKSOURCE_TI2:
mbed_official 340:28d1f895c6fe 3967 {
mbed_official 340:28d1f895c6fe 3968 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
mbed_official 340:28d1f895c6fe 3969 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 3970
mbed_official 630:825f75ca301e 3971 TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official 630:825f75ca301e 3972 sClockSourceConfig->ClockPolarity,
mbed_official 340:28d1f895c6fe 3973 sClockSourceConfig->ClockFilter);
mbed_official 340:28d1f895c6fe 3974 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
mbed_official 340:28d1f895c6fe 3975 }
mbed_official 340:28d1f895c6fe 3976 break;
mbed_official 340:28d1f895c6fe 3977 case TIM_CLOCKSOURCE_TI1ED:
mbed_official 340:28d1f895c6fe 3978 {
mbed_official 340:28d1f895c6fe 3979 /* Check whether or not the timer instance supports external clock mode 1 */
mbed_official 340:28d1f895c6fe 3980 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 3981
mbed_official 630:825f75ca301e 3982 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 340:28d1f895c6fe 3983 sClockSourceConfig->ClockPolarity,
mbed_official 340:28d1f895c6fe 3984 sClockSourceConfig->ClockFilter);
mbed_official 340:28d1f895c6fe 3985 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
mbed_official 340:28d1f895c6fe 3986 }
mbed_official 340:28d1f895c6fe 3987 break;
mbed_official 340:28d1f895c6fe 3988 case TIM_CLOCKSOURCE_ITR0:
mbed_official 340:28d1f895c6fe 3989 {
mbed_official 340:28d1f895c6fe 3990 /* Check whether or not the timer instance supports external clock mode 1 */
mbed_official 340:28d1f895c6fe 3991 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 3992
mbed_official 340:28d1f895c6fe 3993 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
mbed_official 340:28d1f895c6fe 3994 }
mbed_official 340:28d1f895c6fe 3995 break;
mbed_official 340:28d1f895c6fe 3996 case TIM_CLOCKSOURCE_ITR1:
mbed_official 340:28d1f895c6fe 3997 {
mbed_official 340:28d1f895c6fe 3998 /* Check whether or not the timer instance supports external clock mode 1 */
mbed_official 340:28d1f895c6fe 3999 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 4000
mbed_official 340:28d1f895c6fe 4001 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
mbed_official 340:28d1f895c6fe 4002 }
mbed_official 340:28d1f895c6fe 4003 break;
mbed_official 340:28d1f895c6fe 4004 case TIM_CLOCKSOURCE_ITR2:
mbed_official 340:28d1f895c6fe 4005 {
mbed_official 340:28d1f895c6fe 4006 /* Check whether or not the timer instance supports external clock mode 1 */
mbed_official 340:28d1f895c6fe 4007 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 4008
mbed_official 340:28d1f895c6fe 4009 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
mbed_official 340:28d1f895c6fe 4010 }
mbed_official 340:28d1f895c6fe 4011 break;
mbed_official 340:28d1f895c6fe 4012 case TIM_CLOCKSOURCE_ITR3:
mbed_official 340:28d1f895c6fe 4013 {
mbed_official 340:28d1f895c6fe 4014 /* Check whether or not the timer instance supports external clock mode 1 */
mbed_official 340:28d1f895c6fe 4015 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 4016
mbed_official 340:28d1f895c6fe 4017 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
mbed_official 340:28d1f895c6fe 4018 }
mbed_official 340:28d1f895c6fe 4019 break;
mbed_official 630:825f75ca301e 4020
mbed_official 340:28d1f895c6fe 4021 default:
mbed_official 630:825f75ca301e 4022 break;
mbed_official 340:28d1f895c6fe 4023 }
mbed_official 340:28d1f895c6fe 4024 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 4025
mbed_official 340:28d1f895c6fe 4026 __HAL_UNLOCK(htim);
mbed_official 630:825f75ca301e 4027
mbed_official 340:28d1f895c6fe 4028 return HAL_OK;
mbed_official 340:28d1f895c6fe 4029 }
mbed_official 340:28d1f895c6fe 4030
mbed_official 340:28d1f895c6fe 4031 /**
mbed_official 340:28d1f895c6fe 4032 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
mbed_official 340:28d1f895c6fe 4033 * or a XOR combination between CH1_input, CH2_input & CH3_input
mbed_official 340:28d1f895c6fe 4034 * @param htim : TIM handle.
mbed_official 340:28d1f895c6fe 4035 * @param TI1_Selection : Indicate whether or not channel 1 is connected to the
mbed_official 340:28d1f895c6fe 4036 * output of a XOR gate.
mbed_official 340:28d1f895c6fe 4037 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 4038 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
mbed_official 340:28d1f895c6fe 4039 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
mbed_official 340:28d1f895c6fe 4040 * pins are connected to the TI1 input (XOR combination)
mbed_official 340:28d1f895c6fe 4041 * @retval HAL status
mbed_official 340:28d1f895c6fe 4042 */
mbed_official 340:28d1f895c6fe 4043 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
mbed_official 340:28d1f895c6fe 4044 {
mbed_official 340:28d1f895c6fe 4045 uint32_t tmpcr2 = 0;
mbed_official 630:825f75ca301e 4046
mbed_official 340:28d1f895c6fe 4047 /* Check the parameters */
mbed_official 630:825f75ca301e 4048 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 4049 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
mbed_official 340:28d1f895c6fe 4050
mbed_official 340:28d1f895c6fe 4051 /* Get the TIMx CR2 register value */
mbed_official 340:28d1f895c6fe 4052 tmpcr2 = htim->Instance->CR2;
mbed_official 340:28d1f895c6fe 4053
mbed_official 340:28d1f895c6fe 4054 /* Reset the TI1 selection */
mbed_official 340:28d1f895c6fe 4055 tmpcr2 &= ~TIM_CR2_TI1S;
mbed_official 340:28d1f895c6fe 4056
mbed_official 340:28d1f895c6fe 4057 /* Set the the TI1 selection */
mbed_official 340:28d1f895c6fe 4058 tmpcr2 |= TI1_Selection;
mbed_official 630:825f75ca301e 4059
mbed_official 340:28d1f895c6fe 4060 /* Write to TIMxCR2 */
mbed_official 340:28d1f895c6fe 4061 htim->Instance->CR2 = tmpcr2;
mbed_official 340:28d1f895c6fe 4062
mbed_official 340:28d1f895c6fe 4063 return HAL_OK;
mbed_official 340:28d1f895c6fe 4064 }
mbed_official 340:28d1f895c6fe 4065
mbed_official 340:28d1f895c6fe 4066 /**
mbed_official 340:28d1f895c6fe 4067 * @brief Configures the TIM in Slave mode
mbed_official 340:28d1f895c6fe 4068 * @param htim : TIM handle.
mbed_official 340:28d1f895c6fe 4069 * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official 340:28d1f895c6fe 4070 * contains the selected trigger (internal trigger input, filtered
mbed_official 340:28d1f895c6fe 4071 * timer input or external trigger input) and the ) and the Slave
mbed_official 630:825f75ca301e 4072 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official 340:28d1f895c6fe 4073 * @retval HAL status
mbed_official 340:28d1f895c6fe 4074 */
mbed_official 340:28d1f895c6fe 4075 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official 340:28d1f895c6fe 4076 {
mbed_official 340:28d1f895c6fe 4077 /* Check the parameters */
mbed_official 340:28d1f895c6fe 4078 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 4079 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
mbed_official 340:28d1f895c6fe 4080 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
mbed_official 630:825f75ca301e 4081
mbed_official 340:28d1f895c6fe 4082 __HAL_LOCK(htim);
mbed_official 340:28d1f895c6fe 4083
mbed_official 340:28d1f895c6fe 4084 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 4085
mbed_official 340:28d1f895c6fe 4086 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
mbed_official 630:825f75ca301e 4087
mbed_official 340:28d1f895c6fe 4088 /* Disable Trigger Interrupt */
mbed_official 340:28d1f895c6fe 4089 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
mbed_official 630:825f75ca301e 4090
mbed_official 340:28d1f895c6fe 4091 /* Disable Trigger DMA request */
mbed_official 340:28d1f895c6fe 4092 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
mbed_official 630:825f75ca301e 4093
mbed_official 340:28d1f895c6fe 4094 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 4095
mbed_official 630:825f75ca301e 4096 __HAL_UNLOCK(htim);
mbed_official 630:825f75ca301e 4097
mbed_official 340:28d1f895c6fe 4098 return HAL_OK;
mbed_official 340:28d1f895c6fe 4099 }
mbed_official 630:825f75ca301e 4100
mbed_official 340:28d1f895c6fe 4101 /**
mbed_official 340:28d1f895c6fe 4102 * @brief Configures the TIM in Slave mode in interrupt mode
mbed_official 340:28d1f895c6fe 4103 * @param htim: TIM handle.
mbed_official 340:28d1f895c6fe 4104 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official 340:28d1f895c6fe 4105 * contains the selected trigger (internal trigger input, filtered
mbed_official 340:28d1f895c6fe 4106 * timer input or external trigger input) and the ) and the Slave
mbed_official 630:825f75ca301e 4107 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official 340:28d1f895c6fe 4108 * @retval HAL status
mbed_official 340:28d1f895c6fe 4109 */
mbed_official 630:825f75ca301e 4110 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
mbed_official 340:28d1f895c6fe 4111 TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official 340:28d1f895c6fe 4112 {
mbed_official 340:28d1f895c6fe 4113 /* Check the parameters */
mbed_official 340:28d1f895c6fe 4114 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 4115 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
mbed_official 340:28d1f895c6fe 4116 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
mbed_official 630:825f75ca301e 4117
mbed_official 340:28d1f895c6fe 4118 __HAL_LOCK(htim);
mbed_official 630:825f75ca301e 4119
mbed_official 340:28d1f895c6fe 4120 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 630:825f75ca301e 4121
mbed_official 340:28d1f895c6fe 4122 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
mbed_official 630:825f75ca301e 4123
mbed_official 340:28d1f895c6fe 4124 /* Enable Trigger Interrupt */
mbed_official 340:28d1f895c6fe 4125 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
mbed_official 630:825f75ca301e 4126
mbed_official 340:28d1f895c6fe 4127 /* Disable Trigger DMA request */
mbed_official 340:28d1f895c6fe 4128 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
mbed_official 630:825f75ca301e 4129
mbed_official 340:28d1f895c6fe 4130 htim->State = HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 4131
mbed_official 630:825f75ca301e 4132 __HAL_UNLOCK(htim);
mbed_official 630:825f75ca301e 4133
mbed_official 340:28d1f895c6fe 4134 return HAL_OK;
mbed_official 630:825f75ca301e 4135 }
mbed_official 340:28d1f895c6fe 4136
mbed_official 340:28d1f895c6fe 4137 /**
mbed_official 340:28d1f895c6fe 4138 * @brief Read the captured value from Capture Compare unit
mbed_official 340:28d1f895c6fe 4139 * @param htim : TIM handle.
mbed_official 340:28d1f895c6fe 4140 * @param Channel : TIM Channels to be enabled
mbed_official 340:28d1f895c6fe 4141 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 4142 * @arg TIM_CHANNEL_1 : TIM Channel 1 selected
mbed_official 340:28d1f895c6fe 4143 * @arg TIM_CHANNEL_2 : TIM Channel 2 selected
mbed_official 340:28d1f895c6fe 4144 * @arg TIM_CHANNEL_3 : TIM Channel 3 selected
mbed_official 340:28d1f895c6fe 4145 * @arg TIM_CHANNEL_4 : TIM Channel 4 selected
mbed_official 340:28d1f895c6fe 4146 * @retval Captured value
mbed_official 340:28d1f895c6fe 4147 */
mbed_official 340:28d1f895c6fe 4148 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 340:28d1f895c6fe 4149 {
mbed_official 340:28d1f895c6fe 4150 uint32_t tmpreg = 0;
mbed_official 630:825f75ca301e 4151
mbed_official 340:28d1f895c6fe 4152 __HAL_LOCK(htim);
mbed_official 630:825f75ca301e 4153
mbed_official 340:28d1f895c6fe 4154 switch (Channel)
mbed_official 340:28d1f895c6fe 4155 {
mbed_official 340:28d1f895c6fe 4156 case TIM_CHANNEL_1:
mbed_official 340:28d1f895c6fe 4157 {
mbed_official 340:28d1f895c6fe 4158 /* Check the parameters */
mbed_official 340:28d1f895c6fe 4159 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 4160
mbed_official 340:28d1f895c6fe 4161 /* Return the capture 1 value */
mbed_official 340:28d1f895c6fe 4162 tmpreg = htim->Instance->CCR1;
mbed_official 630:825f75ca301e 4163
mbed_official 340:28d1f895c6fe 4164 break;
mbed_official 340:28d1f895c6fe 4165 }
mbed_official 340:28d1f895c6fe 4166 case TIM_CHANNEL_2:
mbed_official 340:28d1f895c6fe 4167 {
mbed_official 340:28d1f895c6fe 4168 /* Check the parameters */
mbed_official 340:28d1f895c6fe 4169 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 4170
mbed_official 340:28d1f895c6fe 4171 /* Return the capture 2 value */
mbed_official 340:28d1f895c6fe 4172 tmpreg = htim->Instance->CCR2;
mbed_official 630:825f75ca301e 4173
mbed_official 340:28d1f895c6fe 4174 break;
mbed_official 340:28d1f895c6fe 4175 }
mbed_official 630:825f75ca301e 4176
mbed_official 340:28d1f895c6fe 4177 case TIM_CHANNEL_3:
mbed_official 340:28d1f895c6fe 4178 {
mbed_official 340:28d1f895c6fe 4179 /* Check the parameters */
mbed_official 340:28d1f895c6fe 4180 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 4181
mbed_official 340:28d1f895c6fe 4182 /* Return the capture 3 value */
mbed_official 340:28d1f895c6fe 4183 tmpreg = htim->Instance->CCR3;
mbed_official 630:825f75ca301e 4184
mbed_official 340:28d1f895c6fe 4185 break;
mbed_official 340:28d1f895c6fe 4186 }
mbed_official 630:825f75ca301e 4187
mbed_official 340:28d1f895c6fe 4188 case TIM_CHANNEL_4:
mbed_official 340:28d1f895c6fe 4189 {
mbed_official 340:28d1f895c6fe 4190 /* Check the parameters */
mbed_official 340:28d1f895c6fe 4191 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 630:825f75ca301e 4192
mbed_official 340:28d1f895c6fe 4193 /* Return the capture 4 value */
mbed_official 340:28d1f895c6fe 4194 tmpreg = htim->Instance->CCR4;
mbed_official 630:825f75ca301e 4195
mbed_official 340:28d1f895c6fe 4196 break;
mbed_official 340:28d1f895c6fe 4197 }
mbed_official 630:825f75ca301e 4198
mbed_official 340:28d1f895c6fe 4199 default:
mbed_official 630:825f75ca301e 4200 break;
mbed_official 340:28d1f895c6fe 4201 }
mbed_official 630:825f75ca301e 4202
mbed_official 630:825f75ca301e 4203 __HAL_UNLOCK(htim);
mbed_official 340:28d1f895c6fe 4204 return tmpreg;
mbed_official 340:28d1f895c6fe 4205 }
mbed_official 340:28d1f895c6fe 4206
mbed_official 340:28d1f895c6fe 4207 /**
mbed_official 340:28d1f895c6fe 4208 * @}
mbed_official 340:28d1f895c6fe 4209 */
mbed_official 630:825f75ca301e 4210
mbed_official 340:28d1f895c6fe 4211 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
mbed_official 340:28d1f895c6fe 4212 * @brief TIM Callbacks functions
mbed_official 340:28d1f895c6fe 4213 *
mbed_official 630:825f75ca301e 4214 @verbatim
mbed_official 340:28d1f895c6fe 4215 ==============================================================================
mbed_official 340:28d1f895c6fe 4216 ##### TIM Callbacks functions #####
mbed_official 630:825f75ca301e 4217 ==============================================================================
mbed_official 630:825f75ca301e 4218 [..]
mbed_official 340:28d1f895c6fe 4219 This section provides TIM callback functions:
mbed_official 340:28d1f895c6fe 4220 (+) Timer Period elapsed callback
mbed_official 340:28d1f895c6fe 4221 (+) Timer Output Compare callback
mbed_official 340:28d1f895c6fe 4222 (+) Timer Input capture callback
mbed_official 340:28d1f895c6fe 4223 (+) Timer Trigger callback
mbed_official 340:28d1f895c6fe 4224 (+) Timer Error callback
mbed_official 340:28d1f895c6fe 4225
mbed_official 340:28d1f895c6fe 4226 @endverbatim
mbed_official 340:28d1f895c6fe 4227 * @{
mbed_official 340:28d1f895c6fe 4228 */
mbed_official 340:28d1f895c6fe 4229
mbed_official 340:28d1f895c6fe 4230 /**
mbed_official 340:28d1f895c6fe 4231 * @brief Period elapsed callback in non blocking mode
mbed_official 340:28d1f895c6fe 4232 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 4233 * @retval None
mbed_official 340:28d1f895c6fe 4234 */
mbed_official 340:28d1f895c6fe 4235 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 4236 {
mbed_official 340:28d1f895c6fe 4237 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 4238 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
mbed_official 340:28d1f895c6fe 4239 */
mbed_official 630:825f75ca301e 4240
mbed_official 340:28d1f895c6fe 4241 }
mbed_official 340:28d1f895c6fe 4242 /**
mbed_official 340:28d1f895c6fe 4243 * @brief Output Compare callback in non blocking mode
mbed_official 340:28d1f895c6fe 4244 * @param htim : TIM OC handle
mbed_official 340:28d1f895c6fe 4245 * @retval None
mbed_official 340:28d1f895c6fe 4246 */
mbed_official 340:28d1f895c6fe 4247 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 4248 {
mbed_official 340:28d1f895c6fe 4249 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 4250 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
mbed_official 340:28d1f895c6fe 4251 */
mbed_official 340:28d1f895c6fe 4252 }
mbed_official 340:28d1f895c6fe 4253 /**
mbed_official 340:28d1f895c6fe 4254 * @brief Input Capture callback in non blocking mode
mbed_official 340:28d1f895c6fe 4255 * @param htim : TIM IC handle
mbed_official 340:28d1f895c6fe 4256 * @retval None
mbed_official 340:28d1f895c6fe 4257 */
mbed_official 340:28d1f895c6fe 4258 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 4259 {
mbed_official 340:28d1f895c6fe 4260 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 4261 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
mbed_official 340:28d1f895c6fe 4262 */
mbed_official 340:28d1f895c6fe 4263 }
mbed_official 340:28d1f895c6fe 4264
mbed_official 340:28d1f895c6fe 4265 /**
mbed_official 340:28d1f895c6fe 4266 * @brief PWM Pulse finished callback in non blocking mode
mbed_official 340:28d1f895c6fe 4267 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 4268 * @retval None
mbed_official 340:28d1f895c6fe 4269 */
mbed_official 340:28d1f895c6fe 4270 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 4271 {
mbed_official 340:28d1f895c6fe 4272 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 4273 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
mbed_official 340:28d1f895c6fe 4274 */
mbed_official 340:28d1f895c6fe 4275 }
mbed_official 340:28d1f895c6fe 4276
mbed_official 340:28d1f895c6fe 4277 /**
mbed_official 340:28d1f895c6fe 4278 * @brief Hall Trigger detection callback in non blocking mode
mbed_official 340:28d1f895c6fe 4279 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 4280 * @retval None
mbed_official 340:28d1f895c6fe 4281 */
mbed_official 340:28d1f895c6fe 4282 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 4283 {
mbed_official 340:28d1f895c6fe 4284 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 4285 the HAL_TIM_TriggerCallback could be implemented in the user file
mbed_official 340:28d1f895c6fe 4286 */
mbed_official 340:28d1f895c6fe 4287 }
mbed_official 340:28d1f895c6fe 4288
mbed_official 340:28d1f895c6fe 4289 /**
mbed_official 340:28d1f895c6fe 4290 * @brief Timer error callback in non blocking mode
mbed_official 340:28d1f895c6fe 4291 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 4292 * @retval None
mbed_official 340:28d1f895c6fe 4293 */
mbed_official 340:28d1f895c6fe 4294 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 4295 {
mbed_official 340:28d1f895c6fe 4296 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 4297 the HAL_TIM_ErrorCallback could be implemented in the user file
mbed_official 340:28d1f895c6fe 4298 */
mbed_official 340:28d1f895c6fe 4299 }
mbed_official 340:28d1f895c6fe 4300
mbed_official 340:28d1f895c6fe 4301 /**
mbed_official 340:28d1f895c6fe 4302 * @}
mbed_official 340:28d1f895c6fe 4303 */
mbed_official 340:28d1f895c6fe 4304
mbed_official 340:28d1f895c6fe 4305 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
mbed_official 340:28d1f895c6fe 4306 * @brief Peripheral State functions
mbed_official 340:28d1f895c6fe 4307 *
mbed_official 630:825f75ca301e 4308 @verbatim
mbed_official 340:28d1f895c6fe 4309 ==============================================================================
mbed_official 340:28d1f895c6fe 4310 ##### Peripheral State functions #####
mbed_official 630:825f75ca301e 4311 ==============================================================================
mbed_official 340:28d1f895c6fe 4312 [..]
mbed_official 340:28d1f895c6fe 4313 This subsection permit to get in run-time the status of the peripheral
mbed_official 340:28d1f895c6fe 4314 and the data flow.
mbed_official 340:28d1f895c6fe 4315
mbed_official 340:28d1f895c6fe 4316 @endverbatim
mbed_official 340:28d1f895c6fe 4317 * @{
mbed_official 340:28d1f895c6fe 4318 */
mbed_official 340:28d1f895c6fe 4319
mbed_official 340:28d1f895c6fe 4320 /**
mbed_official 340:28d1f895c6fe 4321 * @brief Return the TIM Base state
mbed_official 340:28d1f895c6fe 4322 * @param htim : TIM Base handle
mbed_official 340:28d1f895c6fe 4323 * @retval HAL state
mbed_official 340:28d1f895c6fe 4324 */
mbed_official 340:28d1f895c6fe 4325 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 4326 {
mbed_official 340:28d1f895c6fe 4327 return htim->State;
mbed_official 340:28d1f895c6fe 4328 }
mbed_official 340:28d1f895c6fe 4329
mbed_official 340:28d1f895c6fe 4330 /**
mbed_official 340:28d1f895c6fe 4331 * @brief Return the TIM OC state
mbed_official 340:28d1f895c6fe 4332 * @param htim : TIM Ouput Compare handle
mbed_official 340:28d1f895c6fe 4333 * @retval HAL state
mbed_official 340:28d1f895c6fe 4334 */
mbed_official 340:28d1f895c6fe 4335 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 4336 {
mbed_official 340:28d1f895c6fe 4337 return htim->State;
mbed_official 340:28d1f895c6fe 4338 }
mbed_official 340:28d1f895c6fe 4339
mbed_official 340:28d1f895c6fe 4340 /**
mbed_official 340:28d1f895c6fe 4341 * @brief Return the TIM PWM state
mbed_official 340:28d1f895c6fe 4342 * @param htim : TIM handle
mbed_official 340:28d1f895c6fe 4343 * @retval HAL state
mbed_official 340:28d1f895c6fe 4344 */
mbed_official 340:28d1f895c6fe 4345 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 4346 {
mbed_official 340:28d1f895c6fe 4347 return htim->State;
mbed_official 340:28d1f895c6fe 4348 }
mbed_official 340:28d1f895c6fe 4349
mbed_official 340:28d1f895c6fe 4350 /**
mbed_official 340:28d1f895c6fe 4351 * @brief Return the TIM Input Capture state
mbed_official 340:28d1f895c6fe 4352 * @param htim : TIM IC handle
mbed_official 340:28d1f895c6fe 4353 * @retval HAL state
mbed_official 340:28d1f895c6fe 4354 */
mbed_official 340:28d1f895c6fe 4355 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 4356 {
mbed_official 340:28d1f895c6fe 4357 return htim->State;
mbed_official 340:28d1f895c6fe 4358 }
mbed_official 340:28d1f895c6fe 4359
mbed_official 340:28d1f895c6fe 4360 /**
mbed_official 340:28d1f895c6fe 4361 * @brief Return the TIM One Pulse Mode state
mbed_official 340:28d1f895c6fe 4362 * @param htim : TIM OPM handle
mbed_official 340:28d1f895c6fe 4363 * @retval HAL state
mbed_official 340:28d1f895c6fe 4364 */
mbed_official 340:28d1f895c6fe 4365 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 4366 {
mbed_official 340:28d1f895c6fe 4367 return htim->State;
mbed_official 340:28d1f895c6fe 4368 }
mbed_official 340:28d1f895c6fe 4369
mbed_official 340:28d1f895c6fe 4370 /**
mbed_official 340:28d1f895c6fe 4371 * @brief Return the TIM Encoder Mode state
mbed_official 340:28d1f895c6fe 4372 * @param htim : TIM Encoder handle
mbed_official 340:28d1f895c6fe 4373 * @retval HAL state
mbed_official 340:28d1f895c6fe 4374 */
mbed_official 340:28d1f895c6fe 4375 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
mbed_official 340:28d1f895c6fe 4376 {
mbed_official 340:28d1f895c6fe 4377 return htim->State;
mbed_official 340:28d1f895c6fe 4378 }
mbed_official 340:28d1f895c6fe 4379
mbed_official 340:28d1f895c6fe 4380 /**
mbed_official 340:28d1f895c6fe 4381 * @}
mbed_official 340:28d1f895c6fe 4382 */
mbed_official 340:28d1f895c6fe 4383
mbed_official 340:28d1f895c6fe 4384 /**
mbed_official 340:28d1f895c6fe 4385 * @}
mbed_official 630:825f75ca301e 4386 */
mbed_official 340:28d1f895c6fe 4387
mbed_official 340:28d1f895c6fe 4388 /** @addtogroup TIM_Private_Functions TIM_Private_Functions
mbed_official 340:28d1f895c6fe 4389 * @{
mbed_official 630:825f75ca301e 4390 */
mbed_official 630:825f75ca301e 4391
mbed_official 340:28d1f895c6fe 4392 /**
mbed_official 340:28d1f895c6fe 4393 * @brief TIM DMA error callback
mbed_official 340:28d1f895c6fe 4394 * @param hdma : pointer to DMA handle.
mbed_official 340:28d1f895c6fe 4395 * @retval None
mbed_official 340:28d1f895c6fe 4396 */
mbed_official 630:825f75ca301e 4397 void TIM_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 340:28d1f895c6fe 4398 {
mbed_official 340:28d1f895c6fe 4399 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 630:825f75ca301e 4400
mbed_official 340:28d1f895c6fe 4401 htim->State= HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 4402
mbed_official 340:28d1f895c6fe 4403 HAL_TIM_ErrorCallback(htim);
mbed_official 340:28d1f895c6fe 4404 }
mbed_official 340:28d1f895c6fe 4405
mbed_official 340:28d1f895c6fe 4406 /**
mbed_official 630:825f75ca301e 4407 * @brief TIM DMA Delay Pulse complete callback.
mbed_official 340:28d1f895c6fe 4408 * @param hdma : pointer to DMA handle.
mbed_official 340:28d1f895c6fe 4409 * @retval None
mbed_official 340:28d1f895c6fe 4410 */
mbed_official 630:825f75ca301e 4411 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
mbed_official 340:28d1f895c6fe 4412 {
mbed_official 340:28d1f895c6fe 4413 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 630:825f75ca301e 4414
mbed_official 630:825f75ca301e 4415 htim->State= HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 4416
mbed_official 340:28d1f895c6fe 4417 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
mbed_official 340:28d1f895c6fe 4418 {
mbed_official 340:28d1f895c6fe 4419 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 340:28d1f895c6fe 4420 }
mbed_official 340:28d1f895c6fe 4421 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
mbed_official 340:28d1f895c6fe 4422 {
mbed_official 340:28d1f895c6fe 4423 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 340:28d1f895c6fe 4424 }
mbed_official 340:28d1f895c6fe 4425 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
mbed_official 340:28d1f895c6fe 4426 {
mbed_official 340:28d1f895c6fe 4427 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 340:28d1f895c6fe 4428 }
mbed_official 340:28d1f895c6fe 4429 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
mbed_official 340:28d1f895c6fe 4430 {
mbed_official 340:28d1f895c6fe 4431 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 340:28d1f895c6fe 4432 }
mbed_official 340:28d1f895c6fe 4433
mbed_official 340:28d1f895c6fe 4434 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 340:28d1f895c6fe 4435
mbed_official 340:28d1f895c6fe 4436 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 340:28d1f895c6fe 4437 }
mbed_official 340:28d1f895c6fe 4438 /**
mbed_official 630:825f75ca301e 4439 * @brief TIM DMA Capture complete callback.
mbed_official 340:28d1f895c6fe 4440 * @param hdma : pointer to DMA handle.
mbed_official 340:28d1f895c6fe 4441 * @retval None
mbed_official 340:28d1f895c6fe 4442 */
mbed_official 630:825f75ca301e 4443 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
mbed_official 340:28d1f895c6fe 4444 {
mbed_official 340:28d1f895c6fe 4445 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 630:825f75ca301e 4446
mbed_official 340:28d1f895c6fe 4447 htim->State= HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 4448
mbed_official 340:28d1f895c6fe 4449 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
mbed_official 340:28d1f895c6fe 4450 {
mbed_official 340:28d1f895c6fe 4451 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 340:28d1f895c6fe 4452 }
mbed_official 340:28d1f895c6fe 4453 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
mbed_official 340:28d1f895c6fe 4454 {
mbed_official 340:28d1f895c6fe 4455 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 340:28d1f895c6fe 4456 }
mbed_official 340:28d1f895c6fe 4457 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
mbed_official 340:28d1f895c6fe 4458 {
mbed_official 340:28d1f895c6fe 4459 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 340:28d1f895c6fe 4460 }
mbed_official 340:28d1f895c6fe 4461 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
mbed_official 340:28d1f895c6fe 4462 {
mbed_official 340:28d1f895c6fe 4463 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 340:28d1f895c6fe 4464 }
mbed_official 630:825f75ca301e 4465
mbed_official 630:825f75ca301e 4466 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 630:825f75ca301e 4467
mbed_official 340:28d1f895c6fe 4468 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 340:28d1f895c6fe 4469 }
mbed_official 630:825f75ca301e 4470
mbed_official 340:28d1f895c6fe 4471 /**
mbed_official 630:825f75ca301e 4472 * @brief TIM DMA Period Elapse complete callback.
mbed_official 340:28d1f895c6fe 4473 * @param hdma : pointer to DMA handle.
mbed_official 340:28d1f895c6fe 4474 * @retval None
mbed_official 340:28d1f895c6fe 4475 */
mbed_official 340:28d1f895c6fe 4476 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
mbed_official 340:28d1f895c6fe 4477 {
mbed_official 340:28d1f895c6fe 4478 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 630:825f75ca301e 4479
mbed_official 340:28d1f895c6fe 4480 htim->State= HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 4481
mbed_official 340:28d1f895c6fe 4482 HAL_TIM_PeriodElapsedCallback(htim);
mbed_official 340:28d1f895c6fe 4483 }
mbed_official 340:28d1f895c6fe 4484
mbed_official 340:28d1f895c6fe 4485 /**
mbed_official 630:825f75ca301e 4486 * @brief TIM DMA Trigger callback.
mbed_official 340:28d1f895c6fe 4487 * @param hdma : pointer to DMA handle.
mbed_official 340:28d1f895c6fe 4488 * @retval None
mbed_official 340:28d1f895c6fe 4489 */
mbed_official 340:28d1f895c6fe 4490 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
mbed_official 340:28d1f895c6fe 4491 {
mbed_official 630:825f75ca301e 4492 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 630:825f75ca301e 4493
mbed_official 630:825f75ca301e 4494 htim->State= HAL_TIM_STATE_READY;
mbed_official 630:825f75ca301e 4495
mbed_official 340:28d1f895c6fe 4496 HAL_TIM_TriggerCallback(htim);
mbed_official 340:28d1f895c6fe 4497 }
mbed_official 340:28d1f895c6fe 4498
mbed_official 340:28d1f895c6fe 4499 /**
mbed_official 340:28d1f895c6fe 4500 * @brief Time Base configuration
mbed_official 340:28d1f895c6fe 4501 * @param TIMx : TIM periheral
mbed_official 340:28d1f895c6fe 4502 * @param Structure : TIM Base configuration structure
mbed_official 340:28d1f895c6fe 4503 * @retval None
mbed_official 340:28d1f895c6fe 4504 */
mbed_official 340:28d1f895c6fe 4505 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
mbed_official 340:28d1f895c6fe 4506 {
mbed_official 340:28d1f895c6fe 4507 uint32_t tmpcr1 = 0;
mbed_official 340:28d1f895c6fe 4508 tmpcr1 = TIMx->CR1;
mbed_official 630:825f75ca301e 4509
mbed_official 340:28d1f895c6fe 4510 /* Set TIM Time Base Unit parameters ---------------------------------------*/
mbed_official 340:28d1f895c6fe 4511 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
mbed_official 340:28d1f895c6fe 4512 {
mbed_official 340:28d1f895c6fe 4513 /* Select the Counter Mode */
mbed_official 340:28d1f895c6fe 4514 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
mbed_official 340:28d1f895c6fe 4515 tmpcr1 |= Structure->CounterMode;
mbed_official 340:28d1f895c6fe 4516 }
mbed_official 630:825f75ca301e 4517
mbed_official 340:28d1f895c6fe 4518 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
mbed_official 340:28d1f895c6fe 4519 {
mbed_official 340:28d1f895c6fe 4520 /* Set the clock division */
mbed_official 340:28d1f895c6fe 4521 tmpcr1 &= ~TIM_CR1_CKD;
mbed_official 340:28d1f895c6fe 4522 tmpcr1 |= (uint32_t)Structure->ClockDivision;
mbed_official 340:28d1f895c6fe 4523 }
mbed_official 340:28d1f895c6fe 4524
mbed_official 340:28d1f895c6fe 4525 TIMx->CR1 = tmpcr1;
mbed_official 340:28d1f895c6fe 4526
mbed_official 340:28d1f895c6fe 4527 /* Set the Autoreload value */
mbed_official 340:28d1f895c6fe 4528 TIMx->ARR = (uint32_t)Structure->Period ;
mbed_official 630:825f75ca301e 4529
mbed_official 340:28d1f895c6fe 4530 /* Set the Prescaler value */
mbed_official 340:28d1f895c6fe 4531 TIMx->PSC = (uint32_t)Structure->Prescaler;
mbed_official 630:825f75ca301e 4532
mbed_official 630:825f75ca301e 4533 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
mbed_official 340:28d1f895c6fe 4534 {
mbed_official 340:28d1f895c6fe 4535 /* Set the Repetition Counter value */
mbed_official 340:28d1f895c6fe 4536 TIMx->RCR = Structure->RepetitionCounter;
mbed_official 340:28d1f895c6fe 4537 }
mbed_official 340:28d1f895c6fe 4538
mbed_official 340:28d1f895c6fe 4539 /* Generate an update event to reload the Prescaler
mbed_official 340:28d1f895c6fe 4540 and the repetition counter(only for TIM1 and TIM8) value immediatly */
mbed_official 340:28d1f895c6fe 4541 TIMx->EGR = TIM_EGR_UG;
mbed_official 340:28d1f895c6fe 4542 }
mbed_official 340:28d1f895c6fe 4543
mbed_official 340:28d1f895c6fe 4544 /**
mbed_official 340:28d1f895c6fe 4545 * @brief Time Ouput Compare 1 configuration
mbed_official 340:28d1f895c6fe 4546 * @param TIMx to select the TIM peripheral
mbed_official 340:28d1f895c6fe 4547 * @param OC_Config : The ouput configuration structure
mbed_official 340:28d1f895c6fe 4548 * @retval None
mbed_official 340:28d1f895c6fe 4549 */
mbed_official 340:28d1f895c6fe 4550 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 340:28d1f895c6fe 4551 {
mbed_official 340:28d1f895c6fe 4552 uint32_t tmpccmrx = 0;
mbed_official 340:28d1f895c6fe 4553 uint32_t tmpccer = 0;
mbed_official 630:825f75ca301e 4554 uint32_t tmpcr2 = 0;
mbed_official 340:28d1f895c6fe 4555
mbed_official 340:28d1f895c6fe 4556 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 340:28d1f895c6fe 4557 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 630:825f75ca301e 4558
mbed_official 340:28d1f895c6fe 4559 /* Get the TIMx CCER register value */
mbed_official 340:28d1f895c6fe 4560 tmpccer = TIMx->CCER;
mbed_official 340:28d1f895c6fe 4561 /* Get the TIMx CR2 register value */
mbed_official 630:825f75ca301e 4562 tmpcr2 = TIMx->CR2;
mbed_official 630:825f75ca301e 4563
mbed_official 340:28d1f895c6fe 4564 /* Get the TIMx CCMR1 register value */
mbed_official 340:28d1f895c6fe 4565 tmpccmrx = TIMx->CCMR1;
mbed_official 340:28d1f895c6fe 4566
mbed_official 340:28d1f895c6fe 4567 /* Reset the Output Compare Mode Bits */
mbed_official 340:28d1f895c6fe 4568 tmpccmrx &= ~TIM_CCMR1_OC1M;
mbed_official 340:28d1f895c6fe 4569 tmpccmrx &= ~TIM_CCMR1_CC1S;
mbed_official 340:28d1f895c6fe 4570 /* Select the Output Compare Mode */
mbed_official 340:28d1f895c6fe 4571 tmpccmrx |= OC_Config->OCMode;
mbed_official 630:825f75ca301e 4572
mbed_official 340:28d1f895c6fe 4573 /* Reset the Output Polarity level */
mbed_official 340:28d1f895c6fe 4574 tmpccer &= ~TIM_CCER_CC1P;
mbed_official 340:28d1f895c6fe 4575 /* Set the Output Compare Polarity */
mbed_official 340:28d1f895c6fe 4576 tmpccer |= OC_Config->OCPolarity;
mbed_official 340:28d1f895c6fe 4577
mbed_official 340:28d1f895c6fe 4578 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
mbed_official 340:28d1f895c6fe 4579 {
mbed_official 340:28d1f895c6fe 4580 /* Check parameters */
mbed_official 340:28d1f895c6fe 4581 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official 630:825f75ca301e 4582
mbed_official 340:28d1f895c6fe 4583 /* Reset the Output N Polarity level */
mbed_official 340:28d1f895c6fe 4584 tmpccer &= ~TIM_CCER_CC1NP;
mbed_official 340:28d1f895c6fe 4585 /* Set the Output N Polarity */
mbed_official 340:28d1f895c6fe 4586 tmpccer |= OC_Config->OCNPolarity;
mbed_official 340:28d1f895c6fe 4587 /* Reset the Output N State */
mbed_official 340:28d1f895c6fe 4588 tmpccer &= ~TIM_CCER_CC1NE;
mbed_official 340:28d1f895c6fe 4589 }
mbed_official 630:825f75ca301e 4590
mbed_official 340:28d1f895c6fe 4591 if(IS_TIM_BREAK_INSTANCE(TIMx))
mbed_official 340:28d1f895c6fe 4592 {
mbed_official 340:28d1f895c6fe 4593 /* Check parameters */
mbed_official 340:28d1f895c6fe 4594 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 340:28d1f895c6fe 4595 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 340:28d1f895c6fe 4596
mbed_official 340:28d1f895c6fe 4597 /* Reset the Output Compare and Output Compare N IDLE State */
mbed_official 340:28d1f895c6fe 4598 tmpcr2 &= ~TIM_CR2_OIS1;
mbed_official 340:28d1f895c6fe 4599 tmpcr2 &= ~TIM_CR2_OIS1N;
mbed_official 340:28d1f895c6fe 4600 /* Set the Output Idle state */
mbed_official 340:28d1f895c6fe 4601 tmpcr2 |= OC_Config->OCIdleState;
mbed_official 340:28d1f895c6fe 4602 /* Set the Output N Idle state */
mbed_official 340:28d1f895c6fe 4603 tmpcr2 |= OC_Config->OCNIdleState;
mbed_official 340:28d1f895c6fe 4604 }
mbed_official 340:28d1f895c6fe 4605 /* Write to TIMx CR2 */
mbed_official 340:28d1f895c6fe 4606 TIMx->CR2 = tmpcr2;
mbed_official 630:825f75ca301e 4607
mbed_official 340:28d1f895c6fe 4608 /* Write to TIMx CCMR1 */
mbed_official 340:28d1f895c6fe 4609 TIMx->CCMR1 = tmpccmrx;
mbed_official 630:825f75ca301e 4610
mbed_official 340:28d1f895c6fe 4611 /* Set the Capture Compare Register value */
mbed_official 340:28d1f895c6fe 4612 TIMx->CCR1 = OC_Config->Pulse;
mbed_official 630:825f75ca301e 4613
mbed_official 340:28d1f895c6fe 4614 /* Write to TIMx CCER */
mbed_official 630:825f75ca301e 4615 TIMx->CCER = tmpccer;
mbed_official 630:825f75ca301e 4616 }
mbed_official 340:28d1f895c6fe 4617
mbed_official 340:28d1f895c6fe 4618 /**
mbed_official 340:28d1f895c6fe 4619 * @brief Time Ouput Compare 2 configuration
mbed_official 340:28d1f895c6fe 4620 * @param TIMx to select the TIM peripheral
mbed_official 340:28d1f895c6fe 4621 * @param OC_Config : The ouput configuration structure
mbed_official 340:28d1f895c6fe 4622 * @retval None
mbed_official 340:28d1f895c6fe 4623 */
mbed_official 340:28d1f895c6fe 4624 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 340:28d1f895c6fe 4625 {
mbed_official 340:28d1f895c6fe 4626 uint32_t tmpccmrx = 0;
mbed_official 340:28d1f895c6fe 4627 uint32_t tmpccer = 0;
mbed_official 630:825f75ca301e 4628 uint32_t tmpcr2 = 0;
mbed_official 340:28d1f895c6fe 4629
mbed_official 340:28d1f895c6fe 4630 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 340:28d1f895c6fe 4631 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 630:825f75ca301e 4632
mbed_official 340:28d1f895c6fe 4633 /* Get the TIMx CCER register value */
mbed_official 340:28d1f895c6fe 4634 tmpccer = TIMx->CCER;
mbed_official 340:28d1f895c6fe 4635 /* Get the TIMx CR2 register value */
mbed_official 630:825f75ca301e 4636 tmpcr2 = TIMx->CR2;
mbed_official 630:825f75ca301e 4637
mbed_official 340:28d1f895c6fe 4638 /* Get the TIMx CCMR1 register value */
mbed_official 340:28d1f895c6fe 4639 tmpccmrx = TIMx->CCMR1;
mbed_official 340:28d1f895c6fe 4640
mbed_official 340:28d1f895c6fe 4641 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 340:28d1f895c6fe 4642 tmpccmrx &= ~TIM_CCMR1_OC2M;
mbed_official 340:28d1f895c6fe 4643 tmpccmrx &= ~TIM_CCMR1_CC2S;
mbed_official 630:825f75ca301e 4644
mbed_official 340:28d1f895c6fe 4645 /* Select the Output Compare Mode */
mbed_official 340:28d1f895c6fe 4646 tmpccmrx |= (OC_Config->OCMode << 8);
mbed_official 630:825f75ca301e 4647
mbed_official 340:28d1f895c6fe 4648 /* Reset the Output Polarity level */
mbed_official 340:28d1f895c6fe 4649 tmpccer &= ~TIM_CCER_CC2P;
mbed_official 340:28d1f895c6fe 4650 /* Set the Output Compare Polarity */
mbed_official 340:28d1f895c6fe 4651 tmpccer |= (OC_Config->OCPolarity << 4);
mbed_official 340:28d1f895c6fe 4652
mbed_official 340:28d1f895c6fe 4653 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
mbed_official 630:825f75ca301e 4654 {
mbed_official 340:28d1f895c6fe 4655 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official 340:28d1f895c6fe 4656 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 340:28d1f895c6fe 4657 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 340:28d1f895c6fe 4658
mbed_official 340:28d1f895c6fe 4659 /* Reset the Output N Polarity level */
mbed_official 340:28d1f895c6fe 4660 tmpccer &= ~TIM_CCER_CC2NP;
mbed_official 340:28d1f895c6fe 4661 /* Set the Output N Polarity */
mbed_official 340:28d1f895c6fe 4662 tmpccer |= (OC_Config->OCNPolarity << 4);
mbed_official 340:28d1f895c6fe 4663 /* Reset the Output N State */
mbed_official 340:28d1f895c6fe 4664 tmpccer &= ~TIM_CCER_CC2NE;
mbed_official 630:825f75ca301e 4665
mbed_official 340:28d1f895c6fe 4666 }
mbed_official 340:28d1f895c6fe 4667
mbed_official 340:28d1f895c6fe 4668 if(IS_TIM_BREAK_INSTANCE(TIMx))
mbed_official 340:28d1f895c6fe 4669 {
mbed_official 340:28d1f895c6fe 4670 /* Check parameters */
mbed_official 340:28d1f895c6fe 4671 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 340:28d1f895c6fe 4672 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 340:28d1f895c6fe 4673
mbed_official 340:28d1f895c6fe 4674 /* Reset the Output Compare and Output Compare N IDLE State */
mbed_official 340:28d1f895c6fe 4675 tmpcr2 &= ~TIM_CR2_OIS2;
mbed_official 340:28d1f895c6fe 4676 tmpcr2 &= ~TIM_CR2_OIS2N;
mbed_official 340:28d1f895c6fe 4677 /* Set the Output Idle state */
mbed_official 340:28d1f895c6fe 4678 tmpcr2 |= (OC_Config->OCIdleState << 2);
mbed_official 340:28d1f895c6fe 4679 /* Set the Output N Idle state */
mbed_official 340:28d1f895c6fe 4680 tmpcr2 |= (OC_Config->OCNIdleState << 2);
mbed_official 340:28d1f895c6fe 4681 }
mbed_official 340:28d1f895c6fe 4682
mbed_official 340:28d1f895c6fe 4683 /* Write to TIMx CR2 */
mbed_official 340:28d1f895c6fe 4684 TIMx->CR2 = tmpcr2;
mbed_official 630:825f75ca301e 4685
mbed_official 340:28d1f895c6fe 4686 /* Write to TIMx CCMR1 */
mbed_official 340:28d1f895c6fe 4687 TIMx->CCMR1 = tmpccmrx;
mbed_official 630:825f75ca301e 4688
mbed_official 340:28d1f895c6fe 4689 /* Set the Capture Compare Register value */
mbed_official 340:28d1f895c6fe 4690 TIMx->CCR2 = OC_Config->Pulse;
mbed_official 630:825f75ca301e 4691
mbed_official 340:28d1f895c6fe 4692 /* Write to TIMx CCER */
mbed_official 630:825f75ca301e 4693 TIMx->CCER = tmpccer;
mbed_official 340:28d1f895c6fe 4694 }
mbed_official 340:28d1f895c6fe 4695
mbed_official 340:28d1f895c6fe 4696 /**
mbed_official 340:28d1f895c6fe 4697 * @brief Time Ouput Compare 3 configuration
mbed_official 340:28d1f895c6fe 4698 * @param TIMx to select the TIM peripheral
mbed_official 340:28d1f895c6fe 4699 * @param OC_Config : The ouput configuration structure
mbed_official 340:28d1f895c6fe 4700 * @retval None
mbed_official 340:28d1f895c6fe 4701 */
mbed_official 340:28d1f895c6fe 4702 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 340:28d1f895c6fe 4703 {
mbed_official 340:28d1f895c6fe 4704 uint32_t tmpccmrx = 0;
mbed_official 340:28d1f895c6fe 4705 uint32_t tmpccer = 0;
mbed_official 630:825f75ca301e 4706 uint32_t tmpcr2 = 0;
mbed_official 340:28d1f895c6fe 4707
mbed_official 340:28d1f895c6fe 4708 /* Disable the Channel 3: Reset the CC2E Bit */
mbed_official 340:28d1f895c6fe 4709 TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official 630:825f75ca301e 4710
mbed_official 340:28d1f895c6fe 4711 /* Get the TIMx CCER register value */
mbed_official 340:28d1f895c6fe 4712 tmpccer = TIMx->CCER;
mbed_official 340:28d1f895c6fe 4713 /* Get the TIMx CR2 register value */
mbed_official 630:825f75ca301e 4714 tmpcr2 = TIMx->CR2;
mbed_official 630:825f75ca301e 4715
mbed_official 340:28d1f895c6fe 4716 /* Get the TIMx CCMR2 register value */
mbed_official 340:28d1f895c6fe 4717 tmpccmrx = TIMx->CCMR2;
mbed_official 340:28d1f895c6fe 4718
mbed_official 340:28d1f895c6fe 4719 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 340:28d1f895c6fe 4720 tmpccmrx &= ~TIM_CCMR2_OC3M;
mbed_official 630:825f75ca301e 4721 tmpccmrx &= ~TIM_CCMR2_CC3S;
mbed_official 340:28d1f895c6fe 4722 /* Select the Output Compare Mode */
mbed_official 340:28d1f895c6fe 4723 tmpccmrx |= OC_Config->OCMode;
mbed_official 630:825f75ca301e 4724
mbed_official 340:28d1f895c6fe 4725 /* Reset the Output Polarity level */
mbed_official 340:28d1f895c6fe 4726 tmpccer &= ~TIM_CCER_CC3P;
mbed_official 340:28d1f895c6fe 4727 /* Set the Output Compare Polarity */
mbed_official 340:28d1f895c6fe 4728 tmpccer |= (OC_Config->OCPolarity << 8);
mbed_official 340:28d1f895c6fe 4729
mbed_official 340:28d1f895c6fe 4730 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
mbed_official 630:825f75ca301e 4731 {
mbed_official 340:28d1f895c6fe 4732 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official 340:28d1f895c6fe 4733 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 340:28d1f895c6fe 4734 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 340:28d1f895c6fe 4735
mbed_official 340:28d1f895c6fe 4736 /* Reset the Output N Polarity level */
mbed_official 340:28d1f895c6fe 4737 tmpccer &= ~TIM_CCER_CC3NP;
mbed_official 340:28d1f895c6fe 4738 /* Set the Output N Polarity */
mbed_official 340:28d1f895c6fe 4739 tmpccer |= (OC_Config->OCNPolarity << 8);
mbed_official 340:28d1f895c6fe 4740 /* Reset the Output N State */
mbed_official 340:28d1f895c6fe 4741 tmpccer &= ~TIM_CCER_CC3NE;
mbed_official 340:28d1f895c6fe 4742 }
mbed_official 630:825f75ca301e 4743
mbed_official 340:28d1f895c6fe 4744 if(IS_TIM_BREAK_INSTANCE(TIMx))
mbed_official 340:28d1f895c6fe 4745 {
mbed_official 340:28d1f895c6fe 4746 /* Check parameters */
mbed_official 340:28d1f895c6fe 4747 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 340:28d1f895c6fe 4748 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 340:28d1f895c6fe 4749
mbed_official 340:28d1f895c6fe 4750 /* Reset the Output Compare and Output Compare N IDLE State */
mbed_official 340:28d1f895c6fe 4751 tmpcr2 &= ~TIM_CR2_OIS3;
mbed_official 340:28d1f895c6fe 4752 tmpcr2 &= ~TIM_CR2_OIS3N;
mbed_official 340:28d1f895c6fe 4753 /* Set the Output Idle state */
mbed_official 340:28d1f895c6fe 4754 tmpcr2 |= (OC_Config->OCIdleState << 4);
mbed_official 340:28d1f895c6fe 4755 /* Set the Output N Idle state */
mbed_official 340:28d1f895c6fe 4756 tmpcr2 |= (OC_Config->OCNIdleState << 4);
mbed_official 340:28d1f895c6fe 4757 }
mbed_official 340:28d1f895c6fe 4758
mbed_official 340:28d1f895c6fe 4759 /* Write to TIMx CR2 */
mbed_official 340:28d1f895c6fe 4760 TIMx->CR2 = tmpcr2;
mbed_official 630:825f75ca301e 4761
mbed_official 340:28d1f895c6fe 4762 /* Write to TIMx CCMR2 */
mbed_official 340:28d1f895c6fe 4763 TIMx->CCMR2 = tmpccmrx;
mbed_official 630:825f75ca301e 4764
mbed_official 340:28d1f895c6fe 4765 /* Set the Capture Compare Register value */
mbed_official 340:28d1f895c6fe 4766 TIMx->CCR3 = OC_Config->Pulse;
mbed_official 630:825f75ca301e 4767
mbed_official 340:28d1f895c6fe 4768 /* Write to TIMx CCER */
mbed_official 630:825f75ca301e 4769 TIMx->CCER = tmpccer;
mbed_official 340:28d1f895c6fe 4770 }
mbed_official 340:28d1f895c6fe 4771
mbed_official 340:28d1f895c6fe 4772 /**
mbed_official 340:28d1f895c6fe 4773 * @brief Time Ouput Compare 4 configuration
mbed_official 340:28d1f895c6fe 4774 * @param TIMx to select the TIM peripheral
mbed_official 340:28d1f895c6fe 4775 * @param OC_Config : The ouput configuration structure
mbed_official 340:28d1f895c6fe 4776 * @retval None
mbed_official 340:28d1f895c6fe 4777 */
mbed_official 340:28d1f895c6fe 4778 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 340:28d1f895c6fe 4779 {
mbed_official 340:28d1f895c6fe 4780 uint32_t tmpccmrx = 0;
mbed_official 340:28d1f895c6fe 4781 uint32_t tmpccer = 0;
mbed_official 630:825f75ca301e 4782 uint32_t tmpcr2 = 0;
mbed_official 340:28d1f895c6fe 4783
mbed_official 340:28d1f895c6fe 4784 /* Disable the Channel 4: Reset the CC4E Bit */
mbed_official 340:28d1f895c6fe 4785 TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official 630:825f75ca301e 4786
mbed_official 340:28d1f895c6fe 4787 /* Get the TIMx CCER register value */
mbed_official 340:28d1f895c6fe 4788 tmpccer = TIMx->CCER;
mbed_official 340:28d1f895c6fe 4789 /* Get the TIMx CR2 register value */
mbed_official 630:825f75ca301e 4790 tmpcr2 = TIMx->CR2;
mbed_official 630:825f75ca301e 4791
mbed_official 340:28d1f895c6fe 4792 /* Get the TIMx CCMR2 register value */
mbed_official 340:28d1f895c6fe 4793 tmpccmrx = TIMx->CCMR2;
mbed_official 340:28d1f895c6fe 4794
mbed_official 340:28d1f895c6fe 4795 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 340:28d1f895c6fe 4796 tmpccmrx &= ~TIM_CCMR2_OC4M;
mbed_official 340:28d1f895c6fe 4797 tmpccmrx &= ~TIM_CCMR2_CC4S;
mbed_official 630:825f75ca301e 4798
mbed_official 340:28d1f895c6fe 4799 /* Select the Output Compare Mode */
mbed_official 340:28d1f895c6fe 4800 tmpccmrx |= (OC_Config->OCMode << 8);
mbed_official 630:825f75ca301e 4801
mbed_official 340:28d1f895c6fe 4802 /* Reset the Output Polarity level */
mbed_official 340:28d1f895c6fe 4803 tmpccer &= ~TIM_CCER_CC4P;
mbed_official 340:28d1f895c6fe 4804 /* Set the Output Compare Polarity */
mbed_official 340:28d1f895c6fe 4805 tmpccer |= (OC_Config->OCPolarity << 12);
mbed_official 340:28d1f895c6fe 4806
mbed_official 340:28d1f895c6fe 4807 if(IS_TIM_BREAK_INSTANCE(TIMx))
mbed_official 340:28d1f895c6fe 4808 {
mbed_official 340:28d1f895c6fe 4809 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 340:28d1f895c6fe 4810
mbed_official 340:28d1f895c6fe 4811 /* Reset the Output Compare IDLE State */
mbed_official 340:28d1f895c6fe 4812 tmpcr2 &= ~TIM_CR2_OIS4;
mbed_official 340:28d1f895c6fe 4813 /* Set the Output Idle state */
mbed_official 340:28d1f895c6fe 4814 tmpcr2 |= (OC_Config->OCIdleState << 6);
mbed_official 340:28d1f895c6fe 4815 }
mbed_official 340:28d1f895c6fe 4816
mbed_official 340:28d1f895c6fe 4817 /* Write to TIMx CR2 */
mbed_official 340:28d1f895c6fe 4818 TIMx->CR2 = tmpcr2;
mbed_official 630:825f75ca301e 4819
mbed_official 340:28d1f895c6fe 4820 /* Write to TIMx CCMR2 */
mbed_official 340:28d1f895c6fe 4821 TIMx->CCMR2 = tmpccmrx;
mbed_official 630:825f75ca301e 4822
mbed_official 340:28d1f895c6fe 4823 /* Set the Capture Compare Register value */
mbed_official 340:28d1f895c6fe 4824 TIMx->CCR4 = OC_Config->Pulse;
mbed_official 630:825f75ca301e 4825
mbed_official 340:28d1f895c6fe 4826 /* Write to TIMx CCER */
mbed_official 630:825f75ca301e 4827 TIMx->CCER = tmpccer;
mbed_official 340:28d1f895c6fe 4828 }
mbed_official 340:28d1f895c6fe 4829
mbed_official 340:28d1f895c6fe 4830 void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
mbed_official 340:28d1f895c6fe 4831 TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official 340:28d1f895c6fe 4832 {
mbed_official 340:28d1f895c6fe 4833 uint32_t tmpsmcr = 0;
mbed_official 340:28d1f895c6fe 4834 uint32_t tmpccmr1 = 0;
mbed_official 340:28d1f895c6fe 4835 uint32_t tmpccer = 0;
mbed_official 340:28d1f895c6fe 4836
mbed_official 340:28d1f895c6fe 4837 /* Get the TIMx SMCR register value */
mbed_official 340:28d1f895c6fe 4838 tmpsmcr = htim->Instance->SMCR;
mbed_official 340:28d1f895c6fe 4839
mbed_official 340:28d1f895c6fe 4840 /* Reset the Trigger Selection Bits */
mbed_official 340:28d1f895c6fe 4841 tmpsmcr &= ~TIM_SMCR_TS;
mbed_official 340:28d1f895c6fe 4842 /* Set the Input Trigger source */
mbed_official 340:28d1f895c6fe 4843 tmpsmcr |= sSlaveConfig->InputTrigger;
mbed_official 340:28d1f895c6fe 4844
mbed_official 340:28d1f895c6fe 4845 /* Reset the slave mode Bits */
mbed_official 340:28d1f895c6fe 4846 tmpsmcr &= ~TIM_SMCR_SMS;
mbed_official 340:28d1f895c6fe 4847 /* Set the slave mode */
mbed_official 340:28d1f895c6fe 4848 tmpsmcr |= sSlaveConfig->SlaveMode;
mbed_official 340:28d1f895c6fe 4849
mbed_official 340:28d1f895c6fe 4850 /* Write to TIMx SMCR */
mbed_official 340:28d1f895c6fe 4851 htim->Instance->SMCR = tmpsmcr;
mbed_official 630:825f75ca301e 4852
mbed_official 340:28d1f895c6fe 4853 /* Configure the trigger prescaler, filter, and polarity */
mbed_official 340:28d1f895c6fe 4854 switch (sSlaveConfig->InputTrigger)
mbed_official 340:28d1f895c6fe 4855 {
mbed_official 340:28d1f895c6fe 4856 case TIM_TS_ETRF:
mbed_official 340:28d1f895c6fe 4857 {
mbed_official 340:28d1f895c6fe 4858 /* Check the parameters */
mbed_official 340:28d1f895c6fe 4859 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 4860 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
mbed_official 340:28d1f895c6fe 4861 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 340:28d1f895c6fe 4862 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 340:28d1f895c6fe 4863 /* Configure the ETR Trigger source */
mbed_official 630:825f75ca301e 4864 TIM_ETR_SetConfig(htim->Instance,
mbed_official 630:825f75ca301e 4865 sSlaveConfig->TriggerPrescaler,
mbed_official 630:825f75ca301e 4866 sSlaveConfig->TriggerPolarity,
mbed_official 340:28d1f895c6fe 4867 sSlaveConfig->TriggerFilter);
mbed_official 340:28d1f895c6fe 4868 }
mbed_official 340:28d1f895c6fe 4869 break;
mbed_official 630:825f75ca301e 4870
mbed_official 340:28d1f895c6fe 4871 case TIM_TS_TI1F_ED:
mbed_official 340:28d1f895c6fe 4872 {
mbed_official 340:28d1f895c6fe 4873 /* Check the parameters */
mbed_official 340:28d1f895c6fe 4874 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 4875 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 630:825f75ca301e 4876
mbed_official 340:28d1f895c6fe 4877 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 340:28d1f895c6fe 4878 tmpccer = htim->Instance->CCER;
mbed_official 340:28d1f895c6fe 4879 htim->Instance->CCER &= ~TIM_CCER_CC1E;
mbed_official 630:825f75ca301e 4880 tmpccmr1 = htim->Instance->CCMR1;
mbed_official 630:825f75ca301e 4881
mbed_official 340:28d1f895c6fe 4882 /* Set the filter */
mbed_official 340:28d1f895c6fe 4883 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 340:28d1f895c6fe 4884 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
mbed_official 630:825f75ca301e 4885
mbed_official 340:28d1f895c6fe 4886 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 340:28d1f895c6fe 4887 htim->Instance->CCMR1 = tmpccmr1;
mbed_official 630:825f75ca301e 4888 htim->Instance->CCER = tmpccer;
mbed_official 630:825f75ca301e 4889
mbed_official 340:28d1f895c6fe 4890 }
mbed_official 340:28d1f895c6fe 4891 break;
mbed_official 630:825f75ca301e 4892
mbed_official 340:28d1f895c6fe 4893 case TIM_TS_TI1FP1:
mbed_official 340:28d1f895c6fe 4894 {
mbed_official 340:28d1f895c6fe 4895 /* Check the parameters */
mbed_official 340:28d1f895c6fe 4896 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 4897 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 340:28d1f895c6fe 4898 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 630:825f75ca301e 4899
mbed_official 340:28d1f895c6fe 4900 /* Configure TI1 Filter and Polarity */
mbed_official 340:28d1f895c6fe 4901 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 340:28d1f895c6fe 4902 sSlaveConfig->TriggerPolarity,
mbed_official 340:28d1f895c6fe 4903 sSlaveConfig->TriggerFilter);
mbed_official 340:28d1f895c6fe 4904 }
mbed_official 340:28d1f895c6fe 4905 break;
mbed_official 630:825f75ca301e 4906
mbed_official 340:28d1f895c6fe 4907 case TIM_TS_TI2FP2:
mbed_official 340:28d1f895c6fe 4908 {
mbed_official 340:28d1f895c6fe 4909 /* Check the parameters */
mbed_official 340:28d1f895c6fe 4910 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 4911 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 340:28d1f895c6fe 4912 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 630:825f75ca301e 4913
mbed_official 340:28d1f895c6fe 4914 /* Configure TI2 Filter and Polarity */
mbed_official 340:28d1f895c6fe 4915 TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official 340:28d1f895c6fe 4916 sSlaveConfig->TriggerPolarity,
mbed_official 340:28d1f895c6fe 4917 sSlaveConfig->TriggerFilter);
mbed_official 340:28d1f895c6fe 4918 }
mbed_official 340:28d1f895c6fe 4919 break;
mbed_official 630:825f75ca301e 4920
mbed_official 340:28d1f895c6fe 4921 case TIM_TS_ITR0:
mbed_official 340:28d1f895c6fe 4922 {
mbed_official 340:28d1f895c6fe 4923 /* Check the parameter */
mbed_official 340:28d1f895c6fe 4924 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 4925 }
mbed_official 340:28d1f895c6fe 4926 break;
mbed_official 630:825f75ca301e 4927
mbed_official 340:28d1f895c6fe 4928 case TIM_TS_ITR1:
mbed_official 340:28d1f895c6fe 4929 {
mbed_official 340:28d1f895c6fe 4930 /* Check the parameter */
mbed_official 340:28d1f895c6fe 4931 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 4932 }
mbed_official 340:28d1f895c6fe 4933 break;
mbed_official 630:825f75ca301e 4934
mbed_official 340:28d1f895c6fe 4935 case TIM_TS_ITR2:
mbed_official 340:28d1f895c6fe 4936 {
mbed_official 340:28d1f895c6fe 4937 /* Check the parameter */
mbed_official 340:28d1f895c6fe 4938 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 4939 }
mbed_official 340:28d1f895c6fe 4940 break;
mbed_official 630:825f75ca301e 4941
mbed_official 340:28d1f895c6fe 4942 case TIM_TS_ITR3:
mbed_official 340:28d1f895c6fe 4943 {
mbed_official 340:28d1f895c6fe 4944 /* Check the parameter */
mbed_official 340:28d1f895c6fe 4945 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 340:28d1f895c6fe 4946 }
mbed_official 340:28d1f895c6fe 4947 break;
mbed_official 630:825f75ca301e 4948
mbed_official 340:28d1f895c6fe 4949 default:
mbed_official 340:28d1f895c6fe 4950 break;
mbed_official 340:28d1f895c6fe 4951 }
mbed_official 340:28d1f895c6fe 4952 }
mbed_official 340:28d1f895c6fe 4953
mbed_official 340:28d1f895c6fe 4954 /**
mbed_official 340:28d1f895c6fe 4955 * @brief Configure the TI1 as Input.
mbed_official 340:28d1f895c6fe 4956 * @param TIMx to select the TIM peripheral.
mbed_official 340:28d1f895c6fe 4957 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 340:28d1f895c6fe 4958 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 4959 * @arg TIM_ICPOLARITY_RISING
mbed_official 630:825f75ca301e 4960 * @arg TIM_ICPOLARITY_FALLING
mbed_official 630:825f75ca301e 4961 * @arg TIM_ICPOLARITY_BOTHEDGE
mbed_official 340:28d1f895c6fe 4962 * @param TIM_ICSelection : specifies the input to be used.
mbed_official 340:28d1f895c6fe 4963 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 4964 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1.
mbed_official 630:825f75ca301e 4965 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2.
mbed_official 630:825f75ca301e 4966 * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC.
mbed_official 340:28d1f895c6fe 4967 * @param TIM_ICFilter : Specifies the Input Capture Filter.
mbed_official 340:28d1f895c6fe 4968 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 340:28d1f895c6fe 4969 * @retval None
mbed_official 340:28d1f895c6fe 4970 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
mbed_official 340:28d1f895c6fe 4971 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
mbed_official 340:28d1f895c6fe 4972 * protected against un-initialized filter and polarity values.
mbed_official 340:28d1f895c6fe 4973 */
mbed_official 340:28d1f895c6fe 4974 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 340:28d1f895c6fe 4975 uint32_t TIM_ICFilter)
mbed_official 340:28d1f895c6fe 4976 {
mbed_official 340:28d1f895c6fe 4977 uint32_t tmpccmr1 = 0;
mbed_official 340:28d1f895c6fe 4978 uint32_t tmpccer = 0;
mbed_official 340:28d1f895c6fe 4979
mbed_official 340:28d1f895c6fe 4980 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 340:28d1f895c6fe 4981 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 340:28d1f895c6fe 4982 tmpccmr1 = TIMx->CCMR1;
mbed_official 340:28d1f895c6fe 4983 tmpccer = TIMx->CCER;
mbed_official 340:28d1f895c6fe 4984
mbed_official 340:28d1f895c6fe 4985 /* Select the Input */
mbed_official 340:28d1f895c6fe 4986 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
mbed_official 340:28d1f895c6fe 4987 {
mbed_official 340:28d1f895c6fe 4988 tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official 340:28d1f895c6fe 4989 tmpccmr1 |= TIM_ICSelection;
mbed_official 630:825f75ca301e 4990 }
mbed_official 340:28d1f895c6fe 4991 else
mbed_official 340:28d1f895c6fe 4992 {
mbed_official 340:28d1f895c6fe 4993 tmpccmr1 |= TIM_CCMR1_CC1S_0;
mbed_official 340:28d1f895c6fe 4994 }
mbed_official 630:825f75ca301e 4995
mbed_official 340:28d1f895c6fe 4996 /* Set the filter */
mbed_official 340:28d1f895c6fe 4997 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 340:28d1f895c6fe 4998 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
mbed_official 340:28d1f895c6fe 4999
mbed_official 340:28d1f895c6fe 5000 /* Select the Polarity and set the CC1E Bit */
mbed_official 340:28d1f895c6fe 5001 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
mbed_official 340:28d1f895c6fe 5002 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
mbed_official 340:28d1f895c6fe 5003
mbed_official 340:28d1f895c6fe 5004 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 340:28d1f895c6fe 5005 TIMx->CCMR1 = tmpccmr1;
mbed_official 340:28d1f895c6fe 5006 TIMx->CCER = tmpccer;
mbed_official 340:28d1f895c6fe 5007 }
mbed_official 340:28d1f895c6fe 5008
mbed_official 340:28d1f895c6fe 5009 /**
mbed_official 340:28d1f895c6fe 5010 * @brief Configure the Polarity and Filter for TI1.
mbed_official 340:28d1f895c6fe 5011 * @param TIMx to select the TIM peripheral.
mbed_official 340:28d1f895c6fe 5012 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 340:28d1f895c6fe 5013 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 5014 * @arg TIM_ICPOLARITY_RISING
mbed_official 630:825f75ca301e 5015 * @arg TIM_ICPOLARITY_FALLING
mbed_official 630:825f75ca301e 5016 * @arg TIM_ICPOLARITY_BOTHEDGE
mbed_official 340:28d1f895c6fe 5017 * @param TIM_ICFilter : Specifies the Input Capture Filter.
mbed_official 340:28d1f895c6fe 5018 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 340:28d1f895c6fe 5019 * @retval None
mbed_official 340:28d1f895c6fe 5020 */
mbed_official 340:28d1f895c6fe 5021 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official 340:28d1f895c6fe 5022 {
mbed_official 340:28d1f895c6fe 5023 uint32_t tmpccmr1 = 0;
mbed_official 340:28d1f895c6fe 5024 uint32_t tmpccer = 0;
mbed_official 630:825f75ca301e 5025
mbed_official 340:28d1f895c6fe 5026 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 340:28d1f895c6fe 5027 tmpccer = TIMx->CCER;
mbed_official 340:28d1f895c6fe 5028 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 630:825f75ca301e 5029 tmpccmr1 = TIMx->CCMR1;
mbed_official 630:825f75ca301e 5030
mbed_official 340:28d1f895c6fe 5031 /* Set the filter */
mbed_official 340:28d1f895c6fe 5032 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 340:28d1f895c6fe 5033 tmpccmr1 |= (TIM_ICFilter << 4);
mbed_official 630:825f75ca301e 5034
mbed_official 340:28d1f895c6fe 5035 /* Select the Polarity and set the CC1E Bit */
mbed_official 340:28d1f895c6fe 5036 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
mbed_official 340:28d1f895c6fe 5037 tmpccer |= TIM_ICPolarity;
mbed_official 630:825f75ca301e 5038
mbed_official 340:28d1f895c6fe 5039 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 340:28d1f895c6fe 5040 TIMx->CCMR1 = tmpccmr1;
mbed_official 340:28d1f895c6fe 5041 TIMx->CCER = tmpccer;
mbed_official 340:28d1f895c6fe 5042 }
mbed_official 340:28d1f895c6fe 5043
mbed_official 340:28d1f895c6fe 5044 /**
mbed_official 340:28d1f895c6fe 5045 * @brief Configure the TI2 as Input.
mbed_official 340:28d1f895c6fe 5046 * @param TIMx to select the TIM peripheral
mbed_official 340:28d1f895c6fe 5047 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 340:28d1f895c6fe 5048 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 5049 * @arg TIM_ICPOLARITY_RISING
mbed_official 630:825f75ca301e 5050 * @arg TIM_ICPOLARITY_FALLING
mbed_official 630:825f75ca301e 5051 * @arg TIM_ICPOLARITY_BOTHEDGE
mbed_official 340:28d1f895c6fe 5052 * @param TIM_ICSelection : specifies the input to be used.
mbed_official 340:28d1f895c6fe 5053 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 5054 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2.
mbed_official 630:825f75ca301e 5055 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1.
mbed_official 630:825f75ca301e 5056 * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC.
mbed_official 340:28d1f895c6fe 5057 * @param TIM_ICFilter : Specifies the Input Capture Filter.
mbed_official 340:28d1f895c6fe 5058 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 340:28d1f895c6fe 5059 * @retval None
mbed_official 340:28d1f895c6fe 5060 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
mbed_official 340:28d1f895c6fe 5061 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
mbed_official 340:28d1f895c6fe 5062 * protected against un-initialized filter and polarity values.
mbed_official 340:28d1f895c6fe 5063 */
mbed_official 340:28d1f895c6fe 5064 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 340:28d1f895c6fe 5065 uint32_t TIM_ICFilter)
mbed_official 340:28d1f895c6fe 5066 {
mbed_official 340:28d1f895c6fe 5067 uint32_t tmpccmr1 = 0;
mbed_official 340:28d1f895c6fe 5068 uint32_t tmpccer = 0;
mbed_official 340:28d1f895c6fe 5069
mbed_official 340:28d1f895c6fe 5070 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 340:28d1f895c6fe 5071 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 340:28d1f895c6fe 5072 tmpccmr1 = TIMx->CCMR1;
mbed_official 340:28d1f895c6fe 5073 tmpccer = TIMx->CCER;
mbed_official 340:28d1f895c6fe 5074
mbed_official 340:28d1f895c6fe 5075 /* Select the Input */
mbed_official 340:28d1f895c6fe 5076 tmpccmr1 &= ~TIM_CCMR1_CC2S;
mbed_official 340:28d1f895c6fe 5077 tmpccmr1 |= (TIM_ICSelection << 8);
mbed_official 340:28d1f895c6fe 5078
mbed_official 340:28d1f895c6fe 5079 /* Set the filter */
mbed_official 340:28d1f895c6fe 5080 tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official 340:28d1f895c6fe 5081 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
mbed_official 340:28d1f895c6fe 5082
mbed_official 340:28d1f895c6fe 5083 /* Select the Polarity and set the CC2E Bit */
mbed_official 340:28d1f895c6fe 5084 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
mbed_official 340:28d1f895c6fe 5085 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
mbed_official 340:28d1f895c6fe 5086
mbed_official 340:28d1f895c6fe 5087 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 340:28d1f895c6fe 5088 TIMx->CCMR1 = tmpccmr1 ;
mbed_official 340:28d1f895c6fe 5089 TIMx->CCER = tmpccer;
mbed_official 340:28d1f895c6fe 5090 }
mbed_official 340:28d1f895c6fe 5091
mbed_official 340:28d1f895c6fe 5092 /**
mbed_official 340:28d1f895c6fe 5093 * @brief Configure the Polarity and Filter for TI2.
mbed_official 340:28d1f895c6fe 5094 * @param TIMx to select the TIM peripheral.
mbed_official 340:28d1f895c6fe 5095 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 340:28d1f895c6fe 5096 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 5097 * @arg TIM_ICPOLARITY_RISING
mbed_official 630:825f75ca301e 5098 * @arg TIM_ICPOLARITY_FALLING
mbed_official 630:825f75ca301e 5099 * @arg TIM_ICPOLARITY_BOTHEDGE
mbed_official 340:28d1f895c6fe 5100 * @param TIM_ICFilter : Specifies the Input Capture Filter.
mbed_official 340:28d1f895c6fe 5101 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 340:28d1f895c6fe 5102 * @retval None
mbed_official 340:28d1f895c6fe 5103 */
mbed_official 340:28d1f895c6fe 5104 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official 340:28d1f895c6fe 5105 {
mbed_official 340:28d1f895c6fe 5106 uint32_t tmpccmr1 = 0;
mbed_official 340:28d1f895c6fe 5107 uint32_t tmpccer = 0;
mbed_official 630:825f75ca301e 5108
mbed_official 340:28d1f895c6fe 5109 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 340:28d1f895c6fe 5110 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 340:28d1f895c6fe 5111 tmpccmr1 = TIMx->CCMR1;
mbed_official 340:28d1f895c6fe 5112 tmpccer = TIMx->CCER;
mbed_official 630:825f75ca301e 5113
mbed_official 340:28d1f895c6fe 5114 /* Set the filter */
mbed_official 340:28d1f895c6fe 5115 tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official 340:28d1f895c6fe 5116 tmpccmr1 |= (TIM_ICFilter << 12);
mbed_official 340:28d1f895c6fe 5117
mbed_official 340:28d1f895c6fe 5118 /* Select the Polarity and set the CC2E Bit */
mbed_official 340:28d1f895c6fe 5119 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
mbed_official 340:28d1f895c6fe 5120 tmpccer |= (TIM_ICPolarity << 4);
mbed_official 340:28d1f895c6fe 5121
mbed_official 340:28d1f895c6fe 5122 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 340:28d1f895c6fe 5123 TIMx->CCMR1 = tmpccmr1 ;
mbed_official 340:28d1f895c6fe 5124 TIMx->CCER = tmpccer;
mbed_official 340:28d1f895c6fe 5125 }
mbed_official 340:28d1f895c6fe 5126
mbed_official 340:28d1f895c6fe 5127 /**
mbed_official 340:28d1f895c6fe 5128 * @brief Configure the TI3 as Input.
mbed_official 340:28d1f895c6fe 5129 * @param TIMx to select the TIM peripheral
mbed_official 340:28d1f895c6fe 5130 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 340:28d1f895c6fe 5131 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 5132 * @arg TIM_ICPOLARITY_RISING
mbed_official 630:825f75ca301e 5133 * @arg TIM_ICPOLARITY_FALLING
mbed_official 630:825f75ca301e 5134 * @arg TIM_ICPOLARITY_BOTHEDGE
mbed_official 340:28d1f895c6fe 5135 * @param TIM_ICSelection : specifies the input to be used.
mbed_official 340:28d1f895c6fe 5136 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 5137 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3.
mbed_official 630:825f75ca301e 5138 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4.
mbed_official 630:825f75ca301e 5139 * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC.
mbed_official 340:28d1f895c6fe 5140 * @param TIM_ICFilter : Specifies the Input Capture Filter.
mbed_official 340:28d1f895c6fe 5141 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 340:28d1f895c6fe 5142 * @retval None
mbed_official 340:28d1f895c6fe 5143 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
mbed_official 340:28d1f895c6fe 5144 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
mbed_official 340:28d1f895c6fe 5145 * protected against un-initialized filter and polarity values.
mbed_official 340:28d1f895c6fe 5146 */
mbed_official 340:28d1f895c6fe 5147 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 340:28d1f895c6fe 5148 uint32_t TIM_ICFilter)
mbed_official 340:28d1f895c6fe 5149 {
mbed_official 340:28d1f895c6fe 5150 uint32_t tmpccmr2 = 0;
mbed_official 340:28d1f895c6fe 5151 uint32_t tmpccer = 0;
mbed_official 340:28d1f895c6fe 5152
mbed_official 340:28d1f895c6fe 5153 /* Disable the Channel 3: Reset the CC3E Bit */
mbed_official 340:28d1f895c6fe 5154 TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official 340:28d1f895c6fe 5155 tmpccmr2 = TIMx->CCMR2;
mbed_official 340:28d1f895c6fe 5156 tmpccer = TIMx->CCER;
mbed_official 340:28d1f895c6fe 5157
mbed_official 340:28d1f895c6fe 5158 /* Select the Input */
mbed_official 340:28d1f895c6fe 5159 tmpccmr2 &= ~TIM_CCMR2_CC3S;
mbed_official 340:28d1f895c6fe 5160 tmpccmr2 |= TIM_ICSelection;
mbed_official 340:28d1f895c6fe 5161
mbed_official 340:28d1f895c6fe 5162 /* Set the filter */
mbed_official 340:28d1f895c6fe 5163 tmpccmr2 &= ~TIM_CCMR2_IC3F;
mbed_official 340:28d1f895c6fe 5164 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
mbed_official 340:28d1f895c6fe 5165
mbed_official 340:28d1f895c6fe 5166 /* Select the Polarity and set the CC3E Bit */
mbed_official 340:28d1f895c6fe 5167 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
mbed_official 340:28d1f895c6fe 5168 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
mbed_official 340:28d1f895c6fe 5169
mbed_official 340:28d1f895c6fe 5170 /* Write to TIMx CCMR2 and CCER registers */
mbed_official 340:28d1f895c6fe 5171 TIMx->CCMR2 = tmpccmr2;
mbed_official 340:28d1f895c6fe 5172 TIMx->CCER = tmpccer;
mbed_official 340:28d1f895c6fe 5173 }
mbed_official 340:28d1f895c6fe 5174
mbed_official 340:28d1f895c6fe 5175 /**
mbed_official 340:28d1f895c6fe 5176 * @brief Configure the TI4 as Input.
mbed_official 340:28d1f895c6fe 5177 * @param TIMx to select the TIM peripheral
mbed_official 340:28d1f895c6fe 5178 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 340:28d1f895c6fe 5179 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 5180 * @arg TIM_ICPOLARITY_RISING
mbed_official 630:825f75ca301e 5181 * @arg TIM_ICPOLARITY_FALLING
mbed_official 630:825f75ca301e 5182 * @arg TIM_ICPOLARITY_BOTHEDGE
mbed_official 340:28d1f895c6fe 5183 * @param TIM_ICSelection : specifies the input to be used.
mbed_official 340:28d1f895c6fe 5184 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 5185 * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4.
mbed_official 630:825f75ca301e 5186 * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3.
mbed_official 630:825f75ca301e 5187 * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC.
mbed_official 340:28d1f895c6fe 5188 * @param TIM_ICFilter : Specifies the Input Capture Filter.
mbed_official 340:28d1f895c6fe 5189 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 340:28d1f895c6fe 5190 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
mbed_official 340:28d1f895c6fe 5191 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
mbed_official 340:28d1f895c6fe 5192 * protected against un-initialized filter and polarity values.
mbed_official 340:28d1f895c6fe 5193 * @retval None
mbed_official 340:28d1f895c6fe 5194 */
mbed_official 340:28d1f895c6fe 5195 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 340:28d1f895c6fe 5196 uint32_t TIM_ICFilter)
mbed_official 340:28d1f895c6fe 5197 {
mbed_official 340:28d1f895c6fe 5198 uint32_t tmpccmr2 = 0;
mbed_official 340:28d1f895c6fe 5199 uint32_t tmpccer = 0;
mbed_official 340:28d1f895c6fe 5200
mbed_official 340:28d1f895c6fe 5201 /* Disable the Channel 4: Reset the CC4E Bit */
mbed_official 340:28d1f895c6fe 5202 TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official 340:28d1f895c6fe 5203 tmpccmr2 = TIMx->CCMR2;
mbed_official 340:28d1f895c6fe 5204 tmpccer = TIMx->CCER;
mbed_official 340:28d1f895c6fe 5205
mbed_official 340:28d1f895c6fe 5206 /* Select the Input */
mbed_official 340:28d1f895c6fe 5207 tmpccmr2 &= ~TIM_CCMR2_CC4S;
mbed_official 340:28d1f895c6fe 5208 tmpccmr2 |= (TIM_ICSelection << 8);
mbed_official 340:28d1f895c6fe 5209
mbed_official 340:28d1f895c6fe 5210 /* Set the filter */
mbed_official 340:28d1f895c6fe 5211 tmpccmr2 &= ~TIM_CCMR2_IC4F;
mbed_official 340:28d1f895c6fe 5212 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
mbed_official 340:28d1f895c6fe 5213
mbed_official 340:28d1f895c6fe 5214 /* Select the Polarity and set the CC4E Bit */
mbed_official 340:28d1f895c6fe 5215 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
mbed_official 340:28d1f895c6fe 5216 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
mbed_official 340:28d1f895c6fe 5217
mbed_official 340:28d1f895c6fe 5218 /* Write to TIMx CCMR2 and CCER registers */
mbed_official 340:28d1f895c6fe 5219 TIMx->CCMR2 = tmpccmr2;
mbed_official 340:28d1f895c6fe 5220 TIMx->CCER = tmpccer ;
mbed_official 340:28d1f895c6fe 5221 }
mbed_official 340:28d1f895c6fe 5222
mbed_official 340:28d1f895c6fe 5223 /**
mbed_official 340:28d1f895c6fe 5224 * @brief Selects the Input Trigger source
mbed_official 340:28d1f895c6fe 5225 * @param TIMx to select the TIM peripheral
mbed_official 340:28d1f895c6fe 5226 * @param InputTriggerSource : The Input Trigger source.
mbed_official 340:28d1f895c6fe 5227 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 5228 * @arg TIM_TS_ITR0 : Internal Trigger 0
mbed_official 340:28d1f895c6fe 5229 * @arg TIM_TS_ITR1 : Internal Trigger 1
mbed_official 340:28d1f895c6fe 5230 * @arg TIM_TS_ITR2 : Internal Trigger 2
mbed_official 340:28d1f895c6fe 5231 * @arg TIM_TS_ITR3 : Internal Trigger 3
mbed_official 340:28d1f895c6fe 5232 * @arg TIM_TS_TI1F_ED : TI1 Edge Detector
mbed_official 340:28d1f895c6fe 5233 * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
mbed_official 340:28d1f895c6fe 5234 * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
mbed_official 340:28d1f895c6fe 5235 * @arg TIM_TS_ETRF : External Trigger input
mbed_official 340:28d1f895c6fe 5236 * @retval None
mbed_official 340:28d1f895c6fe 5237 */
mbed_official 340:28d1f895c6fe 5238 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
mbed_official 340:28d1f895c6fe 5239 {
mbed_official 340:28d1f895c6fe 5240 uint32_t tmpsmcr = 0;
mbed_official 630:825f75ca301e 5241
mbed_official 340:28d1f895c6fe 5242 /* Get the TIMx SMCR register value */
mbed_official 340:28d1f895c6fe 5243 tmpsmcr = TIMx->SMCR;
mbed_official 340:28d1f895c6fe 5244 /* Reset the TS Bits */
mbed_official 340:28d1f895c6fe 5245 tmpsmcr &= ~TIM_SMCR_TS;
mbed_official 340:28d1f895c6fe 5246 /* Set the Input Trigger source and the slave mode*/
mbed_official 340:28d1f895c6fe 5247 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
mbed_official 340:28d1f895c6fe 5248 /* Write to TIMx SMCR */
mbed_official 340:28d1f895c6fe 5249 TIMx->SMCR = tmpsmcr;
mbed_official 340:28d1f895c6fe 5250 }
mbed_official 340:28d1f895c6fe 5251 /**
mbed_official 340:28d1f895c6fe 5252 * @brief Configures the TIMx External Trigger (ETR).
mbed_official 340:28d1f895c6fe 5253 * @param TIMx to select the TIM peripheral
mbed_official 340:28d1f895c6fe 5254 * @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
mbed_official 340:28d1f895c6fe 5255 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 5256 * @arg TIM_ExtTRGPSC_DIV1 : ETRP Prescaler OFF.
mbed_official 340:28d1f895c6fe 5257 * @arg TIM_ExtTRGPSC_DIV2 : ETRP frequency divided by 2.
mbed_official 340:28d1f895c6fe 5258 * @arg TIM_ExtTRGPSC_DIV4 : ETRP frequency divided by 4.
mbed_official 340:28d1f895c6fe 5259 * @arg TIM_ExtTRGPSC_DIV8 : ETRP frequency divided by 8.
mbed_official 340:28d1f895c6fe 5260 * @param TIM_ExtTRGPolarity : The external Trigger Polarity.
mbed_official 340:28d1f895c6fe 5261 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 5262 * @arg TIM_ExtTRGPolarity_Inverted : active low or falling edge active.
mbed_official 340:28d1f895c6fe 5263 * @arg TIM_ExtTRGPolarity_NonInverted : active high or rising edge active.
mbed_official 340:28d1f895c6fe 5264 * @param ExtTRGFilter : External Trigger Filter.
mbed_official 340:28d1f895c6fe 5265 * This parameter must be a value between 0x00 and 0x0F
mbed_official 340:28d1f895c6fe 5266 * @retval None
mbed_official 340:28d1f895c6fe 5267 */
mbed_official 340:28d1f895c6fe 5268 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official 340:28d1f895c6fe 5269 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
mbed_official 340:28d1f895c6fe 5270 {
mbed_official 340:28d1f895c6fe 5271 uint32_t tmpsmcr = 0;
mbed_official 340:28d1f895c6fe 5272
mbed_official 340:28d1f895c6fe 5273 tmpsmcr = TIMx->SMCR;
mbed_official 340:28d1f895c6fe 5274
mbed_official 340:28d1f895c6fe 5275 /* Reset the ETR Bits */
mbed_official 340:28d1f895c6fe 5276 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
mbed_official 340:28d1f895c6fe 5277
mbed_official 340:28d1f895c6fe 5278 /* Set the Prescaler, the Filter value and the Polarity */
mbed_official 340:28d1f895c6fe 5279 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
mbed_official 340:28d1f895c6fe 5280
mbed_official 340:28d1f895c6fe 5281 /* Write to TIMx SMCR */
mbed_official 340:28d1f895c6fe 5282 TIMx->SMCR = tmpsmcr;
mbed_official 630:825f75ca301e 5283 }
mbed_official 340:28d1f895c6fe 5284
mbed_official 340:28d1f895c6fe 5285 /**
mbed_official 340:28d1f895c6fe 5286 * @brief Enables or disables the TIM Capture Compare Channel x.
mbed_official 340:28d1f895c6fe 5287 * @param TIMx to select the TIM peripheral
mbed_official 340:28d1f895c6fe 5288 * @param Channel : specifies the TIM Channel
mbed_official 340:28d1f895c6fe 5289 * This parameter can be one of the following values:
mbed_official 630:825f75ca301e 5290 * @arg TIM_CHANNEL_1 : TIM Channel 1
mbed_official 630:825f75ca301e 5291 * @arg TIM_CHANNEL_2 : TIM Channel 2
mbed_official 630:825f75ca301e 5292 * @arg TIM_CHANNEL_3 : TIM Channel 3
mbed_official 630:825f75ca301e 5293 * @arg TIM_CHANNEL_4 : TIM Channel 4
mbed_official 340:28d1f895c6fe 5294 * @param ChannelState : specifies the TIM Channel CCxE bit new state.
mbed_official 630:825f75ca301e 5295 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
mbed_official 340:28d1f895c6fe 5296 * @retval None
mbed_official 340:28d1f895c6fe 5297 */
mbed_official 340:28d1f895c6fe 5298 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
mbed_official 340:28d1f895c6fe 5299 {
mbed_official 340:28d1f895c6fe 5300 uint32_t tmp = 0;
mbed_official 340:28d1f895c6fe 5301
mbed_official 340:28d1f895c6fe 5302 /* Check the parameters */
mbed_official 630:825f75ca301e 5303 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
mbed_official 340:28d1f895c6fe 5304 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 340:28d1f895c6fe 5305
mbed_official 340:28d1f895c6fe 5306 tmp = TIM_CCER_CC1E << Channel;
mbed_official 340:28d1f895c6fe 5307
mbed_official 340:28d1f895c6fe 5308 /* Reset the CCxE Bit */
mbed_official 340:28d1f895c6fe 5309 TIMx->CCER &= ~tmp;
mbed_official 340:28d1f895c6fe 5310
mbed_official 630:825f75ca301e 5311 /* Set or reset the CCxE Bit */
mbed_official 340:28d1f895c6fe 5312 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
mbed_official 340:28d1f895c6fe 5313 }
mbed_official 340:28d1f895c6fe 5314
mbed_official 340:28d1f895c6fe 5315
mbed_official 340:28d1f895c6fe 5316 /**
mbed_official 340:28d1f895c6fe 5317 * @}
mbed_official 340:28d1f895c6fe 5318 */
mbed_official 340:28d1f895c6fe 5319
mbed_official 340:28d1f895c6fe 5320 #endif /* HAL_TIM_MODULE_ENABLED */
mbed_official 340:28d1f895c6fe 5321 /**
mbed_official 340:28d1f895c6fe 5322 * @}
mbed_official 630:825f75ca301e 5323 */
mbed_official 340:28d1f895c6fe 5324
mbed_official 340:28d1f895c6fe 5325 /**
mbed_official 340:28d1f895c6fe 5326 * @}
mbed_official 630:825f75ca301e 5327 */
mbed_official 340:28d1f895c6fe 5328 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/