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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h@630:825f75ca301e, 2015-09-28 (annotated)

Committer:: mbed_official
Date:: Mon Sep 28 10:45:10 2015 +0100
Revision:: 630:825f75ca301e
Parent:: 441:d2c15dda23c1

Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10

Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/

NUCLEO_F031K6 : Add new target

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	340:28d1f895c6fe	1	/**
mbed_official	340:28d1f895c6fe	2	******************************************************************************
mbed_official	340:28d1f895c6fe	3	* @file stm32f0xx_hal_rcc_ex.h
mbed_official	340:28d1f895c6fe	4	* @author MCD Application Team
mbed_official	630:825f75ca301e	5	* @version V1.3.0
mbed_official	630:825f75ca301e	6	* @date 26-June-2015
mbed_official	340:28d1f895c6fe	7	* @brief Header file of RCC HAL Extension module.
mbed_official	340:28d1f895c6fe	8	******************************************************************************
mbed_official	340:28d1f895c6fe	9	* @attention
mbed_official	340:28d1f895c6fe	10	*
mbed_official	630:825f75ca301e	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	340:28d1f895c6fe	12	*
mbed_official	340:28d1f895c6fe	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	340:28d1f895c6fe	14	* are permitted provided that the following conditions are met:
mbed_official	340:28d1f895c6fe	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	340:28d1f895c6fe	16	* this list of conditions and the following disclaimer.
mbed_official	340:28d1f895c6fe	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	340:28d1f895c6fe	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	340:28d1f895c6fe	19	* and/or other materials provided with the distribution.
mbed_official	340:28d1f895c6fe	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	340:28d1f895c6fe	21	* may be used to endorse or promote products derived from this software
mbed_official	340:28d1f895c6fe	22	* without specific prior written permission.
mbed_official	340:28d1f895c6fe	23	*
mbed_official	340:28d1f895c6fe	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	340:28d1f895c6fe	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	340:28d1f895c6fe	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	340:28d1f895c6fe	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	340:28d1f895c6fe	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	340:28d1f895c6fe	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	340:28d1f895c6fe	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	340:28d1f895c6fe	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	340:28d1f895c6fe	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	340:28d1f895c6fe	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	340:28d1f895c6fe	34	*
mbed_official	340:28d1f895c6fe	35	******************************************************************************
mbed_official	340:28d1f895c6fe	36	*/
mbed_official	340:28d1f895c6fe	37
mbed_official	340:28d1f895c6fe	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	340:28d1f895c6fe	39	#ifndef __STM32F0xx_HAL_RCC_EX_H
mbed_official	630:825f75ca301e	40	#define __HAL_RCC_STM32F0xx_HAL_RCC_EX_H
mbed_official	340:28d1f895c6fe	41
mbed_official	340:28d1f895c6fe	42	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	43	extern "C" {
mbed_official	340:28d1f895c6fe	44	#endif
mbed_official	340:28d1f895c6fe	45
mbed_official	340:28d1f895c6fe	46	/* Includes ------------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	47	#include "stm32f0xx_hal_def.h"
mbed_official	340:28d1f895c6fe	48
mbed_official	340:28d1f895c6fe	49	/** @addtogroup STM32F0xx_HAL_Driver
mbed_official	340:28d1f895c6fe	50	* @{
mbed_official	340:28d1f895c6fe	51	*/
mbed_official	340:28d1f895c6fe	52
mbed_official	630:825f75ca301e	53	/** @addtogroup RCC
mbed_official	630:825f75ca301e	54	* @{
mbed_official	630:825f75ca301e	55	*/
mbed_official	630:825f75ca301e	56
mbed_official	630:825f75ca301e	57	/** @addtogroup RCC_Private_Macros
mbed_official	630:825f75ca301e	58	* @{
mbed_official	630:825f75ca301e	59	*/
mbed_official	630:825f75ca301e	60	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	61	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	62	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	63	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
mbed_official	630:825f75ca301e	64	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
mbed_official	630:825f75ca301e	65	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
mbed_official	630:825f75ca301e	66	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
mbed_official	630:825f75ca301e	67	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
mbed_official	630:825f75ca301e	68	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) \|\| \
mbed_official	630:825f75ca301e	69	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
mbed_official	630:825f75ca301e	70	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	630:825f75ca301e	71	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	630:825f75ca301e	72	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
mbed_official	630:825f75ca301e	73	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
mbed_official	630:825f75ca301e	74
mbed_official	630:825f75ca301e	75	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
mbed_official	630:825f75ca301e	76	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
mbed_official	630:825f75ca301e	77	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
mbed_official	630:825f75ca301e	78	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
mbed_official	630:825f75ca301e	79	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	630:825f75ca301e	80	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
mbed_official	630:825f75ca301e	81	((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official	630:825f75ca301e	82	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
mbed_official	630:825f75ca301e	83	#else
mbed_official	630:825f75ca301e	84	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
mbed_official	630:825f75ca301e	85	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
mbed_official	630:825f75ca301e	86	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
mbed_official	630:825f75ca301e	87	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
mbed_official	630:825f75ca301e	88	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
mbed_official	630:825f75ca301e	89	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14))
mbed_official	630:825f75ca301e	90	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	630:825f75ca301e	91	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	630:825f75ca301e	92	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official	630:825f75ca301e	93
mbed_official	630:825f75ca301e	94	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
mbed_official	630:825f75ca301e	95	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
mbed_official	630:825f75ca301e	96	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
mbed_official	630:825f75ca301e	97	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	630:825f75ca301e	98	((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official	630:825f75ca301e	99
mbed_official	630:825f75ca301e	100	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	101	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	102	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	103
mbed_official	630:825f75ca301e	104	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	105	\|\| defined(STM32F070xB) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	106
mbed_official	630:825f75ca301e	107	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
mbed_official	630:825f75ca301e	108	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
mbed_official	630:825f75ca301e	109	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
mbed_official	630:825f75ca301e	110	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
mbed_official	630:825f75ca301e	111	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
mbed_official	630:825f75ca301e	112	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
mbed_official	630:825f75ca301e	113	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
mbed_official	630:825f75ca301e	114	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
mbed_official	630:825f75ca301e	115	((SOURCE) == RCC_MCOSOURCE_HSI14))
mbed_official	630:825f75ca301e	116
mbed_official	630:825f75ca301e	117	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| STM32F070xB \|\| STM32F030xC */
mbed_official	630:825f75ca301e	118
mbed_official	630:825f75ca301e	119	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	630:825f75ca301e	120
mbed_official	630:825f75ca301e	121	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
mbed_official	630:825f75ca301e	122	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
mbed_official	630:825f75ca301e	123	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
mbed_official	630:825f75ca301e	124	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
mbed_official	630:825f75ca301e	125	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
mbed_official	630:825f75ca301e	126	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
mbed_official	630:825f75ca301e	127	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
mbed_official	630:825f75ca301e	128	((SOURCE) == RCC_MCOSOURCE_HSI14))
mbed_official	630:825f75ca301e	129
mbed_official	630:825f75ca301e	130	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
mbed_official	630:825f75ca301e	131
mbed_official	630:825f75ca301e	132	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	133	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	134	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	135
mbed_official	630:825f75ca301e	136	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
mbed_official	630:825f75ca301e	137	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
mbed_official	630:825f75ca301e	138	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
mbed_official	630:825f75ca301e	139	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
mbed_official	630:825f75ca301e	140	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
mbed_official	630:825f75ca301e	141	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
mbed_official	630:825f75ca301e	142	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
mbed_official	630:825f75ca301e	143	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
mbed_official	630:825f75ca301e	144	((SOURCE) == RCC_MCOSOURCE_HSI14) \|\| \
mbed_official	630:825f75ca301e	145	((SOURCE) == RCC_MCOSOURCE_HSI48))
mbed_official	630:825f75ca301e	146
mbed_official	630:825f75ca301e	147	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	148	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	149	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	150
mbed_official	630:825f75ca301e	151	/**
mbed_official	630:825f75ca301e	152	* @}
mbed_official	630:825f75ca301e	153	*/
mbed_official	630:825f75ca301e	154
mbed_official	630:825f75ca301e	155	/** @addtogroup RCC_Exported_Constants
mbed_official	630:825f75ca301e	156	* @{
mbed_official	630:825f75ca301e	157	*/
mbed_official	630:825f75ca301e	158	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	159	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	160	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	161
mbed_official	630:825f75ca301e	162	/** @addtogroup RCC_PLL_Clock_Source
mbed_official	630:825f75ca301e	163	* @{
mbed_official	630:825f75ca301e	164	*/
mbed_official	630:825f75ca301e	165	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
mbed_official	630:825f75ca301e	166	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
mbed_official	630:825f75ca301e	167
mbed_official	630:825f75ca301e	168	/**
mbed_official	630:825f75ca301e	169	* @}
mbed_official	630:825f75ca301e	170	*/
mbed_official	630:825f75ca301e	171
mbed_official	630:825f75ca301e	172	/** @addtogroup RCC_Oscillator_Type
mbed_official	630:825f75ca301e	173	* @{
mbed_official	630:825f75ca301e	174	*/
mbed_official	630:825f75ca301e	175	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
mbed_official	630:825f75ca301e	176	/**
mbed_official	630:825f75ca301e	177	* @}
mbed_official	630:825f75ca301e	178	*/
mbed_official	630:825f75ca301e	179
mbed_official	630:825f75ca301e	180	/** @addtogroup RCC_Interrupt
mbed_official	630:825f75ca301e	181	* @{
mbed_official	630:825f75ca301e	182	*/
mbed_official	630:825f75ca301e	183	#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
mbed_official	630:825f75ca301e	184	/**
mbed_official	630:825f75ca301e	185	* @}
mbed_official	630:825f75ca301e	186	*/
mbed_official	630:825f75ca301e	187
mbed_official	630:825f75ca301e	188	/** @addtogroup RCC_Flag
mbed_official	630:825f75ca301e	189	* @{
mbed_official	630:825f75ca301e	190	*/
mbed_official	630:825f75ca301e	191	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI48RDY_BitNumber))
mbed_official	630:825f75ca301e	192	/**
mbed_official	630:825f75ca301e	193	* @}
mbed_official	630:825f75ca301e	194	*/
mbed_official	630:825f75ca301e	195
mbed_official	630:825f75ca301e	196	/** @addtogroup RCC_System_Clock_Source
mbed_official	630:825f75ca301e	197	* @{
mbed_official	630:825f75ca301e	198	*/
mbed_official	630:825f75ca301e	199	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
mbed_official	630:825f75ca301e	200	/**
mbed_official	630:825f75ca301e	201	* @}
mbed_official	630:825f75ca301e	202	*/
mbed_official	630:825f75ca301e	203
mbed_official	630:825f75ca301e	204	/** @addtogroup RCC_System_Clock_Source_Status
mbed_official	630:825f75ca301e	205	* @{
mbed_official	630:825f75ca301e	206	*/
mbed_official	630:825f75ca301e	207	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
mbed_official	630:825f75ca301e	208	/**
mbed_official	630:825f75ca301e	209	* @}
mbed_official	630:825f75ca301e	210	*/
mbed_official	630:825f75ca301e	211
mbed_official	630:825f75ca301e	212	#else
mbed_official	630:825f75ca301e	213	/** @addtogroup RCC_PLL_Clock_Source
mbed_official	630:825f75ca301e	214	* @{
mbed_official	630:825f75ca301e	215	*/
mbed_official	630:825f75ca301e	216
mbed_official	630:825f75ca301e	217	#if defined(STM32F070xB) \|\| defined(STM32F070x6) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	218	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
mbed_official	630:825f75ca301e	219	#else
mbed_official	630:825f75ca301e	220	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
mbed_official	630:825f75ca301e	221	#endif
mbed_official	630:825f75ca301e	222
mbed_official	630:825f75ca301e	223	/**
mbed_official	630:825f75ca301e	224	* @}
mbed_official	630:825f75ca301e	225	*/
mbed_official	630:825f75ca301e	226
mbed_official	630:825f75ca301e	227	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	228	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	229	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	230
mbed_official	630:825f75ca301e	231	/** @addtogroup RCC_MCO_Clock_Source
mbed_official	630:825f75ca301e	232	* @{
mbed_official	630:825f75ca301e	233	*/
mbed_official	630:825f75ca301e	234
mbed_official	630:825f75ca301e	235	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	236	\|\| defined(STM32F070xB) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	237
mbed_official	630:825f75ca301e	238	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
mbed_official	630:825f75ca301e	239
mbed_official	630:825f75ca301e	240	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| STM32F070xB \|\| STM32F030xC */
mbed_official	630:825f75ca301e	241
mbed_official	630:825f75ca301e	242	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	243	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	244	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	245
mbed_official	630:825f75ca301e	246	#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
mbed_official	630:825f75ca301e	247	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
mbed_official	630:825f75ca301e	248
mbed_official	630:825f75ca301e	249	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	250	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	251	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	252	/**
mbed_official	630:825f75ca301e	253	* @}
mbed_official	630:825f75ca301e	254	*/
mbed_official	630:825f75ca301e	255
mbed_official	630:825f75ca301e	256	/**
mbed_official	630:825f75ca301e	257	* @}
mbed_official	630:825f75ca301e	258	*/
mbed_official	630:825f75ca301e	259
mbed_official	630:825f75ca301e	260	/**
mbed_official	630:825f75ca301e	261	* @}
mbed_official	630:825f75ca301e	262	*/
mbed_official	630:825f75ca301e	263
mbed_official	340:28d1f895c6fe	264	/** @addtogroup RCCEx
mbed_official	340:28d1f895c6fe	265	* @{
mbed_official	340:28d1f895c6fe	266	*/
mbed_official	340:28d1f895c6fe	267
mbed_official	630:825f75ca301e	268	/* Private macro -------------------------------------------------------------*/
mbed_official	630:825f75ca301e	269	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
mbed_official	630:825f75ca301e	270	* @{
mbed_official	630:825f75ca301e	271	*/
mbed_official	630:825f75ca301e	272	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
mbed_official	630:825f75ca301e	273	\|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	274
mbed_official	630:825f75ca301e	275	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
mbed_official	630:825f75ca301e	276	RCC_PERIPHCLK_RTC))
mbed_official	630:825f75ca301e	277	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
mbed_official	630:825f75ca301e	278	STM32F030xC */
mbed_official	630:825f75ca301e	279
mbed_official	630:825f75ca301e	280	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
mbed_official	630:825f75ca301e	281
mbed_official	630:825f75ca301e	282	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
mbed_official	630:825f75ca301e	283	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
mbed_official	630:825f75ca301e	284	#endif /* STM32F070x6 \|\| STM32F070xB */
mbed_official	630:825f75ca301e	285
mbed_official	630:825f75ca301e	286	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
mbed_official	630:825f75ca301e	287
mbed_official	630:825f75ca301e	288	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
mbed_official	630:825f75ca301e	289	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
mbed_official	630:825f75ca301e	290	RCC_PERIPHCLK_USB))
mbed_official	630:825f75ca301e	291	#endif /* STM32F042x6 \|\| STM32F048xx */
mbed_official	630:825f75ca301e	292
mbed_official	630:825f75ca301e	293	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	630:825f75ca301e	294
mbed_official	630:825f75ca301e	295	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
mbed_official	630:825f75ca301e	296	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
mbed_official	630:825f75ca301e	297	#endif /* STM32F051x8 \|\| STM32F058xx */
mbed_official	630:825f75ca301e	298
mbed_official	630:825f75ca301e	299	#if defined(STM32F071xB)
mbed_official	630:825f75ca301e	300
mbed_official	630:825f75ca301e	301	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
mbed_official	630:825f75ca301e	302	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
mbed_official	630:825f75ca301e	303	RCC_PERIPHCLK_RTC))
mbed_official	630:825f75ca301e	304	#endif /* STM32F071xB */
mbed_official	630:825f75ca301e	305
mbed_official	630:825f75ca301e	306	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	630:825f75ca301e	307
mbed_official	630:825f75ca301e	308	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
mbed_official	630:825f75ca301e	309	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
mbed_official	630:825f75ca301e	310	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
mbed_official	630:825f75ca301e	311	#endif /* STM32F072xB \|\| STM32F078xx */
mbed_official	630:825f75ca301e	312
mbed_official	630:825f75ca301e	313	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	314
mbed_official	630:825f75ca301e	315	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
mbed_official	630:825f75ca301e	316	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
mbed_official	630:825f75ca301e	317	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USART3 ))
mbed_official	630:825f75ca301e	318	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	319
mbed_official	630:825f75ca301e	320	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	630:825f75ca301e	321
mbed_official	630:825f75ca301e	322	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
mbed_official	630:825f75ca301e	323	((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
mbed_official	630:825f75ca301e	324
mbed_official	630:825f75ca301e	325	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
mbed_official	630:825f75ca301e	326
mbed_official	630:825f75ca301e	327	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
mbed_official	630:825f75ca301e	328
mbed_official	630:825f75ca301e	329	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
mbed_official	630:825f75ca301e	330
mbed_official	630:825f75ca301e	331	#endif /* STM32F070x6 \|\| STM32F070xB */
mbed_official	630:825f75ca301e	332
mbed_official	630:825f75ca301e	333	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	334	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	335
mbed_official	630:825f75ca301e	336	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
mbed_official	630:825f75ca301e	337	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
mbed_official	630:825f75ca301e	338	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
mbed_official	630:825f75ca301e	339	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
mbed_official	630:825f75ca301e	340
mbed_official	630:825f75ca301e	341	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	342	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	343
mbed_official	630:825f75ca301e	344	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	345
mbed_official	630:825f75ca301e	346	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
mbed_official	630:825f75ca301e	347	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
mbed_official	630:825f75ca301e	348	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
mbed_official	630:825f75ca301e	349	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
mbed_official	630:825f75ca301e	350	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	351
mbed_official	630:825f75ca301e	352
mbed_official	630:825f75ca301e	353	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	354	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	355	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	356	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	357
mbed_official	630:825f75ca301e	358	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
mbed_official	630:825f75ca301e	359	((SOURCE) == RCC_CECCLKSOURCE_LSE))
mbed_official	630:825f75ca301e	360	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	361	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	630:825f75ca301e	362	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	363	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	364
mbed_official	630:825f75ca301e	365	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	630:825f75ca301e	366
mbed_official	630:825f75ca301e	367	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
mbed_official	630:825f75ca301e	368
mbed_official	630:825f75ca301e	369	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
mbed_official	630:825f75ca301e	370
mbed_official	630:825f75ca301e	371	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	372	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	373	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	374	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	375
mbed_official	630:825f75ca301e	376	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
mbed_official	630:825f75ca301e	377	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
mbed_official	630:825f75ca301e	378	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
mbed_official	630:825f75ca301e	379	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
mbed_official	630:825f75ca301e	380
mbed_official	630:825f75ca301e	381	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	382	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070x6 \|\| STM32F070xB */
mbed_official	630:825f75ca301e	383	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	630:825f75ca301e	384
mbed_official	630:825f75ca301e	385	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	386	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	387	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	388
mbed_official	630:825f75ca301e	389	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
mbed_official	630:825f75ca301e	390	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
mbed_official	630:825f75ca301e	391	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
mbed_official	630:825f75ca301e	392	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
mbed_official	630:825f75ca301e	393	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
mbed_official	630:825f75ca301e	394	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
mbed_official	630:825f75ca301e	395	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
mbed_official	630:825f75ca301e	396	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
mbed_official	630:825f75ca301e	397	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
mbed_official	630:825f75ca301e	398	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
mbed_official	630:825f75ca301e	399	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
mbed_official	630:825f75ca301e	400	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
mbed_official	630:825f75ca301e	401	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
mbed_official	630:825f75ca301e	402	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
mbed_official	630:825f75ca301e	403	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	404	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	405	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	406	/**
mbed_official	630:825f75ca301e	407	* @}
mbed_official	630:825f75ca301e	408	*/
mbed_official	630:825f75ca301e	409
mbed_official	340:28d1f895c6fe	410	/* Exported types ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	411
mbed_official	340:28d1f895c6fe	412	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
mbed_official	340:28d1f895c6fe	413	* @{
mbed_official	340:28d1f895c6fe	414	*/
mbed_official	340:28d1f895c6fe	415
mbed_official	340:28d1f895c6fe	416	/**
mbed_official	340:28d1f895c6fe	417	* @brief RCC extended clocks structure definition
mbed_official	340:28d1f895c6fe	418	*/
mbed_official	630:825f75ca301e	419	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
mbed_official	630:825f75ca301e	420	\|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	421	typedef struct
mbed_official	340:28d1f895c6fe	422	{
mbed_official	340:28d1f895c6fe	423	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	424	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	425
mbed_official	340:28d1f895c6fe	426	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	427	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	428
mbed_official	340:28d1f895c6fe	429	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	430	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	431
mbed_official	340:28d1f895c6fe	432	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	433	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	434
mbed_official	340:28d1f895c6fe	435	}RCC_PeriphCLKInitTypeDef;
mbed_official	441:d2c15dda23c1	436	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
mbed_official	441:d2c15dda23c1	437	STM32F030xC */
mbed_official	441:d2c15dda23c1	438
mbed_official	441:d2c15dda23c1	439	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
mbed_official	441:d2c15dda23c1	440	typedef struct
mbed_official	441:d2c15dda23c1	441	{
mbed_official	441:d2c15dda23c1	442	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	441:d2c15dda23c1	443	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	441:d2c15dda23c1	444
mbed_official	441:d2c15dda23c1	445	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	441:d2c15dda23c1	446	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	441:d2c15dda23c1	447
mbed_official	441:d2c15dda23c1	448	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	441:d2c15dda23c1	449	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	441:d2c15dda23c1	450
mbed_official	441:d2c15dda23c1	451	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	441:d2c15dda23c1	452	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	441:d2c15dda23c1	453
mbed_official	441:d2c15dda23c1	454	uint32_t UsbClockSelection; /*!< USB clock source
mbed_official	441:d2c15dda23c1	455	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	441:d2c15dda23c1	456
mbed_official	441:d2c15dda23c1	457	}RCC_PeriphCLKInitTypeDef;
mbed_official	441:d2c15dda23c1	458	#endif /* STM32F070x6 \|\| STM32F070xB */
mbed_official	340:28d1f895c6fe	459
mbed_official	340:28d1f895c6fe	460	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
mbed_official	340:28d1f895c6fe	461	typedef struct
mbed_official	340:28d1f895c6fe	462	{
mbed_official	340:28d1f895c6fe	463	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	464	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	465
mbed_official	340:28d1f895c6fe	466	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	467	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	468
mbed_official	340:28d1f895c6fe	469	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	470	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	471
mbed_official	340:28d1f895c6fe	472	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	473	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	474
mbed_official	340:28d1f895c6fe	475	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	476	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	477
mbed_official	340:28d1f895c6fe	478	uint32_t UsbClockSelection; /*!< USB clock source
mbed_official	340:28d1f895c6fe	479	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	340:28d1f895c6fe	480
mbed_official	340:28d1f895c6fe	481	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	482	#endif /* STM32F042x6 \|\| STM32F048xx */
mbed_official	340:28d1f895c6fe	483
mbed_official	340:28d1f895c6fe	484	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	340:28d1f895c6fe	485	typedef struct
mbed_official	340:28d1f895c6fe	486	{
mbed_official	340:28d1f895c6fe	487	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	488	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	489
mbed_official	340:28d1f895c6fe	490	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	491	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	492
mbed_official	340:28d1f895c6fe	493	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	494	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	495
mbed_official	340:28d1f895c6fe	496	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	497	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	498
mbed_official	340:28d1f895c6fe	499	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	500	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	501
mbed_official	340:28d1f895c6fe	502	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	503	#endif /* STM32F051x8 \|\| STM32F058xx */
mbed_official	340:28d1f895c6fe	504
mbed_official	340:28d1f895c6fe	505	#if defined(STM32F071xB)
mbed_official	340:28d1f895c6fe	506	typedef struct
mbed_official	340:28d1f895c6fe	507	{
mbed_official	340:28d1f895c6fe	508	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	509	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	510
mbed_official	340:28d1f895c6fe	511	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	512	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	513
mbed_official	340:28d1f895c6fe	514	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	515	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	516
mbed_official	340:28d1f895c6fe	517	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	340:28d1f895c6fe	518	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
mbed_official	340:28d1f895c6fe	519
mbed_official	340:28d1f895c6fe	520	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	521	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	522
mbed_official	340:28d1f895c6fe	523	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	524	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	525
mbed_official	340:28d1f895c6fe	526	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	527	#endif /* STM32F071xB */
mbed_official	340:28d1f895c6fe	528
mbed_official	340:28d1f895c6fe	529	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	340:28d1f895c6fe	530	typedef struct
mbed_official	340:28d1f895c6fe	531	{
mbed_official	340:28d1f895c6fe	532	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	533	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	534
mbed_official	340:28d1f895c6fe	535	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	536	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	537
mbed_official	340:28d1f895c6fe	538	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	539	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	540
mbed_official	340:28d1f895c6fe	541	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	340:28d1f895c6fe	542	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
mbed_official	340:28d1f895c6fe	543
mbed_official	340:28d1f895c6fe	544	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	545	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	546
mbed_official	340:28d1f895c6fe	547	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	548	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	549
mbed_official	340:28d1f895c6fe	550	uint32_t UsbClockSelection; /*!< USB clock source
mbed_official	340:28d1f895c6fe	551	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	340:28d1f895c6fe	552
mbed_official	340:28d1f895c6fe	553	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	554	#endif /* STM32F072xB \|\| STM32F078xx */
mbed_official	340:28d1f895c6fe	555
mbed_official	340:28d1f895c6fe	556
mbed_official	340:28d1f895c6fe	557	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	558	typedef struct
mbed_official	340:28d1f895c6fe	559	{
mbed_official	340:28d1f895c6fe	560	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	561	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	562
mbed_official	340:28d1f895c6fe	563	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	564	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	565
mbed_official	340:28d1f895c6fe	566	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	567	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	568
mbed_official	340:28d1f895c6fe	569	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	340:28d1f895c6fe	570	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
mbed_official	340:28d1f895c6fe	571
mbed_official	340:28d1f895c6fe	572	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	340:28d1f895c6fe	573	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
mbed_official	340:28d1f895c6fe	574
mbed_official	340:28d1f895c6fe	575	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	576	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	577
mbed_official	340:28d1f895c6fe	578	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	579	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	580
mbed_official	340:28d1f895c6fe	581	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	582	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	583
mbed_official	630:825f75ca301e	584	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	585	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	586	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	587
mbed_official	340:28d1f895c6fe	588	/**
mbed_official	340:28d1f895c6fe	589	* @brief RCC_CRS Init structure definition
mbed_official	340:28d1f895c6fe	590	*/
mbed_official	340:28d1f895c6fe	591	typedef struct
mbed_official	340:28d1f895c6fe	592	{
mbed_official	340:28d1f895c6fe	593	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
mbed_official	340:28d1f895c6fe	594	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
mbed_official	340:28d1f895c6fe	595
mbed_official	340:28d1f895c6fe	596	uint32_t Source; /*!< Specifies the SYNC signal source.
mbed_official	340:28d1f895c6fe	597	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
mbed_official	340:28d1f895c6fe	598
mbed_official	340:28d1f895c6fe	599	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
mbed_official	340:28d1f895c6fe	600	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
mbed_official	340:28d1f895c6fe	601
mbed_official	340:28d1f895c6fe	602	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
mbed_official	340:28d1f895c6fe	603	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
mbed_official	340:28d1f895c6fe	604	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
mbed_official	340:28d1f895c6fe	605
mbed_official	340:28d1f895c6fe	606	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
mbed_official	340:28d1f895c6fe	607	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
mbed_official	340:28d1f895c6fe	608
mbed_official	340:28d1f895c6fe	609	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
mbed_official	340:28d1f895c6fe	610	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
mbed_official	340:28d1f895c6fe	611
mbed_official	340:28d1f895c6fe	612	}RCC_CRSInitTypeDef;
mbed_official	340:28d1f895c6fe	613
mbed_official	340:28d1f895c6fe	614	/**
mbed_official	340:28d1f895c6fe	615	* @brief RCC_CRS Synchronization structure definition
mbed_official	340:28d1f895c6fe	616	*/
mbed_official	340:28d1f895c6fe	617	typedef struct
mbed_official	340:28d1f895c6fe	618	{
mbed_official	340:28d1f895c6fe	619	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
mbed_official	340:28d1f895c6fe	620	This parameter must be a number between 0 and 0xFFFF*/
mbed_official	340:28d1f895c6fe	621
mbed_official	340:28d1f895c6fe	622	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
mbed_official	340:28d1f895c6fe	623	This parameter must be a number between 0 and 0x3F */
mbed_official	340:28d1f895c6fe	624
mbed_official	340:28d1f895c6fe	625	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
mbed_official	340:28d1f895c6fe	626	value latched in the time of the last SYNC event.
mbed_official	340:28d1f895c6fe	627	This parameter must be a number between 0 and 0xFFFF */
mbed_official	340:28d1f895c6fe	628
mbed_official	340:28d1f895c6fe	629	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
mbed_official	340:28d1f895c6fe	630	frequency error counter latched in the time of the last SYNC event.
mbed_official	340:28d1f895c6fe	631	It shows whether the actual frequency is below or above the target.
mbed_official	340:28d1f895c6fe	632	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
mbed_official	340:28d1f895c6fe	633
mbed_official	340:28d1f895c6fe	634	}RCC_CRSSynchroInfoTypeDef;
mbed_official	340:28d1f895c6fe	635
mbed_official	441:d2c15dda23c1	636	#endif /* STM32F042x6 \|\| STM32F048xx */
mbed_official	340:28d1f895c6fe	637	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	638	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	639
mbed_official	340:28d1f895c6fe	640	/**
mbed_official	340:28d1f895c6fe	641	* @}
mbed_official	340:28d1f895c6fe	642	*/
mbed_official	340:28d1f895c6fe	643
mbed_official	340:28d1f895c6fe	644	/* Exported constants --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	645
mbed_official	340:28d1f895c6fe	646	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
mbed_official	340:28d1f895c6fe	647	* @{
mbed_official	340:28d1f895c6fe	648	*/
mbed_official	340:28d1f895c6fe	649
mbed_official	630:825f75ca301e	650	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	651	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	652	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	653	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
mbed_official	630:825f75ca301e	654	* @{
mbed_official	630:825f75ca301e	655	*/
mbed_official	630:825f75ca301e	656	#define RCC_HSI48_OFF ((uint8_t)0x00)
mbed_official	630:825f75ca301e	657	#define RCC_HSI48_ON ((uint8_t)0x01)
mbed_official	630:825f75ca301e	658
mbed_official	630:825f75ca301e	659	/**
mbed_official	630:825f75ca301e	660	* @}
mbed_official	630:825f75ca301e	661	*/
mbed_official	630:825f75ca301e	662
mbed_official	441:d2c15dda23c1	663	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
mbed_official	441:d2c15dda23c1	664	* @{
mbed_official	441:d2c15dda23c1	665	*/
mbed_official	441:d2c15dda23c1	666	#define RCC_CRS_NONE ((uint32_t)0x00000000)
mbed_official	441:d2c15dda23c1	667	#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	668	#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	669	#define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	670	#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	671	#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	672	#define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	673
mbed_official	441:d2c15dda23c1	674	/**
mbed_official	441:d2c15dda23c1	675	* @}
mbed_official	441:d2c15dda23c1	676	*/
mbed_official	441:d2c15dda23c1	677
mbed_official	630:825f75ca301e	678	#else
mbed_official	630:825f75ca301e	679
mbed_official	630:825f75ca301e	680	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
mbed_official	630:825f75ca301e	681	* @{
mbed_official	630:825f75ca301e	682	*/
mbed_official	630:825f75ca301e	683	#define RCC_HSI48_OFF ((uint8_t)0x00)
mbed_official	630:825f75ca301e	684	/**
mbed_official	630:825f75ca301e	685	* @}
mbed_official	630:825f75ca301e	686	*/
mbed_official	630:825f75ca301e	687
mbed_official	630:825f75ca301e	688	#endif /* STM32F042x6 \|\| STM32F048xx */
mbed_official	630:825f75ca301e	689	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	690	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	691
mbed_official	340:28d1f895c6fe	692	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
mbed_official	340:28d1f895c6fe	693	* @{
mbed_official	340:28d1f895c6fe	694	*/
mbed_official	630:825f75ca301e	695	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
mbed_official	630:825f75ca301e	696	\|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	697	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	698	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	699	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	700
mbed_official	441:d2c15dda23c1	701	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
mbed_official	441:d2c15dda23c1	702	STM32F030xC */
mbed_official	441:d2c15dda23c1	703
mbed_official	441:d2c15dda23c1	704	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
mbed_official	441:d2c15dda23c1	705	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	706	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	707	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	441:d2c15dda23c1	708	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	441:d2c15dda23c1	709
mbed_official	441:d2c15dda23c1	710	#endif /* STM32F070x6 \|\| STM32F070xB */
mbed_official	340:28d1f895c6fe	711
mbed_official	340:28d1f895c6fe	712	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
mbed_official	340:28d1f895c6fe	713	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	714	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	715	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	716	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	717	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	340:28d1f895c6fe	718
mbed_official	340:28d1f895c6fe	719	#endif /* STM32F042x6 \|\| STM32F048xx */
mbed_official	340:28d1f895c6fe	720
mbed_official	340:28d1f895c6fe	721	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	340:28d1f895c6fe	722	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	723	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	724	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	725	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	726
mbed_official	340:28d1f895c6fe	727	#endif /* STM32F051x8 \|\| STM32F058xx */
mbed_official	340:28d1f895c6fe	728
mbed_official	340:28d1f895c6fe	729	#if defined(STM32F071xB)
mbed_official	340:28d1f895c6fe	730	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	731	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	340:28d1f895c6fe	732	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	733	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	734	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	735
mbed_official	340:28d1f895c6fe	736	#endif /* STM32F071xB */
mbed_official	340:28d1f895c6fe	737
mbed_official	340:28d1f895c6fe	738	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	340:28d1f895c6fe	739	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	740	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	340:28d1f895c6fe	741	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	742	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	743	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	744	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	340:28d1f895c6fe	745
mbed_official	340:28d1f895c6fe	746	#endif /* STM32F072xB \|\| STM32F078xx */
mbed_official	340:28d1f895c6fe	747
mbed_official	340:28d1f895c6fe	748	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	749	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	750	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	340:28d1f895c6fe	751	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	752	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	753	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	754	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
mbed_official	340:28d1f895c6fe	755
mbed_official	340:28d1f895c6fe	756	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	757
mbed_official	340:28d1f895c6fe	758	/**
mbed_official	340:28d1f895c6fe	759	* @}
mbed_official	340:28d1f895c6fe	760	*/
mbed_official	340:28d1f895c6fe	761
mbed_official	340:28d1f895c6fe	762	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	340:28d1f895c6fe	763
mbed_official	340:28d1f895c6fe	764	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
mbed_official	340:28d1f895c6fe	765	* @{
mbed_official	340:28d1f895c6fe	766	*/
mbed_official	340:28d1f895c6fe	767	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
mbed_official	340:28d1f895c6fe	768	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
mbed_official	340:28d1f895c6fe	769
mbed_official	340:28d1f895c6fe	770	/**
mbed_official	340:28d1f895c6fe	771	* @}
mbed_official	340:28d1f895c6fe	772	*/
mbed_official	340:28d1f895c6fe	773
mbed_official	340:28d1f895c6fe	774	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
mbed_official	340:28d1f895c6fe	775
mbed_official	441:d2c15dda23c1	776	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
mbed_official	441:d2c15dda23c1	777
mbed_official	441:d2c15dda23c1	778	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
mbed_official	441:d2c15dda23c1	779	* @{
mbed_official	441:d2c15dda23c1	780	*/
mbed_official	441:d2c15dda23c1	781	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
mbed_official	441:d2c15dda23c1	782
mbed_official	441:d2c15dda23c1	783	/**
mbed_official	441:d2c15dda23c1	784	* @}
mbed_official	441:d2c15dda23c1	785	*/
mbed_official	441:d2c15dda23c1	786
mbed_official	441:d2c15dda23c1	787	#endif /* STM32F070x6 \|\| STM32F070xB */
mbed_official	441:d2c15dda23c1	788
mbed_official	630:825f75ca301e	789	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	790	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	791
mbed_official	340:28d1f895c6fe	792	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
mbed_official	340:28d1f895c6fe	793	* @{
mbed_official	340:28d1f895c6fe	794	*/
mbed_official	340:28d1f895c6fe	795	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
mbed_official	340:28d1f895c6fe	796	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
mbed_official	340:28d1f895c6fe	797	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
mbed_official	340:28d1f895c6fe	798	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
mbed_official	340:28d1f895c6fe	799
mbed_official	340:28d1f895c6fe	800	/**
mbed_official	340:28d1f895c6fe	801	* @}
mbed_official	340:28d1f895c6fe	802	*/
mbed_official	340:28d1f895c6fe	803
mbed_official	340:28d1f895c6fe	804	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	805	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	806
mbed_official	340:28d1f895c6fe	807	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	808
mbed_official	340:28d1f895c6fe	809	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
mbed_official	340:28d1f895c6fe	810	* @{
mbed_official	340:28d1f895c6fe	811	*/
mbed_official	340:28d1f895c6fe	812	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
mbed_official	340:28d1f895c6fe	813	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
mbed_official	340:28d1f895c6fe	814	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
mbed_official	340:28d1f895c6fe	815	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
mbed_official	340:28d1f895c6fe	816
mbed_official	340:28d1f895c6fe	817	/**
mbed_official	340:28d1f895c6fe	818	* @}
mbed_official	340:28d1f895c6fe	819	*/
mbed_official	340:28d1f895c6fe	820
mbed_official	340:28d1f895c6fe	821	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	822
mbed_official	340:28d1f895c6fe	823
mbed_official	630:825f75ca301e	824	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	825	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	826	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	827	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	828
mbed_official	340:28d1f895c6fe	829	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
mbed_official	340:28d1f895c6fe	830	* @{
mbed_official	340:28d1f895c6fe	831	*/
mbed_official	340:28d1f895c6fe	832	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
mbed_official	340:28d1f895c6fe	833	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
mbed_official	340:28d1f895c6fe	834
mbed_official	340:28d1f895c6fe	835	/**
mbed_official	340:28d1f895c6fe	836	* @}
mbed_official	340:28d1f895c6fe	837	*/
mbed_official	340:28d1f895c6fe	838
mbed_official	340:28d1f895c6fe	839	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	840	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	841	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	842	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	843
mbed_official	340:28d1f895c6fe	844	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
mbed_official	340:28d1f895c6fe	845	* @{
mbed_official	340:28d1f895c6fe	846	*/
mbed_official	340:28d1f895c6fe	847
mbed_official	340:28d1f895c6fe	848	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	340:28d1f895c6fe	849
mbed_official	630:825f75ca301e	850	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
mbed_official	340:28d1f895c6fe	851
mbed_official	340:28d1f895c6fe	852	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
mbed_official	340:28d1f895c6fe	853
mbed_official	630:825f75ca301e	854	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	855	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	856	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	857	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	858
mbed_official	340:28d1f895c6fe	859	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
mbed_official	340:28d1f895c6fe	860	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
mbed_official	340:28d1f895c6fe	861	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
mbed_official	340:28d1f895c6fe	862	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
mbed_official	340:28d1f895c6fe	863	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
mbed_official	340:28d1f895c6fe	864	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
mbed_official	340:28d1f895c6fe	865	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
mbed_official	340:28d1f895c6fe	866	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
mbed_official	340:28d1f895c6fe	867
mbed_official	340:28d1f895c6fe	868	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	441:d2c15dda23c1	869	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070x6 \|\| STM32F070xB */
mbed_official	441:d2c15dda23c1	870	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	871
mbed_official	340:28d1f895c6fe	872	/**
mbed_official	340:28d1f895c6fe	873	* @}
mbed_official	340:28d1f895c6fe	874	*/
mbed_official	340:28d1f895c6fe	875
mbed_official	630:825f75ca301e	876	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	877	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	878	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	879
mbed_official	340:28d1f895c6fe	880	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
mbed_official	340:28d1f895c6fe	881	* @{
mbed_official	340:28d1f895c6fe	882	*/
mbed_official	340:28d1f895c6fe	883	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal soucre GPIO /
mbed_official	340:28d1f895c6fe	884	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
mbed_official	340:28d1f895c6fe	885	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
mbed_official	340:28d1f895c6fe	886
mbed_official	340:28d1f895c6fe	887	/**
mbed_official	340:28d1f895c6fe	888	* @}
mbed_official	340:28d1f895c6fe	889	*/
mbed_official	340:28d1f895c6fe	890
mbed_official	340:28d1f895c6fe	891	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
mbed_official	340:28d1f895c6fe	892	* @{
mbed_official	340:28d1f895c6fe	893	*/
mbed_official	340:28d1f895c6fe	894	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
mbed_official	340:28d1f895c6fe	895	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
mbed_official	340:28d1f895c6fe	896	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
mbed_official	340:28d1f895c6fe	897	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
mbed_official	340:28d1f895c6fe	898	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
mbed_official	340:28d1f895c6fe	899	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
mbed_official	340:28d1f895c6fe	900	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
mbed_official	340:28d1f895c6fe	901	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
mbed_official	340:28d1f895c6fe	902
mbed_official	340:28d1f895c6fe	903	/**
mbed_official	340:28d1f895c6fe	904	* @}
mbed_official	340:28d1f895c6fe	905	*/
mbed_official	340:28d1f895c6fe	906
mbed_official	340:28d1f895c6fe	907	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
mbed_official	340:28d1f895c6fe	908	* @{
mbed_official	340:28d1f895c6fe	909	*/
mbed_official	340:28d1f895c6fe	910	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
mbed_official	340:28d1f895c6fe	911	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
mbed_official	340:28d1f895c6fe	912
mbed_official	340:28d1f895c6fe	913	/**
mbed_official	340:28d1f895c6fe	914	* @}
mbed_official	340:28d1f895c6fe	915	*/
mbed_official	340:28d1f895c6fe	916
mbed_official	340:28d1f895c6fe	917	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
mbed_official	340:28d1f895c6fe	918	* @{
mbed_official	340:28d1f895c6fe	919	*/
mbed_official	340:28d1f895c6fe	920	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
mbed_official	340:28d1f895c6fe	921	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
mbed_official	340:28d1f895c6fe	922
mbed_official	340:28d1f895c6fe	923	/**
mbed_official	340:28d1f895c6fe	924	* @}
mbed_official	340:28d1f895c6fe	925	*/
mbed_official	340:28d1f895c6fe	926
mbed_official	340:28d1f895c6fe	927	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
mbed_official	340:28d1f895c6fe	928	* @{
mbed_official	340:28d1f895c6fe	929	*/
mbed_official	340:28d1f895c6fe	930	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
mbed_official	340:28d1f895c6fe	931
mbed_official	340:28d1f895c6fe	932	/**
mbed_official	340:28d1f895c6fe	933	* @}
mbed_official	340:28d1f895c6fe	934	*/
mbed_official	340:28d1f895c6fe	935
mbed_official	340:28d1f895c6fe	936	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
mbed_official	340:28d1f895c6fe	937	* @{
mbed_official	340:28d1f895c6fe	938	*/
mbed_official	340:28d1f895c6fe	939	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
mbed_official	340:28d1f895c6fe	940	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
mbed_official	340:28d1f895c6fe	941	corresponds to a higher output frequency */
mbed_official	340:28d1f895c6fe	942
mbed_official	340:28d1f895c6fe	943	/**
mbed_official	340:28d1f895c6fe	944	* @}
mbed_official	340:28d1f895c6fe	945	*/
mbed_official	340:28d1f895c6fe	946
mbed_official	340:28d1f895c6fe	947	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
mbed_official	340:28d1f895c6fe	948	* @{
mbed_official	340:28d1f895c6fe	949	*/
mbed_official	340:28d1f895c6fe	950	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
mbed_official	340:28d1f895c6fe	951	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
mbed_official	340:28d1f895c6fe	952
mbed_official	340:28d1f895c6fe	953	/**
mbed_official	340:28d1f895c6fe	954	* @}
mbed_official	340:28d1f895c6fe	955	*/
mbed_official	340:28d1f895c6fe	956
mbed_official	340:28d1f895c6fe	957	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
mbed_official	340:28d1f895c6fe	958	* @{
mbed_official	340:28d1f895c6fe	959	*/
mbed_official	340:28d1f895c6fe	960	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
mbed_official	340:28d1f895c6fe	961	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
mbed_official	340:28d1f895c6fe	962	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
mbed_official	340:28d1f895c6fe	963	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
mbed_official	340:28d1f895c6fe	964	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
mbed_official	340:28d1f895c6fe	965	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
mbed_official	340:28d1f895c6fe	966	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
mbed_official	340:28d1f895c6fe	967
mbed_official	340:28d1f895c6fe	968	/**
mbed_official	340:28d1f895c6fe	969	* @}
mbed_official	340:28d1f895c6fe	970	*/
mbed_official	340:28d1f895c6fe	971
mbed_official	340:28d1f895c6fe	972	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
mbed_official	340:28d1f895c6fe	973	* @{
mbed_official	340:28d1f895c6fe	974	*/
mbed_official	340:28d1f895c6fe	975	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
mbed_official	340:28d1f895c6fe	976	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
mbed_official	340:28d1f895c6fe	977	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
mbed_official	340:28d1f895c6fe	978	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
mbed_official	340:28d1f895c6fe	979	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
mbed_official	340:28d1f895c6fe	980	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
mbed_official	340:28d1f895c6fe	981	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
mbed_official	340:28d1f895c6fe	982
mbed_official	340:28d1f895c6fe	983	/**
mbed_official	340:28d1f895c6fe	984	* @}
mbed_official	340:28d1f895c6fe	985	*/
mbed_official	340:28d1f895c6fe	986
mbed_official	441:d2c15dda23c1	987	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	441:d2c15dda23c1	988	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	441:d2c15dda23c1	989	/* STM32F091xC \|\| STM32F098xx */
mbed_official	441:d2c15dda23c1	990
mbed_official	340:28d1f895c6fe	991	/**
mbed_official	340:28d1f895c6fe	992	* @}
mbed_official	340:28d1f895c6fe	993	*/
mbed_official	340:28d1f895c6fe	994
mbed_official	340:28d1f895c6fe	995	/* Exported macros ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	996	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
mbed_official	340:28d1f895c6fe	997	* @{
mbed_official	340:28d1f895c6fe	998	*/
mbed_official	340:28d1f895c6fe	999
mbed_official	340:28d1f895c6fe	1000	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
mbed_official	340:28d1f895c6fe	1001	* @brief Enables or disables the AHB1 peripheral clock.
mbed_official	340:28d1f895c6fe	1002	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	1003	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	1004	* using it.
mbed_official	340:28d1f895c6fe	1005	* @{
mbed_official	340:28d1f895c6fe	1006	*/
mbed_official	630:825f75ca301e	1007	#if defined(STM32F030x6) \|\| defined(STM32F030x8)\
mbed_official	630:825f75ca301e	1008	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1009	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1010	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1011
mbed_official	630:825f75ca301e	1012	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1013	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1014	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
mbed_official	630:825f75ca301e	1015	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1016	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
mbed_official	630:825f75ca301e	1017	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1018	} while(0)
mbed_official	340:28d1f895c6fe	1019
mbed_official	630:825f75ca301e	1020	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
mbed_official	340:28d1f895c6fe	1021
mbed_official	441:d2c15dda23c1	1022	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
mbed_official	441:d2c15dda23c1	1023	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1024	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	441:d2c15dda23c1	1025	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1026
mbed_official	630:825f75ca301e	1027	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1028	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1029
mbed_official	630:825f75ca301e	1030	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1031	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1032	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
mbed_official	630:825f75ca301e	1033	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1034	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
mbed_official	630:825f75ca301e	1035	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1036	} while(0)
mbed_official	340:28d1f895c6fe	1037
mbed_official	630:825f75ca301e	1038	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
mbed_official	340:28d1f895c6fe	1039
mbed_official	441:d2c15dda23c1	1040	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1041	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1042
mbed_official	630:825f75ca301e	1043	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1044	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1045	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1046	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1047
mbed_official	630:825f75ca301e	1048	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1049	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1050	SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
mbed_official	630:825f75ca301e	1051	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1052	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
mbed_official	630:825f75ca301e	1053	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1054	} while(0)
mbed_official	340:28d1f895c6fe	1055
mbed_official	630:825f75ca301e	1056	#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
mbed_official	340:28d1f895c6fe	1057
mbed_official	340:28d1f895c6fe	1058	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1059	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1060	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1061	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1062
mbed_official	340:28d1f895c6fe	1063	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1064
mbed_official	630:825f75ca301e	1065	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1066	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1067	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
mbed_official	630:825f75ca301e	1068	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1069	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
mbed_official	630:825f75ca301e	1070	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1071	} while(0)
mbed_official	340:28d1f895c6fe	1072
mbed_official	630:825f75ca301e	1073	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
mbed_official	340:28d1f895c6fe	1074
mbed_official	340:28d1f895c6fe	1075	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1076
mbed_official	340:28d1f895c6fe	1077	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	340:28d1f895c6fe	1078	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	1079	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	1080	* using it.
mbed_official	340:28d1f895c6fe	1081	*/
mbed_official	630:825f75ca301e	1082	#if defined(STM32F030x8)\
mbed_official	630:825f75ca301e	1083	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	1084	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1085	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1086	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	1087
mbed_official	630:825f75ca301e	1088	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1089	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1090	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
mbed_official	630:825f75ca301e	1091	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1092	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
mbed_official	630:825f75ca301e	1093	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1094	} while(0)
mbed_official	630:825f75ca301e	1095
mbed_official	630:825f75ca301e	1096	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
mbed_official	340:28d1f895c6fe	1097
mbed_official	630:825f75ca301e	1098	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	1099	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
mbed_official	630:825f75ca301e	1100	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	630:825f75ca301e	1101	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1102
mbed_official	630:825f75ca301e	1103	#if defined(STM32F030x8)\
mbed_official	630:825f75ca301e	1104	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1105	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1106	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1107	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	1108
mbed_official	630:825f75ca301e	1109	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1110	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1111	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
mbed_official	630:825f75ca301e	1112	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1113	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
mbed_official	630:825f75ca301e	1114	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1115	} while(0)
mbed_official	630:825f75ca301e	1116
mbed_official	630:825f75ca301e	1117	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	340:28d1f895c6fe	1118
mbed_official	340:28d1f895c6fe	1119	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1120	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	1121	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1122	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1123
mbed_official	630:825f75ca301e	1124	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
mbed_official	630:825f75ca301e	1125	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1126	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1127	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1128	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1129
mbed_official	630:825f75ca301e	1130	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1131	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1132	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
mbed_official	630:825f75ca301e	1133	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1134	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
mbed_official	630:825f75ca301e	1135	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1136	} while(0)
mbed_official	340:28d1f895c6fe	1137
mbed_official	630:825f75ca301e	1138	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
mbed_official	340:28d1f895c6fe	1139
mbed_official	340:28d1f895c6fe	1140	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
mbed_official	340:28d1f895c6fe	1141	/* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1142	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1143	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1144	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1145
mbed_official	630:825f75ca301e	1146	#if defined(STM32F030x8) \
mbed_official	630:825f75ca301e	1147	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1148	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1149	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1150
mbed_official	630:825f75ca301e	1151	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1152	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1153	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official	630:825f75ca301e	1154	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1155	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official	630:825f75ca301e	1156	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1157	} while(0)
mbed_official	630:825f75ca301e	1158	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1159	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1160	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
mbed_official	630:825f75ca301e	1161	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1162	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
mbed_official	630:825f75ca301e	1163	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1164	} while(0)
mbed_official	340:28d1f895c6fe	1165
mbed_official	630:825f75ca301e	1166	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official	630:825f75ca301e	1167	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	340:28d1f895c6fe	1168
mbed_official	340:28d1f895c6fe	1169	#endif /* STM32F030x8 \|\| */
mbed_official	340:28d1f895c6fe	1170	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	1171	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1172	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1173
mbed_official	630:825f75ca301e	1174	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1175	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1176	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1177
mbed_official	630:825f75ca301e	1178	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1179	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1180	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official	630:825f75ca301e	1181	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1182	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official	630:825f75ca301e	1183	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1184	} while(0)
mbed_official	340:28d1f895c6fe	1185
mbed_official	630:825f75ca301e	1186	#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official	340:28d1f895c6fe	1187
mbed_official	340:28d1f895c6fe	1188	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1189	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1190	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1191
mbed_official	630:825f75ca301e	1192	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1193	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1194	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1195	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1196
mbed_official	630:825f75ca301e	1197	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1198	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1199	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
mbed_official	630:825f75ca301e	1200	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1201	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
mbed_official	630:825f75ca301e	1202	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1203	} while(0)
mbed_official	340:28d1f895c6fe	1204
mbed_official	630:825f75ca301e	1205	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
mbed_official	340:28d1f895c6fe	1206
mbed_official	340:28d1f895c6fe	1207	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1208	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1209	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1210	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1211
mbed_official	630:825f75ca301e	1212	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1213	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1214
mbed_official	630:825f75ca301e	1215	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1216	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1217	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official	630:825f75ca301e	1218	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1219	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official	630:825f75ca301e	1220	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1221	} while(0)
mbed_official	630:825f75ca301e	1222	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1223	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1224	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
mbed_official	630:825f75ca301e	1225	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1226	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
mbed_official	630:825f75ca301e	1227	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1228	} while(0)
mbed_official	630:825f75ca301e	1229	#define __HAL_RCC_USART4_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1230	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1231	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
mbed_official	630:825f75ca301e	1232	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1233	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
mbed_official	630:825f75ca301e	1234	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1235	} while(0)
mbed_official	340:28d1f895c6fe	1236
mbed_official	630:825f75ca301e	1237	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official	630:825f75ca301e	1238	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
mbed_official	630:825f75ca301e	1239	#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
mbed_official	340:28d1f895c6fe	1240
mbed_official	441:d2c15dda23c1	1241	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1242	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1243
mbed_official	630:825f75ca301e	1244	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	1245	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
mbed_official	340:28d1f895c6fe	1246
mbed_official	630:825f75ca301e	1247	#define __HAL_RCC_USB_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1248	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1249	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
mbed_official	630:825f75ca301e	1250	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1251	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
mbed_official	630:825f75ca301e	1252	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1253	} while(0)
mbed_official	340:28d1f895c6fe	1254
mbed_official	630:825f75ca301e	1255	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
mbed_official	340:28d1f895c6fe	1256
mbed_official	441:d2c15dda23c1	1257	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
mbed_official	441:d2c15dda23c1	1258	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
mbed_official	340:28d1f895c6fe	1259
mbed_official	630:825f75ca301e	1260	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
mbed_official	630:825f75ca301e	1261	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1262
mbed_official	630:825f75ca301e	1263	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1264	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1265	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
mbed_official	630:825f75ca301e	1266	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1267	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
mbed_official	630:825f75ca301e	1268	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1269	} while(0)
mbed_official	630:825f75ca301e	1270	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
mbed_official	340:28d1f895c6fe	1271
mbed_official	340:28d1f895c6fe	1272	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
mbed_official	340:28d1f895c6fe	1273	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1274
mbed_official	630:825f75ca301e	1275	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1276	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1277	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1278
mbed_official	630:825f75ca301e	1279	#define __HAL_RCC_CRS_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1280	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1281	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
mbed_official	630:825f75ca301e	1282	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1283	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
mbed_official	630:825f75ca301e	1284	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1285	} while(0)
mbed_official	340:28d1f895c6fe	1286
mbed_official	630:825f75ca301e	1287	#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
mbed_official	340:28d1f895c6fe	1288
mbed_official	340:28d1f895c6fe	1289	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1290	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1291	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1292
mbed_official	441:d2c15dda23c1	1293	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1294
mbed_official	630:825f75ca301e	1295	#define __HAL_RCC_USART5_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1296	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1297	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
mbed_official	630:825f75ca301e	1298	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1299	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
mbed_official	630:825f75ca301e	1300	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1301	} while(0)
mbed_official	340:28d1f895c6fe	1302
mbed_official	630:825f75ca301e	1303	#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
mbed_official	340:28d1f895c6fe	1304
mbed_official	441:d2c15dda23c1	1305	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1306
mbed_official	340:28d1f895c6fe	1307	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	340:28d1f895c6fe	1308	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	1309	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	1310	* using it.
mbed_official	340:28d1f895c6fe	1311	*/
mbed_official	630:825f75ca301e	1312	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	1313	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1314	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1315	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1316
mbed_official	630:825f75ca301e	1317	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1318	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1319	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
mbed_official	630:825f75ca301e	1320	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1321	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
mbed_official	630:825f75ca301e	1322	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1323	} while(0)
mbed_official	340:28d1f895c6fe	1324
mbed_official	630:825f75ca301e	1325	#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
mbed_official	340:28d1f895c6fe	1326
mbed_official	441:d2c15dda23c1	1327	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
mbed_official	340:28d1f895c6fe	1328	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	1329	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1330	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	441:d2c15dda23c1	1331
mbed_official	441:d2c15dda23c1	1332	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	1333
mbed_official	630:825f75ca301e	1334	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1335	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1336	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
mbed_official	630:825f75ca301e	1337	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1338	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
mbed_official	630:825f75ca301e	1339	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1340	} while(0)
mbed_official	441:d2c15dda23c1	1341
mbed_official	630:825f75ca301e	1342	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
mbed_official	441:d2c15dda23c1	1343
mbed_official	441:d2c15dda23c1	1344	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1345
mbed_official	340:28d1f895c6fe	1346	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1347
mbed_official	630:825f75ca301e	1348	#define __HAL_RCC_USART7_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1349	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1350	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
mbed_official	630:825f75ca301e	1351	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1352	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
mbed_official	630:825f75ca301e	1353	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1354	} while(0)
mbed_official	630:825f75ca301e	1355	#define __HAL_RCC_USART8_CLK_ENABLE() do { \
mbed_official	630:825f75ca301e	1356	__IO uint32_t tmpreg; \
mbed_official	630:825f75ca301e	1357	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
mbed_official	630:825f75ca301e	1358	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	630:825f75ca301e	1359	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
mbed_official	630:825f75ca301e	1360	UNUSED(tmpreg); \
mbed_official	630:825f75ca301e	1361	} while(0)
mbed_official	340:28d1f895c6fe	1362
mbed_official	630:825f75ca301e	1363	#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
mbed_official	630:825f75ca301e	1364	#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
mbed_official	340:28d1f895c6fe	1365
mbed_official	340:28d1f895c6fe	1366	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1367
mbed_official	340:28d1f895c6fe	1368	/**
mbed_official	340:28d1f895c6fe	1369	* @}
mbed_official	340:28d1f895c6fe	1370	*/
mbed_official	340:28d1f895c6fe	1371
mbed_official	340:28d1f895c6fe	1372
mbed_official	340:28d1f895c6fe	1373	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
mbed_official	340:28d1f895c6fe	1374	* @brief Forces or releases peripheral reset.
mbed_official	340:28d1f895c6fe	1375	* @{
mbed_official	340:28d1f895c6fe	1376	*/
mbed_official	340:28d1f895c6fe	1377
mbed_official	340:28d1f895c6fe	1378	/** @brief Force or release AHB peripheral reset.
mbed_official	340:28d1f895c6fe	1379	*/
mbed_official	630:825f75ca301e	1380	#if defined(STM32F030x6) \|\| defined(STM32F030x8)\
mbed_official	630:825f75ca301e	1381	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1382	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1383	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1384
mbed_official	630:825f75ca301e	1385	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
mbed_official	340:28d1f895c6fe	1386
mbed_official	630:825f75ca301e	1387	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
mbed_official	340:28d1f895c6fe	1388
mbed_official	340:28d1f895c6fe	1389	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
mbed_official	340:28d1f895c6fe	1390	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	1391	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1392	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1393
mbed_official	630:825f75ca301e	1394	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1395	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1396
mbed_official	630:825f75ca301e	1397	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
mbed_official	340:28d1f895c6fe	1398
mbed_official	630:825f75ca301e	1399	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
mbed_official	340:28d1f895c6fe	1400
mbed_official	441:d2c15dda23c1	1401	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1402	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1403
mbed_official	630:825f75ca301e	1404	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1405	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1406	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1407	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1408
mbed_official	630:825f75ca301e	1409	#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
mbed_official	340:28d1f895c6fe	1410
mbed_official	630:825f75ca301e	1411	#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
mbed_official	340:28d1f895c6fe	1412
mbed_official	340:28d1f895c6fe	1413	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1414	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1415	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1416	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1417
mbed_official	340:28d1f895c6fe	1418	/** @brief Force or release APB1 peripheral reset.
mbed_official	340:28d1f895c6fe	1419	*/
mbed_official	630:825f75ca301e	1420	#if defined(STM32F030x8) \
mbed_official	630:825f75ca301e	1421	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	1422	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1423	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1424	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1425
mbed_official	630:825f75ca301e	1426	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
mbed_official	630:825f75ca301e	1427	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	340:28d1f895c6fe	1428
mbed_official	630:825f75ca301e	1429	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
mbed_official	630:825f75ca301e	1430	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	340:28d1f895c6fe	1431
mbed_official	441:d2c15dda23c1	1432	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
mbed_official	340:28d1f895c6fe	1433	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	1434	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1435	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1436
mbed_official	630:825f75ca301e	1437	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
mbed_official	630:825f75ca301e	1438	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1439	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1440	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1441	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1442
mbed_official	630:825f75ca301e	1443	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
mbed_official	340:28d1f895c6fe	1444
mbed_official	630:825f75ca301e	1445	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
mbed_official	340:28d1f895c6fe	1446
mbed_official	340:28d1f895c6fe	1447	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
mbed_official	340:28d1f895c6fe	1448	/* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1449	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1450	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1451	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1452
mbed_official	630:825f75ca301e	1453	#if defined(STM32F030x8) \
mbed_official	630:825f75ca301e	1454	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1455	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1456	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1457
mbed_official	630:825f75ca301e	1458	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
mbed_official	630:825f75ca301e	1459	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	340:28d1f895c6fe	1460
mbed_official	630:825f75ca301e	1461	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official	630:825f75ca301e	1462	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	340:28d1f895c6fe	1463
mbed_official	340:28d1f895c6fe	1464	#endif /* STM32F030x8 \|\| */
mbed_official	340:28d1f895c6fe	1465	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	1466	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1467	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1468
mbed_official	630:825f75ca301e	1469	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1470	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1471	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1472
mbed_official	630:825f75ca301e	1473	#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
mbed_official	340:28d1f895c6fe	1474
mbed_official	630:825f75ca301e	1475	#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official	340:28d1f895c6fe	1476
mbed_official	340:28d1f895c6fe	1477	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1478	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1479	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1480
mbed_official	630:825f75ca301e	1481	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1482	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1483	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1484	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1485
mbed_official	630:825f75ca301e	1486	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
mbed_official	340:28d1f895c6fe	1487
mbed_official	630:825f75ca301e	1488	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
mbed_official	340:28d1f895c6fe	1489
mbed_official	340:28d1f895c6fe	1490	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1491	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1492	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1493	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1494
mbed_official	630:825f75ca301e	1495	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1496	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1497
mbed_official	630:825f75ca301e	1498	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
mbed_official	630:825f75ca301e	1499	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
mbed_official	630:825f75ca301e	1500	#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
mbed_official	340:28d1f895c6fe	1501
mbed_official	630:825f75ca301e	1502	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official	630:825f75ca301e	1503	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
mbed_official	630:825f75ca301e	1504	#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
mbed_official	340:28d1f895c6fe	1505
mbed_official	441:d2c15dda23c1	1506	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1507	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1508
mbed_official	630:825f75ca301e	1509	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	1510	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
mbed_official	340:28d1f895c6fe	1511
mbed_official	630:825f75ca301e	1512	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
mbed_official	340:28d1f895c6fe	1513
mbed_official	630:825f75ca301e	1514	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
mbed_official	340:28d1f895c6fe	1515
mbed_official	441:d2c15dda23c1	1516	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
mbed_official	441:d2c15dda23c1	1517	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
mbed_official	340:28d1f895c6fe	1518
mbed_official	630:825f75ca301e	1519	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
mbed_official	630:825f75ca301e	1520	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1521
mbed_official	630:825f75ca301e	1522	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
mbed_official	340:28d1f895c6fe	1523
mbed_official	630:825f75ca301e	1524	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
mbed_official	340:28d1f895c6fe	1525
mbed_official	340:28d1f895c6fe	1526	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
mbed_official	340:28d1f895c6fe	1527	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1528
mbed_official	630:825f75ca301e	1529	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1530	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1531	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1532
mbed_official	630:825f75ca301e	1533	#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
mbed_official	340:28d1f895c6fe	1534
mbed_official	630:825f75ca301e	1535	#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
mbed_official	340:28d1f895c6fe	1536
mbed_official	340:28d1f895c6fe	1537	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1538	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1539	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1540
mbed_official	441:d2c15dda23c1	1541	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1542
mbed_official	630:825f75ca301e	1543	#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
mbed_official	340:28d1f895c6fe	1544
mbed_official	630:825f75ca301e	1545	#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
mbed_official	340:28d1f895c6fe	1546
mbed_official	441:d2c15dda23c1	1547	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1548
mbed_official	340:28d1f895c6fe	1549
mbed_official	340:28d1f895c6fe	1550	/** @brief Force or release APB2 peripheral reset.
mbed_official	340:28d1f895c6fe	1551	*/
mbed_official	630:825f75ca301e	1552	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	1553	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1554	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1555	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1556
mbed_official	630:825f75ca301e	1557	#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
mbed_official	340:28d1f895c6fe	1558
mbed_official	630:825f75ca301e	1559	#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
mbed_official	340:28d1f895c6fe	1560
mbed_official	441:d2c15dda23c1	1561	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
mbed_official	340:28d1f895c6fe	1562	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	1563	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1564	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	441:d2c15dda23c1	1565
mbed_official	441:d2c15dda23c1	1566	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	1567
mbed_official	630:825f75ca301e	1568	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
mbed_official	441:d2c15dda23c1	1569
mbed_official	630:825f75ca301e	1570	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
mbed_official	441:d2c15dda23c1	1571
mbed_official	441:d2c15dda23c1	1572	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1573
mbed_official	340:28d1f895c6fe	1574	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1575
mbed_official	630:825f75ca301e	1576	#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART7RST))
mbed_official	630:825f75ca301e	1577	#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART8RST))
mbed_official	340:28d1f895c6fe	1578
mbed_official	630:825f75ca301e	1579	#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
mbed_official	630:825f75ca301e	1580	#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
mbed_official	340:28d1f895c6fe	1581
mbed_official	340:28d1f895c6fe	1582	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1583
mbed_official	340:28d1f895c6fe	1584	/**
mbed_official	340:28d1f895c6fe	1585	* @}
mbed_official	340:28d1f895c6fe	1586	*/
mbed_official	630:825f75ca301e	1587
mbed_official	630:825f75ca301e	1588	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
mbed_official	630:825f75ca301e	1589	* @brief Get the enable or disable status of peripheral clock.
mbed_official	630:825f75ca301e	1590	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	630:825f75ca301e	1591	* is disabled and the application software has to enable this clock before
mbed_official	630:825f75ca301e	1592	* using it.
mbed_official	630:825f75ca301e	1593	* @{
mbed_official	630:825f75ca301e	1594	*/
mbed_official	630:825f75ca301e	1595	/** @brief AHB Peripheral Clock Enable Disable Status
mbed_official	630:825f75ca301e	1596	*/
mbed_official	630:825f75ca301e	1597	#if defined(STM32F030x6) \|\| defined(STM32F030x8)\
mbed_official	630:825f75ca301e	1598	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1599	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1600	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	1601
mbed_official	630:825f75ca301e	1602	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
mbed_official	630:825f75ca301e	1603	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
mbed_official	630:825f75ca301e	1604
mbed_official	630:825f75ca301e	1605	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
mbed_official	630:825f75ca301e	1606	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070xB \|\| */
mbed_official	630:825f75ca301e	1607	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	1608	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	630:825f75ca301e	1609
mbed_official	630:825f75ca301e	1610	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1611	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	1612
mbed_official	630:825f75ca301e	1613	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
mbed_official	630:825f75ca301e	1614	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
mbed_official	630:825f75ca301e	1615
mbed_official	630:825f75ca301e	1616	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	630:825f75ca301e	1617	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	630:825f75ca301e	1618
mbed_official	630:825f75ca301e	1619	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1620	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1621	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1622	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	1623
mbed_official	630:825f75ca301e	1624	#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
mbed_official	630:825f75ca301e	1625	#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
mbed_official	630:825f75ca301e	1626
mbed_official	630:825f75ca301e	1627	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	1628	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	630:825f75ca301e	1629	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	1630	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	1631
mbed_official	630:825f75ca301e	1632	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	1633
mbed_official	630:825f75ca301e	1634	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
mbed_official	630:825f75ca301e	1635	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
mbed_official	630:825f75ca301e	1636
mbed_official	630:825f75ca301e	1637	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	1638
mbed_official	630:825f75ca301e	1639	/** @brief APB1 Peripheral Clock Enable Disable Status
mbed_official	630:825f75ca301e	1640	*/
mbed_official	630:825f75ca301e	1641	#if defined(STM32F030x8)\
mbed_official	630:825f75ca301e	1642	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	1643	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1644	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1645	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	1646
mbed_official	630:825f75ca301e	1647	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
mbed_official	630:825f75ca301e	1648	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
mbed_official	630:825f75ca301e	1649
mbed_official	630:825f75ca301e	1650	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	1651	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
mbed_official	630:825f75ca301e	1652	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	630:825f75ca301e	1653	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	630:825f75ca301e	1654
mbed_official	630:825f75ca301e	1655	#if defined(STM32F030x8)\
mbed_official	630:825f75ca301e	1656	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1657	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1658	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1659	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	1660
mbed_official	630:825f75ca301e	1661	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
mbed_official	630:825f75ca301e	1662	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
mbed_official	630:825f75ca301e	1663
mbed_official	630:825f75ca301e	1664	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	1665	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	630:825f75ca301e	1666	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	630:825f75ca301e	1667	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	630:825f75ca301e	1668
mbed_official	630:825f75ca301e	1669	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
mbed_official	630:825f75ca301e	1670	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1671	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1672	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1673	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	1674
mbed_official	630:825f75ca301e	1675	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
mbed_official	630:825f75ca301e	1676	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
mbed_official	630:825f75ca301e	1677
mbed_official	630:825f75ca301e	1678	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
mbed_official	630:825f75ca301e	1679	/* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	1680	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	630:825f75ca301e	1681	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	1682	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	1683
mbed_official	630:825f75ca301e	1684	#if defined(STM32F030x8) \
mbed_official	630:825f75ca301e	1685	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1686	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1687	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	1688
mbed_official	630:825f75ca301e	1689	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
mbed_official	630:825f75ca301e	1690	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
mbed_official	630:825f75ca301e	1691	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
mbed_official	630:825f75ca301e	1692	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
mbed_official	630:825f75ca301e	1693
mbed_official	630:825f75ca301e	1694	#endif /* STM32F030x8 \|\| */
mbed_official	630:825f75ca301e	1695	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	630:825f75ca301e	1696	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	630:825f75ca301e	1697	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	630:825f75ca301e	1698
mbed_official	630:825f75ca301e	1699	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1700	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1701	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	1702
mbed_official	630:825f75ca301e	1703	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
mbed_official	630:825f75ca301e	1704	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
mbed_official	630:825f75ca301e	1705
mbed_official	630:825f75ca301e	1706	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	630:825f75ca301e	1707	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	1708	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	1709
mbed_official	630:825f75ca301e	1710	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1711	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1712	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1713	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	1714
mbed_official	630:825f75ca301e	1715	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
mbed_official	630:825f75ca301e	1716	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
mbed_official	630:825f75ca301e	1717
mbed_official	630:825f75ca301e	1718	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	1719	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	630:825f75ca301e	1720	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	1721	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	1722
mbed_official	630:825f75ca301e	1723	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1724	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	1725
mbed_official	630:825f75ca301e	1726	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
mbed_official	630:825f75ca301e	1727	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
mbed_official	630:825f75ca301e	1728	#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET)
mbed_official	630:825f75ca301e	1729	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
mbed_official	630:825f75ca301e	1730	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
mbed_official	630:825f75ca301e	1731	#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET)
mbed_official	630:825f75ca301e	1732
mbed_official	630:825f75ca301e	1733	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	630:825f75ca301e	1734	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	630:825f75ca301e	1735
mbed_official	630:825f75ca301e	1736	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	1737	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
mbed_official	630:825f75ca301e	1738
mbed_official	630:825f75ca301e	1739	#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
mbed_official	630:825f75ca301e	1740	#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
mbed_official	630:825f75ca301e	1741
mbed_official	630:825f75ca301e	1742	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
mbed_official	630:825f75ca301e	1743	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
mbed_official	630:825f75ca301e	1744
mbed_official	630:825f75ca301e	1745	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
mbed_official	630:825f75ca301e	1746	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	1747
mbed_official	630:825f75ca301e	1748	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
mbed_official	630:825f75ca301e	1749	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
mbed_official	630:825f75ca301e	1750
mbed_official	630:825f75ca301e	1751	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
mbed_official	630:825f75ca301e	1752	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	1753
mbed_official	630:825f75ca301e	1754	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1755	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1756	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	1757
mbed_official	630:825f75ca301e	1758	#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET)
mbed_official	630:825f75ca301e	1759	#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET)
mbed_official	630:825f75ca301e	1760
mbed_official	630:825f75ca301e	1761	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	630:825f75ca301e	1762	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	630:825f75ca301e	1763	/* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	1764
mbed_official	630:825f75ca301e	1765	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	1766
mbed_official	630:825f75ca301e	1767	#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET)
mbed_official	630:825f75ca301e	1768	#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET)
mbed_official	630:825f75ca301e	1769
mbed_official	630:825f75ca301e	1770	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	630:825f75ca301e	1771
mbed_official	630:825f75ca301e	1772	/** @brief APB1 Peripheral Clock Enable Disable Status
mbed_official	630:825f75ca301e	1773	*/
mbed_official	630:825f75ca301e	1774	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	1775	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1776	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1777	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	1778
mbed_official	630:825f75ca301e	1779	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
mbed_official	630:825f75ca301e	1780	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
mbed_official	630:825f75ca301e	1781
mbed_official	630:825f75ca301e	1782	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
mbed_official	630:825f75ca301e	1783	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	630:825f75ca301e	1784	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	630:825f75ca301e	1785	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	630:825f75ca301e	1786
mbed_official	630:825f75ca301e	1787	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	630:825f75ca301e	1788
mbed_official	630:825f75ca301e	1789	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
mbed_official	630:825f75ca301e	1790	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
mbed_official	630:825f75ca301e	1791
mbed_official	630:825f75ca301e	1792	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	630:825f75ca301e	1793
mbed_official	630:825f75ca301e	1794	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	630:825f75ca301e	1795
mbed_official	630:825f75ca301e	1796	#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET)
mbed_official	630:825f75ca301e	1797	#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET)
mbed_official	630:825f75ca301e	1798	#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET)
mbed_official	630:825f75ca301e	1799	#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET)
mbed_official	630:825f75ca301e	1800
mbed_official	630:825f75ca301e	1801	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	630:825f75ca301e	1802	/**
mbed_official	630:825f75ca301e	1803	* @}
mbed_official	630:825f75ca301e	1804	*/
mbed_official	630:825f75ca301e	1805
mbed_official	340:28d1f895c6fe	1806
mbed_official	340:28d1f895c6fe	1807	/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
mbed_official	340:28d1f895c6fe	1808	* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
mbed_official	340:28d1f895c6fe	1809	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	340:28d1f895c6fe	1810	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
mbed_official	340:28d1f895c6fe	1811	* you have to select another source of the system clock then stop the HSI14.
mbed_official	340:28d1f895c6fe	1812	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
mbed_official	340:28d1f895c6fe	1813	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
mbed_official	340:28d1f895c6fe	1814	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
mbed_official	340:28d1f895c6fe	1815	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
mbed_official	340:28d1f895c6fe	1816	* clock cycles.
mbed_official	340:28d1f895c6fe	1817	* @{
mbed_official	340:28d1f895c6fe	1818	*/
mbed_official	630:825f75ca301e	1819	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1820	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1821	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1822
mbed_official	340:28d1f895c6fe	1823	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
mbed_official	340:28d1f895c6fe	1824	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
mbed_official	340:28d1f895c6fe	1825
mbed_official	340:28d1f895c6fe	1826	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
mbed_official	340:28d1f895c6fe	1827	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1828	* @arg RCC_HSI48_ON: HSI48 enabled
mbed_official	340:28d1f895c6fe	1829	* @arg RCC_HSI48_OFF: HSI48 disabled
mbed_official	340:28d1f895c6fe	1830	*/
mbed_official	340:28d1f895c6fe	1831	#define __HAL_RCC_GET_HSI48_STATE() \
mbed_official	340:28d1f895c6fe	1832	(((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
mbed_official	340:28d1f895c6fe	1833
mbed_official	340:28d1f895c6fe	1834	#else
mbed_official	340:28d1f895c6fe	1835
mbed_official	340:28d1f895c6fe	1836	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
mbed_official	340:28d1f895c6fe	1837	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1838	* @arg RCC_HSI_OFF: HSI48 disabled
mbed_official	340:28d1f895c6fe	1839	*/
mbed_official	340:28d1f895c6fe	1840	#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
mbed_official	340:28d1f895c6fe	1841
mbed_official	340:28d1f895c6fe	1842	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1843	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1844	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1845
mbed_official	340:28d1f895c6fe	1846	/**
mbed_official	340:28d1f895c6fe	1847	* @}
mbed_official	340:28d1f895c6fe	1848	*/
mbed_official	340:28d1f895c6fe	1849
mbed_official	340:28d1f895c6fe	1850	/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
mbed_official	340:28d1f895c6fe	1851	* @{
mbed_official	340:28d1f895c6fe	1852	*/
mbed_official	630:825f75ca301e	1853	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1854	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1855	\|\| defined(STM32F070x6) \|\| defined(STM32F070xB)
mbed_official	340:28d1f895c6fe	1856
mbed_official	340:28d1f895c6fe	1857	/** @brief Macro to configure the USB clock (USBCLK).
mbed_official	340:28d1f895c6fe	1858	* @param __USBCLKSource__: specifies the USB clock source.
mbed_official	340:28d1f895c6fe	1859	* This parameter can be one of the following values:
mbed_official	441:d2c15dda23c1	1860	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
mbed_official	340:28d1f895c6fe	1861	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
mbed_official	340:28d1f895c6fe	1862	*/
mbed_official	340:28d1f895c6fe	1863	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
mbed_official	340:28d1f895c6fe	1864	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
mbed_official	340:28d1f895c6fe	1865
mbed_official	340:28d1f895c6fe	1866	/** @brief Macro to get the USB clock source.
mbed_official	340:28d1f895c6fe	1867	* @retval The clock source can be one of the following values:
mbed_official	630:825f75ca301e	1868	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
mbed_official	340:28d1f895c6fe	1869	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
mbed_official	340:28d1f895c6fe	1870	*/
mbed_official	340:28d1f895c6fe	1871	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
mbed_official	340:28d1f895c6fe	1872
mbed_official	340:28d1f895c6fe	1873	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	441:d2c15dda23c1	1874	/* STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	441:d2c15dda23c1	1875	/* STM32F070x6 \|\| STM32F070xB */
mbed_official	340:28d1f895c6fe	1876
mbed_official	630:825f75ca301e	1877	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	1878	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
mbed_official	630:825f75ca301e	1879	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1880	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1881
mbed_official	340:28d1f895c6fe	1882	/** @brief Macro to configure the CEC clock.
mbed_official	340:28d1f895c6fe	1883	* @param __CECCLKSource__: specifies the CEC clock source.
mbed_official	340:28d1f895c6fe	1884	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1885	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
mbed_official	340:28d1f895c6fe	1886	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official	340:28d1f895c6fe	1887	*/
mbed_official	340:28d1f895c6fe	1888	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
mbed_official	340:28d1f895c6fe	1889	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
mbed_official	340:28d1f895c6fe	1890
mbed_official	340:28d1f895c6fe	1891	/** @brief Macro to get the HDMI CEC clock source.
mbed_official	340:28d1f895c6fe	1892	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1893	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
mbed_official	340:28d1f895c6fe	1894	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official	340:28d1f895c6fe	1895	*/
mbed_official	340:28d1f895c6fe	1896	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
mbed_official	340:28d1f895c6fe	1897
mbed_official	340:28d1f895c6fe	1898	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1899	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1900	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1901	/* STM32F091xC \|\| defined(STM32F098xx) */
mbed_official	340:28d1f895c6fe	1902
mbed_official	630:825f75ca301e	1903	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
mbed_official	630:825f75ca301e	1904	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
mbed_official	630:825f75ca301e	1905	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
mbed_official	630:825f75ca301e	1906	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1907
mbed_official	340:28d1f895c6fe	1908	/** @brief Macro to configure the MCO clock.
mbed_official	340:28d1f895c6fe	1909	* @param __MCOCLKSource__: specifies the MCO clock source.
mbed_official	340:28d1f895c6fe	1910	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1911	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
mbed_official	340:28d1f895c6fe	1912	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
mbed_official	340:28d1f895c6fe	1913	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
mbed_official	340:28d1f895c6fe	1914	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
mbed_official	340:28d1f895c6fe	1915	* @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
mbed_official	340:28d1f895c6fe	1916	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
mbed_official	340:28d1f895c6fe	1917	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
mbed_official	340:28d1f895c6fe	1918	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
mbed_official	340:28d1f895c6fe	1919	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
mbed_official	340:28d1f895c6fe	1920	* @param __MCODiv__: specifies the MCO clock prescaler.
mbed_official	340:28d1f895c6fe	1921	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1922	* @arg RCC_MCO_DIV1: MCO clock source is divided by 1
mbed_official	340:28d1f895c6fe	1923	* @arg RCC_MCO_DIV2: MCO clock source is divided by 2
mbed_official	340:28d1f895c6fe	1924	* @arg RCC_MCO_DIV4: MCO clock source is divided by 4
mbed_official	340:28d1f895c6fe	1925	* @arg RCC_MCO_DIV8: MCO clock source is divided by 8
mbed_official	340:28d1f895c6fe	1926	* @arg RCC_MCO_DIV16: MCO clock source is divided by 16
mbed_official	340:28d1f895c6fe	1927	* @arg RCC_MCO_DIV32: MCO clock source is divided by 32
mbed_official	340:28d1f895c6fe	1928	* @arg RCC_MCO_DIV64: MCO clock source is divided by 64
mbed_official	340:28d1f895c6fe	1929	* @arg RCC_MCO_DIV128: MCO clock source is divided by 128
mbed_official	340:28d1f895c6fe	1930	*/
mbed_official	340:28d1f895c6fe	1931	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
mbed_official	340:28d1f895c6fe	1932	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
mbed_official	340:28d1f895c6fe	1933	#else
mbed_official	340:28d1f895c6fe	1934
mbed_official	340:28d1f895c6fe	1935	/** @brief Macro to configure the MCO clock.
mbed_official	340:28d1f895c6fe	1936	* @param __MCOCLKSource__: specifies the MCO clock source.
mbed_official	340:28d1f895c6fe	1937	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1938	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
mbed_official	340:28d1f895c6fe	1939	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
mbed_official	340:28d1f895c6fe	1940	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
mbed_official	340:28d1f895c6fe	1941	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
mbed_official	340:28d1f895c6fe	1942	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
mbed_official	340:28d1f895c6fe	1943	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
mbed_official	340:28d1f895c6fe	1944	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
mbed_official	340:28d1f895c6fe	1945	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
mbed_official	340:28d1f895c6fe	1946	* @param __MCODiv__: specifies the MCO clock prescaler.
mbed_official	340:28d1f895c6fe	1947	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1948	* @arg RCC_MCODIV_1: No division applied on MCO clock source
mbed_official	340:28d1f895c6fe	1949	*/
mbed_official	340:28d1f895c6fe	1950	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
mbed_official	340:28d1f895c6fe	1951	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
mbed_official	340:28d1f895c6fe	1952
mbed_official	441:d2c15dda23c1	1953	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| */
mbed_official	441:d2c15dda23c1	1954	/* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	441:d2c15dda23c1	1955	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1956	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	441:d2c15dda23c1	1957
mbed_official	630:825f75ca301e	1958	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	1959	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	441:d2c15dda23c1	1960	/** @brief Macro to configure the USART2 clock (USART2CLK).
mbed_official	441:d2c15dda23c1	1961	* @param __USART2CLKSource__: specifies the USART2 clock source.
mbed_official	441:d2c15dda23c1	1962	* This parameter can be one of the following values:
mbed_official	441:d2c15dda23c1	1963	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
mbed_official	441:d2c15dda23c1	1964	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
mbed_official	441:d2c15dda23c1	1965	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
mbed_official	441:d2c15dda23c1	1966	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
mbed_official	441:d2c15dda23c1	1967	*/
mbed_official	441:d2c15dda23c1	1968	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
mbed_official	441:d2c15dda23c1	1969	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
mbed_official	441:d2c15dda23c1	1970
mbed_official	441:d2c15dda23c1	1971	/** @brief Macro to get the USART2 clock source.
mbed_official	441:d2c15dda23c1	1972	* @retval The clock source can be one of the following values:
mbed_official	441:d2c15dda23c1	1973	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
mbed_official	441:d2c15dda23c1	1974	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
mbed_official	441:d2c15dda23c1	1975	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
mbed_official	441:d2c15dda23c1	1976	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
mbed_official	441:d2c15dda23c1	1977	*/
mbed_official	441:d2c15dda23c1	1978	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
mbed_official	441:d2c15dda23c1	1979	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx*/
mbed_official	340:28d1f895c6fe	1980
mbed_official	340:28d1f895c6fe	1981	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1982	/** @brief Macro to configure the USART3 clock (USART3CLK).
mbed_official	340:28d1f895c6fe	1983	* @param __USART3CLKSource__: specifies the USART3 clock source.
mbed_official	340:28d1f895c6fe	1984	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1985	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
mbed_official	340:28d1f895c6fe	1986	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
mbed_official	340:28d1f895c6fe	1987	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
mbed_official	340:28d1f895c6fe	1988	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
mbed_official	340:28d1f895c6fe	1989	*/
mbed_official	340:28d1f895c6fe	1990	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
mbed_official	340:28d1f895c6fe	1991	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
mbed_official	340:28d1f895c6fe	1992
mbed_official	340:28d1f895c6fe	1993	/** @brief Macro to get the USART3 clock source.
mbed_official	340:28d1f895c6fe	1994	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1995	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
mbed_official	340:28d1f895c6fe	1996	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
mbed_official	340:28d1f895c6fe	1997	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
mbed_official	340:28d1f895c6fe	1998	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
mbed_official	340:28d1f895c6fe	1999	*/
mbed_official	340:28d1f895c6fe	2000	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
mbed_official	340:28d1f895c6fe	2001
mbed_official	441:d2c15dda23c1	2002	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	2003	/**
mbed_official	340:28d1f895c6fe	2004	* @}
mbed_official	340:28d1f895c6fe	2005	*/
mbed_official	340:28d1f895c6fe	2006
mbed_official	630:825f75ca301e	2007	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	2008	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	2009	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	2010
mbed_official	340:28d1f895c6fe	2011	/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
mbed_official	340:28d1f895c6fe	2012	* @{
mbed_official	340:28d1f895c6fe	2013	*/
mbed_official	340:28d1f895c6fe	2014	/* Interrupt & Flag management */
mbed_official	340:28d1f895c6fe	2015
mbed_official	340:28d1f895c6fe	2016	/**
mbed_official	340:28d1f895c6fe	2017	* @brief Enables the specified CRS interrupts.
mbed_official	340:28d1f895c6fe	2018	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
mbed_official	340:28d1f895c6fe	2019	* This parameter can be any combination of the following values:
mbed_official	340:28d1f895c6fe	2020	* @arg RCC_CRS_IT_SYNCOK
mbed_official	340:28d1f895c6fe	2021	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	340:28d1f895c6fe	2022	* @arg RCC_CRS_IT_ERR
mbed_official	340:28d1f895c6fe	2023	* @arg RCC_CRS_IT_ESYNC
mbed_official	340:28d1f895c6fe	2024	* @retval None
mbed_official	340:28d1f895c6fe	2025	*/
mbed_official	340:28d1f895c6fe	2026	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
mbed_official	340:28d1f895c6fe	2027
mbed_official	340:28d1f895c6fe	2028	/**
mbed_official	340:28d1f895c6fe	2029	* @brief Disables the specified CRS interrupts.
mbed_official	340:28d1f895c6fe	2030	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
mbed_official	340:28d1f895c6fe	2031	* This parameter can be any combination of the following values:
mbed_official	340:28d1f895c6fe	2032	* @arg RCC_CRS_IT_SYNCOK
mbed_official	340:28d1f895c6fe	2033	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	340:28d1f895c6fe	2034	* @arg RCC_CRS_IT_ERR
mbed_official	340:28d1f895c6fe	2035	* @arg RCC_CRS_IT_ESYNC
mbed_official	340:28d1f895c6fe	2036	* @retval None
mbed_official	340:28d1f895c6fe	2037	*/
mbed_official	340:28d1f895c6fe	2038	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
mbed_official	340:28d1f895c6fe	2039
mbed_official	340:28d1f895c6fe	2040	/** @brief Check the CRS's interrupt has occurred or not.
mbed_official	340:28d1f895c6fe	2041	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
mbed_official	340:28d1f895c6fe	2042	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2043	* @arg RCC_CRS_IT_SYNCOK
mbed_official	340:28d1f895c6fe	2044	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	340:28d1f895c6fe	2045	* @arg RCC_CRS_IT_ERR
mbed_official	340:28d1f895c6fe	2046	* @arg RCC_CRS_IT_ESYNC
mbed_official	340:28d1f895c6fe	2047	* @retval The new state of __INTERRUPT__ (SET or RESET).
mbed_official	340:28d1f895c6fe	2048	*/
mbed_official	340:28d1f895c6fe	2049	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
mbed_official	340:28d1f895c6fe	2050
mbed_official	340:28d1f895c6fe	2051	/** @brief Clear the CRS's interrupt pending bits
mbed_official	340:28d1f895c6fe	2052	* bits to clear the selected interrupt pending bits.
mbed_official	340:28d1f895c6fe	2053	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	340:28d1f895c6fe	2054	* This parameter can be any combination of the following values:
mbed_official	340:28d1f895c6fe	2055	* @arg RCC_CRS_IT_SYNCOK
mbed_official	340:28d1f895c6fe	2056	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	340:28d1f895c6fe	2057	* @arg RCC_CRS_IT_ERR
mbed_official	340:28d1f895c6fe	2058	* @arg RCC_CRS_IT_ESYNC
mbed_official	340:28d1f895c6fe	2059	* @arg RCC_CRS_IT_TRIMOVF
mbed_official	340:28d1f895c6fe	2060	* @arg RCC_CRS_IT_SYNCERR
mbed_official	340:28d1f895c6fe	2061	* @arg RCC_CRS_IT_SYNCMISS
mbed_official	340:28d1f895c6fe	2062	*/
mbed_official	340:28d1f895c6fe	2063	/* CRS IT Error Mask */
mbed_official	340:28d1f895c6fe	2064	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
mbed_official	340:28d1f895c6fe	2065
mbed_official	340:28d1f895c6fe	2066	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
mbed_official	340:28d1f895c6fe	2067	(CRS->ICR \|= (__INTERRUPT__)))
mbed_official	340:28d1f895c6fe	2068
mbed_official	340:28d1f895c6fe	2069	/**
mbed_official	340:28d1f895c6fe	2070	* @brief Checks whether the specified CRS flag is set or not.
mbed_official	340:28d1f895c6fe	2071	* @param _FLAG_: specifies the flag to check.
mbed_official	340:28d1f895c6fe	2072	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2073	* @arg RCC_CRS_FLAG_SYNCOK
mbed_official	340:28d1f895c6fe	2074	* @arg RCC_CRS_FLAG_SYNCWARN
mbed_official	340:28d1f895c6fe	2075	* @arg RCC_CRS_FLAG_ERR
mbed_official	340:28d1f895c6fe	2076	* @arg RCC_CRS_FLAG_ESYNC
mbed_official	340:28d1f895c6fe	2077	* @arg RCC_CRS_FLAG_TRIMOVF
mbed_official	340:28d1f895c6fe	2078	* @arg RCC_CRS_FLAG_SYNCERR
mbed_official	340:28d1f895c6fe	2079	* @arg RCC_CRS_FLAG_SYNCMISS
mbed_official	340:28d1f895c6fe	2080	* @retval The new state of _FLAG_ (TRUE or FALSE).
mbed_official	340:28d1f895c6fe	2081	*/
mbed_official	340:28d1f895c6fe	2082	#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
mbed_official	340:28d1f895c6fe	2083
mbed_official	340:28d1f895c6fe	2084	/**
mbed_official	340:28d1f895c6fe	2085	* @brief Clears the CRS specified FLAG.
mbed_official	340:28d1f895c6fe	2086	* @param _FLAG_: specifies the flag to clear.
mbed_official	340:28d1f895c6fe	2087	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2088	* @arg RCC_CRS_FLAG_SYNCOK
mbed_official	340:28d1f895c6fe	2089	* @arg RCC_CRS_FLAG_SYNCWARN
mbed_official	340:28d1f895c6fe	2090	* @arg RCC_CRS_FLAG_ERR
mbed_official	340:28d1f895c6fe	2091	* @arg RCC_CRS_FLAG_ESYNC
mbed_official	340:28d1f895c6fe	2092	* @arg RCC_CRS_FLAG_TRIMOVF
mbed_official	340:28d1f895c6fe	2093	* @arg RCC_CRS_FLAG_SYNCERR
mbed_official	340:28d1f895c6fe	2094	* @arg RCC_CRS_FLAG_SYNCMISS
mbed_official	340:28d1f895c6fe	2095	* @retval None
mbed_official	340:28d1f895c6fe	2096	*/
mbed_official	340:28d1f895c6fe	2097
mbed_official	340:28d1f895c6fe	2098	/* CRS Flag Error Mask */
mbed_official	340:28d1f895c6fe	2099	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
mbed_official	340:28d1f895c6fe	2100
mbed_official	340:28d1f895c6fe	2101	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
mbed_official	340:28d1f895c6fe	2102	(CRS->ICR \|= (__FLAG__)))
mbed_official	340:28d1f895c6fe	2103
mbed_official	340:28d1f895c6fe	2104	/**
mbed_official	340:28d1f895c6fe	2105	* @}
mbed_official	340:28d1f895c6fe	2106	*/
mbed_official	340:28d1f895c6fe	2107
mbed_official	340:28d1f895c6fe	2108	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
mbed_official	340:28d1f895c6fe	2109	* @{
mbed_official	340:28d1f895c6fe	2110	*/
mbed_official	340:28d1f895c6fe	2111	/**
mbed_official	340:28d1f895c6fe	2112	* @brief Enables the oscillator clock for frequency error counter.
mbed_official	340:28d1f895c6fe	2113	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
mbed_official	340:28d1f895c6fe	2114	* @retval None
mbed_official	340:28d1f895c6fe	2115	*/
mbed_official	340:28d1f895c6fe	2116	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
mbed_official	340:28d1f895c6fe	2117
mbed_official	340:28d1f895c6fe	2118	/**
mbed_official	340:28d1f895c6fe	2119	* @brief Disables the oscillator clock for frequency error counter.
mbed_official	340:28d1f895c6fe	2120	* @retval None
mbed_official	340:28d1f895c6fe	2121	*/
mbed_official	340:28d1f895c6fe	2122	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
mbed_official	340:28d1f895c6fe	2123
mbed_official	340:28d1f895c6fe	2124	/**
mbed_official	340:28d1f895c6fe	2125	* @brief Enables the automatic hardware adjustement of TRIM bits.
mbed_official	340:28d1f895c6fe	2126	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
mbed_official	340:28d1f895c6fe	2127	* @retval None
mbed_official	340:28d1f895c6fe	2128	*/
mbed_official	340:28d1f895c6fe	2129	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
mbed_official	340:28d1f895c6fe	2130
mbed_official	340:28d1f895c6fe	2131	/**
mbed_official	340:28d1f895c6fe	2132	* @brief Enables or disables the automatic hardware adjustement of TRIM bits.
mbed_official	340:28d1f895c6fe	2133	* @retval None
mbed_official	340:28d1f895c6fe	2134	*/
mbed_official	340:28d1f895c6fe	2135	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
mbed_official	340:28d1f895c6fe	2136
mbed_official	340:28d1f895c6fe	2137	/**
mbed_official	340:28d1f895c6fe	2138	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
mbed_official	340:28d1f895c6fe	2139	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
mbed_official	340:28d1f895c6fe	2140	* of the synchronization source after prescaling. It is then decreased by one in order to
mbed_official	340:28d1f895c6fe	2141	* reach the expected synchronization on the zero value. The formula is the following:
mbed_official	340:28d1f895c6fe	2142	* RELOAD = (fTARGET / fSYNC) -1
mbed_official	340:28d1f895c6fe	2143	* @param _FTARGET_ Target frequency (value in Hz)
mbed_official	340:28d1f895c6fe	2144	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
mbed_official	340:28d1f895c6fe	2145	* @retval None
mbed_official	340:28d1f895c6fe	2146	*/
mbed_official	340:28d1f895c6fe	2147	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
mbed_official	340:28d1f895c6fe	2148
mbed_official	340:28d1f895c6fe	2149	/**
mbed_official	340:28d1f895c6fe	2150	* @}
mbed_official	340:28d1f895c6fe	2151	*/
mbed_official	340:28d1f895c6fe	2152
mbed_official	340:28d1f895c6fe	2153	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	2154	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	2155	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	2156
mbed_official	340:28d1f895c6fe	2157	/**
mbed_official	340:28d1f895c6fe	2158	* @}
mbed_official	340:28d1f895c6fe	2159	*/
mbed_official	340:28d1f895c6fe	2160
mbed_official	340:28d1f895c6fe	2161	/* Exported functions --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	2162	/** @addtogroup RCCEx_Exported_Functions
mbed_official	340:28d1f895c6fe	2163	* @{
mbed_official	340:28d1f895c6fe	2164	*/
mbed_official	340:28d1f895c6fe	2165
mbed_official	340:28d1f895c6fe	2166	/** @addtogroup RCCEx_Exported_Functions_Group1
mbed_official	340:28d1f895c6fe	2167	* @{
mbed_official	340:28d1f895c6fe	2168	*/
mbed_official	340:28d1f895c6fe	2169
mbed_official	340:28d1f895c6fe	2170	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	340:28d1f895c6fe	2171	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	630:825f75ca301e	2172	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
mbed_official	340:28d1f895c6fe	2173
mbed_official	630:825f75ca301e	2174	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
mbed_official	630:825f75ca301e	2175	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
mbed_official	630:825f75ca301e	2176	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	2177	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
mbed_official	340:28d1f895c6fe	2178	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
mbed_official	340:28d1f895c6fe	2179	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
mbed_official	441:d2c15dda23c1	2180	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
mbed_official	340:28d1f895c6fe	2181	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	2182	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	2183	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	2184
mbed_official	340:28d1f895c6fe	2185
mbed_official	340:28d1f895c6fe	2186	/**
mbed_official	340:28d1f895c6fe	2187	* @}
mbed_official	340:28d1f895c6fe	2188	*/
mbed_official	340:28d1f895c6fe	2189
mbed_official	340:28d1f895c6fe	2190	/**
mbed_official	340:28d1f895c6fe	2191	* @}
mbed_official	340:28d1f895c6fe	2192	*/
mbed_official	340:28d1f895c6fe	2193
mbed_official	340:28d1f895c6fe	2194	/**
mbed_official	340:28d1f895c6fe	2195	* @}
mbed_official	340:28d1f895c6fe	2196	*/
mbed_official	340:28d1f895c6fe	2197
mbed_official	340:28d1f895c6fe	2198	/**
mbed_official	340:28d1f895c6fe	2199	* @}
mbed_official	340:28d1f895c6fe	2200	*/
mbed_official	340:28d1f895c6fe	2201
mbed_official	340:28d1f895c6fe	2202	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	2203	}
mbed_official	340:28d1f895c6fe	2204	#endif
mbed_official	340:28d1f895c6fe	2205
mbed_official	340:28d1f895c6fe	2206	#endif /* __STM32F0xx_HAL_RCC_EX_H */
mbed_official	340:28d1f895c6fe	2207
mbed_official	340:28d1f895c6fe	2208	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/