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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c@630:825f75ca301e, 2015-09-28 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Sep 28 10:45:10 2015 +0100
- Revision:
- 630:825f75ca301e
- Parent:
- 441:d2c15dda23c1
Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10
Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/
NUCLEO_F031K6 : Add new target
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 340:28d1f895c6fe | 1 | /** |
| mbed_official | 340:28d1f895c6fe | 2 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 3 | * @file stm32f0xx_hal_rcc_ex.c |
| mbed_official | 340:28d1f895c6fe | 4 | * @author MCD Application Team |
| mbed_official | 630:825f75ca301e | 5 | * @version V1.3.0 |
| mbed_official | 630:825f75ca301e | 6 | * @date 26-June-2015 |
| mbed_official | 340:28d1f895c6fe | 7 | * @brief Extended RCC HAL module driver |
| mbed_official | 340:28d1f895c6fe | 8 | * This file provides firmware functions to manage the following |
| mbed_official | 340:28d1f895c6fe | 9 | * functionalities RCC extension peripheral: |
| mbed_official | 340:28d1f895c6fe | 10 | * + Extended Clock Source configuration functions |
| mbed_official | 340:28d1f895c6fe | 11 | * |
| mbed_official | 340:28d1f895c6fe | 12 | @verbatim |
| mbed_official | 340:28d1f895c6fe | 13 | ============================================================================== |
| mbed_official | 340:28d1f895c6fe | 14 | ##### How to use this driver ##### |
| mbed_official | 340:28d1f895c6fe | 15 | ============================================================================== |
| mbed_official | 340:28d1f895c6fe | 16 | |
| mbed_official | 340:28d1f895c6fe | 17 | For CRS, RCC Extention HAL driver can be used as follows: |
| mbed_official | 340:28d1f895c6fe | 18 | |
| mbed_official | 340:28d1f895c6fe | 19 | (#) In System clock config, HSI48 need to be enabled |
| mbed_official | 340:28d1f895c6fe | 20 | |
| mbed_official | 340:28d1f895c6fe | 21 | (#] Enable CRS clock in IP MSP init which will use CRS functions |
| mbed_official | 340:28d1f895c6fe | 22 | |
| mbed_official | 340:28d1f895c6fe | 23 | (#) Call CRS functions like this |
| mbed_official | 340:28d1f895c6fe | 24 | (##) Prepare synchronization configuration necessary for HSI48 calibration |
| mbed_official | 340:28d1f895c6fe | 25 | (+++) Default values can be set for frequency Error Measurement (reload and error limit) |
| mbed_official | 340:28d1f895c6fe | 26 | and also HSI48 oscillator smooth trimming. |
| mbed_official | 340:28d1f895c6fe | 27 | (+++) Macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE can be also used to calculate |
| mbed_official | 340:28d1f895c6fe | 28 | directly reload value with target and sychronization frequencies values |
| mbed_official | 340:28d1f895c6fe | 29 | (##) Call function HAL_RCCEx_CRSConfig which |
| mbed_official | 340:28d1f895c6fe | 30 | (+++) Reset CRS registers to their default values. |
| mbed_official | 340:28d1f895c6fe | 31 | (+++) Configure CRS registers with synchronization configuration |
| mbed_official | 340:28d1f895c6fe | 32 | (+++) Enable automatic calibration and frequency error counter feature |
| mbed_official | 340:28d1f895c6fe | 33 | |
| mbed_official | 340:28d1f895c6fe | 34 | (##) A polling function is provided to wait for complete Synchronization |
| mbed_official | 340:28d1f895c6fe | 35 | (+++) Call function HAL_RCCEx_CRSWaitSynchronization() |
| mbed_official | 340:28d1f895c6fe | 36 | (+++) According to CRS status, user can decide to adjust again the calibration or continue |
| mbed_official | 340:28d1f895c6fe | 37 | application if synchronization is OK |
| mbed_official | 340:28d1f895c6fe | 38 | |
| mbed_official | 340:28d1f895c6fe | 39 | (#) User can retrieve information related to synchronization in calling function |
| mbed_official | 340:28d1f895c6fe | 40 | HAL_RCCEx_CRSGetSynchronizationInfo() |
| mbed_official | 340:28d1f895c6fe | 41 | |
| mbed_official | 340:28d1f895c6fe | 42 | (#) Regarding synchronization status and synchronization information, user can try a new calibration |
| mbed_official | 340:28d1f895c6fe | 43 | in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. |
| mbed_official | 340:28d1f895c6fe | 44 | Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), |
| mbed_official | 340:28d1f895c6fe | 45 | it means that the actual frequency is lower than the target (and so, that the TRIM value should be |
| mbed_official | 340:28d1f895c6fe | 46 | incremented), while when it is detected during the upcounting phase it means that the actual frequency |
| mbed_official | 340:28d1f895c6fe | 47 | is higher (and that the TRIM value should be decremented). |
| mbed_official | 340:28d1f895c6fe | 48 | |
| mbed_official | 340:28d1f895c6fe | 49 | (#) To use IT mode, user needs to handle it in calling different macros available to do it |
| mbed_official | 340:28d1f895c6fe | 50 | (__HAL_RCC_CRS_XXX_IT). Interuptions will go through RCC Handler (RCC_IRQn/RCC_CRS_IRQHandler) |
| mbed_official | 340:28d1f895c6fe | 51 | (++) Call function HAL_RCCEx_CRSConfig() |
| mbed_official | 340:28d1f895c6fe | 52 | (++) Enable RCC_IRQn (thnaks to NVIC functions) |
| mbed_official | 340:28d1f895c6fe | 53 | (++) Enable CRS IT (__HAL_RCC_CRS_ENABLE_IT) |
| mbed_official | 340:28d1f895c6fe | 54 | (++) Implement CRS status management in RCC_CRS_IRQHandler |
| mbed_official | 340:28d1f895c6fe | 55 | |
| mbed_official | 340:28d1f895c6fe | 56 | (#) To force a SYNC EVENT, user can use function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). Function can be |
| mbed_official | 340:28d1f895c6fe | 57 | called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) |
| mbed_official | 340:28d1f895c6fe | 58 | |
| mbed_official | 340:28d1f895c6fe | 59 | @endverbatim |
| mbed_official | 340:28d1f895c6fe | 60 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 61 | * @attention |
| mbed_official | 340:28d1f895c6fe | 62 | * |
| mbed_official | 630:825f75ca301e | 63 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| mbed_official | 340:28d1f895c6fe | 64 | * |
| mbed_official | 340:28d1f895c6fe | 65 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 340:28d1f895c6fe | 66 | * are permitted provided that the following conditions are met: |
| mbed_official | 340:28d1f895c6fe | 67 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 68 | * this list of conditions and the following disclaimer. |
| mbed_official | 340:28d1f895c6fe | 69 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 70 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 340:28d1f895c6fe | 71 | * and/or other materials provided with the distribution. |
| mbed_official | 340:28d1f895c6fe | 72 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 340:28d1f895c6fe | 73 | * may be used to endorse or promote products derived from this software |
| mbed_official | 340:28d1f895c6fe | 74 | * without specific prior written permission. |
| mbed_official | 340:28d1f895c6fe | 75 | * |
| mbed_official | 340:28d1f895c6fe | 76 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 340:28d1f895c6fe | 77 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 340:28d1f895c6fe | 78 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 340:28d1f895c6fe | 79 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 340:28d1f895c6fe | 80 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 340:28d1f895c6fe | 81 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 340:28d1f895c6fe | 82 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 340:28d1f895c6fe | 83 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 340:28d1f895c6fe | 84 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 340:28d1f895c6fe | 85 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 340:28d1f895c6fe | 86 | * |
| mbed_official | 340:28d1f895c6fe | 87 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 88 | */ |
| mbed_official | 340:28d1f895c6fe | 89 | |
| mbed_official | 340:28d1f895c6fe | 90 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 91 | #include "stm32f0xx_hal.h" |
| mbed_official | 340:28d1f895c6fe | 92 | |
| mbed_official | 340:28d1f895c6fe | 93 | /** @addtogroup STM32F0xx_HAL_Driver |
| mbed_official | 340:28d1f895c6fe | 94 | * @{ |
| mbed_official | 340:28d1f895c6fe | 95 | */ |
| mbed_official | 340:28d1f895c6fe | 96 | |
| mbed_official | 630:825f75ca301e | 97 | #ifdef HAL_RCC_MODULE_ENABLED |
| mbed_official | 630:825f75ca301e | 98 | |
| mbed_official | 630:825f75ca301e | 99 | /** @defgroup RCCEx RCCEx |
| mbed_official | 340:28d1f895c6fe | 100 | * @brief RCC Extension HAL module driver. |
| mbed_official | 340:28d1f895c6fe | 101 | * @{ |
| mbed_official | 340:28d1f895c6fe | 102 | */ |
| mbed_official | 340:28d1f895c6fe | 103 | |
| mbed_official | 340:28d1f895c6fe | 104 | /* Private typedef -----------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 105 | /* Private define ------------------------------------------------------------*/ |
| mbed_official | 630:825f75ca301e | 106 | /** @defgroup RCCEx_Private_Constants RCCEx Private Constants |
| mbed_official | 340:28d1f895c6fe | 107 | * @{ |
| mbed_official | 340:28d1f895c6fe | 108 | */ |
| mbed_official | 340:28d1f895c6fe | 109 | /* Bit position in register */ |
| mbed_official | 340:28d1f895c6fe | 110 | #define CRS_CFGR_FELIM_BITNUMBER 16 |
| mbed_official | 340:28d1f895c6fe | 111 | #define CRS_CR_TRIM_BITNUMBER 8 |
| mbed_official | 340:28d1f895c6fe | 112 | #define CRS_ISR_FECAP_BITNUMBER 16 |
| mbed_official | 340:28d1f895c6fe | 113 | /** |
| mbed_official | 340:28d1f895c6fe | 114 | * @} |
| mbed_official | 340:28d1f895c6fe | 115 | */ |
| mbed_official | 340:28d1f895c6fe | 116 | |
| mbed_official | 340:28d1f895c6fe | 117 | /* Private macro -------------------------------------------------------------*/ |
| mbed_official | 630:825f75ca301e | 118 | /** @defgroup RCCEx_Private_Macros RCCEx Private Macros |
| mbed_official | 340:28d1f895c6fe | 119 | * @{ |
| mbed_official | 340:28d1f895c6fe | 120 | */ |
| mbed_official | 340:28d1f895c6fe | 121 | /** |
| mbed_official | 340:28d1f895c6fe | 122 | * @} |
| mbed_official | 340:28d1f895c6fe | 123 | */ |
| mbed_official | 630:825f75ca301e | 124 | /* Private variables ---------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 125 | /* Private function prototypes -----------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 126 | /* Exported functions ---------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 127 | |
| mbed_official | 340:28d1f895c6fe | 128 | /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions |
| mbed_official | 340:28d1f895c6fe | 129 | * @{ |
| mbed_official | 340:28d1f895c6fe | 130 | */ |
| mbed_official | 340:28d1f895c6fe | 131 | |
| mbed_official | 340:28d1f895c6fe | 132 | /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions |
| mbed_official | 340:28d1f895c6fe | 133 | * @brief Extended RCC clocks control functions |
| mbed_official | 340:28d1f895c6fe | 134 | * |
| mbed_official | 340:28d1f895c6fe | 135 | @verbatim |
| mbed_official | 340:28d1f895c6fe | 136 | =============================================================================== |
| mbed_official | 340:28d1f895c6fe | 137 | ##### Extended Peripheral Control functions ##### |
| mbed_official | 340:28d1f895c6fe | 138 | =============================================================================== |
| mbed_official | 340:28d1f895c6fe | 139 | [..] |
| mbed_official | 340:28d1f895c6fe | 140 | This subsection provides a set of functions allowing to control the RCC Clocks |
| mbed_official | 340:28d1f895c6fe | 141 | frequencies. |
| mbed_official | 340:28d1f895c6fe | 142 | [..] |
| mbed_official | 340:28d1f895c6fe | 143 | (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to |
| mbed_official | 340:28d1f895c6fe | 144 | select the RTC clock source; in this case the Backup domain will be reset in |
| mbed_official | 340:28d1f895c6fe | 145 | order to modify the RTC Clock source, as consequence RTC registers (including |
| mbed_official | 340:28d1f895c6fe | 146 | the backup registers) and RCC_BDCR register are set to their reset values. |
| mbed_official | 340:28d1f895c6fe | 147 | |
| mbed_official | 340:28d1f895c6fe | 148 | @endverbatim |
| mbed_official | 340:28d1f895c6fe | 149 | * @{ |
| mbed_official | 340:28d1f895c6fe | 150 | */ |
| mbed_official | 340:28d1f895c6fe | 151 | |
| mbed_official | 340:28d1f895c6fe | 152 | /** |
| mbed_official | 340:28d1f895c6fe | 153 | * @brief Initializes the RCC extended peripherals clocks according to the specified |
| mbed_official | 340:28d1f895c6fe | 154 | * parameters in the RCC_PeriphCLKInitTypeDef. |
| mbed_official | 340:28d1f895c6fe | 155 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
| mbed_official | 340:28d1f895c6fe | 156 | * contains the configuration information for the Extended Peripherals clocks |
| mbed_official | 340:28d1f895c6fe | 157 | * (USART, RTC, I2C, CEC and USB). |
| mbed_official | 340:28d1f895c6fe | 158 | * |
| mbed_official | 340:28d1f895c6fe | 159 | * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select |
| mbed_official | 340:28d1f895c6fe | 160 | * the RTC clock source; in this case the Backup domain will be reset in |
| mbed_official | 340:28d1f895c6fe | 161 | * order to modify the RTC Clock source, as consequence RTC registers (including |
| mbed_official | 340:28d1f895c6fe | 162 | * the backup registers) and RCC_BDCR register are set to their reset values. |
| mbed_official | 340:28d1f895c6fe | 163 | * |
| mbed_official | 340:28d1f895c6fe | 164 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 165 | */ |
| mbed_official | 340:28d1f895c6fe | 166 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
| mbed_official | 340:28d1f895c6fe | 167 | { |
| mbed_official | 340:28d1f895c6fe | 168 | uint32_t tickstart = 0; |
| mbed_official | 630:825f75ca301e | 169 | uint32_t temp_reg = 0; |
| mbed_official | 340:28d1f895c6fe | 170 | |
| mbed_official | 340:28d1f895c6fe | 171 | /* Check the parameters */ |
| mbed_official | 340:28d1f895c6fe | 172 | assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection)); |
| mbed_official | 340:28d1f895c6fe | 173 | |
| mbed_official | 340:28d1f895c6fe | 174 | /*---------------------------- RTC configuration -------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 175 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) |
| mbed_official | 340:28d1f895c6fe | 176 | { |
| mbed_official | 340:28d1f895c6fe | 177 | /* Reset the Backup domain only if the RTC Clock source selction is modified */ |
| mbed_official | 340:28d1f895c6fe | 178 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) |
| mbed_official | 340:28d1f895c6fe | 179 | { |
| mbed_official | 630:825f75ca301e | 180 | /* Enable Power Clock*/ |
| mbed_official | 630:825f75ca301e | 181 | __HAL_RCC_PWR_CLK_ENABLE(); |
| mbed_official | 630:825f75ca301e | 182 | |
| mbed_official | 630:825f75ca301e | 183 | /* Enable write access to Backup domain */ |
| mbed_official | 630:825f75ca301e | 184 | SET_BIT(PWR->CR, PWR_CR_DBP); |
| mbed_official | 630:825f75ca301e | 185 | |
| mbed_official | 630:825f75ca301e | 186 | /* Wait for Backup domain Write protection disable */ |
| mbed_official | 630:825f75ca301e | 187 | tickstart = HAL_GetTick(); |
| mbed_official | 630:825f75ca301e | 188 | |
| mbed_official | 630:825f75ca301e | 189 | while((PWR->CR & PWR_CR_DBP) == RESET) |
| mbed_official | 630:825f75ca301e | 190 | { |
| mbed_official | 630:825f75ca301e | 191 | if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) |
| mbed_official | 630:825f75ca301e | 192 | { |
| mbed_official | 630:825f75ca301e | 193 | return HAL_TIMEOUT; |
| mbed_official | 630:825f75ca301e | 194 | } |
| mbed_official | 630:825f75ca301e | 195 | } |
| mbed_official | 630:825f75ca301e | 196 | |
| mbed_official | 340:28d1f895c6fe | 197 | /* Store the content of BDCR register before the reset of Backup Domain */ |
| mbed_official | 630:825f75ca301e | 198 | temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); |
| mbed_official | 340:28d1f895c6fe | 199 | /* RTC Clock selection can be changed only if the Backup Domain is reset */ |
| mbed_official | 340:28d1f895c6fe | 200 | __HAL_RCC_BACKUPRESET_FORCE(); |
| mbed_official | 340:28d1f895c6fe | 201 | __HAL_RCC_BACKUPRESET_RELEASE(); |
| mbed_official | 340:28d1f895c6fe | 202 | /* Restore the Content of BDCR register */ |
| mbed_official | 630:825f75ca301e | 203 | RCC->BDCR = temp_reg; |
| mbed_official | 630:825f75ca301e | 204 | |
| mbed_official | 630:825f75ca301e | 205 | /* Wait for LSERDY if LSE was enabled */ |
| mbed_official | 630:825f75ca301e | 206 | if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)) |
| mbed_official | 630:825f75ca301e | 207 | { |
| mbed_official | 630:825f75ca301e | 208 | /* Get timeout */ |
| mbed_official | 630:825f75ca301e | 209 | tickstart = HAL_GetTick(); |
| mbed_official | 340:28d1f895c6fe | 210 | |
| mbed_official | 630:825f75ca301e | 211 | /* Wait till LSE is ready */ |
| mbed_official | 630:825f75ca301e | 212 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
| mbed_official | 340:28d1f895c6fe | 213 | { |
| mbed_official | 630:825f75ca301e | 214 | if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) |
| mbed_official | 630:825f75ca301e | 215 | { |
| mbed_official | 630:825f75ca301e | 216 | return HAL_TIMEOUT; |
| mbed_official | 630:825f75ca301e | 217 | } |
| mbed_official | 630:825f75ca301e | 218 | } |
| mbed_official | 630:825f75ca301e | 219 | } |
| mbed_official | 630:825f75ca301e | 220 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
| mbed_official | 340:28d1f895c6fe | 221 | } |
| mbed_official | 340:28d1f895c6fe | 222 | } |
| mbed_official | 340:28d1f895c6fe | 223 | |
| mbed_official | 340:28d1f895c6fe | 224 | /*------------------------------- USART1 Configuration ------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 225 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) |
| mbed_official | 340:28d1f895c6fe | 226 | { |
| mbed_official | 340:28d1f895c6fe | 227 | /* Check the parameters */ |
| mbed_official | 340:28d1f895c6fe | 228 | assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); |
| mbed_official | 340:28d1f895c6fe | 229 | |
| mbed_official | 340:28d1f895c6fe | 230 | /* Configure the USART1 clock source */ |
| mbed_official | 340:28d1f895c6fe | 231 | __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); |
| mbed_official | 340:28d1f895c6fe | 232 | } |
| mbed_official | 340:28d1f895c6fe | 233 | |
| mbed_official | 630:825f75ca301e | 234 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
| mbed_official | 630:825f75ca301e | 235 | || defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 236 | /*----------------------------- USART2 Configuration --------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 237 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) |
| mbed_official | 340:28d1f895c6fe | 238 | { |
| mbed_official | 340:28d1f895c6fe | 239 | /* Check the parameters */ |
| mbed_official | 340:28d1f895c6fe | 240 | assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); |
| mbed_official | 340:28d1f895c6fe | 241 | |
| mbed_official | 340:28d1f895c6fe | 242 | /* Configure the USART2 clock source */ |
| mbed_official | 340:28d1f895c6fe | 243 | __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); |
| mbed_official | 340:28d1f895c6fe | 244 | } |
| mbed_official | 340:28d1f895c6fe | 245 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
| mbed_official | 340:28d1f895c6fe | 246 | /* STM32F091xC || STM32F098xx */ |
| mbed_official | 340:28d1f895c6fe | 247 | |
| mbed_official | 340:28d1f895c6fe | 248 | #if defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 249 | /*----------------------------- USART3 Configuration --------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 250 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) |
| mbed_official | 340:28d1f895c6fe | 251 | { |
| mbed_official | 340:28d1f895c6fe | 252 | /* Check the parameters */ |
| mbed_official | 340:28d1f895c6fe | 253 | assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); |
| mbed_official | 340:28d1f895c6fe | 254 | |
| mbed_official | 340:28d1f895c6fe | 255 | /* Configure the USART3 clock source */ |
| mbed_official | 340:28d1f895c6fe | 256 | __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); |
| mbed_official | 340:28d1f895c6fe | 257 | } |
| mbed_official | 340:28d1f895c6fe | 258 | #endif /* STM32F091xC || STM32F098xx */ |
| mbed_official | 340:28d1f895c6fe | 259 | |
| mbed_official | 340:28d1f895c6fe | 260 | /*------------------------------ I2C1 Configuration ------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 261 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) |
| mbed_official | 340:28d1f895c6fe | 262 | { |
| mbed_official | 340:28d1f895c6fe | 263 | /* Check the parameters */ |
| mbed_official | 340:28d1f895c6fe | 264 | assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); |
| mbed_official | 340:28d1f895c6fe | 265 | |
| mbed_official | 340:28d1f895c6fe | 266 | /* Configure the I2C1 clock source */ |
| mbed_official | 340:28d1f895c6fe | 267 | __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); |
| mbed_official | 340:28d1f895c6fe | 268 | } |
| mbed_official | 340:28d1f895c6fe | 269 | |
| mbed_official | 441:d2c15dda23c1 | 270 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) |
| mbed_official | 340:28d1f895c6fe | 271 | /*------------------------------ USB Configuration ------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 272 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) |
| mbed_official | 340:28d1f895c6fe | 273 | { |
| mbed_official | 340:28d1f895c6fe | 274 | /* Check the parameters */ |
| mbed_official | 340:28d1f895c6fe | 275 | assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); |
| mbed_official | 340:28d1f895c6fe | 276 | |
| mbed_official | 340:28d1f895c6fe | 277 | /* Configure the USB clock source */ |
| mbed_official | 340:28d1f895c6fe | 278 | __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); |
| mbed_official | 340:28d1f895c6fe | 279 | } |
| mbed_official | 441:d2c15dda23c1 | 280 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ |
| mbed_official | 340:28d1f895c6fe | 281 | |
| mbed_official | 630:825f75ca301e | 282 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
| mbed_official | 630:825f75ca301e | 283 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
| mbed_official | 630:825f75ca301e | 284 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
| mbed_official | 630:825f75ca301e | 285 | || defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 286 | /*------------------------------ CEC clock Configuration -------------------*/ |
| mbed_official | 340:28d1f895c6fe | 287 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) |
| mbed_official | 340:28d1f895c6fe | 288 | { |
| mbed_official | 340:28d1f895c6fe | 289 | /* Check the parameters */ |
| mbed_official | 340:28d1f895c6fe | 290 | assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); |
| mbed_official | 340:28d1f895c6fe | 291 | |
| mbed_official | 340:28d1f895c6fe | 292 | /* Configure the CEC clock source */ |
| mbed_official | 340:28d1f895c6fe | 293 | __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); |
| mbed_official | 340:28d1f895c6fe | 294 | } |
| mbed_official | 340:28d1f895c6fe | 295 | #endif /* STM32F042x6 || STM32F048xx || */ |
| mbed_official | 340:28d1f895c6fe | 296 | /* STM32F051x8 || STM32F058xx || */ |
| mbed_official | 340:28d1f895c6fe | 297 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
| mbed_official | 340:28d1f895c6fe | 298 | /* STM32F091xC || STM32F098xx */ |
| mbed_official | 340:28d1f895c6fe | 299 | |
| mbed_official | 340:28d1f895c6fe | 300 | return HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 301 | } |
| mbed_official | 340:28d1f895c6fe | 302 | |
| mbed_official | 340:28d1f895c6fe | 303 | /** |
| mbed_official | 340:28d1f895c6fe | 304 | * @brief Get the RCC_ClkInitStruct according to the internal |
| mbed_official | 340:28d1f895c6fe | 305 | * RCC configuration registers. |
| mbed_official | 340:28d1f895c6fe | 306 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
| mbed_official | 340:28d1f895c6fe | 307 | * returns the configuration information for the Extended Peripherals clocks |
| mbed_official | 340:28d1f895c6fe | 308 | * (USART, RTC, I2C, CEC and USB). |
| mbed_official | 340:28d1f895c6fe | 309 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 310 | */ |
| mbed_official | 340:28d1f895c6fe | 311 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
| mbed_official | 340:28d1f895c6fe | 312 | { |
| mbed_official | 340:28d1f895c6fe | 313 | /* Set all possible values for the extended clock type parameter------------*/ |
| mbed_official | 340:28d1f895c6fe | 314 | /* Common part first */ |
| mbed_official | 340:28d1f895c6fe | 315 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; |
| mbed_official | 340:28d1f895c6fe | 316 | /* Get the RTC configuration --------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 317 | PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); |
| mbed_official | 340:28d1f895c6fe | 318 | /* Get the USART1 configuration --------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 319 | PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); |
| mbed_official | 340:28d1f895c6fe | 320 | /* Get the I2C1 clock source -----------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 321 | PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); |
| mbed_official | 340:28d1f895c6fe | 322 | |
| mbed_official | 630:825f75ca301e | 323 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
| mbed_official | 630:825f75ca301e | 324 | || defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 325 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2; |
| mbed_official | 340:28d1f895c6fe | 326 | /* Get the USART2 clock source ---------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 327 | PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); |
| mbed_official | 340:28d1f895c6fe | 328 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
| mbed_official | 340:28d1f895c6fe | 329 | /* STM32F091xC || STM32F098xx */ |
| mbed_official | 340:28d1f895c6fe | 330 | |
| mbed_official | 340:28d1f895c6fe | 331 | #if defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 332 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3; |
| mbed_official | 340:28d1f895c6fe | 333 | /* Get the USART3 clock source ---------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 334 | PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); |
| mbed_official | 340:28d1f895c6fe | 335 | #endif /* STM32F091xC || STM32F098xx */ |
| mbed_official | 340:28d1f895c6fe | 336 | |
| mbed_official | 441:d2c15dda23c1 | 337 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6) |
| mbed_official | 340:28d1f895c6fe | 338 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; |
| mbed_official | 340:28d1f895c6fe | 339 | /* Get the USB clock source ---------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 340 | PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); |
| mbed_official | 441:d2c15dda23c1 | 341 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */ |
| mbed_official | 340:28d1f895c6fe | 342 | |
| mbed_official | 630:825f75ca301e | 343 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
| mbed_official | 630:825f75ca301e | 344 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
| mbed_official | 630:825f75ca301e | 345 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
| mbed_official | 630:825f75ca301e | 346 | || defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 347 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; |
| mbed_official | 340:28d1f895c6fe | 348 | /* Get the CEC clock source ------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 349 | PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); |
| mbed_official | 340:28d1f895c6fe | 350 | #endif /* STM32F042x6 || STM32F048xx || */ |
| mbed_official | 340:28d1f895c6fe | 351 | /* STM32F051x8 || STM32F058xx || */ |
| mbed_official | 340:28d1f895c6fe | 352 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
| mbed_official | 340:28d1f895c6fe | 353 | /* STM32F091xC || STM32F098xx */ |
| mbed_official | 340:28d1f895c6fe | 354 | |
| mbed_official | 340:28d1f895c6fe | 355 | } |
| mbed_official | 340:28d1f895c6fe | 356 | |
| mbed_official | 630:825f75ca301e | 357 | /** |
| mbed_official | 630:825f75ca301e | 358 | * @brief Returns the peripheral clock frequency |
| mbed_official | 630:825f75ca301e | 359 | * @note Returns 0 if peripheral clock is unknown |
| mbed_official | 630:825f75ca301e | 360 | * @param PeriphClk: Peripheral clock identifier |
| mbed_official | 630:825f75ca301e | 361 | * This parameter can be one of the following values: |
| mbed_official | 630:825f75ca301e | 362 | * @arg RCC_PERIPHCLK_RTC RTC peripheral clock |
| mbed_official | 630:825f75ca301e | 363 | * @arg RCC_PERIPHCLK_USART1 USART1 peripheral clock |
| mbed_official | 630:825f75ca301e | 364 | * @arg RCC_PERIPHCLK_USART2 USART2 peripheral clock (*) |
| mbed_official | 630:825f75ca301e | 365 | * @arg RCC_PERIPHCLK_USART3 USART3 peripheral clock (*) |
| mbed_official | 630:825f75ca301e | 366 | * @arg RCC_PERIPHCLK_I2C1 I2C1 peripheral clock |
| mbed_official | 630:825f75ca301e | 367 | * @arg RCC_PERIPHCLK_USB USB peripheral clock (*) |
| mbed_official | 630:825f75ca301e | 368 | * @arg RCC_PERIPHCLK_CEC CEC peripheral clock (*) |
| mbed_official | 630:825f75ca301e | 369 | * @note (*) means that this peripheral is not present on all the STM32F0xx devices |
| mbed_official | 630:825f75ca301e | 370 | * @retval Frequency in Hz (0: means that no available frequency for the peripheral) |
| mbed_official | 630:825f75ca301e | 371 | */ |
| mbed_official | 630:825f75ca301e | 372 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) |
| mbed_official | 630:825f75ca301e | 373 | { |
| mbed_official | 630:825f75ca301e | 374 | uint32_t frequency = 0; |
| mbed_official | 630:825f75ca301e | 375 | uint32_t srcclk = 0; |
| mbed_official | 630:825f75ca301e | 376 | #if defined(USB) |
| mbed_official | 630:825f75ca301e | 377 | uint32_t pllmull = 0, pllsource = 0, predivfactor = 0; |
| mbed_official | 630:825f75ca301e | 378 | #endif /* USB */ |
| mbed_official | 630:825f75ca301e | 379 | |
| mbed_official | 630:825f75ca301e | 380 | /* Check the parameters */ |
| mbed_official | 630:825f75ca301e | 381 | assert_param(IS_RCC_PERIPHCLK(PeriphClk)); |
| mbed_official | 630:825f75ca301e | 382 | |
| mbed_official | 630:825f75ca301e | 383 | switch (PeriphClk) |
| mbed_official | 630:825f75ca301e | 384 | { |
| mbed_official | 630:825f75ca301e | 385 | case RCC_PERIPHCLK_RTC: |
| mbed_official | 630:825f75ca301e | 386 | { |
| mbed_official | 630:825f75ca301e | 387 | /* Get the current RTC source */ |
| mbed_official | 630:825f75ca301e | 388 | srcclk = __HAL_RCC_GET_RTC_SOURCE(); |
| mbed_official | 630:825f75ca301e | 389 | |
| mbed_official | 630:825f75ca301e | 390 | /* Check if LSE is ready and if RTC clock selection is LSE */ |
| mbed_official | 630:825f75ca301e | 391 | if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) |
| mbed_official | 630:825f75ca301e | 392 | { |
| mbed_official | 630:825f75ca301e | 393 | frequency = LSE_VALUE; |
| mbed_official | 630:825f75ca301e | 394 | } |
| mbed_official | 630:825f75ca301e | 395 | /* Check if LSI is ready and if RTC clock selection is LSI */ |
| mbed_official | 630:825f75ca301e | 396 | else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) |
| mbed_official | 630:825f75ca301e | 397 | { |
| mbed_official | 630:825f75ca301e | 398 | frequency = LSI_VALUE; |
| mbed_official | 630:825f75ca301e | 399 | } |
| mbed_official | 630:825f75ca301e | 400 | /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ |
| mbed_official | 630:825f75ca301e | 401 | else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) |
| mbed_official | 630:825f75ca301e | 402 | { |
| mbed_official | 630:825f75ca301e | 403 | frequency = HSE_VALUE / 32; |
| mbed_official | 630:825f75ca301e | 404 | } |
| mbed_official | 630:825f75ca301e | 405 | /* Clock not enabled for RTC*/ |
| mbed_official | 630:825f75ca301e | 406 | else |
| mbed_official | 630:825f75ca301e | 407 | { |
| mbed_official | 630:825f75ca301e | 408 | frequency = 0; |
| mbed_official | 630:825f75ca301e | 409 | } |
| mbed_official | 630:825f75ca301e | 410 | break; |
| mbed_official | 630:825f75ca301e | 411 | } |
| mbed_official | 630:825f75ca301e | 412 | case RCC_PERIPHCLK_USART1: |
| mbed_official | 630:825f75ca301e | 413 | { |
| mbed_official | 630:825f75ca301e | 414 | /* Get the current USART1 source */ |
| mbed_official | 630:825f75ca301e | 415 | srcclk = __HAL_RCC_GET_USART1_SOURCE(); |
| mbed_official | 630:825f75ca301e | 416 | |
| mbed_official | 630:825f75ca301e | 417 | /* Check if USART1 clock selection is PCLK1 */ |
| mbed_official | 630:825f75ca301e | 418 | if (srcclk == RCC_USART1CLKSOURCE_PCLK1) |
| mbed_official | 630:825f75ca301e | 419 | { |
| mbed_official | 630:825f75ca301e | 420 | frequency = HAL_RCC_GetPCLK1Freq(); |
| mbed_official | 630:825f75ca301e | 421 | } |
| mbed_official | 630:825f75ca301e | 422 | /* Check if HSI is ready and if USART1 clock selection is HSI */ |
| mbed_official | 630:825f75ca301e | 423 | else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) |
| mbed_official | 630:825f75ca301e | 424 | { |
| mbed_official | 630:825f75ca301e | 425 | frequency = HSI_VALUE; |
| mbed_official | 630:825f75ca301e | 426 | } |
| mbed_official | 630:825f75ca301e | 427 | /* Check if USART1 clock selection is SYSCLK */ |
| mbed_official | 630:825f75ca301e | 428 | else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) |
| mbed_official | 630:825f75ca301e | 429 | { |
| mbed_official | 630:825f75ca301e | 430 | frequency = HAL_RCC_GetSysClockFreq(); |
| mbed_official | 630:825f75ca301e | 431 | } |
| mbed_official | 630:825f75ca301e | 432 | /* Check if LSE is ready and if USART1 clock selection is LSE */ |
| mbed_official | 630:825f75ca301e | 433 | else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) |
| mbed_official | 630:825f75ca301e | 434 | { |
| mbed_official | 630:825f75ca301e | 435 | frequency = LSE_VALUE; |
| mbed_official | 630:825f75ca301e | 436 | } |
| mbed_official | 630:825f75ca301e | 437 | /* Clock not enabled for USART1*/ |
| mbed_official | 630:825f75ca301e | 438 | else |
| mbed_official | 630:825f75ca301e | 439 | { |
| mbed_official | 630:825f75ca301e | 440 | frequency = 0; |
| mbed_official | 630:825f75ca301e | 441 | } |
| mbed_official | 630:825f75ca301e | 442 | break; |
| mbed_official | 630:825f75ca301e | 443 | } |
| mbed_official | 630:825f75ca301e | 444 | #if defined(RCC_CFGR3_USART2SW) |
| mbed_official | 630:825f75ca301e | 445 | case RCC_PERIPHCLK_USART2: |
| mbed_official | 630:825f75ca301e | 446 | { |
| mbed_official | 630:825f75ca301e | 447 | /* Get the current USART2 source */ |
| mbed_official | 630:825f75ca301e | 448 | srcclk = __HAL_RCC_GET_USART2_SOURCE(); |
| mbed_official | 630:825f75ca301e | 449 | |
| mbed_official | 630:825f75ca301e | 450 | /* Check if USART2 clock selection is PCLK1 */ |
| mbed_official | 630:825f75ca301e | 451 | if (srcclk == RCC_USART2CLKSOURCE_PCLK1) |
| mbed_official | 630:825f75ca301e | 452 | { |
| mbed_official | 630:825f75ca301e | 453 | frequency = HAL_RCC_GetPCLK1Freq(); |
| mbed_official | 630:825f75ca301e | 454 | } |
| mbed_official | 630:825f75ca301e | 455 | /* Check if HSI is ready and if USART2 clock selection is HSI */ |
| mbed_official | 630:825f75ca301e | 456 | else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) |
| mbed_official | 630:825f75ca301e | 457 | { |
| mbed_official | 630:825f75ca301e | 458 | frequency = HSI_VALUE; |
| mbed_official | 630:825f75ca301e | 459 | } |
| mbed_official | 630:825f75ca301e | 460 | /* Check if USART2 clock selection is SYSCLK */ |
| mbed_official | 630:825f75ca301e | 461 | else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) |
| mbed_official | 630:825f75ca301e | 462 | { |
| mbed_official | 630:825f75ca301e | 463 | frequency = HAL_RCC_GetSysClockFreq(); |
| mbed_official | 630:825f75ca301e | 464 | } |
| mbed_official | 630:825f75ca301e | 465 | /* Check if LSE is ready and if USART2 clock selection is LSE */ |
| mbed_official | 630:825f75ca301e | 466 | else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) |
| mbed_official | 630:825f75ca301e | 467 | { |
| mbed_official | 630:825f75ca301e | 468 | frequency = LSE_VALUE; |
| mbed_official | 630:825f75ca301e | 469 | } |
| mbed_official | 630:825f75ca301e | 470 | /* Clock not enabled for USART2*/ |
| mbed_official | 630:825f75ca301e | 471 | else |
| mbed_official | 630:825f75ca301e | 472 | { |
| mbed_official | 630:825f75ca301e | 473 | frequency = 0; |
| mbed_official | 630:825f75ca301e | 474 | } |
| mbed_official | 630:825f75ca301e | 475 | break; |
| mbed_official | 630:825f75ca301e | 476 | } |
| mbed_official | 630:825f75ca301e | 477 | #endif /* RCC_CFGR3_USART2SW */ |
| mbed_official | 630:825f75ca301e | 478 | #if defined(RCC_CFGR3_USART3SW) |
| mbed_official | 630:825f75ca301e | 479 | case RCC_PERIPHCLK_USART3: |
| mbed_official | 630:825f75ca301e | 480 | { |
| mbed_official | 630:825f75ca301e | 481 | /* Get the current USART3 source */ |
| mbed_official | 630:825f75ca301e | 482 | srcclk = __HAL_RCC_GET_USART3_SOURCE(); |
| mbed_official | 630:825f75ca301e | 483 | |
| mbed_official | 630:825f75ca301e | 484 | /* Check if USART3 clock selection is PCLK1 */ |
| mbed_official | 630:825f75ca301e | 485 | if (srcclk == RCC_USART3CLKSOURCE_PCLK1) |
| mbed_official | 630:825f75ca301e | 486 | { |
| mbed_official | 630:825f75ca301e | 487 | frequency = HAL_RCC_GetPCLK1Freq(); |
| mbed_official | 630:825f75ca301e | 488 | } |
| mbed_official | 630:825f75ca301e | 489 | /* Check if HSI is ready and if USART3 clock selection is HSI */ |
| mbed_official | 630:825f75ca301e | 490 | else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) |
| mbed_official | 630:825f75ca301e | 491 | { |
| mbed_official | 630:825f75ca301e | 492 | frequency = HSI_VALUE; |
| mbed_official | 630:825f75ca301e | 493 | } |
| mbed_official | 630:825f75ca301e | 494 | /* Check if USART3 clock selection is SYSCLK */ |
| mbed_official | 630:825f75ca301e | 495 | else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) |
| mbed_official | 630:825f75ca301e | 496 | { |
| mbed_official | 630:825f75ca301e | 497 | frequency = HAL_RCC_GetSysClockFreq(); |
| mbed_official | 630:825f75ca301e | 498 | } |
| mbed_official | 630:825f75ca301e | 499 | /* Check if LSE is ready and if USART3 clock selection is LSE */ |
| mbed_official | 630:825f75ca301e | 500 | else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) |
| mbed_official | 630:825f75ca301e | 501 | { |
| mbed_official | 630:825f75ca301e | 502 | frequency = LSE_VALUE; |
| mbed_official | 630:825f75ca301e | 503 | } |
| mbed_official | 630:825f75ca301e | 504 | /* Clock not enabled for USART3*/ |
| mbed_official | 630:825f75ca301e | 505 | else |
| mbed_official | 630:825f75ca301e | 506 | { |
| mbed_official | 630:825f75ca301e | 507 | frequency = 0; |
| mbed_official | 630:825f75ca301e | 508 | } |
| mbed_official | 630:825f75ca301e | 509 | break; |
| mbed_official | 630:825f75ca301e | 510 | } |
| mbed_official | 630:825f75ca301e | 511 | #endif /* RCC_CFGR3_USART3SW */ |
| mbed_official | 630:825f75ca301e | 512 | case RCC_PERIPHCLK_I2C1: |
| mbed_official | 630:825f75ca301e | 513 | { |
| mbed_official | 630:825f75ca301e | 514 | /* Get the current I2C1 source */ |
| mbed_official | 630:825f75ca301e | 515 | srcclk = __HAL_RCC_GET_I2C1_SOURCE(); |
| mbed_official | 630:825f75ca301e | 516 | |
| mbed_official | 630:825f75ca301e | 517 | /* Check if HSI is ready and if I2C1 clock selection is HSI */ |
| mbed_official | 630:825f75ca301e | 518 | if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) |
| mbed_official | 630:825f75ca301e | 519 | { |
| mbed_official | 630:825f75ca301e | 520 | frequency = HSI_VALUE; |
| mbed_official | 630:825f75ca301e | 521 | } |
| mbed_official | 630:825f75ca301e | 522 | /* Check if I2C1 clock selection is SYSCLK */ |
| mbed_official | 630:825f75ca301e | 523 | else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) |
| mbed_official | 630:825f75ca301e | 524 | { |
| mbed_official | 630:825f75ca301e | 525 | frequency = HAL_RCC_GetSysClockFreq(); |
| mbed_official | 630:825f75ca301e | 526 | } |
| mbed_official | 630:825f75ca301e | 527 | /* Clock not enabled for I2C1*/ |
| mbed_official | 630:825f75ca301e | 528 | else |
| mbed_official | 630:825f75ca301e | 529 | { |
| mbed_official | 630:825f75ca301e | 530 | frequency = 0; |
| mbed_official | 630:825f75ca301e | 531 | } |
| mbed_official | 630:825f75ca301e | 532 | break; |
| mbed_official | 630:825f75ca301e | 533 | } |
| mbed_official | 630:825f75ca301e | 534 | #if defined(USB) |
| mbed_official | 630:825f75ca301e | 535 | case RCC_PERIPHCLK_USB: |
| mbed_official | 630:825f75ca301e | 536 | { |
| mbed_official | 630:825f75ca301e | 537 | /* Get the current USB source */ |
| mbed_official | 630:825f75ca301e | 538 | srcclk = __HAL_RCC_GET_USB_SOURCE(); |
| mbed_official | 630:825f75ca301e | 539 | |
| mbed_official | 630:825f75ca301e | 540 | /* Check if PLL is ready and if USB clock selection is PLL */ |
| mbed_official | 630:825f75ca301e | 541 | if ((srcclk == RCC_USBCLKSOURCE_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) |
| mbed_official | 630:825f75ca301e | 542 | { |
| mbed_official | 630:825f75ca301e | 543 | /* Get PLL clock source and multiplication factor ----------------------*/ |
| mbed_official | 630:825f75ca301e | 544 | pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; |
| mbed_official | 630:825f75ca301e | 545 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
| mbed_official | 630:825f75ca301e | 546 | pllmull = (pllmull >> RCC_CFGR_PLLMUL_BITNUMBER) + 2; |
| mbed_official | 630:825f75ca301e | 547 | predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; |
| mbed_official | 630:825f75ca301e | 548 | |
| mbed_official | 630:825f75ca301e | 549 | if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) |
| mbed_official | 630:825f75ca301e | 550 | { |
| mbed_official | 630:825f75ca301e | 551 | /* HSE used as PLL clock source : frequency = HSE/PREDIV * PLLMUL */ |
| mbed_official | 630:825f75ca301e | 552 | frequency = (HSE_VALUE/predivfactor) * pllmull; |
| mbed_official | 630:825f75ca301e | 553 | } |
| mbed_official | 630:825f75ca301e | 554 | #if defined(RCC_CR2_HSI48ON) |
| mbed_official | 630:825f75ca301e | 555 | else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) |
| mbed_official | 630:825f75ca301e | 556 | { |
| mbed_official | 630:825f75ca301e | 557 | /* HSI48 used as PLL clock source : frequency = HSI48/PREDIV * PLLMUL */ |
| mbed_official | 630:825f75ca301e | 558 | frequency = (HSI48_VALUE / predivfactor) * pllmull; |
| mbed_official | 630:825f75ca301e | 559 | } |
| mbed_official | 630:825f75ca301e | 560 | #endif /* RCC_CR2_HSI48ON */ |
| mbed_official | 630:825f75ca301e | 561 | else |
| mbed_official | 630:825f75ca301e | 562 | { |
| mbed_official | 630:825f75ca301e | 563 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F072xB) || defined(STM32F070xB) |
| mbed_official | 630:825f75ca301e | 564 | /* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */ |
| mbed_official | 630:825f75ca301e | 565 | frequency = (HSI_VALUE / predivfactor) * pllmull; |
| mbed_official | 630:825f75ca301e | 566 | #else |
| mbed_official | 630:825f75ca301e | 567 | /* HSI used as PLL clock source : frequency = HSI/2 * PLLMUL */ |
| mbed_official | 630:825f75ca301e | 568 | frequency = (HSI_VALUE >> 1) * pllmull; |
| mbed_official | 630:825f75ca301e | 569 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */ |
| mbed_official | 630:825f75ca301e | 570 | } |
| mbed_official | 630:825f75ca301e | 571 | } |
| mbed_official | 630:825f75ca301e | 572 | #if defined(RCC_CR2_HSI48ON) |
| mbed_official | 630:825f75ca301e | 573 | /* Check if HSI48 is ready and if USB clock selection is HSI48 */ |
| mbed_official | 630:825f75ca301e | 574 | else if ((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CR2, RCC_CR2_HSI48RDY))) |
| mbed_official | 630:825f75ca301e | 575 | { |
| mbed_official | 630:825f75ca301e | 576 | frequency = HSI48_VALUE; |
| mbed_official | 630:825f75ca301e | 577 | } |
| mbed_official | 630:825f75ca301e | 578 | #endif /* RCC_CR2_HSI48ON */ |
| mbed_official | 630:825f75ca301e | 579 | /* Clock not enabled for USB*/ |
| mbed_official | 630:825f75ca301e | 580 | else |
| mbed_official | 630:825f75ca301e | 581 | { |
| mbed_official | 630:825f75ca301e | 582 | frequency = 0; |
| mbed_official | 630:825f75ca301e | 583 | } |
| mbed_official | 630:825f75ca301e | 584 | break; |
| mbed_official | 630:825f75ca301e | 585 | } |
| mbed_official | 630:825f75ca301e | 586 | #endif /* USB */ |
| mbed_official | 630:825f75ca301e | 587 | #if defined(CEC) |
| mbed_official | 630:825f75ca301e | 588 | case RCC_PERIPHCLK_CEC: |
| mbed_official | 630:825f75ca301e | 589 | { |
| mbed_official | 630:825f75ca301e | 590 | /* Get the current CEC source */ |
| mbed_official | 630:825f75ca301e | 591 | srcclk = __HAL_RCC_GET_CEC_SOURCE(); |
| mbed_official | 630:825f75ca301e | 592 | |
| mbed_official | 630:825f75ca301e | 593 | /* Check if HSI is ready and if CEC clock selection is HSI */ |
| mbed_official | 630:825f75ca301e | 594 | if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) |
| mbed_official | 630:825f75ca301e | 595 | { |
| mbed_official | 630:825f75ca301e | 596 | frequency = HSI_VALUE; |
| mbed_official | 630:825f75ca301e | 597 | } |
| mbed_official | 630:825f75ca301e | 598 | /* Check if LSE is ready and if CEC clock selection is LSE */ |
| mbed_official | 630:825f75ca301e | 599 | else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) |
| mbed_official | 630:825f75ca301e | 600 | { |
| mbed_official | 630:825f75ca301e | 601 | frequency = LSE_VALUE; |
| mbed_official | 630:825f75ca301e | 602 | } |
| mbed_official | 630:825f75ca301e | 603 | /* Clock not enabled for CEC */ |
| mbed_official | 630:825f75ca301e | 604 | else |
| mbed_official | 630:825f75ca301e | 605 | { |
| mbed_official | 630:825f75ca301e | 606 | frequency = 0; |
| mbed_official | 630:825f75ca301e | 607 | } |
| mbed_official | 630:825f75ca301e | 608 | break; |
| mbed_official | 630:825f75ca301e | 609 | } |
| mbed_official | 630:825f75ca301e | 610 | #endif /* CEC */ |
| mbed_official | 630:825f75ca301e | 611 | default: |
| mbed_official | 630:825f75ca301e | 612 | { |
| mbed_official | 630:825f75ca301e | 613 | break; |
| mbed_official | 630:825f75ca301e | 614 | } |
| mbed_official | 630:825f75ca301e | 615 | } |
| mbed_official | 630:825f75ca301e | 616 | return(frequency); |
| mbed_official | 630:825f75ca301e | 617 | } |
| mbed_official | 630:825f75ca301e | 618 | |
| mbed_official | 630:825f75ca301e | 619 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
| mbed_official | 630:825f75ca301e | 620 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
| mbed_official | 630:825f75ca301e | 621 | || defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 622 | /** |
| mbed_official | 340:28d1f895c6fe | 623 | * @brief Start automatic synchronization using polling mode |
| mbed_official | 340:28d1f895c6fe | 624 | * @param pInit Pointer on RCC_CRSInitTypeDef structure |
| mbed_official | 340:28d1f895c6fe | 625 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 626 | */ |
| mbed_official | 340:28d1f895c6fe | 627 | void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) |
| mbed_official | 340:28d1f895c6fe | 628 | { |
| mbed_official | 340:28d1f895c6fe | 629 | /* Check the parameters */ |
| mbed_official | 340:28d1f895c6fe | 630 | assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); |
| mbed_official | 340:28d1f895c6fe | 631 | assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); |
| mbed_official | 340:28d1f895c6fe | 632 | assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); |
| mbed_official | 340:28d1f895c6fe | 633 | assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); |
| mbed_official | 340:28d1f895c6fe | 634 | assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); |
| mbed_official | 340:28d1f895c6fe | 635 | assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); |
| mbed_official | 340:28d1f895c6fe | 636 | |
| mbed_official | 340:28d1f895c6fe | 637 | |
| mbed_official | 340:28d1f895c6fe | 638 | /* CONFIGURATION */ |
| mbed_official | 340:28d1f895c6fe | 639 | |
| mbed_official | 340:28d1f895c6fe | 640 | /* Before configuration, reset CRS registers to their default values*/ |
| mbed_official | 630:825f75ca301e | 641 | __HAL_RCC_CRS_FORCE_RESET(); |
| mbed_official | 630:825f75ca301e | 642 | __HAL_RCC_CRS_RELEASE_RESET(); |
| mbed_official | 340:28d1f895c6fe | 643 | |
| mbed_official | 340:28d1f895c6fe | 644 | /* Configure Synchronization input */ |
| mbed_official | 340:28d1f895c6fe | 645 | /* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */ |
| mbed_official | 340:28d1f895c6fe | 646 | CRS->CFGR &= ~(CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL); |
| mbed_official | 340:28d1f895c6fe | 647 | |
| mbed_official | 340:28d1f895c6fe | 648 | /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to Prescaler value */ |
| mbed_official | 340:28d1f895c6fe | 649 | CRS->CFGR |= pInit->Prescaler; |
| mbed_official | 340:28d1f895c6fe | 650 | |
| mbed_official | 340:28d1f895c6fe | 651 | /* Set the SYNCSRC[1:0] bits according to Source value */ |
| mbed_official | 340:28d1f895c6fe | 652 | CRS->CFGR |= pInit->Source; |
| mbed_official | 340:28d1f895c6fe | 653 | |
| mbed_official | 340:28d1f895c6fe | 654 | /* Set the SYNCSPOL bits according to Polarity value */ |
| mbed_official | 340:28d1f895c6fe | 655 | CRS->CFGR |= pInit->Polarity; |
| mbed_official | 340:28d1f895c6fe | 656 | |
| mbed_official | 340:28d1f895c6fe | 657 | /* Configure Frequency Error Measurement */ |
| mbed_official | 340:28d1f895c6fe | 658 | /* Clear RELOAD[15:0] & FELIM[7:0] bits*/ |
| mbed_official | 340:28d1f895c6fe | 659 | CRS->CFGR &= ~(CRS_CFGR_RELOAD | CRS_CFGR_FELIM); |
| mbed_official | 340:28d1f895c6fe | 660 | |
| mbed_official | 340:28d1f895c6fe | 661 | /* Set the RELOAD[15:0] bits according to ReloadValue value */ |
| mbed_official | 340:28d1f895c6fe | 662 | CRS->CFGR |= pInit->ReloadValue; |
| mbed_official | 340:28d1f895c6fe | 663 | |
| mbed_official | 340:28d1f895c6fe | 664 | /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ |
| mbed_official | 340:28d1f895c6fe | 665 | CRS->CFGR |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER); |
| mbed_official | 340:28d1f895c6fe | 666 | |
| mbed_official | 340:28d1f895c6fe | 667 | /* Adjust HSI48 oscillator smooth trimming */ |
| mbed_official | 340:28d1f895c6fe | 668 | /* Clear TRIM[5:0] bits */ |
| mbed_official | 340:28d1f895c6fe | 669 | CRS->CR &= ~CRS_CR_TRIM; |
| mbed_official | 340:28d1f895c6fe | 670 | |
| mbed_official | 340:28d1f895c6fe | 671 | /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ |
| mbed_official | 340:28d1f895c6fe | 672 | CRS->CR |= (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER); |
| mbed_official | 340:28d1f895c6fe | 673 | |
| mbed_official | 340:28d1f895c6fe | 674 | |
| mbed_official | 340:28d1f895c6fe | 675 | /* START AUTOMATIC SYNCHRONIZATION*/ |
| mbed_official | 340:28d1f895c6fe | 676 | |
| mbed_official | 340:28d1f895c6fe | 677 | /* Enable Automatic trimming */ |
| mbed_official | 340:28d1f895c6fe | 678 | __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB(); |
| mbed_official | 340:28d1f895c6fe | 679 | |
| mbed_official | 340:28d1f895c6fe | 680 | /* Enable Frequency error counter */ |
| mbed_official | 340:28d1f895c6fe | 681 | __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER(); |
| mbed_official | 340:28d1f895c6fe | 682 | |
| mbed_official | 340:28d1f895c6fe | 683 | } |
| mbed_official | 340:28d1f895c6fe | 684 | |
| mbed_official | 340:28d1f895c6fe | 685 | /** |
| mbed_official | 340:28d1f895c6fe | 686 | * @brief Generate the software synchronization event |
| mbed_official | 340:28d1f895c6fe | 687 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 688 | */ |
| mbed_official | 340:28d1f895c6fe | 689 | void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) |
| mbed_official | 340:28d1f895c6fe | 690 | { |
| mbed_official | 340:28d1f895c6fe | 691 | CRS->CR |= CRS_CR_SWSYNC; |
| mbed_official | 340:28d1f895c6fe | 692 | } |
| mbed_official | 340:28d1f895c6fe | 693 | |
| mbed_official | 340:28d1f895c6fe | 694 | |
| mbed_official | 340:28d1f895c6fe | 695 | /** |
| mbed_official | 340:28d1f895c6fe | 696 | * @brief Function to return synchronization info |
| mbed_official | 340:28d1f895c6fe | 697 | * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure |
| mbed_official | 340:28d1f895c6fe | 698 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 699 | */ |
| mbed_official | 340:28d1f895c6fe | 700 | void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) |
| mbed_official | 340:28d1f895c6fe | 701 | { |
| mbed_official | 340:28d1f895c6fe | 702 | /* Check the parameter */ |
| mbed_official | 441:d2c15dda23c1 | 703 | assert_param(pSynchroInfo != NULL); |
| mbed_official | 340:28d1f895c6fe | 704 | |
| mbed_official | 340:28d1f895c6fe | 705 | /* Get the reload value */ |
| mbed_official | 340:28d1f895c6fe | 706 | pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD); |
| mbed_official | 340:28d1f895c6fe | 707 | |
| mbed_official | 340:28d1f895c6fe | 708 | /* Get HSI48 oscillator smooth trimming */ |
| mbed_official | 340:28d1f895c6fe | 709 | pSynchroInfo->HSI48CalibrationValue = (uint32_t)((CRS->CR & CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER); |
| mbed_official | 340:28d1f895c6fe | 710 | |
| mbed_official | 340:28d1f895c6fe | 711 | /* Get Frequency error capture */ |
| mbed_official | 340:28d1f895c6fe | 712 | pSynchroInfo->FreqErrorCapture = (uint32_t)((CRS->ISR & CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER); |
| mbed_official | 340:28d1f895c6fe | 713 | |
| mbed_official | 340:28d1f895c6fe | 714 | /* Get FFrequency error direction */ |
| mbed_official | 340:28d1f895c6fe | 715 | pSynchroInfo->FreqErrorDirection = (uint32_t)(CRS->ISR & CRS_ISR_FEDIR); |
| mbed_official | 340:28d1f895c6fe | 716 | |
| mbed_official | 340:28d1f895c6fe | 717 | |
| mbed_official | 340:28d1f895c6fe | 718 | } |
| mbed_official | 340:28d1f895c6fe | 719 | |
| mbed_official | 340:28d1f895c6fe | 720 | /** |
| mbed_official | 340:28d1f895c6fe | 721 | * @brief This function handles CRS Synchronization Timeout. |
| mbed_official | 340:28d1f895c6fe | 722 | * @param Timeout: Duration of the timeout |
| mbed_official | 340:28d1f895c6fe | 723 | * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization |
| mbed_official | 340:28d1f895c6fe | 724 | * frequency. |
| mbed_official | 340:28d1f895c6fe | 725 | * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. |
| mbed_official | 340:28d1f895c6fe | 726 | * @retval Combination of Synchronization status |
| mbed_official | 340:28d1f895c6fe | 727 | * This parameter can be a combination of the following values: |
| mbed_official | 340:28d1f895c6fe | 728 | * @arg RCC_CRS_TIMEOUT |
| mbed_official | 340:28d1f895c6fe | 729 | * @arg RCC_CRS_SYNCOK |
| mbed_official | 340:28d1f895c6fe | 730 | * @arg RCC_CRS_SYNCWARM |
| mbed_official | 340:28d1f895c6fe | 731 | * @arg RCC_CRS_SYNCERR |
| mbed_official | 340:28d1f895c6fe | 732 | * @arg RCC_CRS_SYNCMISS |
| mbed_official | 340:28d1f895c6fe | 733 | * @arg RCC_CRS_TRIMOV |
| mbed_official | 340:28d1f895c6fe | 734 | */ |
| mbed_official | 441:d2c15dda23c1 | 735 | uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) |
| mbed_official | 340:28d1f895c6fe | 736 | { |
| mbed_official | 441:d2c15dda23c1 | 737 | uint32_t crsstatus = RCC_CRS_NONE; |
| mbed_official | 340:28d1f895c6fe | 738 | uint32_t tickstart = 0; |
| mbed_official | 340:28d1f895c6fe | 739 | |
| mbed_official | 340:28d1f895c6fe | 740 | /* Get timeout */ |
| mbed_official | 340:28d1f895c6fe | 741 | tickstart = HAL_GetTick(); |
| mbed_official | 340:28d1f895c6fe | 742 | |
| mbed_official | 340:28d1f895c6fe | 743 | /* Check that if one of CRS flags have been set */ |
| mbed_official | 340:28d1f895c6fe | 744 | while(RCC_CRS_NONE == crsstatus) |
| mbed_official | 340:28d1f895c6fe | 745 | { |
| mbed_official | 340:28d1f895c6fe | 746 | if(Timeout != HAL_MAX_DELAY) |
| mbed_official | 340:28d1f895c6fe | 747 | { |
| mbed_official | 340:28d1f895c6fe | 748 | if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) |
| mbed_official | 340:28d1f895c6fe | 749 | { |
| mbed_official | 340:28d1f895c6fe | 750 | crsstatus = RCC_CRS_TIMEOUT; |
| mbed_official | 340:28d1f895c6fe | 751 | } |
| mbed_official | 340:28d1f895c6fe | 752 | } |
| mbed_official | 340:28d1f895c6fe | 753 | /* Check CRS SYNCOK flag */ |
| mbed_official | 340:28d1f895c6fe | 754 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) |
| mbed_official | 340:28d1f895c6fe | 755 | { |
| mbed_official | 340:28d1f895c6fe | 756 | /* CRS SYNC event OK */ |
| mbed_official | 340:28d1f895c6fe | 757 | crsstatus |= RCC_CRS_SYNCOK; |
| mbed_official | 340:28d1f895c6fe | 758 | |
| mbed_official | 340:28d1f895c6fe | 759 | /* Clear CRS SYNC event OK bit */ |
| mbed_official | 340:28d1f895c6fe | 760 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); |
| mbed_official | 340:28d1f895c6fe | 761 | } |
| mbed_official | 340:28d1f895c6fe | 762 | |
| mbed_official | 340:28d1f895c6fe | 763 | /* Check CRS SYNCWARN flag */ |
| mbed_official | 340:28d1f895c6fe | 764 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) |
| mbed_official | 340:28d1f895c6fe | 765 | { |
| mbed_official | 340:28d1f895c6fe | 766 | /* CRS SYNC warning */ |
| mbed_official | 340:28d1f895c6fe | 767 | crsstatus |= RCC_CRS_SYNCWARM; |
| mbed_official | 340:28d1f895c6fe | 768 | |
| mbed_official | 340:28d1f895c6fe | 769 | /* Clear CRS SYNCWARN bit */ |
| mbed_official | 340:28d1f895c6fe | 770 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); |
| mbed_official | 340:28d1f895c6fe | 771 | } |
| mbed_official | 340:28d1f895c6fe | 772 | |
| mbed_official | 340:28d1f895c6fe | 773 | /* Check CRS TRIM overflow flag */ |
| mbed_official | 340:28d1f895c6fe | 774 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) |
| mbed_official | 340:28d1f895c6fe | 775 | { |
| mbed_official | 340:28d1f895c6fe | 776 | /* CRS SYNC Error */ |
| mbed_official | 340:28d1f895c6fe | 777 | crsstatus |= RCC_CRS_TRIMOV; |
| mbed_official | 340:28d1f895c6fe | 778 | |
| mbed_official | 340:28d1f895c6fe | 779 | /* Clear CRS Error bit */ |
| mbed_official | 340:28d1f895c6fe | 780 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); |
| mbed_official | 340:28d1f895c6fe | 781 | } |
| mbed_official | 340:28d1f895c6fe | 782 | |
| mbed_official | 340:28d1f895c6fe | 783 | /* Check CRS Error flag */ |
| mbed_official | 340:28d1f895c6fe | 784 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) |
| mbed_official | 340:28d1f895c6fe | 785 | { |
| mbed_official | 340:28d1f895c6fe | 786 | /* CRS SYNC Error */ |
| mbed_official | 340:28d1f895c6fe | 787 | crsstatus |= RCC_CRS_SYNCERR; |
| mbed_official | 340:28d1f895c6fe | 788 | |
| mbed_official | 340:28d1f895c6fe | 789 | /* Clear CRS Error bit */ |
| mbed_official | 340:28d1f895c6fe | 790 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); |
| mbed_official | 340:28d1f895c6fe | 791 | } |
| mbed_official | 340:28d1f895c6fe | 792 | |
| mbed_official | 340:28d1f895c6fe | 793 | /* Check CRS SYNC Missed flag */ |
| mbed_official | 340:28d1f895c6fe | 794 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) |
| mbed_official | 340:28d1f895c6fe | 795 | { |
| mbed_official | 340:28d1f895c6fe | 796 | /* CRS SYNC Missed */ |
| mbed_official | 340:28d1f895c6fe | 797 | crsstatus |= RCC_CRS_SYNCMISS; |
| mbed_official | 340:28d1f895c6fe | 798 | |
| mbed_official | 340:28d1f895c6fe | 799 | /* Clear CRS SYNC Missed bit */ |
| mbed_official | 340:28d1f895c6fe | 800 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); |
| mbed_official | 340:28d1f895c6fe | 801 | } |
| mbed_official | 340:28d1f895c6fe | 802 | |
| mbed_official | 340:28d1f895c6fe | 803 | /* Check CRS Expected SYNC flag */ |
| mbed_official | 340:28d1f895c6fe | 804 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) |
| mbed_official | 340:28d1f895c6fe | 805 | { |
| mbed_official | 340:28d1f895c6fe | 806 | /* frequency error counter reached a zero value */ |
| mbed_official | 340:28d1f895c6fe | 807 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); |
| mbed_official | 340:28d1f895c6fe | 808 | } |
| mbed_official | 340:28d1f895c6fe | 809 | } |
| mbed_official | 340:28d1f895c6fe | 810 | |
| mbed_official | 340:28d1f895c6fe | 811 | return crsstatus; |
| mbed_official | 340:28d1f895c6fe | 812 | } |
| mbed_official | 340:28d1f895c6fe | 813 | |
| mbed_official | 340:28d1f895c6fe | 814 | #endif /* STM32F042x6 || STM32F048xx || */ |
| mbed_official | 340:28d1f895c6fe | 815 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
| mbed_official | 340:28d1f895c6fe | 816 | /* STM32F091xC || STM32F098xx */ |
| mbed_official | 340:28d1f895c6fe | 817 | |
| mbed_official | 340:28d1f895c6fe | 818 | /** |
| mbed_official | 340:28d1f895c6fe | 819 | * @} |
| mbed_official | 340:28d1f895c6fe | 820 | */ |
| mbed_official | 340:28d1f895c6fe | 821 | |
| mbed_official | 340:28d1f895c6fe | 822 | /** |
| mbed_official | 340:28d1f895c6fe | 823 | * @} |
| mbed_official | 340:28d1f895c6fe | 824 | */ |
| mbed_official | 340:28d1f895c6fe | 825 | |
| mbed_official | 340:28d1f895c6fe | 826 | /** |
| mbed_official | 340:28d1f895c6fe | 827 | * @} |
| mbed_official | 340:28d1f895c6fe | 828 | */ |
| mbed_official | 630:825f75ca301e | 829 | |
| mbed_official | 630:825f75ca301e | 830 | #endif /* HAL_RCC_MODULE_ENABLED */ |
| mbed_official | 340:28d1f895c6fe | 831 | |
| mbed_official | 340:28d1f895c6fe | 832 | /** |
| mbed_official | 340:28d1f895c6fe | 833 | * @} |
| mbed_official | 340:28d1f895c6fe | 834 | */ |
| mbed_official | 340:28d1f895c6fe | 835 | |
| mbed_official | 340:28d1f895c6fe | 836 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
