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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h@630:825f75ca301e, 2015-09-28 (annotated)

Committer:: mbed_official
Date:: Mon Sep 28 10:45:10 2015 +0100
Revision:: 630:825f75ca301e
Parent:: 441:d2c15dda23c1

Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10

Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/

NUCLEO_F031K6 : Add new target

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	340:28d1f895c6fe	1	/**
mbed_official	340:28d1f895c6fe	2	******************************************************************************
mbed_official	340:28d1f895c6fe	3	* @file stm32f0xx_hal_tim.h
mbed_official	340:28d1f895c6fe	4	* @author MCD Application Team
mbed_official	630:825f75ca301e	5	* @version V1.3.0
mbed_official	630:825f75ca301e	6	* @date 26-June-2015
mbed_official	340:28d1f895c6fe	7	* @brief Header file of TIM HAL module.
mbed_official	340:28d1f895c6fe	8	******************************************************************************
mbed_official	340:28d1f895c6fe	9	* @attention
mbed_official	340:28d1f895c6fe	10	*
mbed_official	630:825f75ca301e	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	340:28d1f895c6fe	12	*
mbed_official	340:28d1f895c6fe	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	340:28d1f895c6fe	14	* are permitted provided that the following conditions are met:
mbed_official	340:28d1f895c6fe	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	340:28d1f895c6fe	16	* this list of conditions and the following disclaimer.
mbed_official	340:28d1f895c6fe	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	340:28d1f895c6fe	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	340:28d1f895c6fe	19	* and/or other materials provided with the distribution.
mbed_official	340:28d1f895c6fe	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	340:28d1f895c6fe	21	* may be used to endorse or promote products derived from this software
mbed_official	340:28d1f895c6fe	22	* without specific prior written permission.
mbed_official	340:28d1f895c6fe	23	*
mbed_official	340:28d1f895c6fe	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	340:28d1f895c6fe	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	340:28d1f895c6fe	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	340:28d1f895c6fe	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	340:28d1f895c6fe	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	340:28d1f895c6fe	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	340:28d1f895c6fe	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	340:28d1f895c6fe	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	340:28d1f895c6fe	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	340:28d1f895c6fe	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	340:28d1f895c6fe	34	*
mbed_official	340:28d1f895c6fe	35	******************************************************************************
mbed_official	630:825f75ca301e	36	*/
mbed_official	340:28d1f895c6fe	37
mbed_official	340:28d1f895c6fe	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	340:28d1f895c6fe	39	#ifndef __STM32F0xx_HAL_TIM_H
mbed_official	340:28d1f895c6fe	40	#define __STM32F0xx_HAL_TIM_H
mbed_official	340:28d1f895c6fe	41
mbed_official	340:28d1f895c6fe	42	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	43	extern "C" {
mbed_official	340:28d1f895c6fe	44	#endif
mbed_official	340:28d1f895c6fe	45
mbed_official	340:28d1f895c6fe	46	/* Includes ------------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	47	#include "stm32f0xx_hal_def.h"
mbed_official	340:28d1f895c6fe	48
mbed_official	340:28d1f895c6fe	49	/** @addtogroup STM32F0xx_HAL_Driver
mbed_official	340:28d1f895c6fe	50	* @{
mbed_official	340:28d1f895c6fe	51	*/
mbed_official	340:28d1f895c6fe	52
mbed_official	340:28d1f895c6fe	53	/** @addtogroup TIM
mbed_official	340:28d1f895c6fe	54	* @{
mbed_official	630:825f75ca301e	55	*/
mbed_official	340:28d1f895c6fe	56
mbed_official	630:825f75ca301e	57	/* Exported types ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	58	/** @defgroup TIM_Exported_Types TIM Exported Types
mbed_official	340:28d1f895c6fe	59	* @{
mbed_official	340:28d1f895c6fe	60	*/
mbed_official	630:825f75ca301e	61	/**
mbed_official	630:825f75ca301e	62	* @brief TIM Time base Configuration Structure definition
mbed_official	340:28d1f895c6fe	63	*/
mbed_official	340:28d1f895c6fe	64	typedef struct
mbed_official	340:28d1f895c6fe	65	{
mbed_official	340:28d1f895c6fe	66	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
mbed_official	340:28d1f895c6fe	67	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	340:28d1f895c6fe	68
mbed_official	340:28d1f895c6fe	69	uint32_t CounterMode; /*!< Specifies the counter mode.
mbed_official	340:28d1f895c6fe	70	This parameter can be a value of @ref TIM_Counter_Mode */
mbed_official	340:28d1f895c6fe	71
mbed_official	340:28d1f895c6fe	72	uint32_t Period; /*!< Specifies the period value to be loaded into the active
mbed_official	340:28d1f895c6fe	73	Auto-Reload Register at the next update event.
mbed_official	630:825f75ca301e	74	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
mbed_official	340:28d1f895c6fe	75
mbed_official	340:28d1f895c6fe	76	uint32_t ClockDivision; /*!< Specifies the clock division.
mbed_official	340:28d1f895c6fe	77	This parameter can be a value of @ref TIM_ClockDivision */
mbed_official	340:28d1f895c6fe	78
mbed_official	340:28d1f895c6fe	79	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
mbed_official	340:28d1f895c6fe	80	reaches zero, an update event is generated and counting restarts
mbed_official	340:28d1f895c6fe	81	from the RCR value (N).
mbed_official	340:28d1f895c6fe	82	This means in PWM mode that (N+1) corresponds to:
mbed_official	340:28d1f895c6fe	83	- the number of PWM periods in edge-aligned mode
mbed_official	340:28d1f895c6fe	84	- the number of half PWM period in center-aligned mode
mbed_official	630:825f75ca301e	85	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
mbed_official	340:28d1f895c6fe	86	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	340:28d1f895c6fe	87	} TIM_Base_InitTypeDef;
mbed_official	340:28d1f895c6fe	88
mbed_official	630:825f75ca301e	89	/**
mbed_official	630:825f75ca301e	90	* @brief TIM Output Compare Configuration Structure definition
mbed_official	340:28d1f895c6fe	91	*/
mbed_official	340:28d1f895c6fe	92	typedef struct
mbed_official	630:825f75ca301e	93	{
mbed_official	340:28d1f895c6fe	94	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	340:28d1f895c6fe	95	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	340:28d1f895c6fe	96
mbed_official	630:825f75ca301e	97	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	630:825f75ca301e	98	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	340:28d1f895c6fe	99
mbed_official	340:28d1f895c6fe	100	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	340:28d1f895c6fe	101	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	340:28d1f895c6fe	102
mbed_official	340:28d1f895c6fe	103	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	340:28d1f895c6fe	104	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	340:28d1f895c6fe	105	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	630:825f75ca301e	106
mbed_official	340:28d1f895c6fe	107	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
mbed_official	340:28d1f895c6fe	108	This parameter can be a value of @ref TIM_Output_Fast_State
mbed_official	340:28d1f895c6fe	109	@note This parameter is valid only in PWM1 and PWM2 mode. */
mbed_official	340:28d1f895c6fe	110
mbed_official	340:28d1f895c6fe	111
mbed_official	340:28d1f895c6fe	112	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	340:28d1f895c6fe	113	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	340:28d1f895c6fe	114	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	340:28d1f895c6fe	115
mbed_official	340:28d1f895c6fe	116	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	340:28d1f895c6fe	117	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	340:28d1f895c6fe	118	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	630:825f75ca301e	119	} TIM_OC_InitTypeDef;
mbed_official	340:28d1f895c6fe	120
mbed_official	630:825f75ca301e	121	/**
mbed_official	630:825f75ca301e	122	* @brief TIM One Pulse Mode Configuration Structure definition
mbed_official	340:28d1f895c6fe	123	*/
mbed_official	340:28d1f895c6fe	124	typedef struct
mbed_official	630:825f75ca301e	125	{
mbed_official	340:28d1f895c6fe	126	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	340:28d1f895c6fe	127	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	340:28d1f895c6fe	128
mbed_official	630:825f75ca301e	129	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	630:825f75ca301e	130	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	340:28d1f895c6fe	131
mbed_official	340:28d1f895c6fe	132	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	340:28d1f895c6fe	133	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	340:28d1f895c6fe	134
mbed_official	340:28d1f895c6fe	135	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	340:28d1f895c6fe	136	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	340:28d1f895c6fe	137	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	340:28d1f895c6fe	138
mbed_official	340:28d1f895c6fe	139	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	340:28d1f895c6fe	140	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	340:28d1f895c6fe	141	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	340:28d1f895c6fe	142
mbed_official	340:28d1f895c6fe	143	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	340:28d1f895c6fe	144	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	340:28d1f895c6fe	145	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	340:28d1f895c6fe	146
mbed_official	340:28d1f895c6fe	147	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	340:28d1f895c6fe	148	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	340:28d1f895c6fe	149
mbed_official	340:28d1f895c6fe	150	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	340:28d1f895c6fe	151	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	340:28d1f895c6fe	152
mbed_official	340:28d1f895c6fe	153	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	630:825f75ca301e	154	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	630:825f75ca301e	155	} TIM_OnePulse_InitTypeDef;
mbed_official	340:28d1f895c6fe	156
mbed_official	340:28d1f895c6fe	157
mbed_official	630:825f75ca301e	158	/**
mbed_official	630:825f75ca301e	159	* @brief TIM Input Capture Configuration Structure definition
mbed_official	340:28d1f895c6fe	160	*/
mbed_official	340:28d1f895c6fe	161	typedef struct
mbed_official	630:825f75ca301e	162	{
mbed_official	340:28d1f895c6fe	163	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	340:28d1f895c6fe	164	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	340:28d1f895c6fe	165
mbed_official	340:28d1f895c6fe	166	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	340:28d1f895c6fe	167	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	340:28d1f895c6fe	168
mbed_official	340:28d1f895c6fe	169	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	340:28d1f895c6fe	170	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	340:28d1f895c6fe	171
mbed_official	340:28d1f895c6fe	172	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	340:28d1f895c6fe	173	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	340:28d1f895c6fe	174	} TIM_IC_InitTypeDef;
mbed_official	340:28d1f895c6fe	175
mbed_official	630:825f75ca301e	176	/**
mbed_official	630:825f75ca301e	177	* @brief TIM Encoder Configuration Structure definition
mbed_official	340:28d1f895c6fe	178	*/
mbed_official	340:28d1f895c6fe	179	typedef struct
mbed_official	340:28d1f895c6fe	180	{
mbed_official	340:28d1f895c6fe	181	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
mbed_official	340:28d1f895c6fe	182	This parameter can be a value of @ref TIM_Encoder_Mode */
mbed_official	630:825f75ca301e	183
mbed_official	340:28d1f895c6fe	184	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	340:28d1f895c6fe	185	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	340:28d1f895c6fe	186
mbed_official	340:28d1f895c6fe	187	uint32_t IC1Selection; /*!< Specifies the input.
mbed_official	340:28d1f895c6fe	188	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	340:28d1f895c6fe	189
mbed_official	340:28d1f895c6fe	190	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	340:28d1f895c6fe	191	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	340:28d1f895c6fe	192
mbed_official	340:28d1f895c6fe	193	uint32_t IC1Filter; /*!< Specifies the input capture filter.
mbed_official	340:28d1f895c6fe	194	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	630:825f75ca301e	195
mbed_official	340:28d1f895c6fe	196	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	340:28d1f895c6fe	197	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	340:28d1f895c6fe	198
mbed_official	340:28d1f895c6fe	199	uint32_t IC2Selection; /*!< Specifies the input.
mbed_official	340:28d1f895c6fe	200	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	340:28d1f895c6fe	201
mbed_official	340:28d1f895c6fe	202	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	340:28d1f895c6fe	203	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	340:28d1f895c6fe	204
mbed_official	340:28d1f895c6fe	205	uint32_t IC2Filter; /*!< Specifies the input capture filter.
mbed_official	630:825f75ca301e	206	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	340:28d1f895c6fe	207	} TIM_Encoder_InitTypeDef;
mbed_official	340:28d1f895c6fe	208
mbed_official	340:28d1f895c6fe	209
mbed_official	630:825f75ca301e	210	/**
mbed_official	630:825f75ca301e	211	* @brief TIM Clock Configuration Handle Structure definition
mbed_official	340:28d1f895c6fe	212	*/
mbed_official	340:28d1f895c6fe	213	typedef struct
mbed_official	340:28d1f895c6fe	214	{
mbed_official	340:28d1f895c6fe	215	uint32_t ClockSource; /*!< TIM clock sources
mbed_official	630:825f75ca301e	216	This parameter can be a value of @ref TIM_Clock_Source */
mbed_official	340:28d1f895c6fe	217	uint32_t ClockPolarity; /*!< TIM clock polarity
mbed_official	340:28d1f895c6fe	218	This parameter can be a value of @ref TIM_Clock_Polarity */
mbed_official	340:28d1f895c6fe	219	uint32_t ClockPrescaler; /*!< TIM clock prescaler
mbed_official	340:28d1f895c6fe	220	This parameter can be a value of @ref TIM_Clock_Prescaler */
mbed_official	340:28d1f895c6fe	221	uint32_t ClockFilter; /*!< TIM clock filter
mbed_official	630:825f75ca301e	222	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	340:28d1f895c6fe	223	}TIM_ClockConfigTypeDef;
mbed_official	340:28d1f895c6fe	224
mbed_official	630:825f75ca301e	225	/**
mbed_official	630:825f75ca301e	226	* @brief TIM Clear Input Configuration Handle Structure definition
mbed_official	340:28d1f895c6fe	227	*/
mbed_official	340:28d1f895c6fe	228	typedef struct
mbed_official	630:825f75ca301e	229	{
mbed_official	340:28d1f895c6fe	230	uint32_t ClearInputState; /*!< TIM clear Input state
mbed_official	630:825f75ca301e	231	This parameter can be ENABLE or DISABLE */
mbed_official	340:28d1f895c6fe	232	uint32_t ClearInputSource; /*!< TIM clear Input sources
mbed_official	630:825f75ca301e	233	This parameter can be a value of @ref TIM_ClearInput_Source */
mbed_official	340:28d1f895c6fe	234	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
mbed_official	340:28d1f895c6fe	235	This parameter can be a value of @ref TIM_ClearInput_Polarity */
mbed_official	340:28d1f895c6fe	236	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
mbed_official	340:28d1f895c6fe	237	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
mbed_official	340:28d1f895c6fe	238	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
mbed_official	630:825f75ca301e	239	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	340:28d1f895c6fe	240	}TIM_ClearInputConfigTypeDef;
mbed_official	340:28d1f895c6fe	241
mbed_official	630:825f75ca301e	242	/**
mbed_official	630:825f75ca301e	243	* @brief TIM Slave configuration Structure definition
mbed_official	340:28d1f895c6fe	244	*/
mbed_official	340:28d1f895c6fe	245	typedef struct {
mbed_official	340:28d1f895c6fe	246	uint32_t SlaveMode; /*!< Slave mode selection
mbed_official	630:825f75ca301e	247	This parameter can be a value of @ref TIM_Slave_Mode */
mbed_official	340:28d1f895c6fe	248	uint32_t InputTrigger; /*!< Input Trigger source
mbed_official	340:28d1f895c6fe	249	This parameter can be a value of @ref TIM_Trigger_Selection */
mbed_official	340:28d1f895c6fe	250	uint32_t TriggerPolarity; /*!< Input Trigger polarity
mbed_official	340:28d1f895c6fe	251	This parameter can be a value of @ref TIM_Trigger_Polarity */
mbed_official	340:28d1f895c6fe	252	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
mbed_official	340:28d1f895c6fe	253	This parameter can be a value of @ref TIM_Trigger_Prescaler */
mbed_official	340:28d1f895c6fe	254	uint32_t TriggerFilter; /*!< Input trigger filter
mbed_official	630:825f75ca301e	255	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	340:28d1f895c6fe	256
mbed_official	340:28d1f895c6fe	257	}TIM_SlaveConfigTypeDef;
mbed_official	340:28d1f895c6fe	258
mbed_official	630:825f75ca301e	259	/**
mbed_official	630:825f75ca301e	260	* @brief HAL State structures definition
mbed_official	340:28d1f895c6fe	261	*/
mbed_official	340:28d1f895c6fe	262	typedef enum
mbed_official	340:28d1f895c6fe	263	{
mbed_official	340:28d1f895c6fe	264	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
mbed_official	340:28d1f895c6fe	265	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
mbed_official	630:825f75ca301e	266	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
mbed_official	630:825f75ca301e	267	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
mbed_official	630:825f75ca301e	268	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
mbed_official	340:28d1f895c6fe	269	}HAL_TIM_StateTypeDef;
mbed_official	340:28d1f895c6fe	270
mbed_official	630:825f75ca301e	271	/**
mbed_official	630:825f75ca301e	272	* @brief HAL Active channel structures definition
mbed_official	340:28d1f895c6fe	273	*/
mbed_official	340:28d1f895c6fe	274	typedef enum
mbed_official	340:28d1f895c6fe	275	{
mbed_official	340:28d1f895c6fe	276	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
mbed_official	340:28d1f895c6fe	277	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
mbed_official	630:825f75ca301e	278	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
mbed_official	340:28d1f895c6fe	279	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
mbed_official	630:825f75ca301e	280	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
mbed_official	340:28d1f895c6fe	281	}HAL_TIM_ActiveChannel;
mbed_official	340:28d1f895c6fe	282
mbed_official	630:825f75ca301e	283	/**
mbed_official	630:825f75ca301e	284	* @brief TIM Time Base Handle Structure definition
mbed_official	340:28d1f895c6fe	285	*/
mbed_official	340:28d1f895c6fe	286	typedef struct
mbed_official	340:28d1f895c6fe	287	{
mbed_official	630:825f75ca301e	288	TIM_TypeDef Instance; /!< Register base address */
mbed_official	340:28d1f895c6fe	289	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
mbed_official	630:825f75ca301e	290	HAL_TIM_ActiveChannel Channel; /!< Active channel /
mbed_official	340:28d1f895c6fe	291	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
mbed_official	441:d2c15dda23c1	292	This array is accessed by a @ref TIM_DMA_Handle_index */
mbed_official	340:28d1f895c6fe	293	HAL_LockTypeDef Lock; /!< Locking object /
mbed_official	630:825f75ca301e	294	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
mbed_official	340:28d1f895c6fe	295	}TIM_HandleTypeDef;
mbed_official	340:28d1f895c6fe	296
mbed_official	340:28d1f895c6fe	297	/**
mbed_official	340:28d1f895c6fe	298	* @}
mbed_official	340:28d1f895c6fe	299	*/
mbed_official	340:28d1f895c6fe	300
mbed_official	340:28d1f895c6fe	301	/* Exported constants --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	302	/** @defgroup TIM_Exported_Constants TIM Exported Constants
mbed_official	340:28d1f895c6fe	303	* @{
mbed_official	340:28d1f895c6fe	304	*/
mbed_official	340:28d1f895c6fe	305
mbed_official	630:825f75ca301e	306	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
mbed_official	340:28d1f895c6fe	307	* @{
mbed_official	340:28d1f895c6fe	308	*/
mbed_official	340:28d1f895c6fe	309	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
mbed_official	340:28d1f895c6fe	310	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
mbed_official	340:28d1f895c6fe	311	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
mbed_official	340:28d1f895c6fe	312	/**
mbed_official	340:28d1f895c6fe	313	* @}
mbed_official	340:28d1f895c6fe	314	*/
mbed_official	340:28d1f895c6fe	315
mbed_official	340:28d1f895c6fe	316	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
mbed_official	340:28d1f895c6fe	317	* @{
mbed_official	340:28d1f895c6fe	318	*/
mbed_official	630:825f75ca301e	319	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
mbed_official	630:825f75ca301e	320	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
mbed_official	340:28d1f895c6fe	321	/**
mbed_official	340:28d1f895c6fe	322	* @}
mbed_official	340:28d1f895c6fe	323	*/
mbed_official	340:28d1f895c6fe	324
mbed_official	340:28d1f895c6fe	325	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
mbed_official	340:28d1f895c6fe	326	* @{
mbed_official	340:28d1f895c6fe	327	*/
mbed_official	340:28d1f895c6fe	328	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
mbed_official	340:28d1f895c6fe	329	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
mbed_official	340:28d1f895c6fe	330	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
mbed_official	340:28d1f895c6fe	331	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
mbed_official	340:28d1f895c6fe	332	/**
mbed_official	340:28d1f895c6fe	333	* @}
mbed_official	340:28d1f895c6fe	334	*/
mbed_official	340:28d1f895c6fe	335
mbed_official	340:28d1f895c6fe	336	/** @defgroup TIM_Counter_Mode TIM Counter Mode
mbed_official	340:28d1f895c6fe	337	* @{
mbed_official	340:28d1f895c6fe	338	*/
mbed_official	340:28d1f895c6fe	339	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	340	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
mbed_official	340:28d1f895c6fe	341	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
mbed_official	340:28d1f895c6fe	342	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
mbed_official	340:28d1f895c6fe	343	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
mbed_official	340:28d1f895c6fe	344	/**
mbed_official	340:28d1f895c6fe	345	* @}
mbed_official	340:28d1f895c6fe	346	*/
mbed_official	340:28d1f895c6fe	347
mbed_official	630:825f75ca301e	348	/** @defgroup TIM_ClockDivision TIM Clock Division
mbed_official	340:28d1f895c6fe	349	* @{
mbed_official	340:28d1f895c6fe	350	*/
mbed_official	630:825f75ca301e	351	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
mbed_official	630:825f75ca301e	352	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
mbed_official	630:825f75ca301e	353	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
mbed_official	630:825f75ca301e	354	/**
mbed_official	630:825f75ca301e	355	* @}
mbed_official	630:825f75ca301e	356	*/
mbed_official	340:28d1f895c6fe	357
mbed_official	630:825f75ca301e	358	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
mbed_official	630:825f75ca301e	359	* @{
mbed_official	630:825f75ca301e	360	*/
mbed_official	340:28d1f895c6fe	361	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	362	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
mbed_official	340:28d1f895c6fe	363	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
mbed_official	340:28d1f895c6fe	364	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
mbed_official	340:28d1f895c6fe	365	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
mbed_official	340:28d1f895c6fe	366	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
mbed_official	340:28d1f895c6fe	367	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
mbed_official	340:28d1f895c6fe	368	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
mbed_official	340:28d1f895c6fe	369	/**
mbed_official	340:28d1f895c6fe	370	* @}
mbed_official	340:28d1f895c6fe	371	*/
mbed_official	340:28d1f895c6fe	372
mbed_official	340:28d1f895c6fe	373	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
mbed_official	340:28d1f895c6fe	374	* @{
mbed_official	340:28d1f895c6fe	375	*/
mbed_official	340:28d1f895c6fe	376	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	377	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
mbed_official	340:28d1f895c6fe	378	/**
mbed_official	340:28d1f895c6fe	379	* @}
mbed_official	340:28d1f895c6fe	380	*/
mbed_official	340:28d1f895c6fe	381
mbed_official	340:28d1f895c6fe	382	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
mbed_official	340:28d1f895c6fe	383	* @{
mbed_official	340:28d1f895c6fe	384	*/
mbed_official	340:28d1f895c6fe	385	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	386	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
mbed_official	340:28d1f895c6fe	387	/**
mbed_official	340:28d1f895c6fe	388	* @}
mbed_official	340:28d1f895c6fe	389	*/
mbed_official	340:28d1f895c6fe	390
mbed_official	340:28d1f895c6fe	391	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
mbed_official	340:28d1f895c6fe	392	* @{
mbed_official	630:825f75ca301e	393	*/
mbed_official	340:28d1f895c6fe	394	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	395	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
mbed_official	340:28d1f895c6fe	396	/**
mbed_official	340:28d1f895c6fe	397	* @}
mbed_official	340:28d1f895c6fe	398	*/
mbed_official	340:28d1f895c6fe	399
mbed_official	340:28d1f895c6fe	400	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
mbed_official	340:28d1f895c6fe	401	* @{
mbed_official	340:28d1f895c6fe	402	*/
mbed_official	340:28d1f895c6fe	403	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
mbed_official	340:28d1f895c6fe	404	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	405	/**
mbed_official	340:28d1f895c6fe	406	* @}
mbed_official	340:28d1f895c6fe	407	*/
mbed_official	340:28d1f895c6fe	408
mbed_official	340:28d1f895c6fe	409	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
mbed_official	340:28d1f895c6fe	410	* @{
mbed_official	340:28d1f895c6fe	411	*/
mbed_official	340:28d1f895c6fe	412	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
mbed_official	340:28d1f895c6fe	413	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	414	/**
mbed_official	340:28d1f895c6fe	415	* @}
mbed_official	340:28d1f895c6fe	416	*/
mbed_official	340:28d1f895c6fe	417
mbed_official	340:28d1f895c6fe	418	/** @defgroup TIM_Channel TIM Channel
mbed_official	340:28d1f895c6fe	419	* @{
mbed_official	340:28d1f895c6fe	420	*/
mbed_official	340:28d1f895c6fe	421	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	422	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
mbed_official	340:28d1f895c6fe	423	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
mbed_official	340:28d1f895c6fe	424	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
mbed_official	340:28d1f895c6fe	425	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
mbed_official	340:28d1f895c6fe	426	/**
mbed_official	340:28d1f895c6fe	427	* @}
mbed_official	340:28d1f895c6fe	428	*/
mbed_official	340:28d1f895c6fe	429
mbed_official	340:28d1f895c6fe	430	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
mbed_official	340:28d1f895c6fe	431	* @{
mbed_official	340:28d1f895c6fe	432	*/
mbed_official	340:28d1f895c6fe	433	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
mbed_official	340:28d1f895c6fe	434	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
mbed_official	340:28d1f895c6fe	435	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
mbed_official	340:28d1f895c6fe	436	/**
mbed_official	340:28d1f895c6fe	437	* @}
mbed_official	340:28d1f895c6fe	438	*/
mbed_official	340:28d1f895c6fe	439
mbed_official	340:28d1f895c6fe	440	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
mbed_official	340:28d1f895c6fe	441	* @{
mbed_official	340:28d1f895c6fe	442	*/
mbed_official	340:28d1f895c6fe	443	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	340:28d1f895c6fe	444	connected to IC1, IC2, IC3 or IC4, respectively */
mbed_official	340:28d1f895c6fe	445	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	340:28d1f895c6fe	446	connected to IC2, IC1, IC4 or IC3, respectively */
mbed_official	340:28d1f895c6fe	447	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
mbed_official	340:28d1f895c6fe	448	/**
mbed_official	340:28d1f895c6fe	449	* @}
mbed_official	340:28d1f895c6fe	450	*/
mbed_official	340:28d1f895c6fe	451
mbed_official	340:28d1f895c6fe	452	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
mbed_official	340:28d1f895c6fe	453	* @{
mbed_official	340:28d1f895c6fe	454	*/
mbed_official	340:28d1f895c6fe	455	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
mbed_official	340:28d1f895c6fe	456	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
mbed_official	340:28d1f895c6fe	457	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
mbed_official	340:28d1f895c6fe	458	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
mbed_official	340:28d1f895c6fe	459	/**
mbed_official	340:28d1f895c6fe	460	* @}
mbed_official	340:28d1f895c6fe	461	*/
mbed_official	340:28d1f895c6fe	462
mbed_official	340:28d1f895c6fe	463	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
mbed_official	340:28d1f895c6fe	464	* @{
mbed_official	340:28d1f895c6fe	465	*/
mbed_official	340:28d1f895c6fe	466	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
mbed_official	340:28d1f895c6fe	467	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	468	/**
mbed_official	340:28d1f895c6fe	469	* @}
mbed_official	340:28d1f895c6fe	470	*/
mbed_official	630:825f75ca301e	471
mbed_official	340:28d1f895c6fe	472	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
mbed_official	340:28d1f895c6fe	473	* @{
mbed_official	630:825f75ca301e	474	*/
mbed_official	340:28d1f895c6fe	475	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
mbed_official	340:28d1f895c6fe	476	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
mbed_official	340:28d1f895c6fe	477	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
mbed_official	340:28d1f895c6fe	478	/**
mbed_official	340:28d1f895c6fe	479	* @}
mbed_official	340:28d1f895c6fe	480	*/
mbed_official	630:825f75ca301e	481
mbed_official	630:825f75ca301e	482	/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
mbed_official	340:28d1f895c6fe	483	* @{
mbed_official	630:825f75ca301e	484	*/
mbed_official	340:28d1f895c6fe	485	#define TIM_IT_UPDATE (TIM_DIER_UIE)
mbed_official	340:28d1f895c6fe	486	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
mbed_official	340:28d1f895c6fe	487	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
mbed_official	340:28d1f895c6fe	488	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
mbed_official	340:28d1f895c6fe	489	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
mbed_official	340:28d1f895c6fe	490	#define TIM_IT_COM (TIM_DIER_COMIE)
mbed_official	340:28d1f895c6fe	491	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
mbed_official	340:28d1f895c6fe	492	#define TIM_IT_BREAK (TIM_DIER_BIE)
mbed_official	340:28d1f895c6fe	493	/**
mbed_official	340:28d1f895c6fe	494	* @}
mbed_official	340:28d1f895c6fe	495	*/
mbed_official	340:28d1f895c6fe	496
mbed_official	630:825f75ca301e	497	/** @defgroup TIM_Commutation_Source TIM Commutation Source
mbed_official	340:28d1f895c6fe	498	* @{
mbed_official	340:28d1f895c6fe	499	*/
mbed_official	340:28d1f895c6fe	500	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
mbed_official	340:28d1f895c6fe	501	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	502
mbed_official	340:28d1f895c6fe	503	/**
mbed_official	340:28d1f895c6fe	504	* @}
mbed_official	340:28d1f895c6fe	505	*/
mbed_official	630:825f75ca301e	506
mbed_official	340:28d1f895c6fe	507	/** @defgroup TIM_DMA_sources TIM DMA Sources
mbed_official	340:28d1f895c6fe	508	* @{
mbed_official	340:28d1f895c6fe	509	*/
mbed_official	340:28d1f895c6fe	510	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
mbed_official	340:28d1f895c6fe	511	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
mbed_official	340:28d1f895c6fe	512	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
mbed_official	340:28d1f895c6fe	513	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
mbed_official	340:28d1f895c6fe	514	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
mbed_official	340:28d1f895c6fe	515	#define TIM_DMA_COM (TIM_DIER_COMDE)
mbed_official	340:28d1f895c6fe	516	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
mbed_official	340:28d1f895c6fe	517	/**
mbed_official	340:28d1f895c6fe	518	* @}
mbed_official	340:28d1f895c6fe	519	*/
mbed_official	340:28d1f895c6fe	520
mbed_official	340:28d1f895c6fe	521	/** @defgroup TIM_Event_Source TIM Event Source
mbed_official	340:28d1f895c6fe	522	* @{
mbed_official	340:28d1f895c6fe	523	*/
mbed_official	630:825f75ca301e	524	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
mbed_official	630:825f75ca301e	525	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
mbed_official	630:825f75ca301e	526	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
mbed_official	630:825f75ca301e	527	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
mbed_official	630:825f75ca301e	528	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
mbed_official	630:825f75ca301e	529	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
mbed_official	630:825f75ca301e	530	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
mbed_official	630:825f75ca301e	531	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
mbed_official	340:28d1f895c6fe	532	/**
mbed_official	340:28d1f895c6fe	533	* @}
mbed_official	340:28d1f895c6fe	534	*/
mbed_official	340:28d1f895c6fe	535
mbed_official	340:28d1f895c6fe	536	/** @defgroup TIM_Flag_definition TIM Flag Definition
mbed_official	340:28d1f895c6fe	537	* @{
mbed_official	340:28d1f895c6fe	538	*/
mbed_official	340:28d1f895c6fe	539	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
mbed_official	340:28d1f895c6fe	540	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
mbed_official	340:28d1f895c6fe	541	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
mbed_official	340:28d1f895c6fe	542	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
mbed_official	340:28d1f895c6fe	543	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
mbed_official	340:28d1f895c6fe	544	#define TIM_FLAG_COM (TIM_SR_COMIF)
mbed_official	340:28d1f895c6fe	545	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
mbed_official	340:28d1f895c6fe	546	#define TIM_FLAG_BREAK (TIM_SR_BIF)
mbed_official	340:28d1f895c6fe	547	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
mbed_official	340:28d1f895c6fe	548	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
mbed_official	340:28d1f895c6fe	549	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
mbed_official	340:28d1f895c6fe	550	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
mbed_official	340:28d1f895c6fe	551	/**
mbed_official	340:28d1f895c6fe	552	* @}
mbed_official	340:28d1f895c6fe	553	*/
mbed_official	340:28d1f895c6fe	554
mbed_official	340:28d1f895c6fe	555	/** @defgroup TIM_Clock_Source TIM Clock Source
mbed_official	340:28d1f895c6fe	556	* @{
mbed_official	340:28d1f895c6fe	557	*/
mbed_official	630:825f75ca301e	558	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
mbed_official	630:825f75ca301e	559	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
mbed_official	340:28d1f895c6fe	560	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	561	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
mbed_official	340:28d1f895c6fe	562	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
mbed_official	340:28d1f895c6fe	563	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
mbed_official	340:28d1f895c6fe	564	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
mbed_official	340:28d1f895c6fe	565	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
mbed_official	340:28d1f895c6fe	566	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
mbed_official	340:28d1f895c6fe	567	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
mbed_official	340:28d1f895c6fe	568	/**
mbed_official	340:28d1f895c6fe	569	* @}
mbed_official	340:28d1f895c6fe	570	*/
mbed_official	340:28d1f895c6fe	571
mbed_official	340:28d1f895c6fe	572	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
mbed_official	340:28d1f895c6fe	573	* @{
mbed_official	340:28d1f895c6fe	574	*/
mbed_official	630:825f75ca301e	575	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
mbed_official	630:825f75ca301e	576	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
mbed_official	630:825f75ca301e	577	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
mbed_official	630:825f75ca301e	578	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
mbed_official	630:825f75ca301e	579	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
mbed_official	340:28d1f895c6fe	580	/**
mbed_official	340:28d1f895c6fe	581	* @}
mbed_official	340:28d1f895c6fe	582	*/
mbed_official	630:825f75ca301e	583
mbed_official	340:28d1f895c6fe	584	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
mbed_official	340:28d1f895c6fe	585	* @{
mbed_official	630:825f75ca301e	586	*/
mbed_official	340:28d1f895c6fe	587	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	340:28d1f895c6fe	588	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
mbed_official	340:28d1f895c6fe	589	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
mbed_official	340:28d1f895c6fe	590	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
mbed_official	340:28d1f895c6fe	591	/**
mbed_official	340:28d1f895c6fe	592	* @}
mbed_official	340:28d1f895c6fe	593	*/
mbed_official	340:28d1f895c6fe	594
mbed_official	340:28d1f895c6fe	595	/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
mbed_official	340:28d1f895c6fe	596	* @{
mbed_official	340:28d1f895c6fe	597	*/
mbed_official	630:825f75ca301e	598	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
mbed_official	340:28d1f895c6fe	599	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	600	/**
mbed_official	340:28d1f895c6fe	601	* @}
mbed_official	340:28d1f895c6fe	602	*/
mbed_official	340:28d1f895c6fe	603
mbed_official	340:28d1f895c6fe	604	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
mbed_official	340:28d1f895c6fe	605	* @{
mbed_official	340:28d1f895c6fe	606	*/
mbed_official	630:825f75ca301e	607	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
mbed_official	630:825f75ca301e	608	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
mbed_official	340:28d1f895c6fe	609	/**
mbed_official	340:28d1f895c6fe	610	* @}
mbed_official	630:825f75ca301e	611	*/
mbed_official	340:28d1f895c6fe	612
mbed_official	340:28d1f895c6fe	613	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
mbed_official	340:28d1f895c6fe	614	* @{
mbed_official	340:28d1f895c6fe	615	*/
mbed_official	340:28d1f895c6fe	616	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	340:28d1f895c6fe	617	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
mbed_official	340:28d1f895c6fe	618	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
mbed_official	340:28d1f895c6fe	619	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
mbed_official	340:28d1f895c6fe	620	/**
mbed_official	340:28d1f895c6fe	621	* @}
mbed_official	340:28d1f895c6fe	622	*/
mbed_official	340:28d1f895c6fe	623
mbed_official	630:825f75ca301e	624	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
mbed_official	340:28d1f895c6fe	625	* @{
mbed_official	340:28d1f895c6fe	626	*/
mbed_official	340:28d1f895c6fe	627	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
mbed_official	340:28d1f895c6fe	628	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	629	/**
mbed_official	340:28d1f895c6fe	630	* @}
mbed_official	340:28d1f895c6fe	631	*/
mbed_official	340:28d1f895c6fe	632
mbed_official	630:825f75ca301e	633	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
mbed_official	340:28d1f895c6fe	634	* @{
mbed_official	340:28d1f895c6fe	635	*/
mbed_official	340:28d1f895c6fe	636	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
mbed_official	340:28d1f895c6fe	637	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	638	/**
mbed_official	340:28d1f895c6fe	639	* @}
mbed_official	340:28d1f895c6fe	640	*/
mbed_official	630:825f75ca301e	641
mbed_official	630:825f75ca301e	642	/** @defgroup TIM_Lock_level TIM Lock level
mbed_official	340:28d1f895c6fe	643	* @{
mbed_official	340:28d1f895c6fe	644	*/
mbed_official	340:28d1f895c6fe	645	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	646	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
mbed_official	340:28d1f895c6fe	647	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
mbed_official	340:28d1f895c6fe	648	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
mbed_official	340:28d1f895c6fe	649	/**
mbed_official	340:28d1f895c6fe	650	* @}
mbed_official	340:28d1f895c6fe	651	*/
mbed_official	630:825f75ca301e	652
mbed_official	630:825f75ca301e	653	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
mbed_official	340:28d1f895c6fe	654	* @{
mbed_official	340:28d1f895c6fe	655	*/
mbed_official	340:28d1f895c6fe	656	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
mbed_official	340:28d1f895c6fe	657	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	658	/**
mbed_official	340:28d1f895c6fe	659	* @}
mbed_official	340:28d1f895c6fe	660	*/
mbed_official	630:825f75ca301e	661
mbed_official	340:28d1f895c6fe	662	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
mbed_official	340:28d1f895c6fe	663	* @{
mbed_official	340:28d1f895c6fe	664	*/
mbed_official	340:28d1f895c6fe	665	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	666	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
mbed_official	340:28d1f895c6fe	667	/**
mbed_official	340:28d1f895c6fe	668	* @}
mbed_official	340:28d1f895c6fe	669	*/
mbed_official	340:28d1f895c6fe	670	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
mbed_official	340:28d1f895c6fe	671	* @{
mbed_official	340:28d1f895c6fe	672	*/
mbed_official	340:28d1f895c6fe	673	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
mbed_official	340:28d1f895c6fe	674	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	675	/**
mbed_official	340:28d1f895c6fe	676	* @}
mbed_official	340:28d1f895c6fe	677	*/
mbed_official	340:28d1f895c6fe	678
mbed_official	340:28d1f895c6fe	679	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
mbed_official	340:28d1f895c6fe	680	* @{
mbed_official	340:28d1f895c6fe	681	*/
mbed_official	630:825f75ca301e	682	#define TIM_TRGO_RESET ((uint32_t)0x0000)
mbed_official	630:825f75ca301e	683	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
mbed_official	630:825f75ca301e	684	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
mbed_official	630:825f75ca301e	685	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	630:825f75ca301e	686	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
mbed_official	630:825f75ca301e	687	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
mbed_official	630:825f75ca301e	688	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
mbed_official	630:825f75ca301e	689	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	340:28d1f895c6fe	690	/**
mbed_official	340:28d1f895c6fe	691	* @}
mbed_official	630:825f75ca301e	692	*/
mbed_official	340:28d1f895c6fe	693
mbed_official	340:28d1f895c6fe	694	/** @defgroup TIM_Slave_Mode TIM Slave Mode
mbed_official	340:28d1f895c6fe	695	* @{
mbed_official	340:28d1f895c6fe	696	*/
mbed_official	340:28d1f895c6fe	697	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	698	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
mbed_official	340:28d1f895c6fe	699	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
mbed_official	340:28d1f895c6fe	700	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
mbed_official	340:28d1f895c6fe	701	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
mbed_official	340:28d1f895c6fe	702	/**
mbed_official	340:28d1f895c6fe	703	* @}
mbed_official	340:28d1f895c6fe	704	*/
mbed_official	340:28d1f895c6fe	705
mbed_official	630:825f75ca301e	706	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
mbed_official	340:28d1f895c6fe	707	* @{
mbed_official	340:28d1f895c6fe	708	*/
mbed_official	340:28d1f895c6fe	709	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
mbed_official	340:28d1f895c6fe	710	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	711	/**
mbed_official	340:28d1f895c6fe	712	* @}
mbed_official	340:28d1f895c6fe	713	*/
mbed_official	630:825f75ca301e	714
mbed_official	340:28d1f895c6fe	715	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
mbed_official	340:28d1f895c6fe	716	* @{
mbed_official	340:28d1f895c6fe	717	*/
mbed_official	340:28d1f895c6fe	718	#define TIM_TS_ITR0 ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	719	#define TIM_TS_ITR1 ((uint32_t)0x0010)
mbed_official	340:28d1f895c6fe	720	#define TIM_TS_ITR2 ((uint32_t)0x0020)
mbed_official	340:28d1f895c6fe	721	#define TIM_TS_ITR3 ((uint32_t)0x0030)
mbed_official	340:28d1f895c6fe	722	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
mbed_official	340:28d1f895c6fe	723	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
mbed_official	340:28d1f895c6fe	724	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
mbed_official	340:28d1f895c6fe	725	#define TIM_TS_ETRF ((uint32_t)0x0070)
mbed_official	340:28d1f895c6fe	726	#define TIM_TS_NONE ((uint32_t)0xFFFF)
mbed_official	340:28d1f895c6fe	727	/**
mbed_official	340:28d1f895c6fe	728	* @}
mbed_official	340:28d1f895c6fe	729	*/
mbed_official	340:28d1f895c6fe	730
mbed_official	340:28d1f895c6fe	731	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
mbed_official	340:28d1f895c6fe	732	* @{
mbed_official	340:28d1f895c6fe	733	*/
mbed_official	630:825f75ca301e	734	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
mbed_official	630:825f75ca301e	735	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
mbed_official	630:825f75ca301e	736	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	630:825f75ca301e	737	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	630:825f75ca301e	738	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	340:28d1f895c6fe	739	/**
mbed_official	340:28d1f895c6fe	740	* @}
mbed_official	340:28d1f895c6fe	741	*/
mbed_official	340:28d1f895c6fe	742
mbed_official	340:28d1f895c6fe	743	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
mbed_official	340:28d1f895c6fe	744	* @{
mbed_official	340:28d1f895c6fe	745	*/
mbed_official	340:28d1f895c6fe	746	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	340:28d1f895c6fe	747	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
mbed_official	340:28d1f895c6fe	748	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
mbed_official	340:28d1f895c6fe	749	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
mbed_official	340:28d1f895c6fe	750	/**
mbed_official	340:28d1f895c6fe	751	* @}
mbed_official	340:28d1f895c6fe	752	*/
mbed_official	340:28d1f895c6fe	753
mbed_official	340:28d1f895c6fe	754	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
mbed_official	340:28d1f895c6fe	755	* @{
mbed_official	340:28d1f895c6fe	756	*/
mbed_official	340:28d1f895c6fe	757	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	758	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
mbed_official	340:28d1f895c6fe	759	/**
mbed_official	340:28d1f895c6fe	760	* @}
mbed_official	340:28d1f895c6fe	761	*/
mbed_official	340:28d1f895c6fe	762
mbed_official	630:825f75ca301e	763	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
mbed_official	340:28d1f895c6fe	764	* @{
mbed_official	340:28d1f895c6fe	765	*/
mbed_official	630:825f75ca301e	766	#define TIM_DMABASE_CR1 (0x00000000)
mbed_official	630:825f75ca301e	767	#define TIM_DMABASE_CR2 (0x00000001)
mbed_official	630:825f75ca301e	768	#define TIM_DMABASE_SMCR (0x00000002)
mbed_official	630:825f75ca301e	769	#define TIM_DMABASE_DIER (0x00000003)
mbed_official	630:825f75ca301e	770	#define TIM_DMABASE_SR (0x00000004)
mbed_official	630:825f75ca301e	771	#define TIM_DMABASE_EGR (0x00000005)
mbed_official	630:825f75ca301e	772	#define TIM_DMABASE_CCMR1 (0x00000006)
mbed_official	630:825f75ca301e	773	#define TIM_DMABASE_CCMR2 (0x00000007)
mbed_official	630:825f75ca301e	774	#define TIM_DMABASE_CCER (0x00000008)
mbed_official	630:825f75ca301e	775	#define TIM_DMABASE_CNT (0x00000009)
mbed_official	630:825f75ca301e	776	#define TIM_DMABASE_PSC (0x0000000A)
mbed_official	630:825f75ca301e	777	#define TIM_DMABASE_ARR (0x0000000B)
mbed_official	630:825f75ca301e	778	#define TIM_DMABASE_RCR (0x0000000C)
mbed_official	630:825f75ca301e	779	#define TIM_DMABASE_CCR1 (0x0000000D)
mbed_official	630:825f75ca301e	780	#define TIM_DMABASE_CCR2 (0x0000000E)
mbed_official	630:825f75ca301e	781	#define TIM_DMABASE_CCR3 (0x0000000F)
mbed_official	630:825f75ca301e	782	#define TIM_DMABASE_CCR4 (0x00000010)
mbed_official	630:825f75ca301e	783	#define TIM_DMABASE_BDTR (0x00000011)
mbed_official	630:825f75ca301e	784	#define TIM_DMABASE_DCR (0x00000012)
mbed_official	630:825f75ca301e	785	#define TIM_DMABASE_OR (0x00000013)
mbed_official	340:28d1f895c6fe	786	/**
mbed_official	340:28d1f895c6fe	787	* @}
mbed_official	340:28d1f895c6fe	788	*/
mbed_official	340:28d1f895c6fe	789
mbed_official	340:28d1f895c6fe	790	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
mbed_official	340:28d1f895c6fe	791	* @{
mbed_official	340:28d1f895c6fe	792	*/
mbed_official	630:825f75ca301e	793	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
mbed_official	630:825f75ca301e	794	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
mbed_official	630:825f75ca301e	795	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
mbed_official	630:825f75ca301e	796	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
mbed_official	630:825f75ca301e	797	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
mbed_official	630:825f75ca301e	798	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
mbed_official	630:825f75ca301e	799	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
mbed_official	630:825f75ca301e	800	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
mbed_official	630:825f75ca301e	801	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
mbed_official	630:825f75ca301e	802	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
mbed_official	630:825f75ca301e	803	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
mbed_official	630:825f75ca301e	804	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
mbed_official	630:825f75ca301e	805	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
mbed_official	630:825f75ca301e	806	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
mbed_official	630:825f75ca301e	807	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
mbed_official	630:825f75ca301e	808	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
mbed_official	630:825f75ca301e	809	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
mbed_official	630:825f75ca301e	810	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
mbed_official	340:28d1f895c6fe	811	/**
mbed_official	340:28d1f895c6fe	812	* @}
mbed_official	340:28d1f895c6fe	813	*/
mbed_official	340:28d1f895c6fe	814
mbed_official	441:d2c15dda23c1	815	/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
mbed_official	340:28d1f895c6fe	816	* @{
mbed_official	340:28d1f895c6fe	817	*/
mbed_official	340:28d1f895c6fe	818	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
mbed_official	340:28d1f895c6fe	819	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
mbed_official	340:28d1f895c6fe	820	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
mbed_official	340:28d1f895c6fe	821	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
mbed_official	340:28d1f895c6fe	822	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
mbed_official	340:28d1f895c6fe	823	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
mbed_official	340:28d1f895c6fe	824	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
mbed_official	340:28d1f895c6fe	825	/**
mbed_official	340:28d1f895c6fe	826	* @}
mbed_official	340:28d1f895c6fe	827	*/
mbed_official	340:28d1f895c6fe	828
mbed_official	630:825f75ca301e	829	/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
mbed_official	340:28d1f895c6fe	830	* @{
mbed_official	340:28d1f895c6fe	831	*/
mbed_official	340:28d1f895c6fe	832	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
mbed_official	340:28d1f895c6fe	833	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	834	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
mbed_official	340:28d1f895c6fe	835	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	836	/**
mbed_official	340:28d1f895c6fe	837	* @}
mbed_official	340:28d1f895c6fe	838	*/
mbed_official	340:28d1f895c6fe	839
mbed_official	340:28d1f895c6fe	840	/**
mbed_official	340:28d1f895c6fe	841	* @}
mbed_official	340:28d1f895c6fe	842	*/
mbed_official	630:825f75ca301e	843
mbed_official	630:825f75ca301e	844	/* Private Constants -----------------------------------------------------------*/
mbed_official	630:825f75ca301e	845	/** @defgroup TIM_Private_Constants TIM Private Constants
mbed_official	630:825f75ca301e	846	* @{
mbed_official	630:825f75ca301e	847	*/
mbed_official	630:825f75ca301e	848
mbed_official	630:825f75ca301e	849	/* The counter of a timer instance is disabled only if all the CCx and CCxN
mbed_official	630:825f75ca301e	850	channels have been disabled */
mbed_official	630:825f75ca301e	851	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
mbed_official	630:825f75ca301e	852	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
mbed_official	630:825f75ca301e	853
mbed_official	630:825f75ca301e	854	/**
mbed_official	630:825f75ca301e	855	* @}
mbed_official	630:825f75ca301e	856	*/
mbed_official	630:825f75ca301e	857
mbed_official	630:825f75ca301e	858	/* Private Macros -----------------------------------------------------------*/
mbed_official	630:825f75ca301e	859	/** @defgroup TIM_Private_Macros TIM Private Macros
mbed_official	630:825f75ca301e	860	* @{
mbed_official	630:825f75ca301e	861	*/
mbed_official	630:825f75ca301e	862
mbed_official	630:825f75ca301e	863	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
mbed_official	630:825f75ca301e	864	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
mbed_official	630:825f75ca301e	865	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
mbed_official	630:825f75ca301e	866	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
mbed_official	630:825f75ca301e	867	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
mbed_official	630:825f75ca301e	868
mbed_official	630:825f75ca301e	869	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
mbed_official	630:825f75ca301e	870	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
mbed_official	630:825f75ca301e	871	((DIV) == TIM_CLOCKDIVISION_DIV4))
mbed_official	630:825f75ca301e	872
mbed_official	630:825f75ca301e	873	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
mbed_official	630:825f75ca301e	874	((MODE) == TIM_OCMODE_PWM2))
mbed_official	630:825f75ca301e	875
mbed_official	630:825f75ca301e	876	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
mbed_official	630:825f75ca301e	877	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
mbed_official	630:825f75ca301e	878	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
mbed_official	630:825f75ca301e	879	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
mbed_official	630:825f75ca301e	880	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
mbed_official	630:825f75ca301e	881	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
mbed_official	630:825f75ca301e	882
mbed_official	630:825f75ca301e	883	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
mbed_official	630:825f75ca301e	884	((STATE) == TIM_OCFAST_ENABLE))
mbed_official	630:825f75ca301e	885
mbed_official	630:825f75ca301e	886	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
mbed_official	630:825f75ca301e	887	((POLARITY) == TIM_OCPOLARITY_LOW))
mbed_official	630:825f75ca301e	888
mbed_official	630:825f75ca301e	889	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
mbed_official	630:825f75ca301e	890	((POLARITY) == TIM_OCNPOLARITY_LOW))
mbed_official	630:825f75ca301e	891
mbed_official	630:825f75ca301e	892	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
mbed_official	630:825f75ca301e	893	((STATE) == TIM_OCIDLESTATE_RESET))
mbed_official	630:825f75ca301e	894
mbed_official	630:825f75ca301e	895	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
mbed_official	630:825f75ca301e	896	((STATE) == TIM_OCNIDLESTATE_RESET))
mbed_official	630:825f75ca301e	897
mbed_official	630:825f75ca301e	898	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	630:825f75ca301e	899	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	630:825f75ca301e	900	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	630:825f75ca301e	901	((CHANNEL) == TIM_CHANNEL_4) \|\| \
mbed_official	630:825f75ca301e	902	((CHANNEL) == TIM_CHANNEL_ALL))
mbed_official	630:825f75ca301e	903
mbed_official	630:825f75ca301e	904	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	630:825f75ca301e	905	((CHANNEL) == TIM_CHANNEL_2))
mbed_official	630:825f75ca301e	906
mbed_official	630:825f75ca301e	907	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	630:825f75ca301e	908	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	630:825f75ca301e	909	((CHANNEL) == TIM_CHANNEL_3))
mbed_official	630:825f75ca301e	910
mbed_official	630:825f75ca301e	911	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
mbed_official	630:825f75ca301e	912	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
mbed_official	630:825f75ca301e	913	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
mbed_official	630:825f75ca301e	914
mbed_official	630:825f75ca301e	915	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
mbed_official	630:825f75ca301e	916	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
mbed_official	630:825f75ca301e	917	((SELECTION) == TIM_ICSELECTION_TRC))
mbed_official	630:825f75ca301e	918
mbed_official	630:825f75ca301e	919	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
mbed_official	630:825f75ca301e	920	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
mbed_official	630:825f75ca301e	921	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
mbed_official	630:825f75ca301e	922	((PRESCALER) == TIM_ICPSC_DIV8))
mbed_official	630:825f75ca301e	923
mbed_official	630:825f75ca301e	924	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
mbed_official	630:825f75ca301e	925	((MODE) == TIM_OPMODE_REPETITIVE))
mbed_official	630:825f75ca301e	926
mbed_official	630:825f75ca301e	927	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
mbed_official	630:825f75ca301e	928	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
mbed_official	630:825f75ca301e	929	((MODE) == TIM_ENCODERMODE_TI12))
mbed_official	630:825f75ca301e	930
mbed_official	630:825f75ca301e	931	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	630:825f75ca301e	932
mbed_official	630:825f75ca301e	933	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	630:825f75ca301e	934
mbed_official	630:825f75ca301e	935	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
mbed_official	630:825f75ca301e	936	((FLAG) == TIM_FLAG_CC1) \|\| \
mbed_official	630:825f75ca301e	937	((FLAG) == TIM_FLAG_CC2) \|\| \
mbed_official	630:825f75ca301e	938	((FLAG) == TIM_FLAG_CC3) \|\| \
mbed_official	630:825f75ca301e	939	((FLAG) == TIM_FLAG_CC4) \|\| \
mbed_official	630:825f75ca301e	940	((FLAG) == TIM_FLAG_COM) \|\| \
mbed_official	630:825f75ca301e	941	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
mbed_official	630:825f75ca301e	942	((FLAG) == TIM_FLAG_BREAK) \|\| \
mbed_official	630:825f75ca301e	943	((FLAG) == TIM_FLAG_CC1OF) \|\| \
mbed_official	630:825f75ca301e	944	((FLAG) == TIM_FLAG_CC2OF) \|\| \
mbed_official	630:825f75ca301e	945	((FLAG) == TIM_FLAG_CC3OF) \|\| \
mbed_official	630:825f75ca301e	946	((FLAG) == TIM_FLAG_CC4OF))
mbed_official	630:825f75ca301e	947
mbed_official	630:825f75ca301e	948	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
mbed_official	630:825f75ca301e	949	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
mbed_official	630:825f75ca301e	950	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
mbed_official	630:825f75ca301e	951	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
mbed_official	630:825f75ca301e	952	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
mbed_official	630:825f75ca301e	953	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
mbed_official	630:825f75ca301e	954	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
mbed_official	630:825f75ca301e	955	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
mbed_official	630:825f75ca301e	956	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
mbed_official	630:825f75ca301e	957	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
mbed_official	630:825f75ca301e	958
mbed_official	630:825f75ca301e	959	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
mbed_official	630:825f75ca301e	960	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
mbed_official	630:825f75ca301e	961	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
mbed_official	630:825f75ca301e	962	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
mbed_official	630:825f75ca301e	963	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
mbed_official	630:825f75ca301e	964
mbed_official	630:825f75ca301e	965	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
mbed_official	630:825f75ca301e	966	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
mbed_official	630:825f75ca301e	967	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
mbed_official	630:825f75ca301e	968	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
mbed_official	630:825f75ca301e	969
mbed_official	630:825f75ca301e	970	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	630:825f75ca301e	971
mbed_official	630:825f75ca301e	972	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
mbed_official	630:825f75ca301e	973	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
mbed_official	630:825f75ca301e	974
mbed_official	630:825f75ca301e	975	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
mbed_official	630:825f75ca301e	976	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
mbed_official	630:825f75ca301e	977
mbed_official	630:825f75ca301e	978	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
mbed_official	630:825f75ca301e	979	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
mbed_official	630:825f75ca301e	980	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
mbed_official	630:825f75ca301e	981	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
mbed_official	630:825f75ca301e	982
mbed_official	630:825f75ca301e	983	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	630:825f75ca301e	984
mbed_official	630:825f75ca301e	985	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
mbed_official	630:825f75ca301e	986	((STATE) == TIM_OSSR_DISABLE))
mbed_official	630:825f75ca301e	987
mbed_official	630:825f75ca301e	988	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
mbed_official	630:825f75ca301e	989	((STATE) == TIM_OSSI_DISABLE))
mbed_official	630:825f75ca301e	990
mbed_official	630:825f75ca301e	991	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
mbed_official	630:825f75ca301e	992	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
mbed_official	630:825f75ca301e	993	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
mbed_official	630:825f75ca301e	994	((LEVEL) == TIM_LOCKLEVEL_3))
mbed_official	630:825f75ca301e	995
mbed_official	630:825f75ca301e	996	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
mbed_official	630:825f75ca301e	997	((STATE) == TIM_BREAK_DISABLE))
mbed_official	630:825f75ca301e	998
mbed_official	630:825f75ca301e	999	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
mbed_official	630:825f75ca301e	1000	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
mbed_official	630:825f75ca301e	1001
mbed_official	630:825f75ca301e	1002	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
mbed_official	630:825f75ca301e	1003	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
mbed_official	630:825f75ca301e	1004
mbed_official	630:825f75ca301e	1005	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
mbed_official	630:825f75ca301e	1006	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
mbed_official	630:825f75ca301e	1007	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
mbed_official	630:825f75ca301e	1008	((SOURCE) == TIM_TRGO_OC1) \|\| \
mbed_official	630:825f75ca301e	1009	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
mbed_official	630:825f75ca301e	1010	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
mbed_official	630:825f75ca301e	1011	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
mbed_official	630:825f75ca301e	1012	((SOURCE) == TIM_TRGO_OC4REF))
mbed_official	630:825f75ca301e	1013
mbed_official	630:825f75ca301e	1014	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
mbed_official	630:825f75ca301e	1015	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
mbed_official	630:825f75ca301e	1016	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
mbed_official	630:825f75ca301e	1017	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
mbed_official	630:825f75ca301e	1018	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
mbed_official	630:825f75ca301e	1019
mbed_official	630:825f75ca301e	1020	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
mbed_official	630:825f75ca301e	1021	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
mbed_official	630:825f75ca301e	1022
mbed_official	630:825f75ca301e	1023	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	630:825f75ca301e	1024	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	630:825f75ca301e	1025	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	630:825f75ca301e	1026	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	630:825f75ca301e	1027	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
mbed_official	630:825f75ca301e	1028	((SELECTION) == TIM_TS_TI1FP1) \|\| \
mbed_official	630:825f75ca301e	1029	((SELECTION) == TIM_TS_TI2FP2) \|\| \
mbed_official	630:825f75ca301e	1030	((SELECTION) == TIM_TS_ETRF))
mbed_official	630:825f75ca301e	1031
mbed_official	630:825f75ca301e	1032	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	630:825f75ca301e	1033	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	630:825f75ca301e	1034	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	630:825f75ca301e	1035	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	630:825f75ca301e	1036	((SELECTION) == TIM_TS_NONE))
mbed_official	630:825f75ca301e	1037
mbed_official	630:825f75ca301e	1038	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
mbed_official	630:825f75ca301e	1039	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
mbed_official	630:825f75ca301e	1040	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
mbed_official	630:825f75ca301e	1041	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
mbed_official	630:825f75ca301e	1042	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
mbed_official	630:825f75ca301e	1043
mbed_official	630:825f75ca301e	1044	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
mbed_official	630:825f75ca301e	1045	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
mbed_official	630:825f75ca301e	1046	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
mbed_official	630:825f75ca301e	1047	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
mbed_official	630:825f75ca301e	1048
mbed_official	630:825f75ca301e	1049	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	630:825f75ca301e	1050
mbed_official	630:825f75ca301e	1051	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
mbed_official	630:825f75ca301e	1052	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
mbed_official	630:825f75ca301e	1053
mbed_official	630:825f75ca301e	1054	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
mbed_official	630:825f75ca301e	1055	((BASE) == TIM_DMABASE_CR2) \|\| \
mbed_official	630:825f75ca301e	1056	((BASE) == TIM_DMABASE_SMCR) \|\| \
mbed_official	630:825f75ca301e	1057	((BASE) == TIM_DMABASE_DIER) \|\| \
mbed_official	630:825f75ca301e	1058	((BASE) == TIM_DMABASE_SR) \|\| \
mbed_official	630:825f75ca301e	1059	((BASE) == TIM_DMABASE_EGR) \|\| \
mbed_official	630:825f75ca301e	1060	((BASE) == TIM_DMABASE_CCMR1) \|\| \
mbed_official	630:825f75ca301e	1061	((BASE) == TIM_DMABASE_CCMR2) \|\| \
mbed_official	630:825f75ca301e	1062	((BASE) == TIM_DMABASE_CCER) \|\| \
mbed_official	630:825f75ca301e	1063	((BASE) == TIM_DMABASE_CNT) \|\| \
mbed_official	630:825f75ca301e	1064	((BASE) == TIM_DMABASE_PSC) \|\| \
mbed_official	630:825f75ca301e	1065	((BASE) == TIM_DMABASE_ARR) \|\| \
mbed_official	630:825f75ca301e	1066	((BASE) == TIM_DMABASE_RCR) \|\| \
mbed_official	630:825f75ca301e	1067	((BASE) == TIM_DMABASE_CCR1) \|\| \
mbed_official	630:825f75ca301e	1068	((BASE) == TIM_DMABASE_CCR2) \|\| \
mbed_official	630:825f75ca301e	1069	((BASE) == TIM_DMABASE_CCR3) \|\| \
mbed_official	630:825f75ca301e	1070	((BASE) == TIM_DMABASE_CCR4) \|\| \
mbed_official	630:825f75ca301e	1071	((BASE) == TIM_DMABASE_BDTR) \|\| \
mbed_official	630:825f75ca301e	1072	((BASE) == TIM_DMABASE_DCR) \|\| \
mbed_official	630:825f75ca301e	1073	((BASE) == TIM_DMABASE_OR))
mbed_official	630:825f75ca301e	1074
mbed_official	630:825f75ca301e	1075	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
mbed_official	630:825f75ca301e	1076	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1077	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1078	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1079	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1080	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1081	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1082	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1083	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1084	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1085	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1086	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1087	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1088	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1089	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1090	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1091	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
mbed_official	630:825f75ca301e	1092	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
mbed_official	630:825f75ca301e	1093
mbed_official	630:825f75ca301e	1094	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	630:825f75ca301e	1095
mbed_official	630:825f75ca301e	1096	/** @brief Set TIM IC prescaler
mbed_official	630:825f75ca301e	1097	* @param __HANDLE__: TIM handle
mbed_official	630:825f75ca301e	1098	* @param __CHANNEL__: specifies TIM Channel
mbed_official	630:825f75ca301e	1099	* @param __ICPSC__: specifies the prescaler value.
mbed_official	630:825f75ca301e	1100	* @retval None
mbed_official	630:825f75ca301e	1101	*/
mbed_official	630:825f75ca301e	1102	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	630:825f75ca301e	1103	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
mbed_official	630:825f75ca301e	1104	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
mbed_official	630:825f75ca301e	1105	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
mbed_official	630:825f75ca301e	1106	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
mbed_official	630:825f75ca301e	1107
mbed_official	630:825f75ca301e	1108	/** @brief Reset TIM IC prescaler
mbed_official	630:825f75ca301e	1109	* @param __HANDLE__: TIM handle
mbed_official	630:825f75ca301e	1110	* @param __CHANNEL__: specifies TIM Channel
mbed_official	630:825f75ca301e	1111	* @retval None
mbed_official	630:825f75ca301e	1112	*/
mbed_official	630:825f75ca301e	1113	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
mbed_official	630:825f75ca301e	1114	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
mbed_official	630:825f75ca301e	1115	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
mbed_official	630:825f75ca301e	1116	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
mbed_official	630:825f75ca301e	1117	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
mbed_official	630:825f75ca301e	1118
mbed_official	630:825f75ca301e	1119
mbed_official	630:825f75ca301e	1120	/** @brief Set TIM IC polarity
mbed_official	630:825f75ca301e	1121	* @param __HANDLE__: TIM handle
mbed_official	630:825f75ca301e	1122	* @param __CHANNEL__: specifies TIM Channel
mbed_official	630:825f75ca301e	1123	* @param __POLARITY__: specifies TIM Channel Polarity
mbed_official	630:825f75ca301e	1124	* @retval None
mbed_official	630:825f75ca301e	1125	*/
mbed_official	630:825f75ca301e	1126	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
mbed_official	630:825f75ca301e	1127	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
mbed_official	630:825f75ca301e	1128	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4)) :\
mbed_official	630:825f75ca301e	1129	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8)) :\
mbed_official	630:825f75ca301e	1130	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
mbed_official	630:825f75ca301e	1131
mbed_official	630:825f75ca301e	1132	/** @brief Reset TIM IC polarity
mbed_official	630:825f75ca301e	1133	* @param __HANDLE__: TIM handle
mbed_official	630:825f75ca301e	1134	* @param __CHANNEL__: specifies TIM Channel
mbed_official	630:825f75ca301e	1135	* @retval None
mbed_official	630:825f75ca301e	1136	*/
mbed_official	630:825f75ca301e	1137	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
mbed_official	630:825f75ca301e	1138	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
mbed_official	630:825f75ca301e	1139	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
mbed_official	630:825f75ca301e	1140	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
mbed_official	630:825f75ca301e	1141	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
mbed_official	630:825f75ca301e	1142
mbed_official	630:825f75ca301e	1143	/**
mbed_official	630:825f75ca301e	1144	* @}
mbed_official	630:825f75ca301e	1145	*/
mbed_official	630:825f75ca301e	1146
mbed_official	630:825f75ca301e	1147	/* Private Functions --------------------------------------------------------*/
mbed_official	630:825f75ca301e	1148	/** @addtogroup TIM_Private_Functions
mbed_official	630:825f75ca301e	1149	* @{
mbed_official	630:825f75ca301e	1150	*/
mbed_official	630:825f75ca301e	1151	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
mbed_official	630:825f75ca301e	1152	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
mbed_official	630:825f75ca301e	1153	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	630:825f75ca301e	1154	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
mbed_official	630:825f75ca301e	1155	void TIM_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	630:825f75ca301e	1156	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
mbed_official	630:825f75ca301e	1157	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
mbed_official	630:825f75ca301e	1158	/**
mbed_official	630:825f75ca301e	1159	* @}
mbed_official	630:825f75ca301e	1160	*/
mbed_official	630:825f75ca301e	1161
mbed_official	340:28d1f895c6fe	1162	/* Exported macros -----------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	1163	/** @defgroup TIM_Exported_Macros TIM Exported Macros
mbed_official	340:28d1f895c6fe	1164	* @{
mbed_official	340:28d1f895c6fe	1165	*/
mbed_official	340:28d1f895c6fe	1166
mbed_official	340:28d1f895c6fe	1167	/** @brief Reset TIM handle state
mbed_official	340:28d1f895c6fe	1168	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1169	* @retval None
mbed_official	340:28d1f895c6fe	1170	*/
mbed_official	340:28d1f895c6fe	1171	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
mbed_official	340:28d1f895c6fe	1172
mbed_official	340:28d1f895c6fe	1173	/**
mbed_official	340:28d1f895c6fe	1174	* @brief Enable the TIM peripheral.
mbed_official	340:28d1f895c6fe	1175	* @param __HANDLE__: TIM handle
mbed_official	340:28d1f895c6fe	1176	* @retval None
mbed_official	340:28d1f895c6fe	1177	*/
mbed_official	340:28d1f895c6fe	1178	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
mbed_official	340:28d1f895c6fe	1179
mbed_official	340:28d1f895c6fe	1180	/**
mbed_official	340:28d1f895c6fe	1181	* @brief Enable the TIM main Output.
mbed_official	340:28d1f895c6fe	1182	* @param __HANDLE__: TIM handle
mbed_official	340:28d1f895c6fe	1183	* @retval None
mbed_official	340:28d1f895c6fe	1184	*/
mbed_official	340:28d1f895c6fe	1185	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
mbed_official	340:28d1f895c6fe	1186
mbed_official	340:28d1f895c6fe	1187	/**
mbed_official	340:28d1f895c6fe	1188	* @brief Disable the TIM peripheral.
mbed_official	340:28d1f895c6fe	1189	* @param __HANDLE__: TIM handle
mbed_official	340:28d1f895c6fe	1190	* @retval None
mbed_official	340:28d1f895c6fe	1191	*/
mbed_official	340:28d1f895c6fe	1192	#define __HAL_TIM_DISABLE(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1193	do { \
mbed_official	630:825f75ca301e	1194	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
mbed_official	340:28d1f895c6fe	1195	{ \
mbed_official	630:825f75ca301e	1196	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
mbed_official	340:28d1f895c6fe	1197	{ \
mbed_official	340:28d1f895c6fe	1198	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
mbed_official	340:28d1f895c6fe	1199	} \
mbed_official	340:28d1f895c6fe	1200	} \
mbed_official	340:28d1f895c6fe	1201	} while(0)
mbed_official	340:28d1f895c6fe	1202	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
mbed_official	630:825f75ca301e	1203	channels have been disabled */
mbed_official	340:28d1f895c6fe	1204	/**
mbed_official	340:28d1f895c6fe	1205	* @brief Disable the TIM main Output.
mbed_official	340:28d1f895c6fe	1206	* @param __HANDLE__: TIM handle
mbed_official	340:28d1f895c6fe	1207	* @retval None
mbed_official	630:825f75ca301e	1208	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
mbed_official	340:28d1f895c6fe	1209	*/
mbed_official	340:28d1f895c6fe	1210	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1211	do { \
mbed_official	630:825f75ca301e	1212	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
mbed_official	340:28d1f895c6fe	1213	{ \
mbed_official	630:825f75ca301e	1214	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
mbed_official	340:28d1f895c6fe	1215	{ \
mbed_official	340:28d1f895c6fe	1216	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
mbed_official	340:28d1f895c6fe	1217	} \
mbed_official	340:28d1f895c6fe	1218	} \
mbed_official	340:28d1f895c6fe	1219	} while(0)
mbed_official	340:28d1f895c6fe	1220
mbed_official	630:825f75ca301e	1221	/**
mbed_official	630:825f75ca301e	1222	* @brief Enables the specified TIM interrupt.
mbed_official	630:825f75ca301e	1223	* @param __HANDLE__: specifies the TIM Handle.
mbed_official	630:825f75ca301e	1224	* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
mbed_official	630:825f75ca301e	1225	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1226	* @arg TIM_IT_UPDATE: Update interrupt
mbed_official	630:825f75ca301e	1227	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
mbed_official	630:825f75ca301e	1228	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
mbed_official	630:825f75ca301e	1229	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
mbed_official	630:825f75ca301e	1230	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
mbed_official	630:825f75ca301e	1231	* @arg TIM_IT_COM: Commutation interrupt
mbed_official	630:825f75ca301e	1232	* @arg TIM_IT_TRIGGER: Trigger interrupt
mbed_official	630:825f75ca301e	1233	* @arg TIM_IT_BREAK: Break interrupt
mbed_official	630:825f75ca301e	1234	* @retval None
mbed_official	630:825f75ca301e	1235	*/
mbed_official	340:28d1f895c6fe	1236	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
mbed_official	630:825f75ca301e	1237
mbed_official	630:825f75ca301e	1238	/**
mbed_official	630:825f75ca301e	1239	* @brief Disables the specified TIM interrupt.
mbed_official	630:825f75ca301e	1240	* @param __HANDLE__: specifies the TIM Handle.
mbed_official	630:825f75ca301e	1241	* @param __INTERRUPT__: specifies the TIM interrupt source to disable.
mbed_official	630:825f75ca301e	1242	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1243	* @arg TIM_IT_UPDATE: Update interrupt
mbed_official	630:825f75ca301e	1244	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
mbed_official	630:825f75ca301e	1245	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
mbed_official	630:825f75ca301e	1246	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
mbed_official	630:825f75ca301e	1247	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
mbed_official	630:825f75ca301e	1248	* @arg TIM_IT_COM: Commutation interrupt
mbed_official	630:825f75ca301e	1249	* @arg TIM_IT_TRIGGER: Trigger interrupt
mbed_official	630:825f75ca301e	1250	* @arg TIM_IT_BREAK: Break interrupt
mbed_official	630:825f75ca301e	1251	* @retval None
mbed_official	630:825f75ca301e	1252	*/
mbed_official	340:28d1f895c6fe	1253	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
mbed_official	630:825f75ca301e	1254
mbed_official	630:825f75ca301e	1255	/**
mbed_official	630:825f75ca301e	1256	* @brief Enables the specified DMA request.
mbed_official	630:825f75ca301e	1257	* @param __HANDLE__: specifies the TIM Handle.
mbed_official	630:825f75ca301e	1258	* @param __DMA__: specifies the TIM DMA request to enable.
mbed_official	630:825f75ca301e	1259	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1260	* @arg TIM_DMA_UPDATE: Update DMA request
mbed_official	630:825f75ca301e	1261	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
mbed_official	630:825f75ca301e	1262	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
mbed_official	630:825f75ca301e	1263	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
mbed_official	630:825f75ca301e	1264	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
mbed_official	630:825f75ca301e	1265	* @arg TIM_DMA_COM: Commutation DMA request
mbed_official	630:825f75ca301e	1266	* @arg TIM_DMA_TRIGGER: Trigger DMA request
mbed_official	630:825f75ca301e	1267	* @retval None
mbed_official	630:825f75ca301e	1268	*/
mbed_official	630:825f75ca301e	1269	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
mbed_official	630:825f75ca301e	1270
mbed_official	630:825f75ca301e	1271	/**
mbed_official	630:825f75ca301e	1272	* @brief Disables the specified DMA request.
mbed_official	630:825f75ca301e	1273	* @param __HANDLE__: specifies the TIM Handle.
mbed_official	630:825f75ca301e	1274	* @param __DMA__: specifies the TIM DMA request to disable.
mbed_official	630:825f75ca301e	1275	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1276	* @arg TIM_DMA_UPDATE: Update DMA request
mbed_official	630:825f75ca301e	1277	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
mbed_official	630:825f75ca301e	1278	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
mbed_official	630:825f75ca301e	1279	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
mbed_official	630:825f75ca301e	1280	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
mbed_official	630:825f75ca301e	1281	* @arg TIM_DMA_COM: Commutation DMA request
mbed_official	630:825f75ca301e	1282	* @arg TIM_DMA_TRIGGER: Trigger DMA request
mbed_official	630:825f75ca301e	1283	* @retval None
mbed_official	630:825f75ca301e	1284	*/
mbed_official	340:28d1f895c6fe	1285	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
mbed_official	630:825f75ca301e	1286
mbed_official	630:825f75ca301e	1287	/**
mbed_official	630:825f75ca301e	1288	* @brief Checks whether the specified TIM interrupt flag is set or not.
mbed_official	630:825f75ca301e	1289	* @param __HANDLE__: specifies the TIM Handle.
mbed_official	630:825f75ca301e	1290	* @param __FLAG__: specifies the TIM interrupt flag to check.
mbed_official	630:825f75ca301e	1291	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1292	* @arg TIM_FLAG_UPDATE: Update interrupt flag
mbed_official	630:825f75ca301e	1293	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
mbed_official	630:825f75ca301e	1294	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
mbed_official	630:825f75ca301e	1295	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
mbed_official	630:825f75ca301e	1296	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
mbed_official	630:825f75ca301e	1297	* @arg TIM_FLAG_COM: Commutation interrupt flag
mbed_official	630:825f75ca301e	1298	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
mbed_official	630:825f75ca301e	1299	* @arg TIM_FLAG_BREAK: Break interrupt flag
mbed_official	630:825f75ca301e	1300	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
mbed_official	630:825f75ca301e	1301	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
mbed_official	630:825f75ca301e	1302	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
mbed_official	630:825f75ca301e	1303	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
mbed_official	630:825f75ca301e	1304	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	630:825f75ca301e	1305	*/
mbed_official	340:28d1f895c6fe	1306	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
mbed_official	630:825f75ca301e	1307
mbed_official	630:825f75ca301e	1308	/**
mbed_official	630:825f75ca301e	1309	* @brief Clears the specified TIM interrupt flag.
mbed_official	630:825f75ca301e	1310	* @param __HANDLE__: specifies the TIM Handle.
mbed_official	630:825f75ca301e	1311	* @param __FLAG__: specifies the TIM interrupt flag to clear.
mbed_official	630:825f75ca301e	1312	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1313	* @arg TIM_FLAG_UPDATE: Update interrupt flag
mbed_official	630:825f75ca301e	1314	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
mbed_official	630:825f75ca301e	1315	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
mbed_official	630:825f75ca301e	1316	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
mbed_official	630:825f75ca301e	1317	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
mbed_official	630:825f75ca301e	1318	* @arg TIM_FLAG_COM: Commutation interrupt flag
mbed_official	630:825f75ca301e	1319	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
mbed_official	630:825f75ca301e	1320	* @arg TIM_FLAG_BREAK: Break interrupt flag
mbed_official	630:825f75ca301e	1321	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
mbed_official	630:825f75ca301e	1322	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
mbed_official	630:825f75ca301e	1323	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
mbed_official	630:825f75ca301e	1324	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
mbed_official	630:825f75ca301e	1325	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	630:825f75ca301e	1326	*/
mbed_official	340:28d1f895c6fe	1327	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
mbed_official	340:28d1f895c6fe	1328
mbed_official	630:825f75ca301e	1329	/**
mbed_official	630:825f75ca301e	1330	* @brief Checks whether the specified TIM interrupt has occurred or not.
mbed_official	630:825f75ca301e	1331	* @param __HANDLE__: TIM handle
mbed_official	630:825f75ca301e	1332	* @param __INTERRUPT__: specifies the TIM interrupt source to check.
mbed_official	630:825f75ca301e	1333	* @retval The state of TIM_IT (SET or RESET).
mbed_official	630:825f75ca301e	1334	*/
mbed_official	630:825f75ca301e	1335	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
mbed_official	630:825f75ca301e	1336
mbed_official	630:825f75ca301e	1337	/**
mbed_official	630:825f75ca301e	1338	* @brief Clear the TIM interrupt pending bits
mbed_official	630:825f75ca301e	1339	* @param __HANDLE__: TIM handle
mbed_official	630:825f75ca301e	1340	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	630:825f75ca301e	1341	* @retval None
mbed_official	630:825f75ca301e	1342	*/
mbed_official	340:28d1f895c6fe	1343	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
mbed_official	340:28d1f895c6fe	1344
mbed_official	630:825f75ca301e	1345	/**
mbed_official	630:825f75ca301e	1346	* @brief Indicates whether or not the TIM Counter is used as downcounter
mbed_official	630:825f75ca301e	1347	* @param __HANDLE__: TIM handle.
mbed_official	630:825f75ca301e	1348	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
mbed_official	630:825f75ca301e	1349	* @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
mbed_official	630:825f75ca301e	1350	mode.
mbed_official	630:825f75ca301e	1351	*/
mbed_official	630:825f75ca301e	1352	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
mbed_official	340:28d1f895c6fe	1353
mbed_official	630:825f75ca301e	1354	/**
mbed_official	630:825f75ca301e	1355	* @brief Sets the TIM active prescaler register value on update event.
mbed_official	630:825f75ca301e	1356	* @param __HANDLE__: TIM handle.
mbed_official	630:825f75ca301e	1357	* @param __PRESC__: specifies the active prescaler register new value.
mbed_official	630:825f75ca301e	1358	* @retval None
mbed_official	630:825f75ca301e	1359	*/
mbed_official	630:825f75ca301e	1360	#define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
mbed_official	340:28d1f895c6fe	1361
mbed_official	340:28d1f895c6fe	1362	/**
mbed_official	340:28d1f895c6fe	1363	* @brief Sets the TIM Capture Compare Register value on runtime without
mbed_official	340:28d1f895c6fe	1364	* calling another time ConfigChannel function.
mbed_official	340:28d1f895c6fe	1365	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1366	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	340:28d1f895c6fe	1367	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1368	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1369	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1370	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1371	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1372	* @param __COMPARE__: specifies the Capture Compare register new value.
mbed_official	340:28d1f895c6fe	1373	* @retval None
mbed_official	340:28d1f895c6fe	1374	*/
mbed_official	630:825f75ca301e	1375	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
mbed_official	340:28d1f895c6fe	1376	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
mbed_official	340:28d1f895c6fe	1377
mbed_official	340:28d1f895c6fe	1378	/**
mbed_official	340:28d1f895c6fe	1379	* @brief Gets the TIM Capture Compare Register value on runtime
mbed_official	340:28d1f895c6fe	1380	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1381	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
mbed_official	340:28d1f895c6fe	1382	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1383	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
mbed_official	340:28d1f895c6fe	1384	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
mbed_official	340:28d1f895c6fe	1385	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
mbed_official	340:28d1f895c6fe	1386	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
mbed_official	340:28d1f895c6fe	1387	* @retval None
mbed_official	340:28d1f895c6fe	1388	*/
mbed_official	630:825f75ca301e	1389	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
mbed_official	340:28d1f895c6fe	1390	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
mbed_official	340:28d1f895c6fe	1391
mbed_official	340:28d1f895c6fe	1392	/**
mbed_official	340:28d1f895c6fe	1393	* @brief Sets the TIM Counter Register value on runtime.
mbed_official	340:28d1f895c6fe	1394	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1395	* @param __COUNTER__: specifies the Counter register new value.
mbed_official	340:28d1f895c6fe	1396	* @retval None
mbed_official	340:28d1f895c6fe	1397	*/
mbed_official	630:825f75ca301e	1398	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
mbed_official	340:28d1f895c6fe	1399
mbed_official	340:28d1f895c6fe	1400	/**
mbed_official	340:28d1f895c6fe	1401	* @brief Gets the TIM Counter Register value on runtime.
mbed_official	340:28d1f895c6fe	1402	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1403	* @retval None
mbed_official	340:28d1f895c6fe	1404	*/
mbed_official	630:825f75ca301e	1405	#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1406	((__HANDLE__)->Instance->CNT)
mbed_official	630:825f75ca301e	1407
mbed_official	340:28d1f895c6fe	1408	/**
mbed_official	340:28d1f895c6fe	1409	* @brief Sets the TIM Autoreload Register value on runtime without calling
mbed_official	340:28d1f895c6fe	1410	* another time any Init function.
mbed_official	340:28d1f895c6fe	1411	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1412	* @param __AUTORELOAD__: specifies the Counter register new value.
mbed_official	340:28d1f895c6fe	1413	* @retval None
mbed_official	340:28d1f895c6fe	1414	*/
mbed_official	630:825f75ca301e	1415	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
mbed_official	340:28d1f895c6fe	1416	do{ \
mbed_official	340:28d1f895c6fe	1417	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
mbed_official	340:28d1f895c6fe	1418	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
mbed_official	340:28d1f895c6fe	1419	} while(0)
mbed_official	340:28d1f895c6fe	1420
mbed_official	340:28d1f895c6fe	1421	/**
mbed_official	340:28d1f895c6fe	1422	* @brief Gets the TIM Autoreload Register value on runtime
mbed_official	340:28d1f895c6fe	1423	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1424	* @retval None
mbed_official	340:28d1f895c6fe	1425	*/
mbed_official	630:825f75ca301e	1426	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1427	((__HANDLE__)->Instance->ARR)
mbed_official	630:825f75ca301e	1428
mbed_official	340:28d1f895c6fe	1429	/**
mbed_official	340:28d1f895c6fe	1430	* @brief Sets the TIM Clock Division value on runtime without calling
mbed_official	630:825f75ca301e	1431	* another time any Init function.
mbed_official	340:28d1f895c6fe	1432	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1433	* @param __CKD__: specifies the clock division value.
mbed_official	340:28d1f895c6fe	1434	* This parameter can be one of the following value:
mbed_official	340:28d1f895c6fe	1435	* @arg TIM_CLOCKDIVISION_DIV1
mbed_official	340:28d1f895c6fe	1436	* @arg TIM_CLOCKDIVISION_DIV2
mbed_official	630:825f75ca301e	1437	* @arg TIM_CLOCKDIVISION_DIV4
mbed_official	340:28d1f895c6fe	1438	* @retval None
mbed_official	340:28d1f895c6fe	1439	*/
mbed_official	630:825f75ca301e	1440	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
mbed_official	340:28d1f895c6fe	1441	do{ \
mbed_official	340:28d1f895c6fe	1442	(__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \
mbed_official	340:28d1f895c6fe	1443	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
mbed_official	340:28d1f895c6fe	1444	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
mbed_official	340:28d1f895c6fe	1445	} while(0)
mbed_official	630:825f75ca301e	1446
mbed_official	340:28d1f895c6fe	1447	/**
mbed_official	340:28d1f895c6fe	1448	* @brief Gets the TIM Clock Division value on runtime
mbed_official	630:825f75ca301e	1449	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1450	* @retval None
mbed_official	340:28d1f895c6fe	1451	*/
mbed_official	630:825f75ca301e	1452	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1453	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
mbed_official	630:825f75ca301e	1454
mbed_official	340:28d1f895c6fe	1455	/**
mbed_official	340:28d1f895c6fe	1456	* @brief Sets the TIM Input Capture prescaler on runtime without calling
mbed_official	340:28d1f895c6fe	1457	* another time HAL_TIM_IC_ConfigChannel() function.
mbed_official	340:28d1f895c6fe	1458	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1459	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	340:28d1f895c6fe	1460	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1461	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1462	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1463	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1464	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1465	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
mbed_official	340:28d1f895c6fe	1466	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1467	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	340:28d1f895c6fe	1468	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	340:28d1f895c6fe	1469	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	340:28d1f895c6fe	1470	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	340:28d1f895c6fe	1471	* @retval None
mbed_official	340:28d1f895c6fe	1472	*/
mbed_official	630:825f75ca301e	1473	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	340:28d1f895c6fe	1474	do{ \
mbed_official	630:825f75ca301e	1475	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
mbed_official	630:825f75ca301e	1476	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
mbed_official	630:825f75ca301e	1477	} while(0)
mbed_official	340:28d1f895c6fe	1478
mbed_official	340:28d1f895c6fe	1479	/**
mbed_official	340:28d1f895c6fe	1480	* @brief Gets the TIM Input Capture prescaler on runtime
mbed_official	340:28d1f895c6fe	1481	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1482	* @param __CHANNEL__: TIM Channels to be configured.
mbed_official	340:28d1f895c6fe	1483	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1484	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
mbed_official	340:28d1f895c6fe	1485	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
mbed_official	340:28d1f895c6fe	1486	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
mbed_official	340:28d1f895c6fe	1487	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
mbed_official	340:28d1f895c6fe	1488	* @retval None
mbed_official	340:28d1f895c6fe	1489	*/
mbed_official	630:825f75ca301e	1490	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
mbed_official	340:28d1f895c6fe	1491	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
mbed_official	340:28d1f895c6fe	1492	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
mbed_official	340:28d1f895c6fe	1493	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
mbed_official	340:28d1f895c6fe	1494	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
mbed_official	630:825f75ca301e	1495
mbed_official	340:28d1f895c6fe	1496	/**
mbed_official	340:28d1f895c6fe	1497	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
mbed_official	340:28d1f895c6fe	1498	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1499	* @note When the USR bit of the TIMx_CR1 register is set, only counter
mbed_official	340:28d1f895c6fe	1500	* overflow/underflow generates an update interrupt or DMA request (if
mbed_official	340:28d1f895c6fe	1501	* enabled)
mbed_official	340:28d1f895c6fe	1502	* @retval None
mbed_official	340:28d1f895c6fe	1503	*/
mbed_official	340:28d1f895c6fe	1504	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1505	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
mbed_official	340:28d1f895c6fe	1506
mbed_official	340:28d1f895c6fe	1507	/**
mbed_official	340:28d1f895c6fe	1508	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
mbed_official	340:28d1f895c6fe	1509	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1510	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
mbed_official	340:28d1f895c6fe	1511	* following events generate an update interrupt or DMA request (if
mbed_official	340:28d1f895c6fe	1512	* enabled):
mbed_official	340:28d1f895c6fe	1513	* (+) Counter overflow/underflow
mbed_official	340:28d1f895c6fe	1514	* (+) Setting the UG bit
mbed_official	340:28d1f895c6fe	1515	* (+) Update generation through the slave mode controller
mbed_official	340:28d1f895c6fe	1516	* @retval None
mbed_official	340:28d1f895c6fe	1517	*/
mbed_official	340:28d1f895c6fe	1518	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1519	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
mbed_official	340:28d1f895c6fe	1520
mbed_official	340:28d1f895c6fe	1521	/**
mbed_official	630:825f75ca301e	1522	* @brief Sets the TIM Capture x input polarity on runtime.
mbed_official	630:825f75ca301e	1523	* @param __HANDLE__: TIM handle.
mbed_official	630:825f75ca301e	1524	* @param __CHANNEL__: TIM Channels to be configured.
mbed_official	630:825f75ca301e	1525	* This parameter can be one of the following values:
mbed_official	630:825f75ca301e	1526	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	630:825f75ca301e	1527	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	630:825f75ca301e	1528	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	630:825f75ca301e	1529	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	630:825f75ca301e	1530	* @param __POLARITY__: Polarity for TIx source
mbed_official	630:825f75ca301e	1531	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
mbed_official	630:825f75ca301e	1532	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
mbed_official	630:825f75ca301e	1533	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
mbed_official	630:825f75ca301e	1534	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
mbed_official	630:825f75ca301e	1535	* @retval None
mbed_official	630:825f75ca301e	1536	*/
mbed_official	630:825f75ca301e	1537	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
mbed_official	630:825f75ca301e	1538	do{ \
mbed_official	630:825f75ca301e	1539	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
mbed_official	630:825f75ca301e	1540	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
mbed_official	630:825f75ca301e	1541	}while(0)
mbed_official	630:825f75ca301e	1542
mbed_official	630:825f75ca301e	1543	/**
mbed_official	340:28d1f895c6fe	1544	* @}
mbed_official	340:28d1f895c6fe	1545	*/
mbed_official	340:28d1f895c6fe	1546
mbed_official	340:28d1f895c6fe	1547	/* Include TIM HAL Extension module */
mbed_official	340:28d1f895c6fe	1548	#include "stm32f0xx_hal_tim_ex.h"
mbed_official	340:28d1f895c6fe	1549
mbed_official	340:28d1f895c6fe	1550	/* Exported functions --------------------------------------------------------*/
mbed_official	630:825f75ca301e	1551	/** @addtogroup TIM_Exported_Functions
mbed_official	340:28d1f895c6fe	1552	* @{
mbed_official	340:28d1f895c6fe	1553	*/
mbed_official	340:28d1f895c6fe	1554
mbed_official	630:825f75ca301e	1555	/** @addtogroup TIM_Exported_Functions_Group1
mbed_official	340:28d1f895c6fe	1556	* @{
mbed_official	340:28d1f895c6fe	1557	*/
mbed_official	340:28d1f895c6fe	1558	/* Time Base functions ********************************************************/
mbed_official	340:28d1f895c6fe	1559	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1560	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1561	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1562	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1563	/* Blocking mode: Polling */
mbed_official	340:28d1f895c6fe	1564	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1565	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1566	/* Non-Blocking mode: Interrupt */
mbed_official	340:28d1f895c6fe	1567	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1568	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1569	/* Non-Blocking mode: DMA */
mbed_official	340:28d1f895c6fe	1570	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
mbed_official	340:28d1f895c6fe	1571	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1572	/**
mbed_official	340:28d1f895c6fe	1573	* @}
mbed_official	340:28d1f895c6fe	1574	*/
mbed_official	340:28d1f895c6fe	1575
mbed_official	630:825f75ca301e	1576	/** @addtogroup TIM_Exported_Functions_Group2
mbed_official	340:28d1f895c6fe	1577	* @{
mbed_official	340:28d1f895c6fe	1578	*/
mbed_official	340:28d1f895c6fe	1579	/* Timer Output Compare functions **********************************************/
mbed_official	340:28d1f895c6fe	1580	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1581	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1582	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1583	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1584	/* Blocking mode: Polling */
mbed_official	340:28d1f895c6fe	1585	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1586	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1587	/* Non-Blocking mode: Interrupt */
mbed_official	340:28d1f895c6fe	1588	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1589	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1590	/* Non-Blocking mode: DMA */
mbed_official	340:28d1f895c6fe	1591	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	340:28d1f895c6fe	1592	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	630:825f75ca301e	1593
mbed_official	340:28d1f895c6fe	1594	/**
mbed_official	340:28d1f895c6fe	1595	* @}
mbed_official	340:28d1f895c6fe	1596	*/
mbed_official	340:28d1f895c6fe	1597
mbed_official	630:825f75ca301e	1598	/** @addtogroup TIM_Exported_Functions_Group3
mbed_official	340:28d1f895c6fe	1599	* @{
mbed_official	340:28d1f895c6fe	1600	*/
mbed_official	340:28d1f895c6fe	1601	/* Timer PWM functions *********************************************************/
mbed_official	340:28d1f895c6fe	1602	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1603	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1604	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1605	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1606	/* Blocking mode: Polling */
mbed_official	340:28d1f895c6fe	1607	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1608	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1609	/* Non-Blocking mode: Interrupt */
mbed_official	340:28d1f895c6fe	1610	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1611	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1612	/* Non-Blocking mode: DMA */
mbed_official	340:28d1f895c6fe	1613	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	340:28d1f895c6fe	1614	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1615	/**
mbed_official	340:28d1f895c6fe	1616	* @}
mbed_official	340:28d1f895c6fe	1617	*/
mbed_official	340:28d1f895c6fe	1618
mbed_official	630:825f75ca301e	1619	/** @addtogroup TIM_Exported_Functions_Group4
mbed_official	340:28d1f895c6fe	1620	* @{
mbed_official	340:28d1f895c6fe	1621	*/
mbed_official	340:28d1f895c6fe	1622	/* Timer Input Capture functions ***********************************************/
mbed_official	340:28d1f895c6fe	1623	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1624	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1625	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1626	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1627	/* Blocking mode: Polling */
mbed_official	340:28d1f895c6fe	1628	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1629	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1630	/* Non-Blocking mode: Interrupt */
mbed_official	340:28d1f895c6fe	1631	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1632	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1633	/* Non-Blocking mode: DMA */
mbed_official	340:28d1f895c6fe	1634	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	340:28d1f895c6fe	1635	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1636	/**
mbed_official	340:28d1f895c6fe	1637	* @}
mbed_official	340:28d1f895c6fe	1638	*/
mbed_official	340:28d1f895c6fe	1639
mbed_official	630:825f75ca301e	1640	/** @addtogroup TIM_Exported_Functions_Group5
mbed_official	340:28d1f895c6fe	1641	* @{
mbed_official	340:28d1f895c6fe	1642	*/
mbed_official	340:28d1f895c6fe	1643	/* Timer One Pulse functions ***************************************************/
mbed_official	340:28d1f895c6fe	1644	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
mbed_official	340:28d1f895c6fe	1645	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1646	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1647	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1648	/* Blocking mode: Polling */
mbed_official	340:28d1f895c6fe	1649	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	340:28d1f895c6fe	1650	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	340:28d1f895c6fe	1651	/* Non-Blocking mode: Interrupt */
mbed_official	340:28d1f895c6fe	1652	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	340:28d1f895c6fe	1653	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	340:28d1f895c6fe	1654	/**
mbed_official	340:28d1f895c6fe	1655	* @}
mbed_official	340:28d1f895c6fe	1656	*/
mbed_official	340:28d1f895c6fe	1657
mbed_official	630:825f75ca301e	1658	/** @addtogroup TIM_Exported_Functions_Group6
mbed_official	340:28d1f895c6fe	1659	* @{
mbed_official	340:28d1f895c6fe	1660	*/
mbed_official	340:28d1f895c6fe	1661	/* Timer Encoder functions *****************************************************/
mbed_official	340:28d1f895c6fe	1662	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
mbed_official	340:28d1f895c6fe	1663	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1664	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1665	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1666	/* Blocking mode: Polling */
mbed_official	340:28d1f895c6fe	1667	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1668	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1669	/* Non-Blocking mode: Interrupt */
mbed_official	340:28d1f895c6fe	1670	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1671	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1672	/* Non-Blocking mode: DMA */
mbed_official	340:28d1f895c6fe	1673	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
mbed_official	340:28d1f895c6fe	1674	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	630:825f75ca301e	1675
mbed_official	340:28d1f895c6fe	1676	/**
mbed_official	340:28d1f895c6fe	1677	* @}
mbed_official	340:28d1f895c6fe	1678	*/
mbed_official	340:28d1f895c6fe	1679
mbed_official	630:825f75ca301e	1680	/** @addtogroup TIM_Exported_Functions_Group7
mbed_official	340:28d1f895c6fe	1681	* @{
mbed_official	340:28d1f895c6fe	1682	*/
mbed_official	340:28d1f895c6fe	1683	/* Interrupt Handler functions **********************************************/
mbed_official	340:28d1f895c6fe	1684	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1685	/**
mbed_official	340:28d1f895c6fe	1686	* @}
mbed_official	340:28d1f895c6fe	1687	*/
mbed_official	340:28d1f895c6fe	1688
mbed_official	630:825f75ca301e	1689	/** @addtogroup TIM_Exported_Functions_Group8
mbed_official	340:28d1f895c6fe	1690	* @{
mbed_official	340:28d1f895c6fe	1691	*/
mbed_official	340:28d1f895c6fe	1692	/* Control functions *********************************************************/
mbed_official	340:28d1f895c6fe	1693	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1694	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1695	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1696	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
mbed_official	340:28d1f895c6fe	1697	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1698	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
mbed_official	340:28d1f895c6fe	1699	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
mbed_official	340:28d1f895c6fe	1700	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	340:28d1f895c6fe	1701	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	340:28d1f895c6fe	1702	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	340:28d1f895c6fe	1703	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	340:28d1f895c6fe	1704	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	340:28d1f895c6fe	1705	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	340:28d1f895c6fe	1706	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	340:28d1f895c6fe	1707	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	340:28d1f895c6fe	1708	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
mbed_official	340:28d1f895c6fe	1709	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	630:825f75ca301e	1710
mbed_official	340:28d1f895c6fe	1711	/**
mbed_official	340:28d1f895c6fe	1712	* @}
mbed_official	340:28d1f895c6fe	1713	*/
mbed_official	340:28d1f895c6fe	1714
mbed_official	340:28d1f895c6fe	1715	/** @addtogroup TIM_Exported_Functions_Group9
mbed_official	340:28d1f895c6fe	1716	* @{
mbed_official	340:28d1f895c6fe	1717	*/
mbed_official	340:28d1f895c6fe	1718	/* Callback in non blocking modes (Interrupt and DMA) *************************/
mbed_official	340:28d1f895c6fe	1719	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1720	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1721	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1722	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1723	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1724	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1725	/**
mbed_official	340:28d1f895c6fe	1726	* @}
mbed_official	340:28d1f895c6fe	1727	*/
mbed_official	340:28d1f895c6fe	1728
mbed_official	340:28d1f895c6fe	1729	/** @addtogroup TIM_Exported_Functions_Group10
mbed_official	340:28d1f895c6fe	1730	* @{
mbed_official	340:28d1f895c6fe	1731	*/
mbed_official	340:28d1f895c6fe	1732	/* Peripheral State functions **************************************************/
mbed_official	340:28d1f895c6fe	1733	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1734	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1735	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1736	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1737	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1738	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
mbed_official	630:825f75ca301e	1739
mbed_official	340:28d1f895c6fe	1740	/**
mbed_official	340:28d1f895c6fe	1741	* @}
mbed_official	340:28d1f895c6fe	1742	*/
mbed_official	340:28d1f895c6fe	1743
mbed_official	340:28d1f895c6fe	1744	/**
mbed_official	340:28d1f895c6fe	1745	* @}
mbed_official	340:28d1f895c6fe	1746	*/
mbed_official	340:28d1f895c6fe	1747
mbed_official	340:28d1f895c6fe	1748	/**
mbed_official	340:28d1f895c6fe	1749	* @}
mbed_official	340:28d1f895c6fe	1750	*/
mbed_official	340:28d1f895c6fe	1751
mbed_official	340:28d1f895c6fe	1752	/**
mbed_official	340:28d1f895c6fe	1753	* @}
mbed_official	340:28d1f895c6fe	1754	*/
mbed_official	340:28d1f895c6fe	1755
mbed_official	340:28d1f895c6fe	1756	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	1757	}
mbed_official	340:28d1f895c6fe	1758	#endif
mbed_official	340:28d1f895c6fe	1759
mbed_official	340:28d1f895c6fe	1760	#endif /* __STM32F0xx_HAL_TIM_H */
mbed_official	340:28d1f895c6fe	1761
mbed_official	340:28d1f895c6fe	1762	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/