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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.c@630:825f75ca301e, 2015-09-28 (annotated)

Committer:
mbed_official
Date:
Mon Sep 28 10:45:10 2015 +0100
Revision:
630:825f75ca301e
Parent:
441:d2c15dda23c1 
Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10



Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/



NUCLEO_F031K6 : Add new target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 340:28d1f895c6fe 1 /**
mbed_official 340:28d1f895c6fe 2 ******************************************************************************
mbed_official 340:28d1f895c6fe 3 * @file stm32f0xx_hal_dma.c
mbed_official 340:28d1f895c6fe 4 * @author MCD Application Team
mbed_official 630:825f75ca301e 5 * @version V1.3.0
mbed_official 630:825f75ca301e 6 * @date 26-June-2015
mbed_official 340:28d1f895c6fe 7 * @brief DMA HAL module driver.
mbed_official 340:28d1f895c6fe 8 *
mbed_official 340:28d1f895c6fe 9 * This file provides firmware functions to manage the following
mbed_official 340:28d1f895c6fe 10 * functionalities of the Direct Memory Access (DMA) peripheral:
mbed_official 340:28d1f895c6fe 11 * + Initialization and de-initialization functions
mbed_official 340:28d1f895c6fe 12 * + IO operation functions
mbed_official 340:28d1f895c6fe 13 * + Peripheral State and errors functions
mbed_official 340:28d1f895c6fe 14 @verbatim
mbed_official 340:28d1f895c6fe 15 ==============================================================================
mbed_official 340:28d1f895c6fe 16 ##### How to use this driver #####
mbed_official 340:28d1f895c6fe 17 ==============================================================================
mbed_official 340:28d1f895c6fe 18 [..]
mbed_official 340:28d1f895c6fe 19 (#) Enable and configure the peripheral to be connected to the DMA Channel
mbed_official 340:28d1f895c6fe 20 (except for internal SRAM / FLASH memories: no initialization is
mbed_official 340:28d1f895c6fe 21 necessary) please refer to Reference manual for connection between peripherals
mbed_official 340:28d1f895c6fe 22 and DMA requests .
mbed_official 340:28d1f895c6fe 23
mbed_official 340:28d1f895c6fe 24 (#) For a given Channel, program the required configuration through the following parameters:
mbed_official 340:28d1f895c6fe 25 Transfer Direction, Source and Destination data formats,
mbed_official 340:28d1f895c6fe 26 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
mbed_official 340:28d1f895c6fe 27 using HAL_DMA_Init() function.
mbed_official 340:28d1f895c6fe 28
mbed_official 340:28d1f895c6fe 29 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
mbed_official 340:28d1f895c6fe 30 detection.
mbed_official 340:28d1f895c6fe 31
mbed_official 340:28d1f895c6fe 32 (#) Use HAL_DMA_Abort() function to abort the current transfer
mbed_official 340:28d1f895c6fe 33
mbed_official 340:28d1f895c6fe 34 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
mbed_official 340:28d1f895c6fe 35 *** Polling mode IO operation ***
mbed_official 340:28d1f895c6fe 36 =================================
mbed_official 340:28d1f895c6fe 37 [..]
mbed_official 340:28d1f895c6fe 38 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
mbed_official 340:28d1f895c6fe 39 address and destination address and the Length of data to be transferred
mbed_official 340:28d1f895c6fe 40 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
mbed_official 340:28d1f895c6fe 41 case a fixed Timeout can be configured by User depending from his application.
mbed_official 340:28d1f895c6fe 42
mbed_official 340:28d1f895c6fe 43 *** Interrupt mode IO operation ***
mbed_official 340:28d1f895c6fe 44 ===================================
mbed_official 340:28d1f895c6fe 45 [..]
mbed_official 340:28d1f895c6fe 46 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
mbed_official 340:28d1f895c6fe 47 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
mbed_official 340:28d1f895c6fe 48 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
mbed_official 340:28d1f895c6fe 49 Source address and destination address and the Length of data to be transferred.
mbed_official 340:28d1f895c6fe 50 In this case the DMA interrupt is configured
mbed_official 340:28d1f895c6fe 51 (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
mbed_official 340:28d1f895c6fe 52 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
mbed_official 340:28d1f895c6fe 53 add his own function by customization of function pointer XferCpltCallback and
mbed_official 340:28d1f895c6fe 54 XferErrorCallback (i.e a member of DMA handle structure).
mbed_official 340:28d1f895c6fe 55
mbed_official 340:28d1f895c6fe 56 *** DMA HAL driver macros list ***
mbed_official 340:28d1f895c6fe 57 =============================================
mbed_official 340:28d1f895c6fe 58 [..]
mbed_official 340:28d1f895c6fe 59 Below the list of most used macros in DMA HAL driver.
mbed_official 340:28d1f895c6fe 60
mbed_official 340:28d1f895c6fe 61 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
mbed_official 340:28d1f895c6fe 62 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
mbed_official 340:28d1f895c6fe 63 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
mbed_official 340:28d1f895c6fe 64 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
mbed_official 340:28d1f895c6fe 65 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
mbed_official 340:28d1f895c6fe 66 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
mbed_official 340:28d1f895c6fe 67 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
mbed_official 340:28d1f895c6fe 68
mbed_official 340:28d1f895c6fe 69 [..]
mbed_official 340:28d1f895c6fe 70 (@) You can refer to the DMA HAL driver header file for more useful macros
mbed_official 340:28d1f895c6fe 71
mbed_official 340:28d1f895c6fe 72 @endverbatim
mbed_official 340:28d1f895c6fe 73 ******************************************************************************
mbed_official 340:28d1f895c6fe 74 * @attention
mbed_official 340:28d1f895c6fe 75 *
mbed_official 630:825f75ca301e 76 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 340:28d1f895c6fe 77 *
mbed_official 340:28d1f895c6fe 78 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 340:28d1f895c6fe 79 * are permitted provided that the following conditions are met:
mbed_official 340:28d1f895c6fe 80 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 340:28d1f895c6fe 81 * this list of conditions and the following disclaimer.
mbed_official 340:28d1f895c6fe 82 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 340:28d1f895c6fe 83 * this list of conditions and the following disclaimer in the documentation
mbed_official 340:28d1f895c6fe 84 * and/or other materials provided with the distribution.
mbed_official 340:28d1f895c6fe 85 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 340:28d1f895c6fe 86 * may be used to endorse or promote products derived from this software
mbed_official 340:28d1f895c6fe 87 * without specific prior written permission.
mbed_official 340:28d1f895c6fe 88 *
mbed_official 340:28d1f895c6fe 89 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 340:28d1f895c6fe 90 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 340:28d1f895c6fe 91 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 340:28d1f895c6fe 92 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 340:28d1f895c6fe 93 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 340:28d1f895c6fe 94 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 340:28d1f895c6fe 95 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 340:28d1f895c6fe 96 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 340:28d1f895c6fe 97 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 340:28d1f895c6fe 98 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 340:28d1f895c6fe 99 *
mbed_official 340:28d1f895c6fe 100 ******************************************************************************
mbed_official 340:28d1f895c6fe 101 */
mbed_official 340:28d1f895c6fe 102
mbed_official 340:28d1f895c6fe 103 /* Includes ------------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 104 #include "stm32f0xx_hal.h"
mbed_official 340:28d1f895c6fe 105
mbed_official 340:28d1f895c6fe 106 /** @addtogroup STM32F0xx_HAL_Driver
mbed_official 340:28d1f895c6fe 107 * @{
mbed_official 340:28d1f895c6fe 108 */
mbed_official 340:28d1f895c6fe 109
mbed_official 630:825f75ca301e 110 #ifdef HAL_DMA_MODULE_ENABLED
mbed_official 630:825f75ca301e 111
mbed_official 340:28d1f895c6fe 112 /** @defgroup DMA DMA
mbed_official 340:28d1f895c6fe 113 * @brief DMA HAL module driver
mbed_official 340:28d1f895c6fe 114 * @{
mbed_official 340:28d1f895c6fe 115 */
mbed_official 340:28d1f895c6fe 116
mbed_official 340:28d1f895c6fe 117
mbed_official 340:28d1f895c6fe 118 /* Private typedef -----------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 119 /* Private define ------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 120 /** @defgroup DMA_Private_Constants DMA Private Constants
mbed_official 340:28d1f895c6fe 121 * @{
mbed_official 340:28d1f895c6fe 122 */
mbed_official 340:28d1f895c6fe 123 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
mbed_official 340:28d1f895c6fe 124 /**
mbed_official 340:28d1f895c6fe 125 * @}
mbed_official 340:28d1f895c6fe 126 */
mbed_official 340:28d1f895c6fe 127
mbed_official 340:28d1f895c6fe 128 /* Private macro -------------------------------------------------------------*/
mbed_official 630:825f75ca301e 129 /* Private macros ------------------------------------------------------------*/
mbed_official 630:825f75ca301e 130 /** @defgroup DMA_Private_Macros DMA Private Macros
mbed_official 630:825f75ca301e 131 * @{
mbed_official 630:825f75ca301e 132 */
mbed_official 630:825f75ca301e 133 /**
mbed_official 630:825f75ca301e 134 * @}
mbed_official 630:825f75ca301e 135 */
mbed_official 340:28d1f895c6fe 136 /* Private variables ---------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 137 /* Private function prototypes -----------------------------------------------*/
mbed_official 340:28d1f895c6fe 138 /** @defgroup DMA_Private_Functions DMA Private Functions
mbed_official 340:28d1f895c6fe 139 * @{
mbed_official 340:28d1f895c6fe 140 */
mbed_official 340:28d1f895c6fe 141 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
mbed_official 340:28d1f895c6fe 142 /**
mbed_official 340:28d1f895c6fe 143 * @}
mbed_official 340:28d1f895c6fe 144 */
mbed_official 340:28d1f895c6fe 145
mbed_official 340:28d1f895c6fe 146 /* Exported functions ---------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 147
mbed_official 340:28d1f895c6fe 148 /** @defgroup DMA_Exported_Functions DMA Exported Functions
mbed_official 340:28d1f895c6fe 149 * @{
mbed_official 340:28d1f895c6fe 150 */
mbed_official 340:28d1f895c6fe 151
mbed_official 630:825f75ca301e 152 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official 340:28d1f895c6fe 153 * @brief Initialization and de-initialization functions
mbed_official 340:28d1f895c6fe 154 *
mbed_official 340:28d1f895c6fe 155 @verbatim
mbed_official 340:28d1f895c6fe 156 ===============================================================================
mbed_official 340:28d1f895c6fe 157 ##### Initialization and de-initialization functions #####
mbed_official 340:28d1f895c6fe 158 ===============================================================================
mbed_official 340:28d1f895c6fe 159 [..]
mbed_official 340:28d1f895c6fe 160 This section provides functions allowing to initialize the DMA Channel source
mbed_official 340:28d1f895c6fe 161 and destination addresses, incrementation and data sizes, transfer direction,
mbed_official 340:28d1f895c6fe 162 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
mbed_official 340:28d1f895c6fe 163 [..]
mbed_official 340:28d1f895c6fe 164 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
mbed_official 340:28d1f895c6fe 165 reference manual.
mbed_official 340:28d1f895c6fe 166
mbed_official 340:28d1f895c6fe 167 @endverbatim
mbed_official 340:28d1f895c6fe 168 * @{
mbed_official 340:28d1f895c6fe 169 */
mbed_official 340:28d1f895c6fe 170
mbed_official 340:28d1f895c6fe 171 /**
mbed_official 340:28d1f895c6fe 172 * @brief Initializes the DMA according to the specified
mbed_official 340:28d1f895c6fe 173 * parameters in the DMA_InitTypeDef and create the associated handle.
mbed_official 340:28d1f895c6fe 174 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 175 * the configuration information for the specified DMA Channel.
mbed_official 340:28d1f895c6fe 176 * @retval HAL status
mbed_official 340:28d1f895c6fe 177 */
mbed_official 340:28d1f895c6fe 178 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
mbed_official 340:28d1f895c6fe 179 {
mbed_official 340:28d1f895c6fe 180 uint32_t tmp = 0;
mbed_official 340:28d1f895c6fe 181
mbed_official 340:28d1f895c6fe 182 /* Check the DMA handle allocation */
mbed_official 441:d2c15dda23c1 183 if(hdma == NULL)
mbed_official 340:28d1f895c6fe 184 {
mbed_official 340:28d1f895c6fe 185 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 186 }
mbed_official 340:28d1f895c6fe 187
mbed_official 340:28d1f895c6fe 188 /* Check the parameters */
mbed_official 340:28d1f895c6fe 189 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
mbed_official 340:28d1f895c6fe 190 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
mbed_official 340:28d1f895c6fe 191 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
mbed_official 340:28d1f895c6fe 192 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
mbed_official 340:28d1f895c6fe 193 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
mbed_official 340:28d1f895c6fe 194 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
mbed_official 340:28d1f895c6fe 195 assert_param(IS_DMA_MODE(hdma->Init.Mode));
mbed_official 340:28d1f895c6fe 196 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
mbed_official 630:825f75ca301e 197
mbed_official 630:825f75ca301e 198 if(hdma->State == HAL_DMA_STATE_RESET)
mbed_official 630:825f75ca301e 199 {
mbed_official 630:825f75ca301e 200 /* Allocate lock resource and initialize it */
mbed_official 630:825f75ca301e 201 hdma->Lock = HAL_UNLOCKED;
mbed_official 630:825f75ca301e 202 }
mbed_official 340:28d1f895c6fe 203
mbed_official 340:28d1f895c6fe 204 /* Change DMA peripheral state */
mbed_official 340:28d1f895c6fe 205 hdma->State = HAL_DMA_STATE_BUSY;
mbed_official 340:28d1f895c6fe 206
mbed_official 340:28d1f895c6fe 207 /* Get the CR register value */
mbed_official 340:28d1f895c6fe 208 tmp = hdma->Instance->CCR;
mbed_official 340:28d1f895c6fe 209
mbed_official 340:28d1f895c6fe 210 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
mbed_official 340:28d1f895c6fe 211 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
mbed_official 340:28d1f895c6fe 212 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
mbed_official 340:28d1f895c6fe 213 DMA_CCR_DIR));
mbed_official 340:28d1f895c6fe 214
mbed_official 340:28d1f895c6fe 215 /* Prepare the DMA Channel configuration */
mbed_official 340:28d1f895c6fe 216 tmp |= hdma->Init.Direction |
mbed_official 340:28d1f895c6fe 217 hdma->Init.PeriphInc | hdma->Init.MemInc |
mbed_official 340:28d1f895c6fe 218 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
mbed_official 340:28d1f895c6fe 219 hdma->Init.Mode | hdma->Init.Priority;
mbed_official 340:28d1f895c6fe 220
mbed_official 340:28d1f895c6fe 221 /* Write to DMA Channel CR register */
mbed_official 340:28d1f895c6fe 222 hdma->Instance->CCR = tmp;
mbed_official 340:28d1f895c6fe 223
mbed_official 340:28d1f895c6fe 224 /* Initialise the error code */
mbed_official 340:28d1f895c6fe 225 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
mbed_official 340:28d1f895c6fe 226
mbed_official 340:28d1f895c6fe 227 /* Initialize the DMA state*/
mbed_official 340:28d1f895c6fe 228 hdma->State = HAL_DMA_STATE_READY;
mbed_official 340:28d1f895c6fe 229
mbed_official 340:28d1f895c6fe 230 return HAL_OK;
mbed_official 340:28d1f895c6fe 231 }
mbed_official 340:28d1f895c6fe 232
mbed_official 340:28d1f895c6fe 233 /**
mbed_official 340:28d1f895c6fe 234 * @brief DeInitializes the DMA peripheral
mbed_official 340:28d1f895c6fe 235 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 236 * the configuration information for the specified DMA Channel.
mbed_official 340:28d1f895c6fe 237 * @retval HAL status
mbed_official 340:28d1f895c6fe 238 */
mbed_official 340:28d1f895c6fe 239 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
mbed_official 340:28d1f895c6fe 240 {
mbed_official 340:28d1f895c6fe 241 /* Check the DMA handle allocation */
mbed_official 441:d2c15dda23c1 242 if(hdma == NULL)
mbed_official 340:28d1f895c6fe 243 {
mbed_official 340:28d1f895c6fe 244 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 245 }
mbed_official 340:28d1f895c6fe 246
mbed_official 340:28d1f895c6fe 247 /* Check the parameters */
mbed_official 340:28d1f895c6fe 248 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
mbed_official 340:28d1f895c6fe 249
mbed_official 340:28d1f895c6fe 250 /* Check the DMA peripheral state */
mbed_official 340:28d1f895c6fe 251 if(hdma->State == HAL_DMA_STATE_BUSY)
mbed_official 340:28d1f895c6fe 252 {
mbed_official 340:28d1f895c6fe 253 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 254 }
mbed_official 340:28d1f895c6fe 255
mbed_official 340:28d1f895c6fe 256 /* Disable the selected DMA Channelx */
mbed_official 340:28d1f895c6fe 257 __HAL_DMA_DISABLE(hdma);
mbed_official 340:28d1f895c6fe 258
mbed_official 340:28d1f895c6fe 259 /* Reset DMA Channel control register */
mbed_official 340:28d1f895c6fe 260 hdma->Instance->CCR = 0;
mbed_official 340:28d1f895c6fe 261
mbed_official 340:28d1f895c6fe 262 /* Reset DMA Channel Number of Data to Transfer register */
mbed_official 340:28d1f895c6fe 263 hdma->Instance->CNDTR = 0;
mbed_official 340:28d1f895c6fe 264
mbed_official 340:28d1f895c6fe 265 /* Reset DMA Channel peripheral address register */
mbed_official 340:28d1f895c6fe 266 hdma->Instance->CPAR = 0;
mbed_official 340:28d1f895c6fe 267
mbed_official 340:28d1f895c6fe 268 /* Reset DMA Channel memory address register */
mbed_official 340:28d1f895c6fe 269 hdma->Instance->CMAR = 0;
mbed_official 340:28d1f895c6fe 270
mbed_official 340:28d1f895c6fe 271 /* Clear all flags */
mbed_official 340:28d1f895c6fe 272 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
mbed_official 340:28d1f895c6fe 273 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
mbed_official 340:28d1f895c6fe 274 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
mbed_official 340:28d1f895c6fe 275
mbed_official 630:825f75ca301e 276 /* Initialize the error code */
mbed_official 340:28d1f895c6fe 277 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
mbed_official 340:28d1f895c6fe 278
mbed_official 340:28d1f895c6fe 279 /* Initialize the DMA state */
mbed_official 340:28d1f895c6fe 280 hdma->State = HAL_DMA_STATE_RESET;
mbed_official 340:28d1f895c6fe 281
mbed_official 340:28d1f895c6fe 282 /* Release Lock */
mbed_official 340:28d1f895c6fe 283 __HAL_UNLOCK(hdma);
mbed_official 340:28d1f895c6fe 284
mbed_official 340:28d1f895c6fe 285 return HAL_OK;
mbed_official 340:28d1f895c6fe 286 }
mbed_official 340:28d1f895c6fe 287
mbed_official 340:28d1f895c6fe 288 /**
mbed_official 340:28d1f895c6fe 289 * @}
mbed_official 340:28d1f895c6fe 290 */
mbed_official 340:28d1f895c6fe 291
mbed_official 340:28d1f895c6fe 292 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
mbed_official 340:28d1f895c6fe 293 * @brief I/O operation functions
mbed_official 340:28d1f895c6fe 294 *
mbed_official 340:28d1f895c6fe 295 @verbatim
mbed_official 340:28d1f895c6fe 296 ===============================================================================
mbed_official 340:28d1f895c6fe 297 ##### IO operation functions #####
mbed_official 340:28d1f895c6fe 298 ===============================================================================
mbed_official 340:28d1f895c6fe 299 [..] This section provides functions allowing to:
mbed_official 340:28d1f895c6fe 300 (+) Configure the source, destination address and data length and Start DMA transfer
mbed_official 340:28d1f895c6fe 301 (+) Configure the source, destination address and data length and
mbed_official 340:28d1f895c6fe 302 Start DMA transfer with interrupt
mbed_official 340:28d1f895c6fe 303 (+) Abort DMA transfer
mbed_official 340:28d1f895c6fe 304 (+) Poll for transfer complete
mbed_official 340:28d1f895c6fe 305 (+) Handle DMA interrupt request
mbed_official 340:28d1f895c6fe 306
mbed_official 340:28d1f895c6fe 307 @endverbatim
mbed_official 340:28d1f895c6fe 308 * @{
mbed_official 340:28d1f895c6fe 309 */
mbed_official 340:28d1f895c6fe 310
mbed_official 340:28d1f895c6fe 311 /**
mbed_official 340:28d1f895c6fe 312 * @brief Starts the DMA Transfer.
mbed_official 340:28d1f895c6fe 313 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 314 * the configuration information for the specified DMA Channel.
mbed_official 340:28d1f895c6fe 315 * @param SrcAddress: The source memory Buffer address
mbed_official 340:28d1f895c6fe 316 * @param DstAddress: The destination memory Buffer address
mbed_official 340:28d1f895c6fe 317 * @param DataLength: The length of data to be transferred from source to destination
mbed_official 340:28d1f895c6fe 318 * @retval HAL status
mbed_official 340:28d1f895c6fe 319 */
mbed_official 340:28d1f895c6fe 320 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
mbed_official 340:28d1f895c6fe 321 {
mbed_official 340:28d1f895c6fe 322 /* Process locked */
mbed_official 340:28d1f895c6fe 323 __HAL_LOCK(hdma);
mbed_official 340:28d1f895c6fe 324
mbed_official 340:28d1f895c6fe 325 /* Change DMA peripheral state */
mbed_official 340:28d1f895c6fe 326 hdma->State = HAL_DMA_STATE_BUSY;
mbed_official 340:28d1f895c6fe 327
mbed_official 340:28d1f895c6fe 328 /* Check the parameters */
mbed_official 340:28d1f895c6fe 329 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
mbed_official 340:28d1f895c6fe 330
mbed_official 340:28d1f895c6fe 331 /* Disable the peripheral */
mbed_official 340:28d1f895c6fe 332 __HAL_DMA_DISABLE(hdma);
mbed_official 340:28d1f895c6fe 333
mbed_official 340:28d1f895c6fe 334 /* Configure the source, destination address and the data length */
mbed_official 340:28d1f895c6fe 335 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
mbed_official 340:28d1f895c6fe 336
mbed_official 340:28d1f895c6fe 337 /* Enable the Peripheral */
mbed_official 340:28d1f895c6fe 338 __HAL_DMA_ENABLE(hdma);
mbed_official 340:28d1f895c6fe 339
mbed_official 340:28d1f895c6fe 340 return HAL_OK;
mbed_official 340:28d1f895c6fe 341 }
mbed_official 340:28d1f895c6fe 342
mbed_official 340:28d1f895c6fe 343 /**
mbed_official 340:28d1f895c6fe 344 * @brief Start the DMA Transfer with interrupt enabled.
mbed_official 340:28d1f895c6fe 345 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 346 * the configuration information for the specified DMA Channel.
mbed_official 340:28d1f895c6fe 347 * @param SrcAddress: The source memory Buffer address
mbed_official 340:28d1f895c6fe 348 * @param DstAddress: The destination memory Buffer address
mbed_official 340:28d1f895c6fe 349 * @param DataLength: The length of data to be transferred from source to destination
mbed_official 340:28d1f895c6fe 350 * @retval HAL status
mbed_official 340:28d1f895c6fe 351 */
mbed_official 340:28d1f895c6fe 352 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
mbed_official 340:28d1f895c6fe 353 {
mbed_official 340:28d1f895c6fe 354 /* Process locked */
mbed_official 340:28d1f895c6fe 355 __HAL_LOCK(hdma);
mbed_official 340:28d1f895c6fe 356
mbed_official 340:28d1f895c6fe 357 /* Change DMA peripheral state */
mbed_official 340:28d1f895c6fe 358 hdma->State = HAL_DMA_STATE_BUSY;
mbed_official 340:28d1f895c6fe 359
mbed_official 340:28d1f895c6fe 360 /* Check the parameters */
mbed_official 340:28d1f895c6fe 361 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
mbed_official 340:28d1f895c6fe 362
mbed_official 340:28d1f895c6fe 363 /* Disable the peripheral */
mbed_official 340:28d1f895c6fe 364 __HAL_DMA_DISABLE(hdma);
mbed_official 340:28d1f895c6fe 365
mbed_official 340:28d1f895c6fe 366 /* Configure the source, destination address and the data length */
mbed_official 340:28d1f895c6fe 367 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
mbed_official 340:28d1f895c6fe 368
mbed_official 340:28d1f895c6fe 369 /* Enable the transfer complete interrupt */
mbed_official 340:28d1f895c6fe 370 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
mbed_official 340:28d1f895c6fe 371
mbed_official 340:28d1f895c6fe 372 /* Enable the Half transfer complete interrupt */
mbed_official 340:28d1f895c6fe 373 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
mbed_official 340:28d1f895c6fe 374
mbed_official 340:28d1f895c6fe 375 /* Enable the transfer Error interrupt */
mbed_official 340:28d1f895c6fe 376 __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
mbed_official 340:28d1f895c6fe 377
mbed_official 340:28d1f895c6fe 378 /* Enable the Peripheral */
mbed_official 340:28d1f895c6fe 379 __HAL_DMA_ENABLE(hdma);
mbed_official 340:28d1f895c6fe 380
mbed_official 340:28d1f895c6fe 381 return HAL_OK;
mbed_official 340:28d1f895c6fe 382 }
mbed_official 340:28d1f895c6fe 383
mbed_official 340:28d1f895c6fe 384 /**
mbed_official 340:28d1f895c6fe 385 * @brief Aborts the DMA Transfer.
mbed_official 340:28d1f895c6fe 386 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 387 * the configuration information for the specified DMA Channel.
mbed_official 340:28d1f895c6fe 388 *
mbed_official 340:28d1f895c6fe 389 * @note After disabling a DMA Channel, a check for wait until the DMA Channel is
mbed_official 340:28d1f895c6fe 390 * effectively disabled is added. If a Channel is disabled
mbed_official 340:28d1f895c6fe 391 * while a data transfer is ongoing, the current data will be transferred
mbed_official 340:28d1f895c6fe 392 * and the Channel will be effectively disabled only after the transfer of
mbed_official 340:28d1f895c6fe 393 * this single data is finished.
mbed_official 340:28d1f895c6fe 394 * @retval HAL status
mbed_official 340:28d1f895c6fe 395 */
mbed_official 340:28d1f895c6fe 396 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
mbed_official 340:28d1f895c6fe 397 {
mbed_official 340:28d1f895c6fe 398 uint32_t tickstart = 0x00;
mbed_official 340:28d1f895c6fe 399
mbed_official 340:28d1f895c6fe 400 /* Disable the channel */
mbed_official 340:28d1f895c6fe 401 __HAL_DMA_DISABLE(hdma);
mbed_official 340:28d1f895c6fe 402
mbed_official 630:825f75ca301e 403 /* Get tick */
mbed_official 340:28d1f895c6fe 404 tickstart = HAL_GetTick();
mbed_official 340:28d1f895c6fe 405
mbed_official 340:28d1f895c6fe 406 /* Check if the DMA Channel is effectively disabled */
mbed_official 340:28d1f895c6fe 407 while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
mbed_official 340:28d1f895c6fe 408 {
mbed_official 340:28d1f895c6fe 409 /* Check for the Timeout */
mbed_official 340:28d1f895c6fe 410 if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
mbed_official 340:28d1f895c6fe 411 {
mbed_official 340:28d1f895c6fe 412 /* Update error code */
mbed_official 340:28d1f895c6fe 413 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
mbed_official 340:28d1f895c6fe 414
mbed_official 340:28d1f895c6fe 415 /* Change the DMA state */
mbed_official 340:28d1f895c6fe 416 hdma->State = HAL_DMA_STATE_TIMEOUT;
mbed_official 340:28d1f895c6fe 417
mbed_official 340:28d1f895c6fe 418 /* Process Unlocked */
mbed_official 340:28d1f895c6fe 419 __HAL_UNLOCK(hdma);
mbed_official 340:28d1f895c6fe 420
mbed_official 340:28d1f895c6fe 421 return HAL_TIMEOUT;
mbed_official 340:28d1f895c6fe 422 }
mbed_official 340:28d1f895c6fe 423 }
mbed_official 340:28d1f895c6fe 424 /* Change the DMA state*/
mbed_official 340:28d1f895c6fe 425 hdma->State = HAL_DMA_STATE_READY;
mbed_official 340:28d1f895c6fe 426
mbed_official 340:28d1f895c6fe 427 /* Process Unlocked */
mbed_official 340:28d1f895c6fe 428 __HAL_UNLOCK(hdma);
mbed_official 340:28d1f895c6fe 429
mbed_official 340:28d1f895c6fe 430 return HAL_OK;
mbed_official 340:28d1f895c6fe 431 }
mbed_official 340:28d1f895c6fe 432
mbed_official 340:28d1f895c6fe 433 /**
mbed_official 340:28d1f895c6fe 434 * @brief Polling for transfer complete.
mbed_official 340:28d1f895c6fe 435 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 436 * the configuration information for the specified DMA Channel.
mbed_official 340:28d1f895c6fe 437 * @param CompleteLevel: Specifies the DMA level complete.
mbed_official 340:28d1f895c6fe 438 * @param Timeout: Timeout duration.
mbed_official 340:28d1f895c6fe 439 * @retval HAL status
mbed_official 340:28d1f895c6fe 440 */
mbed_official 340:28d1f895c6fe 441 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
mbed_official 340:28d1f895c6fe 442 {
mbed_official 340:28d1f895c6fe 443 uint32_t temp;
mbed_official 340:28d1f895c6fe 444 uint32_t tickstart = 0x00;
mbed_official 340:28d1f895c6fe 445
mbed_official 340:28d1f895c6fe 446 /* Get the level transfer complete flag */
mbed_official 340:28d1f895c6fe 447 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
mbed_official 340:28d1f895c6fe 448 {
mbed_official 340:28d1f895c6fe 449 /* Transfer Complete flag */
mbed_official 340:28d1f895c6fe 450 temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
mbed_official 340:28d1f895c6fe 451 }
mbed_official 340:28d1f895c6fe 452 else
mbed_official 340:28d1f895c6fe 453 {
mbed_official 340:28d1f895c6fe 454 /* Half Transfer Complete flag */
mbed_official 340:28d1f895c6fe 455 temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
mbed_official 340:28d1f895c6fe 456 }
mbed_official 340:28d1f895c6fe 457
mbed_official 630:825f75ca301e 458 /* Get tick */
mbed_official 340:28d1f895c6fe 459 tickstart = HAL_GetTick();
mbed_official 340:28d1f895c6fe 460
mbed_official 340:28d1f895c6fe 461 while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
mbed_official 340:28d1f895c6fe 462 {
mbed_official 340:28d1f895c6fe 463 if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
mbed_official 340:28d1f895c6fe 464 {
mbed_official 340:28d1f895c6fe 465 /* Clear the transfer error flags */
mbed_official 340:28d1f895c6fe 466 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
mbed_official 340:28d1f895c6fe 467
mbed_official 340:28d1f895c6fe 468 /* Update error code */
mbed_official 340:28d1f895c6fe 469 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
mbed_official 340:28d1f895c6fe 470
mbed_official 340:28d1f895c6fe 471 /* Change the DMA state */
mbed_official 340:28d1f895c6fe 472 hdma->State= HAL_DMA_STATE_ERROR;
mbed_official 340:28d1f895c6fe 473
mbed_official 340:28d1f895c6fe 474 /* Process Unlocked */
mbed_official 340:28d1f895c6fe 475 __HAL_UNLOCK(hdma);
mbed_official 340:28d1f895c6fe 476
mbed_official 340:28d1f895c6fe 477 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 478 }
mbed_official 340:28d1f895c6fe 479 /* Check for the Timeout */
mbed_official 340:28d1f895c6fe 480 if(Timeout != HAL_MAX_DELAY)
mbed_official 340:28d1f895c6fe 481 {
mbed_official 340:28d1f895c6fe 482 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
mbed_official 340:28d1f895c6fe 483 {
mbed_official 340:28d1f895c6fe 484 /* Update error code */
mbed_official 340:28d1f895c6fe 485 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
mbed_official 340:28d1f895c6fe 486
mbed_official 340:28d1f895c6fe 487 /* Change the DMA state */
mbed_official 340:28d1f895c6fe 488 hdma->State = HAL_DMA_STATE_TIMEOUT;
mbed_official 340:28d1f895c6fe 489
mbed_official 340:28d1f895c6fe 490 /* Process Unlocked */
mbed_official 340:28d1f895c6fe 491 __HAL_UNLOCK(hdma);
mbed_official 340:28d1f895c6fe 492
mbed_official 340:28d1f895c6fe 493 return HAL_TIMEOUT;
mbed_official 340:28d1f895c6fe 494 }
mbed_official 340:28d1f895c6fe 495 }
mbed_official 340:28d1f895c6fe 496 }
mbed_official 340:28d1f895c6fe 497
mbed_official 340:28d1f895c6fe 498 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
mbed_official 340:28d1f895c6fe 499 {
mbed_official 340:28d1f895c6fe 500 /* Clear the transfer complete flag */
mbed_official 340:28d1f895c6fe 501 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
mbed_official 340:28d1f895c6fe 502
mbed_official 340:28d1f895c6fe 503 /* The selected Channelx EN bit is cleared (DMA is disabled and
mbed_official 340:28d1f895c6fe 504 all transfers are complete) */
mbed_official 340:28d1f895c6fe 505 hdma->State = HAL_DMA_STATE_READY;
mbed_official 340:28d1f895c6fe 506
mbed_official 340:28d1f895c6fe 507 }
mbed_official 340:28d1f895c6fe 508 else
mbed_official 340:28d1f895c6fe 509 {
mbed_official 340:28d1f895c6fe 510 /* Clear the half transfer complete flag */
mbed_official 340:28d1f895c6fe 511 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
mbed_official 340:28d1f895c6fe 512
mbed_official 340:28d1f895c6fe 513 /* The selected Channelx EN bit is cleared (DMA is disabled and
mbed_official 340:28d1f895c6fe 514 all transfers of half buffer are complete) */
mbed_official 340:28d1f895c6fe 515 hdma->State = HAL_DMA_STATE_READY_HALF;
mbed_official 340:28d1f895c6fe 516 }
mbed_official 340:28d1f895c6fe 517
mbed_official 340:28d1f895c6fe 518 /* Process unlocked */
mbed_official 340:28d1f895c6fe 519 __HAL_UNLOCK(hdma);
mbed_official 340:28d1f895c6fe 520
mbed_official 340:28d1f895c6fe 521 return HAL_OK;
mbed_official 340:28d1f895c6fe 522 }
mbed_official 340:28d1f895c6fe 523
mbed_official 340:28d1f895c6fe 524 /**
mbed_official 340:28d1f895c6fe 525 * @brief Handles DMA interrupt request.
mbed_official 340:28d1f895c6fe 526 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 527 * the configuration information for the specified DMA Channel.
mbed_official 340:28d1f895c6fe 528 * @retval None
mbed_official 340:28d1f895c6fe 529 */
mbed_official 340:28d1f895c6fe 530 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
mbed_official 340:28d1f895c6fe 531 {
mbed_official 340:28d1f895c6fe 532 /* Transfer Error Interrupt management ***************************************/
mbed_official 340:28d1f895c6fe 533 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
mbed_official 340:28d1f895c6fe 534 {
mbed_official 340:28d1f895c6fe 535 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
mbed_official 340:28d1f895c6fe 536 {
mbed_official 340:28d1f895c6fe 537 /* Disable the transfer error interrupt */
mbed_official 340:28d1f895c6fe 538 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
mbed_official 340:28d1f895c6fe 539
mbed_official 340:28d1f895c6fe 540 /* Clear the transfer error flag */
mbed_official 340:28d1f895c6fe 541 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
mbed_official 340:28d1f895c6fe 542
mbed_official 340:28d1f895c6fe 543 /* Update error code */
mbed_official 340:28d1f895c6fe 544 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
mbed_official 340:28d1f895c6fe 545
mbed_official 340:28d1f895c6fe 546 /* Change the DMA state */
mbed_official 340:28d1f895c6fe 547 hdma->State = HAL_DMA_STATE_ERROR;
mbed_official 340:28d1f895c6fe 548
mbed_official 340:28d1f895c6fe 549 /* Process Unlocked */
mbed_official 340:28d1f895c6fe 550 __HAL_UNLOCK(hdma);
mbed_official 340:28d1f895c6fe 551
mbed_official 441:d2c15dda23c1 552 if (hdma->XferErrorCallback != (void (*)(DMA_HandleTypeDef *))NULL)
mbed_official 340:28d1f895c6fe 553 {
mbed_official 340:28d1f895c6fe 554 /* Transfer error callback */
mbed_official 340:28d1f895c6fe 555 hdma->XferErrorCallback(hdma);
mbed_official 340:28d1f895c6fe 556 }
mbed_official 340:28d1f895c6fe 557 }
mbed_official 340:28d1f895c6fe 558 }
mbed_official 340:28d1f895c6fe 559
mbed_official 340:28d1f895c6fe 560 /* Half Transfer Complete Interrupt management ******************************/
mbed_official 340:28d1f895c6fe 561 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
mbed_official 340:28d1f895c6fe 562 {
mbed_official 340:28d1f895c6fe 563 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
mbed_official 340:28d1f895c6fe 564 {
mbed_official 340:28d1f895c6fe 565 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
mbed_official 340:28d1f895c6fe 566 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
mbed_official 340:28d1f895c6fe 567 {
mbed_official 340:28d1f895c6fe 568 /* Disable the half transfer interrupt */
mbed_official 340:28d1f895c6fe 569 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
mbed_official 340:28d1f895c6fe 570 }
mbed_official 340:28d1f895c6fe 571 /* Clear the half transfer complete flag */
mbed_official 340:28d1f895c6fe 572 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
mbed_official 340:28d1f895c6fe 573
mbed_official 340:28d1f895c6fe 574 /* Change DMA peripheral state */
mbed_official 340:28d1f895c6fe 575 hdma->State = HAL_DMA_STATE_READY_HALF;
mbed_official 340:28d1f895c6fe 576
mbed_official 441:d2c15dda23c1 577 if(hdma->XferHalfCpltCallback != (void (*)(DMA_HandleTypeDef *))NULL)
mbed_official 340:28d1f895c6fe 578 {
mbed_official 340:28d1f895c6fe 579 /* Half transfer callback */
mbed_official 340:28d1f895c6fe 580 hdma->XferHalfCpltCallback(hdma);
mbed_official 340:28d1f895c6fe 581 }
mbed_official 340:28d1f895c6fe 582 }
mbed_official 340:28d1f895c6fe 583 }
mbed_official 340:28d1f895c6fe 584
mbed_official 340:28d1f895c6fe 585 /* Transfer Complete Interrupt management ***********************************/
mbed_official 340:28d1f895c6fe 586 if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
mbed_official 340:28d1f895c6fe 587 {
mbed_official 340:28d1f895c6fe 588 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
mbed_official 340:28d1f895c6fe 589 {
mbed_official 340:28d1f895c6fe 590 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
mbed_official 340:28d1f895c6fe 591 {
mbed_official 340:28d1f895c6fe 592 /* Disable the transfer complete interrupt */
mbed_official 340:28d1f895c6fe 593 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
mbed_official 340:28d1f895c6fe 594 }
mbed_official 340:28d1f895c6fe 595 /* Clear the transfer complete flag */
mbed_official 340:28d1f895c6fe 596 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
mbed_official 340:28d1f895c6fe 597
mbed_official 340:28d1f895c6fe 598 /* Update error code */
mbed_official 340:28d1f895c6fe 599 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE);
mbed_official 340:28d1f895c6fe 600
mbed_official 340:28d1f895c6fe 601 /* Change the DMA state */
mbed_official 340:28d1f895c6fe 602 hdma->State = HAL_DMA_STATE_READY;
mbed_official 340:28d1f895c6fe 603
mbed_official 340:28d1f895c6fe 604 /* Process Unlocked */
mbed_official 340:28d1f895c6fe 605 __HAL_UNLOCK(hdma);
mbed_official 340:28d1f895c6fe 606
mbed_official 441:d2c15dda23c1 607 if(hdma->XferCpltCallback != (void (*)(DMA_HandleTypeDef *))NULL)
mbed_official 340:28d1f895c6fe 608 {
mbed_official 340:28d1f895c6fe 609 /* Transfer complete callback */
mbed_official 340:28d1f895c6fe 610 hdma->XferCpltCallback(hdma);
mbed_official 340:28d1f895c6fe 611 }
mbed_official 340:28d1f895c6fe 612 }
mbed_official 340:28d1f895c6fe 613 }
mbed_official 340:28d1f895c6fe 614 }
mbed_official 340:28d1f895c6fe 615
mbed_official 340:28d1f895c6fe 616 /**
mbed_official 340:28d1f895c6fe 617 * @}
mbed_official 340:28d1f895c6fe 618 */
mbed_official 340:28d1f895c6fe 619
mbed_official 340:28d1f895c6fe 620 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
mbed_official 340:28d1f895c6fe 621 * @brief Peripheral State functions
mbed_official 340:28d1f895c6fe 622 *
mbed_official 340:28d1f895c6fe 623 @verbatim
mbed_official 340:28d1f895c6fe 624 ===============================================================================
mbed_official 340:28d1f895c6fe 625 ##### State and Errors functions #####
mbed_official 340:28d1f895c6fe 626 ===============================================================================
mbed_official 340:28d1f895c6fe 627 [..]
mbed_official 340:28d1f895c6fe 628 This subsection provides functions allowing to
mbed_official 340:28d1f895c6fe 629 (+) Check the DMA state
mbed_official 340:28d1f895c6fe 630 (+) Get error code
mbed_official 340:28d1f895c6fe 631
mbed_official 340:28d1f895c6fe 632 @endverbatim
mbed_official 340:28d1f895c6fe 633 * @{
mbed_official 340:28d1f895c6fe 634 */
mbed_official 340:28d1f895c6fe 635
mbed_official 340:28d1f895c6fe 636 /**
mbed_official 340:28d1f895c6fe 637 * @brief Returns the DMA state.
mbed_official 340:28d1f895c6fe 638 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 639 * the configuration information for the specified DMA Channel.
mbed_official 340:28d1f895c6fe 640 * @retval HAL state
mbed_official 340:28d1f895c6fe 641 */
mbed_official 340:28d1f895c6fe 642 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
mbed_official 340:28d1f895c6fe 643 {
mbed_official 340:28d1f895c6fe 644 return hdma->State;
mbed_official 340:28d1f895c6fe 645 }
mbed_official 340:28d1f895c6fe 646
mbed_official 340:28d1f895c6fe 647 /**
mbed_official 340:28d1f895c6fe 648 * @brief Return the DMA error code
mbed_official 340:28d1f895c6fe 649 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 650 * the configuration information for the specified DMA Channel.
mbed_official 340:28d1f895c6fe 651 * @retval DMA Error Code
mbed_official 340:28d1f895c6fe 652 */
mbed_official 340:28d1f895c6fe 653 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
mbed_official 340:28d1f895c6fe 654 {
mbed_official 340:28d1f895c6fe 655 return hdma->ErrorCode;
mbed_official 340:28d1f895c6fe 656 }
mbed_official 340:28d1f895c6fe 657
mbed_official 340:28d1f895c6fe 658 /**
mbed_official 340:28d1f895c6fe 659 * @}
mbed_official 340:28d1f895c6fe 660 */
mbed_official 340:28d1f895c6fe 661
mbed_official 340:28d1f895c6fe 662 /**
mbed_official 340:28d1f895c6fe 663 * @}
mbed_official 340:28d1f895c6fe 664 */
mbed_official 340:28d1f895c6fe 665
mbed_official 630:825f75ca301e 666 /** @addtogroup DMA_Private_Functions
mbed_official 340:28d1f895c6fe 667 * @{
mbed_official 340:28d1f895c6fe 668 */
mbed_official 340:28d1f895c6fe 669
mbed_official 340:28d1f895c6fe 670 /**
mbed_official 340:28d1f895c6fe 671 * @brief Sets the DMA Transfer parameter.
mbed_official 340:28d1f895c6fe 672 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 673 * the configuration information for the specified DMA Channel.
mbed_official 340:28d1f895c6fe 674 * @param SrcAddress: The source memory Buffer address
mbed_official 340:28d1f895c6fe 675 * @param DstAddress: The destination memory Buffer address
mbed_official 340:28d1f895c6fe 676 * @param DataLength: The length of data to be transferred from source to destination
mbed_official 340:28d1f895c6fe 677 * @retval HAL status
mbed_official 340:28d1f895c6fe 678 */
mbed_official 340:28d1f895c6fe 679 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
mbed_official 340:28d1f895c6fe 680 {
mbed_official 340:28d1f895c6fe 681 /* Configure DMA Channel data length */
mbed_official 340:28d1f895c6fe 682 hdma->Instance->CNDTR = DataLength;
mbed_official 340:28d1f895c6fe 683
mbed_official 340:28d1f895c6fe 684 /* Peripheral to Memory */
mbed_official 340:28d1f895c6fe 685 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
mbed_official 340:28d1f895c6fe 686 {
mbed_official 340:28d1f895c6fe 687 /* Configure DMA Channel destination address */
mbed_official 340:28d1f895c6fe 688 hdma->Instance->CPAR = DstAddress;
mbed_official 340:28d1f895c6fe 689
mbed_official 340:28d1f895c6fe 690 /* Configure DMA Channel source address */
mbed_official 340:28d1f895c6fe 691 hdma->Instance->CMAR = SrcAddress;
mbed_official 340:28d1f895c6fe 692 }
mbed_official 340:28d1f895c6fe 693 /* Memory to Peripheral */
mbed_official 340:28d1f895c6fe 694 else
mbed_official 340:28d1f895c6fe 695 {
mbed_official 340:28d1f895c6fe 696 /* Configure DMA Channel source address */
mbed_official 340:28d1f895c6fe 697 hdma->Instance->CPAR = SrcAddress;
mbed_official 340:28d1f895c6fe 698
mbed_official 340:28d1f895c6fe 699 /* Configure DMA Channel destination address */
mbed_official 340:28d1f895c6fe 700 hdma->Instance->CMAR = DstAddress;
mbed_official 340:28d1f895c6fe 701 }
mbed_official 340:28d1f895c6fe 702 }
mbed_official 340:28d1f895c6fe 703
mbed_official 340:28d1f895c6fe 704 /**
mbed_official 340:28d1f895c6fe 705 * @}
mbed_official 340:28d1f895c6fe 706 */
mbed_official 340:28d1f895c6fe 707
mbed_official 340:28d1f895c6fe 708 /**
mbed_official 340:28d1f895c6fe 709 * @}
mbed_official 340:28d1f895c6fe 710 */
mbed_official 630:825f75ca301e 711 #endif /* HAL_DMA_MODULE_ENABLED */
mbed_official 340:28d1f895c6fe 712
mbed_official 340:28d1f895c6fe 713 /**
mbed_official 340:28d1f895c6fe 714 * @}
mbed_official 340:28d1f895c6fe 715 */
mbed_official 340:28d1f895c6fe 716
mbed_official 340:28d1f895c6fe 717 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/