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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.c@630:825f75ca301e, 2015-09-28 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Sep 28 10:45:10 2015 +0100
- Revision:
- 630:825f75ca301e
Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10
Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/
NUCLEO_F031K6 : Add new target
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 630:825f75ca301e | 1 | /** |
| mbed_official | 630:825f75ca301e | 2 | ****************************************************************************** |
| mbed_official | 630:825f75ca301e | 3 | * @file system_stm32f0xx.c |
| mbed_official | 630:825f75ca301e | 4 | * @author MCD Application Team |
| mbed_official | 630:825f75ca301e | 5 | * @version V2.2.2 |
| mbed_official | 630:825f75ca301e | 6 | * @date 26-June-2015 |
| mbed_official | 630:825f75ca301e | 7 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. |
| mbed_official | 630:825f75ca301e | 8 | * |
| mbed_official | 630:825f75ca301e | 9 | * 1. This file provides two functions and one global variable to be called from |
| mbed_official | 630:825f75ca301e | 10 | * user application: |
| mbed_official | 630:825f75ca301e | 11 | * - SystemInit(): This function is called at startup just after reset and |
| mbed_official | 630:825f75ca301e | 12 | * before branch to main program. This call is made inside |
| mbed_official | 630:825f75ca301e | 13 | * the "startup_stm32f0xx.s" file. |
| mbed_official | 630:825f75ca301e | 14 | * |
| mbed_official | 630:825f75ca301e | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
| mbed_official | 630:825f75ca301e | 16 | * by the user application to setup the SysTick |
| mbed_official | 630:825f75ca301e | 17 | * timer or configure other parameters. |
| mbed_official | 630:825f75ca301e | 18 | * |
| mbed_official | 630:825f75ca301e | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
| mbed_official | 630:825f75ca301e | 20 | * be called whenever the core clock is changed |
| mbed_official | 630:825f75ca301e | 21 | * during program execution. |
| mbed_official | 630:825f75ca301e | 22 | * |
| mbed_official | 630:825f75ca301e | 23 | * 2. After each device reset the HSI (8 MHz) is used as system clock source. |
| mbed_official | 630:825f75ca301e | 24 | * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to |
| mbed_official | 630:825f75ca301e | 25 | * configure the system clock before to branch to main program. |
| mbed_official | 630:825f75ca301e | 26 | * |
| mbed_official | 630:825f75ca301e | 27 | * 3. This file configures the system clock as follows: |
| mbed_official | 630:825f75ca301e | 28 | *============================================================================= |
| mbed_official | 630:825f75ca301e | 29 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
| mbed_official | 630:825f75ca301e | 30 | * | (external 8 MHz clock) | (internal 48 MHz) |
| mbed_official | 630:825f75ca301e | 31 | * | 2- PLL_HSE_XTAL | |
| mbed_official | 630:825f75ca301e | 32 | * | (external 8 MHz xtal) | |
| mbed_official | 630:825f75ca301e | 33 | *----------------------------------------------------------------------------- |
| mbed_official | 630:825f75ca301e | 34 | * SYSCLK(MHz) | 48 | 48 |
| mbed_official | 630:825f75ca301e | 35 | *----------------------------------------------------------------------------- |
| mbed_official | 630:825f75ca301e | 36 | * AHBCLK (MHz) | 48 | 48 |
| mbed_official | 630:825f75ca301e | 37 | *----------------------------------------------------------------------------- |
| mbed_official | 630:825f75ca301e | 38 | * APB1CLK (MHz) | 48 | 48 |
| mbed_official | 630:825f75ca301e | 39 | *----------------------------------------------------------------------------- |
| mbed_official | 630:825f75ca301e | 40 | * USB capable (48 MHz precise clock) | YES | YES |
| mbed_official | 630:825f75ca301e | 41 | *============================================================================= |
| mbed_official | 630:825f75ca301e | 42 | ****************************************************************************** |
| mbed_official | 630:825f75ca301e | 43 | * @attention |
| mbed_official | 630:825f75ca301e | 44 | * |
| mbed_official | 630:825f75ca301e | 45 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| mbed_official | 630:825f75ca301e | 46 | * |
| mbed_official | 630:825f75ca301e | 47 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 630:825f75ca301e | 48 | * are permitted provided that the following conditions are met: |
| mbed_official | 630:825f75ca301e | 49 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 630:825f75ca301e | 50 | * this list of conditions and the following disclaimer. |
| mbed_official | 630:825f75ca301e | 51 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 630:825f75ca301e | 52 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 630:825f75ca301e | 53 | * and/or other materials provided with the distribution. |
| mbed_official | 630:825f75ca301e | 54 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 630:825f75ca301e | 55 | * may be used to endorse or promote products derived from this software |
| mbed_official | 630:825f75ca301e | 56 | * without specific prior written permission. |
| mbed_official | 630:825f75ca301e | 57 | * |
| mbed_official | 630:825f75ca301e | 58 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 630:825f75ca301e | 59 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 630:825f75ca301e | 60 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 630:825f75ca301e | 61 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 630:825f75ca301e | 62 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 630:825f75ca301e | 63 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 630:825f75ca301e | 64 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 630:825f75ca301e | 65 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 630:825f75ca301e | 66 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 630:825f75ca301e | 67 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 630:825f75ca301e | 68 | * |
| mbed_official | 630:825f75ca301e | 69 | ****************************************************************************** |
| mbed_official | 630:825f75ca301e | 70 | */ |
| mbed_official | 630:825f75ca301e | 71 | |
| mbed_official | 630:825f75ca301e | 72 | /** @addtogroup CMSIS |
| mbed_official | 630:825f75ca301e | 73 | * @{ |
| mbed_official | 630:825f75ca301e | 74 | */ |
| mbed_official | 630:825f75ca301e | 75 | |
| mbed_official | 630:825f75ca301e | 76 | /** @addtogroup stm32f0xx_system |
| mbed_official | 630:825f75ca301e | 77 | * @{ |
| mbed_official | 630:825f75ca301e | 78 | */ |
| mbed_official | 630:825f75ca301e | 79 | |
| mbed_official | 630:825f75ca301e | 80 | /** @addtogroup STM32F0xx_System_Private_Includes |
| mbed_official | 630:825f75ca301e | 81 | * @{ |
| mbed_official | 630:825f75ca301e | 82 | */ |
| mbed_official | 630:825f75ca301e | 83 | |
| mbed_official | 630:825f75ca301e | 84 | #include "stm32f0xx.h" |
| mbed_official | 630:825f75ca301e | 85 | |
| mbed_official | 630:825f75ca301e | 86 | /** |
| mbed_official | 630:825f75ca301e | 87 | * @} |
| mbed_official | 630:825f75ca301e | 88 | */ |
| mbed_official | 630:825f75ca301e | 89 | |
| mbed_official | 630:825f75ca301e | 90 | /** @addtogroup STM32F0xx_System_Private_TypesDefinitions |
| mbed_official | 630:825f75ca301e | 91 | * @{ |
| mbed_official | 630:825f75ca301e | 92 | */ |
| mbed_official | 630:825f75ca301e | 93 | |
| mbed_official | 630:825f75ca301e | 94 | /** |
| mbed_official | 630:825f75ca301e | 95 | * @} |
| mbed_official | 630:825f75ca301e | 96 | */ |
| mbed_official | 630:825f75ca301e | 97 | |
| mbed_official | 630:825f75ca301e | 98 | /** @addtogroup STM32F0xx_System_Private_Defines |
| mbed_official | 630:825f75ca301e | 99 | * @{ |
| mbed_official | 630:825f75ca301e | 100 | */ |
| mbed_official | 630:825f75ca301e | 101 | #if !defined (HSE_VALUE) |
| mbed_official | 630:825f75ca301e | 102 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. |
| mbed_official | 630:825f75ca301e | 103 | This value can be provided and adapted by the user application. */ |
| mbed_official | 630:825f75ca301e | 104 | #endif /* HSE_VALUE */ |
| mbed_official | 630:825f75ca301e | 105 | |
| mbed_official | 630:825f75ca301e | 106 | #if !defined (HSI_VALUE) |
| mbed_official | 630:825f75ca301e | 107 | #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. |
| mbed_official | 630:825f75ca301e | 108 | This value can be provided and adapted by the user application. */ |
| mbed_official | 630:825f75ca301e | 109 | #endif /* HSI_VALUE */ |
| mbed_official | 630:825f75ca301e | 110 | |
| mbed_official | 630:825f75ca301e | 111 | /** |
| mbed_official | 630:825f75ca301e | 112 | * @} |
| mbed_official | 630:825f75ca301e | 113 | */ |
| mbed_official | 630:825f75ca301e | 114 | |
| mbed_official | 630:825f75ca301e | 115 | /** @addtogroup STM32F0xx_System_Private_Macros |
| mbed_official | 630:825f75ca301e | 116 | * @{ |
| mbed_official | 630:825f75ca301e | 117 | */ |
| mbed_official | 630:825f75ca301e | 118 | |
| mbed_official | 630:825f75ca301e | 119 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
| mbed_official | 630:825f75ca301e | 120 | #define USE_PLL_HSE_EXTC (1) /* Use external clock */ |
| mbed_official | 630:825f75ca301e | 121 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
| mbed_official | 630:825f75ca301e | 122 | |
| mbed_official | 630:825f75ca301e | 123 | /** |
| mbed_official | 630:825f75ca301e | 124 | * @} |
| mbed_official | 630:825f75ca301e | 125 | */ |
| mbed_official | 630:825f75ca301e | 126 | |
| mbed_official | 630:825f75ca301e | 127 | /** @addtogroup STM32F0xx_System_Private_Variables |
| mbed_official | 630:825f75ca301e | 128 | * @{ |
| mbed_official | 630:825f75ca301e | 129 | */ |
| mbed_official | 630:825f75ca301e | 130 | /* This variable is updated in three ways: |
| mbed_official | 630:825f75ca301e | 131 | 1) by calling CMSIS function SystemCoreClockUpdate() |
| mbed_official | 630:825f75ca301e | 132 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
| mbed_official | 630:825f75ca301e | 133 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
| mbed_official | 630:825f75ca301e | 134 | Note: If you use this function to configure the system clock there is no need to |
| mbed_official | 630:825f75ca301e | 135 | call the 2 first functions listed above, since SystemCoreClock variable is |
| mbed_official | 630:825f75ca301e | 136 | updated automatically. |
| mbed_official | 630:825f75ca301e | 137 | */ |
| mbed_official | 630:825f75ca301e | 138 | uint32_t SystemCoreClock = 48000000; |
| mbed_official | 630:825f75ca301e | 139 | |
| mbed_official | 630:825f75ca301e | 140 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
| mbed_official | 630:825f75ca301e | 141 | |
| mbed_official | 630:825f75ca301e | 142 | /** |
| mbed_official | 630:825f75ca301e | 143 | * @} |
| mbed_official | 630:825f75ca301e | 144 | */ |
| mbed_official | 630:825f75ca301e | 145 | |
| mbed_official | 630:825f75ca301e | 146 | /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes |
| mbed_official | 630:825f75ca301e | 147 | * @{ |
| mbed_official | 630:825f75ca301e | 148 | */ |
| mbed_official | 630:825f75ca301e | 149 | |
| mbed_official | 630:825f75ca301e | 150 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| mbed_official | 630:825f75ca301e | 151 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
| mbed_official | 630:825f75ca301e | 152 | #endif |
| mbed_official | 630:825f75ca301e | 153 | |
| mbed_official | 630:825f75ca301e | 154 | uint8_t SetSysClock_PLL_HSI(void); |
| mbed_official | 630:825f75ca301e | 155 | |
| mbed_official | 630:825f75ca301e | 156 | /** |
| mbed_official | 630:825f75ca301e | 157 | * @} |
| mbed_official | 630:825f75ca301e | 158 | */ |
| mbed_official | 630:825f75ca301e | 159 | |
| mbed_official | 630:825f75ca301e | 160 | /** @addtogroup STM32F0xx_System_Private_Functions |
| mbed_official | 630:825f75ca301e | 161 | * @{ |
| mbed_official | 630:825f75ca301e | 162 | */ |
| mbed_official | 630:825f75ca301e | 163 | |
| mbed_official | 630:825f75ca301e | 164 | /** |
| mbed_official | 630:825f75ca301e | 165 | * @brief Setup the microcontroller system. |
| mbed_official | 630:825f75ca301e | 166 | * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. |
| mbed_official | 630:825f75ca301e | 167 | * @param None |
| mbed_official | 630:825f75ca301e | 168 | * @retval None |
| mbed_official | 630:825f75ca301e | 169 | */ |
| mbed_official | 630:825f75ca301e | 170 | void SystemInit(void) |
| mbed_official | 630:825f75ca301e | 171 | { |
| mbed_official | 630:825f75ca301e | 172 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
| mbed_official | 630:825f75ca301e | 173 | /* Set HSION bit */ |
| mbed_official | 630:825f75ca301e | 174 | RCC->CR |= (uint32_t)0x00000001; |
| mbed_official | 630:825f75ca301e | 175 | |
| mbed_official | 630:825f75ca301e | 176 | #if defined (STM32F051x8) || defined (STM32F058x8) |
| mbed_official | 630:825f75ca301e | 177 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ |
| mbed_official | 630:825f75ca301e | 178 | RCC->CFGR &= (uint32_t)0xF8FFB80C; |
| mbed_official | 630:825f75ca301e | 179 | #else |
| mbed_official | 630:825f75ca301e | 180 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ |
| mbed_official | 630:825f75ca301e | 181 | RCC->CFGR &= (uint32_t)0x08FFB80C; |
| mbed_official | 630:825f75ca301e | 182 | #endif /* STM32F051x8 or STM32F058x8 */ |
| mbed_official | 630:825f75ca301e | 183 | |
| mbed_official | 630:825f75ca301e | 184 | /* Reset HSEON, CSSON and PLLON bits */ |
| mbed_official | 630:825f75ca301e | 185 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
| mbed_official | 630:825f75ca301e | 186 | |
| mbed_official | 630:825f75ca301e | 187 | /* Reset HSEBYP bit */ |
| mbed_official | 630:825f75ca301e | 188 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
| mbed_official | 630:825f75ca301e | 189 | |
| mbed_official | 630:825f75ca301e | 190 | /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ |
| mbed_official | 630:825f75ca301e | 191 | RCC->CFGR &= (uint32_t)0xFFC0FFFF; |
| mbed_official | 630:825f75ca301e | 192 | |
| mbed_official | 630:825f75ca301e | 193 | /* Reset PREDIV[3:0] bits */ |
| mbed_official | 630:825f75ca301e | 194 | RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; |
| mbed_official | 630:825f75ca301e | 195 | |
| mbed_official | 630:825f75ca301e | 196 | #if defined (STM32F072xB) || defined (STM32F078xx) |
| mbed_official | 630:825f75ca301e | 197 | /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ |
| mbed_official | 630:825f75ca301e | 198 | RCC->CFGR3 &= (uint32_t)0xFFFCFE2C; |
| mbed_official | 630:825f75ca301e | 199 | #elif defined (STM32F071xB) |
| mbed_official | 630:825f75ca301e | 200 | /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
| mbed_official | 630:825f75ca301e | 201 | RCC->CFGR3 &= (uint32_t)0xFFFFCEAC; |
| mbed_official | 630:825f75ca301e | 202 | #elif defined (STM32F091xC) || defined (STM32F098xx) |
| mbed_official | 630:825f75ca301e | 203 | /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
| mbed_official | 630:825f75ca301e | 204 | RCC->CFGR3 &= (uint32_t)0xFFF0FEAC; |
| mbed_official | 630:825f75ca301e | 205 | #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) |
| mbed_official | 630:825f75ca301e | 206 | /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ |
| mbed_official | 630:825f75ca301e | 207 | RCC->CFGR3 &= (uint32_t)0xFFFFFEEC; |
| mbed_official | 630:825f75ca301e | 208 | #elif defined (STM32F051x8) || defined (STM32F058xx) |
| mbed_official | 630:825f75ca301e | 209 | /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
| mbed_official | 630:825f75ca301e | 210 | RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; |
| mbed_official | 630:825f75ca301e | 211 | #elif defined (STM32F042x6) || defined (STM32F048xx) |
| mbed_official | 630:825f75ca301e | 212 | /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ |
| mbed_official | 630:825f75ca301e | 213 | RCC->CFGR3 &= (uint32_t)0xFFFFFE2C; |
| mbed_official | 630:825f75ca301e | 214 | #elif defined (STM32F070x6) || defined (STM32F070xB) |
| mbed_official | 630:825f75ca301e | 215 | /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ |
| mbed_official | 630:825f75ca301e | 216 | RCC->CFGR3 &= (uint32_t)0xFFFFFE6C; |
| mbed_official | 630:825f75ca301e | 217 | /* Set default USB clock to PLLCLK, since there is no HSI48 */ |
| mbed_official | 630:825f75ca301e | 218 | RCC->CFGR3 |= (uint32_t)0x00000080; |
| mbed_official | 630:825f75ca301e | 219 | #else |
| mbed_official | 630:825f75ca301e | 220 | #warning "No target selected" |
| mbed_official | 630:825f75ca301e | 221 | #endif |
| mbed_official | 630:825f75ca301e | 222 | |
| mbed_official | 630:825f75ca301e | 223 | /* Reset HSI14 bit */ |
| mbed_official | 630:825f75ca301e | 224 | RCC->CR2 &= (uint32_t)0xFFFFFFFE; |
| mbed_official | 630:825f75ca301e | 225 | |
| mbed_official | 630:825f75ca301e | 226 | /* Disable all interrupts */ |
| mbed_official | 630:825f75ca301e | 227 | RCC->CIR = 0x00000000; |
| mbed_official | 630:825f75ca301e | 228 | } |
| mbed_official | 630:825f75ca301e | 229 | |
| mbed_official | 630:825f75ca301e | 230 | /** |
| mbed_official | 630:825f75ca301e | 231 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
| mbed_official | 630:825f75ca301e | 232 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
| mbed_official | 630:825f75ca301e | 233 | * be used by the user application to setup the SysTick timer or configure |
| mbed_official | 630:825f75ca301e | 234 | * other parameters. |
| mbed_official | 630:825f75ca301e | 235 | * |
| mbed_official | 630:825f75ca301e | 236 | * @note Each time the core clock (HCLK) changes, this function must be called |
| mbed_official | 630:825f75ca301e | 237 | * to update SystemCoreClock variable value. Otherwise, any configuration |
| mbed_official | 630:825f75ca301e | 238 | * based on this variable will be incorrect. |
| mbed_official | 630:825f75ca301e | 239 | * |
| mbed_official | 630:825f75ca301e | 240 | * @note - The system frequency computed by this function is not the real |
| mbed_official | 630:825f75ca301e | 241 | * frequency in the chip. It is calculated based on the predefined |
| mbed_official | 630:825f75ca301e | 242 | * constant and the selected clock source: |
| mbed_official | 630:825f75ca301e | 243 | * |
| mbed_official | 630:825f75ca301e | 244 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
| mbed_official | 630:825f75ca301e | 245 | * |
| mbed_official | 630:825f75ca301e | 246 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 630:825f75ca301e | 247 | * |
| mbed_official | 630:825f75ca301e | 248 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 630:825f75ca301e | 249 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
| mbed_official | 630:825f75ca301e | 250 | * |
| mbed_official | 630:825f75ca301e | 251 | * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value |
| mbed_official | 630:825f75ca301e | 252 | * 8 MHz) but the real value may vary depending on the variations |
| mbed_official | 630:825f75ca301e | 253 | * in voltage and temperature. |
| mbed_official | 630:825f75ca301e | 254 | * |
| mbed_official | 630:825f75ca301e | 255 | * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value |
| mbed_official | 630:825f75ca301e | 256 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
| mbed_official | 630:825f75ca301e | 257 | * frequency of the crystal used. Otherwise, this function may |
| mbed_official | 630:825f75ca301e | 258 | * have wrong result. |
| mbed_official | 630:825f75ca301e | 259 | * |
| mbed_official | 630:825f75ca301e | 260 | * - The result of this function could be not correct when using fractional |
| mbed_official | 630:825f75ca301e | 261 | * value for HSE crystal. |
| mbed_official | 630:825f75ca301e | 262 | * |
| mbed_official | 630:825f75ca301e | 263 | * @param None |
| mbed_official | 630:825f75ca301e | 264 | * @retval None |
| mbed_official | 630:825f75ca301e | 265 | */ |
| mbed_official | 630:825f75ca301e | 266 | void SystemCoreClockUpdate (void) |
| mbed_official | 630:825f75ca301e | 267 | { |
| mbed_official | 630:825f75ca301e | 268 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; |
| mbed_official | 630:825f75ca301e | 269 | |
| mbed_official | 630:825f75ca301e | 270 | /* Get SYSCLK source -------------------------------------------------------*/ |
| mbed_official | 630:825f75ca301e | 271 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
| mbed_official | 630:825f75ca301e | 272 | |
| mbed_official | 630:825f75ca301e | 273 | switch (tmp) |
| mbed_official | 630:825f75ca301e | 274 | { |
| mbed_official | 630:825f75ca301e | 275 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ |
| mbed_official | 630:825f75ca301e | 276 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 630:825f75ca301e | 277 | break; |
| mbed_official | 630:825f75ca301e | 278 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ |
| mbed_official | 630:825f75ca301e | 279 | SystemCoreClock = HSE_VALUE; |
| mbed_official | 630:825f75ca301e | 280 | break; |
| mbed_official | 630:825f75ca301e | 281 | case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ |
| mbed_official | 630:825f75ca301e | 282 | /* Get PLL clock source and multiplication factor ----------------------*/ |
| mbed_official | 630:825f75ca301e | 283 | pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; |
| mbed_official | 630:825f75ca301e | 284 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
| mbed_official | 630:825f75ca301e | 285 | pllmull = ( pllmull >> 18) + 2; |
| mbed_official | 630:825f75ca301e | 286 | predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; |
| mbed_official | 630:825f75ca301e | 287 | |
| mbed_official | 630:825f75ca301e | 288 | if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) |
| mbed_official | 630:825f75ca301e | 289 | { |
| mbed_official | 630:825f75ca301e | 290 | /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ |
| mbed_official | 630:825f75ca301e | 291 | SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; |
| mbed_official | 630:825f75ca301e | 292 | } |
| mbed_official | 630:825f75ca301e | 293 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 630:825f75ca301e | 294 | else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) |
| mbed_official | 630:825f75ca301e | 295 | { |
| mbed_official | 630:825f75ca301e | 296 | /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ |
| mbed_official | 630:825f75ca301e | 297 | SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; |
| mbed_official | 630:825f75ca301e | 298 | } |
| mbed_official | 630:825f75ca301e | 299 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ |
| mbed_official | 630:825f75ca301e | 300 | else |
| mbed_official | 630:825f75ca301e | 301 | { |
| mbed_official | 630:825f75ca301e | 302 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ |
| mbed_official | 630:825f75ca301e | 303 | || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ |
| mbed_official | 630:825f75ca301e | 304 | || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
| mbed_official | 630:825f75ca301e | 305 | /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ |
| mbed_official | 630:825f75ca301e | 306 | SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; |
| mbed_official | 630:825f75ca301e | 307 | #else |
| mbed_official | 630:825f75ca301e | 308 | /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ |
| mbed_official | 630:825f75ca301e | 309 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
| mbed_official | 630:825f75ca301e | 310 | #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || |
| mbed_official | 630:825f75ca301e | 311 | STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || |
| mbed_official | 630:825f75ca301e | 312 | STM32F091xC || STM32F098xx || STM32F030xC */ |
| mbed_official | 630:825f75ca301e | 313 | } |
| mbed_official | 630:825f75ca301e | 314 | break; |
| mbed_official | 630:825f75ca301e | 315 | default: /* HSI used as system clock */ |
| mbed_official | 630:825f75ca301e | 316 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 630:825f75ca301e | 317 | break; |
| mbed_official | 630:825f75ca301e | 318 | } |
| mbed_official | 630:825f75ca301e | 319 | /* Compute HCLK clock frequency ----------------*/ |
| mbed_official | 630:825f75ca301e | 320 | /* Get HCLK prescaler */ |
| mbed_official | 630:825f75ca301e | 321 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
| mbed_official | 630:825f75ca301e | 322 | /* HCLK clock frequency */ |
| mbed_official | 630:825f75ca301e | 323 | SystemCoreClock >>= tmp; |
| mbed_official | 630:825f75ca301e | 324 | } |
| mbed_official | 630:825f75ca301e | 325 | |
| mbed_official | 630:825f75ca301e | 326 | /** |
| mbed_official | 630:825f75ca301e | 327 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
| mbed_official | 630:825f75ca301e | 328 | * AHB/APBx prescalers and Flash settings |
| mbed_official | 630:825f75ca301e | 329 | * @note This function should be called only once the RCC clock configuration |
| mbed_official | 630:825f75ca301e | 330 | * is reset to the default reset state (done in SystemInit() function). |
| mbed_official | 630:825f75ca301e | 331 | * @param None |
| mbed_official | 630:825f75ca301e | 332 | * @retval None |
| mbed_official | 630:825f75ca301e | 333 | */ |
| mbed_official | 630:825f75ca301e | 334 | void SetSysClock(void) |
| mbed_official | 630:825f75ca301e | 335 | { |
| mbed_official | 630:825f75ca301e | 336 | /* 1- Try to start with HSE and external clock */ |
| mbed_official | 630:825f75ca301e | 337 | #if USE_PLL_HSE_EXTC != 0 |
| mbed_official | 630:825f75ca301e | 338 | if (SetSysClock_PLL_HSE(1) == 0) |
| mbed_official | 630:825f75ca301e | 339 | #endif |
| mbed_official | 630:825f75ca301e | 340 | { |
| mbed_official | 630:825f75ca301e | 341 | /* 2- If fail try to start with HSE and external xtal */ |
| mbed_official | 630:825f75ca301e | 342 | #if USE_PLL_HSE_XTAL != 0 |
| mbed_official | 630:825f75ca301e | 343 | if (SetSysClock_PLL_HSE(0) == 0) |
| mbed_official | 630:825f75ca301e | 344 | #endif |
| mbed_official | 630:825f75ca301e | 345 | { |
| mbed_official | 630:825f75ca301e | 346 | /* 3- If fail start with HSI clock */ |
| mbed_official | 630:825f75ca301e | 347 | if (SetSysClock_PLL_HSI() == 0) |
| mbed_official | 630:825f75ca301e | 348 | { |
| mbed_official | 630:825f75ca301e | 349 | while(1) |
| mbed_official | 630:825f75ca301e | 350 | { |
| mbed_official | 630:825f75ca301e | 351 | // [TODO] Put something here to tell the user that a problem occured... |
| mbed_official | 630:825f75ca301e | 352 | } |
| mbed_official | 630:825f75ca301e | 353 | } |
| mbed_official | 630:825f75ca301e | 354 | } |
| mbed_official | 630:825f75ca301e | 355 | } |
| mbed_official | 630:825f75ca301e | 356 | |
| mbed_official | 630:825f75ca301e | 357 | // Output clock on MCO pin(PA8) for debugging purpose |
| mbed_official | 630:825f75ca301e | 358 | // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz |
| mbed_official | 630:825f75ca301e | 359 | } |
| mbed_official | 630:825f75ca301e | 360 | |
| mbed_official | 630:825f75ca301e | 361 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| mbed_official | 630:825f75ca301e | 362 | /******************************************************************************/ |
| mbed_official | 630:825f75ca301e | 363 | /* PLL (clocked by HSE) used as System clock source */ |
| mbed_official | 630:825f75ca301e | 364 | /******************************************************************************/ |
| mbed_official | 630:825f75ca301e | 365 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
| mbed_official | 630:825f75ca301e | 366 | { |
| mbed_official | 630:825f75ca301e | 367 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
| mbed_official | 630:825f75ca301e | 368 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
| mbed_official | 630:825f75ca301e | 369 | //Select HSI as system clock source to allow modification of the PLL configuration |
| mbed_official | 630:825f75ca301e | 370 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; |
| mbed_official | 630:825f75ca301e | 371 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; |
| mbed_official | 630:825f75ca301e | 372 | if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) |
| mbed_official | 630:825f75ca301e | 373 | { |
| mbed_official | 630:825f75ca301e | 374 | return 0; // FAIL |
| mbed_official | 630:825f75ca301e | 375 | } |
| mbed_official | 630:825f75ca301e | 376 | |
| mbed_official | 630:825f75ca301e | 377 | |
| mbed_official | 630:825f75ca301e | 378 | // Select HSE oscillator as PLL source |
| mbed_official | 630:825f75ca301e | 379 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
| mbed_official | 630:825f75ca301e | 380 | if (bypass == 0) { |
| mbed_official | 630:825f75ca301e | 381 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT |
| mbed_official | 630:825f75ca301e | 382 | } else { |
| mbed_official | 630:825f75ca301e | 383 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only |
| mbed_official | 630:825f75ca301e | 384 | } |
| mbed_official | 630:825f75ca301e | 385 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 630:825f75ca301e | 386 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| mbed_official | 630:825f75ca301e | 387 | RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; |
| mbed_official | 630:825f75ca301e | 388 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; |
| mbed_official | 630:825f75ca301e | 389 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
| mbed_official | 630:825f75ca301e | 390 | return 0; // FAIL |
| mbed_official | 630:825f75ca301e | 391 | } |
| mbed_official | 630:825f75ca301e | 392 | |
| mbed_official | 630:825f75ca301e | 393 | // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers |
| mbed_official | 630:825f75ca301e | 394 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); |
| mbed_official | 630:825f75ca301e | 395 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz |
| mbed_official | 630:825f75ca301e | 396 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz |
| mbed_official | 630:825f75ca301e | 397 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz |
| mbed_official | 630:825f75ca301e | 398 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { |
| mbed_official | 630:825f75ca301e | 399 | return 0; // FAIL |
| mbed_official | 630:825f75ca301e | 400 | } |
| mbed_official | 630:825f75ca301e | 401 | |
| mbed_official | 630:825f75ca301e | 402 | // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz |
| mbed_official | 630:825f75ca301e | 403 | |
| mbed_official | 630:825f75ca301e | 404 | return 1; // OK |
| mbed_official | 630:825f75ca301e | 405 | } |
| mbed_official | 630:825f75ca301e | 406 | #endif |
| mbed_official | 630:825f75ca301e | 407 | |
| mbed_official | 630:825f75ca301e | 408 | /******************************************************************************/ |
| mbed_official | 630:825f75ca301e | 409 | /* PLL (clocked by HSI) used as System clock source */ |
| mbed_official | 630:825f75ca301e | 410 | /******************************************************************************/ |
| mbed_official | 630:825f75ca301e | 411 | uint8_t SetSysClock_PLL_HSI(void) |
| mbed_official | 630:825f75ca301e | 412 | { |
| mbed_official | 630:825f75ca301e | 413 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| mbed_official | 630:825f75ca301e | 414 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| mbed_official | 630:825f75ca301e | 415 | |
| mbed_official | 630:825f75ca301e | 416 | // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) |
| mbed_official | 630:825f75ca301e | 417 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; |
| mbed_official | 630:825f75ca301e | 418 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
| mbed_official | 630:825f75ca301e | 419 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 630:825f75ca301e | 420 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 |
| mbed_official | 630:825f75ca301e | 421 | RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; |
| mbed_official | 630:825f75ca301e | 422 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; |
| mbed_official | 630:825f75ca301e | 423 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
| mbed_official | 630:825f75ca301e | 424 | return 0; // FAIL |
| mbed_official | 630:825f75ca301e | 425 | } |
| mbed_official | 630:825f75ca301e | 426 | |
| mbed_official | 630:825f75ca301e | 427 | // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers |
| mbed_official | 630:825f75ca301e | 428 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); |
| mbed_official | 630:825f75ca301e | 429 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz |
| mbed_official | 630:825f75ca301e | 430 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz |
| mbed_official | 630:825f75ca301e | 431 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz |
| mbed_official | 630:825f75ca301e | 432 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { |
| mbed_official | 630:825f75ca301e | 433 | return 0; // FAIL |
| mbed_official | 630:825f75ca301e | 434 | } |
| mbed_official | 630:825f75ca301e | 435 | |
| mbed_official | 630:825f75ca301e | 436 | //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz |
| mbed_official | 630:825f75ca301e | 437 | |
| mbed_official | 630:825f75ca301e | 438 | return 1; // OK |
| mbed_official | 630:825f75ca301e | 439 | } |
| mbed_official | 630:825f75ca301e | 440 | |
| mbed_official | 630:825f75ca301e | 441 | /** |
| mbed_official | 630:825f75ca301e | 442 | * @} |
| mbed_official | 630:825f75ca301e | 443 | */ |
| mbed_official | 630:825f75ca301e | 444 | |
| mbed_official | 630:825f75ca301e | 445 | /** |
| mbed_official | 630:825f75ca301e | 446 | * @} |
| mbed_official | 630:825f75ca301e | 447 | */ |
| mbed_official | 630:825f75ca301e | 448 | |
| mbed_official | 630:825f75ca301e | 449 | /** |
| mbed_official | 630:825f75ca301e | 450 | * @} |
| mbed_official | 630:825f75ca301e | 451 | */ |
| mbed_official | 630:825f75ca301e | 452 | |
| mbed_official | 630:825f75ca301e | 453 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| mbed_official | 630:825f75ca301e | 454 |
