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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h@630:825f75ca301e, 2015-09-28 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Sep 28 10:45:10 2015 +0100
- Revision:
- 630:825f75ca301e
- Parent:
- 441:d2c15dda23c1
Synchronized with git revision 54fbe4144faf309c37205a5d39fa665daa919f10
Full URL: https://github.com/mbedmicro/mbed/commit/54fbe4144faf309c37205a5d39fa665daa919f10/
NUCLEO_F031K6 : Add new target
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 340:28d1f895c6fe | 1 | /** |
| mbed_official | 340:28d1f895c6fe | 2 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 3 | * @file stm32f0xx_hal.h |
| mbed_official | 340:28d1f895c6fe | 4 | * @author MCD Application Team |
| mbed_official | 630:825f75ca301e | 5 | * @version V1.3.0 |
| mbed_official | 630:825f75ca301e | 6 | * @date 26-June-2015 |
| mbed_official | 340:28d1f895c6fe | 7 | * @brief This file contains all the functions prototypes for the HAL |
| mbed_official | 340:28d1f895c6fe | 8 | * module driver. |
| mbed_official | 340:28d1f895c6fe | 9 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 10 | * @attention |
| mbed_official | 340:28d1f895c6fe | 11 | * |
| mbed_official | 630:825f75ca301e | 12 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| mbed_official | 340:28d1f895c6fe | 13 | * |
| mbed_official | 340:28d1f895c6fe | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 340:28d1f895c6fe | 15 | * are permitted provided that the following conditions are met: |
| mbed_official | 340:28d1f895c6fe | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 17 | * this list of conditions and the following disclaimer. |
| mbed_official | 340:28d1f895c6fe | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 19 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 340:28d1f895c6fe | 20 | * and/or other materials provided with the distribution. |
| mbed_official | 340:28d1f895c6fe | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 340:28d1f895c6fe | 22 | * may be used to endorse or promote products derived from this software |
| mbed_official | 340:28d1f895c6fe | 23 | * without specific prior written permission. |
| mbed_official | 340:28d1f895c6fe | 24 | * |
| mbed_official | 340:28d1f895c6fe | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 340:28d1f895c6fe | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 340:28d1f895c6fe | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 340:28d1f895c6fe | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 340:28d1f895c6fe | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 340:28d1f895c6fe | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 340:28d1f895c6fe | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 340:28d1f895c6fe | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 340:28d1f895c6fe | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 340:28d1f895c6fe | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 340:28d1f895c6fe | 35 | * |
| mbed_official | 340:28d1f895c6fe | 36 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 37 | */ |
| mbed_official | 340:28d1f895c6fe | 38 | |
| mbed_official | 340:28d1f895c6fe | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 40 | #ifndef __STM32F0xx_HAL_H |
| mbed_official | 340:28d1f895c6fe | 41 | #define __STM32F0xx_HAL_H |
| mbed_official | 340:28d1f895c6fe | 42 | |
| mbed_official | 340:28d1f895c6fe | 43 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 44 | extern "C" { |
| mbed_official | 340:28d1f895c6fe | 45 | #endif |
| mbed_official | 340:28d1f895c6fe | 46 | |
| mbed_official | 340:28d1f895c6fe | 47 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 48 | #include "stm32f0xx_hal_conf.h" |
| mbed_official | 340:28d1f895c6fe | 49 | |
| mbed_official | 340:28d1f895c6fe | 50 | /** @addtogroup STM32F0xx_HAL_Driver |
| mbed_official | 340:28d1f895c6fe | 51 | * @{ |
| mbed_official | 340:28d1f895c6fe | 52 | */ |
| mbed_official | 340:28d1f895c6fe | 53 | |
| mbed_official | 340:28d1f895c6fe | 54 | /** @addtogroup HAL |
| mbed_official | 340:28d1f895c6fe | 55 | * @{ |
| mbed_official | 340:28d1f895c6fe | 56 | */ |
| mbed_official | 340:28d1f895c6fe | 57 | |
| mbed_official | 630:825f75ca301e | 58 | /* Private macros ------------------------------------------------------------*/ |
| mbed_official | 630:825f75ca301e | 59 | /** @addtogroup HAL_Private_Macros |
| mbed_official | 630:825f75ca301e | 60 | * @{ |
| mbed_official | 630:825f75ca301e | 61 | */ |
| mbed_official | 630:825f75ca301e | 62 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ |
| mbed_official | 630:825f75ca301e | 63 | defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ |
| mbed_official | 630:825f75ca301e | 64 | defined(STM32F070xB) || defined(STM32F030x6) |
| mbed_official | 630:825f75ca301e | 65 | #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ |
| mbed_official | 630:825f75ca301e | 66 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ |
| mbed_official | 630:825f75ca301e | 67 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ |
| mbed_official | 630:825f75ca301e | 68 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ |
| mbed_official | 630:825f75ca301e | 69 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ |
| mbed_official | 630:825f75ca301e | 70 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) |
| mbed_official | 630:825f75ca301e | 71 | #else |
| mbed_official | 630:825f75ca301e | 72 | #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ |
| mbed_official | 630:825f75ca301e | 73 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ |
| mbed_official | 630:825f75ca301e | 74 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ |
| mbed_official | 630:825f75ca301e | 75 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) |
| mbed_official | 630:825f75ca301e | 76 | #endif |
| mbed_official | 630:825f75ca301e | 77 | #if defined(SYSCFG_CFGR1_PA11_PA12_RMP) |
| mbed_official | 630:825f75ca301e | 78 | #define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12) |
| mbed_official | 630:825f75ca301e | 79 | #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ |
| mbed_official | 630:825f75ca301e | 80 | #if defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 630:825f75ca301e | 81 | #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ |
| mbed_official | 630:825f75ca301e | 82 | ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ |
| mbed_official | 630:825f75ca301e | 83 | ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) |
| mbed_official | 630:825f75ca301e | 84 | #endif /* STM32F091xC || STM32F098xx */ |
| mbed_official | 630:825f75ca301e | 85 | /** |
| mbed_official | 630:825f75ca301e | 86 | * @} |
| mbed_official | 630:825f75ca301e | 87 | */ |
| mbed_official | 630:825f75ca301e | 88 | |
| mbed_official | 340:28d1f895c6fe | 89 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 90 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 91 | /** @defgroup HAL_Exported_Constants HAL Exported Constants |
| mbed_official | 630:825f75ca301e | 92 | * @{ |
| mbed_official | 340:28d1f895c6fe | 93 | */ |
| mbed_official | 340:28d1f895c6fe | 94 | |
| mbed_official | 340:28d1f895c6fe | 95 | #if defined(SYSCFG_CFGR1_PA11_PA12_RMP) |
| mbed_official | 340:28d1f895c6fe | 96 | /** @defgroup HAL_Pin_remapping HAL Pin remapping |
| mbed_official | 340:28d1f895c6fe | 97 | * @{ |
| mbed_official | 340:28d1f895c6fe | 98 | */ |
| mbed_official | 340:28d1f895c6fe | 99 | #define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins). |
| mbed_official | 340:28d1f895c6fe | 100 | 0: No remap (pin pair PA9/10 mapped on the pins) |
| mbed_official | 340:28d1f895c6fe | 101 | 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */ |
| mbed_official | 340:28d1f895c6fe | 102 | |
| mbed_official | 340:28d1f895c6fe | 103 | /** |
| mbed_official | 340:28d1f895c6fe | 104 | * @} |
| mbed_official | 340:28d1f895c6fe | 105 | */ |
| mbed_official | 340:28d1f895c6fe | 106 | #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ |
| mbed_official | 340:28d1f895c6fe | 107 | |
| mbed_official | 441:d2c15dda23c1 | 108 | #if defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 109 | /** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection |
| mbed_official | 441:d2c15dda23c1 | 110 | * @note Applicable on STM32F09x |
| mbed_official | 340:28d1f895c6fe | 111 | * @{ |
| mbed_official | 340:28d1f895c6fe | 112 | */ |
| mbed_official | 340:28d1f895c6fe | 113 | #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */ |
| mbed_official | 340:28d1f895c6fe | 114 | #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */ |
| mbed_official | 340:28d1f895c6fe | 115 | #define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */ |
| mbed_official | 340:28d1f895c6fe | 116 | |
| mbed_official | 340:28d1f895c6fe | 117 | /** |
| mbed_official | 340:28d1f895c6fe | 118 | * @} |
| mbed_official | 340:28d1f895c6fe | 119 | */ |
| mbed_official | 441:d2c15dda23c1 | 120 | #endif /* STM32F091xC || STM32F098xx */ |
| mbed_official | 340:28d1f895c6fe | 121 | |
| mbed_official | 340:28d1f895c6fe | 122 | |
| mbed_official | 630:825f75ca301e | 123 | /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO |
| mbed_official | 340:28d1f895c6fe | 124 | * @{ |
| mbed_official | 340:28d1f895c6fe | 125 | */ |
| mbed_official | 340:28d1f895c6fe | 126 | |
| mbed_official | 630:825f75ca301e | 127 | /** @brief Fast-mode Plus driving capability on a specific GPIO |
| mbed_official | 630:825f75ca301e | 128 | */ |
| mbed_official | 630:825f75ca301e | 129 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \ |
| mbed_official | 630:825f75ca301e | 130 | defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \ |
| mbed_official | 630:825f75ca301e | 131 | defined(STM32F070xB) || defined(STM32F030x6) |
| mbed_official | 630:825f75ca301e | 132 | #define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */ |
| mbed_official | 630:825f75ca301e | 133 | #define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */ |
| mbed_official | 340:28d1f895c6fe | 134 | #endif |
| mbed_official | 630:825f75ca301e | 135 | #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */ |
| mbed_official | 630:825f75ca301e | 136 | #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */ |
| mbed_official | 630:825f75ca301e | 137 | #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */ |
| mbed_official | 630:825f75ca301e | 138 | #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */ |
| mbed_official | 340:28d1f895c6fe | 139 | |
| mbed_official | 340:28d1f895c6fe | 140 | /** |
| mbed_official | 630:825f75ca301e | 141 | * @} |
| mbed_official | 630:825f75ca301e | 142 | */ |
| mbed_official | 630:825f75ca301e | 143 | |
| mbed_official | 340:28d1f895c6fe | 144 | |
| mbed_official | 340:28d1f895c6fe | 145 | #if defined(STM32F091xC) || defined (STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 146 | /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper |
| mbed_official | 441:d2c15dda23c1 | 147 | * @brief ISR Wrapper |
| mbed_official | 441:d2c15dda23c1 | 148 | * @note applicable on STM32F09x |
| mbed_official | 340:28d1f895c6fe | 149 | * @{ |
| mbed_official | 340:28d1f895c6fe | 150 | */ |
| mbed_official | 441:d2c15dda23c1 | 151 | #define HAL_SYSCFG_ITLINE0 ((uint32_t) 0x00000000) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 152 | #define HAL_SYSCFG_ITLINE1 ((uint32_t) 0x00000001) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 153 | #define HAL_SYSCFG_ITLINE2 ((uint32_t) 0x00000002) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 154 | #define HAL_SYSCFG_ITLINE3 ((uint32_t) 0x00000003) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 155 | #define HAL_SYSCFG_ITLINE4 ((uint32_t) 0x00000004) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 156 | #define HAL_SYSCFG_ITLINE5 ((uint32_t) 0x00000005) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 157 | #define HAL_SYSCFG_ITLINE6 ((uint32_t) 0x00000006) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 158 | #define HAL_SYSCFG_ITLINE7 ((uint32_t) 0x00000007) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 159 | #define HAL_SYSCFG_ITLINE8 ((uint32_t) 0x00000008) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 160 | #define HAL_SYSCFG_ITLINE9 ((uint32_t) 0x00000009) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 161 | #define HAL_SYSCFG_ITLINE10 ((uint32_t) 0x0000000A) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 162 | #define HAL_SYSCFG_ITLINE11 ((uint32_t) 0x0000000B) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 163 | #define HAL_SYSCFG_ITLINE12 ((uint32_t) 0x0000000C) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 164 | #define HAL_SYSCFG_ITLINE13 ((uint32_t) 0x0000000D) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 165 | #define HAL_SYSCFG_ITLINE14 ((uint32_t) 0x0000000E) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 166 | #define HAL_SYSCFG_ITLINE15 ((uint32_t) 0x0000000F) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 167 | #define HAL_SYSCFG_ITLINE16 ((uint32_t) 0x00000010) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 168 | #define HAL_SYSCFG_ITLINE17 ((uint32_t) 0x00000011) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 169 | #define HAL_SYSCFG_ITLINE18 ((uint32_t) 0x00000012) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 170 | #define HAL_SYSCFG_ITLINE19 ((uint32_t) 0x00000013) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 171 | #define HAL_SYSCFG_ITLINE20 ((uint32_t) 0x00000014) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 172 | #define HAL_SYSCFG_ITLINE21 ((uint32_t) 0x00000015) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 173 | #define HAL_SYSCFG_ITLINE22 ((uint32_t) 0x00000016) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 174 | #define HAL_SYSCFG_ITLINE23 ((uint32_t) 0x00000017) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 175 | #define HAL_SYSCFG_ITLINE24 ((uint32_t) 0x00000018) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 176 | #define HAL_SYSCFG_ITLINE25 ((uint32_t) 0x00000019) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 177 | #define HAL_SYSCFG_ITLINE26 ((uint32_t) 0x0000001A) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 178 | #define HAL_SYSCFG_ITLINE27 ((uint32_t) 0x0000001B) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 179 | #define HAL_SYSCFG_ITLINE28 ((uint32_t) 0x0000001C) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 180 | #define HAL_SYSCFG_ITLINE29 ((uint32_t) 0x0000001D) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 181 | #define HAL_SYSCFG_ITLINE30 ((uint32_t) 0x0000001E) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 182 | #define HAL_SYSCFG_ITLINE31 ((uint32_t) 0x0000001F) /*!< Internal define for macro handling */ |
| mbed_official | 340:28d1f895c6fe | 183 | |
| mbed_official | 441:d2c15dda23c1 | 184 | #define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */ |
| mbed_official | 340:28d1f895c6fe | 185 | #if defined(STM32F091xC) |
| mbed_official | 441:d2c15dda23c1 | 186 | #define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */ |
| mbed_official | 340:28d1f895c6fe | 187 | #endif |
| mbed_official | 441:d2c15dda23c1 | 188 | #define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 189 | #define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 190 | #define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 191 | #define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 192 | #define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 193 | #define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 194 | #define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 195 | #define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */ |
| mbed_official | 441:d2c15dda23c1 | 196 | #define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */ |
| mbed_official | 441:d2c15dda23c1 | 197 | #define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */ |
| mbed_official | 441:d2c15dda23c1 | 198 | #define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */ |
| mbed_official | 441:d2c15dda23c1 | 199 | #define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 200 | #define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 201 | #define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 202 | #define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 203 | #define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 204 | #define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 205 | #define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 206 | #define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 207 | #define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 208 | #define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 209 | #define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 210 | #define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 211 | #define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 212 | #define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 213 | #define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 214 | #define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 215 | #define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 216 | #define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 217 | #define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 218 | #define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 219 | #define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 220 | #define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 221 | #define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 222 | #define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 223 | #define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 224 | #define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 225 | #define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 226 | #define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */ |
| mbed_official | 441:d2c15dda23c1 | 227 | #define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */ |
| mbed_official | 441:d2c15dda23c1 | 228 | #define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 229 | #define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 230 | #define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 231 | #define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 232 | #define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 233 | #define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 234 | #define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 235 | #define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 236 | #define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 237 | #define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 238 | #define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 239 | #define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 240 | #define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 241 | #define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 242 | #define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */ |
| mbed_official | 441:d2c15dda23c1 | 243 | #define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 244 | #define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */ |
| mbed_official | 441:d2c15dda23c1 | 245 | #define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 246 | #define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */ |
| mbed_official | 340:28d1f895c6fe | 247 | #define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */ |
| mbed_official | 441:d2c15dda23c1 | 248 | #define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 249 | #define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 250 | #define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 251 | #define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 252 | #define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 253 | #define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 254 | #define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 255 | #define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */ |
| mbed_official | 340:28d1f895c6fe | 256 | /** |
| mbed_official | 340:28d1f895c6fe | 257 | * @} |
| mbed_official | 340:28d1f895c6fe | 258 | */ |
| mbed_official | 340:28d1f895c6fe | 259 | #endif /* STM32F091xC || STM32F098xx */ |
| mbed_official | 340:28d1f895c6fe | 260 | |
| mbed_official | 340:28d1f895c6fe | 261 | /** |
| mbed_official | 340:28d1f895c6fe | 262 | * @} |
| mbed_official | 340:28d1f895c6fe | 263 | */ |
| mbed_official | 340:28d1f895c6fe | 264 | |
| mbed_official | 340:28d1f895c6fe | 265 | /* Exported macros -----------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 266 | /** @defgroup HAL_Exported_Macros HAL Exported Macros |
| mbed_official | 340:28d1f895c6fe | 267 | * @{ |
| mbed_official | 340:28d1f895c6fe | 268 | */ |
| mbed_official | 340:28d1f895c6fe | 269 | |
| mbed_official | 340:28d1f895c6fe | 270 | /** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals |
| mbed_official | 340:28d1f895c6fe | 271 | * @brief Freeze/Unfreeze Peripherals in Debug mode |
| mbed_official | 340:28d1f895c6fe | 272 | * @{ |
| mbed_official | 340:28d1f895c6fe | 273 | */ |
| mbed_official | 340:28d1f895c6fe | 274 | |
| mbed_official | 340:28d1f895c6fe | 275 | #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) |
| mbed_official | 340:28d1f895c6fe | 276 | #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP)) |
| mbed_official | 340:28d1f895c6fe | 277 | #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP)) |
| mbed_official | 340:28d1f895c6fe | 278 | #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */ |
| mbed_official | 340:28d1f895c6fe | 279 | |
| mbed_official | 340:28d1f895c6fe | 280 | #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP) |
| mbed_official | 630:825f75ca301e | 281 | #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
| mbed_official | 630:825f75ca301e | 282 | #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
| mbed_official | 340:28d1f895c6fe | 283 | #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ |
| mbed_official | 340:28d1f895c6fe | 284 | |
| mbed_official | 340:28d1f895c6fe | 285 | #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) |
| mbed_official | 630:825f75ca301e | 286 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
| mbed_official | 630:825f75ca301e | 287 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
| mbed_official | 340:28d1f895c6fe | 288 | #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */ |
| mbed_official | 340:28d1f895c6fe | 289 | |
| mbed_official | 340:28d1f895c6fe | 290 | #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
| mbed_official | 630:825f75ca301e | 291 | #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
| mbed_official | 630:825f75ca301e | 292 | #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
| mbed_official | 340:28d1f895c6fe | 293 | #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */ |
| mbed_official | 340:28d1f895c6fe | 294 | |
| mbed_official | 340:28d1f895c6fe | 295 | #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
| mbed_official | 630:825f75ca301e | 296 | #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
| mbed_official | 630:825f75ca301e | 297 | #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
| mbed_official | 340:28d1f895c6fe | 298 | #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */ |
| mbed_official | 340:28d1f895c6fe | 299 | |
| mbed_official | 340:28d1f895c6fe | 300 | #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
| mbed_official | 630:825f75ca301e | 301 | #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
| mbed_official | 630:825f75ca301e | 302 | #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
| mbed_official | 340:28d1f895c6fe | 303 | #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ |
| mbed_official | 340:28d1f895c6fe | 304 | |
| mbed_official | 340:28d1f895c6fe | 305 | #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
| mbed_official | 630:825f75ca301e | 306 | #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
| mbed_official | 630:825f75ca301e | 307 | #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
| mbed_official | 340:28d1f895c6fe | 308 | #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ |
| mbed_official | 340:28d1f895c6fe | 309 | |
| mbed_official | 340:28d1f895c6fe | 310 | #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
| mbed_official | 630:825f75ca301e | 311 | #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
| mbed_official | 630:825f75ca301e | 312 | #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
| mbed_official | 340:28d1f895c6fe | 313 | #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ |
| mbed_official | 340:28d1f895c6fe | 314 | |
| mbed_official | 340:28d1f895c6fe | 315 | #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
| mbed_official | 630:825f75ca301e | 316 | #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
| mbed_official | 630:825f75ca301e | 317 | #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
| mbed_official | 340:28d1f895c6fe | 318 | #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ |
| mbed_official | 340:28d1f895c6fe | 319 | |
| mbed_official | 340:28d1f895c6fe | 320 | #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) |
| mbed_official | 630:825f75ca301e | 321 | #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
| mbed_official | 630:825f75ca301e | 322 | #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
| mbed_official | 340:28d1f895c6fe | 323 | #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ |
| mbed_official | 340:28d1f895c6fe | 324 | |
| mbed_official | 340:28d1f895c6fe | 325 | #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) |
| mbed_official | 630:825f75ca301e | 326 | #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
| mbed_official | 630:825f75ca301e | 327 | #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
| mbed_official | 340:28d1f895c6fe | 328 | #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */ |
| mbed_official | 340:28d1f895c6fe | 329 | |
| mbed_official | 340:28d1f895c6fe | 330 | #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) |
| mbed_official | 630:825f75ca301e | 331 | #define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) |
| mbed_official | 630:825f75ca301e | 332 | #define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) |
| mbed_official | 340:28d1f895c6fe | 333 | #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */ |
| mbed_official | 340:28d1f895c6fe | 334 | |
| mbed_official | 340:28d1f895c6fe | 335 | #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) |
| mbed_official | 630:825f75ca301e | 336 | #define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) |
| mbed_official | 630:825f75ca301e | 337 | #define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) |
| mbed_official | 340:28d1f895c6fe | 338 | #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */ |
| mbed_official | 340:28d1f895c6fe | 339 | |
| mbed_official | 340:28d1f895c6fe | 340 | #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) |
| mbed_official | 630:825f75ca301e | 341 | #define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) |
| mbed_official | 630:825f75ca301e | 342 | #define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) |
| mbed_official | 340:28d1f895c6fe | 343 | #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */ |
| mbed_official | 340:28d1f895c6fe | 344 | |
| mbed_official | 340:28d1f895c6fe | 345 | /** |
| mbed_official | 340:28d1f895c6fe | 346 | * @} |
| mbed_official | 340:28d1f895c6fe | 347 | */ |
| mbed_official | 340:28d1f895c6fe | 348 | |
| mbed_official | 340:28d1f895c6fe | 349 | /** @defgroup Memory_Mapping_Selection Memory Mapping Selection |
| mbed_official | 340:28d1f895c6fe | 350 | * @{ |
| mbed_official | 340:28d1f895c6fe | 351 | */ |
| mbed_official | 340:28d1f895c6fe | 352 | #if defined(SYSCFG_CFGR1_MEM_MODE) |
| mbed_official | 340:28d1f895c6fe | 353 | /** @brief Main Flash memory mapped at 0x00000000 |
| mbed_official | 340:28d1f895c6fe | 354 | */ |
| mbed_official | 630:825f75ca301e | 355 | #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) |
| mbed_official | 340:28d1f895c6fe | 356 | #endif /* SYSCFG_CFGR1_MEM_MODE */ |
| mbed_official | 340:28d1f895c6fe | 357 | |
| mbed_official | 340:28d1f895c6fe | 358 | #if defined(SYSCFG_CFGR1_MEM_MODE_0) |
| mbed_official | 340:28d1f895c6fe | 359 | /** @brief System Flash memory mapped at 0x00000000 |
| mbed_official | 340:28d1f895c6fe | 360 | */ |
| mbed_official | 630:825f75ca301e | 361 | #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ |
| mbed_official | 340:28d1f895c6fe | 362 | SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ |
| mbed_official | 340:28d1f895c6fe | 363 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 364 | #endif /* SYSCFG_CFGR1_MEM_MODE_0 */ |
| mbed_official | 340:28d1f895c6fe | 365 | |
| mbed_official | 340:28d1f895c6fe | 366 | #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) |
| mbed_official | 340:28d1f895c6fe | 367 | /** @brief Embedded SRAM mapped at 0x00000000 |
| mbed_official | 340:28d1f895c6fe | 368 | */ |
| mbed_official | 630:825f75ca301e | 369 | #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ |
| mbed_official | 340:28d1f895c6fe | 370 | SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ |
| mbed_official | 340:28d1f895c6fe | 371 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 372 | #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ |
| mbed_official | 340:28d1f895c6fe | 373 | /** |
| mbed_official | 340:28d1f895c6fe | 374 | * @} |
| mbed_official | 340:28d1f895c6fe | 375 | */ |
| mbed_official | 340:28d1f895c6fe | 376 | |
| mbed_official | 340:28d1f895c6fe | 377 | |
| mbed_official | 340:28d1f895c6fe | 378 | #if defined(SYSCFG_CFGR1_PA11_PA12_RMP) |
| mbed_official | 340:28d1f895c6fe | 379 | /** @defgroup HAL_Pin_remap HAL Pin remap |
| mbed_official | 340:28d1f895c6fe | 380 | * @brief Pin remapping enable/disable macros |
| mbed_official | 340:28d1f895c6fe | 381 | * @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_remapping |
| mbed_official | 340:28d1f895c6fe | 382 | * @{ |
| mbed_official | 340:28d1f895c6fe | 383 | */ |
| mbed_official | 340:28d1f895c6fe | 384 | #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ |
| mbed_official | 340:28d1f895c6fe | 385 | SYSCFG->CFGR1 |= (__PIN_REMAP__); \ |
| mbed_official | 340:28d1f895c6fe | 386 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 387 | #define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ |
| mbed_official | 340:28d1f895c6fe | 388 | SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \ |
| mbed_official | 340:28d1f895c6fe | 389 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 390 | /** |
| mbed_official | 340:28d1f895c6fe | 391 | * @} |
| mbed_official | 340:28d1f895c6fe | 392 | */ |
| mbed_official | 340:28d1f895c6fe | 393 | #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ |
| mbed_official | 340:28d1f895c6fe | 394 | |
| mbed_official | 630:825f75ca301e | 395 | /** @brief Fast-mode Plus driving capability enable/disable macros |
| mbed_official | 630:825f75ca301e | 396 | * @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. |
| mbed_official | 630:825f75ca301e | 397 | * That you can find above these macros. |
| mbed_official | 340:28d1f895c6fe | 398 | */ |
| mbed_official | 630:825f75ca301e | 399 | #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ |
| mbed_official | 630:825f75ca301e | 400 | SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ |
| mbed_official | 340:28d1f895c6fe | 401 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 402 | |
| mbed_official | 630:825f75ca301e | 403 | #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ |
| mbed_official | 630:825f75ca301e | 404 | CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ |
| mbed_official | 340:28d1f895c6fe | 405 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 406 | #if defined(SYSCFG_CFGR2_LOCKUP_LOCK) |
| mbed_official | 340:28d1f895c6fe | 407 | /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable |
| mbed_official | 340:28d1f895c6fe | 408 | * @{ |
| mbed_official | 340:28d1f895c6fe | 409 | */ |
| mbed_official | 340:28d1f895c6fe | 410 | /** @brief SYSCFG Break Lockup lock |
| mbed_official | 340:28d1f895c6fe | 411 | * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input |
| mbed_official | 340:28d1f895c6fe | 412 | * @note The selected configuration is locked and can be unlocked by system reset |
| mbed_official | 340:28d1f895c6fe | 413 | */ |
| mbed_official | 340:28d1f895c6fe | 414 | #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ |
| mbed_official | 340:28d1f895c6fe | 415 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ |
| mbed_official | 340:28d1f895c6fe | 416 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 417 | /** |
| mbed_official | 340:28d1f895c6fe | 418 | * @} |
| mbed_official | 340:28d1f895c6fe | 419 | */ |
| mbed_official | 340:28d1f895c6fe | 420 | #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ |
| mbed_official | 340:28d1f895c6fe | 421 | |
| mbed_official | 340:28d1f895c6fe | 422 | #if defined(SYSCFG_CFGR2_PVD_LOCK) |
| mbed_official | 340:28d1f895c6fe | 423 | /** @defgroup PVD_Lock_Enable PVD Lock |
| mbed_official | 340:28d1f895c6fe | 424 | * @{ |
| mbed_official | 340:28d1f895c6fe | 425 | */ |
| mbed_official | 340:28d1f895c6fe | 426 | /** @brief SYSCFG Break PVD lock |
| mbed_official | 340:28d1f895c6fe | 427 | * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register |
| mbed_official | 340:28d1f895c6fe | 428 | * @note The selected configuration is locked and can be unlocked by system reset |
| mbed_official | 340:28d1f895c6fe | 429 | */ |
| mbed_official | 340:28d1f895c6fe | 430 | #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ |
| mbed_official | 340:28d1f895c6fe | 431 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ |
| mbed_official | 340:28d1f895c6fe | 432 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 433 | /** |
| mbed_official | 340:28d1f895c6fe | 434 | * @} |
| mbed_official | 340:28d1f895c6fe | 435 | */ |
| mbed_official | 340:28d1f895c6fe | 436 | #endif /* SYSCFG_CFGR2_PVD_LOCK */ |
| mbed_official | 340:28d1f895c6fe | 437 | |
| mbed_official | 340:28d1f895c6fe | 438 | #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) |
| mbed_official | 340:28d1f895c6fe | 439 | /** @defgroup SRAM_Parity_Lock SRAM Parity Lock |
| mbed_official | 340:28d1f895c6fe | 440 | * @{ |
| mbed_official | 340:28d1f895c6fe | 441 | */ |
| mbed_official | 340:28d1f895c6fe | 442 | /** @brief SYSCFG Break SRAM PARITY lock |
| mbed_official | 340:28d1f895c6fe | 443 | * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 |
| mbed_official | 340:28d1f895c6fe | 444 | * @note The selected configuration is locked and can be unlocked by system reset |
| mbed_official | 340:28d1f895c6fe | 445 | */ |
| mbed_official | 340:28d1f895c6fe | 446 | #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ |
| mbed_official | 340:28d1f895c6fe | 447 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ |
| mbed_official | 340:28d1f895c6fe | 448 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 449 | /** |
| mbed_official | 340:28d1f895c6fe | 450 | * @} |
| mbed_official | 340:28d1f895c6fe | 451 | */ |
| mbed_official | 340:28d1f895c6fe | 452 | #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */ |
| mbed_official | 340:28d1f895c6fe | 453 | |
| mbed_official | 340:28d1f895c6fe | 454 | #if defined(SYSCFG_CFGR2_SRAM_PEF) |
| mbed_official | 340:28d1f895c6fe | 455 | /** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM |
| mbed_official | 340:28d1f895c6fe | 456 | * @brief Parity check on RAM disable macro |
| mbed_official | 340:28d1f895c6fe | 457 | * @note Disabling the parity check on RAM locks the configuration bit. |
| mbed_official | 340:28d1f895c6fe | 458 | * To re-enable the parity check on RAM perform a system reset. |
| mbed_official | 340:28d1f895c6fe | 459 | * @{ |
| mbed_official | 340:28d1f895c6fe | 460 | */ |
| mbed_official | 340:28d1f895c6fe | 461 | #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF) |
| mbed_official | 340:28d1f895c6fe | 462 | /** |
| mbed_official | 340:28d1f895c6fe | 463 | * @} |
| mbed_official | 340:28d1f895c6fe | 464 | */ |
| mbed_official | 340:28d1f895c6fe | 465 | #endif /* SYSCFG_CFGR2_SRAM_PEF */ |
| mbed_official | 340:28d1f895c6fe | 466 | |
| mbed_official | 340:28d1f895c6fe | 467 | |
| mbed_official | 340:28d1f895c6fe | 468 | #if defined(STM32F091xC) || defined (STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 469 | /** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check |
| mbed_official | 340:28d1f895c6fe | 470 | * @brief ISR wrapper check |
| mbed_official | 441:d2c15dda23c1 | 471 | * @note This feature is applicable on STM32F09x |
| mbed_official | 441:d2c15dda23c1 | 472 | * @note Allow to determine interrupt source per line. |
| mbed_official | 340:28d1f895c6fe | 473 | * @{ |
| mbed_official | 340:28d1f895c6fe | 474 | */ |
| mbed_official | 340:28d1f895c6fe | 475 | #define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18)] & ((__SOURCE__) & 0x00FFFFFF)) |
| mbed_official | 340:28d1f895c6fe | 476 | /** |
| mbed_official | 340:28d1f895c6fe | 477 | * @} |
| mbed_official | 340:28d1f895c6fe | 478 | */ |
| mbed_official | 340:28d1f895c6fe | 479 | #endif /* (STM32F091xC) || defined (STM32F098xx)*/ |
| mbed_official | 340:28d1f895c6fe | 480 | |
| mbed_official | 340:28d1f895c6fe | 481 | #if defined(STM32F091xC) || defined (STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 482 | /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection |
| mbed_official | 340:28d1f895c6fe | 483 | * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register |
| mbed_official | 441:d2c15dda23c1 | 484 | * @note This feature is applicable on STM32F09x |
| mbed_official | 340:28d1f895c6fe | 485 | * @param __SOURCE__: This parameter can be a value of @ref HAL_IRDA_ENV_SEL |
| mbed_official | 340:28d1f895c6fe | 486 | * @{ |
| mbed_official | 340:28d1f895c6fe | 487 | */ |
| mbed_official | 340:28d1f895c6fe | 488 | #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \ |
| mbed_official | 340:28d1f895c6fe | 489 | SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \ |
| mbed_official | 340:28d1f895c6fe | 490 | SYSCFG->CFGR1 |= (__SOURCE__); \ |
| mbed_official | 340:28d1f895c6fe | 491 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 492 | |
| mbed_official | 340:28d1f895c6fe | 493 | #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0) |
| mbed_official | 340:28d1f895c6fe | 494 | /** |
| mbed_official | 340:28d1f895c6fe | 495 | * @} |
| mbed_official | 340:28d1f895c6fe | 496 | */ |
| mbed_official | 340:28d1f895c6fe | 497 | #endif /* (STM32F091xC) || defined (STM32F098xx)*/ |
| mbed_official | 340:28d1f895c6fe | 498 | |
| mbed_official | 340:28d1f895c6fe | 499 | /** |
| mbed_official | 340:28d1f895c6fe | 500 | * @} |
| mbed_official | 630:825f75ca301e | 501 | */ |
| mbed_official | 630:825f75ca301e | 502 | |
| mbed_official | 340:28d1f895c6fe | 503 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 630:825f75ca301e | 504 | |
| mbed_official | 630:825f75ca301e | 505 | /** @addtogroup HAL_Exported_Functions |
| mbed_official | 340:28d1f895c6fe | 506 | * @{ |
| mbed_official | 340:28d1f895c6fe | 507 | */ |
| mbed_official | 340:28d1f895c6fe | 508 | |
| mbed_official | 630:825f75ca301e | 509 | /** @addtogroup HAL_Exported_Functions_Group1 |
| mbed_official | 340:28d1f895c6fe | 510 | * @{ |
| mbed_official | 340:28d1f895c6fe | 511 | */ |
| mbed_official | 340:28d1f895c6fe | 512 | /* Initialization and de-initialization functions ******************************/ |
| mbed_official | 340:28d1f895c6fe | 513 | HAL_StatusTypeDef HAL_Init(void); |
| mbed_official | 340:28d1f895c6fe | 514 | HAL_StatusTypeDef HAL_DeInit(void); |
| mbed_official | 340:28d1f895c6fe | 515 | void HAL_MspInit(void); |
| mbed_official | 340:28d1f895c6fe | 516 | void HAL_MspDeInit(void); |
| mbed_official | 340:28d1f895c6fe | 517 | HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
| mbed_official | 340:28d1f895c6fe | 518 | /** |
| mbed_official | 340:28d1f895c6fe | 519 | * @} |
| mbed_official | 340:28d1f895c6fe | 520 | */ |
| mbed_official | 340:28d1f895c6fe | 521 | |
| mbed_official | 630:825f75ca301e | 522 | /** @addtogroup HAL_Exported_Functions_Group2 |
| mbed_official | 340:28d1f895c6fe | 523 | * @{ |
| mbed_official | 340:28d1f895c6fe | 524 | */ |
| mbed_official | 630:825f75ca301e | 525 | |
| mbed_official | 630:825f75ca301e | 526 | /* Peripheral Control functions ************************************************/ |
| mbed_official | 340:28d1f895c6fe | 527 | void HAL_IncTick(void); |
| mbed_official | 340:28d1f895c6fe | 528 | void HAL_Delay(__IO uint32_t Delay); |
| mbed_official | 340:28d1f895c6fe | 529 | uint32_t HAL_GetTick(void); |
| mbed_official | 340:28d1f895c6fe | 530 | void HAL_SuspendTick(void); |
| mbed_official | 340:28d1f895c6fe | 531 | void HAL_ResumeTick(void); |
| mbed_official | 340:28d1f895c6fe | 532 | uint32_t HAL_GetHalVersion(void); |
| mbed_official | 340:28d1f895c6fe | 533 | uint32_t HAL_GetREVID(void); |
| mbed_official | 340:28d1f895c6fe | 534 | uint32_t HAL_GetDEVID(void); |
| mbed_official | 630:825f75ca301e | 535 | void HAL_DBGMCU_EnableDBGStopMode(void); |
| mbed_official | 630:825f75ca301e | 536 | void HAL_DBGMCU_DisableDBGStopMode(void); |
| mbed_official | 630:825f75ca301e | 537 | void HAL_DBGMCU_EnableDBGStandbyMode(void); |
| mbed_official | 630:825f75ca301e | 538 | void HAL_DBGMCU_DisableDBGStandbyMode(void); |
| mbed_official | 340:28d1f895c6fe | 539 | /** |
| mbed_official | 340:28d1f895c6fe | 540 | * @} |
| mbed_official | 340:28d1f895c6fe | 541 | */ |
| mbed_official | 340:28d1f895c6fe | 542 | |
| mbed_official | 340:28d1f895c6fe | 543 | /** |
| mbed_official | 340:28d1f895c6fe | 544 | * @} |
| mbed_official | 630:825f75ca301e | 545 | */ |
| mbed_official | 630:825f75ca301e | 546 | |
| mbed_official | 630:825f75ca301e | 547 | /** |
| mbed_official | 630:825f75ca301e | 548 | * @} |
| mbed_official | 340:28d1f895c6fe | 549 | */ |
| mbed_official | 340:28d1f895c6fe | 550 | |
| mbed_official | 340:28d1f895c6fe | 551 | /** |
| mbed_official | 340:28d1f895c6fe | 552 | * @} |
| mbed_official | 630:825f75ca301e | 553 | */ |
| mbed_official | 340:28d1f895c6fe | 554 | |
| mbed_official | 340:28d1f895c6fe | 555 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 556 | } |
| mbed_official | 340:28d1f895c6fe | 557 | #endif |
| mbed_official | 340:28d1f895c6fe | 558 | |
| mbed_official | 340:28d1f895c6fe | 559 | #endif /* __STM32F0xx_HAL_H */ |
| mbed_official | 340:28d1f895c6fe | 560 | |
| mbed_official | 340:28d1f895c6fe | 561 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |